HP Elitebook folio 9470m 6050A2514101
8 7 6 5 4 3 2 1 THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC CORPORATION AND SHALL NOT BE
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THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT WRITTEN PERMISSION,INVENTEC CORPORATION, 2012 ALL RIGHT RESERVED.
HSF Property:ROHS or Halogen-Free
F
F
E
E
BANDIT M2 HD+
D
D
MV BUILD 2013.01.04 C
C
B
B
A
A EE
2012/09/10
2012-ECO-017507
DATE
8
DATE 21-OCT-2002
DESIGN
XXX
21-OCT-2002
CHECK
XXX
21-OCT-2002
RESPONSIBLE
XXX
21-OCT-2002
POWER IRAY CHEN IRAY CHEN IRAY CHEN IRAY CHEN
A3
A
7
XXX
SIZE= FILE NAME:BANDIT-MB-1310A2514101 P/N 6050A2514101
REV
CHANGE NO.
DRAWER
6
5
4
3
INVENTEC
DATE 21-OCT-2002 21-OCT-2002 21-OCT-2002
TITLE
A02
MODEL,PROJECT,FUNCTION
ULTRABOOK MAIN BOARD
21-OCT-2002
VER:
SIZE A3
CODE CS
DOC.NUMBER
2
REV
1310xxxxx-0-0
SHEET
1
1
X01 of
80
8
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1
TABLE OF CONTENTS
D
C
B
A
D
1. PROJECT NAME 2. TABLE OF CONTENTS 3. BLOCK DIAGRAM
23. IVY BRIDGE_1 (CLK,MISC,JTAG)
47. KEYBOARD
24. IVY BRIDGE_2 (POWER)
48. TPM
25. IVY BRIDGE_3 (DMI,DP,PEG,FDI)
49. LAN INTERFACE
4. SYSTEM POWER FLOW
26. IVY BRIDGE_4 (DDR3)
50. LAN RJ45 CNTR
5. SYSTEM POWER(CHARGER) 6. SYSTEM POWER(BATT SELECTOR) 7. SYSTEM POWER(OCP) 8. SYSTEM POWER(P3V3A&P5V0A) 8. SYSTEM POWER(P5V0A _CHG 10. SYSTEM POWER(P1V5) 11. SYSTEM POWER(P1V05M)
27. IVY BRIDGE_5 (GRAPHICS POWER)
51. WLAN
28. IVY BRIDGE_6 (GND,RESERVED)
52. WWAN & SIM CARD
29. DDR3_SO-DIMM0
53. DOCKING CNTR
30. DDR3_SO-DIMM1
54. STICK POINT & B2B CNTR
31. PANTER POINT_1 (HDA,JTAG,SPI,SATA)
55. CODEC
32. PANTER POINT_2 (PCI-E,SMBUS,CLK)
56. EXT MIC AMP
33. PANTER POINT_3 (DMI,FDI,GPIO)
57. JACK & USB3 CNTR
12. SYSTEM POWER(P1V05S)
34. PANTER POINT_4 (LVDS,DDI)
58. CARD READER
13. SYSTEM POWER(P1V8S)
35. PANTER POINT_5 (PCI,USB,NVRAM)
59. BUTTON LED
14. SYSTEM POWER(PVSA)
36. PANTER POINT_6 (GPIO,VSS_NCFT,RSVD)
60. SMART VARD & LED DB
15. SYSTEM POWER(PVCORE1)
37. PANTER POINT_7 (POWER)
61. MIC DB
16. SYSTEM POWER(PVCORE2)
38. PANTER POINT_8 (POWER)
62. SCREW
17. POWER TEST POINT
39. PANTER POINT_9 (GND)
63. EMI & RF SOLUTION 64. SYSTEM SEQUENCE
18. POWER PAD
40. CRT / DISPLAY PORT CNTR
19. POWER(SLEEP)
41. LCM & WEBCAM
20. POWER(SEQUENCE)
42. SATA & MSATA CNTR
21. XDP CONN
43. USB CNTR & USB CHARGER
22. FAN & THERMAL
44. FINGER PRINTER CNTR
C
B
A
45. ACCELEMETOR 46. KBC / SPI
INVENTEC TITLE
MODEL,PROJECT,FUNCTION TABLE
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DATE
21-OCT-2002
2
CODE CS
OF CONTENTS
DOC.NUMBER
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1
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PRIMARY LI-LON BATTERY
SECOND LI-LON BATTERY
R.G.B
CRT
THERMAL SENSOR SMSC_EMC1412
LED PANEL
1666MT/S
IVY BRIDGE
D
D
ULV BGA1023 31MM X 24MM
LVDS
DDR3_SODIMM
DDR3_SODIMM
1666MT/S
SATA0 HDD(GEN3)
ACCELEROMETER ST_HP3DC2TR DISPLAY PORT
SATA
FDI/DMI
SATA2 MSATA
DDP C
DISPLAY PORT X 2 (DOCKING)
PCH
C
AUDIO CODEC IDT 92HD91WC
HDA USB3.0
PANTHER POINT QM77 USB2.0 LPC
PCIE4 WLAN
B
RJ45
USB5 - BLUETOOTH
USB0 - DOCKING
USB1 - DOCKING B
PCIE6 GBE PHY
KBC SMSC 1126
INTEL 82579LM
KEYBOARD
25MM X 25MM
PCIE
PCIE3 MEDIA CARD CONTROLLER
TOUCH PAD
USB1 - CHARGER
TPM1.2 SLB9635
SPI 16MB
USB7 - SMART CARD
USB2 - LEFT
USB2 - RIGHT 1
USB8 - FINGER
USB3 - RIGHT 1
USB3 - RIGHT2
USB10 - CAMERA
USB4 - RIGHT 2
POINT STICK USB12- WWAN
A
A
DOCKING CONNECTOR USB3.0 PORT X 4
RJ-45
LINE IN/LINE OUT
DP1.2
INVENTEC
VGA
TITLE
MODEL,PROJECT,FUNCTION BLOCK
SIZE A3
CHANGE by
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7
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XXX
3
DATE
21-OCT-2002
2
DIAGRAM
DOC.NUMBER
REV
CODE 1310xxxxx-0-0
X01
CS
SHEET
3
80
of
1
8
7
6
5
4
3
2
1
SLP_S3#_3R
P1V8S
RICHTEK 8086AZQW
P5V0A_CHG SLP_S3#_3R ADP_PRES
ADP_EN
LIMIT_SIGNAL
OCP
KBC_PW_ON
OCP_OC#
TPS51463
P3V3ALW
(TPS51123)
P5V0AL
SLP_S3#_3R
D
PVSA
5/3.3V
P5V0S
SLP_S3#_3R
P3V3AL
EN0
AO6402AL
D
ICS PM_SLP_A_#
ADAPTER (65W)
CHARGER BQ24736
P1V05M
RICHTEK 8086AZQW
CHARGER_DAT SPWON CHARGER_CLK
P3V3S
AO6402AL EN_P3V3A
C
FDC638APZ
P3V3A
FDC638APZ
P3V3M
FDC638APZ
PVSIM
C
SLP_LAN#
MAIN BATTERY
2ND BATTERY
WWWAM_OFF
DDR3 / 1.5V DDR3L/1.35V TPS51216
PVBAT
SLP_S4#_3R
P1V5
P1V5S
KBC_GPIO22
B
SPWON
SLP_S4#_KBC
B
FDMS7692
VCCP VCCP_PG P1V8S SLP_S3#_3R
TPS51219
GMT G966A
P1V5S_LDO
EN_VCCP
A
A
PVAXG
IMVP VI EN_CPU
ISL95833
PVCORE
INVENTEC
VGATE
TITLE
MODEL,PROJECT,FUNCTION BLOCK DIAGRAM POWER
SIZE A3
CHANGE by
8
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XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
4
80
of
1
X01
8
7
IN
4
NFE31PT222Z1E9L
Q6010
2
1
SEM_SM24_SOT23_3P
2
1
3
3
1 2
1
1000PF_50V_2 D6015
C6015
C6016
2
100PF_50V_2
3
4 1 C6017 2
D
Q6009
1 3
G
4
G
G1 G2
5 6
ACES_50224_0060N_001_6P
D OUT
755
LIMIT_SIGNAL
PVPACK
FAIR_FDMC4435BZ_8P
4 3 2 1
2
1
S
D
8 7 6 5
1 3
1
2
2
IN
IN
1 2
1
10UF_25V_5
C6001
4 3 2 1
ETQP3W4R7WFN
B 2 4
1
1
R6020
B0530W_7
D6049
A
2
1
2
C6047
2
INVENTEC TITLE
MODEL,PROJECT,FUNCTION Block
SIZE A3
CHANGE by
7
2
1 2
2
0_5%_2
R6049 0_5%_2
8
10UF_25V_5
0.1UF_25V_2
C6021 2
1 2
0.1UF_25V_2
C6024
CSC0402_DY
C6011
1
2
0.1UF_16V_2
10UF_25V_5
C6023
2
1
C6010
RSC_0603_DY
1 1
2
R7600
0.02_1%_6
2
4 3 2 1 R6025
R6001
1
2
C7600
2
C6000 2
R6027 2 V_3.9K
BAT54WS
1 3
2
0.01UF_50V_2
IN
1
0_5%_2
1
7
ICS
CHR_ILIM
2
1
OUT 48 BI CHARGER_DAT 48 BI CHARGER_CLK 7
C6025
1 1 C6048
2
0.01UF_50V_2
1 2
C6049
100PF_50V_2
100PF_50V_2
C6022 1 2
20K_1%_2
1 2
7
A
1
0.047UF_16V_2
D6016
1UF_10V_2
22K_5%_2
2
3 D S
R6023
SSM3K7002FU
2
10K_1%_2
G
1
2
R6024
127K_1%
1 R6021
1
18.2K_1%_2
R6029 2 1 R6030
1
ACDET>0.6V:SMBUS OK ACDET>2.4V& HI DDR-> 1.35V MEM_1V5-> LOW DDR-> 1.5V
D
P5V0A_CHG
D
D
Q6202 1
V5IN
VBST
15
R6205
1
DRVH
14 VRP1V5_HG
SW
13 VRP1V5_PH
2
2.2_5%_3
1
C6204
2
D1
1
G1
PHASE
S2
7
Q1
G2
8
TML
9
1
10UF_25V_5
2
C6211
6
2
D1
0.1UF_16V_2
5
S2
Q2
3
OCP=12AMP
OUT
1 2
REFIN
VDDQSNS
9
VLDOIN
2
VTT
3
VTTSNS
1
GND
1 +
R7620
20
1
1
2
2
C
POWERPAD_2_0610
P0V75M_VREF
19
MODE
VTTGND
4
18
TRIP
VTTREF
5
30.1K_1%_2
2
R6202
1
7
100K_5%_2 R6203
1
0.1UF_16V_2
C6209 2
0.01UF_50V_2
1 2
C6212
1 R6207 2
B
52.3K_1%_2
8
10
PGOOD
4
PAN_ETQP3W1R0WFN_4P
C6200
10K_1%_2
11 VRP1V5_LG
PGND
3
2 4
2
VREF
1 2
6
2
2
1
TML
21
TI_TPS51216RUKR_QFN_20P
1
R6206
C7620
DRVL
2
1
B
0.22UF_6.3V_2
2
0_5%_2
DDR3L_SEL IN
CSC0402_DY
RSC_0402_DY
1 3
RSC_0603_DY
1 S5
C6208
1 R6210
16
2
IN
R6204
2
1
EN_1V5
1
C6207
18
IN
S3
2
35 21 45 18 SLP_S4#_3R
17
IN
10UF_6.3V_3
EN_0V75
P1V5
VRP1V5
PAD6200
L6200
C
18
330UF_2V_9MR_PANA_-35%
12
S2
D1
10UF_25V_5
1 U6200
FAIR_FDMS3668S_8P
C6210
Q6200
4
P0V75S
2
2
C6205
1
2
1
200K_5%_2
R6211
2
PVBAT
SSM3K7002FU
2.2UF_6.3V_3
MEM_1V5 IN
G
S
48
VOUT=REFIN=1.8*(52.3K/(10K+52.3K)) MODE=100KOHM:TRACKING DISCHARGE
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION Block
SIZE A3
CHANGE by
8
7
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XXX
3
DATE
21-OCT-2002
2
CODE CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
10
80
of
1
X01
8
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2
1
D
D
13 VRP1V8_1V05IN
IN OCP=4.5AMP
1
OUT VRP1V05_LAN_M
P1V05M
C
VOUT=((7.68K/10K)+1)*0.6
2
2
2
B
1 C6400 2
22UF_6.3V_5
1
2
RICHTEK_RT8068AZQW_WDFN_10P
1
FB
1
POWERPAD_2_0610
CSC0402_DY
NC
1
LX
C6403
SVIN
PAD6400
1 1 2 VRP1V05_LAN_M_PH 2 3 LX PAN_ELL5PR2R2N 4 PGOOD 5 EN 18 IN EN_P1V05 LX
2
PVIN
L6400
1
PVIN
U6400
10K_1%_2 7.68K_1%_2
TML
R6400
11 10 9 8 7 6
R6401
C6410 2
1 R6402 2 1 C6401 2
10_5%_2
IN
0.1UF_16V_2
VRP1V8_1V05IN
10UF_6.3V_3
C
B
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION Block
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
11
80
of
1
X01
8
7
6
5
4
3
2
1
D
D
MODE=100KHZ:300KHZ
IN
G1
3
GSNS
DL
10 VRP1V05S_VCCP_LG
4
VSNS
V5
9
S2
7
G2
Q1
8
TML
9
C6310
L6300 1
2
3
4
2 4
CYN_PCMB063T_R68MS_4P
2
12
1 3
2
C6305 2
8
R7630
1
P5V0A
1 2
PHASE
1
D1
1
+
2
11 VRP1V05S_VCCP_HG
OUT
C6300
12 VRP1V05S_VCCP_PH
DH
5
6
C OCP=15AMP VRP1V05S_VCCP
P1V05S_VCCP
PAD6300
330UF_2V_9MR_PANA_-35%
BST
EN
MODE
PGOOD
PWPD
SW
R6301
1 2
0.01UF_50V_2
1
D1
REFIN
1 2 C6307
5
S2
Q2
3
VREF
0.01UF_50V_2
S2
D1
2
TI_TPS51219RTER_QFN_16P
11.3K_1%_2 C6320
2
R6308
B
FAIR_FDMS3668S_8P
C7630
IN
4
1
GND
0_5%_2_DY
Q6300
0.1UF_16V_2
PGND
26 VTT_SENSE
2
41.2K_1%_27
IN
R6306
TRIP
26 VSS_SENSE_VTT
1
16
IN
COMP
1 R6305
VCCIO_SEL
2
0_5%_2
1 C6308 2
2.2UF_6.3V_3
26
2
2
2.2_5%_3
U6300
C6304
1
CSC0805_DY
2
RSC_0603_DY
R6302
C6311
13
15
14
16
17
1
2
OUT
CSC0402_DY
VCCP_PG
2.2UF_6.3V_3
20
1
C
1
PVBAT
10UF_25V_5
2
R6304
1
EN_VCCP
100K_1%_2
18
1
1
2
2
POWERPAD_2_0610
B
VOUT=2*11.3/(10+11.3)=1.06V
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION Block
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
12
80
of
1
X01
8
7
6
5
4
3
2
1
D
D
P5V0A_CHG PAD6971 1
1
2
2
13 OUT VRP1V8_1V05IN
POWERPAD_2_0610
VRP1V8S
P1V8S
C VOUT=((20.5K/10K)+1)*0.6 U6970
1
2
RICHTEK_RT8068AZQW_WDFN_10P
2
B
1
OUT P1V8S_PG IN EN_1V8 18
1
2
2
POWERPAD_2_0610
20
22UF_6.3V_5
EN
1
C6970
PGOOD
FB
PAD6970 2
2
NC
L6970
PAN_ELL5PR2R2N
1
LX
VRP1V8S_PH 1
C6974
SVIN
1 2 3 4 5
2
LX
CSC0402_DY
LX
PVIN
1
PVIN
10K_1%_2 20.5K_1%_2
TML
R6973
11 10 9 8 7 6
R6972
1 2
C6975 2
C6972
1
2
R6970
1
IN 10_5%_2
VRP1V8_1V05IN
0.1UF_16V_2
C
10UF_6.3V_3
OCP=4.5AMP
OUT
B
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION Block
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
13
80
of
1
X01
8
7
6
5
4
3
2
1
D
1
1 2
2
RSC_0402_DY
OUT
VRPVSA
PVSA PAD6500
SW
PGND
BST
2 4
1
2 4
1
2
2
POWERPAD_2_0610
CYN_PCMB063T_R33MS_4P
1
C6506
CHOKE_4PIN_2PIN
2
C6500
C6501
C6502
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
18 17 16 15 14 13
2
0.1UF_16V_2
1
SW
PGND
1 3
2
SW
1 3
VRPVSA_PH
7 8 9 10 11 12
C
OCP=7AMP
1
U6500
PGND
EN_PVCCSA
1
B 1
2
C6508
VCCSA_SENSE 27
2
VIN
1UF_6.3V_2
1
IN
1
SW
1UF_6.3V_2
C6509
2
0_5%_2
L6500 SW
VIN
IN
2
R6502
TI_TPS51463RGER_QFN_24P
VIN
P5V0A
B
RSC_0402_DY
1
R6506
R6501
TML
V5DRV V5FILT PGOOD VID1 VID0 EN
1 C6511 2
25 24 23 22 21 20 19
22UF_6.3V_5
1 C6510 2
0.1UF_16V_2
P5V0A_CHG
R6502 SHORT FOR REMOTE SENSE R6506 SHORT FOR LOCAL SENSE
1
GND VREF COMP SLEW VOUT MODE
C
C6505 0.01UF_50V_2
2
1 C6550 2 1
1 2 3 4 5 6
2
R6500
1 C6504 2
0.22UF_6.3V_2
5.1K_1%_2 3300PF_50V_2
D
C6503
2
CSC0402_DY
IN IN OUT
VCCSA_VID0 27 VCCSA_VID1 27 VCCSA_PG 20
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION Block
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
14
80
of
1
X01
7
6
5
4
3
1
C6742
2
GFX_VCC_SENSE
C6741
1 R6737
1
2
1
0.01UF_50V_2
2
1
1
R6740 2K_1%_2
R6738
1
2
2
1
2
R6739 267K_1%_2
2.61K_1%_2 2
1
1
R6741 499_1%_2
2
VRPVAXG_HG1 16
P1V05S_VCCP
4
ALERT#
OUT
5
SDA
CPU_PROCHOT#
OUT
VRPVAXG_LG1
VDD
21
PWM2
20
VRPVCORE_PH1
8
ISEN2
UGATE1
17
OUT
VRPVCORE_HG1
R6633 470K_5%_NTC
2
2
26 OUT VR_SVID_DATA
130_1%_2
1
R6696
2
C
26 OUT VR_SVID_CLK
54.9_1%_2
BOOT1
VRPVCORE_LG1
OUT
PGOOD
OUT
18
COMP
19
PHASE1
FB
LGATE1
NTC
RTN
VR_HOT#
2
R6625
1 1
UGATEG
BOOTG
PGOODG
COMPG
FBG
RTNG
OUT
22
6
PAD
1
P5V0A
R6631 3.83K_1%_2
23
VCCP
7
ISUMN
R6632 27.4K_1%_2
23
2
LGATEG
SHORT_0402_5
OUT
26 VR_SVID_DATA
VRPVAXG_PH1
R6697
C6625 1UF_6.3V_2
VR_SVID_ALERT#
OUT
1
VR_ON SCLK
24
2
2 3
PHASEG
1
1
R6626
2
OUT
VRPVAXG_BOOT1
P5V0A
2
IN OUT
EN_CPU
1
NTCG
26 VR_SVID_CLK
2
2
ISUMPG
1
ISUMNG
2
R6731 3.83K_1%_2
R6733 470K_5%_NTC
1
2
154K_1%_2
47PF_50V_2
25
AXG_PG 20 28
27
29
30
31
32 1
1
ISUMP
2
R6732 27.4K_1%_2
C6738 150PF_50V_2
D
OUT
1
0.01UF_50V_2
C6735 2
1
0.1UF_16V_2
C6734
2
1
11K_1%_2
R6736
1
C6740 470PF_50V_2
ISEN1
1
1
1
C6737 2
619_1%_2
U6600
C
2
C6739 330PF_50V_2
R6742 2
CSC0402_DY
1
GFX_VSS_SENSE 27
2
CSC0402_DY
OUT
IN
2
26
16 VSUMPG
1
IN
C6743
RSC_0402_DY
2
1 1
2 2
D
R6743
R6734 2.61K_1%_2
C6733 2
IN 1
16 VSUMNG
R6735 0.1UF_16V_2 10K_5%_NTC
IN
2
C6626 SHORT_0402_5 1UF_6.3V_2
8
INTERSIL_ISL95833HRTZ_T_TQFN_32P
B 16
15
14
13
12
11
9
10
33
B OUT
VRPVCORE_BOOT1
OUT
CORE_PG
18
C6640 2
1
1
470PF_50V_2
2
C6633
1
2
2
7
1
R6639 267K_1%_2
2200PF_50V_2
2
C6635
1
0.1UF_16V_2
1 C6634
2
11K_1%_2
1 R6636
2
1
2
42.2K_1%_2
1
2
C6638 150PF_50V_2
2
649_1%_2
VCCSENSE
IN
VSSSENSE 26
2
A
2
CSC0402_DY
R6637
C6642
2
1
649_1%_2 R6643
IN
1
330PF_50V_2
C6641 1
1
1
1
R6640 2K_1%_2
1
C6643
INVENTEC
2
0.01UF_50V_2
TITLE
MODEL,PROJECT,FUNCTION
2
Block
2200PF_50V_2
SIZE A3
CHANGE by
8
R6638
2
C6639
2
R6634 2.61K_1%_2 R6635 10K_5%_NTC
IN
C6637
33PF_50V_2
1.96K_1%_2
0.1UF_16V_2
2
1
2
A
16 VSUMN
R6642
1
IN 1
16 VSUMP
1
2
R6641 499_1%_2
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
15
80
of
1
X01
8
7
6
5
4
3
2
1
1
1
PVBAT
PAD6610
1 C6611 2
10UF_25V_5
1
0.1UF_25V_3
2
C6610
D
Q6610
S
65 16
D
1
VRPVAXG_BOOT1 IN
2
R6721 C6721 2.2_5%_3 0.22UF_25V_3 2 1 2
1 +
S
R6612 1_5%_2
1
G
PVAXG
C
ETQP4LR36AFM
1
D
Q6711
S
G
FDMS0306AS
1 2 3 4 2
2 4
C6700
+
IN
L6710
470UF_2V VSUMPG
OUT
15 VSUMNG
OUT
R6711
1
2
2
IN
VRPVAXG_LG1
1
VRPVAXG_PH1
8 7 6 5
C
1 3
3
IN
21
VRPVAXG_HG1
C7671 R7671 0.0015UF_50V_2 4.7_5%_3
OUT
1
15UF_25V
2
4 3 2 1
3.65K_1%_2
15 VSUMN
IN
3
VBATR_GPU
C6710
470UF_2V
D
2
2
Q6710
OUT
1
NMOS_4D3S
CSC0402_DY
15 VSUMP
FDMS7692
S
G
C7661
3 2
470UF_2V R6611
2
+
C6601 +
C6600
POWERPAD_2_0610
1
1
RSC_0603_DY
2
1
PAD6710
R7661
21
D
Q6611
IN
2 4
ETQP4LR36AFM
FDMS0300S
VRPVCORE_LG1
1 3
L6610
5 2 6 7 8
4 3 2 1 5 6 7 8
VRPVCORE_PH1
IN IN
VBATR_CPU IN
1
PVCORE VRPVCORE_HG1
4 3 2 1
G
D
R6621 C6621 2.2_5%_3 0.22UF_25V_3 1 2 1 2
NMOS_4D3S
IN
IN FDMS7692
VRPVCORE_BOOT1
5 2 6 7 8
65 16 VBATR_CPU
2
POWERPAD_2_0610
3.65K_1%_2 1
2 R6712 1_5%_2
B
B
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION Block
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
16
80
of
1
X01
8
7
6
5
4
3
2
1
D
D
PVBAT_IN
IN
C
PVPACK 65 PVADPTR_IN
IN
1
TP6001
1
TP30
1
TP6039
1
1
TP30
TP6002
1
TP30
1
TP6008 TP6009
1
TP30
TP6010
1
TP6015
1
TP30
TP6016
TP6021
TP6025
1
P1V05M
1
TP30
TP30
P3V3AL
C
PVAXG
TP6028
1
TP6032 TP30
P1V05S_VCCP
PVCORE
TP30
TP30
1
TP6020
P5V0AL
TP30
TP30
1
TP30
TP6003
TP6014
PVBATB
1
TP30
TP6022
TP6026
1
TP6029
1
TP40
TP30
1
TP6033 TP30
TP30
TP30
1
TP6040
P5V0A_CHG P5V0A PVADPTR
PVBAT
1
TP6041
1
TP30
TP6004
1
TP30
1
IN
VADPBL
B
TP6007 TP30
1
1
TP30
TP6005
1
TP30
1
TP6011 TP6012
1
TP30
TP6013 TP30
TP6017
1
TP6023
TP7351
1
P0V75S
TP30
TP6030
1
TP30
1
TP30
TP6037 TP30
TP30
1
TP30
TP6006
P1V8S
PVBATA
TP30
TP6018
P3V3ALW
P1V5
PVSA
P0V75M_VREF
TP30
1
TP6019
1
TP6024 TP30
TP30
1
TP6027 TP30
1
TP6031 TP30
1
TP6038
B
TP30
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION Block
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
17
80
of
1
X01
6
1
1
2
5
1
7
2
2
D7680 1SS355VMTE_17
2
1
R7680 1K_5%_2
10 21
SLP_S4#_3R
IN
2
OUT
EN_0V75
10
R7687 18
1
3
R7690 1
A1
D7681
1
IN
KBC_GPIO22
1
P3V3S
2
C
48 23
2
R7681 20K_5%_2
R7682
2
15
CORE_PG
1
IN
2
D
1K_5%_2
OUT
SLP_S4#_KBC
OUT
EN_1V5
55 48
SHORT_0402_5
20K_1%_2
35 45
1
IN
BAT54C
D
SLP_S3#_3R
20 19 18 9 55 48 45 42
3
2
21 57
A2
35 27
4
C7680 0.1UF_16V_2
8
10 35 33
VGATE
R7688
1
IN
2
OUT
CORE_PG
15
18
SHORT_0402_5
20
48
23
PWR_GOOD_3
R7689
1
IN
2
OUT
EN_CPU
15
SHORT_0402_5
2
1 2
SLP_S3#_3R
1
IN
R7684
2
1 2
C7684
B
EN_P1V05
C
11
8
OUT
SHORT_0402_5
57 55 48 45 42 35 27 21 20 19 18 9
OUT
EN_VCCP
5V_PG
R6125
1
IN
2
35 RSMRST# 33 48
OUT
SHORT_0402_5
12
P3V3ALW P3V3AL C7200
P3V3A PAD7200
1
1
0.1UF_16V_2
IN
R7685
4
S
3
G
D
2
OUT
0_5%_2
1 2
C7685
SLP_S3#_3R
IN
1
R7686
TPC6111
13
2
TP30
C7201 10UF_6.3V_3
OUT
EN_PVCCSA
14
A
SHORT_0402_5
1
57 55 48 45 42 35 27 21 20 19 18 9
2
C7686
A
EN_1V8
1
2
1
1 2 5 6
PMOS_4D1S
CSC0402_DY
IN
1 R7200 2 100K_5%_2
TP7201
CSC0402_DY
SLP_S3#_3R 57 55 48 45 42 35 27 21 20 19 18 9
B
Q7200
2 EN_P3V3A
2
2
POWERPAD1X1M_DY
1
R7683
SHORT_0402_5
1
1
IN
0.1UF_16V_2_DY
PM_SLP_A#
C7683
21 19 20 48 35
CSC0402_DY
C
INVENTEC TITLE
MODEL,PROJECT,FUNCTION POWER SEQUENCE
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
DOC.NUMBER
REV
CODE 1310xxxxx-0-0
X01
CS
SHEET
18
80
of
1
8
7
6
5
4
3
2
REFERENCE NUMER : 7000~7350
1
Q2971 WHETHER CAN CHANGE TO 6015B0017101 PMV65XP OR NOT P0V75S
3
NMOS_4D1S
D
1 2 3 4
S
G
1
NMOS_4D3S
FDMS7692
AO6402AL
1
1
TP6036 TP30
Q7152 1
3
Q2971 S
D
G
1 2 5 6
TP2971
1
TP30
PMOS_4D1S
TPC6111
P3V3M
G
P3V3ALW S
SSM3K7002FU_DY
2
SSM3K7002FU
2
S
G
10UF_6.3V_3
D
C2970 2
1
CSC0402_DY
Q2972 1
G
S
3
R7150 2 1 220_5%_5 C7151 2 1
1 C7150 2
2 100_5%_5 C7100 2 1
10UF_6.3V_3
1 C7103 2
1
SPWON IN
CSC0402_DY
19
IN
0.1UF_16V_2
10UF_6.3V_3 C7060 2 1
1 C7102 2
SPWON
CSC0402_DY R7100 1
19
CSC0402_DY
SPWON IN
2 R7050 1 47_5%_2 C7050 2 1
19
4
Q7153 D
AO6402AL
MAX 7.5A
Q7151 8 7 6 5
TP6035 TP30
10UF_6.3V_3
G
1
3 2 R2972 1 47_5%_2 C2971 2 1
NMOS_4D1S
D
4
D
TP30
S
D
R2970 2 1 330K_5%_2
1 2 5 6
R2971 2 1 47K_5%_2
3
MAX 2.8A
Q7100
TP7051
P3V3ALW
22_5%_2
G
1
R7152
4
3 2
S
P1V5S
D
D
P1V5
22_5%_2_DY
MAX 3.3A
Q7050 1 2 5 6
P5V0S
P5V0A_CHG
R7151
P3V3S
3 2
P3V3ALW
P1V8S
Q2970
21
2
2 1 100K_5%_2
2
P1V05M
E C
3
2 1 200K_5%_2
2
1
R2973 47_5%_2
C2976
1
1
C2975
10UF_6.3V_3
3
2
R2974
D S
G
D
1
G
SSM3K7002FU
S
IN
2
PM_SLP_A#
1
1
Q2973
20 21 35 48 18
3
Q2974
3 2
D7000 BAV99W_7_F
10UF_6.3V_3
2
100K_5%_2 2
1
R7003 2 1 61.9K_1%_2
1
1 C7000 2
0.1UF_25V_2
2
SSM3K7002FU
2
Q7000 MMBT3906
3
19 18
100K_5%_2_DY
R7002 2 1 124K_1%_2 R7001 2 1
3 D S
SSM3K7002FU 27
42 48 57
P5V0A
G
2
45 55
SLP_S3#_3R 1
B
IN
E C
9 20 21
19
B
Q7002 35SLP_S3#_3R
SPWON
Q7001 MMBT3906
R7005
B
B
S
C
23
OUT 1
SSM3K7002FU
48
SSM3K7002FU
R7004
SLP_S3_5R
2
D
SSM3K7002FU
G
S
S
S
OUT
P5V0A
G
SSM3K7002FU
2
C
SLP_LAN# 1
2
1
G
SSM3K7002FU
IN
35 19
D
D
1
G
SLP_LAN#
Q7150
2
1
3
3
3
Q7101 D
Q7051
A
A
VRP5V0A_PH
1
IN
C7001 R7000 2 1 2 10_5%_2 0.01UF_50V_2
INVENTEC TITLE
MODEL,PROJECT,FUNCTION POWER(SLEEP)
REFERENCE NUMER : 2950~2999
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
19
80
of
1
X01
8
7
6
5
4
3
2
1
2 1M_5%_2
P5V0A 8
21 20 33 35
1 R7415 2 3.3K_5%_2
M_PWROK
M_PWROK IN
1 R7409 2 0_5%_2
3
5
R7411 1 2 22.6K_1%_2 R7413 1 2 49.9K_1%_2 1 R7402 2
P3V3S
C 15
IN
V-
4 1R7406
1
3
2
R7401
1 R6910 1 2 R6909 2 48
C 2
0.1UF_16V_2 U7400 1 OUT
-IN
V-
4
C7401
27.4K_1%_2
V+
++IN -
0_5%_2 2
1 R7425 2 3.3K_5%_2
IN
R7408
1
TI_LMV393IDGKR_SOP_8P
3300PF_50V_2
1
P1V8S_PG
23
20
2
13
D
48
ADP_A_ID
2 1M_5%_2
1C7400
1 R7400 2 3.3K_5%_2
VCCP_PG IN
18 PWR_GOOD_3
TI_LMV393IDGKR_SOP_8P
RSC_0402_DY
2
12
COLLECTOR
LES_LMBT3906WT1G_SOT323_3P
OUT
PWR_GOOD_3 OUT
7
3
EMITTER
P5V0A
8
AXG_PG
U7400 OUT
7
-IN
2 R7412 1 49.9K_1%_2
1
BAT54A
3300PF_50V_2
2 R7418 1 RSC_0402_DY C7403 2 1
6
P1V5S
V+
++IN -
VBIAS
1
D7414
OUT
8.66K_1%_2
1 1R7407
3.3K_5%_2
2
P3V3S
220K_5%_2
R6902 1 1000PF_50V_2
R6903
2
2 34.8K_1%_2
R6904
SLP_S3#_3R
IN
C7402
2VREF 1 R7410
2VREF IN
2
57 45 42 27 55 19 20
35 SLP_S3#_3R
8 7 20
Q6900
2
45.3K_1%_2
18
1 R7417 2 3.3K_5%_2 1 R7414 2
2
9
IN
VCCSA_PG
14
D
9
1 R7416 2 11.5K_1%_2
2 R7404 1 3.3K_5%_2
P0V75S 48
1 2
1 R7405 2 76.8K_1%_2
1 BASE
P5V0S
130K_1%_2
REFERENCE NUMER : 7400~7450
P3V3AL
IN
LIMIT_SIGNAL_100R
7
8.06K_1%_2
PVADPTR
B
B
AMBIENT TEMP SENSE P3V3A
3
PM_SLP_A#
IN
PM_SLP_A#
1 R2957 2 3.3K_5%_2
2
1
0_5%_2 3
OUT
1
3.3K_5%_2 M_PWROK
4
-
5
M_PWROK35 33
C4411 0.1UF_16V_2 20
VCC
SET GND
4
OUT
R2963
U2951
R2962 2
150_1%_2
-
BAT54A
1
U2950
+
1
HYST
OT
136K_1%_3 2
1 2 3
IN
EN_5V_3V
2
A
AZV331KTR_E1
75 DEG. => 36 KOHM 110 DEG. => 10 KOHM
1
R2956 2 1M_5%_2
1
C2951 2
INVENTEC TITLE
0.068UF_10V_2
21
MODEL,PROJECT,FUNCTION
D2951
POWER(SEQUENCE)
REFERENCE NUMER : 2950~2999
SIZE A3
CHANGE by
8
7
8 9
GMT_G708T1U_SOT23_5P
2
1 R2958 2 14.7K_1%_2
18 20
R2955
1
R2961 1
1 R2959 2 46.4K_1%_2
P1V05M
19 35 48
2 R2954
P3V3M
5
C2950 2
P5V0A
1
A
R2953 2 1M_5%_2
1K_1%_2
1
2
1R2950 2 41.2K_1%_3
2
2VREF
3300PF_50V_2
IN
2 R2960 1 86.6K_1%_2 C2952 2 1
2VREF
71.5K_1%_2
7
1
8
1000PF_50V_2 2 R2951 1
9
+
20
P5V0S
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
20
80
of
1
X01
8
7
6
5
4
3
2
1
D
D
C
C P3V3A
CN4921
SLP_S3#_3R SLP_S4#_3R SLP_S5#_3R PM_SLP_A# 61 48
55 35
49 19
IN IN IN IN
ON_OFF# IN
SLP_LAN#
IN
1 2 3 4 5 6 7 8
ENTERY_3703K_Q08N_11R_8P_DY 1 2 3 4 5 6
G1
7
G2
G1 G2
8
ME DEBUG
B
B
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION XDP CONN
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
21
80
of
1
X01
8
7
6
5
4
3
2
1
REFERENCE NUMBER:4400~4349 P3V3S
P5V0S
0_5%_2
R4301 2
1
D
D
20 MILS 1
IN
2
R4300 4
1
2
TACH_FAN_IN_1126
OUT
22_5%_2
1 2
G
3
G
G1 G2
4
ACES_50271_0040N_001_4P
TC7SET00F
2
C4300
1
3
22 THERM#
IN
48
0.1UF_16V_2_DY
PWM_3S_FAN#
-
48
+
5
CN4300 1 2 3 4
U4300
C
C
REFERENCE NUMBER:4450~4499 THERM SENSOR P3V3S
C4451 1 2 3 4
H_THERMDA H_THERMDC 22
THERM#
OUT
1
0_5%_2
R4452 2
2
C4450
1
2200PF_50V_2 1 2
1
2
R4453
E
2
C
Q4450 MMBT3904
2.2K_5%_2
B
3
B
0.1UF_16V_2
1
B
U4450 VDD
SMCLK
DP
SMDATA
DN
ALERT#
THERM#/ADDR
GND
8 7 6 5
BI BI OUT
THERM_CLK THERM_DATA THERM_SCI#
47 34 34 47 38
SMSC_EMC1412_1_ACZL_TR_MSOP_8P
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION FAN & THERMAL
REFERENCE NUMBER:4411~4449
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
22
80
of
1
X01
8
7
6
5
4
3
2
1
1 R4539 1
OUT
2.2K_5%_2
R4536
U4500
H_SNB_IVB#
2
F49
CLOCKS
SNB_IVB#
38
2
2
R4535
1K_5%_2_DY
1
P1V8S
PROC_SELECT#
MISC
1K_5%_2 TP1 TP24
1
C57
TP4503 TP24
1
C49
CATERR#
A48
PECI
PROC_DETECT#
P1V05S_VCCP
J3 H2
BCLK BCLK#
DPLL_REF_CLK#
THERMTRIP#
SM_RCOMP[2]
JTAG & BPM
P1V5S
TP2438
2Y
4
38
B46 TP2440
IN R4530 1
BE45
2
32
1
1
RESET#
P1V05S_VCCP
39_5%_2_DY
1
D
19
P3V3S
PWR_GOOD_3 IN
50 37 48 53 54 60
U4501 2
IN
BUF_PLT_RST#
2
+
2
SSM3K7002FU_DY
2
5
B
4
1
4
R4555
BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]
43_5%_2
R4655
3
IN
PCH_DDR_RST
2
1
2
R4563
3
1
H_TRST# H_TCK
TP30 TP30 TP30 TP30 TP30 TP30 TP30 TP30
TP2450 TP2451 TP2452 TP2453 TP2454 TP2455 TP2456 TP2457
R4551 1
2
B
1K_5%_2
IN IN IN
R4552 1
2
51_5%_2
R4553 1
2
51_5%_2
R4554 1
2
51_5%_2
IN IN
R4556 1
2 51_5%_2
R4557 1
2 51_5%_2
R4564
32
1
2
OUT
DDR3_DRAMRST#29 31 30
1K_5%_2
Q4522 D
S
3
100K_5%_2
15 23
SSM3K7002FU
1
DDR_RST_EN
G
A S
CPU_PROCHOT#
BSS138
2
IN
TC7SZ05F R4607
H_TDI
G
2
4 -
R4561 2 1 20K_5%_2
2
IN
H_TMS
D
1 5 NC
IN
+
KBC_PROCHOT
1
48
H_TDO
P1V5
1
KBC_GPIO22
1 H_BPM0_XDP# 1 H_BPM1_XDP# 1 H_BPM2_XDP# 1 H_BPM3_XDP# 1 H_BPM4_XDP# 1 H_BPM5_XDP# 1 H_BPM6_XDP# 1 H_BPM7_XDP#
P1V05S_VCCP
1
1
0.1UF_16V_2
C4688 2
A
XDP_DBRESET#
35 IN XDP_DBRESET#
Q4595
U4607
C
P3V3S
20K_1%_2
48 18
H_TDI H_TDO
G58 E55 E59 G55 G59 H60 J59 J61
BPM#[1]
R4571 34
H_TCK H_TMS H_TRST#
P3V3AL
2
NXP_74LVC1G07GW_TSSOP_5P
P3V3S
K58
BPM#[0]
ITL_IVY_BRIDGE_BGA1023_2C_GT1_1023P
1
NC -
140_1%_2 25.5_1%_2 200_1%_2
TP2437 TP30
1
SLP_S3_5R
S
2
IN
R4567
1
G
75_5%_2
Q4505
0.1UF_16V_2
18
SM_DRAMPWROK
TP2441
D44 R4528
2 2 2
23
H_PRDY# H_PREQ#
M60 L59
TDI TDO
DBR#
TP30
C4605
20
R4562
1
DDR3_DRAMRST#_CPU IN
2
0_5%_2_DY
4.99K_1%_2
1 2
1 C4690 2
470PF_50V_2
2
23
INVENTEC
R4550
TITLE
MODEL,PROJECT,FUNCTION CPU-1/6
SIZE A3
CHANGE by
8
7
D
TP30
130_1%_2
NXP_74LVC2G07GW_SC88A_6P
48
UNCOREPWRGOOD
1
H_PWRGD R4527 200_1%_2
PM_SYNC
TP30
1K_1%_2
5
C48 TP2439
BI
1
2A
6
H_PM_SYNC
2
3
1Y VCC
35
2
1
1A GND
R4570
0_5%_2
C4523
TMS TRST#
PWR MANAGEMENT
U4502
1
1
R4529
1
1UF_6.3V_2 2 1
200_1%_2 2 1
TP30
2
R4558 1 R4559 1 R4560 1 TP2432 TP2434 TP2436 TP30 TP30 TP30 TP2431 TP2433 TP2435 TP30 TP30 TP30
L56 L55 J58
TCK
20K_1%_2_DY
P3V3A
1
SM_RCOMP0 SM_RCOMP1 SM_RCOMP2
N53 N55
PRDY#
P3V3S
PM_DRAM_PWRGD IN
TP24 TP24
1
D45
OUT
PM_THRMTRIP#
SM_RCOMP[1]
1
38
BF44 BE43 BG43 TP2430 TP30
SM_RCOMP[0]
DDR3_DRAMRST#_CPU
1
PROCHOT#
OUT
1
1 C4697 2
H_PROCHOT#_R C45
2
56_5%_2
PREQ#
35
1 1
TP4520 TP4521
1
R4540 1
AT30
SM_DRAMRST#
1
OUT
1
H_PECI
CPU_PROCHOT# IN
C
P1V05S_VCCP
FOR IVB 2C FINAL SYMBOL MOVE TO OTHER BLOCK
MISC DDR3
1
62_5%_2
R4531 2
48 38
47pF_50V_2
15
34 34
CLOSE U6600
THERMAL
23
XDP_BCLK_ITP_DP XDP_BCLK_ITP_DN
N59 N58
BCLK_ITP BCLK_ITP#
CLK_DMI_PCH_DP CLK_DMI_PCH_DN
1 1K_5%_2 2 R4500 1 2 R4501 1K_5%_2
AG3 AG1
DPLL_REF_CLK
D
IN IN
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER 1310xxxxx-0-0 SHEET
23
of
80
1
REV X01
8
7
6
5
4
3
2
1
P1V05S_VCCP
U4500 PEG_ICOMPI
DMI_TX0_DN DMI_TX1_DN DMI_TX2_DN DMI_TX3_DN
M2 P6 P1 P10
IN IN IN IN
DMI_TX0_DP DMI_TX1_DP DMI_TX2_DP DMI_TX3_DP
N3 P7 P3 P11
OUT OUT OUT OUT
DMI_RX0_DN DMI_RX1_DN DMI_RX2_DN DMI_RX3_DN
K1 M8 N4 R2
OUT OUT OUT OUT
DMI_RX0_DP DMI_RX1_DP DMI_RX2_DP DMI_RX3_DP
K3 M7 P4 T3
35 35 35 35 35 35 35 35
35 35 35 35 35 35 35 35
C
OUT OUT OUT OUT OUT OUT OUT OUT
FDI_TX0_DN FDI_TX1_DN FDI_TX2_DN FDI_TX3_DN FDI_TX4_DN FDI_TX5_DN FDI_TX6_DN FDI_TX7_DN
DMI_RX#[3]
PEG_RX#[0]
DMI_RX[0]
PEG_RX#[2]
DMI_RX[1]
PEG_RX#[3]
DMI_RX[2]
PEG_RX#[4]
DMI_RX[3]
PEG_RX#[5]
DMI_TX#[0]
PEG_RX#[6] PEG_RX#[7]
DMI_TX#[1]
PEG_RX#[8]
DMI_TX#[2]
PEG_RX#[9]
DMI_TX#[3]
PEG_RX#[10]
U6 W10 W3 AA7 W7 T4 AA3 AC8
35 35
IN IN
FDI_FSYNC0 FDI_FSYNC1
AA11 AC12
35
IN
FDI_INT
IN IN
FDI_LSYNC0 FDI_LSYNC1
DMI_TX[0]
PEG_RX#[12]
DMI_TX[1]
PEG_RX#[13]
DMI_TX[2]
PEG_RX#[14]
DMI_TX[3]
FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3]
FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC
Intel(R) FDI
FDI_TX0_DP FDI_TX1_DP FDI_TX2_DP FDI_TX3_DP FDI_TX4_DP FDI_TX5_DP FDI_TX6_DP FDI_TX7_DP
PEG_RX#[15] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7]
U11
FDI_INT
PEG_TX#[8] PEG_TX#[9]
35 35
AA10 AG8
FDI0_LSYNC
PEG_TX#[10]
FDI1_LSYNC
PEG_TX#[11] PEG_TX#[12]
P1V05S_VCCP
PEG_TX#[13]
B
PEG_TX#[14] PEG_TX#[15]
1 R4502 2 24.9_1%_2
CPU_EDP_COMPIO
AF3 AD2 AG11
eDP_ICOMPO
PEG_TX[0]
eDP_HPD
PEG_TX[1] PEG_TX[3]
eDP_AUX#
PEG_TX[4]
eDP_AUX
PEG_TX[5] PEG_TX[6]
eDP_TX#[0] eDP_TX#[1]
PEG_TX[7]
DP
AC3 AC4 AE11 AE7
PEG_TX[8] PEG_TX[9]
eDP_TX#[2]
PEG_TX[10]
eDP_TX#[3]
PEG_TX[11] PEG_TX[12]
AC1 AA4 AE10 AE6
1
2
24.9_1%_2
H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7
IN IN IN IN IN IN IN IN
72 PEG_RX0_C_DN 72 PEG_RX1_C_DN 72 PEG_RX2_C_DN 72 PEG_RX3_C_DN 72 PEG_RX4_C_DN 72 PEG_RX5_C_DN 72 PEG_RX6_C_DN 72 PEG_RX7_C_DN
K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6
IN IN IN IN IN IN IN IN
72 PEG_RX0_C_DP 72 PEG_RX1_C_DP 72 PEG_RX2_C_DP 72 PEG_RX3_C_DP 72 PEG_RX4_C_DP 72 PEG_RX5_C_DP 72 PEG_RX6_C_DP 72 PEG_RX7_C_DP
G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4
PEG_TX0_DN PEG_TX1_DN PEG_TX2_DN PEG_TX3_DN PEG_TX4_DN PEG_TX5_DN PEG_TX6_DN PEG_TX7_DN
F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4
PEG_TX0_DP PEG_TX1_DP PEG_TX2_DP PEG_TX3_DP PEG_TX4_DP PEG_TX5_DP PEG_TX6_DP PEG_TX7_DP
eDP_COMPIO
PEG_TX[2]
AG4 AF4
CPU_PEG_ICOMPI
DMI_RX#[2]
PEG_RX#[11]
U7 W11 W1 AA6 W6 V4 Y2 AC9
G3 G1 G4
DMI_RX#[1]
PEG_RX#[1]
OUT OUT OUT OUT OUT OUT OUT OUT
35 35 35 35 35 35 35 35
PEG_RCOMPO
DMI
35 35 35 35
DMI_RX#[0]
PCI EXPRESS -- GRAPHICS
D
PEG_ICOMPO
IN IN IN IN
35 35 35 35
R4503
eDP_TX[0]
PEG_TX[13]
eDP_TX[1]
PEG_TX[14]
eDP_TX[2]
PEG_TX[15]
1 C4837 1 C4838 1 C4839 1 C4840 1 C4841 1 C4842 1 C4843 1 C4844
D
C
2 2 2 2 2 2 2 2
0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2
OUT OUT OUT OUT OUT OUT OUT OUT
72 PEG_TX0_C_DN 72 PEG_TX1_C_DN 72 PEG_TX2_C_DN 72 PEG_TX3_C_DN 72 PEG_TX4_C_DN 72 PEG_TX5_C_DN 72 PEG_TX6_C_DN 72 PEG_TX7_C_DN
B 1 C4853 1 C4854 1 C4855 1 C4856 1 C4857 1 C4858 1 C4859 1 C4860
2 2 2 2 2 2 2 2
0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2 0.1UF_16V_2
OUT OUT OUT OUT OUT OUT OUT OUT
72 PEG_TX0_C_DP 72 PEG_TX1_C_DP 72 PEG_TX2_C_DP 72 PEG_TX3_C_DP 72 PEG_TX4_C_DP 72 PEG_TX5_C_DP 72 PEG_TX6_C_DP 72 PEG_TX7_C_DP
eDP_TX[3]
ITL_IVY_BRIDGE_BGA1023_2C_GT1_1023P
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION CPU-2/6
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
24
80
of
1
X01
8
7
6
5
4
3
2
1
U4500
C
B
M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
AG6 AJ6 AP11 AL6 AJ10 AJ8 AL8 AL7 AR11 AP6 AU6 AV9 AR6 AP8 AT13 AU13 BC7 BB7 BA13 BB11 BA7 BA9 BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56
SA_DQ[0] SA_DQ[1]
SA_CLK[0]
SA_DQ[2]
SA_CLK#[0]
SA_DQ[3]
SA_CKE[0]
SA_DQ[8] SA_DQ[9]
SA_CLK[1]
SA_DQ[10]
SA_CLK#[1]
SA_DQ[11]
SA_CKE[1]
M_CKE1
OUT
29 29 29
SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17]
SA_CS#[0]
SA_DQ[18]
SA_CS#[1]
BB40 BC41
M_CS#0 M_CS#1
OUT OUT
29 29
SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24]
SA_ODT[0]
SA_DQ[25]
SA_ODT[1]
SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44]
SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]
SA_DQ[45]
SA_DQS[0]
SA_DQ[46]
SA_DQS[1]
SA_DQ[47]
SA_DQS[2]
SA_DQ[48]
SA_DQS[3]
SA_DQ[49]
SA_DQS[4]
SA_DQ[50]
SA_DQS[5]
SA_DQ[51]
SA_DQS[6]
SA_DQ[52]
SA_DQS[7]
AY40 BA41
AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55
AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54
M_ODT0 M_ODT1
OUT OUT
M_A_DQS0_DN M_A_DQS1_DN M_A_DQS2_DN M_A_DQS3_DN M_A_DQS4_DN M_A_DQS5_DN M_A_DQS6_DN M_A_DQS7_DN
OUT OUT OUT OUT OUT OUT OUT OUT
M_A_DQS0_DP M_A_DQS1_DP M_A_DQS2_DP M_A_DQS3_DP M_A_DQS4_DP M_A_DQS5_DP M_A_DQS6_DP M_A_DQS7_DP
OUT OUT OUT OUT OUT OUT OUT OUT
29 29
29 29 29 29 29 29 29 29
29 29 29 29 29 29 29 29
SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57]
AL4 AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9 BD13 BF12 BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59 AM60 AL59 AF61 AH60
SB_DQ[0] SB_DQ[1]
SB_CLK[0]
SB_DQ[2]
SB_CLK#[0]
SB_DQ[3]
SB_CKE[0]
SB_DQ[9]
SB_CLK[1]
SB_DQ[10]
SB_CLK#[1]
SB_DQ[11]
SB_CKE[1]
SA_MA[1]
SA_DQ[63]
SA_MA[2]
SA_MA[6]
BD37 BF36 BA28
SA_BS[0]
SA_MA[7]
SA_BS[1]
SA_MA[8]
SA_BS[2]
SA_MA[9]
SA_MA[12]
BE39 BD39 AT41
SA_CAS#
SA_MA[13]
SA_RAS#
SA_MA[14]
SA_WE#
SA_MA[15]
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29
OUT OUT OUT
M_B_BS0 M_B_BS1 M_B_BS2
BG39 BD42 AT22
M_B_CAS# M_B_RAS# M_B_WE#
M_ODT2 M_ODT3 1
OUT OUT
30 32 31
M_B_DQS0_DN M_B_DQS1_DN M_B_DQS2_DN M_B_DQS3_DN M_B_DQS4_DN M_B_DQS5_DN M_B_DQS6_DN M_B_DQS7_DN
OUT OUT OUT OUT OUT OUT OUT OUT
30 30 30 30 31 31 31 31
OUT OUT OUT OUT OUT OUT OUT OUT
30 30 30 30 31 31 31 31
SB_DQ[16] SB_DQ[17]
SB_CS#[0]
SB_DQ[18]
SB_CS#[1]
TP24 TP4508
SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24]
SB_ODT[0]
SB_DQ[25]
SB_ODT[1]
SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44]
TP24 TP4509
AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59
SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]
SB_DQ[45] SB_DQ[46]
SB_DQS[0]
SB_DQ[47]
SB_DQS[1]
SB_DQ[48]
SB_DQS[2]
SB_DQ[49]
SB_DQS[3]
SB_DQ[50]
SB_DQS[4]
SB_DQ[51]
SB_DQS[5]
SB_DQ[52]
SB_DQS[6]
SB_DQ[53]
SB_DQS[7]
M_B_DQS0_DP M_B_DQS1_DP M_B_DQS2_DP M_B_DQS3_DP M_B_DQS4_DP M_B_DQS5_DP M_B_DQS6_DP M_B_DQS7_DP
AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61
C
SB_DQ[54]
B
SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61]
SB_MA[0]
SB_DQ[62]
SB_MA[1]
SB_DQ[63]
SB_MA[2]
BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22
SB_MA[7]
SB_BS[0]
SB_MA[8]
SB_BS[1]
SB_MA[9]
SB_BS[2]
SB_MA[12]
AV43 BF40 BD45
AT43 BG47
SB_DQ[15]
SB_MA[11]
OUT OUT OUT
30 32 31
SB_DQ[14]
SB_MA[10]
32 31 30 32 31 30 32 31 30
OUT
D
TP4505 TP4506 TP4507
SB_DQ[13]
SB_MA[6]
30 32 31 32 31 30 32 31 30
M_CS#2 1
TP24 TP24 TP24
SB_DQ[12]
SB_MA[5] SA_MA[0]
BE41 BE47
SB_DQ[8]
SB_MA[4]
SA_DQ[62]
1 1 1
SB_DQ[7]
SB_MA[3]
SA_DQ[61]
BA36 BB36 BF27
30 32 31 30 32 31 32 31 30
OUT OUT OUT
M_CKE2
SB_DQ[6]
SA_DQ[60]
M_A_A M_A_A M_A_A M_A_A M_A_A M_A_A M_A_A M_A_A M_A_A M_A_A M_A_A M_A_A M_A_A M_A_A M_A_A M_A_A
M_CLK_DDR2_DP M_CLK_DDR2_DN
SB_DQ[5]
SA_DQ[59]
BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26
BA34 AY34 AR22
SB_DQ[4]
SA_DQ[58]
SA_MA[11]
M_A_CAS# M_A_RAS# M_A_WE#
M_CLK_DDR1_DP OUT M_CLK_DDR1_DN OUT
SA_DQ[13]
A OUT OUT OUT
AT40 AU40 BB26
SA_DQ[12]
SA_MA[10]
29 29 29
OUT
SA_DQ[7]
SA_MA[5]
M_A_BS0 M_A_BS1 M_A_BS2
M_CKE0
29 29 29
SA_DQ[6]
SA_MA[4]
OUT OUT OUT
M_CLK_DDR0_DP OUT M_CLK_DDR0_DN OUT
SA_DQ[5]
SA_MA[3]
29 29 29
AU36 AV36 AY26
SA_DQ[4]
DDR SYSTEM MEMORY A
D
29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ
DDR SYSTEM MEMORY B
U4500
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31
SB_CAS#
SB_MA[13]
SB_RAS#
SB_MA[14]
SB_WE#
SB_MA[15]
M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A
30 32 31 32 31 30 32 31 30 32 31 30 32 31 30 32 31 30 32 31 30 32 31 30 32 31 30 32 31 30 32 31 30 32 31 30 32 31 30 32 31 30 32 31 30 32 31 30
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
A ITL_IVY_BRIDGE_BGA1023_2C_GT1_1023P
INVENTEC
ITL_IVY_BRIDGE_BGA1023_2C_GT1_1023P
TITLE
MODEL,PROJECT,FUNCTION CPU-3/6
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0
X01
SHEET
25
80
of
1
7
8
6
5
4
3
2
1
F
F
U4500 P1V05S_VCCP
VCC[53] VCC[54] VCC[55]
VCCIO[48] VCCIO[49]
1 C4562 2
1UF_6.3V_2
1UF_6.3V_2
1 2
1UF_6.3V_2 C4556 2 1
C4550
1 2
1UF_6.3V_2
C4545
1 2
1UF_6.3V_2
1 2
C4540
1UF_6.3V_2
1 2
C4535
1UF_6.3V_2
C4530
1 2
1UF_6.3V_2
1 2
1UF_6.3V_2
1 2
C4596
1
1
1UF_6.3V_2
C4592
C4588
C4584
C4579
C4600
1 C4518 2
1UF_6.3V_2
1 2
C4513
1UF_6.3V_2
1 C4598 2
1UF_6.3V_2
1
1UF_6.3V_2
1UF_6.3V_2 C4528 2 1
1UF_6.3V_2 C4526 2 1
1 C4516
1UF_6.3V_2 C4521 2 1
1 C4613 2
10UF_6.3V_3
1 C4610 2
10UF_6.3V_3
1
1 C4604
C4607 2
2 1 C4599 2
VCCIO[47]
D
1UF_6.3V_2
VCC[52]
1
VCCIO[46]
VCC[51]
C4595
VCCIO[45]
VCC[50]
2
VCCIO[44]
VCC[49]
1UF_6.3V_2
VCCIO[43]
VCC[48]
1
VCCIO[42]
VCC[47]
C4591
VCCIO[40] VCCIO[41]
VCC[46]
2
VCCIO[39]
VCC[45]
1UF_6.3V_2
VCCIO[38]
VCC[43] VCC[44]
10UF_6.3V_3
VCCIO[37]
1
VCCIO[36]
C4587
VCC[42]
VCCIO[35]
2
VCC[41]
VCCIO[34]
1UF_6.3V_2
VCC[40]
3.9A
2
VCC[39]
VCCIO[33]
10UF_6.3V_3
VCC[38]
VCCIO[32]
1
VCC[37]
VCCIO[30] VCCIO[31]
C4582
VCC[36]
2
VCC[35]
1UF_6.3V_2
VCC[33] VCC[34]
P1V05S_VCCP
AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15
1
VCC[32]
C4601
VCC[31]
2
VCC[30]
10UF_6.3V_3
VCC[29]
VCCIO[29]
1
VCC[28]
VCCIO[27] VCCIO[28]
C4501
VCC[27]
2
VCC[26]
1UF_6.3V_2
VCC[25]
C4563
VCCIO[26]
VCC[23] VCC[24]
2
VCCIO[25]
VCC[22]
10UF_6.3V_3
VCCIO[24]
VCC[21]
1
VCCIO[23]
VCC[20]
C4568
VCCIO[22]
VCC[19]
2
VCCIO[21]
VCC[18]
10UF_6.3V_3
VCCIO[20]
VCC[17]
PEG AND DDR
VCCIO[18] VCCIO[19]
VCC[16]
2
VCCIO[17]
VCC[14] VCC[15]
1UF_6.3V_2
VCC[13]
E
1
VCCIO[16]
C4589
VCCIO[15]
VCC[12]
2
VCCIO[14]
VCC[11]
10UF_6.3V_3
VCCIO[13]
VCC[10]
2
VCC[9]
1UF_6.3V_2
VCCIO[12]
1
VCC[8]
C4585
VCCIO[11]
2
VCC[7]
10UF_6.3V_3
VCCIO[10]
2
VCCIO[9]
VCC[6]
1UF_6.3V_2
VCCIO[8]
VCC[4] VCC[5]
1
VCCIO[7]
VCC[3]
C4580
VCCIO[6]
VCC[2]
VCC[56] VCC[57] VCC[58]
VCCIO50
VCC[59]
VCCIO51
W16 W17
VCC[60] VCC[61] VCC[62] VCC[63]
C
VCC[64] VCC[66]
VCCPQE[1]
P1V05S_VCCP P1V05S_VCCP
0.4A
SVID
VIDALERT# VIDSCLK VIDSOUT
A44 B43 C44
H_CPU_SVIDALRT#
R4509
1
75_1%_2
CLOCE U6600
1
2
VCC[76]
1
VCCPQE[2]
R4512
VCC[74] VCC[75]
AM25 AN22
12
2
VCC[73]
OUT
130_1%_2
VCC[72]
2
VCC[71]
VCCIO_SEL
R4506
VCC[70]
BC22
1UF_6.3V_2
VCC[69]
VCCIO_SEL
1
VCC[68]
C4583
VCC[67]
QUIET RAILS
1 C4570
2.2UF_6.3V_2
2 1 C4508 2
2.2UF_6.3V_2
1 C4564 2
2.2UF_6.3V_2
2 1 C4503
2.2UF_6.3V_2
1 2
2.2UF_6.3V_2
C4558
2.2UF_6.3V_2
1 C4552 2
2.2UF_6.3V_2
1 C4547 2
2.2UF_6.3V_2
1 C4542 2
1 2
2.2UF_6.3V_2
C4537
1 2
2.2UF_6.3V_2
C4532
2.2UF_6.3V_2
1
1 2
C4527
C4522 2
2.2UF_6.3V_2
1 2
1
2.2UF_6.3V_2
C4517
C4512 2
2.2UF_6.3V_2
1 C4507 2
2.2UF_6.3V_2
1 C4502 2
2.2UF_6.3V_2
C
VCCIO[5]
VCC[1]
CORE SUPPLY
D
A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38
POWER
1
E
22UF_6.3V
1
C4546
1 2
2
2
1
22UF_6.3V
1
C4555
1 2
2
2
22UF_6.3V
1
C4549
1 2
2
22UF_6.3V
1
C4544
1
22UF_6.3V
1
C4539
2
2
2
22UF_6.3V
1
C4534
1 2
1
22UF_6.3V
1
2
2
C4529
1 2
2
22UF_6.3V
1
C4524
1
22UF_6.3V
1
C4519
1 2
2
2
2
22UF_6.3V
1
C4514
1
22UF_6.3V
1 2
2
1
C4509
C4504
2
2
22UF_6.3V
VCCIO[4]
2
VCCIO[3]
AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48
10UF_6.3V_3
VCCIO[1]
1
3.2A PVCORE
VR_SVID_ALERT# VR_SVID_CLK VR_SVID_DATA
2 43_5%_2
OUT OUT OUT
15 15 15
B VCCSENSE VSSSENSE
OUT OUT
15 15
OUT OUT
12 12
VTT_SENSE VSS_SENSE_VTT
2
R4508
1
2
ITL_IVY_BRIDGE_BGA1023_2C_GT1_1023P
10_1%_2
R4507
1
P1V05S_VCCP
10_1%_2
1 AN16 AN17
2
VCCIO_SENSE VSS_SENSE_VCCIO
R4505
1
VSS_SENSE
F43 G43
2
R4504 VCC_SENSE
100_1%_2
SENSE LINES
B
100_1%_2
PVCORE
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION CPU-4/6
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
26
1
X01 of
80
6
5
4
P0V75S_DIMM0_VREF_DQ
F
1
2
2
TP4530 1
1 C4685
VAXG[37] VAXG[38] VAXG[39] VAXG[40] VAXG[41] VAXG[42] VAXG[43] VAXG[44] VAXG[45]
2
1 2
2
C4498
1
0.1UF_16V_2_DY
1 C4497 2
1
1UF_6.3V_2
1 2
C4520
1UF_6.3V_2
1 +
2
100UF_6.3V
1 2
1UF_6.3V_2
C4515 C4511
1 2
10UF_6.3V_3
C4510
1 2 1
1UF_6.3V_2
C4505
1 2
1
1UF_6.3V_2
C4500
C4686 2
1UF_6.3V_2
1UF_6.3V_2
1 2
C4683
1 2
1
1UF_6.3V_2
C4681
VAXG[46] VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54] VAXG[55]
0.6A
AM28 AN26
1
VCCDQ[2]
C4676
VSSAXG_SENSE
P1V5S VCCDQ[1]
2
VAXG_SENSE
C 1UF_6.3V_2
VAXG[56]
VCCPLL[1] VCCPLL[2] VCCPLL[3]
VCCSA[1] VCCSA[2]
VDDQ_SENSE VSS_SENSE_VDDQ
BC43 BA43
1 1
TP4500 TP4501
PVSA
TP24 TP24
R4513 1
VCCSA[3] VCCSA[4]
2
100_5%_2_DY
VCCSA[5] VCCSA[6] VCCSA[7] VCCSA[8] VCCSA[9] VCCSA[10] VCCSA[11] VCCSA[12] VCCSA[13]
VCCSA_SENSE
U10
VCCSA_VID[0]
D48 D49
VCCSA_SENSE
OUT
14
B
VCCSA[14]
VCCSA_VID[1]
VCCSA_VID0 VCCSA_VID1
OUT OUT
14 14
VCCSA[15] VCCSA[16]
R4631 1K_5%_2
1
1
R4630 1K_5%_2
1UF_6.3V_2
1 2
C4567
1 2
1UF_6.3V_2
C4664
1 C4506 2
1UF_6.3V_2
1 C4650 2
1UF_6.3V_2
1UF_6.3V_2
1 C4643
2
1
D
VAXG[36]
ITL_IVY_BRIDGE_BGA1023_2C_GT1_1023P
2
C4525
VDDQ[26]
2
VDDQ[25]
10UF_6.3V_3
VDDQ[24]
1
VDDQ[23]
VAXG[35]
C4691
VDDQ[22]
VAXG[34]
2
VDDQ[21]
VAXG[33]
10UF_6.3V_3
VDDQ[20]
VAXG[32]
C4689
VDDQ[18] VDDQ[19]
VAXG[31]
1
VDDQ[17]
VAXG[30]
C4687
VDDQ[16]
VAXG[29]
2
VDDQ[15]
VAXG[27] VAXG[28]
10UF_6.3V_3
VDDQ[14]
10UF_6.3V_3
VAXG[26]
VDDQ[13]
1
VAXG[25]
2
VAXG[24]
1
VAXG[23]
C4684
VAXG[22]
VDDQ[9]
VDDQ[12]
2
POWER
VAXG[21]
1UF_6.3V_2
VDDQ[7]
VDDQ[11]
10UF_6.3V_3
VAXG[20]
1
VDDQ[6]
VDDQ[10]
C4682
DDR3
VAXG[19]
C4679
VDDQ[5]
VDDQ[8]
VAXG[18]
2
VAXG[17]
VDDQ[4]
10UF_6.3V_3
VAXG[16]
VDDQ[3]
C4680
VAXG[15]
C4677
VAXG[14]
2
VAXG[13]
4.75A 1UF_6.3V_2
- 1.5V
VAXG[12]
E
AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33
2
10UF_6.3V_3
1 2
10UF_6.3V_3 C4573 2 1
C4663
1 C4656 2
10UF_6.3V_3
1 C4649 2
10UF_6.3V_3
10UF_6.3V_3
1 C4642 2
VDDQ[2]
SA RAIL
4.5A
P1V5S VDDQ[1]
1
VAXG[11]
C4678
VAXG[10]
2
VAXG[9]
10UF_6.3V_3
VAXG[7] VAXG[8]
2
2
22UF_6.3V
1 1
C4669
2
1 C4655 2
1uF_6.3V_2
1 C4648 2
1uF_6.3V_2
PVSA
B
RAILS
VAXG[6]
0.93A
L17 L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21 W20
AY43
VAXG[5]
1.8V RAIL
BB3 BC1 BC4
SM_VREF
VAXG[4]
0.1uF_16V_2
VAXG[3]
QUIET RAILS
1UF_6.3V_2
VAXG[2]
10_5%_2
2 R4517 1
P1V8S
VAXG[1]
SENSE LINES
10_5%_2
F45 G45
1
GFX_VCC_SENSE GFX_VSS_SENSE
OUT OUT
AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46 N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61
SENSE LINES
15 15
1UF_6.3V_2
C4672 1 C4675 2
1UF_6.3V_2
2 2 R4516
C
1UF_6.3V_2
1
1 C4665 2
2 1 C4673 2 22UF_6.3V
1 1 2
2
1UF_6.3V_2
1UF_6.3V_2 1UF_6.3V_2
1 C4666 2
1UF_6.3V_2
1 1
C4674
C4668
1 +
C4616
3 470uF_2V
2
PVAXG
TP30
GRAPHICS
1
2
2
C4667
22UF_6.3V
2
C4659
1
C4660
1 2
2
22UF_6.3V
1
1 1
1
C4653
2
2
2
2
22UF_6.3V
C4646
22UF_6.3V
1 1
2
1 2
C4658
1UF_6.3V_2
1 2
C4651
1UF_6.3V_2
2
1 2
2
1
22UF_6.3V
1
10UF_6.3V_3
2 1 2
10UF_6.3V_3 C4640
1 2
10UF_6.3V_3
C4635 C4636
1 2
C4632
10UF_6.3V_3
C4631
1 2
1
10UF_6.3V_3
C4627
C4623
10UF_6.3V_3
2
D
C4644
C4638
1UF_6.3V_2
1
25A
2.2UF_6.3V_3_DY
R4596 2 1 3.3K_5%_2
R4594
G
U4500
PVAXG
IN
35 48 19 21
100K_5%_2
57 55 42 20
2
G
SLP_S3#_3R 9 45 18
1
27
2
AM2302N
IN
1
DDR_RST_EN
C4499
27
470PF_50V_2
2
IN
3
Q4502
P0V75M_VREF_H
E
F
3
Q4501
R4518
G
1
DDR_RST_EN
AM2302N
1
2
1
DDR_WR_VREF02
1K_5%_2_DY
IN
Q4500
AM2302N
1 R4514
S
2
D
1K_5%_2_DY
28
3
S
2
P0V75M_VREF_H
2
D
DDR_WR_VREF01
IN
P0V75M_VREF
P0V75S_DIMM1_VREF_DQ
R4519
1
0_5%_2_DY
0_5%_2_DY 28
2
D
R4515
1
3
S
7
8
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION CPU-5/6
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
27
1
X01 of
80
7
8
6
5
4
3
2
1
F
F
U4500 U4500
OUT
TP4450 TP4451 TP4452 TP4453 TP4454 TP4455 TP4456 TP4457 TP4458 TP4459 TP4460 TP4461 TP4462 TP4463 TP4464 TP4465 TP4466
E
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53
H43 K43
CFG[0]
RSVD28
CFG[1]
RSVD29
CFG[4]
RSVD30
CFG[5]
RSVD31
CFG[6]
RSVD32
CFG[7]
RSVD33
H48 K48
CFG[10]
RSVD34
CFG[11]
RSVD35
CFG[12]
RSVD36
CFG[13]
RSVD37
CFG[14]
RSVD38
CFG[15] CFG[16] CFG[17]
VCC_VAL_SENSE VSS_VAL_SENSE
RSVD39 RSVD40
RSVD41 RSVD42
VAXG_VAL_SENSE
RSVD44
N42 L42 L45 L47
M13 M14 U14 W14 P13
AT49 K24
AH2 AG13 AM14 AM15
VSSAXG_VAL_SENSE
N50
VCC_DIE_SENSE
RSVD6 RSVD7
DC_TEST_C4
D
BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53 BG9 C29 C35 C40 D10 D14 D18 D22 D26 D29 D35 D4 D40 D43 D46 D50 D54 D58 D6 E25 E29 E3 E35 E40 F13 F15 F19 F29 F35 F40 F55 G48 G51 G6 G61 H10 H14 H17 H21 H4 H53 H58 J1 J49 J55 K11 K21 K51 K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61 M11 M15
27 27
CFG[9]
DC_TEST_A4
BA19 AV19 AT21 BB21 BB19 AY21 BA22 AY22 AU19 AU21 BD21 BD22 BD25 BD26 BG22 BE22 BG26 BE26 BF23 BE24
DDR_WR_VREF01 DDR_WR_VREF02
CFG[8]
RSVD45
F48
OUT OUT
CFG[3]
RSVD43
H45 K45
BE7 BG7
CFG[2]
RESERVED
CFG
RSVD8
DC_TEST_D3
RSVD9
DC_TEST_D1
RSVD10
DC_TEST_A58
RSVD11
DC_TEST_A59
RSVD12
DC_TEST_C59
RSVD13
DC_TEST_A61
RSVD14
DC_TEST_C61
RSVD15
DC_TEST_D61
RSVD16
DC_TEST_BD61
RSVD17
DC_TEST_BE61
RSVD18
DC_TEST_BE59
RSVD19
DC_TEST_BG61
RSVD20
DC_TEST_BG59
RSVD21
DC_TEST_BG58
RSVD22
DC_TEST_BG4
RSVD23
DC_TEST_BG3
RSVD24
DC_TEST_BE3
RSVD25
DC_TEST_BG1
RSVD26
DC_TEST_BE1
RSVD27
DC_TEST_BD1
A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1
ITL_IVY_BRIDGE_BGA1023_2C_GT1_1023P
C
VSS[181]
VSS[251]
VSS[182]
VSS[252]
VSS[183]
VSS[253]
VSS[184]
VSS[254]
VSS[185]
VSS[255]
VSS[186]
VSS[256]
VSS[187]
VSS[257]
VSS[188]
VSS[258]
VSS[189]
VSS[259]
VSS[190]
VSS[260]
VSS[191]
VSS[261]
VSS[192]
VSS[262]
VSS[193]
VSS[263]
VSS[194]
VSS[264]
VSS[195]
VSS[265]
VSS[196]
VSS[266]
VSS[197]
VSS[267]
VSS[198]
VSS[268]
VSS[199]
VSS[269] VSS[270]
VSS[200]
VSS[271]
VSS[201] VSS[202] VSS[203] VSS[204]
VSS
VSS[272] VSS[273] VSS[274]
VSS[205]
VSS[275]
VSS[206]
VSS[276]
VSS[207]
VSS[277]
VSS[208]
VSS[278]
VSS[209]
VSS[279]
VSS[210]
VSS[280]
VSS[211]
VSS[281]
VSS[212]
VSS[282]
VSS[213]
VSS[283]
VSS[214]
VSS[284]
VSS[215]
VSS[285]
VSS[216]
VSS[286]
VSS[217]
VSS[287]
VSS[218]
VSS[288]
VSS[219]
VSS[289]
VSS[220]
VSS[290]
VSS[221]
VSS[291]
VSS[222]
VSS[292]
VSS[223]
VSS[293]
VSS[224]
VSS[294]
VSS[225]
VSS[295]
VSS[226]
VSS[296]
VSS[227]
VSS[297]
VSS[228]
VSS[298]
VSS[229]
VSS[299]
VSS[230]
VSS[300]
VSS[231]
VSS[301]
A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53 A9 AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56 AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46 AC6 AD17 AD20 AD4 AD61 AE13 AE8 AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59 AG10 AG14 AG18 AG47 AG52 AG61 AG7 AH4 AH58 AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48 AJ7 AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61 AM13 AM20 AM22 AM26 AM30 AM34
M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59
VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237]
VSS_NCTF_1
VSS[238]
VSS_NCTF_2
VSS[239]
VSS_NCTF_3
VSS[240] VSS[241] VSS[242] VSS[243]
NCTF
U4500
VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7
VSS[244]
VSS_NCTF_8
VSS[245]
VSS_NCTF_9
VSS[246]
VSS_NCTF_10
VSS[247]
VSS_NCTF_11
VSS[248]
VSS_NCTF_12
VSS[249]
VSS_NCTF_13
VSS[250]
VSS_NCTF_14
A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61
ITL_IVY_BRIDGE_BGA1023_2C_GT1_1023P
CFG[2] : PCI Express* Static x16 Lane Numbering Reversal. 1 = NORMAL MODE 0 = LANE REVERSED
VSS[1]
VSS[91]
VSS[2]
VSS[92]
VSS[3]
VSS[93]
VSS[4]
VSS[94]
VSS[5]
VSS[95]
VSS[6]
VSS[96]
VSS[7]
VSS[97]
VSS[8]
VSS[98]
VSS[9]
VSS[99]
VSS[10]
VSS[100]
VSS[11]
VSS[101]
VSS[12]
VSS[102]
VSS[13]
VSS[103]
VSS[14]
VSS[104]
VSS[15]
VSS[105]
VSS[16]
VSS[106]
VSS[17]
VSS[107]
VSS[18]
VSS[108]
VSS[19]
VSS[109]
VSS[20]
VSS[110]
VSS[21]
VSS[111]
VSS[22]
VSS[112]
VSS[23]
VSS[113]
VSS[24]
VSS[114]
VSS[25]
VSS[115]
VSS[26]
VSS[116]
VSS[27]
VSS[117]
VSS[28]
VSS[118]
VSS[29]
VSS[119]
VSS[30]
VSS[120]
VSS[31] VSS[32] VSS[33] VSS[34]
VSS[121]
VSS
VSS[122] VSS[123] VSS[124]
VSS[35]
VSS[125]
VSS[36]
VSS[126]
VSS[37]
VSS[127]
VSS[38]
VSS[128]
VSS[39]
VSS[129]
VSS[40]
VSS[130]
VSS[41]
VSS[131]
VSS[42]
VSS[132]
VSS[43]
VSS[133]
VSS[44]
VSS[134]
VSS[45]
VSS[135]
VSS[46]
VSS[136]
VSS[47]
VSS[137]
VSS[48]
VSS[138]
VSS[49]
VSS[139]
VSS[50]
VSS[140]
VSS[51]
VSS[141]
VSS[52]
VSS[142]
VSS[53]
VSS[143]
VSS[54]
VSS[144]
VSS[55]
VSS[145]
VSS[56]
VSS[146]
VSS[57]
VSS[147]
VSS[58]
VSS[148]
VSS[59]
VSS[149]
VSS[60]
VSS[150]
VSS[61]
VSS[151]
VSS[62]
VSS[152]
VSS[63]
VSS[153]
VSS[64]
VSS[154]
VSS[65]
VSS[155]
VSS[66]
VSS[156]
VSS[67]
VSS[157]
VSS[68]
VSS[158]
VSS[69]
VSS[159]
VSS[70]
VSS[160]
VSS[71]
VSS[161]
VSS[72]
VSS[162]
VSS[73]
VSS[163]
VSS[74]
VSS[164]
VSS[75]
VSS[165]
VSS[76]
VSS[166]
VSS[77]
VSS[167]
VSS[78]
VSS[168]
VSS[79]
VSS[169]
VSS[80]
VSS[170]
VSS[81]
VSS[171]
VSS[82]
VSS[172]
VSS[83]
VSS[173]
VSS[84]
VSS[174]
VSS[85]
VSS[175]
VSS[86]
VSS[176]
VSS[87]
VSS[177]
VSS[88]
VSS[178]
VSS[89]
VSS[179]
VSS[90]
VSS[180]
AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13
E
D
C
ITL_IVY_BRIDGE_BGA1023_2C_GT1_1023P
B
B
CFG[4] : eDP enable 1 = Disabled 0 = Enabled CFG[6:5] : PCI Express Bifurcation: 00 = 1 x8, 2 x4 PCI Expres 01 = reserved 10 = 2 x8 PCI Express 11 = 1 x16 PCI Express CFG[7] :PEG DEFER TRAINING 1: (Default) PEG Train immediately following RESETB deassertion 0: PEG Wait for BIOS for training
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION CPU-6/6
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
28
1
X01 of
80
7
8
6
5
4
3
2
1
F
F
ODT1
DQ37 DQ38
DM0
DQ39
DM1
DQ40
DM2
DQ41
DM3
DQ42
DM4
DQ43
DM5
DQ44
DM6
DQ45
DM7
DQ46 DQ47
DQS0
DQ48
DQS1
DQ49
DQS2
DQ50
DQS3
DQ51
DQS4
DQ52
DQS5
DQ53
DQS6
DQ54
DQS7
DQ55
DQS#0
DQ56
DQS#1
DQ57
DQS#2 DQS#3
DQ58 DQ59
DQS#4
DQ60
DQS#5
DQ61
DQS#6
DQ62
DQS#7
DQ63
10UF_6.3V_3 10UF_6.3V_3
1
10UF_6.3V_3 C4109 2 1
2 1 2
1UF_6.3V_2 C4107 2 1
1 2
10UF_6.3V_3
C4115 C4112
1 2
1UF_6.3V_2
1 2
1
10UF_6.3V_3
C4118 C4116
1 2
1UF_6.3V_2
C4117
C4113 2 1
10UF_6.3V_3
1 +
C4106
2
330UF_2.5V
1 C4148 2
1
1 2
C4147
C4146 2
NOTE: IF SA0_DIM0=0 , SA1_DIM0=0 SO-DIMMA SPD ADDRESS IS 0XA0 SO-DIMMA TS ADDRESS IS 0X30 IF SA0_DIM0=1 , SA1_DIM0=0 SO-DIMMA SPD ADDRESS IS 0XA2 SO-DIMMA TS ADDRESS IS 0X32
IN
SA0_DIM0
29
IN
SA1_DIM0
29
VSS30 VSS31
VDD17
VSS32
VDD18
VSS33 VSS34
VDDSPD
VSS35 VSS36
NC1 NC2
VSS37 VSS38
NCTEST
VSS39
198 30
EVENT#
VSS41
RESET#
VSS42
1 126
VREF_DQ
VSS45
VREF_CA
VSS46
VSS40
VSS44
VSS47
2 3 8 9 13 14 19 20 25 26 31 32 37 38 43
VSS48 VSS1
VSS49
VSS2
VSS50
VSS3
VSS51
VSS4
VSS52
E
VSS5 VSS6
P0V75S
VSS7 VSS8 VSS9 VSS10
VTT1
VSS11
VTT2
VSS12 VSS13
G1
VSS14
G2
203 204 G1 G2
VSS15
D
FOX_AS0A626_U4RG_7H_204P
P0V75S
2
2
FOX_AS0A626_U4RG_7H_204P
VSS29
VDD16
VSS43
P0V75M_VREF
P3V3S
VSS28
VDD15
1
DQ36
VDD14
2
ODT0
VSS27
VDD13
1UF_6.3V_2
DQ34 DQ35
VSS26
VDD12
1
SDA
VSS25
VDD11
C4101
DQ33
31 23 30
VSS23 VSS24
VDD10
2
SCL
P0V75M_VREF
VSS22
VDD8 VDD9
1UF_6.3V_2
DQ32
VSS21
VDD7
1
DQ31
SA1
VSS20
VDD6
C4102
DQ30
SA0
VDD5
44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196
2
DQ29
WE#
VSS19
1UF_6.3V_2
RAS#
PM_EXTTS#1_R OUT DDR3_DRAMRST# OUT
VSS18
VDD4
1
DQ28
VSS17
VDD3
C4103
CAS#
VSS16
VDD2
C4100
DQ27
VDD1
1UF_6.3V_2
CKE1
1
DQ26
C4110
CKE0
77 122 125
P3V3S
2
DQ24 DQ25
199
0.1UF_16V_2
CK1 CK1#
C4114
DQ23
C4108
CK0#
2
DQ22
1UF_6.3V_2
DQ21
CK0
2.2UF_6.3V_3
S1#
1
DQ20
2
S0#
0.1UF_16V_2
DQ19
1
BA2
C4111
DQ18
2
BA1
C4119
DQ17
1
BA0
2
DQ15 DQ16
2.2UF_6.3V_3
A15
C4120
DQ14
2.2UF_6.3V_3
A14
12PF_50V_2
DQ13
0.1UF_16V_2
A13
1
DQ12
2
DQ11
A12
3PF_50V_2
A11
C4104
DQ9
1
DQ8 DQ10
2
DQ7
A10_AP
2.2UF_6.3V_3
A9
75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124
0_5%_2
A8
1
A7
C4105
DQ6
C4149
DQ5
CN4100
2
A5 A6
M_A_DQ
12PF_50V_2
DQ4
BI
4 5 2 7 0 1 3 6 13 9 11 15 8 12 10 14 21 20 22 18 16 17 19 23 24 29 26 31 30 28 27 25 36 35 37 38 32 33 39 34 41 42 45 43 40 44 46 47 52 54 50 55 48 49 51 53 63 60 59 61 57 56 62 58
1
12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
A4
5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194
R4100
D
M_A_DQS0_DP M_A_DQS1_DP M_A_DQS2_DP M_A_DQS3_DP M_A_DQS4_DP M_A_DQS5_DP M_A_DQS6_DP M_A_DQS7_DP M_A_DQS0_DN M_A_DQS1_DN M_A_DQS2_DN M_A_DQS3_DN M_A_DQS4_DN M_A_DQS5_DN M_A_DQS6_DN M_A_DQS7_DN
DQ3
2
25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25
DQ2
A3
1
11 28 46 63 136 153 170 187
DQ1
A2
R4103
M_ODT0 IN M_ODT1 IN
116 120
DQ0
A1
2
25 25
109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200
A0
10K_5%_2_DY
M_A_BS0 M_A_BS1 M_A_BS2 M_CS#0 25 M_CS#1
98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78
1
56 47 34 32 47 56 34 32
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IN IN IN IN IN IN 25 M_CLK_DDR0_DP IN 25 M_CLK_DDR0_DN IN 25 M_CLK_DDR1_DP IN 25 M_CLK_DDR1_DN 25 M_CKE0 IN 25 M_CKE1 IN 25 M_A_CAS# IN 25 M_A_RAS# IN 25 M_A_WE# IN 29 SA0_DIM0 OUT 29 SA1_DIM0 OUT PCH_3S_SMCLK IN PCH_3S_SMDATA IN 25 25 25 25
E
BI
R4101
M_A_A
P1V5
25
CN4100
0_5%_2
25
C
C
B
B
REFERENCE NUMBER:4100~4299
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION DDR3_SO-DIMM0
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
29
1
X01 of
80
7
8
6
5
4
3
2
1
DDR3_B_0 U4104 32 31 32 32 32
31 30 31 31 31
30 29 30 30 30
25 23 25 25 25
IN IN IN IN IN
32 32 32
31 31 31
30 30 30
25 25 25
IN IN IN
F
M_CS#2 DDR3_DRAMRST# M_B_RAS#
M_B_CAS# M_B_WE#
L2 T2 J3 K3 L3
C\S\
DQL0
R\E\S\E\T\
DQL1
R\A\S\
DQL2
C\A\S\
DQL3
W\E\
DQL4 DQL5 DQL6 DQL7
M_CLK_DDR2_DP M_CLK_DDR2_DN M_CKE2
J7 K7 K9
C\K\ CKE
DQ8 DQ9 DQ10
DQ12 DQ13
D3 E7
UDM
DQ14
LDM
DQ15
B7 C7
U\D\Q\S\
A1
UDQS
A2
M_B_DQS1_DN M_B_DQS1_DP
A3 A4 A5
25 25
IN IN
M_B_DQS0_DP M_B_DQS0_DN
F3 G3
LDQS L\D\Q\S\
A6 A7 A8 A9 A10/AP
R4116 1
32
31
30
IN
25
2
M_ODT2
K1 L8
ODT ZQ
A11 A12/B\C\ A13
240_1%_1
A14
E
A15
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
1 C4
1UF_6.3V_2
VSS_2
BA0
VSS_3
BA1
VSS_4
1 C4142 2
10UF_6.3V_3
10UF_6.3V_3
1 2
1 C4140 2
C4141
10UF_6.3V_3
10UF_6.3V_3
1 2
1 C4138 2
C4139
10UF_6.3V_3
1 2
1
10UF_6.3V_3
C4137
C4136 2
10UF_6.3V_3
1 C4135 2
10UF_6.3V_3
M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
BA2
M_B_BS0 M_B_BS1 M_B_BS2
IN IN IN
25 25 25
30 30 30
31 31 31
32 32 32
E
P1V5
VSS_6 VSS_7
VDD_1
VSS_8
VDD_2
VSS_9
VDD_3
VSS_10
VDD_4
VSS_11
VDD_5
VSS_12
VDD_6
B2 D9 G7 K2 K8 N1 N9 R1 R9
VSSQ_1
VDD_9
VSSQ_2 VSSQ_3 VSSQ_4
A1 A8 C1 C9 D2 E9 F1 H2 H9
VDDQ_1
VSSQ_5
VDDQ_2
VSSQ_6
VDDQ_3
VSSQ_7
VDDQ_4
VSSQ_8
VDDQ_5
VSSQ_9
VDDQ_6 VDDQ_7
D
25 25 25 25 25 25 25 25
VSS_5
VDD_8
VDDQ_8
J1 J9 L1 L9
BI BI BI BI BI BI BI BI
M2 N8 M3
VDD_7
B1 B9 D1 D8 E2 E8 F9 G1 G9
D7 M_B_DQ C3 M_B_DQ C8M_B_DQ C2M_B_DQ A7 M_B_DQ A2 M_B_DQ B8 M_B_DQ A3 M_B_DQ
F
VSS_1
2
C3
1UF_6.3V_2
2
C2
1UF_6.3V_2
2
C1
1UF_6.3V_2
1
1
1
C4121
1UF_6.3V_2
2
2
2
1
C4122
1UF_6.3V_2
2
C4123
1UF_6.3V_2
1UF_6.3V_2
2
C4124
1
1
1
P1V5
25 25 25 25 25 25 25 25
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7
A0
IN IN
BI BI BI BI BI BI BI BI
CK
DQ11
25 25
E3 M_B_DQ F7 M_B_DQ F2 M_B_DQ F8 M_B_DQ H3 M_B_DQ H8 M_B_DQ G2 M_B_DQ H7 M_B_DQ
NC_1
VDDQ_9
P0V75M_VREF
NC_2
D
NC_3 NC_4/ZQ1
H1 M8
VREFDQ VREFCA
MICRON_MT41K512M16_FBGA_96P
DDR3_B_1 1
1 1UF_6.3V_2
2
1UF_6.3V_2
1UF_6.3V_2
C4153
C4154
1UF_6.3V_2
2
C4152
2
C4151
2
1UF_6.3V_2
1
1
C4150
2
1UF_6.3V_2
2
2
1
C4145
2
C4144
1UF_6.3V_2
1UF_6.3V_2
1
1
1
U4105 C4143
32 31 32 32 32
31 30 31 31 31
30 29 30 30 30
25 23 25 25 25
IN IN IN IN IN
32 32 32
31 31 31
30 30 30
25 25 25
IN IN IN
M_CS#2 DDR3_DRAMRST# M_B_RAS#
M_B_CAS# M_B_WE#
L2 T2 J3 K3 L3
C\S\
DQL0
R\E\S\E\T\
DQL1
R\A\S\
DQL2
C\A\S\
DQL3
W\E\
DQL4 DQL5 DQL6 DQL7
C
M_CLK_DDR2_DP M_CLK_DDR2_DN M_CKE2
J7 K7 K9
C\K\ CKE
DQ8 DQ9
DQ11 DQ12 DQ13
D3 E7
UDM
DQ14
LDM
DQ15
B7 C7
U\D\Q\S\
A1
UDQS
A2
A0
IN IN
M_B_DQS3_DN M_B_DQS3_DP
A3 A4 A5
25 25
IN IN
M_B_DQS2_DP M_B_DQS2_DN
F3 G3
LDQS L\D\Q\S\
A6 A7 A8 A9 A10/AP
R2 1
32
2
31
30
25
IN
M_ODT2
K1 L8
ODT ZQ
A11 A12/B\C\ A13
240_1%_1
A14 A15
B
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
C4126
C4125
1
1
1
1
P0V75M_VREF
C4128
C4127 0.1UF_16V_2
0.1UF_16V_2
VSS_2
BA0
VSS_3
BA1
VSS_4
BA2
VSS_7
M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ
BI BI BI BI BI BI BI BI
25 25 25 25 25 25 25 25
C
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7
M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A
M2 N8 M3
M_B_BS0 M_B_BS1 M_B_BS2
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI IN IN IN
25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
B 25 25 25
30 30 30
31 31 31
32 32 32
P1V5
B2 D9 G7 K2 K8 N1 N9 R1 R9
VDD_1
VSS_8
VDD_2
VSS_9
VDD_3
VSS_10
VDD_4
VSS_11
VDD_5
VSS_12
VDD_6
VSSQ_1
VDD_9
VSSQ_2 VSSQ_3 VSSQ_4
VDDQ_1
VSSQ_5
VDDQ_2
VSSQ_6
VDDQ_3
VSSQ_7
VDDQ_4
VSSQ_8
VDDQ_5
VSSQ_9
VDDQ_6
A1 A8 C1 C9 D2 E9 F1 H2 H9
VDDQ_7 VDDQ_8
A
D7 C3 C8 C2 A7 A2 B8 A3
VSS_6
VDD_8
J1 J9 L1 L9
25 25 25 25 25 25 25 25
VSS_5
VDD_7
B1 B9 D1 D8 E2 E8 F9 G1 G9
BI BI BI BI BI BI BI BI
VSS_1
2
2
0.1UF_16V_2
2
2
0.1UF_16V_2
M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ
CK
DQ10
25 25
E3 F7 F2 F8 H3 H8 G2 H7
NC_1
VDDQ_9
NC_2
P0V75M_VREF
A
NC_3 NC_4/ZQ1
H1 M8
VREFDQ VREFCA
INVENTEC TITLE
MODEL,PROJECT,FUNCTION
MICRON_MT41K512M16_FBGA_96P
35_DDR3L-2
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
30
1
X01 of
80
7
8
6
5
4
3
2
1
DDR3L_B_2 U4106 32 31 32 32 32
F
30 29 30 30 30
31 30 31 31 31
M_CS#2
IN IN IN IN IN
25 23 25 25 25
L2 T2 J3 K3 L3
DDR3_DRAMRST# M_B_RAS#
M_B_CAS# M_B_WE#
C\S\
DQL0
R\E\S\E\T\
DQL1
R\A\S\
DQL2
C\A\S\
DQL3
W\E\
DQL4 DQL5 DQL6 DQL7
32 32 32
31 31 31
30 30 30
M_CLK_DDR2_DP M_CLK_DDR2_DN M_CKE2
IN IN IN
25 25 25
J7 K7 K9
DQ8 DQ9
CKE
DQ10
DQ12 DQ13
D3 E7
UDM
DQ14
LDM
DQ15
B7 C7
U\D\Q\S\
A1
UDQS
A2
A0
IN IN
M_B_DQS5_DN M_B_DQS5_DP
A3 A4 A5
25 25
IN IN
M_B_DQS4_DP M_B_DQS4_DN
F3 G3
A6
LDQS
A7
L\D\Q\S\
A8 A9 A10/AP
R6
32
1
31
30
25
2
M_ODT2
IN
K1 L8
A11
ODT
A12/B\C\
ZQ
A13
240_1%_1
E
A14 A15
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
BI BI BI BI BI BI BI BI
25 25 25 25 25 25 25 25
D7 C3 C8 C2 A7 A2 B8 A3
M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ
BI BI BI BI BI BI BI BI
25 25 25 25 25 25 25 25
F
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7
M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
E
VSS_1 BA0
VSS_2
BA1
VSS_3
BA2
VSS_4
M2 N8 M3
M_B_BS0 M_B_BS1 M_B_BS2
IN IN IN
25 25 25
30 30 30
31 31 31
32 32 32
VSS_5
P1V5
VSS_6 VSS_7
VDD_1
VSS_8
VDD_2
VSS_9
VDD_3
VSS_10
VDD_4
VSS_11
VDD_5
VSS_12
VDD_6 VDD_7 VDD_8
B1 B9 D1 D8 E2 E8 F9 G1 G9
VDD_9
VSSQ_1
B2 D9 G7 K2 K8 N1 N9 R1 R9
VSSQ_2 VSSQ_3 VSSQ_4
VDDQ_1
VSSQ_5
VDDQ_2
VSSQ_6
VDDQ_3
VSSQ_7
VDDQ_4
VSSQ_8
VDDQ_5
VSSQ_9
VDDQ_6 VDDQ_7 VDDQ_8
J1 J9 L1 L9
D
M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ
CK C\K\
DQ11
25 25
E3 F7 F2 F8 H3 H8 G2 H7
NC_1
VDDQ_9
A1 A8 C1 C9 D2 E9 F1 H2 H9
D
P0V75M_VREF
NC_2 NC_3 NC_4/ZQ1
VREFDQ VREFCA
H1 M8
MICRON_MT41K512M16_FBGA_96P
DDR3L_B_3 U4107 32 31 32 32 32
31 30 31 31 31
30 29 30 30 30
25 23 25 25 25
M_CS#2
IN IN IN IN IN
DDR3_DRAMRST# M_B_RAS#
M_B_CAS# M_B_WE#
L2 T2 J3 K3 L3
C\S\
DQL0
R\E\S\E\T\
DQL1
R\A\S\
DQL2
C\A\S\
DQL3
W\E\
DQL4 DQL5 DQL6 DQL7
C
32 32 32
30 30 30
31 31 31
25 25 25
M_CLK_DDR2_DP M_CLK_DDR2_DN M_CKE2
IN IN IN
J7 K7 K9
C\K\
DQ8
CKE
DQ9
DQ11 DQ12 DQ13
D3 E7
UDM
DQ14
LDM
DQ15
B7 C7
U\D\Q\S\
A1
UDQS
A2
A0
M_B_DQS7_DN M_B_DQS7_DP
IN IN
A3 A4
P0V75M_VREF
A5
25 25
M_B_DQS6_DP M_B_DQS6_DN
IN IN
F3 G3
A6
LDQS
A7
L\D\Q\S\
A8 A9 A10/AP
R5
C4129
C4130
2
31
30
25
IN
M_ODT2
K1 L8
ODT
A11
ZQ
A12/B\C\
1
1
1
1
1
32
C4131
A13
240_1%_1
C4132
A14 A15
B
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
0.1UF_16V_2
2
0.1UF_16V_2
2
0.1UF_16V_2
2
2
0.1UF_16V_2
VSS_2
BA0
VSS_3
BA1
VSS_4
BA2
D7 C3 C8 C2 A7 A2 B8 A3
M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ
BI BI BI BI BI BI BI BI
25 25 25 25 25 25 25 25
C
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7
M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A M_B_A
M2 N8 M3
M_B_BS0 M_B_BS1 M_B_BS2
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
IN IN IN
25 25 25
30 30 30
31 31 31
32 32 32
B
P1V5
VSS_6 VSS_7
VDD_1
VSS_8
VDD_2
VSS_9
VDD_3
VSS_10
VDD_4
VSS_11
VDD_5 VDD_6
VSS_12
VDD_9
VSSQ_1
B2 D9 G7 K2 K8 N1 N9 R1 R9
VSSQ_2 VSSQ_3 VSSQ_4
VDDQ_1
VSSQ_5
VDDQ_2
VSSQ_6
VDDQ_3
VSSQ_7
VDDQ_4
VSSQ_8
VDDQ_5
VSSQ_9
VDDQ_6 VDDQ_7 VDDQ_8
A
25 25 25 25 25 25 25 25
VSS_5
VDD_8
J1 J9 L1 L9
BI BI BI BI BI BI BI BI
VSS_1
VDD_7
B1 B9 D1 D8 E2 E8 F9 G1 G9
M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ
CK
DQ10
25 25
E3 F7 F2 F8 H3 H8 G2 H7
VDDQ_9
NC_1
A1 A8 C1 C9 D2 E9 F1 H2 H9
NC_2
P0V75M_VREF
A
NC_3 VREFDQ
NC_4/ZQ1
VREFCA
INVENTEC
H1 M8 TITLE
MODEL,PROJECT,FUNCTION
MICRON_MT41K512M16_FBGA_96P
36_DDR3L-3
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
31
1
X01 of
80
8
7
6
5
4
3
2
1
P0V75S
1
F
1 1 1
1 1 1
R4227 R4228 R4229
R4230 R4231 R4232
R4233 R4234 R4235
36_1%_2 2
M_CKE2
IN
25
30
31
36_1%_2 2
M_ODT2
IN
25
30
31
36_1%_2 2
M_CS#2
IN
25
30
31
36_1%_2 2
M_B_WE#
IN
25
30
31
36_1%_2 2
M_B_CAS#
IN
25
30
31
36_1%_2 2
M_B_RAS#
IN
25
30
31
36_1%_2 2
M_B_BS0
IN
25
30
31
36_1%_2 2
M_B_BS1
IN
25
30
31
36_1%_2 2
M_B_BS2
IN
25
30
F
31
BI 1 1 1 1
R4236 R4237 R4238 R4239
36_1%_2 2
M_B_A
0
36_1%_2 2
M_B_A
1
36_1%_2 2
M_B_A
2
36_1%_2 2
M_B_A
3
36_1%_2 2
M_B_A
4
36_1%_2 2
M_B_A
5
36_1%_2 2
M_B_A
6
36_1%_2 2
M_B_A
7
36_1%_2 2
M_B_A
8
36_1%_2 2
M_B_A
9
M_B_A
31
1 1 1 1 1 1 1 1
D 1
IN
R4251
M_CLK_DDR2_DP
1
2
E 30_1%_2
C4203
R4242
1.6PF_25V_1
R4243 R4244 R4245
31
30
25
IN
M_CLK_DDR2_DN
R4252 1
2 30_1%_2
R4246 R4247
36_1%_2 2
M_B_A
10
36_1%_2 2
M_B_A
11
36_1%_2 2
M_B_A
12
36_1%_2 2
M_B_A
13
36_1%_2 2
M_B_A
14
36_1%_2 2
M_B_A
15
C4202
1
R4241
25
2
1
30
1
1
R4240
2
E
1
1
R4248 R4249 R4225
0.1UF_16V_2
1
D
R4226
2
2
1
C4207
1UF_6.3V_2
C4206
1UF_6.3V_2
2
C4208
1UF_6.3V_2
2
C4209
1UF_6.3V_2
1
1
1
P0V75S
C
C
C4211
C4210
1UF_6.3V_2_DY
2
1UF_6.3V_2_DY
2
2
1
C4214
1UF_6.3V_2_DY
1UF_6.3V_2_DY
2
C4215
1
1
1
P0V75S
B
B
U4201 A0
VCC
A1
WP
A2
SCL
VSS
SDA
8 7 6 5
0.1UF_16V_2
1 C4213 2
1 R4263 2
10K_5%_2 10K_5%_2_DY
1 R4262 2
10K_5%_2_DY 10K_5%_2
1 R4265 2
1 R4264 2
1 2 3 4
2.2UF_6.3V_2 C4212 2 1
P3V3S
SPD ADDRESS=30 HEX FOR MEMORY DOWN A 56 47
56 47
1
SMB_CLK_MD_A SMB_DATA_MS_A
R4259
34
34
BI
29
BI
29
PCH_3S_SMCLK
1
R4260
2
SMB_CLK_MD_A
0_5%_2
PCH_3S_SMDATA 1
R4261
2 SMB_DATA_MS_A
0_5%_2
2
0_5%_2
ATM_AT24C02B_10TU_1_8_TSSOP_8P
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION 37_DDR TERMAINAL
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
32
1
X01 of
80
8
7
6
5
4
3
REFERENCE NUMER : 4700~4949
2
1
LAYOUT NOTE:JTAG_TMS TERMINATIONS NEED TO BE PLACED NEAR PCH 8/22 LAYOUT NOTE:JTAG_TDI TERMINATIONS NEED TO BE PLACED NEAR PCH LAYOUT NOTE:JTAG_TDO TERMINATIONS NEED TO BE PLACED NEAR XDP
P3V3A
1R4842
C17
INTVRMEN
1 R4910 2 N34 33_5%_2 L34
HDA_SYNC
33 A_3S_ICHSPKR
OUT
A_3S_ICHSPKR
OUT
AZ_R3S_RST# 33
SERIRQ
1 R4861
SATA0RXN
T10
SPKR HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
IN
HDA_SDO_R
HDD_HALTLED 33
ISO_PREP# OUT
IN
PCH_TCK
33
PCH_TMS
33
1 1
IN
33
SATA2TXP
HDA_DOCK_EN#/GPIO33
SATA4RXN SATA4RXP SATA4TXN SATA4TXP
PCH_TCK IN
PCH_TCK
J3
JTAG_TCK
33
PCH_TMS IN
PCH_TMS
H7
JTAG_TMS
33
PCH_TDI
PCH_TDI
K5
JTAG_TDI
33
PCH_TDO OUT
PCH_TDO
H1
JTAG_TDO
51_5%_2
IN
JTAG
33
2
3
OUT
48
SPI_CS0#_FLH
IN
HDA_SDO_R
R4911 2 R_SPI_CLK_FLH 33_5%_2 1 R4894 2 R_SPI_CS0#_FLH 33_5%_2 TP716
48
SPI_SI_FLH
OUT
48
SPI_SO_FLH
IN
1
R4895 2 33_5%_2
T3
SPI_CLK
Y14
SPI_CS0#
1 T1
SPI_CS1#
1 R4891 2 1 R4889 2
100_1%_2_DY
100_1%_2_DY 210_1%_2_DY
1
210_1%_2_DY
R4886 2 1 R4885
1
P3V3S
50
R4912 0_5%_2
IN IN OUT OUT
SATA_RX0_C_DN SATA_RX0_C_DP SATA_TX0_C_DN SATA_TX0_C_DP
IN IN OUT OUT
SATA_RX1_C_DN SATA_RX1_C_DP SATA_TX1_C_DN SATA_TX1_C_DP
33
48
50
44 44 44 44
C
SATA HDD 44 44 44 44
MSATA
AB8 AB10 AF3 AF1 Y7 Y5 AD3 AD1
Y11
SATAICOMPI
Y10
SATA3RBIAS
V4 U3
B
P1V05S_VCCP
L2 MAX. = 100 MILS1R4851
2 37.4_1%_2
L1 MAX. = 500 MILS P1V05S_VCCP
AB12 AB13 L2
MAX. = 100 MILS1R4852
2 49.9_1%_2
1R4821 2 750_1%_2 PLACE CLOSE TO PCH 2 R4816 1 0_5%_2
L1 MAX. = 500 MILS
AH1
P3
SPI_MOSI
SATA0GP/GPIO21
V14
SPI_MISO
SATA1GP/GPIO19
P1
P3V3S
LED_3S_SATA# 1
56 LED_3S_SATA#
OUT
R4907 2 0_5%_2
NOTE: IMPEDANCE TARGET : 50 +/- 15% OHM AVOID ROUTING COMP SIGNALS NEXT TO CLOCK PINS.
33
P3V3S
OUT
A
GPIO19
ITL_PANTHERPOINT_FCBGA_989P
IN
RSMRST#
1
IN
PWR_BTN_OUT#35
1
IN
SRTCRST#
1
IN
PM_PWROK48
1
IN
20 M_PWROK35
18 35 48
P3V3A ISO_PREP# 1R4905
48 49
2
0_5%_2 35
Q4750 57
1
IN
VGATE
1
IN
INTVRMEN_R
35
AZ_R3S_SYNC
1 R4903 2 33_5%_2
OUT
2
3
INVENTEC OUT
HDA_SYNC 33
TITLE
MODEL,PROJECT,FUNCTION G
18
R4911,R4894,R4895,R4882 CLOSE TO PCH
R4904 2 1 1K_5%_2
1
BSS138
P5V0S
PANTHER POINT_1/9
SIZE A3
CHANGE by
8
7
6
5
4
D
AD7 AD5 AH5 AH4
SATA5TXP
SATALED#
R_SPI_SI_FLH
48
OUT
33
1
50 50 50 50
OUT PCI_3S_SERIRQ
AM10 AM8 AP11 AP10
SATAICOMPO
SATA3COMPI
SPI_CLK_FLH
D36 LPC_3S_FRAME#
AM3 AM1 AP7 AP5
48 48 48 48
BI BI BI BI
E36 K36 R4906 1 2 10K_5%_2_DY V5 PCI_3S_SERIRQ
Y3 Y1 AB3 AB1
SATA3RCOMPO
48
LPC_3S_AD(0) LPC_3S_AD(1) LPC_3S_AD(2) LPC_3S_AD(3)
HDA_DOCK_RST#/GPIO13
SPI
PCH_TDO 33
SATA2TXN
C38 A38 B37 C37
1
TP4707 TP30 TP4708 TP30 TP4709 TP30 TP4710 TP30 TP4711 TP30 TP4712 TP30 TP4713 TP30
PCH_TDI
IN
SATA2RXP
D
23
R4867
S
A
IN
1
SATA1TXP SATA2RXN
SATA5TXN
1
OUT
1
1 R4866 2C36 1K_5%_2 ISO_PREP# N32
PLACE R4867 NEAR PCH
G
LES_LBSS84LT1G_SOT23_3P
TP4701 TP30 TP4702 TP30 TP4703 TP30 TP4704 TP30
SATA1TXN
SATA5RXP
S
1
IN
SATA1RXP
SATA5RXN
D
PLT_RST#
SATA1RXN
SATA3RXP
HDA_SDO
HDD_HALTLED
OUT
Q4754 37
SATA0TXP
SATA3TXP
56
LES_LBSS84LT1G_SOT23_3P
51
SATA0TXN
SATA3TXN
33 55 52
72
SATA0RXP
SATA3RXN
1R4863 21 44G 0_5%_2
IN
LDRQ0# LDRQ1#/GPIO23
HDA_BCLK
1R4901 2 33_5%_2 K34
AZ_R3S_SDIN0
IN
AZ_R3S_SDIN0
33
S
BAT_GRNLED#
FWH4/LFRAME#
SATA 6G
HDA_SYNC
D
B
48
2 R4806
INTRUDER#
Q4755 56
PCH_TDI PCH_TMS PCH_TDO
2 SRTCRST#
FWH3/LAD3
LPC
RTCRST#
FWH2/LAD2
RTC
D20
K22
1K_5%_2
2 2
2
SSM3K7002FU
OUT OUT OUT
2
FWH0/LAD0
SATA
54 33
3 S
G
AZ_R3S_BITCLK
OUT
57
P3V3A
OUT
INTRUDER#
D
1 R4831
1M_5%_2
RTCX2
INTRUDER#
OUT
INTVRMEN_R
OUT
AZ_R3S_RST#
33 57
P3V3_RTC
2
4 3
1
33 AZ_R3S_BITCLK
57
1R4880 2 A_3S_ICHSPKR 10K_5%_2_DY
1
INTRUDER#
2 330K_5%_2
33
WWAN_DET# IN
RTCX1
FWH1/LAD1
18PF_50V_2
33
P3V3S
Q4831
U4701
A20 C20
IHDA
57
33 33 33 33
1
22PF_50V_2
C
X4750 32.768KHZ C4788 1 2
SRTCRST# G22 54
C4836 2
2
18PF_50V_2
2 R4862 1 10M_5%_2
1
C4764 2
2 R4833 1 1M_5%_2
A1
1 1K_5%_2
1
1UF_6.3V_2 C4768 2
20K_5%_2
R4832
HDA_SDO_R
C4767
1 2
1
20K_5%_2 1R4834 2
1
2
IN
BSS138
2
1UF_6.3V_2 1R4845 2
3
C
D4750 BAT54C
3
1
C4766 1
1UF_6.3V_2
A2
D
P3V3AL_RTC_BAT
2
P5V0S
2
ACES_50224_0020N_001_2P
R4868 1 33_5%_2 2
OUT
AZ_R3S_SDOUT
1
57
G
P3V3_RTC P3V3AL
R4807
Q4762
3 4
TP4800
G
TP30
G
S
1 2
D
1 2
2
1
CN4750
100_1%_2_DY 210_1%_2_DY
PLACEMENT NOTE
P3V3AL_RTC_BAT
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER 1310xxxxx-0-0 SHEET
33
of
80
1
REV X01
8
7
6
5
4
3
2
1
REFERENCE NUMER : 4700~4949 U4701
GPIO18 R4702 1 2 0_5%_2
1
PERN1 PERP1 PETP1
BE34 BF34 BB32 AY32
CMNID1
SMBALERT#/GPIO11
PETN1
PERN2 PERP2 PETN2 PETP2
H14 PCH_3A_SMCLK
SMBDATA
C9 PCH_3A_SMDATA 2
SML0ALERT#/GPIO60
60 60
R4810 1
2 CLKREQ_PCIE_CARD# 0_5%_2 WLAN R4855 1 2 CLKREQ_WLAN#
53 53 53
0_5%_2 R4797 1 2 PCH_3M_SMCLK 2.2K_5%_2 R4884 1 2 PCH_3M_SMDATA 2.2K_5%_2 R4864 1 2
51 51 51 51
NIC
GPIO44
R4896
GPIO56
1 2 10K_5%_2_DY
GPIO73
53 PCIE_RX4_C_DN PCIE_RX4_C_DP PCIE_TX4_C_DN PCIE_TX4_C_DP
IN IN OUT OUT
1 C4816 1 C4811
1 C4819 1 C4818
2 0.1UF_16V_2 2 0.1UF_16V_2
2 0.1UF_16V_2 2 0.1UF_16V_2
PCIE_TX3_DN PCIE_TX3_DP
BG36 BJ36 AV34 AU34
PCIE_TX4_DN PCIE_TX4_DP
BF36 BE36 AY34 BB34
PERN3 PERP3 PETP3 PERN4 PERP4 PETN4 PETP4
IN IN OUT OUT
PCIE_RX6_C_DN PCIE_RX6_C_DP PCIE_TX6_C_DN PCIE_TX6_C_DP
1 C4820 1 C4817
PCIE_TX6_DN PCIE_TX6_DP
2 0.1UF_16V_2 2 0.1UF_16V_2
SML0DATA
G12 PCH_3M_SMDATA
SML1ALERT#/PCHHOT#/GPIO74
BJ38 BG38 AU36 AV36
5
G2
D1 D2
B
6 PCH_KBC_SMCLK 3 PCH_KBC_SMDATA
4 PCH_SML1DATA 1 S2 R4827 2N7002DW
2 2.2K_5%_2
2 R4913
1 2.2K_5%_2
P3V3S
R4835 2
1 Q4752 G1
5
G2
D1 D2
0_5%_2_DY
1 PCH_3S_SMCLK
S1
2
IN
PETN6
4 PCH_3S_SMDATA
PERN7 PERP7 PETN7 PETP7 PERN8 PERP8
E14 PCH_SML1CLK
M16PCH_SML1DATA
I2C_CLK
R4836
32 29 34 47
PCH_3S_SMDATA 2
IN
0_5%_2_DY 2 1 R4828 2.2K_5%_2
60 60
I2C_DATA P3V3S
56
34 60
CLK_PCIE_CARD_DN CLK_PCIE_CARD_DP
CLKREQ_PCIE_CARD#
32 34 29 56 47
34 53
55
2 R4837
Y43 Y45
CLKREQ_WLAN#L12
CLK_PEG_DN CLK_PEG_DP
2.2K_5%_2
P3V3S Q4756
A
2 5
S1
1
D1 D2
6 3
G1
2 R4843
P3V3AL
4 2N7002DW
GPIO56 THERM_CLK
OUT
CL_RST#1
51
1
2 R4838
51
P3V3AL 1
IN IN
48 73
PCH_KBC_SMCLK PCH_KBC_SMDATA
34 48 73
51 34
CLK_PCIE_LAN_DN CLK_PCIE_LAN_DP 38
34
CLKREQ_LAN#
CLKREQ_LAN#
IN
GPIO46
2.2K_5%_2
2 R4844
AB42 AB40 E6
T13 V38 V37
I213
P3V3S
L14
V40 V42
OUT OUT
IN
THERM_DATA
22 47
TP30 TP30
1
TP830 TP831
1 1
K12 AK14 AK13
2.2K_5%_2
34 53
53 34 53
P3V3A
M10
CLKOUT_PEG_A_P
R4890 2 0_5%_2 R4899 1 2 10K_5%_2_DY
C
CLKOUT_PCIE1N
CLKOUT_DMI_N
CLKOUT_PCIE1P
CLKOUT_DMI_P
AB37 AB38
AV22 AU22
CLKOUT_PCIE2N
OUT OUT
23
CLK_DMI_PCH_DN CLK_DMI_PCH_DP
23
CLKOUT_PCIE2P PCIECLKRQ2#/GPIO20
CLKOUT_PCIE3N CLKOUT_PCIE3P
AM12 AM13
BF18 BE18
1R4823 1 R4820
2 0_5%_2 2 0_5%_2
BJ30 BG30
1R4878 1 R4876
2 0_5%_2 2 0_5%_2
G24 E24
1R4859 1 R4860
2 0_5%_2 2 0_5%_2
CLKIN_SATA_P
AK7 AK5
1R4853 1 R4817
2 0_5%_2 2 0_5%_2
REFCLK14IN
K45
1R4893
2
CLKIN_DMI_N CLKIN_DMI_P
CLKIN_GND1_N CLKIN_GND1_P
PCIECLKRQ3#/GPIO25
CLKOUT_PCIE4N CLKOUT_PCIE4P CLKIN_SATA_N PCIECLKRQ4#/GPIO26
CLKOUT_PCIE5N
B
0_5%_2
CLKOUT_PCIE5P PCIECLKRQ5#/GPIO44
CLKIN_PCILOOPBACK
H45 CLK_R3S_PCH_FB
CLKOUT_PEG_B_N
XTAL25_IN
CLKOUT_PEG_B_P
XTAL25_OUT
V47 XTAL25_IN V49 XTAL25_OUT
XCLK_RCOMP
Y47
IN
CLKOUT_PCIE6N
37 34 CLK_R3S_PCH_FB
C4828 1
P1V05S_VCCP
PEG_B_CLKRQ#/GPIO56
47 22
2.2K_5%_2
G2 S2
IN
34
PCIECLKRQ1#/GPIO18
V45 V46
P3V3S
CL_CLK1
P10 CL_RST#1
CLKOUT_PEG_A_N
CLKREQ_PCIE_CARD# A8
1
BI
34
1
PCIECLKRQ0#/GPIO73
Y37 Y36
GPIO44
PCH_SML1DATA
CLKOUT_PCIE0P
J2
OUT OUT
CLKREQ_WLAN# IN
PCH_SML1CLK
BI
CL_RST1#
CLKOUT_PCIE0N
V10
OUT OUT
BI
34 CL_DATA1
CLKIN_DOT_96P
CLK_PCIE_WLAN_DN CLK_PCIE_WLAN_DP
51 34
D
BI
CLKIN_DOT_96N
53
PCH_3M_SMDATA
T11 CL_DATA1
PETP8
IN
IN
BI
CL_DATA1
CLKOUT_DP_P
55
51 34
PCH_3M_SMCLK
M7 CL_CLK1
CLKOUT_DP_N
GPIO20
34 23
PCH_DDR_RST
BI
CL_CLK1
PETN8
AA48 AA47
P3V3S
PCH_3S_SMCLK
IN
S2
1
IN
OUT
OUT
PETP6
M1
P3V3A
2.2K_5%_2 2 R4830 1 P3V3A 2 1 R4792 2.2K_5%_2
6 PCH_3A_SMCLK 3 PCH_3A_SMDATA
2N7002DW
CMNID1
34 73 48 PCH_KBC_SMCLK 73 48 34 PCH_KBC_SMDATA
IN IN
34
2 0_5%_2
SML1DATA/GPIO75
PERP6
AB49 AB47
P3V3A
PCH_3A_SMDATA
PERN6
1 R4897 2 90.9_1%_2
2
15PF_50V_2 X4751 25MHZ C4826 1
CLKOUT_PCIE6P
2
A
15PF_50V_2
PCIECLKRQ6#/GPIO45
FLEX CLOCKS
G1
1 2.2K_5%_2
BI
PETP5
CLOCKS
2
2 R4856
1 PCH_SML1CLK
S1
34 PCH_3A_SMCLK
PETN5
Y40 Y39
Q4753
46
FPR_OFF
BI
R4840
1
C13
SML1CLK/GPIO58
PEG_A_CLKRQ#/GPIO47
P3V3A
48
IN
P3V3A
PERP5
BE38 BC38 AW38 AY38
GPIO73
PCH_DDR_RST
C8 PCH_3M_SMCLK
PERN5
BG40 BJ40 AY40 BB40
C
A12
0_5%_2
P3V3A R4701 1 20K_5%_2
SML0CLK
PETN3
BG37 BH37 AY36 BB36
GPIO46
0_5%_2 2 0_5%_2 R4822 1 2 0_5%_2 R4829 1 2 0_5%_2 R4888 1
IN IN OUT OUT
Controller Link
D
MEDIA CARD
PCIE_RX3_C_DN PCIE_RX3_C_DP PCIE_TX3_C_DN PCIE_TX3_C_DP
PCI-E*
P3V3A
60 60
R47382
1 E12 FPR_OFF_PCH
SMBCLK
2
0
3
GPIO34
BG34 BJ34 AV32 AU32
4
GPIO20
1
2 0_5%_2
1 R4898 2 1M_5%_2
BANDIT PLATFROM ID
R4908 1
SMBUS
P3V3S
CLKOUT_PCIE7N CLKOUT_PCIE7P PCIECLKRQ7#/GPIO46 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P
CLKOUTFLEX0/GPIO64
K43
CLKOUTFLEX1/GPIO65
F47
CLKOUTFLEX2/GPIO66
H47
CLKOUTFLEX3/GPIO67
K49
INVENTEC
ITL_PANTHERPOINT_FCBGA_989P
TITLE
MODEL,PROJECT,FUNCTION
PANTHER
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
POINT_2/9
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
34
80
of
1
X01
8
7
6
5
4
3
2
1
REFERENCE NUMER : 4700~4949 NOTE: 1.SLP_SUS AND SUSACK# ARE NC IF DSW IS NOT SUPPORTED 2.DPWROK SHOULD CONNECT TO RSMRST# IF DSW NOT SUPPORTED 3.PCH_DPWROK PULL UP TO P3V3S ENABLES DSW WUPPORT. NO INSTALL R4752 TO DISABLE DSW U4701 24 24 24 24
DMI_RX0_DN DMI_RX1_DN DMI_RX2_DN DMI_RX3_DN
IN IN IN IN
BC24 BE20 BG18 BG20
24 24 24 24
DMI_RX0_DP DMI_RX1_DP DMI_RX2_DP DMI_RX3_DP
IN IN IN IN
BE24 BC20 BJ18 BJ20
24 24 24 24
DMI_TX0_DN DMI_TX1_DN DMI_TX2_DN DMI_TX3_DN
OUT OUT OUT OUT
AW24 AW20 BB18 AV18
OUT OUT OUT OUT
AY24 AY20 AY18 AU18
DMI0RXN
FDI_RXN0
DMI1RXN
FDI_RXN1
DMI2RXN
FDI_RXN2
DMI3RXN
FDI_RXN3 FDI_RXN4
D
DMI0RXP
FDI_RXN5
DMI1RXP
FDI_RXN6
DMI2RXP
FDI_RXN7
DMI1TXN DMI2TXN DMI3TXN
FDI_RXP1
FDI
DMI
DMI0TXN
FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5
DMI_TX0_DP DMI_TX1_DP DMI_TX2_DP DMI_TX3_DP
DMI0TXP
FDI_RXP6
DMI1TXP
R4760 1 R4750 1
BJ24
BG25 2 49.9_1%_2 BH21 2 750_1%_2
FDI_TX0_DN FDI_TX1_DN FDI_TX2_DN FDI_TX3_DN FDI_TX4_DN FDI_TX5_DN FDI_TX6_DN FDI_TX7_DN
24 24 24 24 24 24 24 24
BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9
IN IN IN IN IN IN IN IN
FDI_TX0_DP FDI_TX1_DP FDI_TX2_DP FDI_TX3_DP FDI_TX4_DP FDI_TX5_DP FDI_TX6_DP FDI_TX7_DP
24 24 24 24 24 24 24 24
FDI_RXP7
DMI3TXP
AW16 FDI_INT
24
35
OUT
FDI_INT
DMI_ZCOMP
FDI_FSYNC0
AV12
FDI_FSYNC0
OUT
FDI_FSYNC0
24
DMI_IRCOMP
FDI_FSYNC1
BC10
FDI_FSYNC1
OUT
FDI_FSYNC1
24
DMI2RBIAS
FDI_LSYNC0
AV14
FDI_LSYNC0
OUT
FDI_LSYNC0
24
FDI_LSYNC1
BB10
FDI_LSYNC1
OUT
FDI_LSYNC1 P3V3_RTC
35 24
C
TP4700
D
DMI2TXP FDI_INT
P1V05S_VCCP
IN IN IN IN IN IN IN IN
DMI3RXP FDI_RXP0
24 24 24 24
BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9
DSWVRMEN
A18
DPWROK
E22
2 R4742 1 330K_5%_2 R4741 1 2
35 35 35
C
330K_5%_2_DY 1
C12
SUSACK#
IN
RSMRST# 18
33
48
35
TP30 23
18 33 35
33
PM_PWROK IN
20 33
23 35
2
B
VGATE
35
48 35
18 33
SUS_PWR_ACK BI
33 49 35 48
P3V3A
PWR_BTN_OUT# IN R4743
1 48
ADP_PRES_OUT
P3V3A
35
R4744 2
SYS_PWROK
PWROK
APWROK
B13
DRAMPWROK
RSMRST#
C21
RSMRST#
SUS_PWR_ACK
K16
SUSWARN#/SUSPWRDNACK/GPIO30
B9
WAKE#
CLKRUN#/GPIO32
N3
SUS_STAT#/GPIO61
G8
PCI_3S_CLKRUN#
SUSCLK32_KBC
BI
IN
48
PCIE_WAKE#
50 PCI_3S_CLKRUN#
48
53 54
35
SUSCLK/GPIO62
N14
SLP_S5#/GPIO63
D10
OUT
SLP_S5#_3R
21
SLP_S4#
H4
OUT
SLP_S4#_3R
10
SLP_S3#
F4
OUT
SLP_S3#_3R
9 18 19 20 21 27 42 45 48 55 57
OUT
PM_SLP_A#
OUT
H_PM_SYNC
48
35 OUT SUSCLK32_KBC
B
PWR_BTN_OUT#
E20
PWRBTN#
SLP_A#
G10
ADP_PRES_OUT
H20
ACPRESENT/GPIO31
SLP_SUS#
G16
BATLOW#/GPIO72
PMSYNCH
AP14
H_PM_SYNC
K14
SLP_LAN#
18
18
19
21
20
45
21 48
2
0_5%_2
IN
P12
L10
PM_DRAM_PWRGD
RSMRST# IN
SYS_RESET#
L22
M_PWROK IN
PM_DRAM_PWRGD OUT 48
35
VGATE
IN
PM_PWROK R4752 1 0_5%_2
35 48
XDP_DBRESET# K3
XDP_DBRESET# IN
System Power Management
35
R4781 2 PCIE_WAKE#_3A 1 0_5%_2
IN
BT_OFF
1 10K_5%_2_DY
ISOLATION
35
53
PM_RI#
IN
PM_RI#
BT_OFF
E10
A10
RI#
SLP_LAN#/GPIO29
1
TP4705
35 OUT SLP_LAN#
23
35
19 48
21
ITL_PANTHERPOINT_FCBGA_989P
P3V3A
P3V3S 50
A
35 48
PCI_3S_CLKRUN#
BI
PCI_3S_CLKRUN#
1R4727 2 8.2K_5%_2
35 4819 35 21
PM_RI#
OUT
SLP_LAN#
OUT
A
PM_RI#
2 R4717 1 0_5%_2 SLP_LAN# R4745 1 2 10K_5%_2_DY
PCIE_WAKE#_3A R4716 1
2
0_5%_2
INVENTEC TITLE
MODEL,PROJECT,FUNCTION PANTHER POINT_3/9
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
35
80
of
1
X01
8
7
6
5
4
3
2
1
REFERENCE NUMER : 4700~4949 J47 M45
L_BKLTEN
SDVO_TVCLKINN
L_VDD_EN
SDVO_TVCLKINP
INV_PWM_3
P45
L_BKLTCTL
INV_PWM_3 OUT 43 43
P3V3S
LVDS_DDC_CLK LVDS_DDC_DATA
BI BI
D
R4824 1 R4825 1 R4826 1
43 43 43 43 43
2 R4788 1 100K_5%_2
MB_DP_AUXN_CONN
DPD_DDC2DATA S1
42
4 S2 G2
4
S2
LVDSB_DATA0_DP LVDSB_DATA1_DP LVDSB_DATA2_DP
DDPB_HPD
LVDSA_CLK
DDPB_0N
LVDSA_DATA#0
DDPB_1N
LVDSA_DATA#1
DDPB_1P
LVDSA_DATA#2
DDPB_2N
DDPB_0P
LVDSA_DATA#3
AN47 AM49 AK49 AJ47
LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3
AF40 AF39
LVDSB_CLK# LVDSB_CLK
AH45 AH47 AF49 AF45
LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3
AH43 AH49 AF47 AF43
LVDSB_DATA0 LVDSB_DATA1
DDPB_2P DDPB_3N DDPB_3P
CRT_B CRT_G CRT_R
N48 P49 T49
DDPC_CTRLDATA
DDPC_AUXP DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N
CRT_HSYNC CRT_VSYNC
BI BI
CRT_DDCCLK CRT_DDCDATA
T39 M40
OUT OUT
CRT_HSYNC CRT_VSYNC
CRT_RED
DDPD_CTRLCLK DDPD_CTRLDATA
DDPD_AUXN
CRT_DDC_CLK
DDPD_AUXP
CRT_DDC_DATA
DDPD_HPD DDPD_0N
M47 M49
CRT_HSYNC
DDPD_0P
CRT_VSYNC
DDPD_1N DDPD_1P DDPD_2N
2 1K_1%_2 T43 T42
AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49
OUT OUT OUT OUT OUT OUT OUT OUT
DPB0_DN DPB0_DP DPB1_DN DPB1_DP DPB2_DN DPB2_DP DPB3_DN DPB3_DP
55 36 55 55 55
55 55 55 55 55 55 55 55
DPC_DDC2CLK 36 DPC_DDC2DATA
BI BI
DAC_IREF
DDPD_2P
CRT_IRTN
DDPD_3N
AP47 AP49 AT38
BI BI IN
AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49
OUT OUT OUT OUT
DDCAUX_C0_DN DDCAUX_C0_DP DPC_HPD 55 DPC0_DN 55 DPC0_DP 55 DPC1_DN 55 DPC1_DP 55
M43 M36
BI BI
DPD_DDC2CLK 36 DPD_DDC2DATA 36
AT45 AT43 BH41
BI BI IN
DDCAUX_D0_DN DDCAUX_D0_DP 36 36 DPD_HPD
BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42
OUT OUT OUT OUT OUT OUT OUT OUT
36 42
B
42 42 42 42 42 42 42 42
DPD0_DN DPD0_DP DPD1_DN DPD1_DP DPD2_DN DPD2_DP DPD3_DN DPD3_DP
4
DPC_DDC2CLK OUT
DPC_DDC2DATA OUT 6 3
1
2
2.2K_5%_2 R4931 1 2 2.2K_5%_2
G2
5
S2
D1 D2
S1 G1
2N7002DW
2
Q4704
DDCAUX_B0_DN DDCAUX_B0_DP DPB_HPD 36
P3V3S
DPD_AUX_C
2
BI BI IN
36
C DDPC_AUXN
LVDSB_DATA3
CRT_GREEN
AT49 AT47 AT40
P46 P42
DDPC_CTRLCLK
LVDSB_DATA2
CRT_BLUE
DPB_DDC2CLK 55 DPB_DDC2DATA
ITL_PANTHERPOINT_FCBGA_989P
DP_EN
0.1UF_16V_2
A
42
S2
D1 D2
S1 G1
2 C4757 1
OUT OUT OUT
LVDSB_DATA0_DN LVDSB_DATA1_DN LVDSB_DATA2_DN
DDPB_AUXP
BI BI
R4930
1
BI
OUT OUT OUT
LVDSA_CLK#
DDPB_AUXN
DDPD_3P
IN
DP_EN
2 R4791 1 100K_5%_2_DY
DDCAUX_D0_DP
OUT OUT
LVD_VREFL
DPD_AUX#_C
Q4703
36
OUT OUT OUT
1R4627
2N7002DW
36
SDVO_CTRLDATA
LVD_VREFH
AN48 AM47 AK47 AJ48
CRT_B OUT CRT_G OUT CRT_R OUT
CRT_DDCCLK CRT_DDCDATA
36 42
0.1UF_16V_2
42
LVD_VBG
AE48 AE47
P38 M39
G2
2
42
36
5
C4756 1
SDVO_CTRLCLK
4
BI
36 36 36 42
36
1
DDCAUX_D0_DN
LVD_IBG
LVDSA_DATA0_DN LVDSA_DATA1_DN LVDSA_DATA2_DN
LVDSB_CLK_DN LVDSB_CLK_DP
D
L_CTRL_DATA
AF37 AF36
OUT OUT
LVDSA_DATA0_DP LVDSA_DATA1_DP LVDSA_DATA2_DP
L_CTRL_CLK
DDPC_3P
42 42
42 36
6 3
36
2 R4789 1 100K_5%_2_DY
B
SDVO_INTP
AK39 AK40
OUT OUT OUT
AP39 AP40
SDVO_INTN
L_DDC_DATA
42
DDC_EN
IN
DDC_EN P3V3S
43 43 43
43 43 43
MB_DP_AUXP_CONN MB_DP_AUXP_CONN 36 BI
5
2
2N7002DW
36
36
MB_DP_AUXN_CONN
G2
1
6 3
S1
D1 D2 G1
Q4702
42
42
DDC_EN
IN
DPD_DDC2CLK
BI
DPD_DDC2CLK
BI
2 R4790 1 100K_5%_2
DDC_EN
43 43
5
2
2N7002DW
36
D1 D2 G1
Q4701
36
6 3
1
BI
DPD_DDC2DATA
43 43 43
AM42 AM40
SDVO_STALLN
L_DDC_CLK
T45 P39
LVDSA_CLK_DN LVDSA_CLK_DP
P3V3S
C 36
2 2.2K_5%_2 2 2.2K_5%_2 2 2.37K_1%_2
AP43 AP45
SDVO_STALLP
T40 K47
CRT
2 R4786 1 2.2K_5%_2 2 R4787 1 2.2K_5%_2
P3V3S
U4701
L_BKLT_EN LVDS_VDD_EN
Digital Display Interface
36
43
OUT OUT
LVDS
43 43
P3V3S
A
R4782
DP_EN 42
36
IN DP_EN
55
36
DPB_DDC2DATA
55 36
OUT
DPB_DDC2CLK OUT
1
2 55
2.2K_5%_2 R4784 1 2
55
2.2K_5%_2
42
36 36
36
DPB_HPD DPC_HPD DPD_HPD
DPB_HPD 1 R4759
2 100K_5%_2 1 R4932 2
OUT OUT
100K_5%_2
DPD_HPD 1 R4761
2 100K_5%_2
OUT
INVENTEC TITLE
MODEL,PROJECT,FUNCTION PANTHER POINT_4/9
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
DOC.NUMBER
REV
CODE 1310xxxxx-0-0
X01
CS
SHEET
36
80
of
1
8
7
6
5
4
3
2
1
REFERENCE NUMER : 4700~4949 P3V3S
SC_PWRSV#
RSVD1 RSVD2
37 56
R4772 1 R4768 1
2
8.2K_5%_2
GPIO54
2
8.2K_5%_2
ACCEL_INT#
R4709 1 R4758 1
2
8.2K_5%_2
GPIO03
8.2K_5%_2_DY
GPIO50
2 0_5%_2
P3V3S GPIO52
R4770 R4771
2
PCI_3S_INTB# PCI_3S_INTD#
B
PORT4:RIGHT2 USB2.0+USB3.0
1 10K_5%_2_DY
OUT
1 10K_5%_2_DY
IN
1
0_5%_2
R4734 2
1
0_5%_2
R4815 2
1
0_5%_2
R4739 2
1
0_5%_2
R4737 2
1
0_5%_2
R4793 2
1
0_5%_2
R4778 2
1
0_5%_2
R4740 2
1
0_5%_2
51
B21 M20 AY16 BG46
PORT3:RIGHT1 USB2.0+USB3.0
CAMERA_ON37 GPIO55
55 59 45 45 55 59 45 45 55 59 45 45 55 59 45 45
43
37
P3V3A R4736 2
TP4
RSVD5
TP5
RSVD6
37
OUT OUT OUT OUT OUT OUT OUT OUT
33
37
GPIO14
37 52 55
LANLINK_STATUS GPIO59
37
GPIO41
37
GPIO42
37
GPIO9
37
GPIO43
37
GPIO40
72 44 PLT_RST#
BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
USB30_RX1_DN USB30_RX2_DN USB30_RX3_DN USB30_RX4_DN USB30_RX1_DP USB30_RX2_DP USB30_RX3_DP USB30_RX4_DP USB30_TX1_DN USB30_TX2_DN USB30_TX3_DN USB30_TX4_DN USB30_TX1_DP USB30_TX2_DP USB30_TX3_DP USB30_TX4_DP
RSVD22
AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6
RSVD23
AV5
RSVD24
AV10
RSVD25
AT8
USB3RN1
RSVD26
USB3RN2
RSVD27
AY5 BA2
TP7
RSVD7
TP8
RSVD8
TP9
RSVD9
TP10
RSVD10
TP11
RSVD11
TP12
RSVD12
TP13
RSVD13
TP14 TP15 TP16 TP17 TP18 TP19 TP20
RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20
TP23 TP24
USB3RN4
RSVD28
USB3RP1
RSVD29
USB3RP3
USBP13P
C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32
USBRBIAS#
C33
USB3RP4
USBP0N
USB3TN1
USBP0P
USB3TN2
USBP1N
USB3TN3
USBP1P
USB3TN4
USBP2N
USB3TP1
USBP2P
USB3TP2
USBP3N
USB3TP3
USBP3P
USB3TP4
USBP4N
PLT_RST# R4707 1
2 43 37 37
CAMERA_ON OUT OUT GPIO55
PIRQA#
USBP7N
PIRQB#
USBP7P
PIRQC#
USBP8N
PIRQD# REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54
USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N
TP2048
0_5%_2_DY
P3V3A
USBP6P
C46 C44 E40
1
CAMERA_ON
D47 E42 F46
GNT1#/GPIO51
USBP11P
GNT2#/GPIO53
USBP12N
GNT3#/GPIO55
USBP12P
NC
5 1
USBP13N
BUF_PLT_RST#
OUT BUF_PLT_RST#
4
2 R4713 1 100K_5%_2
56
A
2
37
-
47
PHP_74LVC1G17_SOT753_5P
3
37 SC_PWRSV# IN IN GPIO03 48 NMI_SMI_DBG# IN IN ACCEL_INT# 37 P3V3A
G42 G40 NMI_SMI_DBG# C42 ACCEL_INT# D44
1
PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5 USBRBIAS
R4794
2 K10 10K_5%_2_DY PLT_RST# C6
50
48 37 37 34 37 48 37
CLK_R3S_KBPCI CLK_R3S_PCH_FB CLK_R3S_TPM
OUT OUT OUT
CLK_R3S_DEBUG
CLK_R3S_DEBUG OUT
R4774 1 R4775 1 R4777 1 R4773 1
2 22_5%_2 CLK_KBPCI 2 22_5%_2 CLK_PCH_FB 2 22_5%_2 CLK_TPM 2 22_5%_2 CLK_DEBUG
USB_P0_DN USB_P0_DP USB_P1_DN USB_P1_DP USB_P2_DN USB_P2_DP USB_P3_DN USB_P3_DP
BI BI
USB_P5_DN USB_P5_DP
BI BI BI BI
USB_P7_DN USB_P7_DP USB_P8_DN USB_P8_DP
BI BI
USB_P10_DN USB_P10_DP
43 43
CAMERA
BI BI
USB_P12_DN USB_P12_DP
54 54
WWAN
DOCK_PORT CONN (CHARGER) CONN1 RIGHT 45
53 53
NC
1 1
TP7000 TP7001
56 56 46 46
CONN2 RIGHT
BLUETOOTH SMART CARD B
FINGER PRINT
NC
1 R4756 2 22.6_1%_2
B33
PME# PLTRST#
OC0#/GPIO59 OC2#/GPIO41
H49 H43 J48 K42 H40
55 55 45 45 45 45 45
BI BI BI BI BI BI BI BI
PIRQE#/GPIO2
OC1#/GPIO40
CLK_R3S_KBPCI CLK_R3S_PCH_FB CLK_R3S_TPM
CLKOUT_PCI0
OC3#/GPIO42
CLKOUT_PCI1
OC4#/GPIO43
CLKOUT_PCI2
OC5#/GPIO9
CLKOUT_PCI3
OC6#/GPIO10
CLKOUT_PCI4
OC7#/GPIO14
A14 K20 B17 C16 L16 A16 D14 C14
IN IN IN IN IN IN IN IN
LANLINK_STATUS
GPIO59 37 GPIO40 37 GPIO41 37 37 GPIO42 37 GPIO43 37 GPIO9 55 LANLINK_STATUS GPIO14 37
A 52 37
1
1
1
ITL_PANTHERPOINT_FCBGA_989P
C7675 C7674
C4761
2
2
8.2PF_50V_2_DY
2
54 60 23 48 53 37 50
+
U4700
AT12 BF3
USB3RP2
USBP5P
GPIO50 GPIO52 GPIO54
C
USB3RN3
USBP6N
K40 K38 H38 G38
D
TP22
USBP5N
37
OUT
TP21
USBP4P
PCI_3S_INTA# PCI_3S_INTB# PCI_3S_INTC# PCI_3S_INTD#
AT10 BC8
TP6
RSVD21
PORT2:LEFT USB2.0(CHARGE PORT)+USB3.0
P3V3S 2
RSVD4
AY7 AV7 AU3 BG4
TP3
USB
1 2 3 4
8.2K_5%
C
TP2
PORT1:DOCKING
RS4784 8 7 6 5
RSVD3
PCI
2
R4719 1
TP1
NVRAM
OUT
U4701 BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45
8.2K_5%
P3V3S
D
NMI_SMI_DBG# PCI_3S_INTC# PCI_3S_INTA#
1 2 3 4
RSVD
RS4765 8 7 6 5
INVENTEC
8.2PF_50V_2_DY
8.2PF_50V_2_DY
TITLE
MODEL,PROJECT,FUNCTION
FOR RF
PANTHER POINT_5/6
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
37
80
of
1
X01
8
7
6
5
4
3
2
1
REFERENCE NUMER : 4700~4949 10K_5%_2_DY
1
R4722 2
1
R4747 2
0_5%_2
1
R4725 2
0_5%_2
1
R4723 2
1
R4730 2
GPIO17
IN
GPIO27
38
CMNID2
10K_5%_2_DY
GPIO35
0_5%_2
GPIO49
D
D
T7
GPIO0
OCP_OC# A42
P3V3S
0_5%_2
OCP_OC#
2
0_5%_2
GPIO17
R4728 1
2
0_5%_2
DOCK_ID1
R4726 1
2
0_5%_2
DOCK_ID2
0_5%_2
2
10K_5%_2_DY
R4735 1
2
10K_5%_2_DY
R4712 1
2
R4706 1
2
R4710 1
2
R4769 1
2
R4755 1
2
THERM_SCI# E38
38
52 38
51
38
LAN_DIS#
49
GPIO16 GPIO17
MSATA_CD# GPIO0
10K_5%_2_DY 0_5%_2
GPIO37
38
LPC_RESET#
0_5%_2
G2
IN
U2
BI
D40
TACH7/GPIO71
A20GATE
SATA4GP/GPIO16
TACH0/GPIO17 SCLOCK/GPIO22 GPIO24
GPIO27
IN
E16
GPIO27
P8
GPIO28
CMNID2
OUT
K1
STP_PCI#/GPIO34
GPIO35
OUT
K4
GPIO35
RCIN# PROCPWRGD THRMTRIP#
R4720
R4721 R4714
2
1
2
1
1 1
R4841 1
0_5%_2
CLKREQ_LAN#
1K_5%_2
TLS_ENCRYTION_R
2 10K_5%_2_DY GPIO24
2
0_5%_2
34
2
0_5%_2
GPI_INV_LIDWAKE
2
0_5%_2
GPIO35
GPIO35
GPIO49
GPIO50
R4767 R4722
R4841 R4723
R4803 R4730
R4758 R4719
0
1
0
0
1
OUT
0
H L SI 1
0
1
SI 1B
0
1
1
0
SI 2
1
0
0
0
PV 1
1
1
0
0
MV
1
AU16
1
R4749
AY11
H_PWRGD
AY10 T14
DF_TVS
AY1
TS_VSS1
AH8
TS_VSS2
AK11
TS_VSS3
AH10
GPS_XMIT_OFF#
0_5%_2 54 R4753 1 2 0_5%_2
2
0_5%_2
2 0_5%_2_DY 2 0_5%_2_DY
OUT
IN H_PWRGD23
IN
SNB_IVB#
BI
23
H_PECI
38
1 R4708
48
48
P3V3S
PM_3S_KBCCPURST# 38
38
1R4731 2 PM_THRMTRIP# 390_5%_2
IN
EC_3S_A20GATE
IN
H_PECI
48
C
2 0_5%_2
38 PM_THRMTRIP#
23
P1V05S_VCCP
2 R4732 1 56_5%_2_DY
23
AK10
SATA3GP/GPIO37 NC_1
P37
VSS_NCTF_15
BG2
IN
DOCK_ID1
N2
SLOAD/GPIO38
DOCK_ID2
IN
DOCK_ID2
M3
SDATAOUT0/GPIO39
FPR_LOCK#
IN
FPR_LOCK# V13
SDATAOUT1/GPIO48
GPIO49
OUT
V3
SATA5GP/GPIO49/TEMP_ALERT#
VSS_NCTF_16
BG48
WLAN_TRANSMIT_OFF# OUT
D6
GPIO57
VSS_NCTF_17
BH3
VSS_NCTF_18
BH47
38
38
P5 PM_3S_KBCCPURST#
DOCK_ID1
46
53
P4
38
51
38
LAN_DIS#
GPIO17
A
OUT OUT
2
48
SATA2GP/GPIO36
B
38
A4
VSS_NCTF_1
VSS_NCTF_19
BJ4
A44
VSS_NCTF_2
VSS_NCTF_20
BJ44
A45
VSS_NCTF_3
VSS_NCTF_21
BJ45
A46
VSS_NCTF_4
VSS_NCTF_22
BJ46
A5
VSS_NCTF_5
VSS_NCTF_23
BJ5
NCTF
R4724
1
IN
R4704
38
55
R4705
M5
OUT
A40 GPS_XMIT_OFF#
INIT3_3V#
TS_VSS4
GPIO37
LPC_RESET# 38
1
R4839
GPIO15
T5
V8
IN
1
E8
44 OUT MSATA_CD#
P3V3S R4754
60
LAN_PHY_PWR_CTRL/GPIO12
IN
GPIO68
C41 LPC_RESET#
GPIO8
GPIO24
WWAN_TRANSMIT_OFF# BI
54 56
FPR_LOCK#
C4
TACH3/GPIO7
PECI
GPIO16
0_5%_2
LAN_DIS#
IN
TLS_ENCRYTION_R
P3V3A
B
OUT
GPIO49
10K_5%_2_DY
C10
TACH6/GPIO70
GPIO68
D3E_WAKE# 38
A6
VSS_NCTF_6
VSS_NCTF_24
BJ6
B3
VSS_NCTF_7
VSS_NCTF_25
C2
B47
VSS_NCTF_8
VSS_NCTF_26
C48
BD1
VSS_NCTF_9
VSS_NCTF_27
D1
BD49
VSS_NCTF_10
VSS_NCTF_28
D49
BE1
VSS_NCTF_11
VSS_NCTF_29
E1
BE49
VSS_NCTF_12
VSS_NCTF_30
E49
BF1
VSS_NCTF_13
VSS_NCTF_31
F1
BF49
VSS_NCTF_14
VSS_NCTF_32
F49
OUT
OCP_OC#
3
2
R4767 1
2
BI IN
22
TACH2/GPIO6
OUT IN
Q4805 D
R4780 1
R4803 1
THERM_SCI#
GPI_INV_LIDWAKE
B41 D3E_WAKE#
48
OCP_PWM_OUT
1
IN
G
S
RUNSCI0#_3
C40
TACH5/GPIO69
SSM3K7002FU
2
GPIO19
0_5%_2
TACH4/GPIO68
TACH1/GPIO1
CPU/MISC
0_5%_2
RUNSCI0#_3
BMBUSY#/GPIO0
GPIO
2 2
R4729 1
RUNSCI0#_3 H36
38
R4746 1 R4785 1
C
IN
38
48
U4701
A
INVENTEC
ITL_PANTHERPOINT_FCBGA_989P
TITLE
MODEL,PROJECT,FUNCTION PANTHER
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
POINT_6/9
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
38
80
of
1
X01
8
7
6
5
4
3
2
1
REFERENCE NUMER : 4700~4949 TP4807 P1V05S_VCCP
VCCCORE[15] VCCCORE[16] VCCCORE[17]
VCCTX_LVDS[1]
AM37
VCCTX_LVDS[2]
AM38
VCCTX_LVDS[3]
AP36
VCCTX_LVDS[4]
AP37
VCCIO[16]
AN21
VCCIO[17]
AN26
VCCIO[18]
AN27
VCCIO[19]
AP21
VCCIO[20]
AP23
VCCIO[21]
AP24
VCCIO[22] VCCIO[23]
AT24
VCCIO[24]
AN33
VCCIO[25]
AN34
VCCIO[26]
BH29
VCC3_3[3]
VCC3_3[7]
V34
1 C4780 2
30MA
P1V5S VCCVRM[3]
AT16
VCCDMI[1]
AT20
VCCCLKDMI
AB36
P1V05S_VCCP
60MA P1V05S_VCCP
20MA
R4733 1 2 0_5%_2_DY
P1V05S_R_FDIPLL
AJ16
AP16
VCCVRM[2]
BG6
VccAFDIPLL
VCCDFTERM[4]
AJ17
P1V05S_VCCP
AP17
VCCIO[27]
C4725
2
B
P3V3A VCCSPI
20MA
V1
1
P1V05S_VCCP
AU20
1UF_6.3V_2_DY
VCCDFTERM[3]
2
AG17
1 VCCDFTERM[2]
C4737
1 P1V05S_VCCP
FDI
P1V5S
30MA
AG16
2
1 0.1UF_16V_2
VCCDFTERM[1]
TP4805 TP30
C4704
VCCDMI[2]
2
ITL_PANTHERPOINT_FCBGA_989P
1UF_6.3V_2
2
B
1MA
NAND / SPI
P3V3S
0.1UF_16V_2
P1V8S
C4745
70MA 1 2 FBM_11_160808_181A15T
C
1
AP26
V33
P1V8S L4704
0.1UF_16V_2
VCCIO[15]
AN17
VCCIO
1UF_6.3V_2
1UF_6.3V_2 C4743 2 1
AN16
P3V3S VCC3_3[6]
1
VCCAPLLEXP
C4735 2
BJ22
TP30
1UF_6.3V_2 C4727 2 1 1UF_6.3V_2 C4742 2 1
1 C4758 2
10UF_6.3V_3 C4724 2 1
C
1
HVCMOS
TP843
2.7A
VCCIO[28]
DMI
P1V05S_VCCP
AN19
22UF_6.3V
1 C4749
1
TP4806 TP30
P1V05S_VCCP
15MA
D
1
VCCCORE[14]
AK37
1UF_6.3V_2
VCCCORE[13]
VSSALVDS
C4726
VCCCORE[12]
22UF_6.3V
VCCCORE[11]
AK36
0.01UF_50V_2 1 C4782 1 2 2 1
VCCCORE[10]
P3V3S VCCALVDS
70MA 1 L4701 2 FBM_11_160808_181A15T
0.01UF_50V_2 C4781 2 1
VCCCORE[9]
2
VCCCORE[8]
U47
0.1UF_16V_2 1 1 C47502 2
VCCCORE[7]
VSSADAC
1
VCCCORE[6]
C4747
VCCCORE[5]
U48
2
VCCCORE[4]
VCC CORE
VCCCORE[3]
VCCADAC
0.01UF_50V_2
VCCCORE[2]
POWER
CRT
VCCCORE[1]
LVDS
AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31
1UF_6.3V_2
1 C4721 2
1UF_6.3V_2 C4740 2 1
1UF_6.3V_2
10UF_6.3V_3 C4718 2 1
C4751 1 2
D
P3V3S
TP30 U4701
2.04A
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION PANTHER POINT_7/9
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
DOC.NUMBER
REV
CODE 1310xxxxx-0-0
X01
CS
SHEET
39
80
of
1
8
7
6
5
4
3
2
1
REFERENCE NUMER : 4700~4949 P1V05S_VCCP
P1V05S_VCCP
AL24
V23
VCCSUS3_3[10]
V24
VCCSUS3_3[6]
P24
AA24
VCCASW[3]
AA26
VCCASW[4]
AA27
VCCASW[5]
AA29
VCCASW[6]
AA31
VCCASW[7]
AC26
VCCASW[8]
AC27
VCCASW[9]
AC29
VCCASW[10]
AC31
VCCASW[11]
AD29
VCCASW[12]
AD31
VCCASW[13]
W21
VCCASW[14]
W23 W24
2
C4700
VCCIO[34] V5REF_SUS
AN23 AN24
V5REF
VCCSUS3_3[2]
N20
VCCSUS3_3[3]
N22
VCCSUS3_3[4]
P20
VCCSUS3_3[5]
P22
W16
VCCASW[16]
VCC3_3[4]
T34
VCCASW[19]
D4701 3
1
P5V0S
C4746 2
1
1UF_6.3V_2
P3V3S
1R4762 2 10_5%_2
2MA
70MA 1
0.1UF_16V_2
P3V3S
80MA
C4736 1
2
2MA
VCCIO[5]
VCCIO[12]
AH13
C4703 1
B
2
0.1UF_16V_2
AF17 AF33 AF34 AG34
VCCVRM[4]
VCCADPLLA
VCCIO[13]
AH14
VCCIO[6]
AF14
0.1UF_16V_2
BJ8
0.1UF_16V_2 C4711 2 1
1UF_6.3V_2 C4709 2 1
1MA
A22
2
TP2049
1
AK1
P1V5S
TP30 VCCVRM[1]
AF11
VCCIO[2]
AC16
VCCIO[3]
AC17
VCCIO[4]
AD17
30MA P1V05S_VCCP
VCCIO[7] VCCDIFFCLKN[1] VCCDIFFCLKN[2]
C4741 1
120MA
VCCDIFFCLKN[3]
VCCSSC
2
1UF_6.3V_2
A DCPSST
DCPSUS[1] DCPSUS[2]
V_PROC_IO
VCCRTC
MISC
P1V05M VCCASW[22]
T21
VCCASW[23]
V21
VCCASW[21]
T19
60MA
INVENTEC
P3V3A
HDA
2 0_5%_2_DY T17 2 V19 1UF_6.3V_2_DY
C4722 1
1UF_6.3V_2
VCCADPLLB
RTC CPU
AG33
C4769 2 1 V16 0.1UF_16V_2
450MA
VCCSUSHDA
P32
15MA
1
C4733 2
TITLE
MODEL,PROJECT,FUNCTION PANTHER POINT_8/9
ITL_PANTHERPOINT_FCBGA_989P
0.1UF_25V_2 SIZE A3
CHANGE by
8
7
6
C
BAT54_30V_0.2A
2
AJ2 AF13
VCCAPLLSATA
150MA
1
P3V3S
TP4812 TP30
P5V0S_R_V5REF
DCPRTC
P1V05S_VCCP
C4710 2
1R4751 2 10_5%_2
60MA
VCCASW[20]
P3V3_RTC
0.1UF_16V_2
0.1UF_16V_2 C4707 2 1
1 C4705 2
4.7UF_6.3V_3 C4706 2 1
2MA
1
P3V3S
SATA
Y49
50MA
R4748 1 1 C4712
200MA P1V05S_VCCP
P5V0A
C4730
0.1UF_16V_2 VCCASW[18]
N16
P1V05S_VCCP
P1V05M
BAT54_30V_0.2A
C4717
VCC3_3[8]
W29
BF47
1 1UF_6.3V_2
1
P3V3A
VCCASW[15]
W31
BD47
2 C4744
P3V3A
2
P34
AA16
VCCASW[17]
P1V05S_L_ADPLLB
A
3
10UF_6.3V_3_DY 2
VCC3_3[1]
W26
P1V05S_L_ADPLLA
1 1UF_6.3V_2
C4728 1
P1V05S_VCCP
30MA
1
P1V5S
2 C4719
P5V0A_R_V5REF
M26
DCPSUS[4]
P3V3A
D4700
0.1UF_16V_2
0.1UF_16V_2
1 1UF_6.3V_2
TP4811 TP30
2
0.1UF_16V_2
T26
VCCSUS3_3[1]
P1V05S_VCCP
2 C4720
2MA C4713 1
1
VCCASW[2]
D P3V3A
P1V05S_VCCP
PCI/GPIO/LPC
2
1
10UF_6.3V_3
1
10UF_6.3V_3 C4786
C4785
2
AA21
Clock and Miscellaneous
1UF_6.3V_2
1UF_6.3V_2 C4738 2 1 1UF_6.3V_2 C4739 2 1 1UF_6.3V_2 C4763 2 1
1 2
10UF_6.3V_3 C4716 2 1
1
10UF_6.3V_3 C4729
C4708
2
DCPSUS[3]
VCCASW[1]
1
VCCSUS3_3[9]
VCC3_3[2]
1UF_6.3V_2
220UF_2.5V C4753 2 1
11 +
C4755 2
VCCIO[14]
11MA
2
1
W33
1UF_6.3V_2
11 +
T24
1UF_6.3V_2_DY AA19
TP4810 TP30
C4754 2
AL29
TP4809 TP30
P1V05S_VCCP
220UF_2.5V C4752 2 1
VCCSUS3_3[8]
NC
C4723 2
C
1 L4703 2 MLZ1608M100WT
T23
1
TP30
P1V05M
P1V05S_VCCP
VCCSUS3_3[7]
P3V3A
VCCAPLLDMI2
2
30MA
1 BH23
1.81A
1 L4702 2 MLZ1608M100WT
T29
VCC3_3[5]
USB
TP842
P1V05M
B
T27
VCCIO[33]
P1V05S_VCCP
1UF_6.3V_2
1 C4748 2
D
10UF_6.3V_3 C4732 2 1
20MA
P28
VCCIO[32]
NC
0.1UF_16V_2_DY T38
VCCIO[31]
420MA C4734
DCPSUSBYP
P26
1
P3V3S
1
VCCIO[30]
2
C4762 2
N26
1UF_6.3V_2
VCCDSW3_3
V12
0.1UF_16V_2
VCCIO[29]
1
T16
POWER
C4731
2MA
1
VCCACLK
2
C4714
U4701
0.1UF_16V_2
2
P1V05S_R_VCCACLK AD49 P3V3A
C4715 2
1R4779 2 0_5%_2_DY
1UF_6.3V_2
20MA
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
40
80
of
1
X01
8
7
6
5
4
3
2
1
U4701 AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3
REFERENCE NUMER : 4700~4949 U4701 H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3
D
C
B
A
VSS[0] VSS[1]
VSS[80]
VSS[2]
VSS[81]
VSS[3]
VSS[82]
VSS[4]
VSS[83]
VSS[5]
VSS[84]
VSS[6]
VSS[85]
VSS[7]
VSS[86]
VSS[8]
VSS[87]
VSS[9]
VSS[88]
VSS[10]
VSS[89]
VSS[11]
VSS[90]
VSS[12]
VSS[91]
VSS[13]
VSS[92]
VSS[14]
VSS[93]
VSS[15]
VSS[94]
VSS[16]
VSS[95]
VSS[17]
VSS[96]
VSS[18]
VSS[97]
VSS[19]
VSS[98]
VSS[20]
VSS[99]
VSS[21]
VSS[100]
VSS[22]
VSS[101]
VSS[23]
VSS[102]
VSS[24]
VSS[103]
VSS[25]
VSS[104]
VSS[26]
VSS[105]
VSS[27]
VSS[106]
VSS[28]
VSS[107]
VSS[29]
VSS[108]
VSS[30]
VSS[109]
VSS[31]
VSS[110]
VSS[32]
VSS[111]
VSS[33]
VSS[112]
VSS[34]
VSS[113]
VSS[35]
VSS[114]
VSS[36]
VSS[115]
VSS[37]
VSS[116]
VSS[38]
VSS[117]
VSS[39]
VSS[118]
VSS[40]
VSS[119]
VSS[41]
VSS[120]
VSS[42]
VSS[121]
VSS[43]
VSS[122]
VSS[44]
VSS[123]
VSS[45]
VSS[124]
VSS[46]
VSS[125]
VSS[47]
VSS[126]
VSS[48]
VSS[127]
VSS[49]
VSS[128]
VSS[50]
VSS[129]
VSS[51]
VSS[130]
VSS[52]
VSS[131]
VSS[53]
VSS[132]
VSS[54]
VSS[133]
VSS[55]
VSS[134]
VSS[56]
VSS[135]
VSS[57]
VSS[136]
VSS[58]
VSS[137]
VSS[59]
VSS[138]
VSS[60]
VSS[139]
VSS[61]
VSS[140]
VSS[62]
VSS[141]
VSS[63]
VSS[142]
VSS[64]
VSS[143]
VSS[65]
VSS[144]
VSS[66]
VSS[145]
VSS[67]
VSS[146]
VSS[68]
VSS[147]
VSS[69]
VSS[148]
VSS[70]
VSS[149]
VSS[71]
VSS[150]
VSS[72]
VSS[151]
VSS[73]
VSS[152]
VSS[74]
VSS[153]
VSS[75]
VSS[154]
VSS[76]
VSS[155]
VSS[77]
VSS[156]
VSS[78]
VSS[157]
VSS[79]
VSS[158]
AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28
ITL_PANTHERPOINT_FCBGA_989P
VSS[159]
VSS[259]
VSS[160]
VSS[260]
VSS[161]
VSS[261]
VSS[162]
VSS[262]
VSS[163]
VSS[263]
VSS[164]
VSS[264]
VSS[165]
VSS[265]
VSS[166]
VSS[266]
VSS[167]
VSS[267]
VSS[168]
VSS[268]
VSS[169]
VSS[269]
VSS[170]
VSS[270]
VSS[171]
VSS[271]
VSS[172]
VSS[272]
VSS[173]
VSS[273]
VSS[174]
VSS[274]
VSS[175]
VSS[275]
VSS[176]
VSS[276]
VSS[177]
VSS[277]
VSS[178]
VSS[278]
VSS[179]
VSS[279]
VSS[180]
VSS[280]
VSS[181]
VSS[281]
VSS[182]
VSS[282]
VSS[183]
VSS[283]
VSS[184]
VSS[284]
VSS[185]
VSS[285]
VSS[186]
VSS[286]
VSS[187]
VSS[287]
VSS[188]
VSS[288]
VSS[189]
VSS[289]
VSS[190]
VSS[290]
VSS[191]
VSS[291]
VSS[192]
VSS[292]
VSS[193]
VSS[293]
VSS[194]
VSS[294]
VSS[195]
VSS[295]
VSS[196]
VSS[296]
VSS[197]
VSS[297]
VSS[198]
VSS[298]
VSS[199]
VSS[299]
VSS[200]
VSS[300]
VSS[201]
VSS[301]
VSS[202]
VSS[302]
VSS[203]
VSS[303]
VSS[204]
VSS[304]
VSS[205]
VSS[305]
VSS[206]
VSS[306]
VSS[207]
VSS[307]
VSS[208]
VSS[308]
VSS[209]
VSS[309]
VSS[210]
VSS[310]
VSS[211]
VSS[311]
VSS[212]
VSS[312]
VSS[213]
VSS[313]
VSS[214]
VSS[314]
VSS[215]
VSS[315]
VSS[216]
VSS[316]
VSS[217]
VSS[317]
VSS[218]
VSS[318]
VSS[219]
VSS[319]
VSS[220]
VSS[320]
VSS[221]
VSS[321]
VSS[222]
VSS[322]
VSS[223]
VSS[323]
VSS[224]
VSS[324]
VSS[225]
VSS[325]
VSS[226]
VSS[328]
VSS[227]
VSS[329]
VSS[228]
VSS[330]
VSS[229]
VSS[331]
VSS[230]
VSS[333]
VSS[231]
VSS[334]
VSS[232]
VSS[335]
VSS[233]
VSS[337]
VSS[234]
VSS[338]
VSS[235]
VSS[340]
VSS[236]
VSS[342]
VSS[237]
VSS[343]
VSS[238]
VSS[344]
VSS[239]
VSS[345]
VSS[240]
VSS[346]
VSS[241]
VSS[347]
VSS[242]
VSS[348]
VSS[243]
VSS[349]
VSS[244]
VSS[350]
VSS[245]
VSS[351]
VSS[246]
VSS[352]
H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28
D
C
B
A
VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253]
INVENTEC
VSS[254] VSS[255] VSS[256] VSS[257]
TITLE
VSS[258]
MODEL,PROJECT,FUNCTION PANTHER POINT_9/9
ITL_PANTHERPOINT_FCBGA_989P
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
41
80
of
1
X01
8
7
6
5
4
3
2
1
CRT_R
36
IN
CRT_R
36
IN
CRT_G
36
L3052
2 120NH,5%
1
L3053
2 120NH,5%
1
IN
CRT_B
1
L3055
VGA_R_L2
CRT_G VGA_G_L2 VGA_B_L2
2 120NH,5%
SYNC_IN2
VIDEO_1
SYNC_OUT1
VIDEO_2
SYNC_IN1
VIDEO_3
DDC_OUT2
GND
DDC_IN2
VCC-DCC
DDC_IN1 DDC_OUT1
2
CRT_R_HSYNC 1 R3072 2
22_5%_2
OUT CRT_Q_VSYNC IN CRT_VSYNC OUT CRT_Q_HSYNC IN CRT_HSYNC BI CRT_Q_DDCDATA BI CRT_DDCDATA BI CRT_DDCCLK BI CRT_Q_DDCCLK
R3065 2
R3064 1
2
1
22_5%_2
1
CRT_R_VSYNC
D
CLOSE TO PCH
1
BYP
16 15 14 13 12 11 10 9
150_1%_2_DY
SYNC_OUT2
VCC-VIDEO
150_1%_2_DY
R3066 2 VCC-SYNC
1
R3071
U3071 1 2 3 4 5 6 7 8
1
P3V3S
P3V3S
150_1%_2_DY
2
1
12PF_50V_2
1 2
12PF_50V_2 C3061
1 C3057
2
12PF_50V_2 C3060
2
1
12PF_50V_2
1 2
12PF_50V_2 C3056
1 C3068
2
12PF_50V_2 C3058
75_1%_2
75_1%_2
1 R3069 2
75_1%_2
D
1 R3068 2
1 R3067 2
CRT_B
P5V0S
NXP_IP4772CZ16_SSOP_16P C3072
0.1UF_16V_2
2
2
4.7K_5%_2
2 R3058 1 4.7K_5%_2 2 R3063 1
C3071
0.1UF_16V_2
P5V0S_CRTVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P5V0S 42
SLP_S3#_3R
55 48 45 42 35 27 21 20 19 18 9
2
C3309
57
IN
GND
OUT
IN
OUT
IN
OUT
EN
OC#
1 TP3000
8 7 6 5
1
36
CRT_DDCCLK
U3051
P5V0S_CRTVDD
TP30 C3052
0.1UF_16V_2 42 42 42 42
P5V0S_CRTVDD
4.7K_5%_2
R3052
ROHM_BD82024FVJ_TSSOP_8P
2
BI
1 2 3 4
1UF_6.3V_2
C
CRT_DDCDATA
42
1
BI
36
2
1
2 R3051
1
4.7K_5%_2
BI BI BI BI
CRT_Q_DDCDATA CRT_Q_HSYNC CRT_Q_VSYNC CRT_Q_DDCCLK
CN3050 P1 P2 P3 P4
C
P5 P6 P7 P8 P9 P10 P11 P12 P13 P14
G1
P15
G2
G1 G2
T-CONN_T21_0024_1A30_0_15P
REFERENCE NUMBER:3050~3099 P5V0A
CRT
2 36
DP_EN
IN
2
1
Q3300
S1
G1
36
DDC_EN
6 3
IN
2
D1 D2
36
DPD0_DP
IN
1
2 C3300 0.1UF_16V_2
36 36
DPD0_DN DPD1_DP
IN IN
1 C3307
2 C3301 0.1UF_16V_2 0.1UF_16V_2
36 36
DPD1_DN DPD2_DP
IN IN
36 36
DPD2_DN DPD3_DP
IN IN
1
IN
1
36 G2
5
DPD3_DN
1
2
DPD0_C_DP 1 2 DPD0_C_DN 3 DPD1_C_DP 4 5 DPD1_C_DN 6 DPD2_C_DP 7 8 DPD2_C_DN 9 DPD3_C_DP 10 11 DPD3_C_DN12 13 14 15 16 17 18 19 20
C3306 0.1UF_16V_2 1 2 C3302 0.1UF_16V_2 1 2 C3303 0.1UF_16V_2 C3305 2 0.1UF_16V_2 2 C3304 0.1UF_16V_2
1
2
4 S2
2N7002DW 36
IN
36 42
MB_DPD_CONN#42
MB_DP_AUXP_CONN
IN
MB_DP_AUXN_CONN MB_DPD_CONN#
IN IN
P5V0S
OC#
TP30
1 R3302
EN
1 TP3300
8 7 6 5
2
1 OUT
1M_5%_2
OUT
IN
B
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
G1
18
G2
19
G3
20
G4
G1 G2 G3 G4
A
1
ROHM_BD82024FVJ_TSSOP_8P
2
1UF_6.3V_2
DPD_HPD 36
2
IN
OUT
IN
10UF_6.3V_3 C3308 2 1
C3311
1
IN 1UF_6.3V_2
SLP_S3#_3R
9
2
57 55 48 45 42 35 27 21 20 19 18
GND
C3310
S
SSM3K7002FU
U3300
2
1 2 3 4
G
R3304
3
P3V3S
D
1
1 2
TYCO_2023333_3_20P
Q3301
A
CN3300
5.1M_5%_2
0_5%_2
1 R3303
0_5%_2
1
R3305
P5V0A
B
INVENTEC
DISPLAY PORT CNTR
TITLE
MODEL,PROJECT,FUNCTION CRT & DP
REFERENCE NUMBER:3300~3399
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
42
80
of
1
X01
7
6
5
4
3
P3V3S_LCDVDD 1 R3001 2 100_5%_2
D
P3V3S_LCDVDD
1.5A 1
PVBAT
C3003
GND EN
1 2 3
C3010 2
OUT
36
IN R3003 1 100K_5%_2
DIS
NUVO_NCT3521U_SOT23_5P
43 43
C R3004 43
2
36
43
1
4.7K_5%_2 R3005 2 1
LVDS_DDC_DATA IN 36
P3V3S
CN3000
P3V3S
LVDS_DDC_CLK IN
D
LVDS_VDD_EN
2
C3006 2 1 1UF_6.3V_2
IN
4
4.7UF_6.3V_3
2
TP30 U3000
4.7UF_25V_5
680PF_50V_2 C3021 2 1
1 C3019 2
56PF_50V_2 C3020 2 1
TP3301 1
5
1
1
P3V3S
2
68PF_50V_2
8
4.7K_5%_2
36 36
LVDS_DDC_CLK LVDS_DDC_DATA
IN IN
36 36
LVDSB_CLK_DP LVDSB_CLK_DN
IN IN
36 36
LVDSB_DATA0_DP LVDSB_DATA0_DN
IN IN
36 36
LVDSB_DATA1_DP LVDSB_DATA1_DN
IN IN
36 36
LVDSB_DATA2_DP LVDSB_DATA2_DN
IN IN
36 36
LVDSA_DATA0_DN LVDSA_DATA0_DP
IN IN
36 36
LVDSA_DATA1_DN LVDSA_DATA1_DP
IN IN
36 36
LVDSA_DATA2_DN LVDSA_DATA2_DP
IN IN
LVDSA_CLK_DN LVDSA_CLK_DP
IN IN
36 36
PVBAT
2
BAT54_30V_0.2A
1.5A
61
48
LID_SW#_3
NC
D3000 3
IN
B 1
IN
2
R3008
1
L_BKLT_EN
R3009 2
100K_5%_2
36
1 36
INV_PWM_3
IN
C3008 680PF_50V_2 1
2
2K_5%_2
P3V3S C3505 18PF_50V_2 2 1
57 57
DMIC_CLK IN DMIC_DAT IN
37 CAMERA_ON
P5V0S 37 37
1 4
USB_P10_DP IN USB_P10_DN IN
IN
L3000
2 3
USB_P10_L_DP USB_P10_L_DN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1 2 3 4 5 6 7 8 9 10 11 12 13
C
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
B
36 37 38 39 40 41 42 43 44 45 46 47
G1
48
G2
49
G3
50
G4
G1 G2 G3 G4
1 C7676 2
33PF_50V_2
ACES_50473_0500S_002_50P
68PF_50V_2
0.1UF_16V_2 C3016 2 1
0.01UF_50V_2 C3015 2 1
47PF_50V_2 C3014 2 1
1UF_6.3V_2 C3013 2 1
1 C3011 2
A
4.7UF_6.3V_3 C3012 2 1
WCM_2012_900T
A
INVENTEC TITLE
REFERENCE NUMBER:3000~3049
MODEL,PROJECT,FUNCTION LCM & WEBCAM
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
43
80
of
1
X01
8
7
6
5
33 33
D
33 33
4
IN IN
SATA_TX0_C_DP SATA_TX0_C_DN
SATA_RX0_C_DN OUT SATA_RX0_C_DP OUT
3
0.01UF_50V_21 0.01UF_50V_21
2C1705 SATA_TX0_DP 2C1704 SATA_TX0_DN
0.01UF_50V_21 0.01UF_50V_21
2 C1702 SATA_RX0_DN 2C1703 SATA_RX0_DP
P5V0S 1 C1701 2
4.7UF_6.3V_3
1 C1700 2
68PF_50V_2
1.3A
S1 S2 S3 S4 S5 S6 S7 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
2
1
CN1700 GND A+ AGND
D
BB+ GND V3.3 V3.3 V3.3 GND GND GND V5 V5 V5 GND RESERVED GND V12 V12
G
V12
G
G1 G2
HDD ( CN1700 ) : P/N 6012B0449501 HDD TRANSFOR CNTR ( CN1701 ) : P/N 6012B0451301
ALLTOP_SK_C11841_22P
C
C
REFERENCE NUMBER:1700~1749
SATA HDD
P3V3S
1
68PF_50V_2
C1957 2
1 C1956
2
B
10UF_6.3V_3
903MA
NOTE : SWAP SATA_RXP2 AND SATA_RXN2 ON CN1950 PIN 23 AND 25 FOR INTEL SSD 310 SERIES PRODUCT PINDEFINTION
33 33
33 33
SATA_RX1_C_DP OUT SATA_RX1_C_DN OUT
0.01UF_50V_2 2 SATA_RX1_DP C1950 1 2 SATA_RX1_DN C1951 1 0.01UF_50V_2 0.01UF_50V_2 2 SATA_TX1_DN C1952 1 2 SATA_TX1_DP C1953 1
SATA_TX1_C_DN IN SATA_TX1_C_DP IN
0.01UF_50V_2
A 3
D
MSATA_CD# OUT
Q1950 S
38
2
37
33
PLT_RST#
IN
1
G
SSM3K7002FU_DY
72 51
B
CN1950 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 G1
WAKE#
3.3V
RESERVED
GND
RESERVED
1.5V
CLKREQ#
RESERVED
GND
RESERVED
REFCLK-
RESERVED
REFCLK+
RESERVED
RESERVED
RESERVED
RESERVED
GND
RESERVED
RESERVED
GND PERN0
PERST# +3.3VAUX GND
PERP0 GND GND PETN0
1.5V SMB_CLK SMB_DATA
PETP0
GND
GND
USB_D-
RESERVED
USB_D+
RESERVED
GND
RESERVED
LED_WWAN#
RESERVED
LED_WLAN#
RESERVED
LED_WPAN#
RESERVED
1.5V
RESERVED
GND
RESERVED
3.3V
G1
G2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 G2
A
FOX_AS0B226_S40QW_7H_52P
MSATA
INVENTEC TITLE
REFERENCE NUMBER:1950~1999
MODEL,PROJECT,FUNCTION SATA HDD & M-SATA
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER 1310xxxxx-0-0 SHEET
44
of
80
1
CNTR
REV X01
8
7
6
5
R2512 2
4
3
2
1
17.8K_1%_2 1
R2511 2 1 20K_5%_2
P5V0A_CHG
2
17 16 15 14 13 IN
DM_IN DP_IN
EN CTL1 CTL2 CTL3
STATUS#
12 11 10 9
1
C2512
R2511
2
TP2512 TP30
BI BI
TPS2543 TPS2540/A PI5USB2543
USB_P1_U_DN 59 USB_P1_U_DP 59
R2515
R2514
20K
10K
NI
NI
NI
0
D
TEXAS_TPS2543RTER_QFN_16P
IN IN IN
5 6 7 8
0.1UF_16V_2
C2514 2
OUT
DP_OUT ILIM_SET
1
100UF_6.3V
DM_OUT
P5V0A_CHG 1
R2514 1
2.5A
PWPD ILIM_HI ILIM_LO GND FAULT#
1 C2513
2
0_5%_2
R2515 1
BI BI 2
USB_P1_DN USB_P1_DP
1 2 3 4
0_5%_2_DY
37 37
P5V0A_USB_CHARAGE
U2511
+
D
47UF_6.3V_5
P5V0A_CHG
CPPWR_EN 9 48 SLP_S4#_3R 10 SLP_S3#_3R 9
18 21 35 45 19 18 20 21 27 35 42 48 55
REFERENCE NUMBER:2511~2599
57
P5V0A_USB0
1.8A
P5V0A_USB0
2
P5V0A
OUT
IN
OUT
EN
OC#
8 7 6 5
2
B
2
C2415
1
22UF_6.3V_5 C2412 2 1
18 10
1UF_6.3V_2
ROHM_BD82024FVJ_TSSOP_8P 45 35 21
TP2400 TP30
1
1
OUT
IN
22UF_6.3V_5
IN
GND
C2401
SLP_S4#_3R
U2400
1 2 3 4
37 37 37 37 37 37
USB_P2_DN USB_P2_DP
4 1
BI BI
USB30_RX3_DN USB30_RX3_DP
OUT OUT
USB30_TX3_DN USB30_TX3_DP
IN IN
L2400
C
1000PF_50V_2_DY
C2402
P5V0A
0.1UF_16V_2 C2403 2 1
1
C
USB_P2_L_DN USB_P2_L_DP
3 2
WCM_2012_900T 0.1UF_16V_2 2 USB30_TX3_C_DN C2404 1 2 USB30_TX3_C_DP C2405 1 0.1UF_16V_2
1 2 3 4 5 6 7 8 9
CN2400 VBUS DD+ PGND SSRXSSRX+ GND SSTXSSTX+
G G G G
G1 G2 G3 G4
B
SINGA_2UB1585_000121F_9P
USB RIGHT1 P5V0A_USB1
1.8A
OC#
1UF_6.3V_2
2
22UF_6.3V_5 C2414 2 1
21
C2408
1 OUT
1
TP2401 TP30
2
IN EN
8 7 6 5
22UF_6.3V_5
OUT
1
OUT
IN
C2411
GND
ROHM_BD82024FVJ_TSSOP_8P
C2413
A
IN
10
1
45
35
U2401
2
SLP_S4#_3R 18
1 2 3 4
37 37 37 37 37 37
USB_P3_DN USB_P3_DP
USB30_RX4_DN USB30_RX4_DP USB30_TX4_DN USB30_TX4_DP
BI BI OUT OUT IN IN
L2404 4 1
3 2
1000PF_50V_2_DY
P5V0A_USB1
0.1UF_16V_2 C2409 2 1
P5V0A P5V0A
USB_P3_L_DN USB_P3_L_DP
WCM_2012_900T 0.1UF_16V_2 2 USB30_TX4_C_DN C2406 1 2 USB30_TX4_C_DP C2407 1 0.1UF_16V_2
1 2 3 4 5 6 7 8 9
CN2401 VBUS
A
DD+ PGND SSRXSSRX+ GND SSTXSSTX+
G G G G
G1 G2 G3 G4
INVENTEC
SINGA_2UB1585_000121F_9P
TITLE
USB RIGHT2
MODEL,PROJECT,FUNCTION USB &
REFERENCE NUMBER:2400~2499
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
USB CHARGER
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
45
80
of
1
X01
8
7
6
5
4
3
2
1
D
D P3V3ALW 2
2
P3V3A
R2210
R2211
34
FPR_OFF
1 C2200 2
0.1UF_16V_2
1 C2201
4.7UF_6.3V_3
2
2
R2201
0_5%_2
1
TP30
46 48
0_5%_2_DY
1
TP2201 1
1
0_5%_2
IN
C
C
19MA
48 46
USB_P8_DP USB_P8_DN
FPR_OFF
1 2 3 4 5 6
IN
BI BI D2201 2
38
FPR_LOCK#
CN2200 ACES_51571_0064N_001_6P 1 2 3 4 5
G1
6
G2
G1 G2
IN
1
2
PHP_PESD5V2S2UT_SOT23_3P_DY
R2200
1
3
0_5%_2
37 37
34
B
B
FINGER PRINT CONN
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION FINGER
REFERENCE:2200~2249
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
PRINTER
DOC.NUMBER SHEET
46
80
of
1
CNTR
REV
1310xxxxx-0-0
X01
8
7
6
5
4
3
2
1
D
D
2
VDD_IO
GND
NC1
INT1
NC1
RES
SCL_SPC
INT2
GND
1 2 3 4 5
R1004 1
1
2
R1002 0_5%_2
R1003 0_5%_2 1 2
1 1
0_5%_2_DY 2
IN IN
PCH_3S_SMCLK 34 THERM_CLK
BI BI
34 THERM_DATA 29 PCH_3S_SMDATA
32 34 56 29 22
ST_HP3DC2TR_LGA_16P
8 7 6
P3V3S
RES
RES
RES
SDA_SDI_SDO
ACCEL_INT#
SDO_SA0
47
IN
CS
37
ACCEL_INT#
VDD
U1000 13 12 11 10 9
C
10UF_6.3V_3
14 15 16
C1001
1
C
0.1UF_16V_2 C1000 2 1
P3V3S
R1001
2
R1005
2
22 56 32 34
0_5%_2_DY
0_5%_2_DY
B
1
B
2
R1000
0_5%_2_DY
ACCELEMETOR
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION
REFERENCE NUMER : 1000~1099
ACCELEMETOR
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
47
80
of
1
X01
5
ADC_VREF_1126
IN
R301
10_5%_2 2
1
AGND_KBC 20
48 ADP_A_ID 50 48 50 33
33
48 56
1
100PF_50V_2 1 2 300_5%_2 R300
ADP_A_ID
IN
48
2
C300
PCI_3S_SERIRQ
BI
LPC_3S_AD(0..3) 1
R310
2
SHORT_0603_25 R311 1 2
1 C301 2
2200PF_50V_2
C306 2
7
2 C307
7 6 6 48 48 33
IN IN
1
R316
OCP_A_IN 1
2 2
35
CLK_R3S_KBPCI LPC_3S_AD(3) LPC_3S_AD(2) LPC_3S_AD(1) LPC_3S_AD(0) LPC_3S_FRAME# LPC_RESET#
IN
LATCHED_ALARM IN MAIN_BAT_DET# IN IN SPI_CLK_FLH 53 48 WLAN_OFF OUT 5 ADP_DET IN 56 48 IM_5S_DATA OUT 54 48 WWAN_OFF OUT 19 IN SLP_LAN# 48 21
MAIN_BAT_DET# WLAN_OFF IM_5S_DATA WWAN_OFF SLP_LAN#
300_5%_2 300_5%_2 56 48
R315
OUT SLP_S4#_KBC OUT RUNSCI0#_3 PCI_3S_CLKRUN# IN
IN IN
48
2200PF_50V_2 1
CURRENT_ADC OCP_A_IN 48
3 2 1 0
33 LPC_3S_FRAME# LPC_RESET#
50 48 38
SHORT_0603_25
7
P3V3AL 18 55 SLP_S4#_KBC 48 48 RUNSCI0#_3 38 35 50 48 PCI_3S_CLKRUN#
LPC_3S_AD(0..3)
B
OUT
IM_5S_CLK
2 1 37 33_5%_2 R333 48 CLK_R3S_KBPCI
BI
IM_5S_CLK
SP_DATA 5 48 ADP_EN 43 48 61 LID_SW#_3 TRAVEL_BAT_DET#
1
2200PF_50V_2
SP_DATA ADP_EN LID_SW#_3
BI OUT IN IN
KOS04 KOS06
PWM_CHRGCTL
KOS07
GPIO01
KOS08
VREF_PECI
KOS09
GPIO3-PECI_DATA
KOS10
GPIO04
KOS11
GPIO05
KOS12
OUT1-RSMRST#
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 ADC_VREF ADC2_GPIO40
R367 2 SPI_SO_FLH_R SPI_SO_FLH 33_5%_2 1
IN
GPIO09
IMCLK VSS7 AVCC
GPIO11 GPIO012 GPIO013 GPIO014 GPIO015 GPIO16-TACH2PWM_IN GPIO017 KCLK GPIO020 GPIO021 GPIO024 GPIO025
ADC4-GPIO50
GPIO026
NEC_SCI CLKRUN# SER_IRQ
ADP_PRES-CKT#2-GPIO27 GPIO028 GPIO029
PCI_CLK
GPIO030
LAD3
GPIO031
LAD2
GPIO32-AB3_CLK
LAD1
AB1A_CLK
LPC Bus
LAD0
Access Bus Intreface
LFRAME#
AB1A_DATA AB1B_CLK
LRESET#
AB1B_DATA PWMOK_PWMDEAD#-CKT#2-GPIO
AVSS ALARM_CKT#2_GPIO36
32KHZ_INPUT
HSTCLK_GPIO41
ADC_TO_PWM_OUT-GPIO19
FLCLK
32KHZ_OUT-GPIO22 NRESET_OUT
GPIO39
TEST_PIN
AC-CKT#2-GPIO42
VCC1_RST#
IMDAT
Miscellaneous
GPIO38
NBAT_LED NPWR_LED
GPIO37 ADC1_GPIO46
NFDD_LED
ADC_TO_PWM_IN
CFETB_GPIO10
KDAT
PWEGD
GPIO35
FLDATAIN
GPIO34
HSTCS0#_GPIO44
Q_GPIO33 EMCLK EMDAT HSTDATAIN_GPIO43
FLCS0# HSTDATAOUT_GPIO45 FLDATAOUT
1 R375
2 100_5%_2
1 R376 1 R377 1 R378
2 100_5%_2 2 100_5%_2 2 100_5%_2
SPI_CLK_FLH_R6_R SPI_CS0#_FLH_R6_R SPI_SI_FLH_R6_R SPI_SO_FLH_R6_R
R375,R376,R377,R378 CLOSE TO KBC
2 1 124 0_5%_2 5 48 R306 125 CHARGER_DAT D300 BAT54_30V_0.2A OUT CHARGER_DAT 123 FET_A IN FET_A 486 3 1 122 OUT PM_3S_KBCCPURST# 38 121 PWM_3S_FAN# 22 48 OUT PWM_3S_FAN# 120 BAT_GRNLED# 48 33 56 OUT BAT_GRNLED# P1V05S_VCCP 118 OUT PWM#_LED49 45 CPPWR_EN OUT 107 48 0_5%_2 CPPWR_EN 9 2 R356 1 79 243_5%_2 80 38 R328 1 P3V3AL OUT H_PECI 23 81 SLP_S3#_3R 45 57 48 IN SLP_S3#_3R 4218 35 19 21 27 55 9 20 1 R320 2 100K_5%_2 83
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
D
20 21
25
22
26
G1 G2
23 24
DEBUG PORT
85 NUM_LOCK_LED# 48 OUT NUM_LOCK_LED# 2 0_5%_2 RSMRST# 86 FPR_OFF_K 1 0_5%_2_DY 2 R309 49 R330 1 OUT RSMRST# 18 33 35 IN FPR_OFF 46 34 87KBC_WAKE# 1 0_5%_2_DY 2 R302 OUT PCIE_WAKE#54 53 35 R329 1 2 88 PCH_KBC_SMDATA 48 73 48 IN PCH_KBC_SMDATA 34 0_5%_2 89 PCH_KBC_SMCLK IN PCH_KBC_SMCLK 34 73 48 90 KBC_PROCHOT OUT KBC_PROCHOT 48 23 91 A_SD# OUT A_SD# 48 57 92 OUT MEM_1V5 10 101 TACH_FAN_IN_1126 22 48 IN TACH_FAN_IN_1126 102 EC_3S_A20GATE IN EC_3S_A20GATE 38 48 61 SP_CLK BI SP_CLK 56 48 103 105 4 PWR_BTN_OUT# 33 35 49 OUT 48 PWR_BTN_OUT# 73 PWRBTN_1126# IN PWRBTN_1126#48 49 108 SCAN_3S_OUT(17) OUT SCAN_3S_OUT(17) 61 48 74 ADP_PRES 7ADP_PRES 48 IN P3V3AL 93 PM_SLP_A# 19 20 21 35 48 IN PM_SLP_A# 18 35 98 SUS_PWR_ACK IN SUS_PWR_ACK 48 R326 100K_5%_2 99 ADP_PRES_OUT P3V3AL OUT ADP_PRES_OUT 35 2 1 100 48 OUT KBC_PWR_ON 9 P3V3AL 126 CHARGER_CLK OUT CHARGER_CLK R340 1 2 KBC_GPIO22 112 SCL_MAIN 48 6 5 48 18 R307 BI IN 2 1 SCL_MAIN 111 SDA_MAIN 10K_5%_2_DY BI SDA_MAIN 6 48 0_5%_2 110 SCL_MBAY 48 BI SCL_MBAY 0_5%_2 109 SDA_MBAY 48 R3172 BI 1 SDA_MBAY VCC1_POR#_3 ADP_EN IN IN 70 9 48 48 5 OUT KBC_GPIO51 35 R3142 1 71 SUSCLK32_KBC LID_SW#_3 100K_5%_2 10K_5%_2_DY R342 IN SUSCLK32_KBC 48 IN 61 48 43 1 2 59 OCP_PWM_OUT R3222 OUT OCP_PWM_OUT 1 LED_PWRSTBY#0_5%_2 48 55 IN 56 61 75 38 OUT KBC_GPIO22 48 18 48 23 R3242 60 PM_PWROK 1 CAPS_LED# 0_5%_2 48 IN 49 OUT 48 PM_PWROK33 35 69 2 1 1K_5%_2 R327 R3252 VCC1_POR#_3 0_5%_2 1 48 IN 77 48 IN VCC1_POR#_3 56 113 BAT_AMBERLED# OUT BAT_AMBERLED# 48 115 OUT LED_PWRSTBY# 61 56 48 55 114 48 OUT CAPS_LED# 49 116 FET_B IN FET_B 48 P3V3A 78 PWR_GOOD_3 23 48 20 IN PWR_GOOD_3 18 1 2 95 SPI_SO_FLH 48 OUT 33 1 96 R319 10K_5%_2_DY TP1121 97 SPI_CS0#_FLH OUT 48 1 R331 2 SPI_CS0#_FLH 33 IN 127 OUT CHG_RST 48 33 100K_5%_2_DY 128 SPI_SI_FLH OUT 48 1 2 5 33 0_5%_2 R308
1
P3V3AL
KBC_WAKE# OUT
C
B
CE# SO
VDD HOLD#
WP#
SCK
VSS
SI
P3V3S
2
8 7 6 5
SPI_HOLD#_DB SPI_CLK_FLH SPI_SI_FLH
IN IN IN
SPI_HOLD#_DB 48 48 SPI_CLK_FLH 33 SPI_SI_FLH 33 48
56
48
IM_5S_CLK
56
48
IM_5S_DATA
56
48
SP_CLK
56
48
SP_DATA
7
BI BI BI BI
1
R385
2
4.7K_5%_2
1
R386
2
4.7K_5%_2
1
R387
2
4.7K_5%_2
1
R388
2
4.7K_5%_2
INVENTEC
ACES_91960_0084L_8P C366
FET_A C319
2
0.1UF_16V_2
SPI BIOS
68PF_50V_2_DY
FET_B
A
P5V0S
3.3K_5%_2
CN365 1 2 3 4
P3V3AL
R323
0_5%_2 1
R305 1 2 100K_5%_2 R304 1 2
TITLE
MODEL,PROJECT,FUNCTION KBC & SPI
100K_5%_2
FOR RF
SIZE A3
CHANGE by
8
IN IN IN IN IN
LED_PWRSTBY# CAPS_LED# NUM_LOCK_LED# VCC1_POR#_3
BI BI IN
2
16M ROM SOCKET(CN365):6026B0150101 16M_8P_MICRO N25Q128A13ESEC0F(U365):6019B0988601
72
2 1
R368
2
SPI_WP#
GPIO08
1
48
OUT8 OUT10
TP1120
1
R365,R366,R367 CLOSE TO SPI
1 0_5%_2_DY R370
33
2 1 3.3K_5%_2
R369
A
IN OUT
CFETA_OUT7_NSMI OUT9-TACH2PWM_OUT
KOS05
KOS13
SPI_CLK_FLH SPI_CS0#_FLH SPI_SI_FLH SPI_SO_FLH SPI_HOLD#_DB
61 55 48 49 48
LPC_3S_FRAME# PCI_3S_SERIRQ BUF_PLT_RST# NMI_SMI_DBG# LPC_3S_AD(0) LPC_3S_AD(1) LPC_3S_AD(2) LPC_3S_AD(3)
IN IN IN OUT IN BI BI BI
CN375
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SMSC_KBC1126_VTQFP_128P
AGND_KBC
48 33
OUT0 GPIO53-AB3_DATA
CLK_R3S_DEBUG
2
VCC10 ADC3-GPIO23 VCC12 VCC13 VCC14 VCC15 VCC2 CAP VCC0
KOS03
P3V3A
SPI_CS0#_FLH SPI_SO_FLH
14 39 58 84 106 119 49 15 68
KOS02
Genrel Purpose I/O Interface
48 9 ADC_VREF_1126
SCAN_3S_IN(0) SCAN_3S_IN(1) SCAN_3S_IN(2) SCAN_3S_IN(3) SCAN_3S_IN(4) SCAN_3S_IN(5) SCAN_3S_IN(6) SCAN_3S_IN(7)
0 1 2 3 4 5 6 7
KOS01
GPIO52-PWM3
SCAN_3S_IN(7..0)
IN
KOS00
VSS0 VCC11 VSS2 VSS3 VSS4 VSS5 VSS6
49 SCAN_3S_IN(7..0)
21 20 19 18 17 16 13 12 10 9 8 7 6 5 29 28 27 26 25 24 23 22 41 42 35 36 40 38 76 55 57 54 51 50 48 46 52 53 45 1 2 3 30 31 32 33 34 43 44 62 63 64 65 66 67 94
33 33 33 33
NMI_SMI_DBG# NMI_SMI_DBG#OUT 37 P3V3AL 48
U300
SCAN_3S_OUT(0) SCAN_3S_OUT(1) SCAN_3S_OUT(2) SCAN_3S_OUT(3) SCAN_3S_OUT(4) SCAN_3S_OUT(5) SCAN_3S_OUT(6) SCAN_3S_OUT(7) SCAN_3S_OUT(8) SCAN_3S_OUT(9) SCAN_3S_OUT(10) SCAN_3S_OUT(11)
0 1 2 3 4 5 6 7 8 9 10 11
LPC_3S_FRAME# PCI_3S_SERIRQ BUF_PLT_RST# NMI_SMI_DBG# LPC_3S_AD(0) LPC_3S_AD(1) LPC_3S_AD(2) LPC_3S_AD(3)
49 48 48 48 48 48
VADP_DEBUG
VADP_DEBUG OUT CLK_R3S_DEBUG IN
56 48
11 37 47 56 82 104 117
48
SCAN_3S_OUT(11..0)
OUT
SCAN_3S_OUT(11..0)
68PF_50V_2
10K_5%_2_DY 2
Keyboard / Mouse Interface
R303 1
50
48 37 48 37 50 48 33 50 33 48 33 50 48 50 48 33
1
NC
1
0.1UF_16V_2 C317 2 1
P3V3AL
C
0.1UF_16V_2
0.1UF_16V_2 2 C310 1
60 54 53 23
68PF_50V_2
TP332 TP30
1
P3V3_RTC
C312 2 1 0.1UF_16V_2 2 1 C311 1UF_6.3V_2 C302 2 1
2
D
48
C308
5
50 48 33 50 33 48
Power Mgmt SIRQ
P3V3AL
48 9 48 37
IN
FOR RF
0.1UF_16V_2 2 C315 1
0.1UF_16V_2 2 C314 1
1
0.1UF_16V_2 2 C131 1
1 2
2 C303
68PF_50V_2_DY
2
P3V3S
P3V3AL
10MA C316
3
0.1UF_16V_2 C320 2 1
REFERENCE NUMER : 300~399
4
ACES_50238_02471_001_24P
6
4.7UF_6.3V_3 C309 2 1
7
VOLTAGE_ADC 9
8
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
48
80
of
1
X01
7
6
5
4
3
2
REFERENCE NUMER : 300~389
1
IN
G
S
REC_MUTE_LED_CNTR
2
57
OUT OUT OUT OUT OUT OUT
SSM3K7002FU
2
R383
1
0_5%_2 49 6149
49
C
49 49 61 49 49 49 49
OUT OUT OUT OUT OUT OUT OUT OUT OUT
KSCAN_3S_IN(3) KSCAN_3S_IN(1) KSCAN_3S_IN(2) KSCAN_3S_IN(4) KSCAN_3S_IN(0) KSCAN_3S_IN(10) KSCAN_3S_IN(12) KSCAN_3S_IN(8) KSCAN_3S_IN(14)
0_5%_2 R352 1
0_5%_2 R353 1
2
2
0_5%_2 R354 1
0_5%_2 R351 1 2
2
0_5%_2 R350 1 2
R347 1 0_5%_2 R349 1 2
SCAN_3S_IN(1)
4
SCAN_3S_IN(2)
5 SCAN_3S_IN(3)
6 7
SCAN_3S_IN(4)
8 SCAN_3S_IN(5)
9 10
SCAN_3S_IN(6)
11
1 2
D
3 4 5 6 7
SCAN_3S_IN(7)
12
49 SCAN_3S_IN
OUT
13
48
SCAN_3S_IN
14 15 16 17 18
KSCAN_3S_IN(14)
19 20
P3V3S
21 22
D301
23 24
1
D
Q320
KSCAN_3S_IN(9) KSCAN_3S_IN(11) KSCAN_3S_IN(13) SCAN_3S_IN(7) KSCAN_3S_IN(6) KSCAN_3S_IN(5)
SCAN_3S_IN(0)
3
25 26
3 SCAN_3S_IN(6)
C305
3
49 49 49 49 48 49 49
2 R381 270_5%_2
1
2
27 28 29
2
1
0
CN260
30 31
G
32
G
G1 G2
0.1UF_16V_2
NUM_LOCK_LED# IN
REC_MUTE_LED
1 2 3 4 5 SCAN_3S_OUT(9) 6 7 KSCAN_3S_IN(9) KSCAN_3S_IN(11) 8 KSCAN_3S_IN(13) 9 SCAN_3S_IN(7) 10 11 KSCAN_3S_IN(6) 12 KSCAN_3S_IN(5) SCAN_3S_OUT(1) 13 SCAN_3S_OUT(10)14 SCAN_3S_OUT(6) 15 SCAN_3S_OUT(7) 16 SCAN_3S_OUT(4) 17 SCAN_3S_OUT(8) 18 SCAN_3S_OUT(3) 19 20 KSCAN_3S_IN(3) 21 KSCAN_3S_IN(1) 22 KSCAN_3S_IN(2) 23 KSCAN_3S_IN(4) 24 KSCAN_3S_IN(0) KSCAN_3S_IN(10) 25 KSCAN_3S_IN(12) 26 27 KSCAN_3S_IN(8) KSCAN_3S_IN(14) 28 SCAN_3S_OUT(5) 29 SCAN_3S_OUT(2) 30 SCAN_3S_OUT(0) 31 32 SCAN_3S_OUT(11)
1
IN
C
DAP202KGT146
2
D
CAPS_LED#
2
R348 1 2
48
0_5%_2
P3V3AL
P3V3S
48
1
0_5%_2
8
KSCAN_3S_IN(6)
JOINT_F0803WR_S_32PNLNT1T00L_32P
2
R101
1
100K_5%_2
P3V3AL
IN
1
2
47_5%_2
C100
5 KSCAN_3S_IN(5) 4 KSCAN_3S_IN(13)
3
2
SCAN_3S_IN(5)
1
ON_OFF#
1K_5%_2
ON_OFF#
PWRBTN_1126# 48
OUT
D100 3
B
2
49 21
R103
2
55
SCAN_3S_IN(4)
2
KSCAN_3S_IN(12)
6
1
1
NC
D303
KSCAN_3S_IN(4)
1UF_6.3V_2
61
B
P3V3A
R100
1
OUT
PWR_BTN_OUT#
33 35
48
DIODE-BAT54-TAP-PHP_DY
BAW56S
P5V0S SCAN_3S_IN(2)
R9420 1
KSCAN_3S_IN(10) 2
Q9400
4 KSCAN_3S_IN(11)
1
BAW56S
2
G
6
SCAN_3S_IN(0)
SSM3K7002FU
2
KSCAN_3S_IN(8)
1
S
D302 1
IN
3
D
PWM#_LED
A KSCAN_3S_IN(0)
G
38
5 KSCAN_3S_IN(1)
SCAN_3S_IN(1)
4 KSCAN_3S_IN(9)
3
TP9400 TP30
SSM3J327R
Q9401
GPIO16
IN
1
3
3
SCAN_3S_IN(3)
2
4.7K_5%_2
5 KSCAN_3S_IN(3)
2
6
S
D304 1
D
KSCAN_3S_IN(2)
1 2 3 4 5 6 7 8
CN9415 1
A
2 3 4 5 6
G
7
G
G1 G2
8
HIROSE_FH34SRJ_8S_0_5SH_50_8P
INVENTEC
NOTE: GPIO16_SM FOR KEYBOARD LIGHT DETECT
BAW56S
TITLE
MODEL,PROJECT,FUNCTION KEYBOARD
KEYBOARD BACK LIGHT CNTR CHANGE by
8
7
6
5
4
XXX
3
SIZE A3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
49
80
of
1
X01
7
6
5
4
3
2
P3V3AL
P3V3A
2
2
P3V3S
D
R3511
R3516
0_5%_2_DY
0_5%_2_DY
1
2
8
D R3510
0_5%_2
1
INSTALL FOR SLB9635 NO INSTALL FOR SLB9656
R3508
48 33 50
IN IN
PCI_3S_SERIRQ
PCI_3S_CLKRUN#
35 48
1
INSTALL FOR SLB9635 NO INSTALL FOR SLB9656
R3509
BUF_PLT_RST# 16
LPCPD#
27 15 2 PCI_3S_L_CLKRUN#
SERIRQ
NC
CLKRUN#
NC
1 R3513 0_5%_2
9
BUF_PLT_RST#_R 1
8
XTALI GPIO
TESTI
GPIO2
4 11 18 25
1
0_5%_2_DY
7 1 3 12 13 14 6 2
R3512
P3V3S
2
1
R3514
INFINEON_SLB9635TT1_2FW3_19_TSSOP_28P
INSTALL FOR SLB9656 NO INSTALL FOR SLB9635
0_5%_2_DY
TESTBI_BADDR
2
0_5%_2_DY
2
PP NC
XTALO
R3507
2
R3515
GND
LRESET#
28
PCI_3S_SERIRQ
4.7K_5%_2 INSTALL FOR SLB9635 NO INSTALL FOR SLB9656
GND
LFRAME#
GND INSTALL FOR SLB9635
10 2 19 24
LCLK
22 LPC_3S_FRAME#
2 0_5%_2NO INSTALL FOR SLB9656
2
1
VDD
GND
BUF_PLT_RST# IN 54
LAD3
R3501 0_5%_2_DY
2
53 50 48 37 23 60
5
C 1
C3501
NC
C3507
1
2 R3502
18PF_50V_2
0_5%_2_DY
X3500
2
33
LPC_3S_FRAME# IN
10PF_50V_2_DY
LAD2
0.1UF_16V_2
48
VSB
LAD1
0.1UF_16V_2 C3506 2 1
50
2
P3V3S
LAD0
VDD
CLK_R3S_TPM 21
CLK_R3S_TPM IN
C
26 23 20 17
LPC_3S_AD(0) LPC_3S_AD(1) LPC_3S_AD(2) LPC_3S_AD(3)
IN IN IN IN
4 3
LPC_3S_AD(0) LPC_3S_AD(1) LPC_3S_AD(2) LPC_3S_AD(3)
32.768KHZ C3508
1 2
33 33 33 33
1
50 37
48 48 48 48
C3502 2 1 0.1UF_16V_2 C3504 2 1
50 50 50 50
0.1UF_16V_2
P3V3S
INSTALL FOR SLB9656 NO INSTALL FOR SLB9635
U3500
C3503
1
1
1
INSTALL FOR SLB9656 NO INSTALL FOR SLB9635
1
TPM1.2
2
18PF_50V_2 INSTALL FOR SLB9635 NO INSTALL FOR SLB9656
1
1
0_5%_2
INSTALL FOR SLB9635 NO INSTALL FOR SLB9656
B
B
SLB9656TT1.2 SLB9635TT1.2
A
R3507
INSTALL
OPEN
R3508
OPEN
INSTALL
R3509
OPEN
INSTALL
R3510
OPEN
INSTALL
R3511
INSTALL
OPEN
R3512
OPEN
INSTALL
R3513
OPEN
INSTALL
R3514
INSTALL
OPEN
X3500
OPEN
INSTALL
C3507
OPEN
INSTALL
C3508
OPEN
INSTALL
A
INVENTEC TITLE
REFERENCE NUMER : 3500~3549
MODEL,PROJECT,FUNCTION TPM
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
50
80
of
1
X01
8
7
6
5
4
3
2
1
REFERENCE NUMER : 400~469
D
D
38 39
PETp PETn
MDI_MINUS2
IN IN
41 42
PERp
MDI_PLUS3
PERn
MDI_MINUS3
PCH_3M_SMCLK BI PCH_3M_SMDATA BI
PCH_3M_SMCLK 28 PCH_3M_SMDATA 31 R405 1
RSVD_NC
RSVD_VCC3P3_1 RSVD_VCC3P3_2 VDD3P3
P3V3M
R407 1 1 R406
43 11
1
P1V05_LAN P1V05_LAN
XTAL_OUT XTAL_IN
RBIAS
TP30 TP410
2 R401 1 3.01K_1%_2
12
VDD1P0_8
CTRL_1P0 VSS_EPAD
7
TP30 TP411
L410
1 2 SWF2520CF_4R7K_M
22UF_6.3V_5
P1V05_LAN
49
2
C409
1
ITL_82579_PQFN_48P
1
VDD1P0_16 TEST_EN
B
22UF_6.3V_5
VDD1P0_22
30
40 22 16 8
C410
VDD1P0_40
2
JTAG_TCK
C403
JTAG_TMS
332MA P1V05_LAN
0.1UF_16V_2
VDD1P0_43 VDD1P0_11
VDD1P1_46
JTAG_TDO
2
JTAG_TDI
0.1UF_16V_2 C401 2 1
VDD1P2_37
47 46 37
0.1UF_25V_2 C406 2 1
VDD3P3_29
15 19 29
1UF_6.3V_2 C405 2 1
1 VDD3P3_19
TP404 TP30
R404 2 1 1K_5%_2
C P3V3M
90MA
V3M_LAN_OUT_IN
4
0.1UF_25V_2
9 10
1
1 2
R400
25MHZ
2
22PF_50V_2
0_5%_2_DY
3 2
X400
1 4 1 400 C
4.7K_5%_2 1 P3V3M_R_1_RSVD 2 2 P3V3M_R_2_RSVD 2 5 4.7K_5%_2
C402
LED2
JTAG
1
32 34 33 35
2
18PF_50V_2
52
6
P1V05_LAN
R408 10K_5%_2_DY 1 2 1 2 10K_5%_2_DY R409
1 404 C
TRD3_MB_DP TRD3_MB_DN
2
VDD3P3_15
LED1
VDD1P0_47
P3V3M
B
LED0
LED
OUT OUT
26 27 25
1
LED_3S_LANLINK#_R LED_3S_LANACT#
BI BI
52 52 52
LED_3S_LANLINK#
1
51 52 55 52
OUT
470_5%_2 LED_3S_LANLINK#_R 1R402 2 LED_3S_LANACT# 1 2 470_5%_2 R403 TP400 TP401 TP402 TP403 TP30 TP30 TP30 TP30
1
51
VDD3P3_OUT
LED_3S_LANLINK#
TRD2_MB_DP TRD2_MB_DN
LAN_DISABLE_N
52 51
BI BI
23 24
0.1UF_16V_2 C416 2 1
3
20 21
0.1UF_16V_2 C415 2 1
LAN_DIS#
LAN_DIS# IN
52 52
0.1UF_16V_2
52 51 38
TRD1_MB_DP TRD1_MB_DN
0.1UF_16V_2 C414 2 1
10K_5%_2_DY 2
SMB_CLK SMB_DATA
MDI_PLUS2
BI BI
0.1UF_16V_2 C413 2 1
PCIE_RX6_DP PCIE_RX6_DN
C407
52
17 18
1
PCIE_TX6_C_DP PCIE_TX6_C_DN
C408
PCIE
2 2
0.1UF_16V_2
MDI_MINUS1
52 TRD0_MB_DP TRD0_MB_DN
1
34 51
0.1UF_16V_2 1 1
MDI_PLUS1
PE_CLKN
BI BI
C412
OUT OUT
IN IN
13 14
2
51
MDI_PLUS0 MDI_MINUS0
PE_CLKP
PCIE_RX6_C_DP PCIE_RX6_C_DN
34
CLK_REQ_N PE_RST_N
44 45
CLK_PCIE_LAN_DP CLK_PCIE_LAN_DN
34 34
C
48 36
MDI
34 34
34
U400
CLKREQ_LAN# PLT_RST#
SMBUS
34
51
0.1UF_16V_2 C411 2 1
44 72 33
1
34
OUT CLKREQ_LAN# 51 PLT_RST# IN
38 37
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION LAN
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
51
80
of
1
X01
8
7
6
5
4
3
2
1
REFERENCE NUMER : 470~499 3Q487
2
IN
LED_3S_LANLINK#
51
D
G
OUT
D
LANLINK_STATUS
37
S
55
D
SSM3K7002FU 51
38
LAN_DIS#
LAN_DIS#
IN
1
52
2
TO PLACE ONE 0.1UF AT EACH PIN 1 , 4 , 7 , 10 AND PLACE THE 1UF IN THE SPOT THAT
1
2 Q485
C
LES_LBSS84LT1G_SOT23_3P S
1 R485
LAYOUT NOTE:
C
100K_5%_2
P3V3M
G
G
2 TD4-
MX4-
TD4+
MX4+
1
R473 2
2
C473
1
LANK_LG_2405S_1A_SMD_24P
RDRD+
CC+
BI BI
CC+
DD+
BI BI
DD+ 52
1
A
1000PF_2000V_6
52 55 52 55
52 52 52 52 52 52 52 52
TD+ TDRD+ C+ CRDD+ D-
BI BI BI BI BI BI BI BI
B1 1 2 3 4 5 6 7 8 A1
55 52 55 52
B1
Green
Green B2
B2
G
G1
LED_3S_LANLINK#_R
IN
TX+
LED_3S_LANLINK#_R 51
C486
TXRX+ C+
52
680PF_50V_2_DY
CG
RX-
G2
D+ DA1
Yellow
A2 Yellow
A2
LED_3S_LANACT#
IN
51 52 55
LED_3S_LANACT#
C485
SANTA_130456_231_12P
680PF_50V_2_DY 52 55 52
55
B
2
MCT4
1
TCT4
2
MX3+
BI BI
0.01UF_100V_3
MX3-
TD3+
RDRD+
75_1%_2
MCT3
TD3-
1
BI BI
51
MX2+
TCT3
2
TRD3_MB_DN TRD3_MB_DP
51
TD2+
TDTD+
0.01UF_100V_3 C470
BI BI
R471 2
TRD2_MB_DN TRD2_MB_DP
MX2-
BI BI
75_1%_2 R470 2 1
51 51
MCT2
TD2-
1
1UF_6.3V_2
0.1UF_16V_2 C479 2 1
0.1UF_16V_2 C478 2 1
0.1UF_16V_2 C477 2 1
1 C475 2
0.1UF_16V_2 C476 2 1
B
MX1+
TCT2
1
BI BI
TD1+
2
TRD1_MB_DN TRD1_MB_DP
MX1-
TDTD+
0.01UF_100V_3 C471
51 51
51
TD1-
24 22 23 21 19 20 18 16 17 15 13 14
75_1%_2
BI BI
MCT1
0.01UF_100V_3 C472
TRD0_MB_DN TRD0_MB_DP
TCT1
75_1%_2 R472 2 1
51
U470
JACK485
TP485 TP30 55 55 55 55 55 55 55 55
SSM3K7002FU
1 3 2 4 6 5 7 9 8 10 12 11
1
1
1
IN
S
ISO_PREP#
2
D
33
3
Q486 55
1
3
D
IS AS CLOSE AS POSSIBLE TO ALL 4 PINS
52 55 55
RJ45+RJ11 CNTR
2
A
C474
INVENTEC TITLE
MODEL,PROJECT,FUNCTION LAN RJ45
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CONN
DOC.NUMBER
REV
CODE 1310xxxxx-0-0
X01
CS
SHEET
52
80
of
1
8
7
6
5
4
3
2
1
D
D
P3V3A_Q_WLAN P3V3ALW
1 TP1300
P3V3A
CN1300
RESERVED
REFCLK+
RESERVED RESERVED
RESERVED
GND
RESERVED
RESERVED
GND
PERST#
PERN0
+3.3VAUX
PERP0
GND
GND GND PETN0 PETP0
1.5V SMB_CLK SMB_DATA GND
GND
USB_D-
RESERVED
USB_D+
RESERVED
GND
RESERVED
LED_WWAN#
RESERVED
LED_WLAN#
RESERVED
LED_WPAN#
RESERVED
1.5V
RESERVED
GND
RESERVED
3.3V
G1
G2
2 1
REFCLKRESERVED
C
R1300
10K_5%_2_DY
2
RESERVED
D1300 1
IN
OUT
USB_P5_DN USB_P5_DP
3
BUF_PLT_RST#
23 37 48 50 54 60
BI BI
NC
RESERVED
GND
37 37
WL_LED_ALL#
10UF_6.3V_3
CLKREQ#
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 G2
1
1.5V
C1304
3.3V GND
RESERVED
2
WAKE# RESERVED
0.1UF_16V_2 C1303 2 1
1 2
CLKREQ_WLAN#_R
2 0_5%_2_DY R1303 1 2 1 35 48 PCIE_WAKE# OUT 0_5%_2_DY 3 54 5 1 TP1301 7 CLKREQ_WLAN#_R 9 11 IN 34 CLK_PCIE_WLAN_DN 13 IN 34 CLK_PCIE_WLAN_DP 15 17 19 1 TP1302 21 23 34 OUT PCIE_RX4_C_DN 25 34 OUT PCIE_RX4_C_DP 27 29 31 34 IN PCIE_TX4_C_DN 33 34 IN PCIE_TX4_C_DP 35 37 39 41 43 45 34 P3V3A IN CL_CLK1 47 34 IN CL_DATA1 49 34 R1306 IN CL_RST#1 51 1 2 BT_OFF# G1 10K_5%_2_DY Q1302
WLAN_TRANSMIT_OFF#38
IN
BAT54_30V_0.2A
61 56
B
FOX_AS0B226_S40QW_7H_52P
D
3
B
0.1UF_16V_2
0.01UF_50V_2 C1301 2 1
4.7UF_6.3V_3 C1305 2 1
1 C1307
2
1 R1310
220K_5%_2
2
R1304
G
Q1301 SSM3K7002FU
3 OUT CLKREQ_WLAN#
34
0_5%_2
1
G
PMV65XP
1
1 C1308 2
0.1UF_16V_2_DY
1 R1302
0_5%_2
2
576MA
D
WLAN_OFF IN
C
TP30
S
48
2
S
R1301 1
Q1300
3
D
2
IN
BT_OFF
1
G
S
35
2
SSM3K7002FU
A
A
WLAN
REFERENCE NUMBER:1300~1349
INVENTEC TITLE
MODEL,PROJECT,FUNCTION WLAN
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
53
80
of
1
X01
8
7
6
5
4
3
2
1
1
PVSIM
D1451
BAV99
2
3
TP1451 TP30 TP1452 TP30 P5 P6 P7 P8 CD
1
BI
2
RST
DATA
CLK
Reserved
P1 P2 P3 P4
Reserved
UIM_PWR 54 UIM_RST 54 UIM_CLK 54
BI BI BI
D
CD
G2
G
G1
G
1
47K_5%_2_DY
VCC
VPP
TAI_PMPAT3_08GLBS7N14N0_9P
2
SIM CARD
18PF_50V_2_DY
R1451
GND
18PF_50V_2_DY C1405 2 1
1
BI BI
C1451
UIM_VPP UIM_DATA 54 UIM_PWR 54
54
0.1UF_16V_2 C1452 2 1 4.7UF_6.3V_3 C1453 2 1
D
1
CN1451
CAP CLOSE TO SIM CARD
TP1400 TP30
PVSIM
P3V3ALW
R1403 48
WWAN_OFF IN
1
C
68PF_50V_2
68PF_50V_2 C1417 2 1
4.7UF_6.3V_3 C1416 2 1
1
0.1UF_16V_2 C1415 2 1
C1414 2
2
TPC6111
0.01UF_50V_2
PMOS_4D1S
68PF_50V_2 C1413 2 1
1 1 2 5 6
68PF_50V_2 C1412 2 1
G
D
1
S
3
68PF_50V_2 C1411 2 1
4
2.75A C1410
1 C1402
2
2
R1404
0_5%_2
1
C
0.1UF_16V_2_DY
Q1400
2
P3V3S
220K_5%_2
B
38
GPS_XMIT_OFF# IN
WAKE#
3.3V
RESERVED
GND
RESERVED
1.5V
CLKREQ#
RESERVED
GND
RESERVED
REFCLK-
RESERVED
REFCLK+
RESERVED
RESERVED
RESERVED
RESERVED
GND
RESERVED
RESERVED
GND PERN0 PERP0
PERST# +3.3VAUX GND
GND
1.5V
GND
SMB_CLK
PETN0 PETP0
SMB_DATA GND
GND
USB_D-
RESERVED
USB_D+
RESERVED
GND
RESERVED
LED_WWAN#
RESERVED
LED_WLAN#
RESERVED
LED_WPAN#
RESERVED
1.5V
RESERVED
GND
RESERVED
3.3V
G1
G2
1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 G2
BI BI BI BI BI
R1402
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 G1
UIM_PWR 54 UIM_DATA 54 UIM_CLK 54 UIM_RST 54 UIM_VPP 54
D1410 1
IN
BUF_PLT_RST#
2 0_5%_2_DY
L1400
IN
3 2
WCM_2012_900T
OUT
3
IN
23 37 48 50 53 60
WWAN_DET# 1 R1405
USB_P12_L_DN 4 USB_P12_L_DP 1
0_5%_2
PCIE_WAKE# 1
PCIE_WAKE# OUT LTE_GPIO0 OUT LTE_GPIO1 OUT
2
35
2
48
NC
53 54
CN1400
R1406 2 0_5%_2_DY
LED_WWAN_LINK#
INTRUDER#
BI BI
WWAN_TRANSMIT_OFF# 38
56
B
BAT54_30V_0.2A 33
37 37
USB_P12_DN USB_P12_DP
56
FOX_AS0B226_S40QW_7H_52P
A
A
WWAN INVENTEC TITLE
MODEL,PROJECT,FUNCTION WWAN & SIM
REFERENCE NUMBER:1400~1499
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
CARD
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
54
80
of
1
X01
8
7
6
5
4
3
2
1
D
D
DETECT1#1 52 52 52 52
52
57 57
57 57
IN IN
PR_AOUT_L_DOCK PR_AOUT_R_DOCK
IN IN
34 34 36 36 36 38 36 36 9
I2C_CLK I2C_DATA DPB_HPD DPB_DDC2DATA DPB_DDC2CLK DOCK_ID1 DDCAUX_B0_DN DDCAUX_B0_DP SLP_S3#_3R SLP_S4#_KBC
1 C3601 2
1
0.1UF_25V_3
2
IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN
0.1UF_25V_3
ON_OFF# 37 USB_P0_DP 37 USB_P0_DN LIMIT_SIGNAL
PVADPTR
C3600
1
0.1UF_16V_2_DY
C3602
LED_PWRSTBY# IN 36 DPC_HPD IN
DDCAUX_C0_DN DDCAUX_C0_DP
36
2
IN IN
A_LINEINL_DOCK A_LINEINR_DOCK
36
B
IN IN
IN IN
48
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 P1 G3 G4
IN IN
LINE_IN_SENSE LINE_OUT_SENSE
57 57
2 R3600 1
TD+ TD-
LANLINK_STATUS LED_3S_LANACT#
C
1K_5%_2_DY
RD+ RD-
CN3601 DETECT1#
PREP#
RJ45_B+
RJ45_D+
RJ45_B-
RJ45_D-
GND
GND
RJ45_A+
RJ45_C+
RJ45_A-
RJ45_C-
GND
GND Reserved
Reserved
Reserved
Reserved GND
GND
RJ45_LINKLED#
Reserved PCIe TX1+
RJ45_ACTLED#
Reserved PCIe TX1-
Reserved
GND
LINE_IN_SENSE
Reserved PCIe RX1+
LINE_OUT_SENSE
Reserved PCIe RX1-
AUDIOAGND LINE_IN_L LINE_IN_R
GND Reserved DPB_ML1+ Reserved DPB_ML0-
AUDIOAGND
GND
LINE_OUT_L
Reserved DPB_ML1+
LINE_OUT_R
Reserved DPB_ML1-
AUDIOAGND
GND
PWRLED
Reserved DPB_ML2+
Reserved DPB_HPD
Reserved DPB_ML2-
GND
GND
Reserved DPB_CTRLDATA Reserved DPB_ML3+ Reserved DPB_CTRLCLK Reserved DPB_ML3GND
GND
Reserved DPB_AUX-
DP_ML0+
Reserved DPB_AUX+
DP_ML0-
GND
GND
Reserved PCIe CLK1+
DP_ML1+
Reserved PCIe CLK1-
DP_ML1-
DPA_HPD DPA_CTRLDATA DPA_CTRLCLK
GND DP_ML2+ DP_ML2-
DOCK_ID1
GND
DPA_AUX-
DP_ML3+
DPA_AUX+
DP_ML3-
SLP_S3#
GND
RESERVED_SLP_S4#
USB3_RX+
VA_ON#
USB3_RX-
NBSWON# RESERVED (I2C_CLK/USB1+) RESERVED (I2C_Data/USB1-) DOCK_ADP_SIGNAL
GND USB3_TX+ USB3_TXDETECT2#
VA(120W)
GND
GND
GND
GND
GND
47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 G1 G2 G5
IN IN IN
ISO_PREP# D+ 52 D- 52
IN IN
C+ C-
33
52 52
C
DETECT1#
IN IN
DPC0_DP 36 DPC0_DN 36
IN IN
DPC1_DP 36 DPC1_DN 36
IN IN
DPB0_DP DPB0_DN
36 36
IN IN
DPB1_DP DPB1_DN
36 36
IN IN
DPB2_DP DPB2_DN
36 36
IN IN
DPB3_DP DPB3_DN
36 36
IN IN
USB30_RX1_DP USB30_RX1_DN
37 37
IN IN
USB30_TX1_DP USB30_TX1_DN
37 37
B
FOX_QL1046L_D262AR_7H_92P
AGND_AUDIO
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION DOCKING CNTR
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
55
80
of
1
X01
8
7
6
5
4
3
2
1
P3V3S
D
P5V0S
D
2
2 R118
CN200 R113
P3V3S G
4.7K_5%_2
1
1
P3V3AL
IN
WL_LED_ALL#
3 D
1
61 56
53 61
Q112
G
S
WWAN_TRANSMIT_OFF# IN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
4.7K_5%_2
48 33 48 33 33 56 61 53
2
SSM3K7002FU
55 48
IN
37 37 37 48 48
LED_WWAN_LINK#54
C
WLAN_WWAN_BLUETOOTH_ LED
34 47
29 32
32 34 47 29
LED_PWRSTBY# OUT OUT BAT_GRNLED# BAT_AMBERLED# OUT LED_3S_SATA# OUT IN HDD_HALTLED OUT WL_LED_ALL#
OUT BI BI BI BI
SC_PWRSV# USB_P7_DN USB_P7_DP IM_5S_DATA IM_5S_CLK
PCH_3S_SMDATA BI PCH_3S_SMCLK BI 56 ST_LEFT 56 ST_RIGHT
BI BI
G1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
C
18 19 20 21 22 23 24 25 26 G
G2
ACES_51536_02641_001_26P
P5V0S
B
48 48 56 56
SP_DATA SP_CLK ST_LEFT
ST_RIGHT
8 7 6 5 4 3 2 1
BI BI BI BI
SMART CARD
CN202 8 7
G
6
G
B
G2 G1
5 4 3 2 1
HIROSE_FH34SRJ_8S_0_5SH_88_8P
POINT STICK
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION STICK
REFERENCE NUMBER:100~199 CHANGE by
8
7
6
5
4
XXX
3
DATE
SIZE A3
21-OCT-2002
2
CODE CS
POINT
& B2B CNTR
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
56
80
of
1
X01
8
7
6
5
4
3
2
1
SPKR_EN_AB
55
OUT
PR_AOUT_R_DOCK
55
A_LINEINR
1
30_1%_3
X5R 57
57
OUT
A_LINEINL
OUT
C526 2
R504 1 2 6.2K_1%_2
2.2UF_6.3V_3 C514 1 2
R505 1 2 6.2K_1%_2
2.2UF_6.3V_3
R506 2
1
C527 2
PR_AOUT_L_DOCK
X5R
AGND_AUDIO
1
2
2
1SS355VMTE_17
OUT
R507 2
R517 1 0_5%_2
1
X5R
2
1
A_SD# IN
1
OUT
R523 2
20K_1%_2
48
59
SENSE_A
30_1%_3
1 PR_AOUT_C_R_DOCK
0.1UF_16V_2
D500
AGND_AUDIO AGND_AUDIO 57
2
IN
A_LINEINR_DOCK 55
IN
A_LINEINL_DOCK 55
D
2K_5%_2
C512
IN
PR_AOUT_R_AB
1
1
57
D S
SSM3K7002FU
2
2 1
D
R5222
1 PR_AOUT_C_L_DOCK
150UF_6.3V
G
100K_5%_2
R529
55
2
2K_5%_2
P3V3S
Q528 1
IN
LINE_IN_SENSE
1
150UF_6.3V
R502 2 1 20K_1%_2 2 R503 1
1 R528 23
C511
IN
PR_AOUT_L_AB
57
+
IN
+
SENSE_B
20K_1%_2
X5R 57
2
1
82 33_5%_2 11
HDA_SDI
VREFOUT_C/GPIO4
HDA_RST#
PORTE_L PORTE_R
SPKR_EN_AB 47 43
22 4 100_5%_2
1
OUT OUT
SPK_OUT_L_DP SPK_OUT_L_DN
57 57
SPK_PORTD_-R
44 43
OUT OUT
SPK_OUT_R_DP SPK_OUT_R_DN
57 57
MONO_OUT
25
PCBEEP
12
SPK_PORTD_-L SPK_PORTD_+R
SPDIFOUT0/GPIO3
36
CAP+
A_LINEINL A_LINEINR
1
C518
GND
3
EN
5
NR
4
TI_HPA01085DVBR_SOT23_5P
9
2
18
C500
42 35 27 21 20 19 45 48 55
PCBEEP_IC_C
AVSS1 AVSS3
26 30 33
2
TP30
TP642
1
1
TP30
TP641 1
1
C520
1
G
2
G
TP30
TP644
TP30
TP643
1
3 4
2200PF_50V_2 C643 2 1
2200PF_50V_2 C642 2 1
2200PF_50V_2
B
2
PCBEEP_CRC
0.1UF_16V_2
1
100K_5%_2
Q500 D
0_5%_2
1
IN
A_3S_ICHSPKR 33
S
G
SSM3K7002FU
2
2 R510
C519
1
IDT_92HD91B2X5NLGXWCX_QFN_48P
2
PAD
0.01UF_50V_2
PVSS
49
1
1
42
AVSS2
10UF_6.3V_3
2
OUT
1
IN
IN
0.015UF_10V_2 C501 2 1
SLP_S3#_3R
U500
1
1
P5V0S_AUDIO_AVDD
1 2
P5V0S_AUDIO_AVDD
R509 2
10UF_6.3V_3
TP500 TP30
P5V0S
A
DVSS
C515
X5R
7
2
VREG(+2.5V)
4.7UF_6.3V_3
21 22 34 37
1UF_6.3V_2 C517 2 1
V-
4.7UF_6.3V_3 C529
CAP2 CAP-
4.7UF_6.3V_3 C516 2 1
VREFFILT
C521
35 2
1
57 57
0.1UF_16V_2
REC_MUTE_LED_CNTR OUT PLAY_MUTE_LED_CNTR OUT 1
1 2
AGND_AUDIO
DMIC1/GPIO0/SPDIFOUT1
2
61
C640
1 2 R511
58
PCBEEP_IC_CR
49
2.49K_1%_2
1
1
40 41
SPK_PORTD_+L DMIC0/GPIO2
48 46
IN A_MIC EXT_MIC_JACK 59 58 MIC_BIAS 59
15 16
EAPD DMIC_CLK/GPIO1
X7R
1UF_6.3V_3
IN IN
PORTF_R
R516
DMIC_CLK OUT DMIC_DAT IN
IN OUT
59 59
HP_OUT_L1 HP_OUT_R1 2
17 18
PORTF_L
43
OUT OUT C530 1
19 20 24
C CN641
R537 2 1 3.3_5%_2
OUT
PORTC_L
HDA_SYNC
PORTC_R
R514
31 32
R536 2 1 3.3_5%_2
AZ_R3S_SDIN0
IN
10
HP1_PORTB_R
HDA_SDO
R535 2 1 3.3_5%_2
33
AZ_R3S_SYNC
5
3 4
ACES_50224_0020N_001_2P
2200PF_50V_2 C641 2 1
33
IN
HP1_PORTB_L
SPK_OUT_L_DN IN SPK_OUT_L_DP IN
57 57
R534 2 1 3.3_5%_2
C522
B
AZ_R3S_SDOUT
HDA_BITCLK
PR_AOUT_L_AB 57 PR_AOUT_R_AB 57
G
1
IN
33
2 0_5%_2_DY 10PF_50V_2_DY
AZ_R3S_RST#
1 2 R513 1 4.7K_5%_2
33
6
IN
0.01UF_50V_2 C523 21 R515 1
AZ_R3S_BITCLK
OUT OUT
G
ACES_50224_0020N_001_2P
R508
VREFOUT_A
33
28 29 23
1 2
0_5%_2
HP0_PORTA_R
IN IN
SENSE_A SENSE_B
SENSE_A 57 SENSE_B 57
57 57
CN640 1 2
2
HP0_PORTA_L
P3V3S
59 57 57
OUT OUT
SPK_OUT_R_DP IN SPK_OUT_R_DN IN
3
SENSE_B
AGND_AUDIO
13 14
1
SENSE_A
DVDD
1000PF_50V_2
9
45 39
C525
PVDD2
2
PVDD1
DVDD_IO
2 R512
3
2.49K_1%_2
AVDD2
0.1UF_16V_2
AGND_AUDIO
27 38
1
AVDD1
DVDD_CORE
1000PF_50V_2
2
2
U501
1
2
2
0.1UF_16V_2
2
1UF_6.3V_2
2
100K_5%_2
C
INT-SPEAKER CONN.
P5V0S_AUDIO_AVDD
C524
10UF_6.3V_3
0.1UF_16V_2 C510 10UF_6.3V_3 2 1
C505
C503 C504
1UF_6.3V_2 C509 2 1
1
C502
C508
1
C506
1
2
R530
1
1
SSM3K7002FU 2
1
G
2
1
IN
AGND_AUDIO
750MA 0.1UF_16V_2
D
LINE_OUT_SENSE
P5V0S
85MA
S
55
P5V0S_AUDIO_AVDD
P3V3S P3V3S
Q530
1UF_6.3V_2 C507 2 1
23
R531
39.2K_1%_2
A
AGND_AUDIO AGND_AUDIO
PAD500 1
1
2
2
POWERPAD_2_0610
AGND_AUDIO
1
TP510
TP30
AGND_AUDIO
INVENTEC
AGND_AUDIO
TITLE
MODEL,PROJECT,FUNCTION AUDIO
REFERENCE NUMBER:500~549
SIZE A4
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
CODEC
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
57
80
of
1
X01
8
7
6
5
4
3
2
1
D
D
P5V0S_AUDIO_AVDD
IN 1
C
57
1
2
1
15PF_50V_2 R612 2 1
1
U610 1OUT
VDD+
8
2
1IN-
2OUT
7
3
1IN+
2IN-
6
4
GND
2IN+
5
X7R AGND_AUDIO
100K_5%_2
0_5%_2
IN
C617
VREF_EQ
58
R618 1 2 100K_5%_2
68PF_50V_2
R619 100K_5%_2 2 1
2
TI_TLV2462CDGKR_MSOP_8P
AGND_AUDIO
X7R
2.2UF_6.3V_2
X5R
1
0.47UF_10V_3
C
2
0.1UF_16V_2
0.1UF_16V_2 C613 2 1
IN
1
1
C614
EXT_MIC_JACK
R617
2
2
57
L627 BLM18PG600SN1D 1 2
A_MIC OUT
C612
1
59
C620 2
2
C616 100PF_50V_2
C615
VREF_EQ 58
X5R B
B
REFERENCE NUMBER:600~649
AGND_AUDIO
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION EXT.
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
MIC AMPLIFIER
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
58
80
of
1
X01
8
7
6
5
4
3
2
1
1
1000PF_50V_2_DY
C2502
D
2
C2503 0.1UF_16V_2 2 1
P5V0A_USB_CHARAGE
L2500
USB_P1_U_DN USB_P1_U_DP
45 45
USB30_RX2_DN USB30_RX2_DP
37 37
USB30_TX2_DN USB30_TX2_DP
37 37
3 2
BI BI
USB_P1_U_L_DN USB_P1_U_L_DP
4 1
D
1 2 3 4 5 6 7 8 9
WCM_2012_900T
OUT OUT
0.1UF_16V_2 2 C2500 1 2 C2501 1 0.1UF_16V_2
IN IN
USB30_TX2_C_DN USB30_TX2_C_DP
CN2500 VBUS DD+ PGND SSRXSSRX+ GND SSTXSSTX+
G G G G
G1 G2 G3 G4
SINGA_2UB1585_000121F_9P
C
C
REFERENCE NUMBER:2500~2510 USB CHARGER
P5V0S_AUDIO_AVDD 57
IN
1
5
G
SINGA_2SJ3112_000111F_7P
TP601
S
JACK_DET
2
2
SSM3K7002FU
R601
16_1%_2 2
1 1
L602 1 2 BLM18PG600SN1D
IN
HP_OUT_L1
57
1
2
EXT_MIC_JACK MIC_BIAS
58
57
57
2.2K_5%_2
HP_OUT_R1 57 JACK_DET 59
IN OUT
OUT IN
R602
1
1
16_1%_2 2
C600 1UF_6.3V_2
TP600
TP30
2
D
59
4
1 2 L600 FBM_11_160808_121T 1 2 L601 FBM_11_160808_121T
R600
220PF_50V_2
Q600
0.033UF_16V_2 C603 2 1
3
1
6
0.033UF_16V_2 C602 2 1
2
3
2
B
TP30
2
100K_5%_2
7 1
C601
G4
R604
20K_1%_2
TP30 TP606 1
1 R603
G1 G2 G3 G4 7 1 2 6 3 4 5
TP30 TP605 1
G3
1
TP30 TP604 1
G1 G2
B
TP30 TP603 1
JACK600
1
SENSE_A
TP30 TP602 1
OUT
AGND_AUDIO
AGND_AUDIO
AGND_AUDIO
AGND_AUDIO A
A
REFERENCE NUMBER:600~610
INVENTEC TITLE
MODEL,PROJECT,FUNCTION AUDI JACK
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
& USB3.0(LEFT)
DOC.NUMBER SHEET
59
80
of
1
DB
REV
1310xxxxx-0-0
X01
8
7
6
5
4
3
2
1
C801 1
2
1 60 SD_MMC_CMD
IN
2
SD_MMC_DATA060 SD_MMC_DATA160 SD_MMC_DATA260 SD_MMC_DATA360
IN IN IN IN
1
0.1UF_16V_2
C802 2
22PF_50V_2_DY
C815
P3V3S
108MA D
SD_MMC_CLK60
IN
2.2UF_6.3V_2
AS CLOSE AS POSSIBLE TO JMB700
D
P3V3S
P1V8S_CARD 1
TP800
1 C800 2 48 47 46 45 44 43 42 41 40 39 38 37
P1V8S_CARD
0.1UF_16V_2
0.1UF_16V_2 CLOSE TO PIN5 C818 2 1
1 C816 2
CLK_PCIE_CARD_DN CLK_PCIE_CARD_DP
IN IN 1 R804 12K_1%_2 2
34 34 34
OUT OUT
PCIE_RX3_C_DN PCIE_RX3_C_DP 34
1 1
PCIE_TX3_C_DP PCIE_TX3_C_DN C811
2 0.1UF_16V_2 2
IN IN PCIE_RX3_DN PCIE_RX3_DP
XRSTN XTEST
3
IN
D
CLKREQ_PCIE_CARD#
S
34
GND
U800
APGND
GND
APREXT
NC
APRXP
MDIO8
APRXN
MDIO9
APV18
MDIO10
APTXN APTXP
MDIO11 NC
13 14 15 16 17 18 19 20 21 22 23 24
1
NC
APVDD
R818
0_5%_2_DY 2
R820 1
NC
APCLKP
P3V3S CLOSE TO PIN10
NC
APCLKN
0.1UF_16V_2
C813
NC
MDIO6 NC NC CR1_LEDN DV33 DV33 DV18 CR1_PCTLN CR1_CD0N CR1_CD1N NC CPPE*
10UF_6.3V_3 C817 2 1
34 34
1 2 3 4 5 6 7 8 9 10 11 12
DV18 GND TXIN MDIO7 MDIO4 MDIO5 SDDV33_18 DV33 MDIO3 MDIO2 MDIO1 MDIO0
C
2
P3V3S_VCC_READER
36 35 34 33 32 31 30 29 28 27 26 25
60
60 60 60 60 60 60 60 38
IN IN IN IN IN IN IN IN
SD_MMC_CLK SD_MMC_CMD SD_MMC_DATA0 SD_MMC_DATA1 SD_MMC_DATA2 SD_MMC_DATA3 SD_MMC_WP D3E_WAKE#
JM_JMB709_LQFP_48P
10K_5%_2_DY
IN
2
SD_MMC_WP60
G
B
CN820 SD_VDD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3_CD SD_WP SD_CD_SW SD_COM SD_VSS1 SD_VSS2
GND1 GND2
G1 G2
PLAST_CS1R_201_H_N_12P
B
SSM3K7002FU
1 2
C809
R821 2
IN
PLACE R821,C819,C820 CLOSE TO U820
P3V3S 0.1UF_16V_2
P3V3S_VCC_READER 1
C
Q800
D3E_WAKE# IN 60 38
1
P3V3S
4 5 2 7 8 9 1 10 11 12 3 6
C820 0.1UF_10V_2_DY 2 1
IN
BUF_PLT_RST#
54 53 50 48 37 23
0.1UF_16V_2
TP30
SD_MMC_WP 60
1K_5%_2
P3V3S_VCC_READER
A
2
10UF_6.3V_3
1
P1V8S_CARD
C814
1 2
C819
10UF_6.3V_3
TP8191
TP30
A
PLACE C814 CLOSE TO U800-18
INVENTEC TITLE
MODEL,PROJECT,FUNCTION CARD READER
REFERENCE NUMBER:800~899
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
60
80
of
1
X01
8
7
6
5
4
3
2
1
MUTE BOTTON
1
IN
3
KSCAN_3S_IN(0)
1
49
3
P3V3S
OUT
SCAN_3S_OUT(17)
SW154
53 56
WL_LED_ALL#
1
IN
+
3
1
D110
D
2 R114 270_5%_2
D
EVL_23_22B_Y2ST3D_C30_2T_4P
S
61
3
48
2
SSM3K7002FU
SCAN_3S_OUT(17)
OUT
3
1
-
Yellow
4
2
GND
G1
1
SW152
R115 270_5%_2 1 2
G
WIRELESS BOTTON IN
4
3
4
4
2
1
KSCAN_3S_IN(1)
+
PureWhite
Q110
MISAKI_NTC011_BA1J_A160T_4P
49
-
61
2
2
G1
48
GND
D
4
2
MISAKI_NTC011_BA1J_A160T_4P
C
C
WIRELESS/BLUETOOTH LED 1 C9413 2
0.1UF_16V_2
P3V3AL
U9413 1
VDD
2
OUT
GND
48 43
LID_SW#_3
OUT
3
EVL_23_22B_Y2ST3D_C30_2T_4P
MAG_MH248BESO_SOT23_3P
Q125
B
PLAY_MUTE_LED_CNTR
57
2
OUT
5
S1
1
D1 D2
6 3
2
G1
G2
4
R126 270_5%_2
D126
1
Yellow -
+
3 1
2
-
+
4 1
2
2 1 D9006 56 55
POWER SWITCH
48
1
A LED_PWRSTBY#
OUT
19_217_W1D_AP1Q2QY_3T
2 R9031
4
2 1
3
3
1
MISAKI_NTC011_BA1J_A160T_4P
1 R130 0_5%_2
55
130_1%_2
4
2
OUT ON_OFF#
49
GND
G1
2
P3V3AL 21
B
R127 270_5%_2
PureWhite
S2
2N7002DW SW9021
P3V3S
MUTE LED A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION BUTTON LED
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
DOC.NUMBER
REV
CODE 1310xxxxx-0-0
X01
CS
SHEET
61
80
of
1
8
7
6
5
4
3
2
1
XTAL_12M_OUT
X9400
2
1
PVSM_VCC_SM
C9406
NC 62
1
LED_SM_PWRSTBY# IN
P3V3S_SM_AB
POWER LED
SCARDRST SCARDCLK
IN IN
62 62 62
USB_P7_SM_DN USB_P7_SM_DP
IN IN
1
PVSM_VCC_SM 1
C9405
1
XO
SCARD0C6
XI
SCARD0FCB
PWRSV_SEL
SMIO_5VPWR
LEDCRD
SCARD0RST
LEDPWR
SCARD0CLK
RESET
SCARD0DATA
EEPDATA
DM
EEPCLK
DP
P1-6
AV33
ICCINSERTN
SCPWR0
VDDH
5VGND
VDDP
5VINPUT
VDD
V33OUT
V18OUT
DGND_SM
1
+ -
R9003 2
1
Yellow
D
270_5%_2
YELLOW
EVL_12_22_Y2ST3D_C30_2C_3P
BATTERY LED C9411 1UF_6.3V_2
2
C9409 1UF_6.3V_2
2
C9403
P3V3S_SM D9032
C9407
2
1
1
1
C9401
-
3
-
0.1UF_16V_2 DGND_SM
C9400
YELLOW
R9000 1
+ Yellow
1 2 270_5%_2
EVL_12_22_Y2ST3D_C30_2C_3P
C
Q9000
DGND_SM
1
IN
WL_LED_SM_ALL#
G
WIRELESS LED
S
62
2
SSM3K7002FU
DGND_SM
Pure White
D
2
2
0.1UF_16V_2
2
1UF_6.3V_2
0.1UF_16V_2
2
1UF_6.3V_2
WHITE 2
C9402
3
DGND_SM
1
TP30
DGND_SM
1
1
P3V3S_SM_AB
TP94031
DGND_SM
C
Pure White
-
3
OUT
BAT_SM_AMBERLED#
100K_5%_2
P3V3AL_SM
D9002 2
0.1UF_16V_2
P5V0S_SM
1UF_6.3V_2
2
2
WHITE
BAT_SM_GRNLED# OUT
62 62
ALCOR_AU9542B56_GBS_GR_SSOP_28P
C9404
0.1UF_16V_2
SCARD0C8
2
62
1 R9412 2 28 0_5%_2_DY 27 R9402 26 IN SC_PWRSV#_SM 25 62 24 23 22 21 P3V3S_SM_AB 20 19 ICCINSERTN OUT 62 18 17 P1V8S_SM 16 15 C9410
U9400
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1
R9401 2 1 62 SCARDDATA IN 470_5%_2 P3V3S_SM_AB
SCARDFCB
IN IN IN
2
2
DGND_SM
62 SCARDC8 62 SCARDC6 62
R9002 2 1 270_5%_2
2
2
1
1
2
R9400 4.7K_5%_2
1
EVL_12_21_T3D_CP1Q2B12Y_2C_2P
DGND_SM DGND_SM
0.1UF_16V_2
D
P3V3AL_SM
D9001 NC
1 C9419 2
C9418
P5V0S_SM
24MA
2
12MHZ
18PF_50V_2
1
18PF_50V_2
1 XTAL_12M_IN
DGND_SM
1 TP9000
TP30
PVSM_VCC_SM CN9410
GND
HAMB_083AA24F08B_10P
62 62 62 62 62
DGND_SM
62
62 62
ST_RIGHT_SM ST_LEFT_SM
1 2 3 4 5 6 7 8
BI BI BI IM_5S_CLK_SM IM_5S_DATA_SM BI 62
62 62
PCH_3S_SMCLK_SM BI
PCH_3S_SMDATA_SM BI
IN IN IN BI BI
BAT_SM_AMBERLED#
LED_3S_SM_SATA# HDD_SM_HALTLED WL_LED_SM_ALL#
SC_PWRSV#_SM USB_P7_SM_DN USB_P7_SM_DP IM_5S_DATA_SM IM_5S_CLK_SM
CN9413 1
2
62 62
3 4 5 6
G
7
G
62 62
G1 G2
BI BI BI BI
PCH_3S_SMDATA_SM PCH_3S_SMCLK_SM ST_LEFT_SM ST_RIGHT_SM
21 20 19 17 15
1000PF_50V_2
1 C9416
2
HDD_STP#
-
3
-
G
IN
YELLOW
62
13 12 11
1
IN
HDD_SM_HALTLED
1
270_5%_2
2
B
IN
LED_3S_SM_SATA#
62
10 9 8 7 6 5 4 3
G
SSM3K7002FU
SATA LED & HDD-HALTED LED
2 1 G
8
G1
DGND_SM
REFERENCE NUMBER:9000~9099
ACES_51536_02641_001_26P
A
DGND_SM DGND_SM
TOUCHPAD
DGND_SM
REFERENCE NUMBER:9400~9499
FIX9400
FIX9401
FIX9402
FIX9403
FIX9404
TITLE
FIX_MASK
FIX_MASK
1
FIX_MASK
1
FIX_MASK
1
1
1
1
SMART CARD DB
FIX_MASK
FIX_MASK
DGND_SM CHANGE by
6
FIX9405
MODEL,PROJECT,FUNCTION
SMART CARD DOUGHTER BOARD 7
INVENTEC
1
S9400 SCREW420_700_0_1P
8
1
+ Yellow
EVL_12_22_Y2ST3D_C30_2C_3P
SSM3K7002FU
Q9002
14
DGND_SM
DGND_SM
Q9001
I425 R9005
Pure White
16
HIROSE_FH34SRJ_8S_0_5SH_88_8P
A
1
HDD_STP#
18
WHITE 2 3
1
22
D9030
D
LED_SM_PWRSTBY# BAT_SM_GRNLED#
23
S
SW-CD-GND
IN OUT OUT IN IN IN
24
2
62 62 62 62 62 62
SW-CD
P3V3S_SM
25
R9008
C8
P3V3S_SM
26
1K_5%_2
P3V3AL_SM
IO
DGND_SM
P3V3S_SM
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
P3V3S_SM
VPP
G2
2
10 5
C4
G
3
9
OUT
P5V0S_SM
CLK
D
ICCINSERTN
CN9412
RST
S
62
DGND_SM
VCC
2
62
OUT OUT OUT OUT SCARDDATA OUT 62 SCARDC8 OUT
R9007
1 C9415 2
0.1UF_16V_2
B
1 2 3 4 6 7 8
62 SCARDRST 62 SCARDCLK 62 SCARDFCB 62 SCARDC6
TP30
100K_5%_2_DY 2 1
TP94151
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE A3
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
62
80
of
1
X01
7
6
CN630
D
1
2 3 4 5 6 7 8
G1 G2
G
9
G
10
1 2 3 4 5 6 7 8 9 10
5
3
2
1
P3V3S_CAM
OUT DMIC_CLK_DB OUT DMIC_DATA_DB
D L630
1 2 BLM15AG121SS1D
1
TP630
TP30
C630
1UF_16V_3
2
ACES_50376_01001_001_10P
DGND_SYS1
4
1
8
DGND_SYS1
DGND_SYS1
C
C
1
P3V3S_CAM
1
P3V3S_CAM
C631
C632
X7R
MIC630
B
0.1UF_16V_2
P3V3S_CAM
2
2
0.1UF_16V_2
X7R
MIC631
1
GND
VDD
6
2
L_R
DATA
5
IN
3
GND
CLK
4
IN
B
1
GND
VDD
6
DMIC_DATA_DB
2
L_R
DATA
5
IN
DMIC_DATA_DB
DMIC_CLK_DB
3
GND
CLK
4
IN
DMIC_CLK_DB
DGND_SYS1
KNOWLES_SPM0423HD4H_WB_6P
DGND_SYS1
KNOWLES_SPM0423HD4H_WB_6P
LEFT
RIGHT DGND_SYS1
DGND_SYS1
A
A
1
MIC DOUGHTER BOARD
FIX631
FIX_MASK_0.8
INVENTEC
FIX632
FIX_MASK_0.8
1
FIX_MASK_0.8
1
FIX630
REFERENCE NUMBER:630~639
TITLE
MODEL,PROJECT,FUNCTION MIC
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DB
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
63
80
of
1
X01
8
7
6
5
4
3
S9
2
1
SCREW250_0_0_1P SCREW300_600_1P
1
S15
1
S1
SCREW250_500_1P
S5
S7
ST16
1
SCREW330_600_0_1P
STDPAD_3.15_5.5_TOP
SCREW330_600_0_1P
1
1
1
1.75MM
S25
SCREW250_550_500_1P
D
S4
1
ST17 STAPAD_1.15_6_1P
D
1.75MM
1
1
SCREW450_800_600_1P
ST18 STAPAD_1.15_6_1P
SCREW330_600_0_1P
S23
1
1
SCREW300_700_1P
SCREW330_600_0_1P
1
SCREW450_700_0_1P
1.75MM
1
S8
S6
1
S3
ST19 STDPAD_3.15_5.5_TOP
1
1.75MM
S20 S2
S10
SCREW450_800_600_1P
1
SCREW450_800_1P
1
1
SCREW450_800_600_1P
C
C
ST21 STDPAD_3.15_5.5_TOP 1.75MM
1
S27
1
SCREW250_550S_1P
ST22 STDPAD_3.15_5.5_TOP
FIX_MASK
FIX_MASK
FIX4
FIX5
FIX6
1
1
FIX3
S26 SCREW250_500_1P
1
FIX2
1
FIX1
1
1
1.75MM
FIX_MASK
B PVBAT 1
PVBAT
S28
1
1
FIX_MASK FIX_MASK
2200PF_50V_2
C7650
SCREW250_500_1P
S24 SCREW300_700_600_1P
1
2
68PF_50V_2
1
0.1UF_25V_2 C7649 2 1
C7648 2
2200PF_50V_2
1 C7647 2
68PF_50V_2
1 C7645 2
0.1UF_25V_2 C7646 2 1
1
2200PF_50V_2
C7644 2
68PF_50V_2
1
0.1UF_25V_2 C7643 2 1
C7642 2
2200PF_50V_2
1 C7641 2
C7639 2
68PF_50V_2
FIX_MASK
IN 1
VBATP
0.1UF_25V_2 C7640 2 1
9 8 65
1
B
CLOSE TO Q6100
CLOSE TO Q6150
CLOSE TO Q6200
CLOSE TO Q6300
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION SCREW
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
64
80
of
1
X01
8
7
6
3
2
2
P5V0S
C7664
P5V0A
1
1
1 68PF_50V_2
2
2
12PF_50V_2
1
C7553
C7552
68PF_50V_2
2
12PF_50V_2
1
PVBAT
1
1
1 C7551
C7550
4
PVADPTR
1
PVADPTR
5
C7666
C7665
C7667
C7663
0.1UF_25V_2
2
0.1UF_25V_2
0.1UF_25V_2
2
0.1UF_25V_2
2
2
2
1
0.1UF_16V_2
PVADPTR
P5V0A_CHG P3V3S
D
P1V05S_VCCP
2
P3V3S
C7668
P1V05S_VCCP
PVPACK
1
1
2
2
2
2
C C7673
1
1
1
P3V3ALW
P5V0A_CHG
1
2
2
2
68PF_50V_2
C7672
C7632
0.1UF_25V_2
C7510 68PF_50V_2
C7511
68PF_50V_2
2
2
68PF_50V_2
2
C7509
1
1
1
2
2
C7633
0.1UF_25V_2 0.1UF_25V_2
2
0.1UF_25V_2
PVADPTR
2
PVBAT
1
0.1UF_25V_2
2
0.1UF_25V_2
1
1
1
1 2
12PF_50V_2
C
2
C7636
0.1UF_25V_2
C7561
C7560
68PF_50V_2
C7508 68PF_50V_2
C7635
0.1UF_25V_2
0.1UF_25V_2
P5V0A_CHG
C7559
C7558
C7634
0.1UF_25V_2
2
2
0.1UF_16V_2
12PF_50V_2
C7670
C7669
C7677 1
P5V0A_CHG
1
1 68PF_50V_2
2
12PF_50V_2
2
68PF_50V_2
2
12PF_50V_2
1
0.1UF_16V_2
C7557
C7556
D
PVBAT
2
1
C7555
C7554
1
1
1
1
C7656 1
PVBAT VBATR_CPU
65 16
1
1
1
OUT C7637
0.1UF_25V_2
0.1UF_25V_2
2
2
2
0.1UF_25V_2
1
OUT
1
6 MFET_A
1
1
1
C7699
C7698
P1V5
C7514
C7515
B
C7516 68PF_50V_2
68PF_50V_2
2
EMI SOLUTION
C7513 68PF_50V_2
P1V5
P1V8S
P1V5S
C7518
C7519
C7678 1
2
C7694 2
0.1UF_16V_2
1
C7679
P1V5S
P1V5
1
2
1
0.1UF_16V_2
P1V05S_VCCP
P1V5
1
1
C7522
1
120OHM_25%_DY
C7626
5 17
2
PVADPTR_IN
0.1UF_16V_2 1
2
OUT
1
2
VBATR_CPU 65 16 0.1UF_25V_2
OUT A
2
0.1UF_16V_2
AGND_AUDIO
0.1UF_16V_2
2
C7697
C7692 C7521
1
P1V5S 1
PVBAT L7600
0.1UF_25V_2
C7696 2
2
C7628
2
0.1UF_16V_2
C7681 1
1
0.1UF_25V_2
2
0.1UF_16V_2
68PF_50V_2
C7629
OUT
C7695
0.1UF_16V_2
C7691 1
A
64 8 VBATP 9
2
0.1UF_16V_2
0.1UF_16V_2
68PF_50V_2
2
68PF_50V_2
2
2
68PF_50V_2
C7520
2
C7517 68PF_50V_2
1
1
1
1
C7690 1
2
P1V8S
1
2
2
68PF_50V_2
2
C7512
68PF_50V_2
2
B
68PF_50V_2
P1V5S C7693
2
2
P1V5 1
2
0.1UF_16V_2
INVENTEC
AGND_AUDIO
TITLE
MODEL,PROJECT,FUNCTION
RF SOLUTION
EMI & RF SOLUTION
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
65
80
of
1
X01
8
7
6
5
4
3
2
1
D
D
C
C
B
B
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION SYSTEM
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
SEQUENCE
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
66
80
of
1
X01
8
7
6
5
4
3
2
1
D
D
PVCORE_DGPU PAD6750 1
VRPVCORE_DGPU IN
1
2
2
MAX=50A
POWERPAD_2_0610
OCP=42A
PVBAT
V5
9
IN
2
0.1UF_25V_2
10UF_25V_5 C6763 2 1
1 C6761
10UF_25V_5 C6762 2 1
2
2
C6760
1
10UF_25V_5
PGND
2
VR_VDD5
1 Q6751
TI_CSD87588N_LGA_5P
1
VSW
5
2
2
TG
Sync FET
BG
3
2
PGND
4
VIN Control FET
1
R6763 2 1
SHORT_0603_25
1 C6766 2
R6771
B
C6775
A
1
1
1 5
Sync FET
CSC0402_DY
2.2UF_6.3V_3
GND
7
8
42.2K_1%_2
6 1 2
BG
1
PGND
TRIP
COMP
5
R6756
1
0.1UF_16V_2
C6768 2
1 C6769
1 R6751
C6767
0.01UF_50V_2
4
L6750 PCMC104T_R36MN 1 2 3 4
OUT
A
R6764 2
1
RSC_0402_DY
VSNS
2
IN
VRPVCORE_DGPU R6759
0_5%_2
10_1%_2
1
2
IN
GPU_VCC_SENSE
1
2
IN
GPU_VSS_SENSE
1
GSNS
INVENTEC
R6760 SHORT_0402_15 C6774 1000PF_50V_2
TITLE
MODEL,PROJECT,FUNCTION
2
Block
SIZE A3
CHANGE by
8
7
6
VRPVCORE_DGPU
1 + 3 470UF_2V
VRPVCORE_DGPU_LG
VSNS
1
TG
2 C6750
10
2
VSW
VRPVBAT_DGPU
R7675 RSC_0603_DY
DL
4
2
C7700 CSC0402_DY
VRPVCORE_DGPU_HG
GSNS
3
VIN Control FET
3
R6762 2
VRPVCORE_DGPU_PH
11
REFIN
1
12
DH
VREF
2
1 SHORT_0603_25
BST
EN
MODE
PGOOD
SW
1
TI_TPS51219RTER_QFN_16P
2
C6765 0.1UF_16V_2 1 2
13
14
15
16
17 PWPD
1
0_5%_2_DY
R6765 2.2_5%_3 1 2
DGPU_PG OUT
U6750
2
SHORT_0402_5
71
100PF_50V_2
1
C6773
IN
2
DGPU_VID5
R6750
IN
2
DGPU_VID4
0_5%_2_DY
IN
1
DGPU_VID3
B
0.033UF_16V_2
IN
C6770
DGPU_VID2
2 0_5%_2
2
IN
1UF_6.3V_3
DGPU_VID1
P3V3S R6766 2 1 SHORT_0402_5 U6751 ANPEC_APL6502A8I_TRG_8P R6767 2 1 5 3 VID0 VDA SHORT_0402_5 2 VID1 R6768 2 1 1 4 VID2 VDD 8 VID3 SHORT_0402_5 7 6 VID4 GND R6769 2 1 SHORT_0402_5 R6770 2 1
PAD6760
Q6750
TI_CSD87588N_LGA_5P
R6752 1
POWERPAD_2_0610
R6755=100K , FSW=300KHZ R6755=200K , FSW=400KHZ R6755=1K , FSW=500KHZ
2
51219VREF
2
1K_5%_2
R6755
OUT
+
2
IN
EN_DGPU
1
71
C6799
1
C 15UF_25V_DY
C
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
67
80
of
1
X01
8
7
6
5
4
3
2
1
D
D
1 1 2
PAD6940
2
22UF_6.3V_5
1 C6940 2
2 R6943 1
OCP=8AMP HIGH : 0.908V = 0.5 [ 1 + ( ( R6941//R6943) / R6942 ) ] LOW : 0.954V=0.5 ( 1+ R6941/R6942 )
G
D
1
G
R6944 1
1000pF_50V_2
C6944 2
100_1%_2
806_1%_2
2 R6941 1
B
90.9_1%_2
2
C6943
1
1
CSC0402_DY
1 2
IN
EN_VDDCI
R6942
VDDCI_PG
47_5%_2 C6941 0.033UF_16V_2
2
OUT
S Q6941 SSM3K17FU
22UF_6.3V_5 C6947 2 1
C6945 4.7UF_6.3V_3 2 1 R6940 12
1 2
C6942
0.1UF_16V_2
6 5 4
S
EN
D
ADJ
S
DRV
GND
D
VCC PGD
Q6940
U6940
PVDDCI
1 2 3 4
1 2 3
C G
GMT_G9330TB1U_SOT23_6P
NMOS_4D3S
FDMC7672
P5V0A
8 7 6 5
C
POWERPAD_2_0610
P1V0S_VCCP
2
VDDCI_SW
IN
73
1K_5%_2
B
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION Block
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
68
80
of
1
X01
8
7
6
5
4
3
2
1
D
D
BACO
P1V8S_DGPU
P15V0A
MOUNT
OPEN
R135
OPEN
MOUNT
1 2
2
2
2
2
2.2UF_6.3V_2
1 C604
1 C652
1 C599
1 C597
1 C593
C
2.2UF_6.3V_2
2.2UF_6.3V_2
2.2UF_6.3V_2
0.01UF_50V_2
2.2UF_6.3V_2
2.2UF_6.3V_2
1
1 2
G
C120
SI 1011
S
1
NMOS_4D3S
2
3
SSM3K7002FU
DGPU_PWR_EN
G
8 7 6 5
G
Q59
IN
D
Q58
100K_5%_2
71
2
0_5%_2
S
0.1uF_25V_2_DY R518 2 (1.3A) 1
R135
1
S
TPCA8057_H
1
D
1
68PF_50V_2
C651 2
1
(7A)
0_5%_2
C589
2
2
C119
G NMOS_4D1S
AO6402AL
R500
1 2 3 4
0.1uF_25V_2
1
3
Q21
1
SI 1130
C591
4
S
2
C
D
P1V5
3
P3V3A
Q56
R494 560K_1%_2
D
1 2 5 6
P1V5
2
P1V5S_DGPU
SI 1129
2
P1V8S
W/O BACO
R132
2
SSM3K7002FU
B
B
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION Block
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
69
80
of
1
X01
8
7
6
5
4
3
2
1
OCP=6AMP 0.943V=0.5(1+R6951/R6952) PVPCIE
EN_VPCIE
1 2
PAD6950
2
22UF_6.3V_5
C6953 2
1 R6951 2
90.9_1%_2
1
1
R6952
1
C
100_1%_2
IN
2
71
47_5%_2 C6951 0.033UF_16V_2
6 5 4
2
EN
R6950 12
1 2
C6952
0.1UF_16V_2
ADJ
S
DRV
GND
Q6950
VCC PGD
D
U6950
1 2 3 4
C
1 2 3
G
GMT_G9330TB1U_SOT23_6P
NMOS_4D3S
FDMC7696
P5V0A
8 7 6 5
C6955 4.7UF_6.3V_3 2 1
1
P1V0S_VCCP
D
POWERPAD1X1M
D
B
B
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION Block
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
70
80
of
1
X01
7
6
5
4
3
2
1
2
8
NC
D6000 3
D
DIODE-BAT54-TAP-PHP 1
DB 0711
D R6003
1
R6002 2
EN_DGPU OUT
2
8.2K_5%_2
2
C6002
0_5%_2
1
1
DGPU_PWR_EN
IN
67
0.1uF_16V_2
69
DB 0817 C
C
SI 1026 R6004 2
EN_VPCIE
C6003
1
10K_5%_2
C6008 2
2
0.1uF_16V_2
1
R6005 2
EN_P1V5S_DGPU OUT C6004
DB 0807 2
DGPU_PG
1
10K_5%_2
R6011
DGPU_PWROK 1
OUT
1
IN
2
2
B
10K_5%_2
R6010
1
P3V3S
70
OUT
0.1uF_16V_2
1
67
0.1uF_16V_2
DB 0726
B
0_5%_2
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION Block
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
71
80
of
1
X01
8
7
6
5
4
3
2
1
U34 PART 1 0F 9
CLOSE TO GPU
D
24 24
BI BI
PEG_TX0_C_DP PEG_TX0_C_DN
AA38 Y37
PCIE_RX0P
PCIE_TX0P
PCIE_RX0N
PCIE_TX0N
24 24
BI BI
PEG_TX1_C_DP PEG_TX1_C_DN
Y35 W36
PCIE_RX1P
PCIE_TX1P
PCIE_RX1N
PCIE_TX1N
24 24
BI BI
PEG_TX2_C_DP PEG_TX2_C_DN
W38 V37
PCIE_RX2P
PCIE_TX2P
PCIE_RX2N
PCIE_TX2N
24 24
BI BI
PEG_TX3_C_DP PEG_TX3_C_DN
V35 U36
PCIE_RX3P
PCIE_TX3P
PCIE_RX3N
PCIE_TX3N
24 24
BI BI
PEG_TX4_C_DP PEG_TX4_C_DN
U38 T37
PCIE_RX4P
PCIE_TX4P
PCIE_RX4N
PCIE_TX4N
24 24
BI BI
PEG_TX5_C_DP PEG_TX5_C_DN
T35 R36
PCIE_RX5P
PCIE_TX5P
PCIE_RX5N
PCIE_TX5N
24 24
BI BI
PEG_TX6_C_DP PEG_TX6_C_DN
R38 P37
PCIE_RX6P
PCIE_TX6P
PCIE_RX6N
PCIE_TX6N
24 24
BI BI
PEG_TX7_C_DP PEG_TX7_C_DN
P35 N36
PCIE_RX7P
PCIE_TX7P
PCIE_RX7N
PCIE_TX7N
N38 M37
C
PCIE_RX8P
PCIE_TX8P
PCIE_RX8N
PCIE_TX8N
M35 L36
PCIE_RX9P
PCIE_TX9P
PCIE_RX9N
PCIE_TX9N
L38 K37
PCIE_RX10P
K35 J36
PCIE_RX11P
J38 H37
PCIE_RX12P
H35 G36
PCIE_RX13P
PCIE_TX13P
PCIE_RX13N
PCIE_TX13N
G38 F37
PCIE_RX14P
PCIE_TX14P
PCIE_RX14N
PCIE_TX14N
F35 E37
PCIE_RX15P
PCIE_TX15P
PCIE_RX15N
PCIE_TX15N
PCIE_TX10P
PCI EXPRESS INTERFACE
PCIE_RX10N
PCIE_RX11N
PCIE_RX12N
PCIE_TX10N
PCIE_TX11P PCIE_TX11N
PCIE_TX12P PCIE_TX12N
Y33 Y32
PEG_RX0_DP PEG_RX0_DN
BI BI
72 72
W33 W32
PEG_RX1_DP PEG_RX1_DN
BI BI
72 72
U33 U32
PEG_RX2_DP PEG_RX2_DN
BI BI
72 72
U30 U29
PEG_RX3_DP PEG_RX3_DN
BI BI
72 72
T33 T32
PEG_RX4_DP PEG_RX4_DN
BI BI
72 72
T30 T29
PEG_RX5_DP PEG_RX5_DN
BI BI
72 72
P33 P32
PEG_RX6_DP PEG_RX6_DN
BI BI
72 72
P30 P29
PEG_RX7_DP PEG_RX7_DN
BI BI
72 72
N33 N32
N30 N29
WHISTLER M2 PRO
72
IN
PEG_RX0_DN
C5000 1
2
0.1uF_16V_2
PEG_RX0_C_DN OUT
72
IN
PEG_RX1_DN
C5001 1
2
0.1uF_16V_2
PEG_RX1_C_DN OUT
24
72
IN
PEG_RX2_DN
C5002 1
2
0.1uF_16V_2
PEG_RX2_C_DN OUT
24
72
IN
PEG_RX3_DN
C5004 1
2
0.1uF_16V_2
PEG_RX3_C_DN OUT
24
72
IN
PEG_RX4_DN
C5003 1
2
0.1uF_16V_2
PEG_RX4_C_DN OUT
24
72
IN
PEG_RX5_DN
C5006 1
2
0.1uF_16V_2
PEG_RX5_C_DN OUT
24
72
IN
PEG_RX6_DN
C5005 1
2
0.1uF_16V_2
PEG_RX6_C_DN OUT
24
72
IN
PEG_RX7_DN
C5007 1
2
0.1uF_16V_2
PEG_RX7_C_DN OUT
24
72
IN
PEG_RX0_DP
C5010 1
2
0.1uF_16V_2
PEG_RX0_C_DP
OUT
72
IN
PEG_RX1_DP
C5009 1
2
0.1uF_16V_2
PEG_RX1_C_DP
OUT
24
72
IN
PEG_RX2_DP
C5008 1
2
0.1uF_16V_2
PEG_RX2_C_DP
OUT
24
72
IN
PEG_RX3_DP
C5011 1
2
0.1uF_16V_2
PEG_RX3_C_DP
OUT
24
72
IN
PEG_RX4_DP
C5012 1
2
0.1uF_16V_2
PEG_RX4_C_DP
OUT
24
72
IN
PEG_RX5_DP
C5015 1
2
0.1uF_16V_2
PEG_RX5_C_DP
OUT
24
72
IN
PEG_RX6_DP
C5014 1
2
0.1uF_16V_2
PEG_RX6_C_DP
OUT
24
72
IN
PEG_RX7_DP
C5013 1
2
0.1uF_16V_2
PEG_RX7_C_DP
OUT
24
24
D
24
C
C IS 0402
L33 L32
L30 L29
K33 K32
J33 J32
B
B K30 K29
H33 H32
PVPCIE R5002 1 2 1.69K_1%_2
CLOCK
CLK_PEG_DP CLK_PEG_DN
BI BI
AB35 AA36
PCIE_REFCLKP
HEATHROW/CHELSEA
BI
PVPCIE
OPEN
THAMES/WHISTLER/SEYMOUR MOUNT
CALIBRATION PCIE_CALR_TX
Y30
PCIE_CALR_RX
Y29
R5005 2 1K_5%_2
AH16
PEG_PLT_RST#
AA30
A
TEST_PG
1 R5004 2
1K_5%_2
PERSTB
A
AMD_216_0834002_00_FCBGA_962P
P3V3S_DGPU C5018
5
1
BI
DGPU_HOLD_RST# 1 R5006
1
2
0.1UF_16V_2 U5001
+
72
MOUNT
THAMES/WHISTLER/SEYMOUR OPEN R215
PCIE_REFCLKN
FOR PARK AND CAPILANO THE PWRGOOD BALL MUST BE CONNNECCTED TO GND 1
R236 HEATHROW/CHELSEA
2100K_5%_2
4
PEG_PLT_RST#
BI
72
INVENTEC
-
2
3
TC7SZ08FU
TITLE 44 51
37
33
BI
MODEL,PROJECT,FUNCTION
PLT_RST#
GPU-1
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
72
80
of
1
X01
7
8
6
5
4
3
2
1
R90951
2
P3V3S_DGPU
GPU_THM_CLK
1
2 10K_5%_2
BI
GPU_THM_DAT
1
R90699 2 10K_5%_2
0_5%_2
R90710 2
1
E
Q9088 G
SSM3K7002FU
2
S
3
D
PCH_KBC_SMCLK
3 PCH_KBC_SMDATA Q9089 SSM3K7002FU D
2
BI
34
48
BI
34
48
TX3P_DPB2P
DVPDATA_1
DPB
DVPDATA_3
TX4P_DPB1P
DVPDATA_4
TX4M_DPB1N
TX5P_DPB0P
DVPDATA_6
TX5M_DPB0N
DVPDATA_7
DVPDATA_9
TXCCP_DPC3P
DVPDATA_10
TXCCM_DPC3N
G
S
1
P3V3S_DGPU
TX0P_DPC2P
DVPDATA_12
TX0M_DPC2N
DVPDATA_13 DVPDATA_14
DPC
DVPDATA_15
TX1P_DPC1P
DVPDATA_16
TX1M_DPC1N
TX2P_DPC0P
DVPDATA_19
TX2M_DPC0N
DVPDATA_21
TXCDP_DPD3P
DVPDATA_22
TXCDM_DPD3N
DPD SMBCLK
TX4P_DPD1P
SMBus
TX4M_DPD1N
SMBDATA
G
2
1
AM2321P
1
GPU_THROT#
OUT
G
1K_5%_2
P3V3S_DGPU 2
2
SSM3K7002FU
R90184 10K_5%_2
GPIO_13
GPIO_12
GPIO_11
0
0
1
2GB / 1GB (DEFAULT)
1
1
0
RESERVED
GPU_GPIO2 GPU_LCM_BLEN CTF POW_SW0 POW_SW1 POW_SW2
SI2 1227
R90160 1 R90170 1 R90154 1 R90515 1 R90107 1 R909501
73 73 73
OUT OUT OUT
GPU_GPIO11 GPU_GPIO12 GPU_GPIO13
73 73
OUT OUT
POW_SW0 POW_SW2
73 73
OUT OUT
73
OUT
SI 1115 SI2 1227
CTF SI 1115 POW_SW1
1014
10K_5%_2_DY 10K_5%_2_DY 10K_5%_2_DY
2 2 2 2 2 2
10K_5%_2_DY 10K_5%_2_DY 10K_5%_2_DY 10K_5%_2_DY 10K_5%_2_DY 10K_5%_2_DY
2 2 2 2 2
2
GPU_GPIO23
IN IN
AVSSN#1
G
GPIO_2
AVSSN#2
GPIO_5_AC_BATT GPIO_6
1
AVSSN#3
DAC1
TP9033
CLOSE TO GPU
499_1%_2 R90164
SI 1115
AF37GPU_B1 AE38
TP24
GPIO_8_ROMSO
VSYNC
RSET
AB34
AVDD
AD34 AE34
1
TP9090
TP9091
TP9092 TP24
AUD_1 TP24 1 AUD_0
TP9093 TP9094OUT
OUT
GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2
AVSSQ
R90209 1 2 499_1%_2
P1V8S_DGPU
GPIO_16
VDD1DI
GPIO_17_THERMAL_INT
VSS1DI
AC33 AC34
GPIO_18_HPD3 GPIO_19_CTF
NC#9
V13 U13 AC31 AD30 AC32 AD32 AF32 AA29 AG21
NC_TSVSSQ
AF33
GPIO_20_PWRCNTL_1
NC#1
GPIO_21
NC#2
GPIO_22_ROMCSB
NC#3
CLKREQB
NC#4
GPIO_29
NC#7
GPIO_30
NC#8
R90237 2 0_5%_2_DY
1
HEATHROW/CHELSEA
GENERICC GENERICD GENERICE_HPD4
GENERICG_HPD6
CEC_1
AK24
HPD1
2
1 R90238
GENERICF_HPD5
AC30
0_5%_2_DY
C
NC_TSVSSQ SHOULD BE TIED TO GND ON THAMES/WHISTLER/SEYMOUR
AM34
1 R90290
2
0_5%_1_DY PS_0
1 R90291
2
0_5%_1_DY PS_1
MLPS
PS_1
AD31
2
0_5%_1_DY PS_2
2
0_5%_1_DY PS_3
1 R90293
VREFG
PS_2
AG31
PS_3
AD33
OUT
AL21
DDC1CLK
AM26 AN26
TP24
73
PX_EN
B
I572
1 R90162
DEBUG
TP24
PS_0
DDC/AUX
I574
DDC1DATA
AD28
AUX1N
TP9082
GPIO24_TRSTB
1 TP24
TP9013
1
TP24
1 GPIO27_TMS TP9060 TP24
TP9015
1
TP24
AM23 AN23 1 TP24 AK23 AL24 AM24
JTAG_TRSTB JTAG_TDI
DDC2CLK DDC2DATA
JTAG_TMS
AUX2P
JTAG_TDO
AUX2N
DDCCLK_AUX3P DDCDATA_AUX3N
DDCCLK_AUX4P
1
TP9080 TP9079
10K_5%_2
1 TP24 1
AF29 AG29
DPLUS
AK32
GPIO_28_FDO
DDCDATA_AUX4N
DDCCLK_AUX5P DDCDATA_AUX5N
DDCCLK_AUX6P
I=8MA
AM19 AL19
TS_A
DDCDATA_AUX6N
DDCVGACLK
TSVDD
2
0.1UF_16V_2
C90198 1
C90197 1 2
2
C90190 1
BLM18EG601SN1D
AJ32 AJ33
1UF_6.3V_2
2
PS_2 73
AN20 AM20 AL30 AM30
TP24 TP24
1 1
TSVDD TSVSS
DDCVGADATA
OUT
73
IN
AN21 AM21
PS_1
AK30 AK29
73
1 1
GPU_DATA
B
680n
VDDC_CT
TP9014 TP9016
AL29 AM29
AJ30 AJ31
MULTI LEVEL PIN STRAP (MLPS) FOR R_PU_X AND R_PD_X AND C_X, SELECTION REFER TO AN_MGEN_X1 PARTS FOR MLPS SHOULD BE PLACED CLOSE TO ASIC THE TOTAL RESISTANCE OF TRACE SHOULD BE LESS THAN 3 OHM
82n
GPU_CLK
L9012 1
AL31
10UF_6.3V_3
P1V8S_DGPU
AM27 AL27
DMINUS
TP24
ENABLE MLPS
73
JTAG_TCK
THERMAL
R90851 2
73
OUT
TESTEN AUX1P
TP9081
73
2 R90801 1 2K_1%_2
1
P3V3S_DGPU
10K_5%_2_DY
R90191 2
1K_5%_2
2
TP24
TP9095 TP9096 TP24
AMD_216_0834002_00_FCBGA_962P
PS_3
OUT
73
2R90803 1 4.75K_1%_2
2
PS0_0 Bits[5:1]: 11|001 PS0_1 Bits[5:1]: 11|000 PS0_2 Bits[5:1]: 00|000 PS0_3 Bits[5:1]: 11|000
73
IN
5.1K_1%_2
R90190 1
73
VDDC_CT
TP9039 BACO
PX_EN
IN IN IN IN
SI 1111
TP9025 AH13
OPEN
THAMES/WHISTLER/SEYMOUR MOUNT
GENERICA GENERICB
1 R90292
SI 1115
D
I=125MA
GPIO_15_PWRCNTL_0
PS_0
C90186 0.1UF_16V_2
73 73
GPIO_9_ROMSI
GPU_VREFG
R90178 249_1%_2
10K_5%_2 10K_5%_2 10K_5%_2 3K_5%_2 3K_5%_2 3K_5%_2
TP24
AC36 AC38
TP24
AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24
TP24
GPU_G1 AE36 AD35
HSYNC
NC#5
AG32 AG33
TP24
GPU_R1 AD39 AD37
GPIO_7_BLON
TP9034
VR_TT#1
AT23 AR22
1
SI R901771 R901651 R901591 R901451 R905521 R905471
GPU_GPIO9
AU22 AV21
2
73 73 73 73 73 73
GPU_GPIO11 GPU_GPIO12 GPU_GPIO13 GPU_GPIO23 AUD_0 AUD_1
2 2 2
1
IN IN IN IN OUT OUT IN IN IN OUT IN IN
OUT
VR_TT#: REGULTOR HOT INPUT OPTION - NOT CURRENTLY QUALIFIED GPIO_29, GPIO30 ARE NC ON THAMES/WHISTLER/SEYMOUR
P1V8S_DGPU
2 2
73 73 73 73 73 73
R901821 R901711 R901851
73
AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17 AL13 AJ14 AK13 AN13
AT21 AR20
GPIO_0 GPIO_1
NC#6
1
C
GPU_GPIO0 GPU_GPIO1 GPU_GPIO9
VDDCI_SW GPU_LCM_BLEN
MEMORY APERTURE SIZE
P3V3S_DGPU
IN IN IN
OUT OUT
1
GPUTHERM_INT#
OUT IF GPIO_22_EN = 0 , THEN GPIO[13:11] DEFINES THE PRIMARY MEMORY APERTURE SIZE.
73 73 73
68 73
AU20 AT19
I2C
B
D
2
AH20 AH18 AN16
E
AT17 AR16
SDA
R
GPU_GPIO0 GPU_GPIO1 GPU_GPIO2
OUT OUT OUT
73 73 73
10K_5%_2
Q9082
R90679 1
SCL
GENERAL PURPOSE I/O
2
AU16 AV15
DVPDATA_23
TX5M_DPD0N
R90172 1 R90675 200_5%_2
AT15 AR14
DVPDATA_20
TX5P_DPD0P
AK26 AJ26
AU14 AV13
DVPDATA_17 DVPDATA_18
13
R90684 2 1
10K_5%_2
1
C90816
3
Q9084
S
D
1uF_10V_3
2 DGPU_PWR_EN#
IN
S
SI 1201
D
2
GPU_LCM_CLK GPU_LCM_DAT
OUT OUT
P3V3S_DGPU
AT33 AU32
DVPDATA_11
TX3P_DPD2P
AJ23 AH23
AR32 AT31
DVPDATA_8
TX3M_DPD2N
GPU_THM_CLK GPU_THM_DAT
OUT OUT
73 73
AV31 AU30
DVPDATA_5
SYSTEM BORAD PULL UP P3V3S
TX3M_DPB2N
DVPDATA_2
0.68uF_10V_2
BI
73
1
73
AR30 AT29
DVPCLK DVPDATA_0
OUT
SI 1207
NC
CSC0402_DY
P3V3S_DGPU
TXCBP_DPB3P TXCBM_DPB3N
2 R90804 1 0_5%_2_DY
NONE
DVPCNTL_1 DVPCNTL_2
2R90805 1 4.75K_1%_2 C90505 2 1
R90695
NONE
MEM_ID0 MEM_ID1 MEM_ID2 MEM_ID3
AT27 AR26
DVPCNTL_0
2 R90806 1 0_5%_2_DY
ELPIDA (2GB) NONE
0
6019B0971701
A
TX2M_DPA0N
DVPCNTL_MVP_1
C90512 1
0
HYNIX (2GB) (H5GQ2H24AFR-T2C)MV NEW
TX2P_DPA0P
DVPCNTL_MVP_0
2
1
1
AR8 AU8 AP8 AW8 AR3 AR1 AU1 AU3 AW3 AP6 AW5 AU5 AR6 AW6 AU6 AT7 AV7 AN7 AV9 AT9 AR10 AW10 AU10 AP10 AV11 AT11 AR12 AW12 AU12 AP12
2R90807 1 4.75K_1%_2
0
1
6019B0843001
F
AU26 AV25
2
0
6019B0971801
TX1M_DPA1N
1
0
D VEGA
TX1P_DPA1P
CSC0402_DY
HYNIX (2GB)(DEFAULT) (H5GQ2H24MFR-T2C)
AT25 AR24
SWAPLOCKB
1
SAMSUNG(2GB) (K4G20325FD-FC04) MV NEW
0
AU24 AV23
2
1
1
DPA
TX0M_DPA2N
CSC0402_DY
0
0
6019B0842201
SWAPLOCKA
2 R90800 1 8.45K_1%_2
0
0
TXCAM_DPA3N
TX0P_DPA2P
AJ21 AK21
C90501 1
0
TXCAP_DPA3P
GENLK_VSYNC
P1V8S_DGPU
2 R90802 1 0_5%_2_DY
C
GENLK_VSYNC
GENLK_CLK
C90503
SAMSUNG(2GB) (K4G20325FC-HC04)
0
MUTI GFX AD29 AC29
1
0
OUT
IEC P/N
PART 2 0F 9
10K_5%_2_DY
1 R904972 10K_5%_2_DY
0
Die Ver
VENDOR
1 R905102 10K_5%_2
0
MEM_ID0 (R497)
1 R905072 10K_5%_2_DY
MEM_ID1 (R510)
MEM_ID2 (R507)
1 R905142 10K_5%_2_DY
MEM_ID3 (R514)
F
U34
SI2 1227
1
MV 0313
NC
A
A
INVENTEC
THAMES/WHISTLER/SEYMOUR ONLY DO NOT INSTALL FOR HEATHROW/CHELSEA
TITLE
MODEL,PROJECT,FUNCTION
NC_TSVSSQ SHOULD BE TIED TO GND ON THAMES/WHISTLER/SEYMOUR PS_0 SHOULD BE TIED TO GND ON THAMES/WHISTLER/SEYMOUR
GPU-2
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
73
1
X01 of
80
8
7
6
5
4
3
2
1
U34 PART 3 0F 9
D
CHANNEL A
C
DDR3/GDDR3MEMORY STUFF OPTION GDDR5 MVDDQ
1.5V
GDDR3
DDR3
1.8V/1.5V 1.5V
RA
40.2R
40.2R
40.2R
RB
100R
100R
100R
P1V5S_DGPU 2
B
1 C5043 2
1
RB
R5083 100_1%_2
1UF_6.3V_2
R5082 40.2_1%_2
21
RA
2
P1V5S_DGPU R5084
RA
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
C37 C35 A35 E34 G32 D33 F32 E32 D31 F30 C30 A30 F28 C28 A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13 J13 H11 G10 G8 K9 K10 G9 A8 C8 E8 A6 C6 E6 A5
MVREFDA_GPU MVREFSA_GPU
L18 L20
P1V5S_DGPU
1 1 1
2 2 2
RSC_0402_DY RSC_0402_DY RSC_0402_DY
L27 N12 AG12
R5078 1 R5081 1 R5080 1
2 2 2
RSC_0402_DY 120_1%_2 120_1%_2
M12 M27 AH12
R5077 R5076 R5079
DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9
MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8 MAA1_1/MAA_9
DQA0_10
MAA1_2/MAA_10
DQA0_11
MAA1_3/MAA_11
DQA0_12 DQA0_13
MAA1_4/MAA_12 MAA1_5/MAA_BA2
DQA0_14
MAA1_6/MAA_BA0
DQA0_15
MAA1_7/MAA_BA1
G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17
DQA0_16 DQA0_17
WCKA0_0/DQMA_0
DQA0_18
WCKA0B_0/DQMA_1
DQA0_19
WCKA0_1/DQMA_2
DQA0_20
WCKA0B_1/DQMA_3
DQA0_21
WCKA1_0/DQMA_4
DQA0_22
WCKA1B_0/DQMA_5
DQA0_23
WCKA1_1/DQMA_6
DQA0_24
WCKA1B_1/DQMA_7
DQA0_26
EDCA0_0/QSA_0
DQA0_27
EDCA0_1/QSA_1
DQA0_28
EDCA0_2/QSA_2
DQA0_29
EDCA0_3/QSA_3
DQA0_30
EDCA1_0/QSA_4
DQA0_31
EDCA1_1/QSA_5
DQA1_0
EDCA1_2/QSA_6
DQA1_1
EDCA1_3/QSA_7 DDBIA0_0/QSA_0B
DQA1_4
DDBIA0_1/QSA_1B
DQA1_5
DDBIA0_2/QSA_2B
DQA1_6
DDBIA0_3/QSA_3B
DQA1_7
DDBIA1_0/QSA_4B
DQA1_8
DDBIA1_1/QSA_5B
DQA1_9
DDBIA1_2/QSA_6B
DQA1_10
DDBIA1_3/QSA_7B ADBIA0/ODTA0
DQA1_13
ADBIA1/ODTA1
79 79 79 79 79 79 79 79
C34 D29 D25 E20 E16 E12 J10 D7
EDCA0_0 EDCA0_1 EDCA0_2 EDCA0_3 EDCA1_0 EDCA1_1 EDCA1_2 EDCA1_3
BI BI BI BI BI BI BI BI
79 79 79 79 79 79 79 79
A34 E30 E26 C20 C16 C12 J11 F8
DBIA0_0 DBIA0_1 DBIA0_2 DBIA0_3 DBIA1_0 DBIA1_1 DBIA1_2 DBIA1_3
BI BI BI BI BI BI BI BI
79 79 79 79 79 79 79 79
J21 G19
ADBIA0# ADBIA1#
BI BI
79 79
H27 G27
CLKA0 CLKA0#
OUT OUT
79 79
J14 H14
CLKA1 CLKA1#
OUT OUT
79 79
K23 K19
RASA0# RASA1#
OUT OUT
79 79
K20 K17
CASA0# CASA1#
OUT OUT
79 79
K24 K27
CSA0#
OUT
79
M13 K16
CSA1#
OUT
79
K21 J20
CKEA0 CKEA1
OUT OUT
79 79
K26 L15
WEA0# WEA1#
OUT OUT
79 79
H23 J19 M21 M20
MAA0(8) MAA1(8)
DQA1_14 DQA1_15
CLKA0
DQA1_16
CLKA0B
DQA1_17 DQA1_18 DQA1_19
CLKA1 CLKA1B
DQA1_20 DQA1_21
RASA0B
DQA1_22
RASA1B
DQA1_23 DQA1_24
CASA0B
DQA1_25
CASA1B
DQA1_26 DQA1_27
CSA0B_0
DQA1_28
CSA0B_1
DQA1_29 DQA1_30
CSA1B_0
DQA1_31
CSA1B_1
MVREFDA
CKEA0
MVREFSA
CKEA1
NC_MEM_CALRN0
WEA0B
NC_MEM_CALRN1
WEA1B
79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79
BI BI BI BI BI BI BI BI
DQA1_11 DQA1_12
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
WCKA0_0 WCKA0_0# WCKA0_1 WCKA0_1# WCKA1_0 WCKA1_0# WCKA1_1 WCKA1_1#
DQA1_2 DQA1_3
MAA0(0) MAA0(1) MAA0(2) MAA0(3) MAA0(4) MAA0(5) MAA0(6) MAA0(7) MAA1(0) MAA1(1) MAA1(2) MAA1(3) MAA1(4) MAA1(5) MAA1(6) MAA1(7)
A32 C32 D23 E22 C14 A14 E10 D9
DQA0_25
D
C
B
NC_MEM_CALRN2 NC_MEM_CALRP1
MAA0_8/MAA_13
MEM_CALRP0
MAA1_8/MAA_14
MEM_CALRP2
MAA0_9/MAA_15 MAA1_9/RSVD
40.2_1%_2
TP24 TP24
1 1
BI BI
79 79
TP5018 TP5019
A
1 2
R5085 100_1%_2
C5044
RB
1UF_6.3V_2
21
M96/92 ONLY
1
A
DQA0(0) DQA0(1) DQA0(2) DQA0(3) DQA0(4) DQA0(5) DQA0(6) DQA0(7) DQA0(8) DQA0(9) DQA0(10) DQA0(11) DQA0(12) DQA0(13) DQA0(14) DQA0(15) DQA0(16) DQA0(17) DQA0(18) DQA0(19) DQA0(20) DQA0(21) DQA0(22) DQA0(23) DQA0(24) DQA0(25) DQA0(26) DQA0(27) DQA0(28) DQA0(29) DQA0(30) DQA0(31) DQA1(0) DQA1(1) DQA1(2) DQA1(3) DQA1(4) DQA1(5) DQA1(6) DQA1(7) DQA1(8) DQA1(9) DQA1(10) DQA1(11) DQA1(12) DQA1(13) DQA1(14) DQA1(15) DQA1(16) DQA1(17) DQA1(18) DQA1(19) DQA1(20) DQA1(21) DQA1(22) DQA1(23) DQA1(24) DQA1(25) DQA1(26) DQA1(27) DQA1(28) DQA1(29) DQA1(30) DQA1(31)
MEMORY INTERFACE A
GDDR5/DDR3 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79
FOR M97,BROADWAY,MADISO AND PARK ONLY IF R258,R249,R146,R244 SHOULD BE MOUNT, P/N 6013A0087806 (243OHM,1%)
AMD_216_0834002_00_FCBGA_962P
INVENTEC TITLE
MODEL,PROJECT,FUNCTION GPU-3
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
74
80
of
1
X01
8
7
6
5
4
3
2
1
U34 PART 4 0F 9
D
CHANNEL B
C
DDR3/GDDR3MEMORY STUFF OPTION GDDR5
GDDR3
DDR3
MVDDQ
1.5V
1.8V/1.5V 1.5V
RA
40.2R
40.2R
RB
100R
40.2R
100R
100R
P1V5S_DGPU 2
B
21
1UF_6.3V_2
2
1
R90210 100_1%_2
C90273 1
R90221 40.2_1%_2
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
DQB0(0) DQB0(1) DQB0(2) DQB0(3) DQB0(4) DQB0(5) DQB0(6) DQB0(7) DQB0(8) DQB0(9) DQB0(10) DQB0(11) DQB0(12) DQB0(13) DQB0(14) DQB0(15) DQB0(16) DQB0(17) DQB0(18) DQB0(19) DQB0(20) DQB0(21) DQB0(22) DQB0(23) DQB0(24) DQB0(25) DQB0(26) DQB0(27) DQB0(28) DQB0(29) DQB0(30) DQB0(31) DQB1(0) DQB1(1) DQB1(2) DQB1(3) DQB1(4) DQB1(5) DQB1(6) DQB1(7) DQB1(8) DQB1(9) DQB1(10) DQB1(11) DQB1(12) DQB1(13) DQB1(14) DQB1(15) DQB1(16) DQB1(17) DQB1(18) DQB1(19) DQB1(20) DQB1(21) DQB1(22) DQB1(23) DQB1(24) DQB1(25) DQB1(26) DQB1(27) DQB1(28) DQB1(29) DQB1(30) DQB1(31)
C5 C3 E3 E1 F1 F3 F5 G4 H5 H6 J4 K6 K5 L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5 AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6 AG4 AH5 AH6 AJ4 AK3 AF8 AF9 AG8 AG7 AK9 AL7 AM8 AM7 AK1 AL4 AM6 AM1 AN4 AP3 AP1 AP5
GDDR5/DDR3 DQB0_0
MAB0_0/MAB_0
DQB0_1
MAB0_1/MAB_1
DQB0_2
MAB0_2/MAB_2
DQB0_3
MAB0_3/MAB_3
DQB0_4
MAB0_4/MAB_4
DQB0_5
MAB0_5/MAB_5
DQB0_6
MAB0_6/MAB_6
DQB0_7
MAB0_7/MAB_7
DQB0_8 DQB0_9 DQB0_10 DQB0_11 DQB0_12 DQB0_13 DQB0_14 DQB0_15 DQB0_16 DQB0_17 DQB0_18
MAB1_0/MAB_8
MEMORY INTERFACE B
80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80
MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12 MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1 WCKB0_0/DQMB_0 WCKB0B_0/DQMB_1
DQB0_19
WCKB0_1/DQMB_2
DQB0_20
WCKB0B_1/DQMB_3
DQB0_21
WCKB1_0/DQMB_4
DQB0_22
WCKB1B_0/DQMB_5
DQB0_23
WCKB1_1/DQMB_6
DQB0_24
WCKB1B_1/DQMB_7
Y12 AA12
MAB0(0) MAB0(1) MAB0(2) MAB0(3) MAB0(4) MAB0(5) MAB0(6) MAB0(7) MAB1(0) MAB1(1) MAB1(2) MAB1(3) MAB1(4) MAB1(5) MAB1(6) MAB1(7)
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80
H3 H1 T3 T5 AE4 AF5 AK6 AK5
WCKB0_0 WCKB0_0# WCKB0_1 WCKB0_1# WCKB1_0 WCKB1_0# WCKB1_1 WCKB1_1#
BI BI BI BI BI BI BI BI
80 80 80 80 80 80 80 80
F6 K3 P3 V5 AB5 AH1 AJ9 AM5
EDCB0_0 EDCB0_1 EDCB0_2 EDCB0_3 EDCB1_0 EDCB1_1 EDCB1_2 EDCB1_3
BI BI BI BI BI BI BI BI
80 80 80 80 80 80 80 80
G7 K1 P1 W4 AC4 AH3 AJ8 AM3
DBIB0_0 DBIB0_1 DBIB0_2 DBIB0_3 DBIB1_0 DBIB1_1 DBIB1_2 DBIB1_3
BI BI BI BI BI BI BI BI
80 80 80 80 80 80 80 80
T7 W7
ADBIB0# ADBIB1#
BI BI
80 80
L9 L8
CLKB0 CLKB0#
OUT OUT
80 80
AD8 AD7
CLKB1 CLKB1#
OUT OUT
80 80
DQB0_25 DQB0_26
EDCB0_0/QSB_0
DQB0_27
EDCB0_1/QSB_1
DQB0_28
EDCB0_2/QSB_2
DQB0_29
EDCB0_3/QSB_3
DQB0_30
EDCB1_0/QSB_4
DQB0_31
EDCB1_1/QSB_5
DQB1_0
EDCB1_2/QSB_6
DQB1_1
EDCB1_3/QSB_7
DQB1_2 DQB1_3
DDBIB0_0/QSB_0B
DQB1_4
DDBIB0_1/QSB_1B
DQB1_5
DDBIB0_2/QSB_2B
DQB1_6
DDBIB0_3/QSB_3B
DQB1_7
DDBIB1_0/QSB_4B
DQB1_8
DDBIB1_1/QSB_5B
DQB1_9
DDBIB1_2/QSB_6B
DQB1_10
DDBIB1_3/QSB_7B
DQB1_11 DQB1_12
ADBIB0/ODTB0
DQB1_13
ADBIB1/ODTB1
DQB1_14 DQB1_15
CLKB0
DQB1_16
CLKB0B
DQB1_17 DQB1_18
CLKB1
DQB1_19
CLKB1B
DQB1_20 DQB1_21
RASB0B
DQB1_22
RASB1B
T10 Y10
RASB0# RASB1#
OUT OUT
80 80
W10 AA10
CASB0# CASB1#
OUT OUT
80 80
P10 L10
CSB0#
OUT
80
AD10 AC10
CSB1#
OUT
80
DQB1_23 DQB1_24
CASB0B
DQB1_25
CASB1B
DQB1_26 DQB1_27
CSB0B_0
DQB1_28
CSB0B_1
DQB1_29 DQB1_30
CSB1B_0
DQB1_31
CSB1B_1 CKEB0
MVREFDB_GPU MVREFSB_GPU
P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9
CKEB1
MVREFDB
U10 AA11
CKEB0 CKEB1
OUT OUT
80 80
N10 AB11
WEB0# WEB1#
OUT OUT
80 80
T8 W8 U12 V12
MAB0(8) MAB1(8)
MVREFSB WEB0B WEB1B
D
C
B
P1V5S_DGPU 2
MAB0_8/MAB_13 MAB1_8/MAB_14 MAB0_9/MAB_15
R90194 40.2_1%_2
MAB1_9/RSVD
80 80
BI BI TP9042 TP9041
M96/92 ONLY
AH11
AMD_216_0834002_00_FCBGA_962P
R90509
R90496 2
1
10_5%_2
2 VM_RST#
IN
79
80
120PF_50V_2
C90639 1
51_1%_2
2
1
R90513 2
1
4.99K_1%_2
2
TP24
A
1UF_6.3V_2
21 1
R90198 100_1%_2
C90233 1
DRAM_RST
A
1 1
TP24
INVENTEC TITLE
MODEL,PROJECT,FUNCTION GPU-4
SIZE A3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
75
80
of
1
X01
7
8
6
5
4
3
2
1
HEATHROW/CHELSEA THAMES/WHISTLER/SEYMOUR PCIE_VDDC
0.935V
1V
VDDCI
0.95V
1V
F
F
P1V8S_DGPU
NC_PCIE_VDDR#2 NC_PCIE_VDDR#3
VDDR1#4
NC_PCIE_VDDR#4
VDDR1#5
NC_PCIE_VDDR#5
VDDR1#6
NC_PCIE_VDDR#6
VDDR1#7
NC_BIF_VDDC#1
VDDR1#8 VDDR1#9
PCIE
VDDR1#3
NC_BIF_VDDC#2 PCIE_PVDD
VDDR1#25
BIF_VDDC#2
VDDC#52 VDDC#53 VDDC#54 VDDC#55
VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4
B
VDDCI#5
VOLTAGE SENESE
AF28
FB_VDDC
AG28
FB_VDDCI
AH29
FB_GND
ISOLATED CORE I/O
VDDCI#6 VDDCI#7 VDDCI#8 VDDCI#9 VDDCI#10 VDDCI#11 VDDCI#12 VDDCI#13 VDDCI#14 VDDCI#15 VDDCI#16 VDDCI#17
SI 1115
VDDCI#18 VDDCI#19 VDDCI#20 VDDCI#21 VDDCI#22
C90240 1
1UF_6.3V_2
2 C90244 1
1UF_6.3V_2
2 C90245 1
2.2UF_6.3V_2
2 C90216 1 2
10UF_6.3V_3
C90223 1 2 C90208 1 2 C90225 1 2 C90257 1 2
C90278 1
1UF_6.3V_2
2 C90221 1 2
1UF_6.3V_2
C90277 1
2.2UF_6.3V_2
2 C90180 1 2
10UF_6.3V_3
C90242 1 2
1UF_6.3V_2
1UF_6.3V_2 1UF_6.3V_2 2.2UF_6.3V_2
C90226 1
1UF_6.3V_2
2 C90222 1
C90264
10UF_6.3V_3 2 1
C90259 1 2
1UF_6.3V_2
C90232 1
1 C90307 2
10UF_6.3V_3
2
2.2uF_6.3V_2
C90281 1
C90289 1 2
1UF_6.3V_2
C90370 1 2
1UF_6.3V_2
C90299 1 2
VDDCI AND VDDC SHOULD HAVE REGULATORS WITH A MERGE OPTION ON PVB
I=33A
D
PVDDCI
I=3.6A~6A
PEAK=4A VDDCI
AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13
C90298 1
VDDC#50
2
VDDC#49
2.2UF_6.3V_2
VDDC#48
VDDC#51
C90211 1
VDDC#47
2
VDDC#46
1UF_6.3V_2
VDDC#45
C90295 1
VDDC#44
2
VDDC#43
C90239 1
VDDC#42
2
VDDC#40
C90296 1
VDDC#39
2
VDDC#38
VDDC#41
PVCORE_DGPU
C
2.2UF_6.3V_2
VDDC#37
C90206 1
VDDC#36
2
VDDC#33 VDDC#34
1UF_6.3V_2
VDDC#32
VDDR4#7 VDDR4#8
C90293 1
VDDC#31
VDDR4#6
2
2
0.1UF_16V_2
C90616 1
1UF_6.3V_2
2
VDDR4#5
AH22 AH27 AH28 M26 N24 R18 R21 R23 R26 T17 T20 T22 T24 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28
C90297 1
VDDC#28
2
VDDC#27
10UF_6.3V_3
VDDC#26
VDDR4#4
2.2UF_6.3V_2
VDDC#25
VDDR4#3
1UF_6.3V_2
VDDC#24
VDDR4#2
2
VDDC#23
VDDR4#1
2.2UF_6.3V_2
VDDC#22
VDDR3#4
C90188 1
VDDR3#3
2
VDDC#21
10UF_6.3V_3
VDDC#20
VDDR3#2
C90274 1
VDDC#19
VDDR3#1
2
VDDC#16
C90294 1
VDDC#14 VDDC#15
VDD_CT#4
2
VDDC#13
VDDC#12
VDD_CT#2 VDD_CT#3
2.2UF_6.3V_2
VDD_CT#1
1UF_6.3V_2
VDDC#11
2
2
LEVEL TRANSLATION
C90247 1
VDDC#6
2
VDDR1#34
1UF_6.3V_2 C90209 2 1
VDDC#5
C90261 1
VDDC#4
2
VDDC#3
VDDR1#32 VDDR1#33
1UF_6.3V_2 C90227 2 1
VDDR1#31
VDDC#35
SI 1115
SI 1014
(27.2A)
AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18
C90207 1
VDDC#2
2
VDDC#1
2.2UF_6.3V_2 C90243 2 1
CORE
VDDR1#30
C90213 1
VDDR1#29
DVP
AF15 AG11 AG13 AG15
R90861 2 0_5%_2
VDDR1#28
VDDC#30
VDDR4
1
N27 T27
VDDR1#27
VDDC#29
2
PVPCIE
I=1.2A BACO
VDDR1#26
BIF_VDDC#1
1UF_6.3V_2
PCIE_VDDC#12
VDDR1#24
I=2.5A
1UF_6.3V_2
PCIE_VDDC#11
VDDR1#22 VDDR1#23
1UF_6.3V_2
PCIE_VDDC#10
VDDR1#21
2.2UF_6.3V_2
VDDR1#20
PVPCIE
MOUNT
22UF_6.3V_5
PCIE_VDDC#9
OPEN
2.2UF_6.3V_2
PCIE_VDDC#8
VDDR1#19
OPEN
THAMES/WHISTLER/SEYMOUR OPEN
22UF_6.3V_5
VDDR1#18
M96 FOR +V1.8S_VGA
C90615 1
1
E
1UF_6.3V_2 C90246 2 1
PCIE_VDDC#7
R231 L14
1UF_6.3V_2 C90279 2 1
VDDR1#17
HEATHROW/CHELSEA
R208
2.2UF_6.3V_2 C90241 2 1
PCIE_VDDC#6
I=300MA
BLM18PG600SN1D
C
SI 1011
G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28
22UF_6.3V_5 C90285 2 1
PCIE_VDDC#5
VDDR1#16
VDDC#18
AD12 AF11 AF12 AF13
PVPCIE R90208 2 1 0_5%_2_DY
2.2UF_6.3V_2 C90291 2 1
PCIE_VDDC#3 PCIE_VDDC#4
VDDR1#15
VDDC#17
AF23 AF24 AG23 AG24
P1V8S_DGPU L9023
AF26 AF27 AG26 AG27
TP90000 TP90001 TP90002 TP90003 TP90004 TP90005
22UF_6.3V_5 C90284 2 1
PCIE_VDDC#2
VDDR1#13 VDDR1#14
I/O
1UF_6.3V_2
C90210 1
C90184 1 2
C90200 2 1 0.1UF_16V_2
2
C90189 1
1UF_6.3V_2
2
10UF_6.3V_3
C90130 1
I=60MA 10UF_6.3V_3
P3V3S_DGPU
VDDC_CT
TP30 TP30 TP30 TP30 TP30 TP30
C90282 1
VDDR1#12
VDDC#8
2
1 1 1 1 1 1
2
PCIE_VDDC#1
VDDC#10
I=250MA
AA31 AA32 AA33 AA34 W30 Y31 V28 W29 AB37
2.2uF_6.3V_2
VDDR1#11
VDDC#7
P1V8S_DGPU L907
SI 1011
VDDR1#10
VDDC#9
1
2
2 NC_PCIE_VDDR#1
VDDR1#2
1 R902312 0_5%_2_DY
VDDR1#1
D
FBM_11_160808_121T
L9014 1 2 BLM18PG121SN1
MEM I/O AC7 AD11 AF7 AG10 AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10 J7 J9 K11 K13 K8 L12 L16 L21 L23 L26 L7 M11 N11 P7 R11 U11 U7 Y11 Y7
10UF_6.3V_3 C90315 2 1
C90214 1 2 C90366 1 2 C90721 1 2
0.1UF_16V_2 1UF_6.3V_2 2.2UF_6.3V_2
2
C90201 1
2
C90272 1
2
C90391 1
2
C90347 1
10UF_6.3V_3
FOR DDR3,MVDDQ=1.5V
0.1UF_16V_2 1UF_6.3V_2 2.2UF_6.3V_2
C90217 1 2 C90311 1 2 C90340 1 2 C90381 1 2
10UF_6.3V_3
I=3.4A
0.1UF_16V_2 1UF_6.3V_2 2.2UF_6.3V_2
C90337 1
22UF_6.3V_5
2 C90286 1 2 C90324 1 2 C90379 1 2
0.1UF_16V_2 1UF_6.3V_2 2.2UF_6.3V_2
+
C90598 1
P1V5S_DGPU
220UF_2V
2
E
PART 5 0F 9
1UF_6.3V_2
U34
P1V5S_DGPU
C90229 2 1 0.1UF_16V_2
C90258 1
0.1UF_16V_2
1.8V 440MA PCIE_VDDR
B
AMD_216_0834002_00_FCBGA_962P
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION GPU-5
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
76
1
X01 of
80
8 7 6
AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13
A39 AW1 AW39
GND#135 GND#136 GND#137 GND#138 GND#139 GND#140 GND#141 GND#142 GND#143 GND#144 GND#145 GND#146 GND#147 GND#148 GND#149 GND#150 GND#151 GND#152 GND#153 GND#154 GND#155 GND#156 GND#157 GND#158 GND#159 GND#160 GND#161 GND#162 GND#163 GND#164 GND#165 GND#166 GND#167 GND#168 GND#169 GND#170 GND#171
VSS_MECH#1 VSS_MECH#2 VSS_MECH#3
5
5
4
4
3
CHANGE by
XXX
3 DATE
21-OCT-2002
2
AMD_216_0834002_00_FCBGA_962P
GND
A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86 GND#87 GND#88 GND#89 GND#90 GND#91 GND#92 GND#93 GND#94 GND#95 GND#96 GND#97 GND#98 GND#99 GND#100 GND#101 GND#102 GND#103 GND#104 GND#105 GND#106 GND#107 GND#108 GND#109 GND#110 GND#111 GND#112 GND#113 GND#114 GND#115 GND#116 GND#117 GND#118 GND#119 GND#120 GND#121 GND#122 GND#123 GND#124 GND#125 GND#126 GND#127 GND#128 GND#129 GND#130 GND#131 GND#132 GND#133 GND#134
6
GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8 GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55 GND#56 GND#57 GND#58 GND#59 GND#60 GND#61 GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74
PCIE_VSS#1 PCIE_VSS#2 PCIE_VSS#3 PCIE_VSS#4 PCIE_VSS#5 PCIE_VSS#6 PCIE_VSS#7 PCIE_VSS#8 PCIE_VSS#9 PCIE_VSS#10 PCIE_VSS#11 PCIE_VSS#12 PCIE_VSS#13 PCIE_VSS#14 PCIE_VSS#15 PCIE_VSS#16 PCIE_VSS#17 PCIE_VSS#18 PCIE_VSS#19 PCIE_VSS#20 PCIE_VSS#21 PCIE_VSS#22 PCIE_VSS#23 PCIE_VSS#24 PCIE_VSS#25 PCIE_VSS#26 PCIE_VSS#27 PCIE_VSS#28 PCIE_VSS#29 PCIE_VSS#30 PCIE_VSS#31 PCIE_VSS#32 PCIE_VSS#33 PCIE_VSS#34 PCIE_VSS#35
PART 6 0F 9
7
F15 F17 F19 F21 F23 F25 F27 F29 F31 F33 F7 F9 G2 G6 H9 J2 J27 J6 J8 K14 K7 L11 L17 L2 L22 L24 L6 M17 M22 M24 N16 N18 N2 N21 N23 N26 N6 R15 R17 R2 R20 R22 R24 R27 R6 T11 T13 T16 T18 T21 T23 T26 U15 U17 U2 U20 U22 U24 U27 U6 V11 V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y22 Y24 Y27
AB39 E39 F34 F39 G33 G34 H31 H34 H39 J31 J34 K31 K34 K39 L31 L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39 W31 W34 Y34 Y39
B U34
8 2 1
D D
C C
SIZE A3
B
A A
INVENTEC TITLE
CODE
MODEL,PROJECT,FUNCTION
CS
GPU-6
1310xxxxx-0-0
DOC.NUMBER
SHEET 77 of
1
REV
80
X01
7
8
6
5
4
3
2
1
F
F
CHECK POWER NET
U34
CHECK POWER NET
PART 8 0F 9 DP_VDDR
P1V0S_DGPU_DPEF_VDD DP_VDDC
P1V8S_DPE_VDD18
I=222MA DP_VDDC#1 DP_VDDC#2 DP_VDDC#3 DP_VDDC#4
AF35 AG36
DP_VSSR#16 DP_VSSR#17 DP_VSSR#18
CALIBRATION
DP_VSSR#19 DP_VSSR#20 DP_VSSR#21
GPU_LCM_L1_TXCL_DP GPU_LCM_L1_TXCL_DN
OUT OUT
R90516 1
DP_VSSR#22
AW28
2
DPAB_CALR
DP_VSSR#23 DP_VSSR#24
TXOUT_L0N_DPE2N
TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N
TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N
TXOUT_L3P
GPU_LCM_L1_TXDL0_DP GPU_LCM_L1_TXDL0_DN
OUT OUT
AR37 AU39
GPU_LCM_L1_TXDL1_DP GPU_LCM_L1_TXDL1_DN
OUT OUT
AP35 AR35
GPU_LCM_L1_TXDL2_DP GPU_LCM_L1_TXDL2_DN
OUT OUT
150_1%_2 R90511 1 2
DP_VSSR#25 DP_VSSR#26
AW18
DPCD_CALR
DP_VSSR#27 DP_VSSR#28
150_1%_2 R90545 1 2
DP_VSSR#29 DP_VSSR#30
AM39
DPEF_CALR
DP_VSSR#31 DP_VSSR#32
150_1%_2
DP_VSSR#33
AN36 AP37
DP_VSSR#34
C90644 1
P1V8S_DPE_VDD18 L9011
I=237MA
2
2
1
AW34
GPU_XOIN_27M
IN
78
SPLL_VDDC
XO_IN2
AW35
GPU_XOIN2_100M
IN
78
AN10
SPLL_PVSS
AF30 AF31
NC_XTAL_PVDD
D
CLKTESTB
AK10 AL10
NC_XTAL_PVSS
AMD_216_0834002_00_FCBGA_962P
OPEN
1 C903 2
C90631 1
C90645 1 2
C
C90650 1
C90199 1 2
R90760 2
5.1K_5%_2
1 R907612
1 1
R90153 2
0.01UF_50V_2
0.01UF_50V_2 C90176 2 1
C90179 1 2
SI 1107 6018B0052601 X904 1
3
4
2 27MHZ
1
1
2 R90521 1M_5%_2 U9010 X1_ICLK
X2
10
B
4 8
VDD_100M
7 3
S0
6 2
GND_PLL
VDD_27M
R90519 33_5%_2 2 GPU_XOIN2_100M
100M
5
1
27M
9
1 R90525 33_5%_2 2 GPU_XOIN_27M
TML
11
S1
GND_27M
OUT
78
OUT
78
IDT_6V40088_DFN_10P
1
L9027 1 2 FBM_11_160808_121T
5.1K_5%_2
R90157 2
P3V3S_DGPU
2.2UF_6.3V_2 C90154 2 1
C90187 1 2
0.1UF_16V_2
C90183 1 2
XO_IN
THAMES/WHISTLER/SEYMOUR MOUNT
P3V3S_DGPU
I=222MA 10UF_6.3V_3
AN9
HEATHROW/CHELSEA
P1V0S_DGPU_DPEF_VDD
B
SPLL_PVDD
CLKTESTA
PVPCIE
I=500MA
TP909 TP24
0.1UF_16V_2
C90195 1 2
10UF_6.3V_3
BLM18PG600SN1D
1 2 L9010 BLM18PG600SN1D
1
SPV10
1 2 L9025 FBM_11_160808_121T
P1V8S_DGPU
AU34
150MA SPV10
AMD_216_0834002_00_FCBGA_962P
C
AM10
SPV18
1 2 L905 FBM_11_160808_121T
PVPCIE
AMD_216_0834002_00_FCBGA_962P
XTALOUT
TP9012 TP24
1.8V 75MA SPV18
2
TXOUT_L3N
AW37 AU35
1
MPLL_PVDD#1
C90658 1
TXOUT_L0P_DPE2P
AV33
MPLL_PVDD#2
2
AP34 AR34
2 L906 FBM_11_160808_121T
MPV18
1
XTALIN
10pF_50V_2
TXCLK_LN_DPE3N
DPLL_PVSS
1.8V 150MA MPV18
2
TXCLK_LP_DPE3P
AN32
P1V8S_DGPU
10pF_50V_2
D
DPLL_VDDC
PLLS/XTAL
TXOUT_U3N
DPLL_PVDD
AN31
0_5%_2_DY
DP_VSSR#13 DP_VSSR#14 DP_VSSR#15
TXOUT_U3P
5.1K_5%_2_DY
TXOUT_U2N_DPF0N
0_5%_2
TXOUT_U2P_DPF0P
AM32
H7 H8
1
DP_VSSR#12
0.1UF_16V_2
DP_VSSR#11
AG38 AH37
R90235 2
DP_VSSR#9
DPLL_VDDC
C90648 1
DP_VSSR#8
2
2
DP_VSSR#7
DP_VSSR#10
L901 FBM_11_160808_121T
1UF_6.3V_2
DP_VDDR#18
SI 1115
AH35 AJ36
I=140MA 1
C90638 1
DP_VSSR#6
PVPCIE
2
DP_VDDR#17
AN27 AP27 AP28 AW24 AW26 AN29 AP29 AP30 AW30 AW32 AN17 AP16 AP17 AW14 AW16 AN19 AP18 AP19 AW20 AW22 AN34 AP39 AR39 AU37 AF39 AH39 AK39 AL34 AV27 AR28 AV17 AR18 AN38 AM35
10UF_6.3V_3
DP_VSSR#5
1
TXOUT_U1N_DPF1N
AJ38 AK37
DP_VSSR#3 DP_VSSR#4
DP_VDDR#16
C90143
TXOUT_U1P_DPF1P
DP_VSSR#2
DP_VDDR#14 DP_VDDR#15
2
TXOUT_U0N_DPF2N
PART 9 0F 9
0.1UF_16V_2
TXOUT_U0P_DPF2P
DP_VSSR#1
AK35 AL36
C90647 1
TXCLK_UN_DPF3N
E
U34
DP GND
DP_VDDR#13
2
TXCLK_UP_DPF3P
AH34 AJ34 AF34 AG34 AM37 AL38
0.1UF_16V_2
2
DP_VDDR#11 DP_VDDR#12
BACK LIGHT POWER CONTORL
C90144 1
OUT OUT
DP_VDDC#12
DP_VDDR#10
2
GPU_LCM_PWM GPU_LCM_VCC_EN
1V
DPLL_PVDD
0.1UF_16V_2
AK27 AJ27
DP_VDDR#8 DP_VDDR#9
10UF_6.3V_3
DIGON
BACK LIGHT BRIGHTNESS MODULATE NO CONNECTOR
DP_VDDC#11
0.1UF_16V_2
1 VARY_BL
LVDS CONTROL
TP24
PART 7 0F 9
DP_VDDR#7
AL33 AM33 AK33 AK34
1
AP20 AP21 AP22 AP23 AU18 AV19
TP9019
I=75MA 1 L9021 2 FBM_11_160808_121T
C90612 1
DP_VDDC#9
C90129
U34
P1V8S_DGPU
DP_VDDR#6
DP_VDDC#10
E
AP13 AT13 AP14 AP15
2
DP_VDDC#8
1UF_6.3V_2
DP_VDDC#7
DP_VDDR#5
10UF_6.3V_3
DP_VDDC#6
DP_VDDR#4
2
10K_5%_2 10K_5%_2
DP_VDDC#5
DP_VDDR#2 DP_VDDR#3
10UF_6.3V_3
2 2
0.935V
DP_VDDR#1
C90128 1
R901761 R901681
AN24 AP24 AP25 AP26 AU28 AV29
HEATHROW/CHELSEA THAMES/WHISTLER/SEYMOUR
DP_VDDC DPLL_VDDC SPLL_VDDC
AP31 AP32 AN33 AP33
10UF_6.3V_3
I=237MA
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION GPU-7
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
78
1
X01 of
80
7
8
6
5
4
3
2
1
U5501 U5500
F
P1V5S_DGPU
79 79
74 74
260.4_1%_2 260.4_1%_2
CLKA0 R5517 1 CLKA0# R5518 1
IN IN
DQA0(7) DQA0(0) DQA0(6) DQA0(2) DQA0(4) DQA0(1) DQA0(5) DQA0(3) DQA0(9) DQA0(10) DQA0(8) DQA0(11) DQA0(12) DQA0(14) DQA0(15) DQA0(13) DQA0(24) DQA0(25) DQA0(29) DQA0(27) DQA0(26) DQA0(28) DQA0(31) DQA0(30) DQA0(22) DQA0(21) DQA0(23) DQA0(20) DQA0(17) DQA0(19) DQA0(18) DQA0(16)
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74
M2 M4 N2 N4 T2 T4 V2 V4 M13 M11 N13 N11 T13 T11 V13 V11 F13 F11 E13 E11 B13 B11 A13 A11 F2 F4 E2 E4 B2 B4 A2 A4
DQ31|DQ7
VDDQ-B1
DQ30|DQ6
VDDQ-B3
DQ29|DQ5
VDDQ-B12
DQ28|DQ4
VDDQ-B14
DQ27|DQ3
VDDQ-D1
DQ26|DQ2
VDDQ-D3
DQ25|DQ1
VDDQ-D12
DQ24|DQ0
VDDQ-D14
DQ23|DQ15
VDDQ-E5
DQ22|DQ14
VDDQ-E10
DQ21|DQ13
VDDQ-F1
DQ20|DQ12
VDDQ-F3
DQ19|DQ11
VDDQ-F12
DQ18|DQ10
VDDQ-F14
DQ17|DQ9
VDDQ-G2
DQ16|DQ8
VDDQ-G13
DQ15|DQ23
VDDQ-H3
DQ14|DQ22
VDDQ-H12
DQ13|DQ21
VDDQ-K3
DQ12|DQ20
VDDQ-K12
DQ11|DQ19
VDDQ-L2
DQ10|DQ18
VDDQ-L13
DQ9|DQ17
VDDQ-M1
DQ8|DQ16
VDDQ-M3
DQ7|DQ31
VDDQ-M12
DQ6|DQ30
VDDQ-M14
DQ5|DQ29
VDDQ-N5
DQ4|DQ28
VDDQ-N10
DQ3|DQ27
VDDQ-P1
DQ2|DQ26
VDDQ-P3
DQ1|DQ25
VDDQ-P12
DQ0|DQ24
VDDQ-P14 VDDQ-T1 VDDQ-T3 VDDQ-T12 VDDQ-T14
E
MAA0(8) MAA0(0) MAA0(1) MAA0(3) MAA0(2) MAA0(5) MAA0(4) MAA0(6) MAA0(7)
BI BI BI BI BI BI BI BI BI
74 74 74 74 74 74 74 74 74
J5 K4 K5 K10 K11 H10 H11 H5 H4
A7/A8|A0/A10
VDD-C5
A6/A11|A1/A9
VDD-C10
A5/BA1|A3/BA3
VDD-D11
A4/BA2|A2/BA0
VDD-G1
A3/BA3|A5/BA1
VDD-G4
A2/BA0|A4/BA2
VDD-G11
A1/A9|A6/A11
VDD-G14
A0/A10|A7/A8
VDD-L1 VDD-L4
VDD-L14
74 74
IN IN
D4 WCKA0_1 WCKA0_1# D5
WCK01|WCK23
74 74
IN IN
P4 WCKA0_0 WCKA0_0# P5
WCK23|WCK01
OUT OUT OUT OUT
EDCA0_0 EDCA0_1 EDCA0_3 EDCA0_2
R2 R13 C13 C2
BI BI BI BI
DBIA0_0 DBIA0_1 DBIA0_3 DBIA0_2
P2 P13 D13 D2
G3 L3
J3 J11 J12
VDD-P11 VDD-R5
WCK01#|WCK23#
VDD-R10
EDC3|EDC0
VSSQ-A3
EDC2|EDC1
VSSQ-A12
EDC1|EDC2
VSSQ-A14
EDC0|EDC3
VSSQ-C1
DBI3#|DBI0#
VSSQ-C4
DBI2#|DBI1#
VSSQ-C11
DBI1#|DBI2#
VSSQ-C12
DBI0#|DBI3#
VSSQ-C14 VSSQ-E1 VSSQ-E3 VSSQ-E12
74 74
IN IN
CASA0# RASA0#
74 74 74
IN BI BI
CKEA0 CLKA0# CLKA0
RAS#|CAS#
VSSQ-E14
CAS#|RAS#
VSSQ-F5 VSSQ-F10 VSSQ-H2
79 79
CKE#
VSSQ-H13
CK#
VSSQ-K2
CK
VSSQ-K13 VSSQ-M5 VSSQ-M10
74 74
WEA0# CSA0#
IN IN
G12 L12
CS#|WE#
VSSQ-N1 VSSQ-N3
WE#|CS#
VSSQ-N12
R5519
1 1
R5500
VSSQ-N14
120_1%_2
2 2
J13 J10
1K_5%_2
VSSQ-R1
ZQ
VSSQ-R3
SEN
VSSQ-R4
P1V5S_DGPU
VSSQ-R11
P1V5S_DGPU
C
80
79
75
VM_RST#
IN
J2 J1
RESET#
VSSQ-R12
MF
VSSQ-R14 VSSQ-V1
C55101
2
R5524 1
2
R5525 1
2
5.49K_1%_2
C5511 1
2
1UF_6.3V_2
1UF_6.3V_2_DY 2.37K_1%_2
1
2
VSSQ-V3
1K_5%_2
VSSQ-V12
R5501
VSSQ-V14
A5 V5
VSS-B10
VREFD2
VSS-D10 VSS-G5 VSS-G10 VSS-H1 VSS-H14 VSS-K1
2
R55211
2
5.49K_1%_2
C55071
2
1UF_6.3V_2
J14
1UF_6.3V_2_DY 2.37K_1%_2
HYNIX SAMSUNG HYNIX
K4G20325FD-FC04
6019B0971801
64MX32
H5GQ2H24AFR-T2C
6019B0971701
64MX32
K4G20325FC-HC04
6019B0842201
64MX32
H5GQ2H24MFR-T2C
6019B0843001
P1V5S_DGPU
VSS-K14
VREFC
VSS-L5 VSS-L10 VSS-P10
J4
B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14
VDDQ-B1
DQ30|DQ6
VDDQ-B3
DQ29|DQ5
VDDQ-B12
DQ28|DQ4
VDDQ-B14
DQ27|DQ3
VDDQ-D1
DQ26|DQ2
VDDQ-D3
DQ25|DQ1
VDDQ-D12
DQ24|DQ0
VDDQ-D14
DQ23|DQ15
VDDQ-E5
DQ22|DQ14
VDDQ-E10
DQ21|DQ13
VDDQ-F1
DQ20|DQ12
VDDQ-F3
DQ19|DQ11
VDDQ-F12
DQ18|DQ10
VDDQ-F14
DQ17|DQ9
VDDQ-G2
DQ16|DQ8
VDDQ-G13
DQ15|DQ23
VDDQ-H3
DQ14|DQ22
VDDQ-H12
DQ13|DQ21
VDDQ-K3
DQ12|DQ20
VDDQ-K12
DQ11|DQ19
VDDQ-L2
DQ10|DQ18
VDDQ-L13
DQ9|DQ17
VDDQ-M1
DQ8|DQ16
VDDQ-M3
DQ7|DQ31
VDDQ-M12
DQ6|DQ30
VDDQ-M14
DQ5|DQ29
VDDQ-N5
DQ4|DQ28
VDDQ-N10
DQ3|DQ27
VDDQ-P1
DQ2|DQ26
VDDQ-P3
DQ1|DQ25
VDDQ-P12
DQ0|DQ24
VDDQ-P14 VDDQ-T1 VDDQ-T3 VDDQ-T12
79 79
74 74
IN IN
260.4_1%_2 260.4_1%_2
CLKA1 R5509 1 CLKA1# R5508 1
VDDQ-T14
BI BI BI BI BI BI BI BI BI
74 74 74 74 74 74 74 74 74
C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10
MAA1(8) MAA1(7) MAA1(6) MAA1(5) MAA1(4) MAA1(3) MAA1(2) MAA1(1) MAA1(0)
J5 K4 K5 K10 K11 H10 H11 H5 H4
E
A7/A8|A0/A10
C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10
VDD-C5
A6/A11|A1/A9
VDD-C10
A5/BA1|A3/BA3
VDD-D11
A4/BA2|A2/BA0
VDD-G1
A3/BA3|A5/BA1
VDD-G4
A2/BA0|A4/BA2
VDD-G11
A1/A9|A6/A11
VDD-G14
A0/A10|A7/A8
VDD-L1 VDD-L4 VDD-L11 VDD-L14
74 74 74 74
IN IN
WCKA1_0 D4 WCKA1_0# D5
WCK01|WCK23
IN IN
WCKA1_1 P4 WCKA1_1# P5
WCK23|WCK01
OUT OUT OUT OUT
EDCA1_3 EDCA1_2 EDCA1_0 EDCA1_1
VDD-P11 VDD-R5
WCK01#|WCK23#
VDD-R10
A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 V1 V3 V12 V14
74 74 74 74
WCK23#|WCK01#
R2 R13 C13 C2
EDC3|EDC0
A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 V1 V3 V12 V14
VSSQ-A3
EDC2|EDC1
VSSQ-A12
EDC1|EDC2
VSSQ-A14
EDC0|EDC3
VSSQ-C1 VSSQ-C3
DBIA1_3 DBIA1_2 DBIA1_0 DBIA1_1
BI BI BI BI
74 74 74 74
P2 P13 D13 D2
DBI3#|DBI0#
VSSQ-C4
DBI2#|DBI1#
VSSQ-C11
DBI1#|DBI2#
VSSQ-C12
DBI0#|DBI3#
VSSQ-C14
RAS#|CAS#
VSSQ-E14
CAS#|RAS#
VSSQ-F5
VSSQ-E1 VSSQ-E3 VSSQ-E12
74 74
IN IN
RASA1# CASA1#
G3 L3
74 74 74
IN BI BI
CKEA1 CLKA1# CLKA1
J3 J11 J12
IN IN
CSA1# WEA1#
G12 L12
VSSQ-F10 VSSQ-H2
79 79
CKE#
VSSQ-H13
CK#
VSSQ-K2
CK
VSSQ-K13 VSSQ-M5 VSSQ-M10
74 74
CS#|WE#
VSSQ-N1 VSSQ-N3
WE#|CS#
VSSQ-N12 VSSQ-N14
R5510 R5502
1 1
2 2
J13 J10
120_1%_2 1K_5%_2
VSSQ-R1
ZQ SEN
VSSQ-R3 VSSQ-R4 VSSQ-R11
P1V5S_DGPU
80
C55001
2
R55121
2
R55111
2
C55011
2
79
75
VM_RST#
IN
1
2
J2 J1
RESET#
VSSQ-R12
MF
VSSQ-R14 VSSQ-V1
1K_5%_2
R5503
1UF_6.3V_2_DY 2.37K_1%_2
VSSQ-V3 VSSQ-V12 VSSQ-V14
5.49K_1%_2
ABI#
VSS-T5 VSS-T10
B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10
A5 V5
1UF_6.3V_2
C
Vpp,NC1
VREFD1
VSS-B10
VREFD2
VSS-D10
B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10
VSS-G5 VSS-G10
P1V5S_DGPU
VSS-H1 VSS-H14 VSS-K1
2
R55131
2
R55141
2
5.49K_1%_2
C55031
2
1UF_6.3V_2
J14
1UF_6.3V_2_DY 2.37K_1%_2
D
Vpp,NC
A10 V10
C55021
F
RFU/A12/NC
VSS-B5
VREFD1
P1V5S_DGPU
R55201
64MX32
DQ31|DQ7
Vpp,NC1 VSS-B5
2
SAMSUNG
IEC PN
VENDER PN
Vpp,NC
A10 V10
C55061
DENSITY
M2 M4 N2 N4 T2 T4 V2 V4 M13 M11 N13 N11 T13 T11 V13 V11 F13 F11 E13 E11 B13 B11 A13 A11 F2 F4 E2 E4 B2 B4 A2 A4
VSSQ-A1
VSSQ-C3
D
MV 0313 VENDER
DQA1(25) DQA1(29) DQA1(27) DQA1(28) DQA1(26) DQA1(31) DQA1(24) DQA1(30) DQA1(21) DQA1(20) DQA1(22) DQA1(23) DQA1(19) DQA1(16) DQA1(18) DQA1(17) DQA1(5) DQA1(7) DQA1(6) DQA1(2) DQA1(3) DQA1(1) DQA1(4) DQA1(0) DQA1(8) DQA1(9) DQA1(10) DQA1(11) DQA1(15) DQA1(13) DQA1(12) DQA1(14)
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74
CHANNEL A MEMORY
WCK23#|WCK01# VSSQ-A1
74 74 74 74
B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14
RFU/A12/NC
VDD-L11
74 74 74 74
P1V5S_DGPU
P1V5S_DGPU
VSS-K14
VREFC
VSS-L5 VSS-L10 VSS-P10
J4
ABI#
VSS-T5 VSS-T10
SAM_K4G10325FE_HC04_FBGA_170P
P1V5S_DGPU
SAM_K4G10325FE_HC04_FBGA_170P
P1V5S_DGPU 2
R55221
2
R55231
2
5.49K_1%_2
C55091
2
1UF_6.3V_2
1UF_6.3V_2_DY 2.37K_1%_2
74
2
5.49K_1%_2
C55051
2
1UF_6.3V_2
1UF_6.3V_2_DY 2.37K_1%_2
B ADBIA1#
IN
74
C5512 1 2
1UF_6.3V_2
C5513 1 2
1UF_6.3V_2
2
1UF_6.3V_2
C5514 1
1 2
2.2UF_6.3V_2
C5515
1 2
1
2.2UF_6.3V_2
C5516
C5517 2
2.2UF_6.3V_2
C5518 1 2
0.1UF_16V_2
C5519 1 2
0.1UF_16V_2
C5520 1 2
0.1UF_16V_2
C5521 1 2
0.1UF_16V_2
C5522 1 2
0.1UF_16V_2
C5523 1 2
C5524 1 2
1UF_6.3V_2
C5525 1 2
1UF_6.3V_2
C5526 1 2
1UF_6.3V_2
1 2
2.2UF_6.3V_2
C5529
1 2
2.2UF_6.3V_2
C5528
1 2
2.2UF_6.3V_2
C5527
C5530 1 2
0.1UF_16V_2
C5531 1 2
0.1UF_16V_2
C5532 1 2
0.1UF_16V_2
C5533 1 2
0.1UF_16V_2
C5534 1 2
2
R55151
P1V5S_DGPU
0.1UF_16V_2
C5535 1 2
10UF_6.3V_3
2
R55161
ADBIA0#
IN
P1V5S_DGPU
A
C55041
10UF_6.3V_3
B
C55081
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION VRAM1 & VRAM2
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
79
1
X01 of
80
7
6
5
75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
F
P1V5S_DGPU
260.4_1%_2 260.4_1%_2
VDDQ-B14
DQ27|DQ3
VDDQ-D1
DQ26|DQ2
VDDQ-D3
DQ25|DQ1
VDDQ-D12
DQ24|DQ0
VDDQ-D14
DQ23|DQ15
VDDQ-E5
DQ22|DQ14
VDDQ-E10
DQ21|DQ13
VDDQ-F1 VDDQ-F3
DQ20|DQ12 DQ19|DQ11
VDDQ-F12
DQ18|DQ10
VDDQ-F14
DQ17|DQ9
VDDQ-G2
DQ16|DQ8
VDDQ-G13
DQ15|DQ23
VDDQ-H3
DQ14|DQ22
VDDQ-H12
DQ13|DQ21
VDDQ-K3
DQ12|DQ20
VDDQ-K12
DQ11|DQ19
VDDQ-L2
DQ10|DQ18
VDDQ-L13
DQ9|DQ17
VDDQ-M1
DQ8|DQ16
VDDQ-M3
DQ7|DQ31
VDDQ-M12
DQ6|DQ30
VDDQ-M14
DQ5|DQ29
VDDQ-N5
DQ4|DQ28
VDDQ-N10
DQ3|DQ27
VDDQ-P1
DQ2|DQ26
VDDQ-P3
DQ1|DQ25
VDDQ-P12
DQ0|DQ24
VDDQ-P14 VDDQ-T1 VDDQ-T3 VDDQ-T12 VDDQ-T14
E
75 75 75 75 75 75 75 75 75
MAB0(8) MAB0(0) MAB0(1) MAB0(3) MAB0(2) MAB0(5) MAB0(4) MAB0(6) MAB0(7)
BI BI BI BI BI BI BI BI BI
J5 K4 K5 K10 K11 H10 H11 H5 H4
A7/A8|A0/A10
VDD-C5
A6/A11|A1/A9
VDD-C10
A5/BA1|A3/BA3
VDD-D11
A4/BA2|A2/BA0
VDD-G1
A3/BA3|A5/BA1
VDD-G4
A2/BA0|A4/BA2
VDD-G11
A1/A9|A6/A11
VDD-G14
A0/A10|A7/A8
VDD-L1 VDD-L4
75 75
IN IN
D4 WCKB0_1 WCKB0_1# D5
WCK01|WCK23
75 75
IN IN
P4 WCKB0_0 WCKB0_0# P5
WCK23|WCK01
VDD-P11 VDD-R5
WCK01#|WCK23#
VDD-R10
R2 R13 C13 C2
75 75 75 75
BI BI BI BI
DBIB0_1 DBIB0_0 DBIB0_2 DBIB0_3
P2 P13 D13 D2
EDC3|EDC0
VSSQ-A3
EDC2|EDC1
VSSQ-A12
EDC1|EDC2
VSSQ-A14
EDC0|EDC3
VSSQ-C1
DBI3#|DBI0#
VSSQ-C4
DBI2#|DBI1#
VSSQ-C11
DBI1#|DBI2#
VSSQ-C12
DBI0#|DBI3#
VSSQ-C14 VSSQ-E1 VSSQ-E3 VSSQ-E12
75 75
IN IN
CASB0# RASB0#
G3 L3
75 75 75
IN BI BI
CKEB0 CLKB0# CLKB0
J3 J11 J12
RAS#|CAS#
VSSQ-E14
CAS#|RAS#
VSSQ-F5 VSSQ-F10 VSSQ-H2
80 80
CKE#
VSSQ-H13
CK#
VSSQ-K2
CK
VSSQ-K13 VSSQ-M5 VSSQ-M10
75 75
WEB0# CSB0#
G12 L12
120_1%_2 1K_5%_2
J13 J10
IN IN
CS#|WE#
VSSQ-N1 VSSQ-N3
WE#|CS#
VSSQ-N12 VSSQ-N14
1 1
R5537 R5504
2 2
VSSQ-R1
ZQ SEN
VSSQ-R3 VSSQ-R4 VSSQ-R11
80
79
75
VM_RST#
IN
P1V5S_DGPU
J2 J1
RESET#
VSSQ-R12
MF
VSSQ-R14 VSSQ-V1
VSSQ-V14
VSS-D10 VSS-G5 VSS-G10
P1V5S_DGPU
VSS-H1 VSS-H14
R55411
2
5.49K_1%_2
C55451
2
1UF_6.3V_2
VSS-K14
VREFC
VSS-L5 VSS-L10 VSS-P10
J4
ABI#
VSS-T5 VSS-T10
2 2
5.49K_1%_2
C55471
2
1UF_6.3V_2
VDDQ-G13
DQ15|DQ23
VDDQ-H3
DQ14|DQ22
VDDQ-H12
DQ13|DQ21
VDDQ-K3
DQ12|DQ20
VDDQ-K12
DQ11|DQ19
VDDQ-L2
DQ10|DQ18
VDDQ-L13
DQ9|DQ17
VDDQ-M1
DQ8|DQ16
VDDQ-M3
DQ7|DQ31
VDDQ-M12
DQ6|DQ30
VDDQ-M14
DQ5|DQ29
VDDQ-N5
DQ4|DQ28
VDDQ-N10
DQ3|DQ27
VDDQ-P1
DQ2|DQ26
VDDQ-P3
DQ1|DQ25
VDDQ-P12
DQ0|DQ24
VDDQ-P14
E
RFU/A12/NC A7/A8|A0/A10
C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10
VDD-C5
A6/A11|A1/A9
VDD-C10
A5/BA1|A3/BA3
VDD-D11
A4/BA2|A2/BA0
VDD-G1
A3/BA3|A5/BA1
VDD-G4
A2/BA0|A4/BA2
VDD-G11
A1/A9|A6/A11
VDD-G14
A0/A10|A7/A8
WCK23|WCK01
75 75 75 75
OUT OUT OUT OUT
R2 R13 C13 C2
75 75 75 75
BI BI BI BI
DBIB1_3 DBIB1_2 DBIB1_0 DBIB1_1
P2 P13 D13 D2
VDD-L1
VDD-P11 VDD-R5
WCK01#|WCK23#
WCK23#|WCK01#
EDC3|EDC0
A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 V1 V3 V12 V14
VSSQ-A3
EDC2|EDC1
VSSQ-A12
EDC1|EDC2
VSSQ-A14
EDC0|EDC3
VSSQ-C1
DBI3#|DBI0#
VSSQ-C4
DBI2#|DBI1#
VSSQ-C11
DBI1#|DBI2#
VSSQ-C12
DBI0#|DBI3#
VSSQ-C14
RAS#|CAS#
VSSQ-E14
CAS#|RAS#
VSSQ-F5
VSSQ-E3
75 75
IN IN
RASB1# CASB1#
G3 L3
75 75 75
IN BI BI
CKEB1 CLKB1# CLKB1
J3 J11 J12
IN IN
CSB1# WEB1#
G12 L12
VSSQ-F10 VSSQ-H2
80 80
CKE#
VSSQ-H13
CK#
VSSQ-K2
CK
VSSQ-K13 VSSQ-M5 VSSQ-M10
75 75
CS#|WE#
VSSQ-N1 VSSQ-N3
WE#|CS#
VSSQ-N12 VSSQ-N14
R5528 R5506
1 1
2 2
J13 J10
120_1%_2 1K_5%_2
VSSQ-R1
ZQ SEN
VSSQ-R3 VSSQ-R4 VSSQ-R11
P1V5S_DGPU
80
C55361
2
R55301
2
R55291
2
C55371
2
79
75
IN
VM_RST#
J2 J1 2 1K_5%_2
1 R5507
RESET#
VSSQ-R12
MF
VSSQ-R14 VSSQ-V1
1UF_6.3V_2_DY 2.37K_1%_2
VSSQ-V3 VSSQ-V12 VSSQ-V14
5.49K_1%_2
A5 V5
1UF_6.3V_2
C
Vpp,NC1
B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10
VSS-B5 VREFD1
VSS-B10
VREFD2
VSS-D10 VSS-G5 VSS-G10
P1V5S_DGPU
VSS-H1 VSS-H14 VSS-K1
2
R55311
2
R55321
2
5.49K_1%_2
C55391
2
1UF_6.3V_2
J14
1UF_6.3V_2_DY 2.37K_1%_2
D
Vpp,NC
A10 V10
C55381
F
VSS-K14
VREFC
VSS-L5 VSS-L10 VSS-P10
J4
ABI#
VSS-T5 VSS-T10
SAM_K4G10325FE_HC04_FBGA_170P
P1V5S_DGPU C55401
2
R55341
2
R55331
2
5.49K_1%_2
C55411
2
1UF_6.3V_2
MF = 1 FOR MIRROR
1UF_6.3V_2_DY 2.37K_1%_2
75
B ADBIB1#
IN
C5548 1 2
1UF_6.3V_2
C5549 1 2
1UF_6.3V_2
2
1UF_6.3V_2
1
C5550 1
C5551 2
2.2UF_6.3V_2
1 2
2.2UF_6.3V_2
C5559 1 2
C5560 1 2
1UF_6.3V_2
C5561 1 2
1UF_6.3V_2
C5562 1 2
1UF_6.3V_2
1 C5563 2
2.2UF_6.3V_2
1 C5564 2
2.2UF_6.3V_2
2.2UF_6.3V_2
C5566 1 2
0.1UF_16V_2 C5565 2 1
C5567 1 2
0.1UF_16V_2
C5568 1 2
0.1UF_16V_2
C5569 1 2
0.1UF_16V_2
C5570 1 2
1
P1V5S_DGPU
0.1UF_16V_2
C5571 1 2
VDDQ-G2
DQ16|DQ8
VSSQ-E1
P1V5S_DGPU
10UF_6.3V_3
VDDQ-F14
DQ17|DQ9
VSSQ-E12
ADBIB0#
IN
VDDQ-F12
DQ18|DQ10
VSSQ-C3
1UF_6.3V_2_DY 2.37K_1%_2
75
VDDQ-F3
DQ19|DQ11
J5 K4 K5 K10 K11 H10 H11 H5 H4
C5552
B
2
R55431
VDDQ-F1
DQ20|DQ12
VDD-R10
SAM_K4G10325FE_HC04_FBGA_170P
R55421
DQ21|DQ13
VSSQ-A1
P1V5S_DGPU C55461
VDDQ-E10
EDCB1_3 EDCB1_2 EDCB1_0 EDCB1_1
2
2
VDDQ-E5
DQ22|DQ14
WCKB1_1 P4 WCKB1_1# P5
2.2UF_6.3V_2
R55381
VSS-K1
J14
1UF_6.3V_2_DY 2.37K_1%_2
VDDQ-D12 VDDQ-D14
DQ23|DQ15
IN IN
75 75
C5554 1
2
VDDQ-D3
DQ25|DQ1 DQ24|DQ0
IN IN
C5553
C55421
VDDQ-D1
DQ26|DQ2
VDD-L4
B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10
VSS-B5 VSS-B10
VREFD2
VDDQ-B14
VDD-L14
Vpp,NC
VREFD1
VDDQ-B12
DQ28|DQ4 DQ27|DQ3
Vpp,NC1
A10 V10
VDDQ-B3
DQ29|DQ5
VDD-L11
2
C
B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14
VDDQ-B1
DQ30|DQ6
WCK01|WCK23
0.1UF_16V_2
1UF_6.3V_2
VSSQ-V12
A5 V5
DQ31|DQ7
WCKB1_0 D4 WCKB1_0# D5
75 75
C5555 1
5.49K_1%_2
2
VSSQ-V3
1K_5%_2
BI BI BI BI BI BI BI BI BI
2
2
C55441
2
MAB1(8) MAB1(7) MAB1(6) MAB1(5) MAB1(4) MAB1(3) MAB1(2) MAB1(1) MAB1(0)
0.1UF_16V_2
2.37K_1%_2
R55401
1 R5505
1UF_6.3V_2_DY
75 75 75 75 75 75 75 75 75
C5556 1
2
M2 M4 N2 N4 T2 T4 V2 V4 M13 M11 N13 N11 T13 T11 V13 V11 F13 F11 E13 E11 B13 B11 A13 A11 F2 F4 E2 E4 B2 B4 A2 A4
VDDQ-T14
2
2
R55391
260.4_1%_2 260.4_1%_2
R5527 1 R5526 1
0.1UF_16V_2
C55431
CLKB1 CLKB1#
C5557 1
P1V5S_DGPU
DQB1(27) DQB1(30) DQB1(25) DQB1(29) DQB1(26) DQB1(31) DQB1(24) DQB1(28) DQB1(22) DQB1(23) DQB1(20) DQB1(21) DQB1(18) DQB1(17) DQB1(19) DQB1(16) DQB1(4) DQB1(0) DQB1(7) DQB1(2) DQB1(6) DQB1(3) DQB1(5) DQB1(1) DQB1(10) DQB1(15) DQB1(9) DQB1(14) DQB1(8) DQB1(12) DQB1(11) DQB1(13)
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
VDDQ-T3
IN IN
A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 V1 V3 V12 V14
VSSQ-C3
D
1 P1V5S_DGPU
VDDQ-T1
75 75
WCK23#|WCK01# VSSQ-A1
EDCB0_1 EDCB0_0 EDCB0_2 EDCB0_3
2
VDDQ-T12
80 80
C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10
VDD-L14
OUT OUT OUT OUT
P1V5S_DGPU
RFU/A12/NC
VDD-L11
75 75 75 75
75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
CHANNEL B MEMORY
2
R5536 1
VDDQ-B3 VDDQ-B12
DQ28|DQ4
0.1UF_16V_2
R5535 1
B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14
VDDQ-B1
DQ30|DQ6 DQ29|DQ5
C5558 1
CLKB0 CLKB0#
IN IN
DQ31|DQ7
2
75 75
M2 M4 N2 N4 T2 T4 V2 V4 M13 M11 N13 N11 T13 T11 V13 V11 F13 F11 E13 E11 B13 B11 A13 A11 F2 F4 E2 E4 B2 B4 A2 A4
3
P1V5S_DGPU
0.1UF_16V_2
80 80
DQB0(14) DQB0(9) DQB0(15) DQB0(8) DQB0(11) DQB0(10) DQB0(13) DQB0(12) DQB0(1) DQB0(6) DQB0(0) DQB0(7) DQB0(2) DQB0(5) DQB0(3) DQB0(4) DQB0(16) DQB0(18) DQB0(17) DQB0(23) DQB0(19) DQB0(21) DQB0(20) DQB0(22) DQB0(26) DQB0(27) DQB0(31) DQB0(24) DQB0(29) DQB0(28) DQB0(30) DQB0(25)
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
4
U5503
U5502
10UF_6.3V_3
8
A
A
INVENTEC TITLE
MODEL,PROJECT,FUNCTION VRAM3 & VRAM4
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0 SHEET
80
1
X01 of
80