Decade Counter
Sample design --Counter VHDL library IEEE; --library definition use IEEE.std_logic_1164.all; use IEEE.std_logic_unsi
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Sample design
--Counter VHDL
library IEEE;
--library definition
use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all;
entity Counter is
--entity definition
port ( clk:in std_logic; reset: in std_logic; q: out std_logic_vector(3 downto 0) ); end Counter;
architecture Counter of Counter is
-- Architecture definition
begin process(clk,reset)
-- Process definition
variable qtemp: std_logic_vector(3 downto 0); -- temporary variable for output q[3..0] begin if reset='1' then qtemp:="0000";
-- Reset asychroniously
else if clk'event and clk='1' then if qtemp