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CHAPTER 5 5.1

(a) R = D'C

D

Q CP

C Q' S = DC

(b) R = (D + C')' =D' C

D

Q C Q' s = (D' + C')' =D C

(c) S = (DC)' =D' + C'

D

Q CP

C Q' R = ((DC)' C)' =DC + C' = (D + C') = (D'C)'

5.2 J

0

2x1 mux

D = JQ' + K'Q Q Y

K

Q

1 s

5.3

D

C

For T – Flip-Flop Q (t + 1) = TQ′ + T′Q = T ⊕ Q

Q′ (t + 1) = [T ⊕ Q]′

= T′Q′ + TQ 5.4

(a)

PN 0 0 1

Q(t + 1) 0 Q(t) 1 0 0 1

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

121

1 1 Q′(t)

(b)

Q(t + 1) = PN′ + PQ(t)′ + N′Q(t) (c) Q(t) 0 0 1 1

Q(t + 1) 0 1 0 1

P 0 1 -

N 1 0

(d)

5.5

State table is also called as transition table. The truth table describes a combinational circuit. The state table describes a sequential circuit. The characteristic table describes the operation of a flip-flop. The excitation table gives the values of flip-flop inputs for a given state transition. The four equations correspond to the algebraic expression of the four tables.

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

122

5.6 x y

xy' + xA

A, z D

Q

D

Q

C

B

CP

(b)

(c)

A(t+1) = xy' + xB B(t+1) = xA + xB' z=A

00, 01

x y 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1

Output

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

Next state

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Inputs

Present state

00, 01

A 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1

z 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1

00 0

01 0

11

00, 01

10,11

10 00, 01

10 1

11 1 10, 11 10, 11

5.7

State Table: Q(t) x y Q(t + 1) Diff. 0 0 0 0

State Diagram: 0

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

123

0 0 0 1 1 1 1

0 1 1 0 0 1 1

1 0 1 0 1 0 1

1 0 0 1 1 0 1

1 1 0 1 0 0 1

Diff. = Q(t)′(x ⊕ y) + Q(t)(x ⊕ y)′

= Q(t) ⊕ x ⊕ y

A counter with a repeated sequence of 00, 01, 10. Present state Next state

5.8

A B A B

FF Inputs T A TB

0 0 1 1

0 1 1 1

0 1 0 1

0 1 0 0

0 0 0 0

00

01

11

10

1 1 0 1

TA = A + B TB = A' + B Repeated sequence: 01 10 00

5.9

(a)

A(t)

B(t)

x

A(t + 1)

B(t + 1)

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

124

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 0 1 1 1 0 0

1 0 0 0 1 0 1 1

A(t + 1):

A(t + 1) = A′x + AB′ B(t + 1):

B(t + 1) = B′x′ + AB (b)

5.10

(a)

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

125

(b) State Table: A(t) B(t) x 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1

y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

A(t + 1) 0 1 1 0 0 1 1 0 0 0 1 0 0 1 1 1 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0

B(t + 1) 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0

z 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0

(c) A(t + 1): Σ(0, 2, 6, 7, 8, 12, 14)

= A x′y′ + Bxy′ + A′Bx + A′B′y′ B(t + 1): Σ(2, 3, 4, 5, 7)

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

126

= A′Bx′ + Axy + A′B′x

5.11

(a)

00 → a, 01 → b, 10 → c, 11 → d State Input Output (b) Present A(t) 0 0 0 0 1 1 1 1

a b d a b d c a d 1 1 0 1 1 1 0 0 1 0 0 1 0 0 0 1 0 0 State Input Next B(t) x A(t + 1) 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1

State Output B(t + 1) z 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0

0 0 1 0 1 0 1 0

OR Present 00 01 01 10

x=0 00 00 00 00

Next x=1 01 01 10 10

O/p x=0 0 1 1 1

x=1 0 0 0 0

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

127

(c) Present State Input A(t) B(t) x 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 JA = A

Next State A(t + 1) B(t + 1) 0 0 1 0 0 0 1 0 0 1 0 1 -

z JA

0 1 0 -

KA JB 0 0 0 0 1 0 1 0 0 - - - - -

KB 0 1 -

1 -

-

0 -

KA = 1

JB =

=x KB:

KB = x′ z:

= Bx′

5.12

Present state a

Next state 0 1 f b

Output 0 1 0 0

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

128

b D F G

5.13

(a)

d a g a f b g d

State Input Output

0 1 1 0

0 0 1 1

a f a f a f g b g b a 0 1 0 1 0 0 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0

(b) State a b a b a b g b g b a Input 0 1 0 1 0 0 1 0 1 1 1 Output 0 0 0 0 0 1 0 1 0 0 0 5.14

State a b c d e

Assignment3 00001 00010 00100 01000 10000

Present State ABCDE x=0 a 0 00 01 b 0 00 10 c 0 01 00 d 0 10 00 e 1 00 00

Next State Output x=1 x=0 x=1 00001 00010 0 00100 01000 0 00001 01000 0 10000 01000 0 00001 01000 0

0 0 0 1 1

5.15

Present State (Q) Input (T) 0 0 0 1 1 0 1 1

Next State (Q) 0 1 1 0

Q(t + 1) = T ⊕ Q(t)

5.16

(a)

DA = Ax′ + Bx DB = A′x + Bx′

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

129

Present state A B 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

Input x 0 1 0 1 0 1 0 1

0 0 0 1 1 0 1 1

0 1 1 1 0 0 1 0

B

Bx

Next state A B

A

00 m0

01 m1

11

0

m2

1 m4

A

10

m3

1

m5

m7

1

m6

1

1

x

DA = Ax' + Bx B

Bx A

00 m0

01 m1

0

11

1 m4

10

m3

m5

m2

1

1

m7

m6

1

A

1 x

DB = A'x + Bx' (b)

DA = A'x + Ax' DB = AB + Bx'

Present state A B 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

Input x 0 1 0 1 0 1 0 1

0 1 0 1 1 0 1 0

0 1 1 0 0 0 1 1

B

Bx

Next state A B

A

00 m0

01 m1

0

1 m4

A

11

1

10

m3

m5

m2

1 m7

m6

1

1 x

DA = A'x + Ax' B

Bx A

00

01

m0

m1

m4

m5

0 A

11

10

m3

m2

m7

m6

1

1

1

1

1

x

DB = AB + Bx' 5.17

The output is 0 for all 0 inputs until the first 1 occurs, at which time the output is 1. Thereafter, the output is the complement of the input. The state diagram has two states. In state 0: output = input; in state 1: output = input'.

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

130

D

x

Q

y

Present state

Input

Next state

Output

clk

A 0 0 1 1

x 0 1 0 1

A 0 1 1 1

y 0 1 1 0

reset_b

0/0

0/1 1/0

reset_b

0

1 1/1

DA = A + x y = Ax' + A'x

5.18

Binary up-down counter with enable E.

Present Next state Input state AB x AB 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11

01 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11

00 00 11 01 01 01 01 10 10 10 01 11 11 11 11 11

Flip-flop inputs JA KA JB KB 0 x 0 x 1 x 0 x 0 x 0 x 0 x 1 x x 0 x 0 x 1 x 0 x 0 x 0 1 0 x1

0 0 1 1 x x x x 1 1 x x x x x x

x x x x 0 0 1 1 0 0 1 1 0 0 1 1

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131

E

Ex AB

00 m0

01 m1

Cx

11

10

m3

m0

1 m4

m5

m7

01

00

m6

m12

m13

x m8

10

m9

x

m14

x

B

m10

x

A

00 m0

01 m1

11 m3

00 m4

m5

x m12

A

m13

x

11 m8

m15

x m9

x m11

1

10

AB

m9

m14

B

m11

m10

1

E 00 m0

1

00

x

01

m14

E

x

11 m3

x m5

m7

m13

A

1

m15

1 m8

10

m9

x

m11

x

x m6

1 m12

10 m2

x

11

x m10

01 m1

m4

x JB = E

5.19

m15

Ex 10

m6

x

m13

m6

x 1

m8

m2

m7

x

m7

x

x KA = (Bx + B'x')E

1

01

x

10

E

Ex

m2

x

11

x

10

m3

m5

x JA = (Bx + B'x')E

AB

11

x

x m12

x

m11

x

x

01

m15

x

01 m1

m4

1

11

C 00

m2

00

A

AB

x

1 m14

E

1 m10

x

x KB = E

(a) Unused states (see Fig. P5.19): 101, 110, 111.

Present Next Input Output state state y ABC x ABC 000 0 011 0 000 1 100 1 001 0 001 0 001 1 100 1 010 0 010 0 010 1 000 1 011 0 001 0 011 1 010 1 0 100 010 0 1 100 011 1 d(A, B, C, x) = Σ (10, 11, 12, 13, 14, 15)

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

132

C

Cx AB

00 m0

01 m1

00

10

m3

1 m4

m5

Cx

11

AB

m2

m0

1

00

m7

m6

01 m12

11

m13

x m8

m15

x m9

m14

x m11

10

B

m10

x

11 A

x

m0

00

01 m1

10

m5

m7

m12

A

m8

10

m13

x

x m9

m15

1

m15

x m9

m14

x m11

1

B

x m10

x

x

C m0

1

00

1

01 B

m10

x

m3

m5

m7

m13

x m8

m15

x m9

m6

1 x m11

10

x

x

x DC = Cx'+ Ax +A'B'x'

10 m2

1

1 m12

A

11

1

11

x

01 m1

m4

m14

x m11

m6

1

1

00

m6

01 11

AB

m2

1 m4

m7

Cx

11 m3

m5

10 m2

x DB = A + C'x' + BCx C

00

m3

m13

m8

10

DA = A'B'x Cx

m1

x

x

AB

11

1 m12

x

01

1 m4

01

A

C 00

m14

B

x m10

x

x y = A'x

The machine is self-correcting, i.e., the unused states transition to known states. 111

101 0/0 1/0

110

0/0 1/0

0/0 1/0

011

010

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

133

(b) With JK flip=flops, the state table is the same as in (a).

Flip-flop inputs JA KA JB KB JC KC 0 1 0 1 0 0 0 0 x x

5.20

x x x x x x x x 1 1

1 0 0 0 x x x x 1 1

x x x x 0 1 1 0 x x

1 0 x x 0 0 x x 0 1

x x 0 1 x x 0 1 x x

JA = B'x KA = 1 JB = A + C'x' KB = C' x+ Cx' JC = Ax + A'B'x' KC = x y = A'x The machine is self-correcting because KA = 1.

DA = (A ⊕ B) + Bx

DB = (x ⊕ A ⊕ B)

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

134

Present State A(t) B(t) 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

DA

Input Next State x A(t + 1) B(t + 1) 0 0 1 0 0 1 1 1 0 1 1 1 0 0 1 1

DA 1 0 1 0 1 0 0 1

DB 0 0 1 1 1 1 0 1

1 0 1 0 1 0 0 1

= Σ(2, 3, 4, 5, 7) = AB′ + Bx + A′B

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

135

= (A ⊕ B) + Bx

DB = Σ(0, 2, 4, 7) = B′x′ + A′x′ + ABx =x⊕A⊕B

5.21

The statements associated with an initial keyword execute once, in sequence, with the activity expiring after the last statment competes execution; the statements assocated with the always keyword execute repeatedly, subject to timing control (e.g, #10).

5.22

(a)

(b) t 0

20

40

60

80

100

120

140

160

5.23

(a) RegA = 125, RegB = 125 (b) RegA = 125, RegB = 50 Note: Text has error, with RegB = 30 at page 526).

5.24

(a) module DFF (output reg Q, input D, clk, preset, clear); always @ (posedge clk, negedge preset, negedge clear ) if (preset == 0) Q