Acer Aspire 4253 (Quanta ZQG).pdf
1 2 3 4 PCB STACK UP 5 7 8 ZQG SYSTEM DIAGRAM LAYER 1 : TOP LAYER 2 : GND DDR3- SODIMM2 LAYER 3 : IN1 DDR3-
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1
2
3
4
PCB STACK UP
5
7
8
ZQG SYSTEM DIAGRAM
LAYER 1 : TOP LAYER 2 : GND
DDR3- SODIMM2
LAYER 3 : IN1
DDR3- SODIMM1
PAGE 7
LAYER 4 : IN2
DDR3 Channel A
PAGE 6
LAYER 5 : VCC A
6
LAYER 6 : BOT
PWM FAN SCH.
CPU (PROCHOT) E.C. (CPUFAN#)
IV@ -----> iGPU / PWW control SW@ -----> Switchable iGPU & dGPU SWS@ -----> VRAM / Strap / BACO option SP@ -----> Board ID / VBIOS option / CPU
32.768KHz
Zacate
CPU THERMAL SENSOR
TDP~18W
LVDS
HDMI
PAGE 21
CRT
PAGE 20
LVDS
PAGE 20
CRT LVDS
PAGE 3,4,5
ATI Seymour XT 128-bit M2 Pkg 29mm X 29mm PAGE 13~17
PCI-Express 4X
HT3 1.8GHz
A
DIG
UMA/Muxless
PAGE 4
CPU SideBand TemperatureSense I2C
HDMI
CRT
19mmX19mm 413pin BGA
(Reserve Only)
PAGE 30
25MHz
HDMI
AMD Brazos
800MHz DDR3 VRAM 64MX16X4,64 bit 64MX16X8,128 bit PAGE 19
VGA AMD Seymour XT PCI-Expresss B
P0
LAN Atheros AR8151L rev.B
Mini PCI-E Card
Hudson-M1
(Wireless LAN)
23mmX23mm, 605pin BGA
PAGE 23
(10/100/1000)
B
AMD
P2
TDP~4.7W
PAGE 22
25MHz
RJ45 PAGE 22
CHARGER (ISL88731A)
P13
Blue Tooth
Web-Camera
on board x1
3 Gb/s
PAGE 24
PAGE 32
USB2.0 Port
SATA0 150MB
SATA - HDD C
P9
C
PAGE 28
PAGE 28
PAGE 20
P4
AMD CPU CORE (ISL6265) PAGE 34
PAGE 8,9,10,11,12
3 Gb/s
PAGE 24
PCLK_DEBUG
LPC
NB_CORE (UP6111AQDD) PAGE 36
NB
CLK_PCI_775
CPU SideBand TemperatureSense I2C
0.9V/DDR 1.5V(RT8207)
USB BOARD
P10
USB2.0 Ports x3
SATA1 150MB
SATA - ODD CPU
FFC
P0
CardReader
WLAN & Debug
AU6437
Azalia
PAGE 23
Winbond KBC
Audio CODEC
NPCE791L
Conexant 20584
PAGE 37
Mini Card
PAGE 31
PAGE 28
PAGE 25
12MHz
PAGE 26
SYSTEM 5V/3V (RT8206) PAGE 33 D
D
Keyboard TouchPad
1.1V(UP6111AQDD) PAGE 35
SPI ROM
INT MIC
AUDIO CONN
Speaker CN
(H.P./ MIC)
PAGE 30
PAGE 31
PAGE 26
PAGE 27
PAGE 27
Quanta Computer Inc.
Discharge /Thermal protec
PROJECT : ZQG Size
PAGE 40
Rev 1A
Block Diagram Date:
1
Document Number
2
3
4
5
6
Monday, November 01, 2010 7
Sheet
1 8
of
41
5
4
INDEX
3
2
1
02
Power Sequence
PAGE#
DESCRIPTION
NOTE AC IN
1
BLOCK DIAGRAM
2
SYSTEM INFORMATION
3
ONTARIO MEM & PCIE I/F(1/3)
Hudson M1 SM BUS 3V/5VPCU
4
ONTATIO DISPLAY/CLK/MI(2/3)
5
ONTARIO POWER & DECOUP(3/3)
6
DDR3 SO-DIMM (RVS)
7
DDR3 SO-DIMM (STD)
8
HUDSON PCIE/LPC/CPU IF(1/5)
9
HUDSON ACPI/GPIO/USB(2/5)
10
HUDSON SATA/BIDs(3/5)
11
HUDSON PWR/GND(4/5)
12
HUDSON STRAPS/PWRGD(5/5)
13
Seymour - PCIE
14
Seymour - HOST
15
Seymour - MEM
16
Seymour - PWR/GND
SB820 SMBUS
Pin NO.
PCLK_SMB
AD22
PDAT_SMB
AE22
SMBUS Function Define
NBSWON#
D
DNBSWON#
D
DDR / RFID
(+3V) S5_ON/S5 RSMRST#
SB_SMBCLK1
F5
SB_SMBDATA1
F4
not used
(+3V_S5)
PCIE_WAKE#
SB_SCLK2
D25
SB_SDATA2
F23
not used
(+3V_S5)
SUSC SUSB
SB_SCLK3
B26
SB_SDATA3
E26
not used
(+3V_S5) SUSON MAINON
SB_SCLK3
B26
SB_SDATA3
E26
not used
(+3V_S5)
VR_ON
C
B
A
C
17
Seymour - DP_PWR/GND ( BACO)
18
VRAM strap
19
VRAM channel B
20
CRT/LVDS/LID
21
HDMI
22
LAN AR8151
23
MINI PCI-E
CPU_CORE
KBC(EC) SM BUS VRM_PWRGD KBC SMBUS
Pin NO.
MBCLK
110
MBDATA
111
SMBUS Function Define
HWPG ECPWROK
Battery
(+3VPCU) SB_PWRGD_IN CPU RESET
24
HDD /ODD
25
CARD READER
26
AUDIO - CONEXANT 20584
27
AUDIO JACK CONN
28
USB / BT /TP
MBCLK_THRM
115
MBDATA_THRM
116
Thermal
(+3VPCU)
CPU POWER OK
B
29
LED / NUT
30
KB/FAN/TP
31
WPCE791 /FLASH
32
CHARGER ( ISL88731)
33
SYSTEM 5V/3V (RT8206)
34
CPU CORE ( OZ8380)
35
VCCP 1.1V ( UP6111A)
36
+1V(G5602)
37
DDR 1.5V (TPS51116)
38
GPU CORE (MAX8792)
39
+1.8V/+1.5_GPU/+1.8V_GPU
40
Discharge/Thermal Protection
A
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
Rev 1A
System Information Date: 5
4
3
2
Monday, November 01, 2010
Sheet 1
2
of
41
2
3
4
5
6
M_A_DQ[0..63] 6,7
6,7 M_A_BS[2..0]
M_ADD0 M_ADD1
M_DATA0
ONTARIO (2.0)
M_DATA1
PART 1 OF 5
M_ADD2
M_DATA2
M_ADD3
M_DATA3
M_ADD4
M_DATA4
M_ADD5
M_DATA5
M_ADD6
M_DATA6
M_ADD7
M_DATA7
6,7 M_A_DM[7..0]
M_ADD9
M_DATA8
M_ADD10
M_DATA9
M_ADD11
M_DATA10
M_ADD12
M_DATA11
M_ADD13
M_DATA12
M_ADD14
M_DATA13
M_ADD15
M_DATA14
M_BANK1
M_DATA16
M_BANK2
M_DATA17
M_DM0
M_DATA19
M_DM1
M_DATA20
M_DM2
M_DATA21
M_DM3
M_DATA22
M_DM4
M_DATA23
M_DM6
M_DATA24
M_DM7
M_DATA25
M_A_DQSP0 M_A_DQSN0 M_A_DQSP1 M_A_DQSN1 M_A_DQSP2 M_A_DQSN2 M_A_DQSP3 M_A_DQSN3 M_A_DQSP4 M_A_DQSN4 M_A_DQSP5 M_A_DQSN5 M_A_DQSP6 M_A_DQSN6 M_A_DQSP7 M_A_DQSN7
A16 B16 B20 A20 E23 E22 J22 J23 R22 P22 W22 V22 AC20 AC21 AB16 AC16
M_A_CLKP0 M_A_CLKN0 M_A_CLKP1 M_A_CLKN1 M_A_CLKP2 M_A_CLKN2 M_A_CLKP3 M_A_CLKN3
M17 M16 M19 M18 N18 N19 L18 L17
M_CLK_H0
M_DATA42
M_CLK_L0
M_DATA43
M_CLK_H1
M_DATA44
M_CLK_L1
M_DATA45
M_CLK_H2
M_DATA46
M_CLK_L2
M_DATA47
L23 N17
M_RESET_L
M_DATA50
M_EVENT_L
M_DATA51
M_CKE0
M_DATA54
M_CKE1
M_DATA55
M_DQS_H0
M_DATA27
M_DQS_L0
M_DATA28
M_DQS_H1
M_DATA29
M_DQS_L1
M_DATA30
M_DQS_H2
M_DATA31
M_DQS_L2 M_DQS_H3 M_DQS_L3 M_DQS_H4 M_DQS_L4 M_DQS_H5 M_DQS_L5
MEMORY I/F
6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7
M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37
M_DQS_H6
M_DATA38
M_DQS_L6
C
M_DATA39
M_DQS_L7
M_DATA40
M_CLK_L3
M_DATA48
M_DATA52 M_DATA53
6,7 6,7
M_A_CKE0 M_A_CKE1
F15 E15
6 6 7 7
M_A_ODT0 M_A_ODT1 M_A_ODT2 M_A_ODT3
W19 V15 U19 W15
M0_ODT0
M_DATA58
M0_ODT1
M_DATA59
M1_ODT0
M_DATA60
M1_ODT1
M_DATA61
6 6 7 7
M_A_CS#0 M_A_CS#1 M_A_CS#2 M_A_CS#3
T17 W16 U17 V16
M0_CS_L0
6,7 6,7 6,7
M_A_RAS# M_A_CAS# M_A_WE#
U18 V19 V17
M_RAS_L
M_DATA56 M_DATA57
M_DATA62
D
M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23
H21 H23 K22 K21 G23 H20 K20 K23
M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31
N23 P21 T20 T23 M20 P20 R23 T22
M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39
V20 V21 Y23 Y22 T21 U23 W23 Y21
M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47
GPU
VDD_10
PEG_RXP0 PEG_RXN0
AA6 Y6
P_GPP_RXP0
PEG_RXP1 PEG_RXN1
AB4 AC4
P_GPP_RXP1 P_GPP_RXN1
P_GPP_TXN1
PEG_RXP2 PEG_RXN2
AA1 AA2
P_GPP_RXP2
P_GPP_TXP2
P_GPP_RXN2
P_GPP_TXN2
PEG_RXP3 PEG_RXN3
Y4 Y3
P_GPP_RXP3
2K/F_4 ON_ZVDD
R375
Y14
P_GPP_TXP0
P_GPP_RXN0
P_GPP_TXN0 ONTARIO (2.0) PART 2 OF 5
P_GPP_TXP1
P_GPP_RXN3
P_GPP_TXP3 P_GPP_TXN3
P_ZVDD_10
P_ZVSS
UMI_RXP0 UMI_RXN0
AA12 Y12
P_UMI_RXP0
P_UMI_TXP0
P_UMI_RXN0
P_UMI_TXN0
UMI_RXP1 UMI_RXN1
AA10 Y10
P_UMI_RXP1
P_UMI_TXP1
P_UMI_RXN1
P_UMI_TXN1
8 8
UMI_RXP2 UMI_RXN2
AB10 AC10
P_UMI_RXP2
8 8
UMI_RXP3 UMI_RXN3
AC7 AB7
P_UMI_RXP3
P_UMI_TXP3
P_UMI_RXN3
P_UMI_TXN3
8 8 8 8
P_UMI_RXN2
P_UMI_TXP2 P_UMI_TXN2
M_DATA63
A
AB6 AC6
PEG_TXP0_C PEG_TXN0_C
C535 C540
[email protected]/10V_4 [email protected]/10V_4
PEG_TXP0 PEG_TXN0
AB3 AC3
PEG_TXP1_C PEG_TXN1_C
C531 C533
[email protected]/10V_4 [email protected]/10V_4
PEG_TXP1 PEG_TXN1
Y1 Y2
PEG_TXP2_C PEG_TXN2_C
C526 C530
[email protected]/10V_4 [email protected]/10V_4
PEG_TXP2 PEG_TXN2
V3 V4
PEG_TXP3_C PEG_TXN3_C
C523 C525
[email protected]/10V_4 [email protected]/10V_4
PEG_TXP3 PEG_TXN3
AA14 ON_ZVSS
R382
1.27K/F_4
AB12 UMI_TXP0_C C574 AC12 UMI_TXN0_C
0.1u/10V_4 C578
0.1u/10V_4
UMI_TXP0 8 UMI_TXN0 8
AC11 UMI_TXP1_C C563 AB11 UMI_TXN1_C
0.1u/10V_4 C568
0.1u/10V_4
UMI_TXP1 8 UMI_TXN1 8
AA8 UMI_TXP2_C C554 UMI_TXN2_C Y8
0.1u/10V_4 C558
0.1u/10V_4
UMI_TXP2 8 UMI_TXN2 8
AB8 UMI_TXP3_C C542 AC8 UMI_TXN3_C
0.1u/10V_4 C548
0.1u/10V_4
UMI_TXP3 8 UMI_TXN3 8
B
SP@FT1_ONTARIO
+M_VREF
+1.5V_SUS
R403 1K/F_4
R410
+1.5V_SUS
R402
+1.5V_SUS
2.2K_4 1K/F_4
M_CLK_H3 M_DATA49
6,7 M_A_RST# 6,7 M_A_EVENT#
C23 D23 F23 F22 C22 D22 F20 F21
This page is different AMD Nile U17A
M_DQS_H7 M_DATA41
6 6 6 6 7 7 7 7
M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15
M_DM5
M_DATA26
B
C18 A19 B21 D20 A18 B18 A21 C20
03
PEG_TXP[3..0] PEG_TXN[3..0] PEG_RXP[3..0] PEG_RXN[3..0]
13 PEG_TXP[3..0] 13 PEG_TXN[3..0] 13 PEG_RXP[3..0] 13 PEG_RXN[3..0]
M_BANK0
M_DATA18
M_A_DM0 D15 M_A_DM1 B19 M_A_DM2 D21 M_A_DM3 H22 M_A_DM4 P23 M_A_DM5 V23 M_A_DM6 AB20 M_A_DM7 AA16
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7
M_ADD8
M_DATA15
M_A_BS0 R18 M_A_BS1 T18 M_A_BS2 F16
B14 A15 A17 D18 A14 C14 C16 D16
PCIE I/F
A
R17 H19 J17 H18 H17 G17 H15 G18 F19 E19 T19 F17 E18 W17 E16 G15
UMI I/F
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
8
+1.5V_SUS 5,6,7,30,37,39 VDD_10 5
U17E
6,7 M_A_A[15:0]
7
2
1
Y20 M_A_DQ48 AB22 M_A_DQ49 AC19 M_A_DQ50 AA18 M_A_DQ51 AA23 M_A_DQ52 AA20 M_A_DQ53 AB19 M_A_DQ54 Y18 M_A_DQ55
M_A_EVENT# R404 1K/F_4
C597
C598
0.1u/10V_4
1000p/50V_4
1
Q32 MMBT3904 R408 3
0_4
C
APU_MEMHOT# 9
0902-- change value from 1uF to 1nF
AC17 M_A_DQ56 Y16 M_A_DQ57 AB14 M_A_DQ58 AC14 M_A_DQ59 AC18 M_A_DQ60 AB18 M_A_DQ61 AB15 M_A_DQ62 AC15 M_A_DQ63
M0_CS_L1 M1_CS_L0 M1_CS_L1
M_VREF
M23
M_ZVDDIO_MEM_S
M22
+M_VREF
M_CAS_L M_WE_L
SP@FT1_ONTARIO
39.2/F_4
R405
+1.5V_SUS
D
?
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
ONTARIO MEM & PCIE I/F(1/3) Date: 1
2
3
4
5
6
Monday, November 01, 2010 7
Sheet
3
of 8
41
Rev 1A
1
+1.8V
+1.8V +3V R70 R69
1K/F_4 1K/F_4
04
5,30,39,40 5,6,7,9,10,11,12,16,17,20,21,23,25,26,29,30,31,33,34,35,36,37,38,39,40
APU_SVC APU_SVD
R301
300_4
LDT_RST#
R326
300_4
APU_PWRGD
U17B
ANALOG/DISPLAY/MISC
INT_CRT_RED INT_CRT_GRE INT_CRT_BLU
R377 R376 R380
150/F_4 150/F_4 150/F_4
R357 R355
21 21
TX0_HDMI+ TX0_HDMI-
0.1u/10V_4
C559
0.1u/10V_4
C569
INT_EDIDCLK INT_EDIDDATA
TXC_HDMI+ TXC_HDMI-
C550
0.1u/10V_4
C555
0.1u/10V_4
C564
A8 B8
TDP1_TXP0
PEG_HDMI_TXDP1 PEG_HDMI_TXDN1
B9 A9
TDP1_TXP1 TDP1_TXN1
PEG_HDMI_TXDP0 D10 PEG_HDMI_TXDN0 C10 PEG_HDMI_TXCP PEG_HDMI_TXCN
DP_ZVSS
H3
DP_BLON
G2 H2 H1
TDP1_TXP2 TDP1_TXN2
A10 B10
TDP1_TXP3
DP_DIGON DP_VARY_BL
INT_HDMI_HPD INT_EDIDCLK 20 INT_EDIDDATA 20
LTDP0_AUXP LTDP0_AUXN
A3 B3
20 INT_TXLOUTP1 20 INT_TXLOUTN1
D6 C6
LTDP0_TXP1
LTDP0_HPD
D3
20 INT_TXLOUTP0 20 INT_TXLOUTN0
A6 B6
LTDP0_TXP2
D8 C8
LTDP0_TXP3 LTDP0_TXN3
DAC_BLUEB DAC_HSYNC
LTDP0_TXN2
INT_TXLCLKP INT_TXLCLKN
8 8
APU_CLKP APU_CLKN
V2 V1
CLKIN_H
8 8
DISP_CLKP DISP_CLKN
D2 D1
DISP_CLKIN_H
J1 J2
APU_SIC APU_SID
P3 P4
DAC_RED DAC_REDB DAC_GREEN DAC_GREENB DAC_BLUE
CLKIN_L
DISP_CLKIN_L
DAC_VSYNC DAC_SCL DAC_SDA
SVC
DAC_ZVSS
SER
SIC SID
TEST5 TEST6 TEST14
R322 R336
8,30 LDT_RST# 8,30 APU_PWRGD
0_4 0_4
LDT_RST#_R APU_PWRGD_R
T3 T4
RESET_L
TEST15
PWROK
TEST16
U1 U2 T2
PROCHOT_L
*0_4
H_PROCHOT# APU_THERMTRIP# APU_ALERT#
TEST17
R324
10 SB_TALERT#
TEST18
CTRL
8,10,31 H_PROCHOT#
THERMTRIP_L
TEST19
ALERT_L
TEST25_H
R60
SB_SCLK3
31
R53
APU_SIC_EC
*0_4
3
N2 N1 P1 P2 M4 M3 M1
APU_SIC
1
Q19
*2N7002K
R59
0_4
0_4
TDI
APU_TDI
TDO
APU_TDO
TEST28_L TEST31
TMS
APU_TMS
TRST_L
APU_TRST#
DBRDY
TEST28_H
TCK
APU_TCK
TEST33_H
JTAG
9
TEST25_L
TEST
2
R71 1K/F_4
DBRDY
TEST33_L TEST34_H
DBREQ_L
TEST34_L TEST35
+3V APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# DBRDY DBREQ#
2
R61 1K/F_4
F4 G1 F3
VDDCR_NB_SENSE
TEST36
VDDCR_CPU_SENSE
TEST37
F1
VSS_SENSE RSVD_1
DMAACTIVE_L
RSVD_2
9
SB_SDATA3
R63
*0_4
31
APU_SID_EC
R54
0_4
3
*100K_4
C12 D13 A12 B12 A13 B13
INT_CRT_RED
E1 E2
INT_CRT_HSYNC INT_CRT_VSYNC
F2 D4
INT_DDCCLK 20 INT_DDCDATA 20
D12 DAC_RSET
R148
*2N7002K
R62
0_4
20
INT_CRT_BLU
20
20 20
499/F_4
APU_THERMDA APU_THERMDC APU_TEST6_DIRECRACKMON APU_BP0_TSTCLK_USCLK0
R1 R2 R6 T5 E4 K4 L1 L2 M2 K1 K2 L5 M5 M21 J18 J19 U15 T15 H4 N5 R5
APU_BP3_SCANSHIFTEND_USDATA1 APU_BP2_SCANSHIFTEN_USDATA0 TEST18 TEST19
R305 R333 R327 R306
T111 T109 T15 T16 T50 T117 T112
1K/F_4 1K/F_4 510/F_4 510/F_4
+1.8V
APU_TEST28_H_PLLCHARZ T110 APU_TEST28_L_PLLCHARZ T17 APU_TEST31_MEM_TEST T154 APU_TEST33_H_M_CLKTST_H C318 0.1u/10V_4 R164 APU_TEST33_H_M_CLKTST_L C310 0.1u/10V_4 R154 APU_TEST34_H_TSTCLKIN_H T65 APU_TEST34_L_TSTCLKIN_L T74 APU_TEST35 R328 *1K/F_4 APU_TEST36 R315 1K_4 +1.8V APU_TEST37_GIO_TSTDTM0_CLKINIT T14
51/F_4 51/F_4
UNNAMED_7_CAP_I337_B
APU_FDO ON_DMAACTIVE#
K3 T1
R335
VSS_SENSE VDDCR_CPU_SENSE
0_4
T113 ALLOW_LDTSTP 8
PART 3 OF 5
R307 1K/F_4
?
APU_SID
1
Q18
20
INT_CRT_GRE
ONTARIO (2.0)
RSVD_3
SP@FT1_ONTARIO R312 R311
0_4 0_4
CPU_VDD0_FB_L CPU_VDD0_FB_H
R325 1K/F_4
A
34 34
+1.8V
+1.8V +1.8V
0831---follow AMD request for HDMI function
+3V
VDDIO_SUS_SENSE
R85
*0_4
VSS_SENSE VDDCR_NB_SENSE
R319 R330
0_4 0_4
CPU_VDDIO_SUS_FB_H CPU_VDDNB_FB_L CPU_VDDNB_FB_H
*10K/F_4 CNTR_VREF
R314
37
34 34
LDT_RST#
R337 10K/F_4
1
R300 *1K/F_4
Q29 *MMBT3904 CPU_LDT_RST_HTPA# 3
Can remove on MP------>LX
2
DIFFERENTIAL ROUTING
R351
33,40 SYS_SHDN#
0_4
Q31 MMST3904-7-F 3
APU_THERMTRIP#
1
VID Override Circuit +1.8V +3V
0906-- modify circuit R88 *300_4
R66 *300_4
R304 *2.2K/F_4
2
R350 *10K/F_4
R331
9 CPU_THERMTRIP#
*0_4
Q30 *MMST3904-7-F 3
APU_SVC
R90
APU_SVD
R68
0_4
APU_PWRGD
R302
*0_4
0_4
1
for normal operation open all switches
CPU_PWRGD_SVID_REG
R89 *220/F_4
R67 *220/F_4
CPU_SVC
34
CPU_SVD
34
CPU_PWRGD_SVID_REG
34
R298 *220/F_4
+3V
R299 10K/F_4
+1.8V
+1.8V
HDT+ Connector
2
R297
0_4
1
R321 *10K/F_4
SML1ALERT#
R296
*0_4
HDT+ HEADER / PLACE ON TOP
R318 1K/F_4
+3V
Q27 *MMST3904-7-F 3
1
+1.8V
APU_ALERT#
H_PROCHOT#
APU_TRST#
+1.8V
+1.8V
CN10
R332 R344 R354 R359
0_4 HDT_TRST# 10K_4 10K_4 10K_4
1 3 5 7 9 11 13 15 17 19
CPU_VDDIO
CPU_TCK
GND
CPU_TMS
GND
CPU_TDI
GND
CPU_TDO
CPU_TRST_L
CPU_PWROK_BUF
CPU_DBRDY3
CPU_RST_L_BUF
CPU_DBRDY2
CPU_DBRDY0
CPU_DBRDY1
CPU_DBREQ_L
GND
CPU_PLLTEST0
CPU_VDDIO
CPU_PLLTEST1
2 4 6 8 10 12 14 16 18 20
APU_TCK
R303 R317 R320
APU_TMS APU_TDI
5
30,31 SML1ALERT#
Q28 MMST3904-7-F 3
1K/F_4 1K/F_4 1K/F_4
C520 0.1u/10V_4
U14
VCC
APU_TDO
LDT_RST#_R
1 1A
1Y 6
LDT_RST#_BUF
R347
1K/F_4
APU_PWRGD_R
3 2A
2Y 4
APU_PWRGD_BUF R348
1K/F_4
APU_PWRGD_BUF LDT_RST#_BUF DBRDY
R366 R338 R316
DBREQ# J108_PLLTST0 J108_PLLTST1
300_4 0_4 0_4
TEST19 TEST18
GND
Quanta Computer Inc.
SN74LVC2G07DCKR
2
0830---add circuit
2
A
DP0_HPD R87
21
VDDIO_MEM_S_SENSE
TEST38
B4 W11 V5
HDMI_DDCCLK 21 HDMI_DDCDATA 21
SVD TEST4
+3V
INT_LVDS_BLON 20 INT_LVDS_DIGON 20 INT_LVDS_PWM 20
C1
LTDP0_TXN0
20 20
0_4 0_4 0_4 10K_4
B2 C2
LTDP0_TXP0
LTDP0_TXN1
R86 R309 R308 R329
TDP1_HPD
B5 A5
APU_SVC APU_SVD
150/F_4
TDP1_AUXN
TDP1_AUXP
TDP1_TXN3
20 INT_TXLOUTP2 20 INT_TXLOUTN2
0901-- change from 2.2k to 2kohm
R310
TDP1_TXN0
DP MISC
C556
21 21
H_PROCHOT#
+3V 2K_1/16W_F_4 2K_1/16W_F_4
0.1u/10V_4
0.1u/10V_4
PEG_HDMI_TXDP2 PEG_HDMI_TXDN2
2
1K/F_4
TX1_HDMI+ TX1_HDMI-
C541
C546
VGA DAC
R323
APU_THERMTRIP# APU_ALERT#
21 21
0.1u/10V_4
DISPLAYPORT 1
1K/F_4 1K/F_4
TX2_HDMI+ TX2_HDMI-
DISPLAYPORT 0
R345 R334
0.1u/10V_4
21 21
CLK
+3V
PROJECT : ZQG
Size
Document Number
ONTATIO DISPLAY/CLK/MI(2/3) Date: 1
Monday, November 01, 2010
Sheet
4
of
41
Rev 1A
1
+1.5V_SUS 3,6,7,30,37,39 +1V 30,36,39 +1.8V 4,30,39,40 +3V 4,6,7,9,10,11,12,16,17,20,21,23,25,26,29,30,31,33,34,35,36,37,38,39,40 +VCORE 30,34 +NBCORE 34 VDD_10 3 +VCORE
+VCORE
U17C
11A 440mil viax22 E5 E6 F5 F7 G6 G8 H5 H7 J6 J8 L7 M6 M8 N7 R8
+NBCORE
VDDCR_CPU_1
VDD_18_1
VDDCR_CPU_2
VDD_18_2
VDDCR_CPU_3
VDD_18_3
VDDCR_CPU_4
VDD_18_4
VDDCR_CPU_5
VDD_18_5
VDDCR_CPU_6
VDD_18_6
VDDCR_CPU_7
VDD_18_7
2A 80mil viax4
VDD_18
U8 W8 U6 U9 W6 T7 V7
1u/6.3V_4
R371
10u/6.3V_8
0.1u/10V_4
C544
C149
0_8
+1.8V
C135
C175
C148 C127
1u/6.3V_4
0.1u/10V_4
1u/6.3V_4
10u/6.3V_8 C501
VDDCR_CPU_9
C170
C498
10u/6.3V_8
C499
C500
C141
C206 10u/6.3V_8
VDDCR_CPU_10
10u/6.3V_8
VDDCR_CPU_11
10u/6.3V_8
10u/6.3V_8
VDDCR_CPU_12
VDDAN_18_DAC
VDDCR_CPU_14
+VCORE
150mA 10mil viax1
VDDCR_CPU_13
L58
+1.8V
VDDCR_CPU_15
VDDCR_NB_1
VDD_18_DAC
W9
C674 10u/6.3V_8
C18
VDDCR_NB_2
C537 10u/6.3V_8
C19
+VCORE
C188 1u/6.3V_4
1u/6.3V_4 C163 1u/6.3V_4
VDDCR_NB_3 VDDCR_NB_4
ONTARIO (2.0)
VDDCR_NB_5
0.1u/10V_4
PART 4 OF 5
0.1u/10V_4
0.1u/10V_4
C138
1u/6.3V_4 C129
C165 1u/6.3V_4
0.1u/10V_4 C167
VDDCR_NB_6 VDDCR_NB_7
C131
+1V
VDDCR_NB_8 VDDCR_NB_9
T49
VDDCR_NB_10
C166
C168
C136
C130
C164
C169
C132 0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
200mA 10mil viax1
POWER
VDDCR_NB_11 VDDCR_NB_12 VDDCR_NB_13 VDDCR_NB_14 VDDCR_NB_15
VDDPL_10
VDDPL_10
U11
R103
0_6
+NBCORE
+NBCORE
0.1u/10V_4 C534
VDDCR_NB_16
C192
0901-- change R7037 P/N and footprint add R
C191
VDDCR_NB_17
10u/6.3V_8
VDDCR_NB_18
+1V
1u/6.3V_4
10u/6.3V_8
VDD_10
VDDCR_NB_19
C155
VDDCR_NB_20
5.5A 220mil viax11
VDDCR_NB_21 VDDCR_NB_22
VDD_10_1 VDD_10_2
2A 80mil viax4
VDD_10_3
G16 G19 E17 J16 L16 L19 N16 R16 R19 W18 U16
10u/6.3V_8
VDDCR_CPU_8
10A 400mil viax20
+1.5V_SUS
This page is different AMD Nile
1u/6.3V_4 C134
BLM18PG221SN1D(220_1.4A)_6 E8 E11 E13 F9 F12 G11 G13 H9 H12 K11 K13 L10 L12 L14 M11 M12 M13 N10 N12 N14 P11 P13
05
VDDIO_MEM_S_1
VDD_10_4
U13 W13 V12 T12
10u/6.3V_8 C579
VDDIO_MEM_S_2
0.1u/10V_4 C280
C237
R149 R144
C147
10u/6.3V_8
0_8 0_8
10u/6.3V_8
C259
10u/6.3V_8
C231 10u/6.3V_8
10u/6.3V_8
C195 1u/6.3V_4
C198
1u/6.3V_4 C233 1u/6.3V_4
C154
C197 1u/6.3V_4
0.1u/10V_4 C236
C238
C235
VDDIO_MEM_S_3 VDDIO_MEM_S_4
1u/6.3V_4
C266
1u/6.3V_4
+NBCORE
1u/6.3V_4
VDDIO_MEM_S_5 VDDIO_MEM_S_6 VDDIO_MEM_S_7
+3V
VDDIO_MEM_S_8
0.1u/10V_4
500mA 20mil viax1
VDDIO_MEM_S_9
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4 C252
VDDIO_MEM_S_10 VDDIO_MEM_S_11
VDD_33
C194
A4
C181
C203
C199
C247
C251
C250
C214 0.1u/10V_4
0.1u/10V_4 SP@FT1_ONTARIO
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
?
C528 1u/6.3V_4 +1.5V_SUS +1.5V_SUS
GND
1u/6.3V_4 A
C269 1u/6.3V_4
C289
C321
C351 10u/6.3V_8
C315 1u/6.3V_4
A
C352 10u/6.3V_8
1u/6.3V_4
+1.5V_SUS
U17D VSS_1
ONTARIO (2.0)
VSS_50
VSS_2
PART 5 OF 5
VSS_51
VSS_3
VSS_52
VSS_4
VSS_53
VSS_5
VSS_54
VSS_6
VSS_55
VSS_7
VSS_56
VSS_8
VSS_57
VSS_9
VSS_58
VSS_10
VSS_59
VSS_11
VSS_60
VSS_12
VSS_61
VSS_13
VSS_62
VSS_14
VSS_63
VSS_15
VSS_64
VSS_16
VSS_65
VSS_17
VSS_66
VSS_18
VSS_67
VSS_19
VSS_68
VSS_20
VSS_69
VSS_21
VSS_70
VSS_22
VSS_71
VSS_23
VSS_72
VSS_24
VSS_73
VSS_25
VSS_74
VSS_26 VSS_27 VSS_28 VSS_29
GROUND
A7 B7 B11 B17 B22 C4 D5 D7 D9 D11 D14 B15 D17 D19 E7 E9 E12 E20 F8 F11 F13 G4 G5 G7 G9 G12 G20 G22 H6 H11 H13 J4 J5 J7 J20 K10 K14 L4 L6 L8 L11 L13 L20 L22 M7 N4 N6 N8 N11
VSS_75 VSS_76 VSS_77 VSS_78
VSS_30
VSS_79
VSS_31
VSS_80
VSS_32
VSS_81
VSS_33
VSS_82
VSS_34
VSS_83
VSS_35
VSS_84
VSS_36
VSS_85
VSS_37
VSS_86
VSS_38
VSS_87
VSS_39
VSS_88
VSS_40
VSS_89
VSS_41
VSS_90
VSS_42
VSS_91
VSS_43
VSS_92
VSS_44
VSS_93
VSS_45
VSS_94
VSS_46
VSS_95
VSS_47
VSS_96
VSS_48
VSS_97
VSS_49
SP@FT1_ONTARIO
VSSBG_DAC
N13 N20 N22 P10 P14 R4 R7 R20 T6 T9 T11 T13 U4 U5 U7 U12 U20 U22 V8 V9 V11 V13 W1 W2 W4 W5 W7 W12 W20 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 AA4 AA22 AB2 AB5 AB9 AB13 AB17 AB21 AC5 AC9 AC13 A11
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4 C350
C272
C275
C311
C273
C271
C296
C319
C316 0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
place capacitors under BGA EMC CAPS +1.5V_SUS
C270 180P/25V_4
C303 180P/25V_4
VDD_18
C174 180P/25V_4
+VCORE
180P/25V_4 C133
+NBCORE
180P/25V_4 C128
VDDAN_18_DAC
C153 180P/25V_4
C187 180P/25V_4
C196 180P/25V_4
VDD_10
+1.5V_SUS
C232 180P/25V_4
0.1u/10V_4 C274
VDDPL_10
C234 180P/25V_4
C190 180P/25V_4
C320 0.1u/10V_4
+3V
C521 0.1u/10V_4
?
GND GND
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
ONTARIO POWER & DECOUP(3/3) Date: 1
Monday, November 01, 2010
Sheet
5
of
41
Rev 1A
1
2
3
4
5
6
7
8
06
+1.5V_SUS 3,5,7,30,37,39
0830--P/N and footprint are follow ZR7B
+0.75V_DDR_VTT 7,37 +3V 4,5,7,9,10,11,12,16,17,20,21,23,25,26,29,30,31,33,34,35,36,37,38,39,40
3 M_A_ODT0 3 M_A_ODT1 3,7 M_A_DM[0..7]
3,7 M_A_DQSP[7:0]
3,7 M_A_DQSN[7:0]
SM_MEM BUS ADDRESS C
SO-DIMM0
1010 000
SO-DIMM1
1010 001
109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200
BA0 BA1 BA2 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# W E# SA0 SA1 SCL SDA
M_A_ODT0 M_A_ODT1
116 120
ODT0 ODT1
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
11 28 46 63 136 153 170 187
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7 M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7
12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7
BUS1_A2
+1.5V_SUS CN16B
+3V
0_4 3,7 3,7
75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18
199
VDDSPD
77 122 125
NC1 NC2 NCTEST
R213 MEM_A_HOT# 198 30
M_A_EVENT# M_A_RST#
7 +DDR_VREF2 7 +DDR_VREF
1 126
+DDR_VREF
C389
0.1u/10V_4
C390
1000p/50V_4
2 3 8 9 13 14 19 20 25 26 31 32 37 38 43
0902--Add C7273
EVENT# RESET# VREF_DQ VREF_CA VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15
A
VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52
44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196
VTT1 VTT2
203 204
B
600mA +0.75V_DDR_VTT C401
DDR3-DIMM1_H=8_STD
GND
7,9,22,23 PCLK_SMB 7,9,22,23 PDAT_SMB
M_A_BS0 M_A_BS1 M_A_BS2 M_A_CS#0 M_A_CS#1 M_A_CLKP0 M_A_CLKN0 M_A_CLKP1 M_A_CLKN1 M_A_CKE0 M_A_CKE1 M_A_CAS# M_A_RAS# M_A_WE# DIMM0_SA0 DIMM0_SA1 PCLK_SMB PDAT_SMB
3,7
M_A_DQ0 M_A_DQ1 M_A_DQ7 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ2 M_A_DQ8 M_A_DQ9 M_A_DQ14 M_A_DQ11 M_A_DQ13 M_A_DQ12 M_A_DQ10 M_A_DQ15 M_A_DQ20 M_A_DQ17 M_A_DQ22 M_A_DQ23 M_A_DQ21 M_A_DQ16 M_A_DQ18 M_A_DQ19 M_A_DQ24 M_A_DQ29 M_A_DQ27 M_A_DQ26 M_A_DQ28 M_A_DQ25 M_A_DQ31 M_A_DQ30 M_A_DQ36 M_A_DQ37 M_A_DQ39 M_A_DQ34 M_A_DQ32 M_A_DQ33 M_A_DQ38 M_A_DQ35 M_A_DQ40 M_A_DQ45 M_A_DQ43 M_A_DQ42 M_A_DQ44 M_A_DQ41 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ52 M_A_DQ54 M_A_DQ50 M_A_DQ53 M_A_DQ49 M_A_DQ51 M_A_DQ55 M_A_DQ60 M_A_DQ61 M_A_DQ63 M_A_DQ62 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59
5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
GND
M_A_CS#0 M_A_CS#1 M_A_CLKP0 M_A_CLKN0 M_A_CLKP1 M_A_CLKN1 M_A_CKE0 M_A_CKE1 M_A_CAS# M_A_RAS# M_A_WE# 10K/F_4 10K/F_4
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15
4.7u/6.3V_6
C400
C386
0.1u/10V_4
4.7u/6.3V_6
206
B
3 3 3 3 3 3 3,7 3,7 3,7 3,7 3,7
98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78
205
R204 R205
M_A_BS[0..2]
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
PC2100 DDR3 SDRAM SO-DIMM (204P)
A
3,7
M_A_DQ[0..63]
CN16A
M_A_A[0..15]
PC2100 DDR3 SDRAM SO-DIMM (204P)
3,7
+1.5V_SUS C
DDR3-DIMM1_H=8_STD
3mA +1.5V_SUS
7,37 +SMDDR_VREF
R235 1K/F_4
+SMDDR_VREF R237
+DDR_VREF
*0_6
+1.5V_SUS C403
C378
C384
0.1u/10V_4 0.1u/10V_4
C415
C375
0.1u/10V_4
0.1u/10V_4
R236 1K/F_4
C372
C371
C402
C409
C413
C376
C412
4.7u/6.3V_6
4.7u/6.3V_6
2.2u/6.3V_6
2.2u/6.3V_6
1u/6.3V_4
1u/6.3V_4
1u/6.3V_4
0.1u/10V_4
+1.5V_SUS +1.5V_SUS C380
C379
C383
C385
C374
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
D
D
C381
C382
C377
C416
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
Rev 1A
DDR3 SO-DIMM (STD) Date: 1
2
3
4
5
6
Monday, November 01, 2010 7
Sheet
6 8
of
41
3
4
5
6
7
0830--P/N and footprint are follow ZR7B
+3V
3 3 3 3 3 3 3,6 3,6 3,6 3,6 3,6
R248 R247
M_A_CS#2 M_A_CS#3 M_A_CLKP2 M_A_CLKN2 M_A_CLKP3 M_A_CLKN3 M_A_CKE0 M_A_CKE1 M_A_CAS# M_A_RAS# M_A_WE# 10K/F_4 10K/F_4
6,9,22,23 PCLK_SMB 6,9,22,23 PDAT_SMB 3 M_A_ODT2 3 M_A_ODT3 3,6 M_A_DM[0..7]
B
3,6 M_A_DQSP[7:0]
3,6 M_A_DQSN[7:0]
SM_MEM BUS ADDRESS
C
SO-DIMM0
1010 000
SO-DIMM1
1010 001
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15
M_A_BS0 M_A_BS1 M_A_BS2 M_A_CS#2 M_A_CS#3 M_A_CLKP2 M_A_CLKN2 M_A_CLKP3 M_A_CLKN3 M_A_CKE0 M_A_CKE1 M_A_CAS# M_A_RAS# M_A_WE# DIMM1_SA0 DIMM1_SA1 PCLK_SMB PDAT_SMB
109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200
BA0 BA1 BA2 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# W E# SA0 SA1 SCL SDA
M_A_ODT2 M_A_ODT3
116 120
ODT0 ODT1
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
11 28 46 63 136 153 170 187
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7 M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7
12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194
M_A_DQ0 M_A_DQ1 M_A_DQ7 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ2 M_A_DQ8 M_A_DQ9 M_A_DQ14 M_A_DQ11 M_A_DQ13 M_A_DQ12 M_A_DQ10 M_A_DQ15 M_A_DQ20 M_A_DQ17 M_A_DQ22 M_A_DQ23 M_A_DQ21 M_A_DQ16 M_A_DQ18 M_A_DQ19 M_A_DQ24 M_A_DQ29 M_A_DQ27 M_A_DQ26 M_A_DQ28 M_A_DQ25 M_A_DQ31 M_A_DQ30 M_A_DQ36 M_A_DQ37 M_A_DQ39 M_A_DQ34 M_A_DQ32 M_A_DQ33 M_A_DQ38 M_A_DQ35 M_A_DQ40 M_A_DQ45 M_A_DQ43 M_A_DQ42 M_A_DQ44 M_A_DQ41 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ52 M_A_DQ54 M_A_DQ50 M_A_DQ53 M_A_DQ49 M_A_DQ51 M_A_DQ55 M_A_DQ60 M_A_DQ61 M_A_DQ63 M_A_DQ62 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59
+1.5V_SUS CN20B
+3V
3,6 3,6
M_A_EVENT# M_A_RST#
6 6
+DDR_VREF2 +DDR_VREF
R251
0_4
MEM_B_HOT#
+DDR_VREF2 +DDR_VREF C432
0.1u/10V_4
C431
1000p/50V_4
75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18
199
VDDSPD
77 122 125
NC1 NC2 NCTEST
198 30
EVENT# RESET#
1 126
VREF_DQ VREF_CA
2 3 8 9 13 14 19 20 25 26 31 32 37 38 43
0902--Add C7274
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15
VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52
44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196
VTT1 VTT2
203 204
A
B
+0.75V_DDR_VTT C421
C419
4.7u/6.3V_6
GND
3,6 M_A_BS[2..0]
98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78
GND
A
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
3,6
C437
0.1u/10V_4
4.7u/6.3V_6
DDR3-DIMM0_H=4_Standard
205
M_A_A[0..15]
07
+1.5V_SUS 3,5,6,30,37,39 +0.75V_DDR_VTT 6,37 +3V 4,5,6,9,10,11,12,16,17,20,21,23,25,26,29,30,31,33,34,35,36,37,38,39,40 M_A_DQ[0..63]
CN20A
PC2100 DDR3 SDRAM SO-DIMM (204P)
3,6
8
206
2
PC2100 DDR3 SDRAM SO-DIMM (204P)
1
DDR3-DIMM0_H=4_Standard
BUS1_A2
C
+1.5V_SUS
3mA 6,37 +SMDDR_VREF
+1.5V_SUS
R245 1K/F_4
+SMDDR_VREF R244
*0_6
+DDR_VREF2
+1.5V_SUS C423
C434
4.7u/6.3V_6
4.7u/6.3V_6
R246 1K/F_4
C410
C439
C417
C435
C420
2.2u/6.3V_6
2.2u/6.3V_6
1u/6.3V_4
1u/6.3V_4
1u/6.3V_4
C433
C426
C428
C429
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
+1.5V_SUS +1.5V_SUS
D
C411
C430
C424
C414
C418
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
D
C436
C427
C425
C438
C404
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
Rev 1A
DDR3 SO-DIMM (STD) Date: 1
2
3
4
5
6
Monday, November 01, 2010 7
Sheet
7 8
of
41
5
4
3
2
1
+3V_S5 +3V_S5
C600
U21 *TC7SH08FU
5
*0.1u/10V_4
R441
PLTRST#
33_4
A_RST#_L
R440
0_4
A_RST#_L
This page is different AMD Nile expect RTC circuit
PCIE_RST#
2 A_RST#_R
2 13,22,23,31
*0.1u/10V_4
5
C601 U20 TC7SH08FU
4
4
1
SB_GPIO_RST#
1
9
150P/25V_4
R439
31 EC_A_RST#_L
3
3
C609
08
PCIE_VDDR 11 +3V_S5 9,10,11,12,22,28,29,30,33 +3VPCU 20,29,30,31,32,33,39 +5VPCU 33,34,35,40
*0_4
R442
*0_4
D
D
RTC
U18A
CPU_CLK
4 4
DISP_CLKP DISP_CLKN
APU_CLKP APU_CLKN
DISP_CLKP DISP_CLKN
R342 R341
APU_CLKP APU_CLKN
R339 R340
13 CLK_PCIE_VGAP 13 CLK_PCIE_VGAN
DISP_CLKP_R DISP_CLKN_R
0_4 0_4
0_4 0_4
APU_CLKP_R APU_CLKN_R 4 2
RP5
SLT_GFX_CLKP 3 SLT_GFX_CLKN 1 SW@0_4P2R_4
M23 P23
PCIE_RCLKP/NB_LNK_CLKP PCIE_RCLKN/NB_LNK_CLKN
U29 U28
NB_DISP_CLKP NB_DISP_CLKN
T26 T27
NB_HT_CLKP NB_HT_CLKN
V21 T21
CPU_HT_CLKP CPU_HT_CLKN
V23 T23
SLT_GFX_CLKP SLT_GFX_CLKN
To LAN Controller
22 CLK_PCIE_LANP 22 CLK_PCIE_LANN
L29 L28
GPP_CLK0P GPP_CLK0N
To WLAN Controller
23 CLK_PCIE_WLAN1P 23 CLK_PCIE_WLAN1N
N29 N28
GPP_CLK1P GPP_CLK1N
To WWAN Connector
23 CLK_PCIE_WLAN2P 23 CLK_PCIE_WLAN2N
M29 M28
GPP_CLK2P GPP_CLK2N
T25 V25
GPP_CLK3P GPP_CLK3N
L24 L23
GPP_CLK4P GPP_CLK4N
P25 M25
GPP_CLK5P GPP_CLK5N
P29 P28
GPP_CLK6P GPP_CLK6N
N26 N27
GPP_CLK7P GPP_CLK7N
T29 T28
GPP_CLK8P GPP_CLK8N
B
T52
C518
22p/50V_4 Y3 25MHz_30PPM
A
C519
25M_X1 R349 1M/F_4
25M_X2
L25
L26
L27
14M_25M_48M_OSC
INTE#/GPIO32 INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35
LPCCLK0 LPCCLK1 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ0# LDRQ1#/CLK_REQ6#/GPIO49 SERIRQ/GPIO48
ALLOW_LDTSTP/DMA_ACTIVE# PROCHOT# LDT_PG LDT_STP# LDT_RST#
AJ6 AG6 AG4 AJ4
H24 H25 J27 J26 H29 H28 G28 J25 AA18 AB19
G21 H21 K19 G22 J24
12 12 12 12
STRAP Function
D22 RB500V-40
20mils
To EC
20mils
+3VPCU T167
+AVBAT D23 RB500V-40
20mils
R406 510/F_6 +3VRTC
20mils 1
+3VRTC_2
G1 *SHORT_ PAD1
C599 1u/6.3V_4 2
R423 1K_4
20mils Del Q33,R434,R435,R444 from BOMs, ZQE no support RTC charge circuits. 20MIL VCCRTC_2 dGPU_RST_GPIO
T75 T161 T88 T71 T87 T80 T153 T94 T99 T151 T98
3 RTC_N01
1
20MIL
CN14 1 2
CR2032 with cable AHL03003004 AHL03003032 AHL03003037 , AHL03001044
T158
+5VPCU C
R435 *68.1K/F_4
RTC_N03 R444 *150K/F_6 CN13
1 2 RTC_CONN
SERR#
*16K_6
*MMBT3904
Debug STRAPs 16
All the PCI bus has build-in Pull-UP/Down resistors
T73 T145 T146 SB_GPIO42
R434
Q33
13
2
AD23 12 AD24 12 AD25 12 AD26 12 AD27 12 dGPU_PWROK
*BAT_CONN
CR2032 (Non-Chargeable) AHL03003014 AHL030M0009
T66
T67 T149 GNT3#CLK_REQ7# LOCK# T147 T148
dGPU_VRON
16
T72 CLKRUN#
31
T95 B
INTG#
LPC_CLK0 LPC_CLK1
T152
T150
LPC_CLK0 LPC_CLK1
R101 R115
22_4 22_4
12 12
To STRAPs Page
CLK_PCI_775 31 PCLK_DEBUG 23
PCLK_DEBUG LPC_LAD0 23,31 LPC_LAD1 23,31 LPC_LAD2 23,31 LPC_LAD3 23,31 LPC_LFRAME# 23,31 LPC_DRQ#0 23
T63 IRQ_SERIRQ
31
ALLOW_LDTSTP 4 H_PROCHOT# 4,10,31 APU_PWRGD 4,30 T56 LDT_RST#
32K_X1
C1
RTC_X1
25M_X1
32K_X2
C2
RTC_X2
25M_X2
RTCCLK INTRUDER_ALERT# VDDBT_RTC_G
D2 B2 B1
PCH_SUSCLK INTRUDER_ALERT# +AVBAT
22p/50V_4
PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4
1VCCRTC_2
GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N
T93
2
GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N
PCI CLKS
PCIE_CALRP PCIE_CALRN
AA28 AA29 Y29 Y28 Y26 Y27 W28 W29 AA22 Y21 AA25 AA24 W23 V24 W24 W25
22 PCIE_RXP0_LAN 22 PCIE_RXN0_LAN 23 PCIE_RXP1 23 PCIE_RXN1 23 PCIE_RXP2 23 PCIE_RXN2
4 4
AD29 AD28
AA1 AA4 AA3 AB1 AA5 AB2 AB6 AB5 AA6 AC2 AC3 AC4 AC1 AD1 AD2 AC6 AE2 AE1 AF8 AE3 AF1 AG1 AF2 AE9 AD9 AC11 AF6 AF4 AF3 AH2 AG2 AH3 AA8 AD5 AD8 AA10 AE8 AB9 AJ3 AE7 AC5 AF5 AE6 AE4 AE11 AH5 AH4 AC12 AD12 AJ5 AH6 AB12 AB11 AD7
22_4
VCCRTC_2
WWAN
PCIE_TXP0_C PCIE_TXN0_C PCIE_TXP1_C PCIE_TXN1_C PCIE_TXP2_C PCIE_TXN2_C
V2
PCI_CLK0 R419
C603 22p/50V_4
4,30 1
WLAN C
22 PCIE_TXP0_LAN 22 PCIE_TXN0_LAN 23 PCIE_TXP1 23 PCIE_TXN1 23 PCIE_TXP2 23 PCIE_TXN2
U600_CALRP U600_CALRN
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
UMI_RX0P UMI_RX0N UMI_RX1P UMI_RX1N UMI_RX2P UMI_RX2N UMI_RX3P UMI_RX3N
AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8 AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31 CBE0# CBE1# CBE2# CBE3# FRAME# DEVSEL# IRDY# TRDY# PAR STOP# PERR# SERR# REQ0# REQ1#/GPIO40 REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42 GNT0# GNT1#/GPO44 GNT2#/GPO45 GNT3#/CLK_REQ7#/GPIO46 CLKRUN# LOCK#
W2 W1 W3 W4 Y1
R409 T156
*10K/F_4
R407 20M_6
+3V_S5
RTC_CLK must ready refore RSMRST#
Y5 32.768KHZ 2
LAN
590/F_4 2K_4 C515 C516 C514 C513 C511 C512
AE24 AE23 AD25 AD24 AC24 AC25 AB25 AB24
PCIRST#
PCI INTERFACE
R105 R108
PCIE_VDDR
UMI_TX0P UMI_TX0N UMI_TX1P UMI_TX1N UMI_TX2P UMI_TX2N UMI_TX3P UMI_TX3N
LPC
UMI_TXP0 UMI_TXN0 UMI_TXP1 UMI_TXN1 UMI_TXP2 UMI_TXN2 UMI_TXP3 UMI_TXN3
AD26 AD27 AC28 AC29 AB29 AB28 AB26 AB27
PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38 PCICLK4/14M_OSC/GPO39
CPU
UMI_RXP0_C UMI_RXN0_C UMI_RXP1_C UMI_RXN1_C UMI_RXP2_C UMI_RXN2_C UMI_RXP3_C UMI_RXN3_C
RTC
3 3 3 3 3 3 3 3
UMI_RXP0 UMI_RXN0 UMI_RXP1 UMI_RXN1 UMI_RXP2 UMI_RXN2 UMI_RXP3 UMI_RXN3
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
Part 1 of 5
Hudson M1 PCIE_RST# A_RST#
PCI EXPRESS INTERFACES
3 3 3 3 3 3 3 3
PLACE THESE PCIE AC COUPLING CAPS CLOSE TO U41
C96 C99 C86 C93 C80 C84 C70 C75
P1 L1
CLOCK GENERATOR
PCIE_RST# A_RST#_R
23,25 PCIE_RST# 30 A_RST#_R
A
C602 22p/50V_4
Hudson M1
INTRUDER_ALERT# Left not connected (Southbridge has 50-kohm internal pull-up to VBAT).
Quanta Computer Inc. PCH_SUSCLK
PCH_SUSCLK
PROJECT : ZQG
31 Size
Document Number
Rev 1A
HUDSON PCIE/LPC/CPU IF(1/5) Date: 5
4
3
2
Monday, November 01, 2010
Sheet 1
8
of
41
5
4
+3V SCL0/SDATA0
is 3V tolerance AMD datasheet define it
NB_PWRGD
R175
10K/F_4
SB_PWRGD_IN SUS_STAT# SB_TEST0 SB_TEST1 SB_TEST2 SIO_A20GATE
T155 T97 T82 31 SIO_A20GATE 31 SIO_RCIN# 31 SIO_EXT_SCI#
CPU_THERMTRIP# 31 SIO_EXT_SMI#
T166
SYS_RST#
SB/ PWR_GOOD / VDDIO_33_S 22,31 PCIE_WAKE# C346
T169
CPU_THERMTRIP# NB_PWRGD
4 CPU_THERMTRIP#
100p/50V_4
G1
30,31 ICH_RSMRST#
+3V_S5
R437
*10K/F_4
T62 T64
SYS_RST# R140
22 PCIE_REQ_LAN#
8 SB_GPIO_RST#
0_4
0908--Add net R120
+3V
*10K/F_4
SIO_A20GATE
R184 R185
+3V_S5
T61
26 SPKR 6,7,22,23 PCLK_SMB 6,7,22,23 PDAT_SMB
By AMD confirm 10K/F_4 10K/F_4
R373 R142
23 PCIE_REQ_WLAN2# 23 PCIE_REQ_WLAN1#
+3V_S5 R436
*10K/F_4
DNBSWON#
R189
10K/F_4
PCIE_WAKE#
R352
10K/F_4
SB_SCLK3
PCIE_REQ_LAN#_R
16 dGPU_PWR_EN
T168
PCLK_SMB PDAT_SMB SB_SMBCLK1 SB_SMBDATA1 0_4 PCIE_REQ_WLAN2#_R 0_4 PCIE_REQ_WLAN1#_R ACCLED_EN T142 T159 T90 T81 T91 T165 T59
C
R353
10K/F_4
SB_SDATA3
R193
10K/F_4
SB_PWRGD_IN T164
R116
2.2K_4
SB_SCLK4
R102
2.2K_4
SB_SDATA4
CPU_MEMHOT#_IN 28 OC_6# *10K/F_4
R187
+3V_S5
28
OC_4# T77 T84 T83 T78
for EMI C607
interface is 3.3S5 voltage
26
*10p/50V_4
R412 R424
26 ACZ_BITCLK_AUDIO 12 ACZ_SDOUT 26 ACZ_SDOUT_AUDIO
To Azalia HD audio
ACZ_SDIN0
26 ACZ_SYNC_AUDIO 26 ACZ_RESET#_AUDIO
C608
*10p/50V_4
C604
*10p/50V_4
C605
ACZ_BITCLK_R ACZ_SDOUT
33_4
R411 R414 R416
H3 D1 E4 D4 E8 F7 E7 F8
*10K_4 33_4 33_4
ACZ_SYNC_R ACZ_RST#_R
M3 N1 L2 M2 M1 M4 N2 P2
*10p/50V_4
+3V_S5
R417 R428
10K/F_4 10K/F_4
GBE_COL GBE_CRS
R171
10K/F_4
GBE_MDIO
B
R169
+3V_S5
R161
10K/F_4
10K/F_4
23 SB_SDATA4 23 SB_SCLK4 T58 T114 T116 T115
USB_FSD1P/GPIO186 USB_FSD1N USB_FSD0P/GPIO185 USB_FSD0N USB_HSD13P USB_HSD13N USB_HSD12P USB_HSD12N USB_HSD11P USB_HSD11N
RSMRST#
USB_HSD10P USB_HSD10N
CLK_REQ4#/SATA_IS0#/GPIO64 CLK_REQ3#/SATA_IS1#/GPIO63 SMARTVOLT1/SATA_IS2#/GPIO50 CLK_REQ0#/SATA_IS3#/GPIO60 SATA_IS4#/FANOUT3/GPIO55 SATA_IS5#/FANIN3/GPIO59 SPKR/GPIO66 SCL0/GPIO43 SDA0/GPIO47 SCL1/GPIO227 SDA1/GPIO228 CLK_REQ2#/FANIN4/GPIO62 CLK_REQ1#/FANOUT4/GPIO61 IR_LED#/LLB#/GPIO184 SMARTVOLT2/SHUTDOWN#/GPIO51 DDR3_RST#/GEVENT7# GBE_LED0/GPIO183 GBE_LED1/GEVENT9# GBE_LED2/GEVENT10# GBE_STAT0/GEVENT11# CLK_REQG#/GPIO65/OSCIN
USB_HSD9P USB_HSD9N USB_HSD8P USB_HSD8N USB_HSD7P USB_HSD7N USB_HSD6P USB_HSD6N USB_HSD5P USB_HSD5N USB_HSD4P USB_HSD4N USB_HSD3P USB_HSD3N
BLINK/USB_OC7#/GEVENT18# USB_OC6#/IR_TX1/GEVENT6# USB_OC5#/IR_TX0/GEVENT17# USB_OC4#/IR_RX0/GEVENT16# USB_OC3#/AC_PRES/TDO/GEVENT15# USB_OC2#/TCK/GEVENT14# USB_OC1#/TDI/GEVENT13# USB_OC0#/TRST#/GEVENT12#
USB_HSD2P USB_HSD2N USB_HSD1P USB_HSD1N USB_HSD0P USB_HSD0N
A10 G19
T144 USB_RCOMP_SB
J10 H11
T69 T70
H9 J8
T76 T85
GBE_RXERR
GBE_PHY_INTR
T1 T4 L6 L5 T9 U1 U3 T2 U2 T5 V5 P5 M5 P9 T7 P7 M7 P4 M9 V7
SB_SDATA4 SB_SCLK4 SB_GPIO166 SB_GPIO160
E23 E24 F21 G29
AC_OK BAT_INT#
D27 F28 F29 E27
AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO167 AZ_SDIN1/GPIO168 AZ_SDIN2/GPIO169 AZ_SDIN3/GPIO170 AZ_SYNC AZ_RST# GBE_COL GBE_CRS GBE_MDCK GBE_MDIO GBE_RXCLK GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0 GBE_RXCTL/RXDV GBE_RXERR GBE_TXCLK GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0 GBE_TXCTL/TXEN GBE_PHY_PD GBE_PHY_RST# GBE_PHY_INTR
PS2KB_DAT/GPIO189 PS2KB_CLK/GPIO190 PS2M_DAT/GPIO191 PS2M_CLK/GPIO192
+3V_S5 Hudson M1
System PWR_OK(CLG)
11.8K/F_4
D
F11 E11 E14 E12 J12 J14
USBP10+ 23 USBP10- 23
WL2(3G)
A13 B13
USBP9+ 23 USBP9- 23
WL1
D13 C13
USBP8+ 28 USBP8- 28
EXT BLUETOOTH
G12 G14
USBP7+ 28 USBP7- 28
BLUETOOTH
G16 G18
USBP6+ 25 USBP6- 25
4 IN 1 CARD READER (MMC)
D16 C16
USBP5+ 28 USBP5- 28
USB3 Connector (Daughter)
B14 A14
C
E18 E16 J16 J18
USBP2+ 20 USBP2- 20
CCD
B17 A17
USBP1+ 28 USBP1- 28
USB2 Connector (Daughter)
A16 B16
USBP0+ 28 USBP0- 28
USB1 Connector (MB Side)
SCL2/SDATA2 is 3V/S5 tolerance AMD datasheet define it SCL2/GPIO193 SDA2/GPIO194 SCL3_LV/GPIO195 SDA3_LV/GPIO196 EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2/EC_TIMER2/GPIO199 EC_PWM3/EC_TIMER3/GPIO200 KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208
PS2_DAT/SDA4/GPIO187 PS2_CLK/SCL4/GPIO188 SPI_CS2#/GBE_STAT2/GPIO166 FC_RST#/GPO160
R139
B12 A12
*10K_4
33_4
R425
AD19 AA16 AB21 AC18 AF20 AE19 AF19 AD22 AE22 F5 F4 AH21 AB18 E1 AJ21 H4 D5 D7 G5 K3 AA20
Hudson M1
USB_RCOMP
USB 1.1 USB MISC
4.7K_4
USBCLK/14M_25M_48M_OSC
USB 2.0
R133 +3V_S5
This page is different AMD Nile
PCI_PME#/GEVENT4# RI#/GEVENT22# SPI_CS3#/GBE_STAT1/GEVENT21# SLP_S3# SLP_S5# PWR_BTN# PWR_GOOD SUS_STAT# Part 4 of 5 TEST0 TEST1/TMS TEST2 GA20IN/GEVENT0# KBRST#/GEVENT1# LPC_PME#/GEVENT3# LPC_SMI#/GEVENT23# GEVENT5# SYS_RESET#/GEVENT19# WAKE#/GEVENT8# IR_RX1/GEVENT20# THRMTRIP#/SMBALERT#/GEVENT2# NB_PWRGD
ACPI / WAKE UP EVENTS
*10K/F_4 SUS_STAT#
J2 K1 D3 F1 H1 F2 H5 G6 B3 C4 F6 AD21 AE21 K2 J29 H2 J1 H6 F3 J6 AC19
GPIO
D
R179
RI# SPI_CS3#
09
4,5,6,7,10,11,12,16,17,20,21,23,25,26,29,30,31,33,34,35,36,37,38,39,40 8,10,11,12,22,28,29,30,33
U18D 3 APU_MEMHOT# T163 T157 30,31 SUSB# 30,31 SUSC# 30,31 DNBSWON#
USB OC
PDAT_SMB
+3V
EMBEDDED CTRL
2.2K_4
Clock gen/Robson/TV tuner /DDR3/DDR3 thermal/Accelerometer
EMBEDDED CTRL
PCLK_SMB
1
+3V +3V_S5
HD AUDIO
R131
2.2K_4
2
GBE LAN
R125
3
KSO_0/GPIO209 KSO_1/GPIO210 KSO_2/GPIO211 KSO_3/GPIO212 KSO_4/GPIO213 KSO_5/GPIO214 KSO_6/GPIO215 KSO_7/GPIO216 KSO_8/GPIO217 KSO_9/GPIO218 KSO_10/GPIO219 KSO_11/GPIO220 KSO_12/GPIO221 KSO_13/GPIO222 KSO_14/GPIO223 KSO_15/GPIO224 KSO_16/GPIO225 KSO_17/GPIO226
D25 F23 B26 E26 F25 E22 F22 E21 G24 G25 E28 E29 D29 D28 C29 C28
T53 T125
SB_SCLK2 SB_SDATA2 SB_SCLK3 SB_SDATA3
R360 R362
SB_GPIO199 SB_GPIO200
R132 R134
10K/F_4 10K/F_4
+3V_S5
SB_SCLK3 4 SB_SDATA3 4 *2.2K_4 2.2K_4
GPIO200
has checked with AMD FAE already--Allen
GPIO199
H,H = Reserved
B
H,L = SPI ROM (DEFAULT) B28 A27 B27 D26 A26 C26 A24 B25 A25 D24 B24 C24 B23 A23 D22 C22 A22 B22
L,H = LPC ROM L,L = FWH ROM
C349 *0.1u/10V_4 A
U8
5
A
2 SB_PWRGD_IN
17,30 SB_PWRGD_IN
CPU_COREPG
4 1
PWROK_EC
PWROK_EC
30,34
30,31
3
TC7SH08FU
Quanta Computer Inc.
R194 100K_4
PROJECT : ZQG Size
Document Number
Date:
Monday, November 01, 2010
Rev 1A
HUDSON ACPI/GPIO/USB(2/5) 5
4
3
2
Sheet 1
9
of
41
5
4
C592 C590
SATA_TXP0 SATA_TXN0
24 24
SATA_RXN0 SATA_RXP0
24 24
SATA_TXP1 SATA_TXN1
24 24
SATA_RXN1 SATA_RXP1
PLACE SATA_CAL RES VERY CLOSE TO BALL OF Hudson M1
1
10
C588 C585
.01U/16V/X7R_4 .01U/16V/X7R_4
.01U/16V/X7R_4 .01U/16V/X7R_4
U18B
SATA_TXP0_C SATA_TXN0_C
SATA_TXP1_C SATA_TXN1_C
XTLVDD_SATA-- SATA crystal power PLVDD_SATA-SATA PLL POWER
SATA_TX0P SATA_TX0N
AJ8 AH8
SATA_RX0N SATA_RX0P
AH10 AJ10
SATA_RX1N SATA_RX1P
AG12 AF12
SATA_TX2P SATA_TX2N
AJ12 AH12
SATA_RX2N SATA_RX2P
AH14 AJ14
SATA_TX3P SATA_TX3N
AG14 AF14
SATA_RX3N SATA_RX3P
AJ17 AH17 AJ18 AH18 AH19 AJ19
AVDD_SATA
29
1K/F_4 931/F_4
SATA_CALRP SATA_CALRN
AB14 AA14 AD11
SATA_LED#
Part 2 of 5
SATA_TX1P SATA_TX1N
AG10 AF10
AG17 AF17
R147 R143
Hudson M1
AH9 AJ9
FLASH
SATA ODD
PLACE SATA AC COUPLING CAPS CLOSE TO Hudson M1
SATA_TX4P SATA_TX4N SATA_RX4N SATA_RX4P SATA_TX5P SATA_TX5N SATA_RX5N SATA_RX5P
SERIAL ATA
D
24 24
2
AVDD_SATA 11 +3V 4,5,6,7,9,11,12,16,17,20,21,23,25,26,29,30,31,33,34,35,36,37,38,39,40 +3V_S5 8,9,11,12,22,28,29,30,33
SATA PORT 0,1,2,3 can support AHCI mode
SATA HDD
3
SATA_X1 Y4 *25MHz_30PPM
C582
AD16
SATA_ACT#/GPIO67
SATA_X1
R381 *1M/F_4 SATA_X2 AC16
*22p/50V_4
T123 T124 T47
FC_OE#/GPIOD145 FC_AVD#/GPIOD146 FC_WE#/GPIOD148 FC_CE1#/GPIOD149 FC_CE2#/GPIOD150 FC_INT1/GPIOD144 FC_INT2/GPIOD147
AF28 AG29 AG26 AF27 AE29 AF29 AH27
T121 T122 T128 T119 T118 T120 T129
FC_ADQ0/GPIOD128 FC_ADQ1/GPIOD129 FC_ADQ2/GPIOD130 FC_ADQ3/GPIOD131 FC_ADQ4/GPIOD132 FC_ADQ5/GPIOD133 FC_ADQ6/GPIOD134 FC_ADQ7/GPIOD135 FC_ADQ8/GPIOD136 FC_ADQ9/GPIOD137 FC_ADQ10/GPIOD138 FC_ADQ11/GPIOD139 FC_ADQ12/GPIOD140 FC_ADQ13/GPIOD141 FC_ADQ14/GPIOD142 FC_ADQ15/GPIOD143
AJ27 AJ26 AH25 AH24 AG23 AH23 AJ22 AG21 AF21 AH22 AJ23 AF23 AJ24 AJ25 AG25 AH26
T126 T133 T132 T137 T135 T134 T138 T143 T139 T140 T141 T131 T136 T130 T46 T127
SATA_X2
This page is different AMD Nile
D
AMD recommand : TEMPIN0 / TEMPIN1 / TEMPIN2 can not maintain on floating stages when without usage. Do not care pull high or pull down.
TEMPIN2 TEMPIN1 TEMPIN0
R388 10K_4
W5 W6 Y9
BOARD_ID0 BOARD_ID1 SB_PROCHOT#
W7 V9 W8
BOARD_ID2 BOARD_ID3 BOARD_ID4
TEMPIN0/GPIO171 TEMPIN1/GPIO172 TEMPIN2/GPIO173 TEMPIN3/TALERT#/GPIO174 TEMP_COMM
B6 A6 A5 B5 C7
TEMPIN0 TEMPIN1 TEMPIN2 SB_TALERT#
VIN0/GPIO175 VIN1/GPIO176 VIN2/GPIO177 VIN3/GPIO178 VIN4/GPIO179 VIN5/GPIO180 VIN6/GBE_STAT3/GPIO181 VIN7/GBE_LED3/GPIO182
A3 B4 A4 C5 A7 B7 B8 A8
CPU_TYPE SB_HOLE_TIME CPU_SENSOR VIN2 R390 R387 VIN3 VIN4 R386 VIN5 R383 BOARD_ID5
FANIN0/GPIO56 FANIN1/GPIO57 FANIN2/GPIO58
SATA_CALRP SATA_CALRN
HW MONITOR
*22p/50V_4
AH28 AG28 AF26
FANOUT0/GPIO52 FANOUT1/GPIO53 FANOUT2/GPIO54
C
C575
FC_CLK FC_FBCLKOUT FC_FBCLKIN
R389 10K_4
0831--modify location
MB ID
SB_TALERT# 4
CPU THERMAL
10K_4 10K_4 10K_4 10K_4
SPI_DI/GPIO164 SPI_DO/GPIO163 SPI_CLK/GPIO162 SPI_CS1#/GPIO165 ROM_RST#/GPIO161
SPI ROM
SPI_DI J5 SPI_DO E2 SPI_CLK K4 SPI_CS1# K9 ROM_RST# G2
NC1 NC2
G27 Y2
1
SB-TSI
0
D6
RB500V-40
H_PROCHOT#
4,8,31 H_PROCHOT#
GPIO57 ( Dis ) SW
1
UMA
0
GPIO53
GPIO58
1.2V
1
VRAM - 800
1.1V
0
VRAM-900
1 0
GPIO56
DU1/MK2
Hudson M1
C
GPIO52
External
SB8XX Hold Time T89 T96 T160 T79 T162
R391 10K_4
GPIO182
MK2.0 AMD
1
PX4.0
1
DU1.0 AMD
0
PX3.0
0
SB_PROCHOT#
0831--add circuit
+3V
GPIO52 R182
10K_4
BOARD_ID0
R181
10K_4
BOARD_ID1
R192
*10K_4
R191
*10K_4
R190
*10K_4
R157
SP@10K_4
R429
SP@10K_4
GPIO53 B
B
GPIO56 R180
10K_4
BOARD_ID2
R158
*SP@10K_4
BOARD_ID3
R418
*SP@10K_4
BOARD_ID4
*SP@10K_4
BOARD_ID5
GPIO57 GPIO58
+3V_S5
GPIO182
R385
R384
R399
SP@10K_4
R400
*10K/F_4
CPU_TYPE
R395
*10K/F_4
CPU_SENSOR
R394
10K/F_4 10K/F_4
R398
*10K/F_4
SB_HOLE_TIME
R397
10K/F_4
A
A
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
Rev 1A
HUDSON SATA/BIDs(3/5) Date: 5
4
3
2
Monday, November 01, 2010
Sheet 1
10
of
41
5
4
3
2
1
11
+3V 4,5,6,7,9,10,12,16,17,20,21,23,25,26,29,30,31,33,34,35,36,37,38,39,40 +1.1V 30,35 +3V_S5 8,9,10,12,22,28,29,30,33 +1.1V_S5 30,35 AVDD_SATA 10 VDDIO_AZ 12
This page is different AMD Nile PLACE ALL THE DECOUPLING CAPS ON THIS SHEET CLOSE TO SB AS POSSIBLE.
C338
C178
0.1u/10V_4
GPIOD Interface Not Implemented connected to GND through a 0-Ω resistor R129
0_6
AF22 AE25 AF24 AC22
VDDIO_18_FC_1 VDDIO_18_FC_2 VDDIO_18_FC_3 VDDIO_18_FC_4
+3V
L49
HCB1608KF-221T20
POWER
22mA
VDDPL_3.3V_PCIE
AE28
1115mA 50mil viax3 +1.1V
C517 2.2u/6.3V_6
PCIE_VDDR
C510 *0.1u/10V_4
U26 V22 V26 V27 V28 V29 W22 W26
C
L46 FBMA-11-201209-800A50T(80,5A) 0.1u/10V_4 C503
C123
22U/6.3V/X5R_8
+3V
VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6 VDDAN_11_CLK_7 VDDAN_11_CLK_8
150mA 10mil viax1 VDDIO_18_FC
C144
C122
1u/6.3V_4
1u/6.3V_4
VDDRF_GBE_S VDDIO_33_GBE_S
VDDPL_33_PCIE VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8
VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8 VDDCR_11_9
VDDCR_11_GBE_S_1 VDDCR_11_GBE_S_2 VDDIO_GBE_S_1 VDDIO_GBE_S_2
R145
VCC_SB_R
N13 R15 N17 U13 U17 V12 V18 W12 W18
0.1u/10V_4
0_6
C245
C284
C291
10u/6.3V_8
C290
C260
1u/6.3V_4
1u/6.3V_4 +1.1V
382mA 20mil viax1 L45
+1.1V_CKVDD
K28 K29 J28 K26 J21 J20 K21 J22
Y14 Y16 AB16 AC14 AE12 AE14 AF9 AF11 AF13 AF16 AG8 AH7 AH11 AH13 AH16 AJ7 AJ11 AJ13 AJ16
0.1u/10V_4
0.1u/10V_4
FBMA-11-201209-800A50T(80,5A)
0.1u/10V_4
C502 C185
C156
C113
1u/6.3V_4
22U/6.3V/X5R_8
C145 1u/6.3V_4
A9 B10 K11 B9 D10 D12 D14 D17 E9 F9 F12 F14 F16 C9 G11 F18 D9 H12 H14 H16 H18 J11 J19 K12 K14 K16 K18 H19
V1 M10
L7 L9 M6 P8
15mA 5mil vaix1 AJ20 AF18 AH20 AG19 AE18 AD18 AE16
C268 2.2u/6.3V_6 +1.1V
AVDD_SATA
VDDPL_33_SATA VDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7
1354mA 60mil viax3
L24
3.3V_S5 I/O
AD14
VDDPL_3.3V_SATA
HCB1608KF-221T20
SERIAL ATA
L29
A18 A19 A20 B18 B19 B20 C18 C20 D18 D19 D20 E19
C224 C228 22U/6.3V/X5R_8
+3V_S5
L52
C249
C229
1u/6.3V_4
HCB1608KF-221T20
AVDD_USB
0.1u/10V_4
B
C572 +1.1V_S5
C244
10u/6.3V_8
L53
1u/6.3V_4
534mA 25mil viax2 1u/6.3V_4
C573
C571
10u/6.3V_8
HCB1608KF-221T20
C230
C217 1u/6.3V_4
C11 D11
VDDAN_33_USB_S_1 VDDAN_33_USB_S_2 VDDAN_33_USB_S_3 VDDAN_33_USB_S_4 VDDAN_33_USB_S_5 VDDAN_33_USB_S_6 VDDAN_33_USB_S_7 VDDAN_33_USB_S_8 VDDAN_33_USB_S_9 VDDAN_33_USB_S_10 VDDAN_33_USB_S_11 VDDAN_33_USB_S_12
USB I/O
0.1u/10V_4
VDDAN_11_USB_S_1 VDDAN_11_USB_S_2
VDDIO_AZ_S VDDCR_11_USB_S_1 VDDCR_11_USB_S_2 VDDPL_33_SYS
VDDPL_33_USB_S
VDDXL_33_S
49mA +3.3ALW_R
C201
R137
0_6
R113
0_6
C301
2.2u/6.3V_6
2.2u/6.3V_6
M8 A11 B11 M21 L22 F19 D6 L20
D8 1u/6.3V_4
15mA
M19
VDDIO_AZ
58mA
C117
C116
VDDCR_1.1_USB
L51 VDDPL_3.3V
P21 P20 M22 M24 M26 P22 P24 P26 T20 T22 T24 V20 J23
HCB1608KF-221T20
0.1u/10V_4
VDDPL_1.1V
C567
AVDD_USB
EFUSE
C583
10u/6.3V_8
C584 +3V
0.1u/10V_4
VDDAN_3.3V_HWM VDDXL_3.3V
C
VSSAN_HWM VSSXL
VSSPL_SYS
L25
HCB1608KF-221T20
VSSIO_PCIECLK_1 VSSIO_PCIECLK_2 VSSIO_PCIECLK_3 VSSIO_PCIECLK_4 VSSIO_PCIECLK_5 VSSIO_PCIECLK_6 VSSIO_PCIECLK_7 VSSIO_PCIECLK_8 VSSIO_PCIECLK_9 VSSIO_PCIECLK_10 VSSIO_PCIECLK_11 VSSIO_PCIECLK_12 VSSIO_PCIECLK_13
C207
C587 0.1u/10V_4
AJ2 A28 A2 E5 D23 E25 E6 F24 N15 R13 R17 T10 P10 V11 U15 M18 V19 M11 L12 L18 J7 P3 V4 AD6 AD4 AB7 AC9 V8 W9 W10 AJ28 B29 U4 Y18 Y10 Y12 Y11 AA11 AA12 G4 J4 G8 G9 M12 AF25 H7 AH29 V10 P6 N4 L4 L8 M20
+1.1V_S5 1u/6.3V_4
46mA 65mA 16mA 12mA 5mA
VSSIO_USB_1 VSSIO_USB_2 VSSIO_USB_3 VSSIO_USB_4 VSSIO_USB_5 VSSIO_USB_6 VSSIO_USB_7 VSSIO_USB_8 VSSIO_USB_9 VSSIO_USB_10 VSSIO_USB_11 VSSIO_USB_12 VSSIO_USB_13 VSSIO_USB_14 VSSIO_USB_15 VSSIO_USB_16 VSSIO_USB_17 VSSIO_USB_18 VSSIO_USB_19 VSSIO_USB_20 VSSIO_USB_21 VSSIO_USB_22 VSSIO_USB_23 VSSIO_USB_24 VSSIO_USB_25 VSSIO_USB_26 VSSIO_USB_27 VSSIO_USB_28
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52
+1.1V_S5
Y4
VDDCR_1.1V
F26 G26
+3V_S5
VSSIO_SATA_1 VSSIO_SATA_2 VSSIO_SATA_3 VSSIO_SATA_4 VSSIO_SATA_5 VSSIO_SATA_6 VSSIO_SATA_7 VSSIO_SATA_8 VSSIO_SATA_9 VSSIO_SATA_10 VSSIO_SATA_11 VSSIO_SATA_12 VSSIO_SATA_13 VSSIO_SATA_14 VSSIO_SATA_15 VSSIO_SATA_16 VSSIO_SATA_17 VSSIO_SATA_18 VSSIO_SATA_19
Hudson M1
88mA C577
VDDCR_11_S_1 VDDCR_11_S_2
VDDAN_33_HWM_S
VDDAN_1.1V_USB
A21 D21 B21 K10 L10 J9 T6 T8
165mA 10mil viax1
VDDPL_11_SYS_S
PLL
0.1u/10V_4
CORE S5
FBMA-11-201209-800A50T(80,5A)
VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8
D
Hudson M1
GROUND
C326
VDDIO_33_PCIGP_1 VDDIO_33_PCIGP_2 VDDIO_33_PCIGP_3 VDDIO_33_PCIGP_4 VDDIO_33_PCIGP_5 VDDIO_33_PCIGP_6 VDDIO_33_PCIGP_7 VDDIO_33_PCIGP_8 VDDIO_33_PCIGP_9 VDDIO_33_PCIGP_10 VDDIO_33_PCIGP_11 VDDIO_33_PCIGP_12
CORE S0
C340 22U/6.3V/X5R_8
AH1 V6 Y19 AE5 AC21 AA2 AB4 AC8 AA7 AA9 AF7 AA19
0.1u/10V_4
CLKGEN I/O
0.1u/10V_4
790mA 35mil viax2
Part 3 of 5
Hudson M1
PCI/GPIO I/O
+3.3V_SB_R
FLASH I/O
0_6
U18C
GBE LAN
R188
+1.1V U18E
42mA
PCI EXPRESS
+3V
D
VSSIO_PCIECLK_14 VSSIO_PCIECLK_15 VSSIO_PCIECLK_16 VSSIO_PCIECLK_17 VSSIO_PCIECLK_18 VSSIO_PCIECLK_19 VSSIO_PCIECLK_20 VSSIO_PCIECLK_21 VSSIO_PCIECLK_22 VSSIO_PCIECLK_23 VSSIO_PCIECLK_24 VSSIO_PCIECLK_25 VSSIO_PCIECLK_26 VSSIO_PCIECLK_27
H23 H26 AA21 AA23 AB23 AD23 AA26 AC26 Y20 W21 W20 AE26 L21 K20
B
Part 5 of 5 Hudson M1
2.2u/6.3V_6
2.2u/6.3V_6
+3V
+3V_S5
VDDIO_AZ +3V
+1.1V
+1.1V_S5
+3V_S5
VDDPL_3.3V R186
*0_6
R183
0_6
L22
VDDAN_3.3V_HWM
VDDPL_1.1V L20
HCB1608KF-221T20
L30 HCB1608KF-221T20
HCB1608KF-221T20
L21 *HCB1608KF-221T20 C183
C98
C334
0.1u/10V_4 C336
C322 2.2u/6.3V_6 A
2.2u/6.3V_6
2.2u/6.3V_6
2.2u/6.3V_6
A
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
Date:
Monday, November 01, 2010
Rev 1A
HUDSON PWR/GND(4/5) 5
4
3
2
Sheet 1
11
of
41
5
4
3
2
12
VDDIO_AZ 11 +3V 4,5,6,7,9,10,11,16,17,20,21,23,25,26,29,30,31,33,34,35,36,37,38,39,40 +3V_S5 8,9,10,11,22,28,29,30,33
intermal have pull Hi 10K , confirm AMD ward this pull Hi not need
OVERLAP COMMON PADS WHERE POSSIBLE FOR DUAL-OP RESISTORS.
1
REQUIRED STRAPS D
D
VDDIO_AZ
+3V
+3V
R430 R413 *10K/F_4 9
ACZ_SDOUT
10K/F_4
+3V
R431
R427
*10K/F_4
*10K/F_4
DEBUG STRAPS HUDSON-M1 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
8
PCI_CLK1
8
PCI_CLK2
R420 R426 10K/F_4
8
PCI_CLK3
R421
*10K/F_4
8 8 8 8 8
R415
10K/F_4
AD27 AD26 AD25 AD24 AD23
10K/F_4
Use 2.2K PD.
C
+3V
8
B
+3V_S5
R432
R128
*10K/F_4
*10K/F_4
PCI_CLK4
8
LPC_CLK0
R127
10K/F_4
10K/F_4
R393 *2.2K_4
R151 *2.2K_4
R165 *2.2K_4
R152 *2.2K_4
C
+3V_S5
R123
PULL HIGH
10K/F_4
8
R422
R401 *2.2K_4
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
USE PCI PLL
DISABLE ILA AUTORUN
USE FC PLL
USE DEFAULT PCIE STRAPS
DISABLE PCI MEM BOOT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
BYPASS PCI PLL
ENABLE ILA AUTORUN
BYPASS FC PLL
USE EEPROM PCIE STRAPS
LPC_CLK1
PULL LOW
R122
ENABLE PCI MEM BOOT
*10K/F_4
PCI_CLK4 CPU/NB HT Clock Selection 0 V – Reserved. 3.3 V – Required setting for integrated clock mode. This strap is not used if the strap CLKGEN is configured for external clock generator mode.
B
REQUIRED STRAPS
PULL HIGH
AZ_SDOUT
PCI_CLK1
PCI_CLK2
LOW POWER MODE
ALLOW PCIE Gen2
Watchdog Timer Enabled
USE DEBUG STRAP
Watchdog Timer Disabled
IGNORE DEBUG STRAP
DEFAULT
DEFAULT
DEFAULT
PERFORMANCE MODE
PULL LOW
DEFAULT
A
FORCE PCIE Gen1
PCI_CLK3
PCI_CLK4 non_Fusion CLOCK MODE
FUSION CLOCK MODE DEFAULT
LPC_CLK0 EC ENABLED
EC DISABLED
LPC_CLK1
GPIO200
GPIO199
CLKGEN ENABLED
H,H = Reserved
DEFAULT
H,L = SPI ROM (Default)
CLKGEN DISABLED
L,H = LPC ROM L,L = FWH ROM
DEFAULT
A
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
Rev 1A
HUDSON STRAPS/PWRGD(5/5) Date: 5
4
3
2
Monday, November 01, 2010
Sheet 1
12
of
41
5
4
3
2
1
15
U15A
PEG_TXP[3..0]
3 PEG_TXP[3..0]
PEG_TXN[3..0]
3 PEG_TXN[3..0]
PEG_TXP3 PEG_TXN3
AA38 Y37
PEG_TXP2 PEG_TXN2
Y35 W36
PEG_TXP1 PEG_TXN1 PEG_TXP0 PEG_TXN0
D
PEG_RXP[3..0]
3 PEG_RXP[3..0]
PCIE_TX0P PCIE_TX0N
Y33 Y32
PEG_RXP3_C PEG_RXN3_C
C179 C189
[email protected]/10V_4 [email protected]/10V_4
PCIE_RX1P PCIE_RX1N
PCIE_TX1P PCIE_TX1N
W33 W32
PEG_RXP2_C PEG_RXN2_C
C205 C213
[email protected]/10V_4 [email protected]/10V_4
PEG_RXP2 PEG_RXN2
W38 V37
PCIE_RX2P PCIE_RX2N
PCIE_TX2P PCIE_TX2N
U33 U32
PEG_RXP1_C PEG_RXN1_C
C221 C246
[email protected]/10V_4 [email protected]/10V_4
PEG_RXP1 PEG_RXN1
V35 U36
PCIE_RX3P PCIE_RX3N
PCIE_TX3P PCIE_TX3N
U30 U29
PEG_RXP0_C PEG_RXN0_C
C255 C262
[email protected]/10V_4 [email protected]/10V_4
PEG_RXP0 PEG_RXN0
U38 T37
PCIE_RX4P PCIE_RX4N
PCIE_TX4P PCIE_TX4N
T33 T32
T35 R36
PCIE_RX5P PCIE_RX5N
PCIE_TX5P PCIE_TX5N
T30 T29
R38 P37
PCIE_RX6P PCIE_RX6N
PCIE_TX6P PCIE_TX6N
P33 P32
P35 N36
PCIE_RX7P PCIE_RX7N
PCIE_TX7P PCIE_TX7N
P30 P29
N38 M37
PCIE_RX8P PCIE_RX8N
PCIE_TX8P PCIE_TX8N
N33 N32
M35 L36
PCIE_RX9P PCIE_RX9N
PCIE_TX9P PCIE_TX9N
N30 N29
L38 K37
PCIE_RX10P PCIE_RX10N
PCIE_TX10P PCIE_TX10N
L33 L32
K35 J36
PCIE_RX11P PCIE_RX11N
PCIE_TX11P PCIE_TX11N
L30 L29
J38 H37
PCIE_RX12P PCIE_RX12N
PCIE_TX12P PCIE_TX12N
K33 K32
H35 G36
PCIE_RX13P PCIE_RX13N
PCIE_TX13P PCIE_TX13N
J33 J32
G38 F37
PCIE_RX14P PCIE_RX14N
PCIE_TX14P PCIE_TX14N
K30 K29
F35 E37
PCIE_RX15P PCIE_RX15N
PCIE_TX15P PCIE_TX15N
H33 H32
PCIE_RX0P PCIE_RX0N
PEG_RXP3 PEG_RXN3 D
PEG_RXN[3..0]
3 PEG_RXN[3..0]
B
PCI EXPRESS INTERFACE
C
C
B
+3V_D
R361 SW@10K/F_4 D20
SW@BAS316
D19
SW@BAS316
PCIE_RST_VGA#
PLTRST# 8,22,23,31
CLOCK 8 CLK_PCIE_VGAP 8 CLK_PCIE_VGAN
For Madison and Park the PWRGOOD ball must be conneccted to ground
A
AB35 AA36
PCIE_REFCLKP PCIE_REFCLKN
AJ21 AK21 AH16
NC#1 NC#2 PWRGOOD
AA30
PERSTB
dGPU_RST_GPIO 8
CALIBRATION
R76
SW@10K_4
PCIE_RST_VGA#
PCIE_CALRP
Y30
R130
[email protected]/F_4
PCIE_CALRN
Y29
R135
SW@2K/F_4
C04 A
+1V_GPU
Quanta Computer Inc.
SW@SEYMOUR_M2
PROJECT : ZQG Size
Document Number
Rev 1A
SeymourPCIE 1/6 Date: 5
4
3
2
Monday, November 01, 2010
Sheet 1
13
of
41
5
4
3
2
1
16
U15B U15G TXCAP_DPA3P TXCAM_DPA3N TX0P_DPA2P TX0M_DPA2N
MUTI GFX DPA
+3V_D
TX5P_DPB0P TX5M_DPB0N TXCCP_DPC3P TXCCM_DPC3N TX0P_DPC2P TX0M_DPC2N DPC
TX1P_DPC1P TX1M_DPC1N TX2P_DPC0P TX2M_DPC0N TXCDP_DPD3P TXCDM_DPD3N TX3P_DPD2P TX3M_DPD2N
DPD R84 SW@10K/F_4
R65 SW@10K/F_4
TX4P_DPD1P TX4M_DPD1N
I2C AK26 AJ26
C
TX5P_DPD0P TX5M_DPD0N
T42 T41 T36 T25
18 SIN_GPIO9 18 GPU_GPIO11 18 GPU_GPIO12 18 GPU_GPIO13
3.3V GPIO
38
IO_VID1 IO_VID0 EV_LVDS_BLON SOUT_GPIO8 SIN_GPIO9 SCLK_GPIO10
T54
T23
GPU_VID1
GPU_VID3 T55
18 ALT#_GPIO17 38
T20 T27
GPU_VID2
SCS#_GPIO22
T48 18 SCS#_GPIO22 R96
GPIO24_TRSTB GPIO25_TDI GPIO26_TCK GPIO27_TMS GPIO28_TDO
*SW@10K/F_4 T31 T38 T37 T18
B
AH20 AH18 AN16 AH23 AJ23 AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17 AL13 AJ14 AK13 AN13 AM23 AN23 AK23 AL24 AM24 AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24 AK24
GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16_SSIN GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCSB GPIO_23_CLKREQB JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF GENERICG
G GB B BB
DAC1
HSYNC VSYNC RSET AVDD AVSSQ VDD1DI VSS1DI R2 R2B G2 G2B B2 B2B C Y COMP
SW@499/F_4
VREFG
AH13
AT33 AU32
AF35 AG36
TXOUT_U3P TXOUT_U3N
AU14 AV13
LVTMDP
AT15 AR14
AP34 AR34
TXCLK_LP_DPE3P TXCLK_LN_DPE3N
AU16 AV15
AW37 AU35
TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N
AT17 AR16
AR37 AU39
TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N
AU20 AT19
AP35 AR35
TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N
AT21 AR20
AN36 AP37
TXOUT_L3P TXOUT_L3N
AU22 AV21 AT23 AR22
SW@SEYMOUR_M2
AD39 AD37
EXT_CRT_RED
AE36 AD35
EXT_CRT_GRN
AF37 AE38
EXT_CRT_BLU
AC36 AC38 AB34
EXT_HSYNC EXT_VSYNC R121
18 18
SW@499/F_4
AD34 AE34
AVDD
AC33 AC34
VDD1DI
+1.8V_GPU
(1.8V@70mA AVDD) AVDD [email protected]/10V_4 C90
AC30 AC31 AD30 AD31
120 ohm/300mA L19 SW@SBY100505T-121Y-N/0.3A/120ohm_4 SW@10U/6.3V_6
C88 C87 SW@1U/6.3V_4
(1.8V@100mA VDD1DI) VDD1DI
AF30 AF31
[email protected]/10V_4 C89 AC32 AD32 AF32
120 ohm/300mA L17 SW@SBY100505T-121Y-N/0.3A/120ohm_4
SW@10U/6.3V_6 C94 C83 SW@1U/6.3V_4
B
DAC2 H2SYNC V2SYNC
HPD1
A2VDD R55
AG38 AH37
TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N
C
R RB
VDD2DI VSS2DI
+1.8V_GPU
AH35 AJ36
TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N
AR32 AT31
SCL SDA GENERAL PURPOSE I/O
18 GPU_GPIO0 18 GPU_GPIO1 18 GPU_GPIO2 18 GPIO3_SMBDAT 18 GPIO4_SMBCLK
AV31 AU30
D
AJ38 AK37
TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N
R124
For Park-M2 NC pin DVPDATA_17 DVPDATA_23
TX4P_DPB1P TX4M_DPB1N
*SW@10K_4
AK35 AL36
TXCLK_UP_DPF3P TXCLK_UN_DPF3N
AR30 AT29
R111
1.8V GPIO
TX3P_DPB2P TX3M_DPB2N
DPB
AT27 AR26
*SW@150/F_4
T21
1 => +3V_D 2 => +VGPU_CORE 3 => +1V 4 => +1.5V_GPU 5 => +1.8V_GPU 6 => dGPU_PWROK
TX2P_DPA0P TX2M_DPA0N TXCBP_DPB3P TXCBM_DPB3N
R107
18 RAM_STRAP0 18 RAM_STRAP1 18 RAM_STRAP2
DVPCNTL_MVP_0 DVPCNTL_MVP_1 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23
R97
AK27 AJ27
VARY_BL DIGON
AU26 AV25
*SW@150/F_4
GPU Power-on sequence
AR8 AU8 AP8 AW8 AR3 AR1 AU1 AU3 AW3 AP6 AW5 AU5 AR6 AW6 AU6 AT7 AV7 AN7 AV9 AT9 AR10 AW10 AU10 AP10 AV11 AT11 AR12 AW12 AU12 AP12
LVDS CONTROL
AT25 AR24
*SW@150/F_4
For Park-M2 NC pin D
TX1P_DPA1P TX1M_DPA1N
AU24 AV23
A2VDDQ VREFG A2VSSQ
R79 C56 SW@249/F_4 [email protected]/10V_4
R2SET
T51
AD29 AC29 AG31 AG32
V2SYNC VDD1DI
AG33 AD33
+3V_D
(3.3V@130mA A2VDD)
A2VDDQ C112 [email protected]/10V_4
AF33 AA29
18
R126
SW@715/F_4
+1.8V(75mA)
+1.8V_GPU
120 ohm/300mA L14 SW@SBY100505T-121Y-N/0.3A/120ohm_4
DPLL_PVDD
DDC/AUX PLL/CLOCK
C60
C63
C68
DPLL_PVDD
AM32 AN32
DPLL_VDDC
AN31
SW@10U/6.3V_6 SW@1U/6.3V_4 [email protected]/10V_4 C53 120 ohm/300mA L13 SW@SBY100505T-121Y-N/0.3A/120ohm_4 C59
C62
DPLL_VDDC
C67
SW@10U/6.3V_6 SW@1U/6.3V_4 [email protected]/10V_4
C54
18 18
+1.8V(5mA)
120 ohm/300mA L18 SW@SBY100505T-121Y-N/0.3A/120ohm_4 C92
SW@10U/6.3V_6
[email protected]/10V_4
XTALIN XTALOUT
AUX2P AUX2N DDCCLK_AUX3P DDCDATA_AUX3N
TS_VDD
AF29 AG29
GPU_D+ GPU_DT40 TS_VDD
C85
AV33 AU34
DDC2CLK DDC2DATA
SW@27p/50V_4
A
+1.8V_GPU
XTALI_27M XTALO_27M Y1 R58 SW@1M_4 SW@27MHZ
AUX1P AUX1N
DPLL_VDDC
1
+1V_GPU
2
+1.0V(125mA)
C05
SW@27p/50V_4
DDC1CLK DDC1DATA
DPLL_PVDD DPLL_PVSS
AK32 AJ32 AJ33
DPLUS DMINUS
THERMAL
DDCCLK_AUX4P DDCDATA_AUX4N DDCCLK_AUX5P DDCDATA_AUX5N
TS_FDO TSVDD TSVSS
DDC6CLK DDC6DATA NC_DDCCLK_AUX7P NC_DDCDATA_AUX7N
AM26 AN26 AM27 AL27 AM19 AL19 AN20 AM20 AL30 AM30 AL29 AM29
T30 T26
+1.8V_GPU
(1.8V@2mA A2VDDQ)
T28 T22
120 ohm/300mA L48 SW@SBY100505T-121Y-N/0.3A/120ohm_4
A2VDDQ
SW@1U/6.3V_4 C508 C507 [email protected]/10V_4
T34 T24 T32 T33 T35 T29
A
AN21 AM21 AJ30 AJ31 AK30 AK29
T39 T19
Quanta Computer Inc. SW@SEYMOUR_M2
PROJECT : ZQG Size
Document Number
Rev 1A
Seymour-HOST 2/6 Date: 5
4
3
2
Monday, November 01, 2010
Sheet 1
14
of
41
5
4
3
2
1
17 VMB_DQ[63..0]
R160 R146 R114
*SW@240/F_4 L27 SW@240/F_4 N12 *SW@240/F_4 AG12
R155 R150 R48
SW@240/F_4 M12 *SW@240/F_4 M27 *SW@240/F_4 AH12
CLKA1 CLKA1B RASA0B RASA1B CASA0B CASA1B CSA0B_0 CSA0B_1 CSA1B_0 CSA1B_1
MVREFDA MVREFSA
CKEA0 CKEA1
MEM_CALRN0 MEM_CALRN1 MEM_CALRN2
WEA0B WEA1B
MEM_CALRP1 MEM_CALRP0 MEM_CALRP2
MAA0_8 MAA1_8
VMB_MA[13..0]
A32 C32 D23 E22 C14 A14 E10 D9 C34 D29 D25 E20 E16 E12 J10 D7 A34 E30 E26 C20 C16 C12 J11 F8 J21 G19 H27 G27 J14 H14 K23 K19 K20 K17 +1.5V_GPU K24 K27 M13 K16
R174 [email protected]/F_4
K21 J20 K26 L15 H23 J19
C5 C3 E3 E1 F1 F3 F5 G4 H5 H6 J4 K6 K5 L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5 AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6 AG4 AH5 AH6 AJ4 AK3 AF8 AF9 AG8 AG7 AK9 AL7 AM8 AM7 AK1 AL4 AM6 AM1 AN4 AP3 AP1 AP5
MVREFDB MVREFSB C341
[email protected]/10V_4
SW@100/F_4
+1.5V_GPU
L18 L20
CLKA0 CLKA0B
VMB_DQ0 VMB_DQ1 VMB_DQ2 VMB_DQ3 VMB_DQ4 VMB_DQ5 VMB_DQ6 VMB_DQ7 VMB_DQ8 VMB_DQ9 VMB_DQ10 VMB_DQ11 VMB_DQ12 VMB_DQ13 VMB_DQ14 VMB_DQ15 VMB_DQ16 VMB_DQ17 VMB_DQ18 VMB_DQ19 VMB_DQ20 VMB_DQ21 VMB_DQ22 VMB_DQ23 VMB_DQ24 VMB_DQ25 VMB_DQ26 VMB_DQ27 VMB_DQ28 VMB_DQ29 VMB_DQ30 VMB_DQ31 VMB_DQ32 VMB_DQ33 VMB_DQ34 VMB_DQ35 VMB_DQ36 VMB_DQ37 VMB_DQ38 VMB_DQ39 VMB_DQ40 VMB_DQ41 VMB_DQ42 VMB_DQ43 VMB_DQ44 VMB_DQ45 VMB_DQ46 VMB_DQ47 VMB_DQ48 VMB_DQ49 VMB_DQ50 VMB_DQ51 VMB_DQ52 VMB_DQ53 VMB_DQ54 VMB_DQ55 VMB_DQ56 VMB_DQ57 VMB_DQ58 VMB_DQ59 VMB_DQ60 VMB_DQ61 VMB_DQ62 VMB_DQ63
+3V_D
R117 R109
Y12 AA12
[email protected]_4 TESTEN
AD28 AK10 AL10
AL31
R163 [email protected]/F_4
RSVD
SW@SEYMOUR_M2
R172 [email protected]/F_4
R74
R73 *SW@0_4
TP1
MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8 MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12 MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1
WCKB0_0/DQMB_0 WCKB0B_0/DQMB_1 WCKB0_1/DQMB_2 WCKB0B_1/DQMB_3 WCKB1_0/DQMB_4 WCKB1B_0/DQMB_5 WCKB1_1/DQMB_6 WCKB1B_1/DQMB_7 GDDR5/DDR2/GDDR3 EDCB0_0/QSB_0/RDQSB_0 EDCB0_1/QSB_1/RDQSB_1 EDCB0_2/QSB_2/RDQSB_2 EDCB0_3/QSB_3/RDQSB_3 EDCB1_0/QSB_4/RDQSB_4 EDCB1_1/QSB_5/RDQSB_5 EDCB1_2/QSB_6/RDQSB_6 EDCB1_3/QSB_7/RDQSB_7
DDBIB0_0/QSB_0B/WDQSB_0 DDBIB0_1/QSB_1B/WDQSB_1 DDBIB0_2/QSB_2B/WDQSB_2 DDBIB0_3/QSB_3B/WDQSB_3 DDBIB1_0/QSB_4B/WDQSB_4 DDBIB1_1/QSB_5B/WDQSB_5 DDBIB1_2/QSB_6B/WDQSB_6 DDBIB1_3/QSB_7B/WDQSB_7 ADBIB0/ODTB0 ADBIB1/ODTB1 CLKB0 CLKB0B CLKB1 CLKB1B RASB0B RASB1B CASB0B CASB1B CSB0B_0 CSB0B_1 CSB1B_0 CSB1B_1 CKEB0 CKEB1
MVREFDB MVREFSB
*SW@10K_4
+1.5V_GPU +1.5V_GPU
DDR2 GDDR5/GDDR3 DDR3
DQB0_0/DQB_0 DQB0_1/DQB_1 DQB0_2/DQB_2 DQB0_3/DQB_3 DQB0_4/DQB_4 DQB0_5/DQB_5 DQB0_6/DQB_6 DQB0_7/DQB_7 DQB0_8/DQB_8 DQB0_9/DQB_9 DQB0_10/DQB_10 DQB0_11/DQB_11 DQB0_12/DQB_12 DQB0_13/DQB_13 DQB0_14/DQB_14 DQB0_15/DQB_15 DQB0_16/DQB_16 DQB0_17/DQB_17 DQB0_18/DQB_18 DQB0_19/DQB_19 DQB0_20/DQB_20 DQB0_21/DQB_21 DQB0_22/DQB_22 DQB0_23/DQB_23 DQB0_24/DQB_24 DQB0_25/DQB_25 DQB0_26/DQB_26 DQB0_27/DQB_27 DQB0_28/DQB_28 DQB0_29/DQB_29 DQB0_30/DQB_30 DQB0_31/DQB_31 DQB1_0/DQB_32 DQB1_1/DQB_33 DQB1_2/DQB_34 DQB1_3/DQB_35 DQB1_4/DQB_36 DQB1_5/DQB_37 DQB1_6/DQB_38 DQB1_7/DQB_39 DQB1_8/DQB_40 DQB1_9/DQB_41 DQB1_10/DQB_42 DQB1_11/DQB_43 DQB1_12/DQB_44 DQB1_13/DQB_45 DQB1_14/DQB_46 DQB1_15/DQB_47 DQB1_16/DQB_48 DQB1_17/DQB_49 DQB1_18/DQB_50 DQB1_19/DQB_51 DQB1_20/DQB_52 DQB1_21/DQB_53 DQB1_22/DQB_54 DQB1_23/DQB_55 DQB1_24/DQB_56 DQB1_25/DQB_57 DQB1_26/DQB_58 DQB1_27/DQB_59 DQB1_28/DQB_60 DQB1_29/DQB_61 DQB1_30/DQB_62 DQB1_31/DQB_63
WEB0B WEB1B
*SW@0_4
B
C307
R162
MVREFDA MVREFSA
ADBIA0/ODTA0 ADBIA1/ODTA1
19 VMB_MA[13..0]
[email protected]/10V_4
R168 [email protected]/F_4
DDBIA0_0/QSA_0B/WDQSA_0 DDBIA0_1/QSA_1B/WDQSA_1 DDBIA0_2/QSA_2B/WDQSA_2 DDBIA0_3/QSA_3B/WDQSA_3 DDBIA1_0/QSA_4B/WDQSA_4 DDBIA1_1/QSA_5B/WDQSA_5 DDBIA1_2/QSA_6B/WDQSA_6 DDBIA1_3/QSA_7B/WDQSA_7
U15D DDR2 GDDR3/GDDR5 DDR3
VMB_WDQS[7..0]
19 VMB_WDQS[7..0]
R176
+1.5V_GPU
WCKA0_0/DQMA_0 WCKA0B_0/DQMA_1 WCKA0_1/DQMA_2 WCKA0B_1/DQMA_3 WCKA1_0/DQMA_4 WCKA1B_0/DQMA_5 WCKA1_1/DQMA_6 WCKA1B_1/DQMA_7 GDDR5/DDR2/GDDR3 EDCA0_0/QSA_0/RDQSA_0 EDCA0_1/QSA_1/RDQSA_1 EDCA0_2/QSA_2/RDQSA_2 EDCA0_3/QSA_3/RDQSA_3 EDCA1_0/QSA_4/RDQSA_4 EDCA1_1/QSA_5/RDQSA_5 EDCA1_2/QSA_6/RDQSA_6 EDCA1_3/QSA_7/RDQSA_7
G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17
VMB_DM[7..0] VMB_RDQS[7..0]
19 VMB_RDQS[7..0]
SW@100/F_4
C
MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8 MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12 MAA1_5/MAA_13_BA2 MAA1_6/MAA_14_BA0 MAA1_7/MAA_A15_BA1
GDDR5
D
DQA0_0/DQA_0 DQA0_1/DQA_1 DQA0_2/DQA_2 DQA0_3/DQA_3 DQA0_4/DQA_4 DQA0_5/DQA_5 DQA0_6/DQA_6 DQA0_7/DQA_7 DQA0_8/DQA_8 DQA0_9/DQA_9 DQA0_10/DQA_10 DQA0_11/DQA_11 DQA0_12/DQA_12 DQA0_13/DQA_13 DQA0_14/DQA_14 DQA0_15/DQA_15 DQA0_16/DQA_16 DQA0_17/DQA_17 DQA0_18/DQA_18 DQA0_19/DQA_19 DQA0_20/DQA_20 DQA0_21/DQA_21 DQA0_22/DQA_22 DQA0_23/DQA_23 DQA0_24/DQA_24 DQA0_25/DQA_25 DQA0_26/DQA_26 DQA0_27/DQA_27 DQA0_28/DQA_28 DQA0_29/DQA_29 DQA0_30/DQA_30 DQA0_31/DQA_31 DQA1_0/DQA_32 DQA1_1/DQA_33 DQA1_2/DQA_34 DQA1_3/DQA_35 DQA1_4/DQA_36 DQA1_5/DQA_37 DQA1_6/DQA_38 DQA1_7/DQA_39 DQA1_8/DQA_40 DQA1_9/DQA_41 DQA1_10/DQA_42 DQA1_11/DQA_43 DQA1_12/DQA_44 DQA1_13/DQA_45 DQA1_14/DQA_46 DQA1_15/DQA_47 DQA1_16/DQA_48 DQA1_17/DQA_49 DQA1_18/DQA_50 DQA1_19/DQA_51 DQA1_20/DQA_52 DQA1_21/DQA_53 DQA1_22/DQA_54 DQA1_23/DQA_55 DQA1_24/DQA_56 DQA1_25/DQA_57 DQA1_26/DQA_58 DQA1_27/DQA_59 DQA1_28/DQA_60 DQA1_29/DQA_61 DQA1_30/DQA_62 DQA1_31/DQA_63
MEMORY INTERFACE A
C37 C35 A35 E34 G32 D33 F32 E32 D31 F30 C30 A30 F28 C28 A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13 J13 H11 G10 G8 K9 K10 G9 A8 C8 E8 A6 C6 E6 A5
DDR2 GDDR5/GDDR3 DDR3
GDDR5
19 VMB_DM[7..0]
MEMORY INTERFACE B
19 VMB_DQ[63..0] U15C DDR2 GDDR3/GDDR5 DDR3
TESTEN CLKTESTA CLKTESTB
MAB0_8 MAB1_8
DRAM_RST
SW@SEYMOUR_M2
P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9
VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_BA2 VMB_BA0 VMB_BA1
H3 H1 T3 T5 AE4 AF5 AK6 AK5
VMB_DM0 VMB_DM1 VMB_DM2 VMB_DM3 VMB_DM4 VMB_DM5 VMB_DM6 VMB_DM7
F6 K3 P3 V5 AB5 AH1 AJ9 AM5
VMB_RDQS0 VMB_RDQS1 VMB_RDQS2 VMB_RDQS3 VMB_RDQS4 VMB_RDQS5 VMB_RDQS6 VMB_RDQS7
QSB[7..0]
G7 K1 P1 W4 AC4 AH3 AJ8 AM3
VMB_WDQS0 VMB_WDQS1 VMB_WDQS2 VMB_WDQS3 VMB_WDQS4 VMB_WDQS5 VMB_WDQS6 VMB_WDQS7
QSB#[7..0]
D
VMB_BA2 19 VMB_BA0 19 VMB_BA1 19
C
T7 W7
VMB_ODT0 19 VMB_ODT1 19
L9 L8
VMB_CLKP0 VMB_CLKN0
AD8 AD7
VMB_CLKP1 VMB_CLKN1
T10 Y10
VMB_RAS0# VMB_RAS1#
W10 AA10
VMB_CAS0# VMB_CAS1#
P10 L10
VMB_CS0#
AD10 AC10
VMB_CS1#
U10 AA11
VMB_CKE0 VMB_CKE1
N10 AB11
VMB_WE0# VMB_WE1#
T8 W8
VMB_MA13
VMB_CLKP0 VMB_CLKN0
19 19
VMB_CLKP1 19 VMB_CLKN1 19 VMB_RAS0# VMB_RAS1#
19 19
VMB_CAS0# VMB_CAS1#
19 19
VMB_CS0#
19
VMB_CS1#
19
VMB_CKE0 VMB_CKE1
19 19
VMB_WE0# VMB_WE1#
19 19
Rb
Ra
R47
R41
SW@10_4
SW@51_4
AH11
MEM_RST# 19
C46
R51
*SW@68p/50V_4
[email protected]_4
C42 SW@150P/25V_4
Rc
C
C342
[email protected]/10V_4
stuff
SW@100/F_4
MEM_CALRNP1
R177
[email protected]/10V_4
C309
R156
SW@100/F_4
For PARK
MEM_CALRNP0
B
C
Ra
Rb
Rc
120pF
51 ohm
10 ohm
5K ohm
MEM_CALRNP2
DDR3/GDDR3 Memory Stuff Option GDDR5
GDDR3
DDR3
1.5V
1.8V/1.5V
1.5V
Ra
40.2R
40.2R
40.2R
Rb
100R
100R
100R
+1.5V_VGA A
A
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
Rev 1A
Seymour-MEM 3/6 Date: 5
4
3
2
Monday, November 01, 2010
Sheet 1
15
of
41
5
4
3
2
1
18
U15F U15E MEM I/O PCIE
C285
C317 C586 C261 C591 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6
D
C139
C325 C327 C243 C331 C314 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
C312
C300 C333 C328 C215 C105 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
C276
C332 C313 C308 C330 [email protected]/10V_4 [email protected]/10V_4 SW@1U/6.3V_4 [email protected]/10V_4 [email protected]/10V_4
SW@SBY100505T-121Y-N/0.3A/120ohm_4
VDDC_CT
AF26 AF27 AG26 AG27
C58
C61 C66 SW@1U/6.3V_4 SW@10U/6.3V_6 [email protected]/10V_4
C
I/O
AF23 AF24 AG23 AG24
+3V_D C106
C118 C101 C102 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@10U/6.3V_6 SW@1U/6.3V_4
C55
C57 [email protected]/10V_4 SW@1U/6.3V_4
+1.8V_GPU
120 ohm/300mA (1.8V@40mA PCIE_PVDD) L50 SW@SBY100505T-121Y-N/0.3A/120ohm_4
B
T86 T92
M20 M21
T57 T60
V12 U12
VDDR4#1 VDDR4#2 VDDR4#3 VDDR4#6
NC_VDDRHA NC_VSSRHA NC_VDDRHB NC_VSSRHB
PLL PCIE_PVDD
AB37
MPV18
H7 H8
SPV18
AM10
C543 C549 SW@1U/6.3V_4 SW@10U/6.3V_6 [email protected]/10V_4
L31
VDDR4#4 VDDR4#5 VDDR4#7 VDDR4#8
AD12 AF11 AF12 AG11
C536
+1.8V_GPU
VDDR3#1 VDDR3#2 VDDR3#3 VDDR3#4
AF13 AF15 AG13 AG15
120 ohm/300mA L11 SW@SBY100505T-121Y-N/0.3A/120ohm_4 VDDR4
120 ohm/300mA (1.8V@150mA MPV18) SW@SBY100505T-121Y-N/0.3A/120ohm_4
SPV10
PCIE_PVDD MPV18#1 MPV18#2
AN9
L10
VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8 VDDCI#9 VDDCI#10 VDDCI#11 VDDCI#12 VDDCI#13 VDDCI#14 ISOLATED VDDCI#15 CORE I/O VDDCI#16 VDDCI#17 VDDCI#18 VDDCI#19 VDDCI#20 VDDCI#21 VDDCI#22
SPV10
AN10
SPVSS
C324 C329 SW@1U/6.3V_4 SW@10U/6.3V_6 [email protected]/10V_4
+1.8V_GPU
VOLTAGE SENESE
120 ohm/300mA (1.8V@75mA SPV18) SW@SBY100505T-121Y-N/0.3A/120ohm_4 T43 C49 [email protected]/10V_4 SW@10U/6.3V_6
AF28
FB_VDDC
C45
+1V_GPU
L9
T45
AG28
T44
AH29
FB_VDDCI FB_GND
120 ohm/300mA (1.0V@120mA SPV10) SW@SBY100505T-121Y-N/0.3A/120ohm_4
C48 [email protected]/10V_4 SW@10U/6.3V_6
VDDC#1 VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8 VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15 VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23 VDDC#24 VDDC#25 VDDC#26 VDDC#27 VDDC#28 VDDC#29 VDDC#30 VDDC#31 VDDC#32 VDDC#33 VDDC#34 VDDC#35 VDDC#36 VDDC#37 VDDC#38 VDDC#39 VDDC#40 VDDC#41 VDDC#42 VDDC#43 VDDC#44 VDDC#45 VDDC#46 VDDC#47 VDDC#48 VDDC#49 VDDC#50 VDDC#51 VDDC#52 VDDC#53 VDDC#54 VDDC#55 VDDC#56 VDDC#57 VDDC#58
SPV18
C337
PCIE_VDDR_1.8
AA31 AA32 AA33 AA34 V28 W29 W30 Y31
(1.8V@400mA PCIE_VDDR)
L23
+1.8V_GPU 180 ohm/1.5A SW@HCB1608KF-181T15/180ohm/1.5A_6
C44
C161
C159 C158 C212 C162 C160 C186 C172 [email protected]/10V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@10U/6.3V_6 [email protected]/10V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28
+1V_GPU
C06
([email protected] PCIE_VDDC)
C304
C287 C278 C254 C288 C297 C222 C306 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@10U/6.3V_6 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
+VGPU_CORE
AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 AH27 AH28 M26 N24 N27 R18 R21 R23 R26 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28
C277
C114 C200 C143 C211 C182 C140 C241 C204 C151 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
C218 C171 C103 C177 C121 C267 C227 C173 C256 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
C263
C184 C124 C281 C150 C152 C258 C210 C120 C146 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
C104
C107 C180 C220 C265 C111 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6
Ra should be removed by PX 4.0 ( BACO mode) R31
Ra
+VGPU_CORE
SWS@0_4
BIF_VDDC
55mA @ 1V in BCAO mode
AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13
C283
C257 C286 C226 C292 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 +VGPU_CORE
+3V C209 C264 C295 C302 C253 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
R35
2 *SW@0_6 C157
C193 C293 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6
Q13 SW@AO3413
+3V
+3V
R52 SW@10K_4
+1.8V_GPU
2
BACO reference schematics for detail
B
PowerXpress control signal for Park only If not used, can be disconnected. PX_EN = LOW, turn on PX_EN = HIGH, turn off PX_EN is used to turn ON/OFF some regulators for PowerXpress mode. An output high ‘3.3V’ will turn the regulators OFF. An output low ‘0V’ will turn the regulators ON. PX_EN outputs low (0V) by default. If this signal is unused, it can be NC (not connected) or connected to ground.
*SW@0_6 Q14 *[email protected]/10V_4
R40 *SW@0_4
2
SW@DTC144EUA Q15
C41
1A
Quanta Computer Inc.
+3V_D C37
C40
C38
*SW@1u/6.3V_4 *[email protected]/6.3V_6 *[email protected]/10V_4
PROJECT : ZQG Size
Document Number
Rev 1A
Seymour (PWR/GND)4/6 4
3
17
*SW@0_4
A
Date: 5
PX_EN R82
2 R38 SW@0_4
SW@1U/6.3V_4 Q16 SW@PDTC143TT
A39 AW1 AW39
C
R37 dGPU_PWREN
2 +1.5V_GPU
C39 [email protected]/10V_4
VSS_MECH#1 VSS_MECH#2 VSS_MECH#3
D
SW@0_6
3
Q17 SW@2N7002K
GND GND#100 GND#101 GND#102 GND#103 GND#104 GND#105 GND#106 GND#107 GND#108 GND#109 GND#110 GND#111 GND#112 GND#113 GND#114 GND#115 GND#116 GND#117 GND#118 GND#119 GND#120 GND#121 GND#122 GND#123 GND#124 GND#125 GND#126 GND#127 GND#128 GND#129 GND#130 GND#131 GND#132 GND#133 GND#134 GND#135 GND#136 GND#137 GND#138 GND#139 GND#140 GND#141 GND#142 GND#143 GND#144 GND#145 GND#146 GND#147 GND#148 GND#149 GND#150 GND#151 GND#153 GND#154 GND#155 GND#156 GND#157 GND#158 GND#159 GND#160 GND#161 GND#163 GND#164 GND#165 GND#166 GND#167 GND#168 GND#169 GND#170 GND#171 GND#172 GND#173 GND#174 GND#175 GND#152 GND#162 SW@SEYMOUR_M2
A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 AL21 AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 AW34 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13
3
D4
R42 SW@10K_4 38,39
1
*SW@BAS316
>1mS delay is required between all MXM power rail stable and MXM_PWREN(enables the module internal power)
dGPU_PWREN
1
D5
3
8 dGPU_VRON
SW@BAS316
R39 [email protected]_4
8
1
9 dGPU_PWR_EN
dGPU_PWROK
3
R36 [email protected]_4
F15 F17 F19 F21 F23 F25 F27 F29 F31 F33 F7 F9 G2 G6 H9 J2 J27 J6 J8 K14 K7 L11 L17 L2 L22 L24 L6 M17 M22 M24 N16 N18 N2 N21 N23 N26 N6 R15 R17 R2 R20 R22 R24 R27 R6 T11 T13 T16 T18 T21 T23 T26 U15 U17 U2 U20 U22 U24 U27 U6 V11 V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y22 Y24 Y27 U13 V13
GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8 GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55 GND#56 GND#57 GND#58 GND#59 GND#60 GND#61 GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86 GND#87 GND#88 GND#89 GND#90 GND#91 GND#92 GND#93 GND#94 GND#95 GND#96 GND#97 GND#98 GND#99
R32
dGPU_VRON 2ms
C33
GPU +3V_D power
+3V
dGPU_PWREN
C32
SW@1U/6.3V_4 SW@10U/6.3V_6 [email protected]/10V_4
+3V
GPU all PWROK
1A +3V_D_EXT
C35
Change from 100K to 4.7K
PCIE_VSS#1 PCIE_VSS#2 PCIE_VSS#3 PCIE_VSS#4 PCIE_VSS#5 PCIE_VSS#6 PCIE_VSS#7 PCIE_VSS#8 PCIE_VSS#9 PCIE_VSS#10 PCIE_VSS#11 PCIE_VSS#12 PCIE_VSS#13 PCIE_VSS#14 PCIE_VSS#15 PCIE_VSS#16 PCIE_VSS#17 PCIE_VSS#18 PCIE_VSS#19 PCIE_VSS#20 PCIE_VSS#21 PCIE_VSS#22 PCIE_VSS#23 PCIE_VSS#24 PCIE_VSS#25 PCIE_VSS#26 PCIE_VSS#27 PCIE_VSS#28 PCIE_VSS#29 PCIE_VSS#30 PCIE_VSS#31 PCIE_VSS#32 PCIE_VSS#33 PCIE_VSS#34 PCIE_VSS#35
C126
SW@SEYMOUR_M2
GPU power enable A
AB39 E39 F34 F39 G33 G34 H31 H34 H39 J31 J34 K31 K34 K39 L31 L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39 W31 W34 Y34 Y39
(30A or more) CORE
VDD_CT#1 VDD_CT#2 VDD_CT#3 VDD_CT#4
(3.3V@60mA))
+1.8V_GPU
PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8 PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12
LEVEL TRANSLATION
(1.8V@110mA VDD_CT)
L12
PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8
POWER
+1.8V_GPU
VDDR1#1 VDDR1#2 VDDR1#3 VDDR1#4 VDDR1#5 VDDR1#6 VDDR1#7 VDDR1#8 VDDR1#9 VDDR1#10 VDDR1#11 VDDR1#12 VDDR1#13 VDDR1#14 VDDR1#15 VDDR1#16 VDDR1#17 VDDR1#18 VDDR1#19 VDDR1#20 VDDR1#21 VDDR1#22 VDDR1#23 VDDR1#24 VDDR1#25 VDDR1#26 VDDR1#27 VDDR1#28 VDDR1#29 VDDR1#30 VDDR1#31 VDDR1#32 VDDR1#33 VDDR1#34
1
AC7 AD11 AF7 AG10 AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10 J7 J9 K11 K13 K8 L12 L16 L21 L23 L26 L7 M11 N11 P7 R11 U11 U7 Y11 Y7
3
For DDR3, MVDDQ = 1.5V (1.5A)
1
+1.5V_GPU
2
Monday, November 01, 2010
Sheet 1
16
of
41
5
4
3
2
1
19
U15H DP C/D POWER
DPAB_VDD18
AP20 AP21
DP A/B POWER
DPAB_VDD18
DPA_VDD18#1 DPA_VDD18#2
AN24 AP24
DPC_VDD10#1 DPC_VDD10#2
DPA_VDD10#1 DPA_VDD10#2
AP31 AP32
DPC_VSSR#1 DPC_VSSR#2 DPC_VSSR#3 DPC_VSSR#4 DPC_VSSR#5
DPA_VSSR#1 DPA_VSSR#2 DPA_VSSR#3 DPA_VSSR#4 DPA_VSSR#5
AN27 AP27 AP28 AW24 AW26
DPD_VDD18#1 DPD_VDD18#2
DPB_VDD18#1 DPB_VDD18#2
AP25 AP26
DPC_VDD18#1 DPC_VDD18#2
DPAB_VDD10
AN17 AP16 AP17 AW14 AW16 DPAB_VDD18
DPAB_VDD10
L47
R92
AP14 AP15
SW@150/F_4 DPCD_CALR
C07
DPD_VDD10#1 DPD_VDD10#2
+1V_GPU
(1.0V@220mA DPAB_VDD10)
AN33 AP33
DPB_VDD10#1 DPB_VDD10#2
AW18
DPB_VSSR#1 DPB_VSSR#2 DPB_VSSR#3 DPB_VSSR#4 DPB_VSSR#5
DPCD_CALR
DPAB_CALR
C506 SW@1U/6.3V_4
C504 [email protected]/10V_4
DP E/F POWER DPE_VDD18#1 DPE_VDD18#2
AL33 AM33
AN34 AP39 AR39 AU37 AW35
+1V_GPU L8
SW@BLM15BB121SS1
C43 SW@10U/6.3V_6
C50 SW@1U/6.3V_4
AW28
DPAB_CALR R72
SW@150/F_4
AU28 AV27
DPE_VDD10#1 DPE_VDD10#2
DPB_PVDD DPB_PVSS
DPE_VSSR#1 DPE_VSSR#2 DPE_VSSR#3 DPE_VSSR#4 DPE_VSSR#5
DPC_PVDD DPC_PVSS
AF34 AG34
AV19 AR18 DPEF_VDD18
AM37 AN38
DPE_PVDD DPE_PVSS
DPEF_VDD10
DPF_VDD10#1 DPF_VDD10#2
AL38 AM35
NC_DPF_PVDD NC_DPF_PVSS AF39 AH39 AK39 AL34 AM34
SW@150/F_4 DPEF_CALR
AU18 AV17
DPF_VDD18#1 DPF_VDD18#2
AK33 AK34
C
AV29 AR28
DPD_PVDD DPD_PVSS
C47 [email protected]/10V_4
R313
SW@BLM15BB121SS1
AN29 AP29 AP30 AW30 AW32
DP PLL POWER DPA_PVDD DPA_PVSS
DPEF_VDD18
DP mode (1.0V@220mA DPEF_VDD10) LVDS mode (1.0V@240mA DPEF_VDD10)
L16 C76 SW@10U/6.3V_6
DPEF_VDD10
C
C07
C79 SW@1U/6.3V_4
DPAB_VDD18
AH34 AJ34
C505 SW@10U/6.3V_6
DPD_VSSR#1 DPD_VSSR#2 DPD_VSSR#3 DPD_VSSR#4 DPD_VSSR#5
DPEF_VDD18
SW@BLM15BB121SS1
C64 SW@10U/6.3V_6
DPAB_VDD10
AN19 AP18 AP19 AW20 AW22
+1.8V_GPU
SW@BLM15BB121SS1
D
C73 [email protected]/10V_4
DP mode (1.8V@300mA DPEF_VDD18) LVDS mode (1.8V@440mA DPEF_VDD18)
C78 SW@1U/6.3V_4
L15
DPAB_VDD18
AP22 AP23
NOTE : DPD is NA on Park,Robson and Seymour.
C72 [email protected]/10V_4
DPAB_VDD10
AP13 AT13 D
+1.8V_GPU
(1.8V@300mA DPAB_VDD18)
DPF_VSSR#1 DPF_VSSR#2 DPF_VSSR#3 DPF_VSSR#4 DPF_VSSR#5
AM39
DPEF_CALR SW@SEYMOUR_M2
B
B
Support BACO Mode
+5V +3V
C07
+5V
Q4 PX4@2N7002
Q8 PX4@2N7002
C29 R34 PX4@1K_4
[email protected]/10V_4
PX_EN## PX_EN#
2
38,39 PG_GPUIO_EN
4 BACO_EN
3
PX_EN#
1
BIF_VDDC
3
3
U4 PX4@TC7SH08FU
+3V
Q6
2
Q11 PX4@2N7002 Q12
2
+VGPU_CORE
1
Q10 PX4@2N7002
3
3
1
[email protected]/10V_4
PX4@2N7002
1
R29
1
5
PX4@2N7002
PX_EN##
BIF_VDDC C36 PX4@10U/6.3VS_8
2
C673
2
PX4@10K_4
3
1
+3V
R28
1
3
PX_MODE 38,39 SB_PWRGD_IN
+1V_GPU
2
R33 PX4@1K_4
2
5
BACO MODE : Board ID / BACO part / Del Ra
2 R27 A
2
PX_EN
1. No BACO Support :BIF_VDDC shorts with VDDC (Install Ra) 2. BACO Support: Refer to the BACO reference schematics/Application note for detail about BIF_VDDC Rail if BACO is Supported (Uninstall Ra)
U25 PX4@TC7SH08FU
R25 Q5
Note1.
PX_MODE 38,39
1 3
*SPE@0_4
3
PX_MODE
4 PX4@0_4
A
C17
16
*SPE@0_4
R26
1
PX4@2N7002
Quanta Computer Inc.
[email protected]
PX_EN = 0, for Normal Operation PX_EN = 1, for BACO MODE
PROJECT : ZQG Size
Document Number
Rev 1A
Seymour (DP_PWR/GND)5/6 Date: 5
4
3
2
Monday, November 01, 2010
Sheet 1
17
of
41
5
4
3
Memory Aperture size
PIN STRAPS
D
GPU_GPIO13 GPU_GPIO12
14
GPU_GPIO11
14
GPU_GPIO0
14
GPU_GPIO1
R77
*SW@10K/F_4
R78
*SW@10K/F_4
R93
SW@10K/F_4
R91
*SW@10K/F_4
R81
*SW@10K/F_4
000
128MB
001
256MB
010
64MB
011
32MB
STRAPS
PIN
DESCRIPTION OF DEFAULT SETTINGS
GPIO0
0 = 50% TX OUTPUT SWING 1 = FULL TX OUTPUT SWING
0
TX_DEEMPH_EN
GPIO1
PCIE TRANSMITTER DE-EMPHASIS ENABLED 0 = TX DE-EMPHASIS DISABLED 1 = TX DE-EMPHASIS ENABLED ENABLE EXTERNAL BIOS ROM 0 = DISABLE 1 = ENABLE
0
BIOS_ROM_EN
14 GPIO4_SMBCLK
GPU_GPIO2
14
EXT_HSYNC
14
EXT_VSYNC
*SW@10K/F_4
GPIO_22_ROMCSB
ROM Table R75
EXT_VSYNC
Discription
*SW@10K/F_4
R112
V2SYNC
ROMIDCFG(2:0)
GPIO[13:11]
BIF_GEN2_EN_A
GPIO2
GPIO_8_ROMSO H2SYNC GPIO_21_BB_EN
GPIO8 H2SYNC GPIO21
AUD[1]
HSYNC
AUD[0]
VSYNC
REMARK
D
0
SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT NUMONYX M25P10A : 101
000
0 = PCIE DEVICE AS 2.5GT/S CAPABLE 1 = PCIE DEVICE AS 5GT/S CAPABLE
0
Reserved Only
0
See ROM table
*SW@10K/F_4
EXT_HSYNC
14 SIN_GPIO9 14
*SW@10K/F_4
R64 R57
14 SCS#_GPIO22 14
R83
DEFAULT
TX_PWRS_ENB
C02 : to slove the Power DVD issue , setting size to 256MB 14 GPIO3_SMBDAT
20
CONFIGURATION STRAPS
GPIO[13:11] Size
14
1
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET
+3V_D 14
2
*SW@10K/F_4
R118
*SW@10K/F_4
R56
*SW@10K/F_4
R110
*SW@10K/F_4
C
0 0 1 1
No Audio
0 1 0 1
Any one by dectec
AUD[1:0] 00: NO AUDIO FUNCTION. 01: AUDIO FOR DISPLAYPORT AND HDMI IF ADAPTER IS DETECTED. 10: AUDIO FOR DISPLAYPORT ONLY.
DP only
00
See Audio table
11: AUDIO FOR BOTH DISPLAYPORT AND HDMI.
Both DP & HDMI
GPIO_9_ROMSI
C08 : to slove the HDMI issue , remove R112,R118 from BOMs
0 = VGA controller capacity enable
GPIO9
VIP_DEVICE_STRAP_ENA
V2SYNC
0
0 = DRIVER would ignore the value sample on VHAD_0 during RESET.
C
0
DDR3 Memory Aperture size Vendor
STN B/S P/N
RAM_STRAP2 DVPDATA_2
RAM_STRAP1
RAM_STRAP0 DVPDATA_0
DVPDATA_1
ZQE/G
AKD5LZWTW05 (64M*16)
1GB ( 900 Mhz)
1
1
0
V
H5TQ1G63BFR-12C
AKD5LZGTW04 (64M*16)
1GB ( 800 Mhz)
1
0
0
V
H5TQ2G63BFR-12C
AKD5MGGTW03 (128M*16)
2GB
1
1
1
V
K4W1G1646G-BC11
AKD5EGGT503 (64M*16)
1GB
0
1
0
Samsung K4W1G1646E-HC12
AKD5LGGT506 (64M*16)
0
0
0
0
0
1
K4W2G1646B-HC12
Thermal Sensor
Total Memory Size
H5TQ1G63DFR-11C Hynix B
Vendor P/N
AKD5MGGT500
1GB ( 800 Mhz) 2GB
B
V
+3V_D_EXT
+3V_D_EXT R80
R94
SW@10K_4
SW@10K_4
C74
+1.8V_GPU
[email protected]/10V_4
U5 A
31 MXM_SMCLK12
8
31 MXM_SMDATA12
7
14 ALT#_GPIO17
6
31 VGA_THERM#
4
SCLK
VCC
SDA
DXP
ALERT#
DXN
OVERT#
GND
14 RAM_STRAP2
1 2
C65
3
[email protected]/50V_4
5
GPU_D+
14
GPU_D-
14
14 RAM_STRAP1
R44
SWS@10K/F_4
R50
*SWS@10K/F_4
R46
SWS@10K/F_4
R45
*SWS@10K/F_4
R43
*SWS@10K/F_4
R49
SWS@10K/F_4
RAM_STRAP2 SET DDR3 Vendor RAM_STRAP[1:0] SET SIZE.
Quanta Computer Inc.
SW@G780-1P81U(MSOP)
Address ID: 98H 14 RAM_STRAP0
PROJECT : ZQG Size
4
3
Document Number
Rev 1A
Seymour Strip/Thermal 6/6 Date:
5
A
2
Sheet
Monday, November 01, 2010 1
18
of
41
5
4
15 VMB_RDQS[7..0] 15 VMB_WDQS[7..0]
VMB_RDQS[7..0]
QSA[7..0]
VMB_WDQS[7..0]
QSA#[7..0]
VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_MA13
15 15 15
VMB_BA0 VMB_BA1 VMB_BA2
15 15 15
VMB_CLKP0 VMB_CLKN0 VMB_CKE0 VMB_ODT0 VMB_CS0# VMB_RAS0# VMB_CAS0# VMB_WE0#
U7 M8 H1
VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_MA13
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7
VMB_BA0 VMB_BA1 VMB_BA2
M2 N8 M3
VMB_CLKP0 VMB_CLKN0 VMB_CKE0
J7 K7 K9
VMB_ODT0 VMB_CS0# VMB_RAS0# VMB_CAS0# VMB_WE0#
K1 L2 J3 K3 L3
VMB_RDQS0 VMB_RDQS3
F3 C7
VMB_DM0 VMB_DM3
E7 D3
VMB_WDQS0 VMB_WDQS3
G3 B7
MEM_RST#
T2
C
15
21
U6
VREFC_VMB1 VREFD_VMB1
15 15 15 15 15
1
VMB_DM[7..0]
15 VMB_DM[7..0]
15 15 15 15 15 15 15 15 15 15 15 15 15 15
2
CHANNEL B: 512MB DDR3 (64M*16*4pcs)
VMB_DQ[63..0]
15 VMB_DQ[63..0]
D
3
MEM_RST#
VMB_ZQ1
L8
VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 BA0 BA1 BA2
CK CK CKE ODT CS RAS CAS WE DQSL DQSU DML DMU DQSL DQSU
RESET ZQ
R166 SW@240/F_4 J1 L1 J9 L9
NC#J1 NC#L1 NC#J9 NC#L9
U13
U19 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
E3 F7 F2 F8 H3 H8 G2 H7
VMB_DQ5 VMB_DQ3 VMB_DQ4 VMB_DQ2 VMB_DQ7 VMB_DQ0 VMB_DQ6 VMB_DQ1
D7 C3 C8 C2 A7 A2 B8 A3
VMB_DQ24 VMB_DQ31 VMB_DQ25 VMB_DQ29 VMB_DQ26 VMB_DQ30 VMB_DQ28 VMB_DQ27
VREFC_VMB2 VREFD_VMB2
0 3
M8 H1
VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_MA13
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7
VMB_BA0 VMB_BA1 VMB_BA2
M2 N8 M3
VMB_CLKP0 VMB_CLKN0 VMB_CKE0
J7 K7 K9
+1.5V_GPU VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9
B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.5V_GPU A1 A8 C1 C9 D2 E9 F1 H2 H9
VMB_ODT0 VMB_CS0# VMB_RAS0# VMB_CAS0# VMB_WE0#
K1 L2 J3 K3 L3
VMB_RDQS1 VMB_RDQS2
F3 C7
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
VMB_DM1 VMB_DM2
E7 D3
VMB_WDQS1 VMB_WDQS2
G3 B7
MEM_RST#
T2
VMB_ZQ2
B1 B9 D1 D8 E2 E8 F9 G1 G9
L8
VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 BA0 BA1 BA2
CK CK CKE ODT CS RAS CAS WE DQSL DQSU DML DMU DQSL DQSU
RESET ZQ
R378 SW@240/F_4 J1 L1 J9 L9
100-BALL SDRAM DDR3 SWS@VRAM _DDR3
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
NC#J1 NC#L1 NC#J9 NC#L9
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
E3 F7 F2 F8 H3 H8 G2 H7
VMB_DQ9 VMB_DQ13 VMB_DQ11 VMB_DQ12 VMB_DQ10 VMB_DQ14 VMB_DQ8 VMB_DQ15
D7 C3 C8 C2 A7 A2 B8 A3
VMB_DQ21 VMB_DQ19 VMB_DQ23 VMB_DQ17 VMB_DQ20 VMB_DQ16 VMB_DQ22 VMB_DQ18
1
2
VREFC_VMB3 VREFD_VMB3
M8 H1
VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_MA13
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7
VMB_BA0 VMB_BA1 VMB_BA2
M2 N8 M3
VMB_CLKP1 VMB_CLKN1 VMB_CKE1
J7 K7 K9
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
E3 F7 F2 F8 H3 H8 G2 H7
VMB_DQ63 VMB_DQ57 VMB_DQ60 VMB_DQ58 VMB_DQ62 VMB_DQ59 VMB_DQ61 VMB_DQ56
VREFC_VMB4 VREFD_VMB4
M8 H1
VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_MA13
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7
D7 C3 C8 C2 A7 A2 B8 A3
VMB_DQ34 VMB_DQ37 VMB_DQ33 VMB_DQ36 VMB_DQ32 VMB_DQ39 VMB_DQ35 VMB_DQ38
VMB_BA0 VMB_BA1 VMB_BA2
M2 N8 M3
VMB_CLKP1 VMB_CLKN1 VMB_CKE1
J7 K7 K9
A1 A8 C1 C9 D2 E9 F1 H2 H9
VMB_ODT1 VMB_CS1# VMB_RAS1# VMB_CAS1# VMB_WE1#
K1 L2 J3 K3 L3
VMB_RDQS6 VMB_RDQS5
F3 C7
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
VMB_DM6 VMB_DM5
E7 D3
VMB_WDQS6 VMB_WDQS5
G3 B7
MEM_RST#
T2
7 4
+1.5V_GPU
VREFCA VREFDQ
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15
E3 F7 F2 F8 H3 H8 G2 H7
VMB_DQ51 VMB_DQ52 VMB_DQ50 VMB_DQ53 VMB_DQ49 VMB_DQ54 VMB_DQ48 VMB_DQ55
D7 C3 C8 C2 A7 A2 B8 A3
VMB_DQ45 VMB_DQ41 VMB_DQ47 VMB_DQ42 VMB_DQ44 VMB_DQ40 VMB_DQ46 VMB_DQ43
6 D
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
5
+1.5V_GPU
+1.5V_GPU VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9
B2 D9 G7 K2 K8 N1 N9 R1 R9
15 15 15
VMB_CLKP1 VMB_CLKN1 VMB_CKE1
15 15 15 15 15
VMB_ODT1 VMB_CS1# VMB_RAS1# VMB_CAS1# VMB_WE1#
BA0 BA1 BA2
CK CK CKE
B2 D9 G7 K2 K8 N1 N9 R1 R9
VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9
+1.5V_GPU
BA0 BA1 BA2
VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9
CK CK CKE
B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.5V_GPU
+1.5V_GPU A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
VMB_ODT1 VMB_CS1# VMB_RAS1# VMB_CAS1# VMB_WE1#
K1 L2 J3 K3 L3
VMB_RDQS7 VMB_RDQS4
F3 C7
VMB_DM7 VMB_DM4
E7 D3
VMB_WDQS7 VMB_WDQS4
G3 B7
MEM_RST#
T2
VMB_ZQ3
B1 B9 D1 D8 E2 E8 F9 G1 G9
L8
ODT CS RAS CAS WE DQSL DQSU DML DMU DQSL DQSU
RESET ZQ
R99 SW@240/F_4 J1 L1 J9 L9
NC#J1 NC#L1 NC#J9 NC#L9
VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9
VMB_ZQ4
B1 B9 D1 D8 E2 E8 F9 G1 G9
VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9
L8
J1 L1 J9 L9
Group-B0 VREF
VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9
DQSL DQSU DML DMU
VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9
DQSL DQSU
RESET ZQ
VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9
NC#J1 NC#L1 NC#J9 NC#L9
A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
C
B1 B9 D1 D8 E2 E8 F9 G1 G9
100-BALL SDRAM DDR3 SWS@VRAM _DDR3
TOP Up
TOP Down
ODT CS RAS CAS WE
R363 SW@240/F_4
100-BALL SDRAM DDR3 SWS@VRAM _DDR3
100-BALL SDRAM DDR3 SWS@VRAM _DDR3
BOT Down
VREFCA VREFDQ
BOT Up
Group-B1 VREF +1.5V_GPU
B
+1.5V_GPU
R159 [email protected]/F_4
R178 [email protected]/F_4
VREFC_VMB1 R153
C299 [email protected]/10V_4 [email protected]/F_4
+1.5V_GPU
+1.5V_GPU
R372 [email protected]/F_4
VREFD_VMB1
R396 [email protected]/F_4
VREFC_VMB2
R167
C335 [email protected]/10V_4 [email protected]/F_4
R374
C565 [email protected]/10V_4 [email protected]/F_4
+1.5V_GPU
R106 [email protected]/F_4
VREFD_VMB2 R392
C594 [email protected]/10V_4 [email protected]/F_4
R104
C95 [email protected]/10V_4 [email protected]/F_4
+1.5V_GPU
R343 [email protected]/F_4
VREFC_VMB3
Group-B0 decoupling CAP
MEM_B0 CLK
+1.5V_GPU
R365 [email protected]/F_4
VREFD_VMB3 R346
C522 [email protected]/10V_4 [email protected]/F_4
+1.5V_GPU
R95 [email protected]/F_4
VREFC_VMB4
VREFD_VMB4
R364
C529 [email protected]/10V_4 [email protected]/F_4
Group-B1 decoupling CAP
+1.5V_GPU
B
R98
C82 [email protected]/10V_4 [email protected]/F_4
MEM_B1 CLK
+1.5V_GPU VMB_CLKP1
VMB_CLKP0
VMB_CLKN1 C593
C561 C596 C589 C595 C343 C119 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
VMB_CLKN0 R170
R173 [email protected]/F_4
C81
C176 C509 C142 C538 C77 C71 C91 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
R358
R356 [email protected]/F_4
[email protected]/F_4 +1.5V_GPU
+1.5V_GPU
[email protected]/F_4 C524 [email protected]/16V_4
A
C566 C339 [email protected]/16V_4
C110 C347 C344 C305 C576 C345 C137 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
+1.5V_GPU
C323 SW@10U/6.3V_6
C109
C51 C219 C69 C115 C100 C97 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
A
+1.5V_GPU
C348 C553 C557 C581 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6
C52 SW@10U/6.3V_6
Quanta Computer Inc.
C298 C545 C248 C547 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6
PROJECT : ZQG Size
Document Number
Rev 1A
MEMORY 2 channel B Date: 5
4
3
2
Monday, November 01, 2010
Sheet 1
19
of
41
2
3
4
5
6
OPTION SIGNAL FROM NB to LVDS/CRT for UMA
CRT
7
30V/ 1A
+5V
F1
C560
30V/ 0.5A
2
CRTVDD5_F
1
D21 2 B0520WS-7-F
8
.22u/6.3V_4 CRTVDD5
1
16
1
SMD1206P100TF INT_DDCCLK INT_DDCDATA
4 INT_DDCCLK 4 INT_DDCDATA
INT_CRT_HSYNC INT_CRT_VSYNC
4 INT_CRT_HSYNC 4 INT_CRT_VSYNC
INT_CRT_RED
L28
BLM18BA470SN1_6
CRT_R1
INT_CRT_GRE
L27
BLM18BA470SN1_6
CRT_G1
INT_CRT_BLU
L26
BLM18BA470SN1_6
CRT_B1
A
R136
R141
R138
C240
C216
C242
C282
C279
C294
INT_CRT_RED
4 INT_CRT_RED
150/F_4
150/F_4
150/F_4
10P/50V_4
10P/50V_4
10P/50V_4
10P/50V_4
10P/50V_4
CN12 CRT
6 1 7 2 8 3 9 4 10 5
11
CRT_11
12
DDCDAT_1
13
CRTHSYNC
14
CRTVSYNC
15
DDCCLK_1
T68
A
10P/50V_4
17
INT_CRT_GRE
4 INT_CRT_GRE
INT_CRT_BLU
4 INT_CRT_BLU
+3V
+3V
U16 CRTVDD5
1
C239 .22u/6.3V_4 CRT_BYP
7 8
C580 0.1u/10V_4
2
+3V
CRTVSYNC CRTHSYNC
VCC_SYNC SYNC_OUT2 SYNC_OUT1 VCC_DDC BYP SYNC_IN2 VCC_VIDEO SYNC_IN1
16 14
VIDEO_1 VIDEO_2 VIDEO_3
DDC_IN1 DDC_IN2
10 11
INT_DDCCLK INT_DDCDATA
DDC_OUT1 DDC_OUT2
9 12
DDCCLK_1 DDCDAT_1
15 13
INT_CRT_VSYNC INT_CRT_HSYNC
R369 2.7K_4
R368 2.7K_4
C551
*.1u/10V_4 CRTVDD5
C125
*10P/50V_4 CRTVSYNC
C202
*10P/50V_4 CRTHSYNC
C108
*10P/50V_4 DDCCLK_1
C570
*10P/50V_4 DDCDAT_1
C223 CRT_R1 CRT_G1 CRT_B1
0.1u/10V_4
3 4 5 6
GND
R370 R367
2.7K_4 2.7K_4
CRTVDD5
CM2009-02QR
B
B
LVDS(LDS)
LCD PW(LDS)
VIN L5 L4 C14
*0_6 0_6
+3V LCDVCC L2 C4
LCD_VIN
0_6
LCDVCC_L C9
C11 *10P/50V_4
*10P/50V_4 L1 0_6
*10P/50V_4
C8 1U/6.3V_4
CCD_POWER C10 *10P/50V_4
C15 *10P/50V_4
6
4 INT_LVDS_DIGON
CN6
+3V
C13
4.7u/25V_8
1000P/50V_4
31
C2
C7
0.1u/10V_4
1000P/50V_4
CONTRAST
R3
SW@0_4
R4
IV@0_4
USBP2USBP2+
LVDS_BRIGHT
1
IN
GND
2
ON/OFF
GND
5
LCDVCC
C5
C1
C6
1U/6.3V_4
*.1u/10V_4
.01u/16V_4
C3 22u/6.3V_8
IC(5P) G5243T11U R2 100K_4
Backlight Control(LDS) 32
32
33
33
34
34
31
31
C
+3V
R8
R7
10K_4
10K_4 BL_ON
D2
2
1 BAS316
LID591#
31
BL#
LVDS
2
2
Q1 2N7002K
EC_FPBACK# 31
Q2 DTC144EUA
1
4 INT_LVDS_PWM
9 9
3
OUT
IN
3
C12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
4
*10P/50V_4
40mil
3
VIN
LCD_VIN
1 +3V 2 LCDVCC_L 3 4 5 6 R5 2.2K_4 INT_EDIDCLK 7 R6 2.2K_4 INT_EDIDDATA 8 9 INT_TXLOUTN0 10 INT_TXLOUTP0 11 12 INT_TXLOUTN1 13 INT_TXLOUTP1 14 15 INT_TXLOUTN2 16 INT_TXLOUTP2 17 18 INT_TXLCLKN 19 INT_TXLCLKP L3 20 *DLW21HN900SQ2L 21 USBP23 3 22 4 4 USBP2+ 2 2 23 1 1 24 25 CCD_POWER 26 27 28 29 BL_ON 30
60mil 40mil
C
U1
1
+3V
3
4 INT_EDIDCLK 4 INT_EDIDDATA 4 INT_TXLCLKN 4 INT_TXLCLKP 4 INT_TXLOUTN0 4 INT_TXLOUTP0 4 INT_TXLOUTN1 4 INT_TXLOUTP1 4 INT_TXLOUTN2 4 INT_TXLOUTP2
2
4 INT_LVDS_BLON
+3VPCU
Lid Switch (HSR)
R9
D
1
R269
D
1U/6.3V_4
1
Q3 2N7002K C480
100K_4
*470K/F_4 LID591#
HE1 AH9249NTR-G1 SOT23_123-2_8-1_9
Quanta Computer Inc.
3
2
PT3661-BB (PLC) : AL003661003 ME268-002 (FCE) : AL000268000
PROJECT : ZQG Size
Document Number
Rev 1A
CRT/LVDS/LID Date: 1
2
3
4
5
6
Monday, November 01, 2010 7
Sheet
20 8
of
41
5
4
3
HDMI SDVO I2C Control
2
HDMI HPD SENSE (HDM)
23
UMA use +3V for the detect pin Dis use +3V_DELAY for the detect pin
HDMI_DDCDATA HDMI_DDCCLK
4 HDMI_DDCDATA 4 HDMI_DDCCLK
1
+3V
D
D
3
R216 10K_4
+3V
2
HDMI_DET_R
R215
HDMI_DET
200K/F_4
Q20 2N7002K
R214 200K/F_4
1
R217 10K_4
3
4 INT_HDMI_HPD
2
HDMI_HPD_EC# 31
Q21 2N7002K
HDMI (HDM)
1
C
C
EMI reserve for HDMI(EMC)
Close to HDMI Connector
Close connector
HDMI PORT (HDM)
TX2_HDMI+ +5V
HDMI_PL_MOS
R234
715/F_4
TX2_HDMI+
R240
715/F_4
TX2_HDMI-
R230
715/F_4
TX1_HDMI+
R238 *100/F_4
CN18
3
TX2_HDMITX2_HDMI+
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
TX1_HDMI+
Q22 2N7002K 2
R226
715/F_4
TX1_HDMI-
R233
715/F_4
TX0_HDMI+
R231
715/F_4
TX0_HDMI-
TX2_HDMITX1_HDMI+
R228 *100/F_4 TX1_HDMI-
TX1_HDMITX0_HDMI+
1
TX0_HDMI+
B
R252
R224
715/F_4
TXC_HDMI+
R221
715/F_4
TXC_HDMI-
TX0_HDMITXC_HDMI+
R232 *100/F_4 TX0_HDMI-
Due to HDMI item7-2 is fail, Change to CS16492FB13.
100K/F_4
TXC_HDMI-
TXC_HDMI+ +5V R223 *100/F_4
DIS Stuff 499 ohm CS14992FB24
HDMI_DDCCLK HDMI_DDCDATA
F2 SMD1206P100TF 2 1
TXC_HDMI-
C09
+5V_HDMI HDMI_DET
: Del D26 to slove HDMI issue.
SHELL1 D2+SHELL3 D2 Shield D2D1+ D1 Shield D1D0+ D0 Shield D0CK+ CK Shield CKCE Remote NC DDC CLK DDC DATA GND +5V HP DET SHELL4 SHELL2
20 22
B
23 21
QJ1119C-NK01-8F C627 .22u/6.3V_4 C633 *1000P/50V_4
4 4 4 4 4 4 4 4
A
TX2_HDMI+ TX2_HDMITX1_HDMI+ TX1_HDMITX0_HDMI+ TX0_HDMITXC_HDMI+ TXC_HDMI-
TX2_HDMI+ TX2_HDMITX1_HDMI+ TX1_HDMITX0_HDMI+ TX0_HDMITXC_HDMI+ TXC_HDMI-
D24 +5V
2
R446
CH501H-40PT D25 +5V
2
HDMI_DDCCLK
1 2K/F_4
C636 *1000P/50V_4
R447 HDMI_DDCDATA
1 CH501H-40PT
A
2K/F_4
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
Rev 1A
HDMI Date: 5
4
3
2
Monday, November 01, 2010
Sheet 1
21
of
41
5
4
3
2
1
Giga-LAN AR8151 +3V_S5
close Pin1
R195
*short0603
C355
C353
C366
C361
C358
10u/6.3V_8
10u/6.3V_8
1u/6.3V_4
0.1u/10V_4
*1000p/50V_4 9/16
8,13,23,31 D
+3V_LAN
+3V_LAN U9
2
PLTRST#
3
9,31 PCIE_WAKE# R201
9 PCIE_REQ_LAN#
*Short_4 8151_CLKREQ# +VDDCT
5
1u/6.3V_4
AVDDL
6
C624
0.1u/10V_4
XTLO
7
XTLI
8
AVDDH
9
RBIAS
10
TX0P
11
TX0N
12
AVDDL
13
TX1P
14
TX1N
15
C368
1u/6.3V_4
C367
0.1u/10V_4
R203
0.1u/10V_4
2.37K/F_4
Wake# and CLKREQ# PU at PCH side already C619
C396
0.1u/10V_4
0.1u/10V_4
1 33p/50V_4
Y2 25MHz C623
2
C364
AVDDH
16
TX2P
17
TX2N
18
AVDDL
19
TX3P
20
TX3N
21
XTLO
33p/50V_4
1.2H C
4
C618
C373
C365
1
0.1u/10V_4
XTLI
VDD33
AVDDH
PERSTn
CLKREQn/LED2
WAKEn
DVDDL
CLKREQn
SMCLK
AR8151 5X5mm
VDDCT
40-Pin QFN
AVDDL_REG XTLO
SMDATA
AVDDH_REG
TX_P
RBIAS
AVDDL
TRXP0
REFCLK_N
TRXN0
REFCLK_P
NC/AVDDL
RX_P
TRXN1
RX_N
NC/AVDDH
DVDDL_REG
NC/TRXP2
LED0
NC/TRXN2
LED1
C405
0.1u/10V_4
24
DVDDL
C406
0.1u/10V_4
25
SMCLK_8151
R218
*0_4
26
SMDATA_8151 R219
*0_4
T100 D
PCLK_SMB 6,7,9,23 PDAT_SMB 6,7,9,23
SMBus PU at PCH side already
29
PCIE_RXN6_C
C407
0.1u/10V_4
30
PCIE_RXP6_C
C408
0.1u/10V_4
31
AVDDL
C621
PCIE_RXN0_LAN
CLK_PCIE_LANN
AVDDL
C622
LX GND
PCIE_TXP0_LAN
37 38
LAN_ACTLED
39
LAN_LINKLED#
40
LX
R208
C393 C397 5.1K_4
L55
8
1u/6.3V_4 0.1u/10V_4
4.7uH/1A_2X2
Layout : need isolate GND
AR8151
8
PCIE_TXN0_LAN DVDDL
41
NC/TRXN3
8
0.1u/10V_4
36
NC/TRXP3
8
CLK_PCIE_LANP
35
NC/AVDDL
8
0.1u/10V_4
33 34
8
PCIE_RXP0_LAN
32
AVDDL
TRXP1
LED2
28
TEST_RST TX_N
AVDDH
23
27
TESTMODE
XTLI
22
+VDDCT C614
C615
C616
*1000p/50V_4
0.1u/10V_4
10u/6.3V_8
C
RJ45(LAN)
TX1N
TX1P
TX0N
TX0P
TRANSFORMER(LAN) R202
R200
R198
R197
CN15
reverse 1000p*4 for EMI
49.9/F_4
AVDD_CEN
LAN_N2
49.9/F_4
49.9/F_4
49.9/F_4 LAN_N1
LAN_ACTLED
Close Transformer U28
C356
reverse 1000p*4 for EMI C363
L54 PBY160808T-181Y-N/2A/180ohm_6
R433
9 10
220_8 X-TX0P X-TX0N X-TX1P X-TX2P X-TX2N X-TX1N X-TX3P X-TX3N
1 2 3 4 5 6 7 8
LAN_LINKLED# LAN_LNK_LED_PWR
11 12
+VDDCT
1U/10V_4
*1000P/50V_4 U22
C369
0.1U/10V_4
*1000P/50V_4
C613 C357
0.1u/10V_4 TX0P TX0N
*1000P/50V_4
1 2 3
0.1U/10V_4 C394 C388
C387
TX3N
TX3P
TX2N
TX2P
C395
0.1u/10V_4
*1000P/50V_4
TX2P TX2N
7 8 9
TX3P TX3N
10 11 12
0.1u/10V_4
R212
R211
R209
R207
4 5 6
0.1u/10V_4
*1000P/50V_4
C362
TX1P TX1N
TCT1 TD1+ TD1-
MCT1 MX1+ MX1-
TCT2 TD2+ TD2-
MCT2 MX2+ MX2-
TCT3 TD3+ TD3-
MCT3 MX3+ MX3-
TCT4 TD4+ TD4-
MCT4 MX4+ MX4-
24 23 22
X-TX0P X-TX0N X-TX1P X-TX1N
18 17 16
X-TX2P X-TX2N
15 14 13
X-TX3P X-TX3N
C399
C398
*1000P/50V_4
0.1U/10V_4
*1000P/50V_4
GREEN_N GREEN_P
LAN_ACTLED
Delta LFE9276C-R (DB0ZR1LAN00) FCE NS892407 (DB0LL1LAN00) Bothhand GST5009B (DB0Z06LAN00)
LAN_N4
LAN_N3
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
C391
0.1U/10V_4
220_8
RJ45
LAN_LINKLED#
2
TRANSFORMER
C392
B
+3V_LAN R445
21 20 19
14 13
R196 75/F_8
R199 75/F_8
R206 75/F_8
C606 *470p/50V_4
R210 75/F_8
2
C370
*1000P/50V_4
GND2 GND1
0+ 01+ 2+ 213+ 3-
C625 *470p/50V_4
1
C359
1
C360
B
YELLOW_N YELLOW_P
C354 1500p/3KV_18
A
A
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
Rev 1A
LAN (AR8151) Date: 5
4
3
2
Monday, November 01, 2010
Sheet 1
22
of
41
1
2
3
4
5
6
7
8
Check LED signal. (active high or low)
MINI-CARD WLAN(MPC)
+3V
+3.3V: 1000mA +3.3Vaux:330mA +1.5V:500mA
26
+WL_VDD R460
*Short_8
CN21 8 8,25 PCIE_RST# 8 PCLK_DEBUG
R463
LPC_DRQ#0
*0_4
+WL_VDD A
8 8
PCIE_TXP1 PCIE_TXN1
8 8
PCIE_RXP1 PCIE_RXN1
8 CLK_PCIE_WLAN1P 8 CLK_PCIE_WLAN1N 9 PCIE_REQ_WLAN1# +5V_TV-CARD
TV use +5V
R449 R448 T170
*0_6 +5V_TV-CARD_R_A *0_6 +5V_TV-CARD_R_B PCIE_WAKE_WL
51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved GND PETp0 PETn0 GND GND PERp0 PERn0 GND Reserved Reserved
15 13 11 9 7 5 3 1 53
GND REFCLK+ REFCLKGND CLKREQ# Reserved Reserved WAKE# PAD53
+3.3V GND +1.5V LED_WPAN# LED_WLAN# LED_WWAN# GND USB_D+ USB_DGND SMB_DATA SMB_CLK +1.5V GND +3.3Vaux PERST# Reserved GND
52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18
Reserved Reserved Reserved Reserved Reserved +1.5V GND +3.3V PAD54
16 14 12 10 8 6 4 2 54
+WL_VDD
C453 10u/10V_8
+WL_1.5V RF_LED#
C628 0.1u/10V_4
C648 *0.1u/10V_4
C632 *0.1u/10V_4
RF_LED# 29 A
USBP9+ 9 USBP9- 9 PDAT_SMB 6,7,9,22 PCLK_SMB 6,7,9,22 +WL_1.5V +WL_VDD
DEBUG_LFRAME# DEBUG_LAD3 DEBUG_LAD2 DEBUG_LAD1 DEBUG_LAD0
R229 R227 R225 R220 R222
*Short_4 *Short_4 *Short_4 *Short_4 *Short_4
LPC_LFRAME# 8,31 LPC_LAD3 8,31 LPC_LAD2 8,31 LPC_LAD1 8,31 LPC_LAD0 8,31
+1.5V
+WL_1.5V
PLTRST# 8,13,22,31 RF_EN 31
R450 C457 *1000P/50V_4
Debug
C443 *0.1u/10V_4
*Short_8
C629 *10u/6.3V_8
+WL_1.5V +WL_VDD
MINI CARD_A
B
Check LED signal. (active high or low)
MINI-CARD WLAN(MPC)
B
+3V
+3.3V: 1000mA +3.3Vaux:330mA +1.5V:500mA
R289 *0_4
+WL_VDD
8 8
PCIE_TXP2 PCIE_TXN2
8 8
PCIE_RXP2 PCIE_RXN2
8 CLK_PCIE_WLAN2P 8 CLK_PCIE_WLAN2N 9 PCIE_REQ_WLAN2#
C
*Short_8
CN7 LPC_DRQ#0 R291 PLTRST# PCLK_DEBUG
+5V
+WL_VDD
R287 R286
500mA, 25mil
T101
*0_6 +5V_TV-CARD_R_A *0_6 +5V_TV-CARD_R_B PCIE_WAKE_WL
51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 53
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved GND PETp0 PETn0 GND GND PERp0 PERn0 GND Reserved Reserved GND REFCLK+ REFCLKGND CLKREQ# Reserved Reserved WAKE# PAD53
+3.3V GND +1.5V LED_WPAN# LED_WLAN# LED_WWAN# GND USB_D+ USB_DGND SMB_DATA SMB_CLK +1.5V GND +3.3Vaux PERST# Reserved GND Reserved Reserved Reserved Reserved Reserved +1.5V GND +3.3V PAD54
52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 54
+WL_VDD
C489 10u/10V_8
+WL_1.5V
C484 0.1u/10V_4
C491 *0.1u/10V_4
C486 *0.1u/10V_4
RF_LED#
USBP10+ 9 USBP10- 9 SB_SDATA4 SB_SCLK4
SB_SDATA4 9 SB_SCLK4 9
+WL_1.5V +WL_VDD
+1.5V
+WL_1.5V
PLTRST# RF_EN
R292 C487 *1000P/50V_4
C485 *0.1u/10V_4
*Short_8
C490 *10u/6.3V_8
+WL_1.5V +WL_VDD
C
MINI CARD_A
D
D
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
Rev 1A
MINI PCI-E card Date: 1
2
3
4
5
6
7
Monday, November 01, 2010
Sheet
23 8
of
41
1
2
3
4
SATA HDD
27
CN19
A
23
GND1 RXP RXN GND2 TXN TXP GND3
1 2 3 4 5 6 7
3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND RSVD GND 12V 12V 12V
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
GND24
24
SATA_TXP0 10 SATA_TXN0 10 SATA_RX0-_C SATA_RX0+_C
C452 C445
.01u/16V_4 .01u/16V_4
120mil +
B
GND23
A
SATA_RXN0 10 SATA_RXP0 10
+5V_HDD
R443
*Short_8
+5V
C620 C617 10u/25V_1206 *100u/6.3V_3528
C612 10u/25V_1206
C611 0.1u/10V_4
C610 .01u/16V_4
B
SATA_HDD
SATA ODD CN11
C
14
GND1 RXP RXN GND2 TXN TXP GND3
1 2 3 4 5 6 7
DP +5V +5V RSVD GND GND
8 9 10 11 12 13
GND15
15
SATA_TXP1 10 SATA_TXN1 10 SATA_RX1-_C SATA_RX1+_C
SATA_DP
R119
C225 C208
.01u/16V_4 .01u/16V_4
SATA_RXN1 10 SATA_RXP1 10
C
*1K_4 +5V_ODD
+
GND14
R379
*Short_8 +5V
C562 *100u/6.3V_3528
C539 10u/25V_1206
C552 10u/25V_1206
C532 0.1u/10V_4
C527 .01u/16V_4
C18534-11305-L
D
D
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
Rev 1A
SATA-HDD/ODD/HOLE Date: 1
2
3
Monday, November 01, 2010
Sheet 4
24
of
41
A
B
C
D
E
2 IN 1 CARD READER (MMC)
30
SD_WP
CARD READER Controller
VCC_XD SD_CMD SD_DAT3 SD_DAT2
SD-CARD
WP/SW SW COM
4 DATA1 DATA0 VSS2 CLK VDD VSS1 CMD DATA3 DATA2
4
GND1
SD_CLK
14
*10P/50V_4
10 9 8 7 6 5 3 2 1
CD/SW
C634
13
4
SD_DAT1 SD_DAT0
GND
CN4
for EMI SD_CLK
11 12
SD_CD#
VCC_XD
Main
DFHS11FR011
Second
C654
0.1u/10V_4
0.1u/10V_4
+3V_VDD
U23
VDDHM GND VDD XTALSEL TRIST NBMD CTRL1 CTRL3 DATA1 DATA0 DATA7 DATA6
*Short_4
48 47 46 45 44 43 42 41 40 39 38 37
CTRL0, CRTL 1 trace length shorter , and surround with GND.
*100K_4
C657 *0.47u/10V_6 +3V
R461
*Short_6
+3V_VDD C658 4.7u/10V_6 R474 330_4
9 9
USBP6+ USBP6C659 *5p/50V_4
XI XO
C660 *5p/50V_4
+1.8V_VDD
1 2 3 4 5 6 7 8 9 10 11 12
GPON7 EXT48IN RSTN REXT VD33P DP DM VS33P XI XO VDD VDD
2
CTRL0 DATA5 CTRL2 GPI4 DATA4 DATA3 DATA2 XDWPN GPI2 XDCEN EEPDATA GPI1
AU6437-GBL
36 35 34 33 32 31 30 29 28 27 26 25
4.7u/10V_6
18p/50V_4
R455
*Short_4
SD_DAT0
DATA1
R456
*Short_4
SD_DAT1
DATA2
R454
*Short_4
SD_DAT2
DATA3
R453
*Short_4
SD_DAT3
CTRL0
R451 SD_CLK BLM15AG121SS1/0.5A/120ohm_4
CTRL1
R459
*Short_4
SD_WP
CTRL2
R452
*Short_4
SD_CMD
CTRL3
R458
*Short_4
SD_CD#
T171 EEPDATA GPI1
T173 T174
T175
R470 270K_4 *0_4
VCC_XD
C663
DATA0 GPI2
VCC_XD
XI Y6 12MHz
T172 DATA3 DATA2
2
EEPCLK 18p/50V_4
CTRL2 GPI4
pin13 output 20mils C655
C662
CTRL0
13 14 15 16 17 18 19 20 21 22 23 24
close PIN11, 12
crystal trace width needs at least 10 mils.
3
XTALSEL CRMD_N NBMD CTRL1 CTRL3 DATA1 DATA0
C653
V18 CF_V33 VCC33 AGND5V V33 VDDHM GND VDD CTRL4 XDCDN SDWPEN EEPCLK
R472
5/10 change Card Redaer conn footpirnt sdcard-sdsn09-08-xa-11p-smt
Close to CNxx pin 14 & pin23 4.7u CAP close to pin23 T177
Clock input selection '1' for 48MHz input [Default] '0' for 12MHz input
8,23 PCIE_RST#
0.1u/10V_4
C708 close PIN48, 47
*Short_4 XTALSEL
R473
DFHS11FR033
C650
T178
+3V_VDD
3
4.7u/10V_6
C743 close PIN46, 47
+1.8V_VDD
R464
C652
XO
+1.8V_VDD +3V_VDD
+3V_VDD C644
C646
4.7u/10V_6
0.1u/10V_4
R457
SD write protect 1:decided by SDWP[Default] 0:letting SD always write-able
C637 *10P/50V_4
1
1
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
Rev 1A
AU6433 CardReader Date: A
B
C
D
Monday, November 01, 2010
Sheet E
25
of
41
5
4
3
FILT_1.65V
AUDIO CODEC
1
C474
Codec(ADO)
AVDD_3.3 pin is output of internal LDO. Do NOT connect to external supply.
C468 C471 1u/16V_6
2
LDO_OUT_3.3V C466
0.1u/10V_4 10u/10V_8 0.1u/10V_4
3V_DVDD
Port Configuration ADOGND ADOGND
C661
C656
Notes:
C651
10u/10V_8 0.1u/10V_4
0.1u/10V_4
+5VA
D
3V_DVDD C475
(3.3V or 1.5V)
C640 1u/16V_6
C467
10u/10V_8 0.1u/10V_4 Layout
C448
3V_DVDD
C642
Note: Path from +5V to LPWR_5.0 and RPWR_5.0 must be very low resistance ( 220K/F_4 (CS42202FB01) Rc --> 40.2K/F_4 (CS34022FB15)
D
Rb --> 110K/F_4 (CS41102FB13) Rd --> 49.9K/F_4 (CS34992FB10)
D
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
Rev 1A
GPU CORE(MAX8792) Date: 1
A
+VGPU_CORE
PQ24
4
8792BST
PGOOD
15
Rc
GPU_VID1
PC89 SW @4.7u/25V_8
REF-2V PR32 SW @100K_4
B
14
PC91 SW @4.7u/25V_8
VCC
EP
for PX4.0 function ( BACO)
8792REFIN 10
TON
1 2 3
16,39 dGPU_PW REN
13
VDD
PC90 SW @4.7u/25V_8
1 2 3
PC22
5
PR30 SW @10K_4
1 2 3
PR33 *SW @10K_4
PC8 SW @2.2n/50V_4
5
PR18 SW @200K/F_4
5
+3V
A
+VGPU_CORE 1Volt +/- 5% TDC : 10.65A PEAK : 14.2A OCP : 15A Width : 440mil
2
3
4
Monday, November 01, 2010
Sheet 5
38
of
41
5
+3VPCU
4
3
2
1
C-Test +1.8V
PC28 10u/10V_8
C-Test
PC29 0.1u/25V_4 PU4 16
C-Test D
MAINON
PR40
*Short_4
PC31 1000p/50V_4
2 15
PH
10
VIN
PH
11
VIN
PH
12
EN
BOOT
13 14
54418-1.8_VFB
6
VSNS
PWRGD
COMP_PIN7
7
COMP
GND
3
8
RT/CLK
GND
4
9
SS
AGND
5
PR35 182K/F_4
PC25 *100P/50V_4
PH10_11_12 PL7 1uH_7X7X3
D
PC30 0.1u/50V_6
R1 PR131 100K/F_4 HW PG_1.8V 31
PR42 10K_4
22 21 20 19 18 17
PR36 15K/F_4
PAD PAD PAD PAD PAD PAD
30,31,36,37,40
1
HPA00835RTER
VIN
PC24 0.01u/25V_4
54418-1.8_VFB
+3V
V0=0.8*(R1+R2)/R2
VIN
PC103 10u/10V_8
PC102 10u/10V_8
PR135 78.7K/F_4
+1V
+15V
PR199 SW @1M_4
3
PR198 SW @1M_4
C
PC101 0.1u/25V_4
R2
PC23 1200p/50V_4
C03
C
+1V_GPU TDC : 2.5A Width : 100mil
2
3
3
dGPU_D1
17,38 PG_GPUIO_EN
PX4@0_4
PR200 SW @1M_4
PQ61 SW @DTC144EU
2
PQ59 SW @AO3404
2 PC156 PQ60 *2.2n/50V_4 SW @DMN601K-7
+1V_GPU
1
1
PC157
1
PR201
+1.8V 1.8Volt +/- 5% TDC : 3A PEAK : 4A Width : 120mil
*1U/6.3V_4
VIN
+1.5V_GPU
+1.5V_SUS
+15V
for PX4.0 function ( BACO) *PX4@0_4 PR182 SW @1M/F_6 PR179
SW @0_6
PR180
*SW @0_6
3
PG_GPUIO_EN
PR177 SW @22_8
PR183 SW @1M/F_6
DGPU_1.5V_ON_R
16,38 dGPU_PW REN
PQ46 SW @AO4468
2 2
2
PR181 SW @1M/F_6
PQ48 SW @DMN601K-7
PR139 SW @1M/F_6
C03 PG_GPUIO_EN
PR133
PR134 SW @22_8
3 2 1
+1.5V_GPU TDC : 2.1A PEAK : 2.8A Width : 90mil
+1.5V_GPU
+1.8V
+15V
PR138 SW @1M/F_6
SW @0_6
A
2
PR136 *SW @0_4
3
3
3
A
+1.8V_GPU
PC141 *SW @2.2n/50V_4
3
VIN
PQ49 SW @DMN601K-7 1
1
SW @DMN601K-7
1
PQ47 PR178 *SW @100K_4
B
4 3
C03
5 6 7 8
PR203
3
17 PX_MODE B
1
2
+1.5V_GPU
2
PQ31 PQ28 SW @DMN601K-7 SW @DMN601K-7
PC105 *SW @2.2n/50V_4
+1.8V_GPU
Quanta Computer Inc. PROJECT : ZQG
1
PR137 SW @1M/F_6 1
SW @DMN601K-7
1
PC104 *SW @1U/10V_4
PQ30 SW @AO3404
2
PQ29
+1.8V_GPU TDC : 1.41A PEAK : 1.88A Width : 60mil Size
Document Number
+1.8V /+1V_GPU / +1.5_GPU / +1.8_GPU Date: 5
4
3
2
Sheet
Monday, November 01, 2010 1
39
of
41
Rev 1A
5
4
3
2
VIN
+3V
PR116 1M_6
+5V
PR104 22_8
1
+1.5V
+1.8V
PR105 22_8
PR171 22_8
+15V
PR106 22_8
PR109 1M_6
MAINON_ON_G
MAIND
MAIND
D
3
3
3
3
33,35,37
3
3
D
2
2
1
PQ14 DMN601K-7
VIN
2
PQ42 DMN601K-7
PQ15 DMN601K-7
+5V_SUS
+15V
PC77 *2200p/50V_4
PQ16 DMN601K-7 1
2 PQ13 DMN601K-7
1
2
1
PR66 *100K_4
PR108 1M_6
1
PQ18 DTC144EU
2
1
MAINON
30,31,36,37,39 MAINON
+5VPCU
VIN PR160 1M_6
PD2 SW1010CPT
PR170 22_8
PR167 1M_6
3
Thermal protection C
3
2
30,31,37 SUSON
2
PC128 *2.2n/50V_4
+5V_SUS
1
PQ39 DMN601K-7
3
3
2
PQ41 DMN601K-7 1
PQ6 AO3409
PQ36 DTC144EUA
1
PR162 *100K_4
PQ40 AO3404
C
2
1
PR39 1M_6
PR161 1M_6
2
1
3
3
SUSD
+5V_SUS TDC : 1.125A PEAK : 1.5A Width : 50mil
S5_ON
30,31,33,35 S5_ON
2
1
PQ7 DTC144EU VL
PR38 *Short_6
VL
B
B
LM393_PIN8 PR52 1.2K/F_4
PR56 200K/F_4
PR37 200K_6
SYS_SHDN# 4,33
8 2.469V
3
+
2
4
LM393_PIN2
3
PR49 200K/F_4
1
2 PQ5 DMN601K-7
PU5A LM393
PC27 0.1u/50V_6
5
+
6
-
A
2
1
PR58 THERMISTOR_10K_6(NTC)
A
7 PU5B LM393
PQ8 DMN601K-7
Quanta Computer Inc. PROJECT : ZQG
1
S5_ON
3
PC26 0.1u/50V_6
For EC control thermal protection (output 3.3V)
Size
Document Number
Rev
Discharge /Thermal protection 1A Date: 5
4
3
2
Monday, November 01, 2010
Sheet 1
40
of
41
5
4
3
2
1
Model
MODEL
REV
ZQE/G M/B
3A
CHANGE LIST
Page
C01 C02 PAGE18 : to slove the Power DVD issue , setting size to 256MB
D
C03 PAGE39 : add PR210,PC157,PQ61,PR198,PR200,PR199,PQ60,PC156,PQ69 for GPU +1V power source . changed control net from HWPG_1V to PG_GPUIO_EN C04 PAGE13 : change the power source from +1V to +1V_GPU C05 PAGE14 : change the power source from +1V to +1V_GPU C06 PAGE16 : change the power source from +1V to +1V_GPU C07 PAGE17 : change the power source from +1V to +1V_GPU C08 PAGE18 : to solve the HDMI issue , remove R112,R118 from BOMs C09 PAGE21 : Del D26 to slove HDMI issue. C10 PAGE26 : net PCBEEP connects with U11 by 10k ohm for AC pulg in /out function.
C
C11 PAGE31 : Both MXM_SMCLK12 / MXM_SMDATA12 should be pull up to +3V by 10k ohm. C12 PAGE35 : stuff 10k ohm C13 PAGE36 : change PR169 PN from 0 ohm to 430K ohm for timing issue. C14 PAGE36 : stuff 10k ohm C15 PAGE36 : change PR75 PN from 3.57k to 3.65k C16 PAGE38 : remove PQ27 for cose down. C17 PAGE38 : remove PQ27 for cose down. C18 PAGE5 :
Add C674 to reduce CRT noise.
C19 PAGE5 :
del R100 , add L58 to reduce CRT noise.
B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
ZQE/G M/B BOARD From
To
1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A
3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A
D
C
B
Note : 1. Remove Jumper : JP7,JP11,JP1,JP2,JP3,JP4,JP5,JP6,JP8,JP9,JP10,JP12,JP13,JP14,JP15,JP16,JP17,JP18 A
Quanta Computer Inc. PROJECT : ZQG Size
Document Number
Rev 1A
CHANGE LIST - 3A Date:
Quanta Computer Inc. ZQE/G 5
PROJECT: ZQE/G
PCBA NO.
APPROVED BY : Johnny O 4
REV: 3A
CHECK BY : Darren Liao
DRAWING BY : Kenneth Huang 3
Monday, November 01, 2010
Sheet
DOC. NO : 2
DATE :10/18/2010
SHEET 1 1
41
of
41
A