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• Inquieta Musaraña

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PRIMER CURSO – SEGUNDO CUATRIMESTRE

ELECTRÓNICA DIGITAL

TODO EL TEMARIO

TEMA 1: Aspectos generales de los sistemas digitales TEMA 2: Circuitos combinacionales TEMA 3: Biestables TEMA 4: Registros y contadores TEMA 5: Síntesis de Sistemas Secuenciales

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: in bit_vector(3 downto 0); -- dato A 4 bits : in bit_vector(3 downto 0); -- dato B 4 bits : in bit; -- selección y enable : out bit_vector(3 downto 0)); -- salida 4 bits

end Mux4; architecture funcionmux of Mux4 is begin -- funcionmux -- purpose: selección l ió uno d de l los d datos A o B en la l salida lid -- type : combinational -- inputs : A, B, S, E -- outputs: O process (A, B, S, E) begin -- process if E = '0' then if S = '0' then O ŵĂdž͗DĄdžŝŵĂĐŽƌƌŝĞŶƚĞĞŶůĂĞŶƚƌĂĚĂĐƵĂŶĚŽůĂƉƵĞƌƚĂƌĞĐŝďĞƵŶ͚Ϭ͛͘

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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

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architecture RTL of cont_asc is signal Pre_Q: std_logic_vector(3 downto 0); begin process(CLK, CLR) begin if CLR = '0' then Pre_Q '0'); elsif (CLK'event and CLK='1') then Pre_Q '&%$@ „ 9HQWDMDV † 0iVUiSLGRVTXHDVtQFURQRV † 1RKD\HVWDGRVLQWHUPHGLRVSRUTXHORVLQVWDQWHVGH FRQPXWDFLyQ VRQ ORV PLVPRV FRQPXWDFLyQVRQORVPLVPRV „ 3UREOHPDV † 0D\RUFRPSOHMLGDGGHGLVHxRUHTXLHUHQSXHUWDV

library ieee; &yGLJR9+'/ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity cont_uni is port( I: in std_logic_vector(3 downto 0); CLK: in std_logic; CLR: in std_logic; LOAD in LOAD: i std_logic; td l i EN: in std_logic; UD: in std_logic; MXMN: out std_logic; Q: out std_logic_vector(3 downto 0)); end cont_uni;

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architecture RTL of cont_uni is signal Pre_Q: std_logic_vector(3 downto 0); begin process(CLK, CLR) begin if (CLR = '0') then Pre_Q '0'); elsif (CLK'event and CLK='1') then if (EN='1') then if (LOAD= (LOAD='0') 0 ) then Pre_Q