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01

Chief River Block Diagram A

A

USB-11

LCD/CCD Con. P28

EXT_LVDS

DDRIII-SODIMM1 DDRIII-SODIMM2

Ivy Bridge(UMA+VGA) DDR SYSTEM MEMORY

P13,14

Dual Channel DDR III

SATA - HDD P33

P27

HDMI Con.

P27

VRAM DDR3-64M*16 VRAM DDR3-128M*16

P3,4, 5, 6, FDI

P28

DMI

DMI(x4) FDI

DMI

SATA 4

B

PCI-E Graphics Interfaces

SATA

USB-11

INT_LVDS

INT_CRT

INT_HDMI

HDMI Level Shift

USB-5

P27

LCD/CCD Con.

P28

CRT Con.

P28

HDMI Con.

P27

B

PantherPoint

P29

PCIE-3

USB-8

USB

USB-4

PCH

P36

USB 2.0 LD Con.

HDMI Level Shift

rPGA 989

CRT Con.

SATA 0

P33

Card Reader Con.

EXT_HDMI

P15,16,17,18,19,20,21,22,25

SATA - ODD

SIM CARD.

EXT_CRT

VGA Thames_M2

PCI-E x16 PCI-E

USB-9

PCIE-5

P32

USB-13

RTC

WLAN P29

BATTERY C

3G P29

P7,8, 9, 10, 11,12

PCIE-7

Giga/10/100 Lan

P8

C

P35 PCI-E PCIE-2

Azalia

IHDA LPC

USB3.0 Controller P30

NVRAM

P32

Audio Codec

USB 3.0 LU Con.

USB-2

P32

EC P37

P34

FAN HP

P34

P31

USB3.0 Level Shift

LPC

MIC JACK

USB 3.0 Right Con.

USB-0

K/B Con.

HALL Sensor

SPI Flash

Touch Pad /B Con.

SPK Con. P34

P34

P3

P38

P28

P8

P38

POWER SYSTEM Charger (ISL88731C) System 5V/3V (TPS51123A) DDR1.5V (TPS51216) VTT (RT8240BGQW) +VCCSA (TI51461) +VCORE+VGFX (ISL95836) +1.8V (G966A) AMD_GPU (ISL95870A)

Power /B Con. P38

D

P40 P41 P42 P43 P44 P45 P46 P47

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Rev A1A

Block Diagram Date: 1

2

3

4

5

6

7

Wednesday, February 01, 2012

Sheet 8

1

of

48

D

5

4

3

AO6402A

low switch

+5V_S5 AC/DC Insert enable D

AC DC

(Peak 12.85A ,AVG 9A)

System Charger ISL88731C

OCP 15A

SYSTEM POWER

1

02

MAIND enable

(Peak 5.774A ,AVG 4.042A)

TPS51461 PWM

+VCCSA

HWPG_VTT enable

D

(Peak 6A ,AVG 4.2A)

RT8223 PWM

+3V_S5 AC/DC Insert enable

PWM

(Peak 13.47A ,AVG 9.43A)

OCP 15A

+SMDDR_VTERM SUSON enable

AON7406

low switch

G9661-25ADJ LDO G9661-25ADJ LDO

MAIND enable

+1.8V

MAINON enable

(Peak 1.242A ,AVG 0.869A)

+1.8V_GPU GFX_+1.8VGFX_ON (Peak 1.217A ,AVG 0.922A) C

AO6402A

+1.5VSUS SUSON enable

(Peak 17.81A ,AVG 12.46A)

+3V

(Peak 6.816A ,AVG 4.771A)

+SMDDR_VTERM SUSON enable

TPS51216 PWM

C

+5V

2

low switch

+1.5V

MAIND enable

(Peak 0.67A ,AVG 0.453A)

OCP 20A

G9661-25ADJ LDO

+1.5V_GPU GFX_+1.5VGFX_ON (Peak 4.6A ,AVG 3.22A)

RT8240 PWM

B

ISL95836HRZ-T PWM

+1.05V +VTT MAINON enable (Peak 18.05A ,AVG 12.63A)

OCP 20A

VIN +VCCRTC

VOLTAGE

CONTROL SIGNAL

Power States ACTIVE IN

10V~+19V

S0~S5

+3.0V~+3.3V

S0~S5

+3V

+3.3V

MAIN_ON

S0

+3V_S5

+3.3V

S5_ON

S0~S5

+3V_HDP

+3.3V

MAIN_ON

S0

+3VPCU

+3.3V

AC/DC Insert enable

S0

+VCC_CORE VRON enable

+5V

+5V

MAIN_ON

S0

+5V_S5

+5V

S5_ON

S0~S5

+VAXG VRON enable

+5VPCU

+5V

AC/DC Insert enable

S0~S5

WIMAX_P

+3.3V

WMAX_P for WLAN

B

(Peak 53A ,AVG 53A)

(Peak 33A ,AVG 23.1A)

ISL95870AHRUZ-T PWM

POWER PLANE

+VGPU_CORE GFX_MAINON (Peak 30A ,AVG 20.5A)

RT9046GE

AON7410 Linear Regulator

+1V_GPU GFX_+1.0VGFX_ON (Peak 2.8A ,AVG 1.96A)

+1.8V

+1.8V

MAIN_ON

+1.5V

+1.5V

MAIN_ON

S0

+1.5V_SUS

+1.5V

SUSON

S0~S3

VRON

S0

+VTT

+1.05V

MAIN_ON

S0

+1.05V

+1.05V

MAIN_ON

S0

MPWROK

S0

+VCC_CORE

+VAXG

S0

A

A

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Rev A1A

POWER TREE TABLE Date: 5

4

3

2

Wednesday, February 01, 2012 1

Sheet

2

of

48

5

4

3

2

CPU/VGA

Ivy Bridge Processor (DMI,PEG,FDI)

1

Ivy Bridge Processor (CLK,MISC,JTAG) CPU

03

U1001A

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

[7] [7] [7] [7] [7] [7] [7] [7]

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

A21 H19 E19 F18 B21 C20 D18 E17 A22 G19 E20 G18 B20 C19 D19 F17 J18 J17

[7] FDI_FSYNC0 [7] FDI_FSYNC1

H20

[7] FDI_INT C

J19 H17

[7] FDI_LSYNC0 [7] FDI_LSYNC1

eDP_COMP

A18 A17 B16 C15 D15 C17 F16 C16 G15 C18 E16 D16 F15

DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]

FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC

eDP_COMPIO eDP_ICOMPO eDP_HPD eDP_AUX eDP_AUX# eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3]

PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

PEG_TXN0_C PEG_TXN1_C PEG_TXN2_C PEG_TXN3_C PEG_TXN4_C PEG_TXN5_C PEG_TXN6_C PEG_TXN7_C PEG_TXN8_C PEG_TXN9_C PEG_TXN10_C PEG_TXN11_C PEG_TXN12_C PEG_TXN13_C PEG_TXN14_C PEG_TXN15_C

C1001 C1002 C1003 C1004 C1005 C1006 C1007 C1008 C1009 C1010 C1011 C1012 C1013 C1014 C1015 C1016

[email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X

PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_TXP0_C PEG_TXP1_C PEG_TXP2_C PEG_TXP3_C PEG_TXP4_C PEG_TXP5_C PEG_TXP6_C PEG_TXP7_C PEG_TXP8_C PEG_TXP9_C PEG_TXP10_C PEG_TXP11_C PEG_TXP12_C PEG_TXP13_C PEG_TXP14_C PEG_TXP15_C

C1017 C1018 C1019 C1020 C1021 C1022 C1023 C1024 C1025 C1026 C1027 C1028 C1029 C1030 C1031 C1032

[email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X

PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15

C26

[8] H_SNB_IVB#

TP1

C3A PEG_RXP[0..15]

C5579 *10P/50V_4C

[15]

TP2

AN34

SKTOCC#

AL33

TP_CATERR#

AN33

[37] EC_PECI

H_PROCHOT#

[45] H_PROCHOT#

PEG_TXN[0..15]

R1006

56_4

H_PROCHOT#_R

AL32

PM_THRMTRIP#_R

AN32

PROC_SELECT# SKTOCC#

CLOCKS

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

BCLK BCLK#

DPLL_REF_CLK DPLL_REF_CLK#

PECI

PROCHOT#

SM_DRAMRST#

A16 A15

CLK_DPLL_SSCLKP_R CLK_DPLL_SSCLKN_R

R78 R84

1K_4 1K_4

[9] [9]

D

+VTT

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

R8

CPU_DRAMRST#

AK1 A5 A4

SM_RCOMP_0 R1007 SM_RCOMP_1 R1008 SM_RCOMP_2 R1009

140/F_4 25.5/F_4 200/F_4

C5602 39P/50V_4N

[26]

C5603 0.1U/10V_4X

[15]

AM34

[7] PM_SYNC

E3A

C5590

39P/50V_4N

R1012

10K_4

AP33

[10] H_PWRGOOD

V8

[26] PM_DRAM_PWRGD_R R1014

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

*75/F_4

CPU_PLTRST#

PEG_TXP[0..15]

CLK_CPU_BCLKP CLK_CPU_BCLKN

THERMTRIP#

PRDY# PREQ#

+VTT

A28 A27

CATERR#

DDR3 MISC

[7] [7] [7] [7] [7] [7] [7] [7]

G22 D22 F20 C21

U1001B

[15]

R1015

CPU_PLTRST#_R

*43_4

[15]

C5595 39P/50V_4N

AR33

RESET#

C5577 0.1U/10V_4X

TCK TMS TRST#

JTAG & BPM

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3]

PEG_RXN[0..15]

MISC

[7] [7] [7] [7]

G21 E22 F21 D21

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_COMP

THERMAL

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3]

J22 J21 H22

PWR MANAGEMENT

[7] [7] [7] [7]

B28 B26 A24 B23

PCI EXPRESS* - GRAPHICS

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3]

DMI

[7] [7] [7] [7]

B27 B25 A25 B24

Intel(R) FDI

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

eDP

D

[7] [7] [7] [7]

TDI TDO

DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

AP29 XDP_PRDY#_R AP27 XDP_PREQ#

E3A

TP3 TP4

AR26 XDP_TCLK AR27 XDP_TMS AP30 XDP_TRST# AR28 XDP_TDI_R AP26 XDP_TDO_R

AL35

TP5 TP6

XDP_DBR#_R

R1013

AT28 XDP_OBS0 AR29 XDP_OBS1 AR30 XDP_OBS2 AT30 XDP_OBS3 AP32 XDP_OBS4 AR31 XDP_OBS5 AT31 XDP_OBS6 AR32 XDP_OBS7

E3A

*SHORT_4

XDP_DBRST#

[7]

TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14

C

ACA-ZIF-069-K01

E3A

ACA-ZIF-069-K01

DP & PEG Compensation CPU

Processor pull-up

Level Shift

CPU

CPU

Thermal Trip & Process HOT CPU

+3V_S5

Intel Turbo mode only

CPU

+VTT

+VTT

C1033

6

FDI Disabling (Discrete Only) OEV B

B

*0.1U/10V_4X

24.9/F_4

1

eDP_COMP +VTT

R1001

OEV@1K_4

FDI_FSYNC0

R1018

OEV@1K_4

FDI_FSYNC1

H_PROCHOT#

R1017

62_4

R1021

OEV@1K_4

FDI_LSYNC0

R1023

OEV@1K_4

FDI_LSYNC1

XDP_TMS XDP_TDI_R XDP_TDO_R XDP_TCLK XDP_TRST#

R1019 R1022 R1024 R1025 R1026

51_4 51_4 *51_4 51_4 51_4

W=12mil; S=15mil; L +1V_GPU 2 => +3V_D 3 => +VGPU_CORE,+1.5V_GPU 4 => +1.8V_GPU

PEG Intel platform: Lane0 ~ Lane15 Brazos platform: Lane12 ~ Lane15 Comal and Sabine platform: Lane8 ~Lane15

PEG_RXP8 [3] PEG_RXN8 [3] PEG_RXP7 [3] PEG_RXN7 [3] PEG_RXP6 [3] PEG_RXN6 [3] PEG_RXP5 [3] PEG_RXN5 [3] PEG_RXP4 [3] PEG_RXN4 [3] PEG_RXP3 [3] PEG_RXN3 [3] PEG_RXP2 [3] PEG_RXN2 [3] PEG_RXP1 [3] PEG_RXN1 [3] PEG_RXP0 [3] PEG_RXN0 [3]

+1V_GPU

+1V_GPU

Quanta Computer Inc.

PERSTB EV@HEATHROW M2

PROJECT : Chief River Size

Document Number

Rev A1A

Thames_M2/ PEG*16 Date:

Wednesday, February 01, 2012

Sheet

15

of

48

VGA/CRV/PX4

16

U5000B

PART 2 0F 9

[18] [18] [18] [18] [18]

AR8 AU8 AP8 AW8 AR3 AR1 AU1 AU3 AW3 AP6 AW5 AU5 AR6 AW6 AU6 AT7 AV7 AN7 AV9 AT9 AR10 AW10 AU10 AP10 AV11 AT11 AR12 AW12 AU12 AP12

RAM_STRAP0 RAM_STRAP1 RAM_STRAP2 RAM_STRAP3 RAM_STRAP4

1.8V GPIO

Tempeature function: Connect to EC GPU_SMBCLK GPU_SMBDAT

R5006 R5007

+3V_D

EV@10K/F_4 EV@10K/F_4

GPU_SCL GPU_SDA

T5025

AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17 AL13 AJ14 AK13 AN13

T5013 T5015

AG32 AG33

T5027 R5133

OEV@0_4

GPIO_7_BLON

[18] GPU_GPIO8 [18] GPU_GPIO9 [18] GPU_GPIO10 [18] GPU_GPIO11 [18] GPU_GPIO12 [18] GPU_GPIO13

GPIO_7_BLON

AK26 AJ26

AH20 AH18 AN16

[18] GPU_GPIO0 [18] GPU_GPIO1 [18] GPU_GPIO2

[7,37] LVDS_BKLT

AJ23 AH23

[47] GFX_CORE_CNTRL0 R5037 *OEV@10K_4

T5003 T5026 [47] GFX_CORE_CNTRL1 [18] GPU_GPIO21 [18] GPU_GPIO22

AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24

[18] GPU_GENERICC

SWAPLOCKA SWAPLOCKB DVPCNTL_MVP_0 DVPCNTL_MVP_1 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23

AU24 AV23

TX0P_DPA2P TX0M_DPA2N

AT25 AR24

TX1P_DPA1P TX1M_DPA1N

AU26 AV25

TX2P_DPA0P TX2M_DPA0N

AT27 AR26

TXCBP_DPB3P TXCBM_DPB3N

AR30 AT29

TX3P_DPB2P TX3M_DPB2N

AV31 AU30

TX4P_DPB1P TX4M_DPB1N

AR32 AT31

TX5P_DPB0P TX5M_DPB0N

AT33 AU32

TXCCP_DPC3P TXCCM_DPC3N

AU14 AV13

DPA

DPB

TX0P_DPC2P TX0M_DPC2N DPC TX1P_DPC1P TX1M_DPC1N

AT15 AR14

TX2P_DPC0P TX2M_DPC0N

AT17 AR16

TXCDP_DPD3P TXCDM_DPD3N

AU20 AT19

TX3P_DPD2P TX3M_DPD2N

AT21 AR20

DPD TX4P_DPD1P SMBCLK TX4M_DPD1N SMBDATA SMBus TX5P_DPD0P TX5M_DPD0N SCL I2C SDA R AVSSN#1 GENERAL PURPOSE I/O GPIO_0 G GPIO_1 AVSSN#2 GPIO_2

AU22 AV21

B AVSSN#3

GPIO_5_AC_BATT GPIO_6 DAC1 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21 GPIO_22_ROMCSB CLKREQB GPIO_29 GPIO_30 GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF_HPD5 GENERICG_HPD6

AK24

[27] EXT_HDMI_HPD

R5014 EV@499/F_4

AH13

C5038 [email protected]/10V_4X

[25] PX_EN

+3V_D

R5016

PX4@0_4

R5017

*EV@0_4

AL21

PU:Disable MLPS PD:Enable MLPS

+3V_D

R5018

EV@1K_4

R5019

*[email protected]/F_4

AD28

T5038 T5042 T5043 T5044 T5045

AM23 AN23 AK23 AL24 AM24

T5037 T5039

AF29 AG29

R5020

EV@10K/F_4

AK32

R5021

*EV@10K/F_4

AL31

1.8V@8mA L5002

EV@BLM15BD121SN1D_300MA

on-die thermal sensor power

[27] [27]

EXT_HDMITX2P EXT_HDMITX2N

[27] [27]

AT23 AR22

AD39 AD37

EXT_CRT_RED

AE36 AD35

EXT_CRT_GRN

[28]

AF37 AE38

EXT_CRT_BLU

[28]

AC36 AC38

RSET

AB34

R5011

AVDD AVSSQ

AD34 AE34

AVDD

VDD1DI VSS1DI

AC33 AC34

VDD1DI

EXT_HSYNC EXT_VSYNC

R5008 ECRT@150/F_4

[18,28] [18,28]

R5009 ECRT@150/F_4

[28]

R5010 ECRT@150/F_4

SMBUS power plane isolate

EV@499/F_4

+3V_D

V13 U13 AC31 AD30 AC32 AD32 AF32 AA29 AG21

R5005 EV@10K/F_4

T5006

D3A

T5008 T5010 T5011 T5012 T5014 T5016

6

[27,37] 3ND_MBCLK

1

Q5047A

TSVDD

C5039

C5040

C5041

[email protected]/6.3V_6X

EV@1U/6.3V_4X

[email protected]/10V_4X

AJ32 AJ33

GPU_SMBCLK

EV@2N7002KDW_115MA

AF33

R5012

EV@0_4

NC_TSVSSQ should be tied to GND on Thames/Whistler/Seymour

PS_0

AM34

R5013

EV@0_4

PS_0 should be tied to GND on Thames/Whistler/Seymour

PS_1

AD31

NC_TSVSSQ

R5004 EV@10K/F_4

CEC_1 HPD1

MLPS

VREFG

PS_2

AG31

BACO PX_EN

PS_3

AD33

DEBUG

+1.8V_GPU

[27] [27]

EXT_HDMITX1P EXT_HDMITX1N

3

[27,37] 3ND_MBDATA

4

Q5047B GPU_VREFG

R5015 EV@249/F_4

AC30

EXT_HDMITX0P EXT_HDMITX0N

+3V_D

+1.8V_GPU T5024

[27] [27]

AU16 AV15

HSYNC VSYNC

NC#1 NC#2 NC#3 NC#4 NC#5 NC#6 NC#7 NC#8 NC#9

EXT_HDMICLK+ EXT_HDMICLK-

2

AJ21 AK21

TXCAP_DPA3P TXCAM_DPA3N

5

AD29 AC29

[18] GENIL_CLK [18] GENIL_VSYNC

MUTI GFX GENLK_CLK GENLK_VSYNC

TESTEN JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

THERMAL DPLUS DMINUS GPIO_28_FDO TS_A TSVDD TSVSS

DDC/AUX DDC1CLK DDC1DATA AUX1P AUX1N DDC2CLK DDC2DATA AUX2P AUX2N DDCCLK_AUX3P DDCDATA_AUX3N

GPU_SMBDAT

EV@2N7002KDW_115MA

PS_1,PS_2, PS_3 are NC on Thames/Whistler/Seymour

DAC Power +1.8V_GPU

AM26 AN26

EV_HDMI_DDCCLK EV_HDMI_DDCDAT

[27] [27]

EV_LVDS_DDCCLK EV_LVDS_DDCDAT

[28] [28]

AM27 AL27 AM19 AL19

AL30 AM30 AL29 AM29

DDCCLK_AUX5P DDCDATA_AUX5N

AN21 AM21

DDCCLK_AUX6P DDCDATA_AUX6N

AK30 AK29

DDCVGACLK DDCVGADATA

AJ30 AJ31

DAC1 Analog Power

1.8V@18mA AVDD

AN20 AM20

DDCCLK_AUX4P DDCDATA_AUX4N

HDMI

EV_CRTDCLK EV_CRTDDAT

[28] [28]

LVDS

L5000

C5032 C5033 [email protected]/10V_4X EV@1U/6.3V_4X

CRT

DAC1 Digital Power

1.8V@117mA VDD1DI

L5001

C5035 C5036 [email protected]/10V_4X EV@1U/6.3V_4X

EV_CRTDCLK_aux EV_CRTDDAT_aux

EV@BLM15BD121SN1D_300MA

C5034 [email protected]/6.3V_6X

EV@BLM15BD121SN1D_300MA

C5037 [email protected]/6.3V_6X

[28] [28]

Quanta Computer Inc.

B2A

PROJECT : Chief River

EV@HEATHROW M2 Size

Document Number

Rev A1A

02_Thames_M2/ GPIO_DP_CRT_I2C Date:

Wednesday, February 01, 2012

Sheet

16

of

48

VGA/GCK/LDV

17 Display phase-locked loop power.

B2A

1.8V@75mA Dedicated analog power pin for the display and DISPCLK PLLs. +1.8V_GPU

L5003

EV@PBY160808T-501Y-N_1.2A

DPE/DPF/LVDS

DPLL_PVDD R9588

U5000G

C5042

C5043

C5044

[email protected]/6.3V_6X

EV@1U/6.3V_4X

[email protected]/10V_4X

U5000I

OEV@10K_4

PART 7 0F 9

B2A

PART 9 0F 9

VARY_BL LVDS CONTROL DIGON

AK27 AJ27

TXCLK_UP_DPF3P TXCLK_UN_DPF3N

AK35 AL36

TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N

AJ38 AK37

TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N

AH35 AJ36

TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N

AG38 AH37

TXOUT_U3P TXOUT_U3N

AF35 AG36

EV_LVDS_BRIGHT [28] EV_LVDS_DIGON [28]

C3A

C5046

DPLL_VDDC

C5047

AN31

R5024 EV@1M/F_4

EV@1U/6.3V_4X

[email protected]/10V_4X

DPLL_PVSS

H7 H8

Memory phase-locked loop power. Dedicated analog power pin for the memory PLLs. MPLL_PVDD

EV@PBY160808T-501Y-N_1.2A

AM10

C5050

C5051

C5052

[email protected]/6.3V_6X

EV@1U/6.3V_4X

[email protected]/10V_4X AN9

AN10

Engine phase-locked loop power.

1.8V@75mA Dedicated analog power pin for the engine and UVD PLLs. +1.8V_GPU

L5006

EV@BLM15BD121SN1D_300MA C5053 [email protected]/6.3V_6X

EV@22P/50V_4N

Y5000 EV@27MHZ_20

AU34

GPU_XTALOUT

R5025

EV@0_4

C5049

SPLL_PVDD

SPLL_VDDC

XO_IN

AW34

T5040

XO_IN2

AW35

T5041

SPLL_PVSS

SPLL_PVDD

C5054

AF30 AF31

C5055

EV@1U/6.3V_4X

[email protected]/10V_4X

NC_XTAL_PVDD NC_XTAL_PVSS

CLKTESTA CLKTESTB

AK10 AL10

CLKTESTA CLKTESTB

+1V_GPU

EV@PBY160808T-501Y-N_1.2A

AP34 AR34

TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N

AW37 AU35

TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N

AR37 AU39

TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N

AP35 AR35

C5057 *[email protected]/10V_4X

R5026 *[email protected]/F_4

R5027 *[email protected]/F_4

Brazos use DPF interface to LVDS display

EV_TXLCLKOUT+ [28] EV_TXLCLKOUT- [28] EV_TXLOUT0+ [28] EV_TXLOUT0- [28] EV_TXLOUT1+ [28] EV_TXLOUT1- [28] EV_TXLOUT2+ [28] EV_TXLOUT2- [28]

AN36 AP37

EV@HEATHROW M2 EV@HEATHROW M2

SPLL_VDDC

C5058

C5059

C5060

[email protected]/6.3V_6X

EV@1U/6.3V_4X

[email protected]/10V_4X

DPLL_PVDD

TXCLK_LP_DPE3P TXCLK_LN_DPE3N

TXOUT_L3P TXOUT_L3N C5056 *[email protected]/10V_4X

Engine phase-locked loop power.

1V@150mA Dedicated digital power pin for the engine and UVD PLLs. L5007

B2A

EV@22P/50V_4N

MPLL_PVDD MPLL_PVDD PLLS/XTAL

1.8V@150mA L5005

C5045

DPLL_VDDC

XTALOUT

+1.8V_GPU

GPU_XTALIN

C5048 AN32

[email protected]/6.3V_6X

XTALIN

DPLL_PVDD

LVTMDP

+1V_GPU

EV@PBY160808T-501Y-N_1.2A

AV33

1

1V@140mA L5004

AM32

2

Display phase-locked loop power. Dedicated digital power pin for the display PLLs.

R5028

*EV@0_4

R5029

*EV@0_4

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Rev A1A

Thames_M2/ XTAL_LVDS Date:

Wednesday, February 01, 2012

Sheet

17

of

48

VGA/VGA-Strap

18

+3V_D

[16] GPU_GPIO0 [16] GPU_GPIO1 [16] GPU_GPIO2 [16] GPU_GPIO9 [16] GPU_GPIO11 [16] GPU_GPIO12 [16] GPU_GPIO13 [16] GPU_GPIO22 [16] GENIL_VSYNC [16,28] EXT_HSYNC

R5030

EV@10K_4

R5031

EV@10K_4

R5032

*EV@10K_4

R5033

*EV@10K_4

[16] GENIL_CLK [16] GPU_GPIO8 [16] GPU_GPIO21 [16] GPU_GENERICC [16] GPU_GPIO10

[16] RAM_STRAP1

R5047

Sam@10K_4

R5048

Hyn@10K_4

R5125

AMD@10K_4

R5049

AMD@10K_4

R5034

EV@10K_4

R5050

Sam@10K_4

R5035

*EV@10K_4

R5134

Hyn@10K_4

R5036

*EV@10K_4

R5038

*EV@10K_4

R5039

*EV@10K_4

R5041

OEV@10K_4

R5042

[16,28] EXT_VSYNC

[16] RAM_STRAP0

[16] RAM_STRAP2

+1.8V_GPU

CONFIGURATION STRAPS -- SEE EACH DATABOOK FOR STRAP DETAILS ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET +1.8V_GPU

R5051

2G@10K_4

+1.8V_GPU

R5127

1G8@10K_4

+1.8V_GPU

R5052

512M@10K_4

R5135

1G4@10K_4

R5151

4G@10K_4

R5053

1G4@10K_4

OEV@10K_4

R5043

*EV@10K_4

R5044

*EV@10K_4

R5045

*EV@10K_4

R5046

*EV@10K_4

R5145

*EV@10K_4

[16] RAM_STRAP3

[16] RAM_STRAP4

R5128

2G@10K_4

R5054

512M@10K_4

R5152

1G8@10K_4

R5153

4G@10K_4

R5055

4G@10K_4

R5056

512M@10K_4

R5154

1G4@10K_4

R5155

1G8@10K_4

R5156

2G@10K_4

MLPS

GPIO PIN

DESCRIPTION OF DEFAULT SETTINGS

MLPS_DISABLE

NA

GPIO_28_FDO

Enable MLPS, NA for Thames/Whistler/Seymour 0: Enable MLPS, disable GPIO PINSTRAP 1: Disable MLPS, enable GPIO PINSTRAP

TX_PWRS_ENB

PS_1[4]

GPIO0

Transmitter Power Savings Enable 0: 50% Tx output swing 1: Full Tx output swing

TX_DEEMPH_EN

PS_1[5]

GPIO1

PCIE Transmitter De-emphasis Enable 0: Tx de-emphasis disabled 1: Tx de-emphasis enabled

1

BIF_GEN3_EN_A

PS_1[1]

GPIO2

PCIE Gen3 Enable (NOTE: RESERVED for Thames/Whistler/Seymour) 0: GEN3 not supported at power-on 1: GEN3 supported at power-on

0

BIF_VGA DIS

PS_2[4]

GPIO9

VGA Control 0: VGA controller capacity enabled 1: VGA controller capacity disabled (for multi-GPU)

0

ROMIDCFG[2:0]

PS_0[3..1]

GPIO[13:11]

Serial ROM type or Memory Aperture Size Select

Vendor

Vendor P/N H5TQ1G63DFR-11C (64M*16)

Hynix

H5TQ2G63BFR-11C (128M*16)

H5TQ4G****** (256M*16)

K4W1G1646G-BC11 (64M*16)

STN B/S P/N

+1.8V_GPU

K4W2G1646C-HC11 (128M*16)

K4W4G****** (256M*16)

23EY2387MC11 (64M*16)

AMD

23EY4187MC11 (128M*16)

23EY********** (256M*16)

Size

RAM_STRAP4 DVPDATA_4

PS_2[3]

BIOS_ROM_EN

DVPDATA_2

DVPDATA_1

0

0

0

0

512@ & Hyn@

AKD5LZWTW02

*8

1GB

0

0

1

0

0

1G8@ & Hyn@

AK*************

AKD5EGGT500

*8

*4

0

1

0

2GB

0

1

1

4GB

1

0

0

512MB

0

0

0

0

0

1G4@ & Hyn@

0

0

2G@ & Hyn@

0

0

4G@ & Hyn@

0

1

512@ & Sam@ 1G8@ & Sam@

*8

1GB

0

0

1

0

1

1GB

0

1

0

0

1

1G4@ & Sam@

AKD5MGWT500 * 4

2GB

0

1

1

0

1

2G@ & Sam@

AKD5MGWT500 * 8

4GB

1

0

0

0

1

4G@ & Sam@

AK*************

512@ & AMD@

*8

AKD5EZWT700

*4

512MB

0

0

0

1

0

AKD5EZWT700

*8

1GB

0

0

1

1

0

*4

1GB

0

1

0

1

0

AKD5DZWT700 * 8

2GB

0

1

1

1

0

AK*************

4GB

1

0

0

1

0

AKD5DZWT700

*8

0

NA NA

HSYNC VSYNC

00 - No audio function 01 - Audio for DP only 10 - Audio for DP and HDMI if dongle is detected 11 - Audio for both DP and HDMI HDMI must only be enabled on systems that are legally entitled. It is the responsibility of the system designer to ensure that the system is entitled to support this feature.

XX

Enable CEC function. Reserved for Thames/Whistler/Seymour 0: Disabled 1: Enabled

CEC_DIS

PS_0[4]

GENLK_VSYNC

RESERVED RESERVED RESERVED RESERVED

PS_1[3] PS_1[2] NA NA

GENLK_CLK GPIO8 GPIO21 GENERICC

0

NOTE: ALLOW FOR PULLUP PADS FOR THE RESERVED STRAPS BUT DO NOT INSTALL RESISTOR IF THESE GPIOS ARE USEED, THEY MUST KEEP LOW AND NOT CONFLICT DURING RESET

0

AKD5MGWTW00 * 8

Enable external BIOS ROM device 0: Disabled 1: Enabled

DVPDATA_0

512MB

1GB

GPIO22

RAM_STRAP0

*4

AKD5MGWTW00 * 4

XXX

Vendor

RAM_STRAP3 RAM_STRAP2 RAM_STRAP1 DVPDATA_3

1

If GPIO22 = 0, defines memory aperture size If GPIO22 = 1, defines ROM type 100 - 512Kbit M25P05A (ST) 101 - 1Mbit M25P10A (ST) 101 - 2Mbit M25P20 (ST) 101 - 4Mbit M25P40 (ST) 101 - 8Mbit M25P80 (ST) 100 - 512Kbit Pm25LV512 (Chingis) 101 - 1Mbit Pm25LV010 (Chingis)

+1.8V_GPU

AKD5LZWTW02

AKD5EGGT500 Samsung

Size

1

+1.8V_GPU

AUD[1] AUD[0]

DDR3 Memory TYPE

MB Default Setting(IC internal PD)

STRAPS

AUD_PORT_CONN_PINSTRAP[2]

PS_3[5]

AUD_PORT_CONN_PINSTRAP[1]

PS_3[4]

AUD_PORT_CONN_PINSTRAP[0]

PS_0[5]

NA NA NA

0 0 0 0

Reserved Reserved Reserved Reserved (for Thames/Whistler/Seymour only)

STRAPS TO INDICATE THE NUMBER OF AUDIO CAPABLE DISPLAY OUTPUTS 111 = 0 usable endpoints 110 = 1 usable endpoints 101 = 2 usable endpoints 100 = 3 usable endpoints 011 = 4 usable endpoints 010 = 5 usable endpoints 001 = 6 usable endpoints 000 = all endpoints are usable

XXX

System Memory Aperture size GPIO22

GPIO13 GPIO12 GPIO11

BIOSROM

ROMIDCFG2

0 0 0 0

128M 256M 64M 32M

0 0 0 0

ROMIDCFG1 ROMIDCFG0

0 0 1 1

0 1 0 1

1G8@ & AMD@ 1G4@ & AMD@ 2G@ & AMD@ 4G@ & AMD@

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Rev A1A

Thames_M2/ STRAPS_Thermal Date:

Wednesday, February 01, 2012

Sheet

18

of

48

VGA

U5000E

C5071 EV@1U/6.3V_4X

C5080 [email protected]/10V_4X

C5088 [email protected]/10V_4X

C5063 [email protected]/6.3V_6X

C5084 EV@1U/6.3V_4X

C5064 [email protected]/6.3V_6X

C5072 EV@1U/6.3V_4X

C5081 [email protected]/10V_4X

C5089 [email protected]/10V_4X

C5065 [email protected]/6.3V_6X

C5073 EV@1U/6.3V_4X

C5082 [email protected]/10V_4X

C5090 [email protected]/10V_4X

C5074 EV@1U/6.3V_4X

C5085 EV@1U/6.3V_4X

C5075 EV@1U/6.3V_4X

C5083 [email protected]/10V_4X

C5091 [email protected]/10V_4X

MEM I/O VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1

NC_PCIE_VDDR NC_PCIE_VDDR NC_PCIE_VDDR NC_PCIE_VDDR NC_PCIE_VDDR NC_PCIE_VDDR NC_BIF_VDDC NC_BIF_VDDC PCIE_PVDD

BACO

(1.8V@17mA) L5009

EV@BLM15BD121SN1D_300MA

I/O power for 3.3-V pins, such as GPIOs.

VDDC_CT

C5099 [email protected]/6.3V_6X

C5100 EV@1U/6.3V_4X

C5101 [email protected]/10V_4X

(3.3V@60mA) +3V_D

L5010

C3A

EV@FCM1005KF-221T03_300MA

C5112 [email protected]/6.3V_6X

VDDR3

C5113 EV@1U/6.3V_4X

(1.8V@170mA) L5011

C3A

EV@FCM1005KF-221T03_300MA

C5125 [email protected]/6.3V_6X

[47] GPU_CORE_SEN [47] GPU_CORE_RTN

LEVEL TRANSLATION VDD_CT VDD_CT VDD_CT VDD_CT

AF23 AF24 AG23 AG24

I/O VDDR3 VDDR3 VDDR3 VDDR3

AD12 AF11 AF12 AF13

DVP VDDR4 VDDR4 VDDR4 VDDR4

C5114 EV@1U/6.3V_4X

Power for all DVP pins; DVPDATA_[23:0]—DVO or GPIO.

+1.8V_GPU

AF26 AF27 AG26 AG27

G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

BIF_VDDC BIF_VDDC

N27 T27

CORE

VDDR4

C5126 EV@1U/6.3V_4X

R9532 R9533

C5127 [email protected]/10V_4X

*EV@0_4 *EV@0_4

AF15 AG11 AG13 AG15

AF28 AG28 AH29

VDDR4 VDDR4 VDDR4 VDDR4

VOLTAGE SENESE FB_VDDC FB_VDDCI

AA31 AA32 AA33 AA34 W30 Y31 V28 W29 AB37

PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC

Level translation between core and I/O, excluding memory receivers.

+1.8V_GPU

19

(1.8V@440mA)

ISOLATED CORE I/O

C5062 [email protected]/6.3V_6X

AC7 AD11 AF7 AG10 AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10 J7 J9 K11 K13 K8 L12 L16 L21 L23 L26 L7 M11 N11 P7 R11 U11 U7 Y11 Y7

PCIE

([email protected] / DDR3 128bits 900MHz)

+1.8V_GPU

PCIe IO power.

PART 5 0F 9

+1.5V_GPU

FB_GND

EV@HEATHROW M2

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

AH22 AH27 AH28 M26 N24 R18 R21 R23 R26 T17 T20 T22 T24 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

PCIE_VDDR

L5008

C5066 [email protected]/25V_4X

C5067 [email protected]/10V_4X

C5068 EV@1U/6.3V_4X

C5069 EV@1U/6.3V_4X

C5070 [email protected]/6.3V_6X

+1V_GPU

PCIe digital power supply.

C5076 EV@1U/6.3V_4X

C5077 EV@1U/6.3V_4X

C5078 EV@1U/6.3V_4X

EV@HCB1608KF-181T15_1.5A

C5079 EV@1U/6.3V_4X

C5086 EV@1U/6.3V_4X

C5087 [email protected]/6.3V_6X

+BIF_VDDC Separate core power for the PCIe bus logic. In non-BACO designs, connect to VDDC. In BACO designs, must be the same voltage as VDDC when the GPU is operating, C5092 EV@1U/6.3V_4X

C5093 [email protected]/6.3V_6X

Dedicated core power, provides power to the internal logic. +VGPU_CORE

(0.9~1V@30A)

C5094 EV@1U/6.3V_4X

C5095 EV@1U/6.3V_4X

C5096 EV@1U/6.3V_4X

C5097 EV@1U/6.3V_4X

C5098 EV@1U/6.3V_4X

C5102 EV@1U/6.3V_4X

C5103 EV@1U/6.3V_4X

C5104 EV@1U/6.3V_4X

C5105 EV@1U/6.3V_4X

C5106 EV@1U/6.3V_4X

C5107 EV@1U/6.3V_4X

C5108 EV@1U/6.3V_4X

C5109 EV@1U/6.3V_4X

C5110 EV@1U/6.3V_4X

C5111 EV@1U/6.3V_4X

C5115 [email protected]/6.3V_6X

C5116 [email protected]/6.3V_6X

C5117 [email protected]/6.3V_6X

C5118 [email protected]/6.3V_6X

C5119 [email protected]/6.3V_6X

C5120 [email protected]/6.3V_6X

C5121 [email protected]/6.3V_6X

C5122 [email protected]/6.3V_6X

C5123 [email protected]/6.3V_6X

C5124 [email protected]/6.3V_6X

Isolated (clean) core power for the l/O logic.

([email protected] / DDR3 128bits 900MHz)

VDDCI

+VGPU_CORE

L5012

EV@HCB1608KF-121T30_3A

L5013

EV@HCB1608KF-121T30_3A

C5128 EV@1U/6.3V_4X

C5129 EV@1U/6.3V_4X

C5130 EV@1U/6.3V_4X

C5131 EV@1U/6.3V_4X

C5132 [email protected]/6.3V_6X

C5133 [email protected]/6.3V_6X

C5134 [email protected]/6.3V_6X

C5135 EV@1U/6.3V_4X

C5136 EV@1U/6.3V_4X

C5137 EV@1U/6.3V_4X

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Rev A1A

Thames_M2/ MainPower Date:

Wednesday, February 01, 2012

Sheet

19

of

48

VGA

20 DP/TMDS/LVDS Transmitter Power 0.935V@222mA per port

U5000H

(1V@222mA)

PART 8 0F 9 DP_VDDR DP/TMDS/LVDS Transmitter Power DP mode: 1.8V@188mA per port HDMI mode: 1.8V@237mA per port

AN24 AP24 AP25 AP26 AU28 AV29

(1.8V@237mA) +1.8V_GPU

L5015

EV@PBY160808T-501Y-N_1.2A C5138 [email protected]/6.3V_6X

DPAB_VDD18

C5139 EV@1U/6.3V_4X

C5140 [email protected]/10V_4X

AP20 AP21 AP22 AP23 AU18 AV19

(1.8V@237mA) +1.8V_GPU

L5018

EV@PBY160808T-501Y-N_1.2A C5150 [email protected]/6.3V_6X

DPCD_VDD18

C5151 EV@1U/6.3V_4X

C5152 [email protected]/10V_4X

(1.8V@237mA) +1.8V_GPU

L5019

DPEF_VDD18

EV@PBY160808T-501Y-N_1.2A C5153 [email protected]/6.3V_6X

C5154 EV@1U/6.3V_4X

AH34 AJ34 AF34 AG34 AM37 AL38

DP_VDDR DP_VDDR DP_VDDR DP_VDDR DP_VDDR DP_VDDR DP_VDDR DP_VDDR DP_VDDR DP_VDDR DP_VDDR DP_VDDR DP_VDDR DP_VDDR DP_VDDR DP_VDDR DP_VDDR DP_VDDR

C5155 [email protected]/10V_4X

CALIBRATION R5057

EV@150/F_4

AW28

R5058

EV@150/F_4

AW18

R5059

EV@150/F_4

AM39

DPAB_CALR DPCD_CALR DPEF_CALR

DPAB_VDD10

DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC

AP31 AP32 AN33 AP33

DP_VDDC DP_VDDC DP_VDDC DP_VDDC

AP13 AT13 AP14 AP15

DP_VDDC DP_VDDC DP_VDDC DP_VDDC

AL33 AM33 AK33 AK34

EV@PBY160808T-501Y-N_1.2A

C5141

C5142

C5143

[email protected]/6.3V_6X

EV@1U/6.3V_4X

[email protected]/10V_4X

+1V_GPU

(1V@222mA) DPCD_VDD10

L5016

EV@PBY160808T-501Y-N_1.2A

C5144

C5145

C5146

[email protected]/6.3V_6X

EV@1U/6.3V_4X

[email protected]/10V_4X

+1V_GPU

(1V@222mA) DPEF_VDD10

DP GND DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR

L5014

L5017

EV@PBY160808T-501Y-N_1.2A

C5147

C5148

C5149

[email protected]/6.3V_6X

EV@1U/6.3V_4X

[email protected]/10V_4X

AN27 AP27 AP28 AW24 AW26 AN29 AP29 AP30 AW30 AW32 AN17 AP16 AP17 AW14 AW16 AN19 AP18 AP19 AW20 AW22 AN34 AP39 AR39 AU37 AF39 AH39 AK39 AL34 AV27 AR28 AV17 AR18 AN38 AM35

+1V_GPU

E3A

+1V_GPU

C5584 EV@39P/50V_4N

C5585 EV@39P/50V_4N

EV@HEATHROW M2

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Rev A1A

Thames_M2/ DP_Powers Date:

Wednesday, February 01, 2012

Sheet

20

of

48

VGA

21

U5000F

PART 6 0F 9 AB39 E39 F34 F39 G33 G34 H31 H34 H39 J31 J34 K31 K34 K39 L31 L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39 W31 W34 Y34 Y39

PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS

GND F15 F17 F19 F21 F23 F25 F27 F29 F31 F33 F7 F9 G2 G6 H9 J2 J27 J6 J8 K14 K7 L11 L17 L2 L22 L24 L6 M17 M22 M24 N16 N18 N2 N21 N23 N26 N6 R15 R17 R2 R20 R22 R24 R27 R6 T11 T13 T16 T18 T21 T23 T26 U15 U17 U2 U20 U22 U24 U27 U6 V11 V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y22 Y24 Y27

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13

VSS_MECH VSS_MECH VSS_MECH

A39 AW1 AW39

EV@HEATHROW M2

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Rev A1A

Thames_M2/ GND Date:

Wednesday, February 01, 2012

Sheet

21

of

48

VGA [24] VMB_DM[7..0] U5000C

[24] VMB_RDQS[7..0]

PART 3 0F 9 VMA_DQ[63..0] VMA_DM[7..0]

[23] VMA_DM[7..0]

VMA_RDQS[7..0]

[23] VMA_RDQS[7..0]

VMA_WDQS[7..0]

[23] VMA_WDQS[7..0]

VMA_MA[14..0]

[23] VMA_MA[14..0]

VMA_BA0 VMA_BA1 VMA_BA2

[23] VMA_BA0 [23] VMA_BA1 [23] VMA_BA2

+1.5V_GPU

(0.7*VDDR1) Ra

Rb

R5060 [email protected]/F_4

R5062 EV@100/F_4

C5156 EV@1U/6.3V_4X

+1.5V_GPU

[24] VMB_WDQS[7..0]

GDDR5/DDR3

VMA_DQ0 VMA_DQ1 VMA_DQ2 VMA_DQ3 VMA_DQ4 VMA_DQ5 VMA_DQ6 VMA_DQ7 VMA_DQ8 VMA_DQ9 VMA_DQ10 VMA_DQ11 VMA_DQ12 VMA_DQ13 VMA_DQ14 VMA_DQ15 VMA_DQ16 VMA_DQ17 VMA_DQ18 VMA_DQ19 VMA_DQ20 VMA_DQ21 VMA_DQ22 VMA_DQ23 VMA_DQ24 VMA_DQ25 VMA_DQ26 VMA_DQ27 VMA_DQ28 VMA_DQ29 VMA_DQ30 VMA_DQ31 VMA_DQ32 VMA_DQ33 VMA_DQ34 VMA_DQ35 VMA_DQ36 VMA_DQ37 VMA_DQ38 VMA_DQ39 VMA_DQ40 VMA_DQ41 VMA_DQ42 VMA_DQ43 VMA_DQ44 VMA_DQ45 VMA_DQ46 VMA_DQ47 VMA_DQ48 VMA_DQ49 VMA_DQ50 VMA_DQ51 VMA_DQ52 VMA_DQ53 VMA_DQ54 VMA_DQ55 VMA_DQ56 VMA_DQ57 VMA_DQ58 VMA_DQ59 VMA_DQ60 VMA_DQ61 VMA_DQ62 VMA_DQ63

C37 C35 A35 E34 G32 D33 F32 E32 D31 F30 C30 A30 F28 C28 A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13 J13 H11 G10 G8 K9 K10 G9 A8 C8 E8 A6 C6 E6 A5

MVREFDA MVREFSA

L18 L20 MVREFDA

DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31

MEMORY INTERFACE A

[23] VMA_DQ[63..0]

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8 MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12 MAA1_5/MAA_BA2 MAA1_6/MAA_BA0 MAA1_7/MAA_BA1

G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17

VMA_MA0 VMA_MA1 VMA_MA2 VMA_MA3 VMA_MA4 VMA_MA5 VMA_MA6 VMA_MA7 VMA_MA8 VMA_MA9 VMA_MA10 VMA_MA11 VMA_MA12 VMA_BA2 VMA_BA0 VMA_BA1

WCKA0_0/DQMA_0 WCKA0B_0/DQMA_1 WCKA0_1/DQMA_2 WCKA0B_1/DQMA_3 WCKA1_0/DQMA_4 WCKA1B_0/DQMA_5 WCKA1_1/DQMA_6 WCKA1B_1/DQMA_7

A32 C32 D23 E22 C14 A14 E10 D9

VMA_DM0 VMA_DM1 VMA_DM2 VMA_DM3 VMA_DM4 VMA_DM5 VMA_DM6 VMA_DM7

EDCA0_0/QSA_0 EDCA0_1/QSA_1 EDCA0_2/QSA_2 EDCA0_3/QSA_3 EDCA1_0/QSA_4 EDCA1_1/QSA_5 EDCA1_2/QSA_6 EDCA1_3/QSA_7

C34 D29 D25 E20 E16 E12 J10 D7

VMA_RDQS0 VMA_RDQS1 VMA_RDQS2 VMA_RDQS3 VMA_RDQS4 VMA_RDQS5 VMA_RDQS6 VMA_RDQS7

DDBIA0_0/QSA_0B DDBIA0_1/QSA_1B DDBIA0_2/QSA_2B DDBIA0_3/QSA_3B DDBIA1_0/QSA_4B DDBIA1_1/QSA_5B DDBIA1_2/QSA_6B DDBIA1_3/QSA_7B

A34 E30 E26 C20 C16 C12 J11 F8

VMA_WDQS0 VMA_WDQS1 VMA_WDQS2 VMA_WDQS3 VMA_WDQS4 VMA_WDQS5 VMA_WDQS6 VMA_WDQS7

ADBIA0/ODTA0 ADBIA1/ODTA1

J21 G19

Thames@243/F_4 L27 Seymour@243/F_4 N12 Thames@243/F_4 AG12

R5067 R5068 R5069

Seymour@243/F_4 M12 Thames@243/F_4 M27 Thames@243/F_4 AH12

CLKA0 CLKA0B CLKA1 CLKA1B

J14 VMA_CLK1 H14 VMA_CLK1#

RASA0B RASA1B

K23 K19

VMA_RAS0# VMA_RAS1#

CASA0B CASA1B

K20 K17

VMA_CAS0# VMA_CAS1#

CSA0B_0 CSA0B_1

K24 K27

VMA_CS0#

CSA1B_0 CSA1B_1

M13 VMA_CS1# K16 K21 J20

VMA_CKE0 VMA_CKE1

NC_MEM_CALRN0 NC_MEM_CALRN1 NC_MEM_CALRN2

WEA0B WEA1B

K26 L15

VMA_WE0# VMA_WE1#

NC_MEM_CALRP1 MEM_CALRP0 MEM_CALRP2

MAA0_8/MAA_13 MAA1_8/MAA_14 MAA0_9/MAA_15 MAA1_9/RSVD

+1.5V_GPU

[24] VMB_BA0 [24] VMB_BA1 [24] VMB_BA2

VMA_ODT0 [23] VMA_ODT1 [23]

H27 VMA_CLK0 G27 VMA_CLK0#

CKEA0 CKEA1

MVREFSA

R5063 R5065 R5066

[24] VMB_MA[14..0]

VMA_CLK0 [23] VMA_CLK0# [23] VMA_CLK1 [23] VMA_CLK1# [23] VMA_RAS0# VMA_RAS1# VMA_CAS0# VMA_CAS1#

[23] [23] [23] [23]

VMA_CS0#

[23]

VMA_CS1#

[23]

VMA_CKE0 VMA_CKE1

[23] [23]

VMA_WE0# VMA_WE1#

[23] [23]

+1.5V_GPU

(0.7*VDDR1) Ra

Rb

VMB_DM[7..0] U5000D VMB_RDQS[7..0] VMB_WDQS[7..0]

VMB_MA[14..0]

VMB_BA0 VMB_BA1 VMB_BA2

VMB_DQ0 VMB_DQ1 VMB_DQ2 VMB_DQ3 VMB_DQ4 VMB_DQ5 VMB_DQ6 VMB_DQ7 VMB_DQ8 VMB_DQ9 VMB_DQ10 VMB_DQ11 VMB_DQ12 VMB_DQ13 VMB_DQ14 VMB_DQ15 VMB_DQ16 VMB_DQ17 VMB_DQ18 VMB_DQ19 VMB_DQ20 VMB_DQ21 VMB_DQ22 VMB_DQ23 VMB_DQ24 VMB_DQ25 VMB_DQ26 VMB_DQ27 VMB_DQ28 VMB_DQ29 VMB_DQ30 VMB_DQ31 VMB_DQ32 VMB_DQ33 VMB_DQ34 VMB_DQ35 VMB_DQ36 VMB_DQ37 VMB_DQ38 VMB_DQ39 VMB_DQ40 VMB_DQ41 VMB_DQ42 VMB_DQ43 VMB_DQ44 VMB_DQ45 VMB_DQ46 VMB_DQ47 VMB_DQ48 VMB_DQ49 VMB_DQ50 VMB_DQ51 VMB_DQ52 VMB_DQ53 VMB_DQ54 VMB_DQ55 VMB_DQ56 VMB_DQ57 VMB_DQ58 VMB_DQ59 VMB_DQ60 VMB_DQ61 VMB_DQ62 VMB_DQ63

MVREFDB MVREFSB

Rb

R5064 EV@100/F_4

C5 C3 E3 E1 F1 F3 F5 G4 H5 H6 J4 K6 K5 L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5 AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6 AG4 AH5 AH6 AJ4 AK3 AF8 AF9 AG8 AG7 AK9 AL7 AM8 AM7 AK1 AL4 AM6 AM1 AN4 AP3 AP1 AP5 Y12 AA12

PART 4 0F 9 GDDR5/DDR3 MAB0_0/MAB_0 DQB0_0 MAB0_1/MAB_1 DQB0_1 MAB0_2/MAB_2 DQB0_2 MAB0_3/MAB_3 DQB0_3 MAB0_4/MAB_4 DQB0_4 MAB0_5/MAB_5 DQB0_5 MAB0_6/MAB_6 DQB0_6 MAB0_7/MAB_7 DQB0_7 MAB1_0/MAB_8 DQB0_8 MAB1_1/MAB_9 DQB0_9 MAB1_2/MAB_10 DQB0_10 MAB1_3/MAB_11 DQB0_11 MAB1_4/MAB_12 DQB0_12 MAB1_5/BA2 DQB0_13 MAB1_6/BA0 DQB0_14 MAB1_7/BA1 DQB0_15 DQB0_16 WCKB0_0/DQMB_0 DQB0_17 WCKB0B_0/DQMB_1 DQB0_18 WCKB0_1/DQMB_2 DQB0_19 WCKB0B_1/DQMB_3 DQB0_20 WCKB1_0/DQMB_4 DQB0_21 WCKB1B_0/DQMB_5 DQB0_22 WCKB1_1/DQMB_6 DQB0_23 WCKB1B_1/DQMB_7 DQB0_24 DQB0_25 EDCB0_0/QSB_0 DQB0_26 EDCB0_1/QSB_1 DQB0_27 EDCB0_2/QSB_2 DQB0_28 EDCB0_3/QSB_3 DQB0_29 EDCB1_0/QSB_4 DQB0_30 EDCB1_1/QSB_5 DQB0_31 EDCB1_2/QSB_6 DQB1_0 EDCB1_3/QSB_7 DQB1_1 DQB1_2 DDBIB0_0/QSB_0B DQB1_3 DDBIB0_1/QSB_1B DQB1_4 DDBIB0_2/QSB_2B DQB1_5 DDBIB0_3/QSB_3B DQB1_6 DDBIB1_0/QSB_4B DQB1_7 DDBIB1_1/QSB_5B DQB1_8 DDBIB1_2/QSB_6B DQB1_9 DDBIB1_3/QSB_7B DQB1_10 DQB1_11 DQB1_12 ADBIB0/ODTB0 DQB1_13 ADBIB1/ODTB1 DQB1_14 CLKB0 DQB1_15 CLKB0B DQB1_16 DQB1_17 CLKB1 DQB1_18 CLKB1B DQB1_19 DQB1_20 DQB1_21 RASB0B DQB1_22 RASB1B DQB1_23 DQB1_24 CASB0B DQB1_25 CASB1B DQB1_26 DQB1_27 CSB0B_0 DQB1_28 CSB0B_1 DQB1_29 DQB1_30 CSB1B_0 DQB1_31 CSB1B_1 CKEB0 CKEB1

MVREFDB MVREFSB

WEB0B WEB1B

C5157 EV@1U/6.3V_4X

MAB0_8/MAB_13 MAB1_8/MAB_14 MAB0_9/MAB_15 MAB1_9/RSVD

H23 VMA_MA13 J19 VMA_MA14 M21 M20 +1.5V_GPU

(0.7*VDDR1) Ra

R5061 [email protected]/F_4

22

VMB_DQ[63..0]

MEMORY INTERFACE B

[24] VMB_DQ[63..0]

Ra

R5071 [email protected]/F_4

Rb

R5073 EV@100/F_4

EV@HEATHROW M2

C5158 EV@1U/6.3V_4X

VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_BA2 VMB_BA0 VMB_BA1

H3 H1 T3 T5 AE4 AF5 AK6 AK5

VMB_DM0 VMB_DM1 VMB_DM2 VMB_DM3 VMB_DM4 VMB_DM5 VMB_DM6 VMB_DM7

F6 K3 P3 V5 AB5 AH1 AJ9 AM5

VMB_RDQS0 VMB_RDQS1 VMB_RDQS2 VMB_RDQS3 VMB_RDQS4 VMB_RDQS5 VMB_RDQS6 VMB_RDQS7

QSB[7..0]

G7 K1 P1 W4 AC4 AH3 AJ8 AM3

VMB_WDQS0 VMB_WDQS1 VMB_WDQS2 VMB_WDQS3 VMB_WDQS4 VMB_WDQS5 VMB_WDQS6 VMB_WDQS7

QSB#[7..0]

T7 W7

VMB_ODT0 [24] VMB_ODT1 [24]

L9 L8

VMB_CLK0 VMB_CLK0#

VMB_CLK0 [24] VMB_CLK0# [24]

AD8 VMB_CLK1 AD7 VMB_CLK1#

VMB_CLK1 [24] VMB_CLK1# [24]

T10 VMB_RAS0# Y10 VMB_RAS1#

VMB_RAS0# VMB_RAS1#

W10 VMB_CAS0# AA10 VMB_CAS1#

VMB_CAS0# VMB_CAS1#

[24] [24] [24] [24]

P10 VMB_CS0# L10

VMB_CS0#

[24]

AD10 VMB_CS1# AC10

VMB_CS1#

[24]

VMB_CKE0 VMB_CKE1

[24] [24]

VMB_WE0# VMB_WE1#

[24] [24]

U10 VMB_CKE0 AA11 VMB_CKE1 N10 VMB_WE0# AB11 VMB_WE1# T8 VMB_MA13 W8 VMB_MA14 U12 V12 AH11

GPU_DRAM_RST

(0.7*VDDR1)

R5070 [email protected]/F_4

R5072 EV@100/F_4

DRAM_RST

P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9

Ball Name

Thames

MEM_CALRN0

243R

Seymour X

MEM_CALRN1

X

243R

MEM_CALRN2

243R

X

MEM_CALRP0

243R

X

MEM_CALRP1

X

243R

MEM_CALRP2

243R

X

EV@HEATHROW M2

C5159 EV@1U/6.3V_4X 25mm (max)

GPU_DRAM_RST

5mm (max)

R5074

25mm (max)

EV@10/F_4

R5076 [email protected]/F_4

R5075

[email protected]/F_4

MEM_RST# [23,24]

C5160 EV@120P/50V_4N

Place all these componets very close to GPU (within 25mm) and keep all components close to each other ** This basic topology should be used for DRAM_RAT for DDR3/GDDR5 These Capacitors and Resistor values arre an example only The series R and || cap values will depend on the DRAM loads and will have to be calculated for differrent Memory, DRAM loads and board to pass Reset Signal Spec

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Rev A1A

Thames_M2/ MEM Interface Date:

Wednesday, February 01, 2012

Sheet

22

of

48

5

[22] VMA_DQ[63..0] [22] VMA_DM[7..0] [22] VMA_RDQS[7..0] [22] VMA_WDQS[7..0] [22] VMA_MA[14..0]

4

3

2

CHANNEL A: 512MB DDR3 (64M*16*4pcs)

VMA_DQ[63..0] VMA_DM[7..0] VMA_RDQS[7..0]

QSA[7..0]

VMA_WDQS[7..0]

QSA#[7..0]

1

23

U5004 VMA_MA[14..0]

[22] [22] [22] [22] [22] [22] [22] [22] [22] [22] [22] [22] [22] [22] [22]

D

U5002

VMA_MA0 VMA_MA1 VMA_MA2 VMA_MA3 VMA_MA4 VMA_MA5 VMA_MA6 VMA_MA7 VMA_MA8 VMA_MA9 VMA_MA10 VMA_MA11 VMA_MA12 VMA_MA13 VMA_MA14

[22] VMA_BA0 [22] VMA_BA1 [22] VMA_BA2

[22] VMA_CLK0 [22] VMA_CLK0# [22] VMA_CKE0 [22] [22] [22] [22] [22]

VMA_ODT0 VMA_CS0# VMA_RAS0# VMA_CAS0# VMA_WE0#

C

VREFC_VMA1 VREFD_VMA1

M8 H1

VMA_MA0 VMA_MA1 VMA_MA2 VMA_MA3 VMA_MA4 VMA_MA5 VMA_MA6 VMA_MA7 VMA_MA8 VMA_MA9 VMA_MA10 VMA_MA11 VMA_MA12 VMA_MA13 VMA_MA14

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

VMA_BA0 VMA_BA1 VMA_BA2

M2 N8 M3

VMA_CLK0 VMA_CLK0# VMA_CKE0

J7 K7 K9

VMA_ODT0 VMA_CS0# VMA_RAS0# VMA_CAS0# VMA_WE0#

K1 L2 J3 K3 L3

VMA_RDQS0 VMA_RDQS3

F3 C7

VMA_DM0 VMA_DM3

E7 D3

VMA_WDQS0 VMA_WDQS3

G3 B7

MEM_RST#

T2

VMA_ZQ1

L8

VREFCA VREFDQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 BA0 BA1 BA2

CK CK CKE ODT CS RAS CAS WE

DQSL DQSU

DML DMU DQSL DQSU

RESET

[22,24] MEM_RST#

ZQ

R5077 Tham es @243/F_4 J1 L1 J9 L9

NC#J1 NC#L1 NC#J9 NC#L9

U5005

U5003

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

E3 F7 F2 F8 H3 H8 G2 H7

VMA_DQ5 VMA_DQ0 VMA_DQ6 VMA_DQ1 VMA_DQ4 VMA_DQ3 VMA_DQ7 VMA_DQ2

D7 C3 C8 C2 A7 A2 B8 A3

VMA_DQ24 VMA_DQ31 VMA_DQ27 VMA_DQ28 VMA_DQ25 VMA_DQ29 VMA_DQ26 VMA_DQ30

VREFC_VMA2 VREFD_VMA2

M8 H1

VMA_MA0 VMA_MA1 VMA_MA2 VMA_MA3 VMA_MA4 VMA_MA5 VMA_MA6 VMA_MA7 VMA_MA8 VMA_MA9 VMA_MA10 VMA_MA11 VMA_MA12 VMA_MA13 VMA_MA14

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

VMA_BA0 VMA_BA1 VMA_BA2

M2 N8 M3

VMA_CLK0 VMA_CLK0# VMA_CKE0

J7 K7 K9

+1.5V_GPU VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.5V_GPU A1 A8 C1 C9 D2 E9 F1 H2 H9

VMA_ODT0 VMA_CS0# VMA_RAS0# VMA_CAS0# VMA_WE0#

K1 L2 J3 K3 L3

VMA_RDQS1 VMA_RDQS2

F3 C7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VMA_DM1 VMA_DM2

E7 D3

B1 B9 D1 D8 E2 E8 F9 G1 G9

100-BALL SDRAM DDR3 Tham es @VRAM _DDR3

TOP Left

VMA_WDQS1 VMA_WDQS2

G3 B7

MEM_RST#

T2

VMA_ZQ2

L8

VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 BA0 BA1 BA2

CK CK CKE ODT CS RAS CAS WE

DQSL DQSU

DML DMU DQSL DQSU

RESET ZQ

R5078 Tham es @243/F_4 J1 L1 J9 L9

NC#J1 NC#L1 NC#J9 NC#L9

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D7 C3 C8 C2 A7 A2 B8 A3

VMA_DQ12 VMA_DQ14 VMA_DQ8 VMA_DQ11 VMA_DQ10 VMA_DQ15 VMA_DQ9 VMA_DQ13 VMA_DQ20 VMA_DQ19 VMA_DQ23 VMA_DQ17 VMA_DQ22 VMA_DQ16 VMA_DQ21 VMA_DQ18

VREFC_VMA3 VREFD_VMA3

M8 H1

VMA_MA0 VMA_MA1 VMA_MA2 VMA_MA3 VMA_MA4 VMA_MA5 VMA_MA6 VMA_MA7 VMA_MA8 VMA_MA9 VMA_MA10 VMA_MA11 VMA_MA12 VMA_MA13 VMA_MA14

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

VMA_BA0 VMA_BA1 VMA_BA2

M2 N8 M3

VMA_CLK1 VMA_CLK1# VMA_CKE1

J7 K7 K9

+1.5V_GPU VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

100-BALL SDRAM DDR3 Tham es @VRAM _DDR3

C3A

E3 F7 F2 F8 H3 H8 G2 H7

B2 D9 G7 K2 K8 N1 N9 R1 R9

[22] VMA_CLK1 [22] VMA_CLK1# [22] VMA_CKE1 +1.5V_GPU [22] [22] [22] [22] [22]

A1 A8 C1 C9 D2 E9 F1 H2 H9

VMA_ODT1 VMA_CS1# VMA_RAS1# VMA_CAS1# VMA_WE1#

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VMA_ODT1 VMA_CS1# VMA_RAS1# VMA_CAS1# VMA_WE1#

K1 L2 J3 K3 L3

VMA_RDQS6 VMA_RDQS4

F3 C7

VMA_DM6 VMA_DM4

E7 D3

VMA_WDQS6 VMA_WDQS4

G3 B7

MEM_RST#

T2

VMA_ZQ3

B1 B9 D1 D8 E2 E8 F9 G1 G9

L8

VREFCA VREFDQ

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

CK CK CKE ODT CS RAS CAS WE

DQSL DQSU

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

DML DMU

VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9

DQSL DQSU

RESET ZQ

NC#J1 NC#L1 NC#J9 NC#L9

E3 F7 F2 F8 H3 H8 G2 H7

VMA_DQ54 VMA_DQ50 VMA_DQ53 VMA_DQ49 VMA_DQ52 VMA_DQ51 VMA_DQ55 VMA_DQ48

VREFC_VMA4 VREFD_VMA4

M8 H1

VMA_MA0 VMA_MA1 VMA_MA2 VMA_MA3 VMA_MA4 VMA_MA5 VMA_MA6 VMA_MA7 VMA_MA8 VMA_MA9 VMA_MA10 VMA_MA11 VMA_MA12 VMA_MA13 VMA_MA14

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

D7 C3 C8 C2 A7 A2 B8 A3

VMA_DQ32 VMA_DQ36 VMA_DQ33 VMA_DQ37 VMA_DQ34 VMA_DQ39 VMA_DQ35 VMA_DQ38

VMA_BA0 VMA_BA1 VMA_BA2

M2 N8 M3

VMA_CLK1 VMA_CLK1# VMA_CKE1

J7 K7 K9

A1 A8 C1 C9 D2 E9 F1 H2 H9

VMA_ODT1 VMA_CS1# VMA_RAS1# VMA_CAS1# VMA_WE1#

K1 L2 J3 K3 L3

VMA_RDQS5 VMA_RDQS7

F3 C7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VMA_DM5 VMA_DM7

E7 D3

VMA_WDQS5 VMA_WDQS7

G3 B7

MEM_RST#

T2

+1.5V_GPU

BA0 BA1 BA2

R5079 Tham es @243/F_4 J1 L1 J9 L9

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.5V_GPU

B1 B9 D1 D8 E2 E8 F9 G1 G9

100-BALL SDRAM DDR3 Tham es @VRAM _DDR3

C3A

VMA_ZQ4

J1 L1 J9 L9

Group-A0 VREF

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 BA0 BA1 BA2

CK CK CKE ODT CS RAS CAS WE

DQSL DQSU DML DMU DQSL DQSU

RESET ZQ

R5080 Tham es @243/F_4 NC#J1 NC#L1 NC#J9 NC#L9

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

E3 F7 F2 F8 H3 H8 G2 H7

VMA_DQ46 VMA_DQ45 VMA_DQ44 VMA_DQ40 VMA_DQ41 VMA_DQ42 VMA_DQ43 VMA_DQ47

D7 C3 C8 C2 A7 A2 B8 A3

VMA_DQ61 VMA_DQ58 VMA_DQ63 VMA_DQ56 VMA_DQ60 VMA_DQ59 VMA_DQ62 VMA_DQ57

D

+1.5V_GPU VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.5V_GPU A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

C

B1 B9 D1 D8 E2 E8 F9 G1 G9

100-BALL SDRAM DDR3 Tham es @VRAM _DDR3

C3A

BOT Right

BOT Left

L8

VREFCA VREFDQ

C3A

TOP Right

Group-A1 VREF

+1.5V_GPU

+1.5V_GPU

+1.5V_GPU

+1.5V_GPU

R5081

R5082

R5083

R5084

Tham es @4.99K/F_4

Tham es @4.99K/F_4

Tham es @4.99K/F_4

Tham es @4.99K/F_4

+1.5V_GPU

+1.5V_GPU

+1.5V_GPU

+1.5V_GPU

R5085

R5086

R5087

R5088

B

B

Tham es @4.99K/F_4 VREFC_VMA1

VREFD_VMA1

VREFC_VMA2

Tham es @4.99K/F_4

VREFC_VMA3 C5161

R5090

C5162

R5091

C5163

R5092

C5164

Tham es @4.99K/F_4

Tham es @0.1U/10V_4X

Tham es @4.99K/F_4

Tham es @0.1U/10V_4X

Tham es @4.99K/F_4

Tham es @0.1U/10V_4X

Tham es @4.99K/F_4

Tham es @0.1U/10V_4X

Group-A0 decoupling CAP

MEM_A0 CLK

Tham es @4.99K/F_4

Tham es @4.99K/F_4

VREFD_VMA2

R5089

VREFD_VMA3

VREFC_VMA4

VREFD_VMA4

R5093

C5165

R5094

C5166

R5095

C5167

R5096

C5168

Tham es @4.99K/F_4

Tham es @0.1U/10V_4X

Tham es @4.99K/F_4

Tham es @0.1U/10V_4X

Tham es @4.99K/F_4

Tham es @0.1U/10V_4X

Tham es @4.99K/F_4

Tham es @0.1U/10V_4X

Group-A1 decoupling CAP MEM_A1 CLK

+1.5V_GPU +1.5V_GPU VMA_CLK0

VMA_CLK1

VMA_CLK0# C5169 Tham es @0.1U/10V_4X R5097 Tham es @40.2/F_4

C5170 Tham es @0.1U/10V_4X

C5171 Tham es @0.1U/10V_4X

C5178 Tham es @0.1U/10V_4X

C5179 Tham es @0.1U/10V_4X

C5180 Tham es @0.1U/10V_4X

C5181 Tham es @0.1U/10V_4X

C5172 Tham es @0.1U/10V_4X

C5182 Tham es @0.1U/10V_4X

C5173 Tham es @0.1U/10V_4X

C5174 Tham es @0.1U/10V_4X

C5175 Tham es @0.1U/10V_4X

C5176 Tham es @0.1U/10V_4X

C5177 Tham es @0.1U/10V_4X

C5183 Tham es @0.1U/10V_4X

VMA_CLK1#

C5184 Tham es @0.1U/10V_4X

R5098 Tham es @40.2/F_4

R5099 Tham es @40.2/F_4

+1.5V_GPU

R5100 Tham es @40.2/F_4

+1.5V_GPU

A

C5189 Tham es @0.01U/25V_4X

C5186 Tham es @1U/6.3V_4X

C5187 Tham es @1U/6.3V_4X

C5188 Tham es @1U/6.3V_4X

C5196 Tham es @1U/6.3V_4X

C5197 Tham es @1U/6.3V_4X

C5198 Tham es @1U/6.3V_4X

C5199 Tham es @1U/6.3V_4X

C5190 Tham es @1U/6.3V_4X

C5200 Tham es @1U/6.3V_4X

C5191 Tham es @1U/6.3V_4X

C5192 Tham es @1U/6.3V_4X

C5193 Tham es @1U/6.3V_4X

C5194 Tham es @1U/6.3V_4X

C5195 Tham es @1U/6.3V_4X

C5201 Tham es @1U/6.3V_4X

C5202 Tham es @1U/6.3V_4X

C5185 Tham es @0.01U/25V_4X

A

+1.5V_GPU +1.5V_GPU

C5203 Tham es @4.7U/6.3V_6X

C5204 Tham es @4.7U/6.3V_6X

C5205 Tham es @4.7U/6.3V_6X

C5206 Tham es @4.7U/6.3V_6X

C5208 Tham es @4.7U/6.3V_6X

C5207 Tham es @4.7U/6.3V_6X

C5209 Tham es @4.7U/6.3V_6X

C5210 Tham es @4.7U/6.3V_6X

C5211 Tham es @4.7U/6.3V_6X

C5212 Tham es @4.7U/6.3V_6X

Quanta Computer Inc.

C3A

C3A

PROJECT : Chief River Size

Docum ent Num ber

Date:

Wednes day, February 01, 2012

Rev A1A

VRAM_A: DDR3*4PCS 5

4

3

2

1

Sheet

23

of

48

5

3

2

CHANNEL B: 512MB DDR3 (64M*16*4pcs)

VMB_DQ[63..0]

[22] VMB_DQ[63..0]

1

24

VMB_DM[7..0]

[22] VMB_DM[7..0] [22] VMB_RDQS[7..0] [22] VMB_WDQS[7..0]

VMB_RDQS[7..0]

QSA[7..0]

VMB_WDQS[7..0]

QSA#[7..0] U5006

U5007

U5008

U5009

VMB_MA[14..0]

[22] VMB_MA[14..0]

[22] VMB_MA0 [22] VMB_MA1 [22] VMB_MA2 [22] VMB_MA3 [22] VMB_MA4 [22] VMB_MA5 [22] VMB_MA6 [22] VMB_MA7 [22] VMB_MA8 [22] VMB_MA9 [22] VMB_MA10 [22] VMB_MA11 [22] VMB_MA12 [22] VMB_MA13 [22] VMB_MA14

D

4

[22] VMB_BA0 [22] VMB_BA1 [22] VMB_BA2

[22] VMB_CLK0 [22] VMB_CLK0# [22] VMB_CKE0

[22] [22] [22] [22] [22]

VMB_ODT0 VMB_CS0# VMB_RAS0# VMB_CAS0# VMB_WE0#

C

VREFC_VMB1 VREFD_VMB1

M8 H1

VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_MA13 VMB_MA14

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

VMB_BA0 VMB_BA1 VMB_BA2

M2 N8 M3

VMB_CLK0 VMB_CLK0# VMB_CKE0

J7 K7 K9

VMB_ODT0 VMB_CS0# VMB_RAS0# VMB_CAS0# VMB_WE0#

K1 L2 J3 K3 L3

VMB_RDQS2 VMB_RDQS3

F3 C7

VMB_DM2 VMB_DM3

E7 D3

VMB_WDQS2 VMB_WDQS3

G3 B7

MEM_RST#

T2

VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

CK CK CKE ODT CS RAS CAS WE

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

DQSL DQSU DML DMU

VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9

DQSL DQSU

RESET

L8

ZQ

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

R5101 EV@243/F_4

J1 L1 J9 L9

E3 F7 F2 F8 H3 H8 G2 H7

VMB_DQ23 VMB_DQ16 VMB_DQ21 VMB_DQ17 VMB_DQ22 VMB_DQ19 VMB_DQ20 VMB_DQ18

D7 C3 C8 C2 A7 A2 B8 A3

VMB_DQ26 VMB_DQ30 VMB_DQ28 VMB_DQ31 VMB_DQ24 VMB_DQ27 VMB_DQ25 VMB_DQ29

VREFC_VMB2 VREFD_VMB2

M8 H1

VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_MA13 VMB_MA14

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

VMB_BA0 VMB_BA1 VMB_BA2

M2 N8 M3

VMB_CLK0 VMB_CLK0# VMB_CKE0

J7 K7 K9

+1.5V_GPU

BA0 BA1 BA2

[22,23] MEM_RST# VMB_ZQ1

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

NC#J1 NC#L1 NC#J9 NC#L9

B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.5V_GPU

A1 A8 C1 C9 D2 E9 F1 H2 H9

VMB_ODT0 VMB_CS0# VMB_RAS0# VMB_CAS0# VMB_WE0#

K1 L2 J3 K3 L3

VMB_RDQS0 VMB_RDQS1

F3 C7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VMB_DM0 VMB_DM1

E7 D3

VMB_WDQS0 VMB_WDQS1

G3 B7

MEM_RST# VMB_ZQ2

B1 B9 D1 D8 E2 E8 F9 G1 G9

T2 L8

J1 L1 J9 L9

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 BA0 BA1 BA2

CK CK CKE ODT CS RAS CAS WE DQSL DQSU DML DMU DQSL DQSU

RESET ZQ

R5102 EV@243/F_4

100-BALL SDRAM DDR3 EV@VRAM _DDR3

BOT Down

VREFCA VREFDQ

NC#J1 NC#L1 NC#J9 NC#L9

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

E3 F7 F2 F8 H3 H8 G2 H7

VMB_DQ1 VMB_DQ4 VMB_DQ2 VMB_DQ5 VMB_DQ0 VMB_DQ7 VMB_DQ3 VMB_DQ6

D7 C3 C8 C2 A7 A2 B8 A3

VMB_DQ15 VMB_DQ10 VMB_DQ14 VMB_DQ8 VMB_DQ12 VMB_DQ9 VMB_DQ13 VMB_DQ11

M8 H1

VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_MA13 VMB_MA14

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

VMB_BA0 VMB_BA1 VMB_BA2

M2 N8 M3

VMB_CLK1 VMB_CLK1# VMB_CKE1

J7 K7 K9

+1.5V_GPU

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

B2 D9 G7 K2 K8 N1 N9 R1 R9

[22] VMB_CLK1 [22] VMB_CLK1# [22] VMB_CKE1

+1.5V_GPU

A1 A8 C1 C9 D2 E9 F1 H2 H9

[22] [22] [22] [22] [22]

VMB_ODT1 VMB_CS1# VMB_RAS1# VMB_CAS1# VMB_WE1#

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VMB_ODT1 VMB_CS1# VMB_RAS1# VMB_CAS1# VMB_WE1#

K1 L2 J3 K3 L3

VMB_RDQS6 VMB_RDQS5

F3 C7

VMB_DM6 VMB_DM5

E7 D3

VMB_WDQS6 VMB_WDQS5

G3 B7

MEM_RST#

T2 L8

VMB_ZQ3

B1 B9 D1 D8 E2 E8 F9 G1 G9

VREFCA VREFDQ

J1 L1 J9 L9

100-BALL SDRAM DDR3 EV@VRAM _DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 BA0 BA1 BA2

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

CK CK CKE ODT CS RAS CAS WE

DML DMU

VREFC_VMB4 VREFD_VMB4

M8 H1

VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_MA13 VMB_MA14

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

D7 C3 C8 C2 A7 A2 B8 A3

VMB_DQ41 VMB_DQ47 VMB_DQ40 VMB_DQ46 VMB_DQ44 VMB_DQ45 VMB_DQ43 VMB_DQ42

VMB_BA0 VMB_BA1 VMB_BA2

M2 N8 M3

VMB_CLK1 VMB_CLK1# VMB_CKE1

J7 K7 K9

A1 A8 C1 C9 D2 E9 F1 H2 H9

VMB_ODT1 VMB_CS1# VMB_RAS1# VMB_CAS1# VMB_WE1#

K1 L2 J3 K3 L3

VMB_RDQS7 VMB_RDQS4

F3 C7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VMB_DM7 VMB_DM4

E7 D3

VMB_WDQS7 VMB_WDQS4

G3 B7

+1.5V_GPU

VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9

DQSL DQSU

RESET ZQ

NC#J1 NC#L1 NC#J9 NC#L9

VMB_DQ55 VMB_DQ51 VMB_DQ54 VMB_DQ50 VMB_DQ52 VMB_DQ49 VMB_DQ53 VMB_DQ48

+1.5V_GPU

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

DQSL DQSU

E3 F7 F2 F8 H3 H8 G2 H7

B2 D9 G7 K2 K8 N1 N9 R1 R9

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

R5103 EV@243/F_4

L8

VMB_ZQ4

B1 B9 D1 D8 E2 E8 F9 G1 G9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

T2

MEM_RST#

VREFCA VREFDQ

J1 L1 J9 L9

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 BA0 BA1 BA2

CK CK CKE ODT CS RAS CAS WE DQSL DQSU DML DMU DQSL DQSU

RESET ZQ

R5104 EV@243/F_4

100-BALL SDRAM DDR3 EV@VRAM _DDR3

C3A

NC#J1 NC#L1 NC#J9 NC#L9

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

E3 F7 F2 F8 H3 H8 G2 H7

VMB_DQ62 VMB_DQ61 VMB_DQ63 VMB_DQ60 VMB_DQ59 VMB_DQ58 VMB_DQ57 VMB_DQ56

D7 C3 C8 C2 A7 A2 B8 A3

VMB_DQ38 VMB_DQ32 VMB_DQ36 VMB_DQ33 VMB_DQ37 VMB_DQ35 VMB_DQ39 VMB_DQ34 +1.5V_GPU

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.5V_GPU

A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

C

B1 B9 D1 D8 E2 E8 F9 G1 G9

C3A

TOP Down

D

100-BALL SDRAM DDR3 EV@VRAM _DDR3

C3A

C3A

TOP Up

Group-B0 VREF

BOT Up

Group-B1 VREF +1.5V_GPU

B

VREFC_VMB3 VREFD_VMB3

+1.5V_GPU

R5105 [email protected]/F_4

+1.5V_GPU

R5106 [email protected]/F_4

VREFC_VMB1

+1.5V_GPU

R5107 [email protected]/F_4

VREFD_VMB1

+1.5V_GPU

R5108 [email protected]/F_4

VREFC_VMB2

+1.5V_GPU

R5109 [email protected]/F_4

VREFD_VMB2

+1.5V_GPU

R5110 [email protected]/F_4

VREFC_VMB3

+1.5V_GPU

R5111 [email protected]/F_4

VREFD_VMB3

VREFC_VMB4

VREFD_VMB4

R5113

C5213

R5114

C5214

R5115

C5215

R5116

C5216

R5117

C5217

R5118

C5218

R5119

C5219

R5120

C5220

[email protected]/F_4

[email protected]/10V_4X

[email protected]/F_4

[email protected]/10V_4X

[email protected]/F_4

[email protected]/10V_4X

[email protected]/F_4

[email protected]/10V_4X

[email protected]/F_4

[email protected]/10V_4X

[email protected]/F_4

[email protected]/10V_4X

[email protected]/F_4

[email protected]/10V_4X

[email protected]/F_4

[email protected]/10V_4X

Group-B0 decoupling CAP

MEM_B0 CLK

Group-B1 decoupling CAP

+1.5V_GPU

MEM_B1 CLK

+1.5V_GPU

C3A

VMB_CLK1

VMB_CLK0

C5221

C5222

C5223

C5224

C5225

C5226

C5227

C5228

C5229

C5230

C5231

C5232

C5233

C5234

C5235

VMB_CLK0#

[email protected]/10V_4X

[email protected]/10V_4X

[email protected]/10V_4X

[email protected]/10V_4X

[email protected]/10V_4X

[email protected]/10V_4X

[email protected]/10V_4X

EV@1U/6.3V_4X

EV@1U/6.3V_4X

EV@1U/6.3V_4X

EV@1U/6.3V_4X

EV@1U/6.3V_4X

EV@1U/6.3V_4X

EV@1U/6.3V_4X

EV@1U/6.3V_4X

R5123

VMB_CLK1#

R5124 +1.5V_GPU

[email protected]/F_4

B

R5112 [email protected]/F_4

R5121

R5122

[email protected]/F_4

[email protected]/F_4

+1.5V_GPU

[email protected]/F_4

A

C5237 [email protected]/25V_4X

C5238

C5239

C5240

C5241

C5242

C5243

C5244

C5245

C5246

C5247

C5248

C5249

C5250

C5251

C5252

EV@1U/6.3V_4X

EV@1U/6.3V_4X

EV@1U/6.3V_4X

EV@1U/6.3V_4X

EV@1U/6.3V_4X

EV@1U/6.3V_4X

EV@1U/6.3V_4X

EV@1U/6.3V_4X

[email protected]/10V_4X

[email protected]/10V_4X

[email protected]/10V_4X

[email protected]/10V_4X

[email protected]/10V_4X

[email protected]/10V_4X

[email protected]/10V_4X

+1.5V_GPU

A

C5236 [email protected]/25V_4X

+1.5V_GPU

C3A C5253

C5254

C5255

C5256

C5257

C5258

C5259

C5260

C5261

C5262

[email protected]/6.3V_6X

[email protected]/6.3V_6X

[email protected]/6.3V_6X

[email protected]/6.3V_6X

[email protected]/6.3V_6X

[email protected]/6.3V_6X

[email protected]/6.3V_6X

[email protected]/6.3V_6X

[email protected]/6.3V_6X

[email protected]/6.3V_6X

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Rev A1A

VRAM_B: DDR3*4PCS Date: 5

4

3

2

Wednesday, February 01, 2012 1

Sheet

24

of

48

5

4

VGA Power Enable Reverse (Intel --> Low Active)

PX

Platform Reset

3

2

PX/OEV

1

PX4/PX5

PX Mode control signal

25

+3V

+3V +3V D

C5263 R5147 PX@1K_4

5

R5126 PX4@10K_4 +3V DGPU_PWR_EN

2

DGPU_PWR_EN

[48]

D

[email protected]/10V_4X

4

PX_MODE

PX_MODE [47,48]

C5559

[email protected]/10V_4X

3

PX_EN =0, for Normal operation PX_EN =1, for BACO MODE

3

3

1 U5010 PX4@TC7SH08FU(F)

2

[9] DGPU_HOLD_RST#

2

[9] VGA_PLTRST#

1

PERST#_BUF

PERST#_BUF

Q5046 PX4@ME2N7002E_200MA

R5129

[15]

R5136

PX5@0_4

1

4

[email protected]/F_4

3

1

Q5049 PX@ME2N7002E_200MA

2

[16] PX_EN

5

[9] DGPU_PWR_EN_R

U5034 PX@TC7SH08FU(F)

C

C

R5149

PX4/PX5/OEV

Core power for PCIE Logic

OEV@0_4

+VGPU_CORE +5V

VGA/PX4/PX5/OEV

3.3V

Designs that do not support the BACO option must connect the BIF_VDDC to VDDC

+5V

R5148

OEV@0_4

R5130

PX5@0_4 +3V

1

R5131 PX4@1K/F_4

2

+3V

3

3

PX_Q

Q5003 PX4@PMV45EN_4A

1

B

1

R5132 PX4@1K/F_4

2

B

Q5004 PX4@PMV45EN_4A +BIF_VDDC

R5146 OEV@0_6

R5150 PX4@0_6

DGPU_PWR_EN_R2 +BIF_+1V_EN

+BIF_CORE_EN

5

PX_PWRGOOD_Q 2

+3V_D

2 +1V_GPU

1 U5011 PX4@TC7SH08FU(F)

Q5006 PX4@ME2N7002E_200MA

Q5005

R5139

*0_4

C5266

C5267

C5268

*EV@10U/6.3V_6X

EV@1U/6.3V_4X

[email protected]/10V_4X

1

DGPU_PWROK

3

0,37,47,48]

3

2 4

GPU +3V power 0.5A

PX4@22U/6.3V_8X

1

PX_MODE

Q5001 PX5@ME1303_3A

C5269

3

[email protected]/10V_4X

3

C5270

PX4@ME2N7002E_200MA

3

A

3

PX_L

Q5000 PX4@PMV45EN_4A

1

2

2

1

Q5007 PX4@PMV45EN_4A A

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Date:

Wednesday, February 01, 2012

Rev A1A

Thames_M2/ Baco 5

4

3

2

Sheet 1

25

of

48

5

4

S3 power Reduction (SM_DRAMRST#)

3

2

1

S3 power Reduction (SM_DRAMPWROK)

S3P/NS3P/CPU

S3P/NS3P/CPU

26

+3V_S5 +1.5VSUS D

D

+1.5V_CPU

3

DDR3_DRAMRST#_R

1K/F_4

NS3@0_4

1

R9516

S3@0_4

CPU_DRAMRST#

[3]

S3@ME2N7002E_200MA

DRAMRST_CNTRL_PCH_R

4 PM_DRAM_PWRGD_Q

PM_DRAM_PWRGD_R

R9515

130/F_4

R9518

*S3@39/F_4 3

PM_DRAM_PWRGD_R

1

[7] PM_DRAM_PWRGD

U5012 C5272 [email protected]/10V_4X

R9514 200/F_4

2

[7] SYS_PWROK_R

2

Q5008 [6,9] DRAMRST_CNTRL_PCH

C5271 [email protected]/10V_4X

5

R9513

[13,14] DDR3_DRAMRST#

R9512

R9517 [email protected]/F_4

S3@TC7SH08FU(F)

3

R9511 1K/F_4

[3]

1 *S3@2N7002K_300MA 2

Q5009 R9519

For S3 power Reduction Sequence

S3P/NS3P/CPU

NS3@0_4

S3 power Reduction (CPU Power)

C

+SMDDR_VREF +3V_S5 R9520

MAINON_ON_G

+VDDR_REF_CPU

S3P/NS3P/CPU +1.5VSUS

+1.5V_CPU

+1.5V_CPU

+1.5VSUS

R9523

NS3@0_8

3

S3@10K_4

4

NS3@0_1206

2

MAINON_ON_G

2

R9528

S3@2N7002KDW_115MA MAIND

R9527 100K_4

S3@1K_4

C5273 *0.1U/10V_4X

4 Q5010 S3@AO6402A

C5274 *0.1U/10V_4X

C5275 *0.1U/10V_4X

C5276 *0.1U/10V_4X

+1.5V_CPU

C5277 *S3@470P/50V_4X

R9529 S3@220_8 3

Q5013 S3@FDV301N_200MA 1

6

4

Q5014B S3@2N7002KDW_115MA

MAIND

5

3

[41,42,46] MAIND

3

3

S3@TC7SH08FU(F)

5

C5278 *[email protected]/10V_4X

[46]

[46] MAINON_ON_G

2

Q5014A S3@2N7002KDW_115MA

B

Q5015 S3@ME2N7002E_200MA 1

1

R9524

3

5

S3@10K_4

[37,43,46]

Q5016B

B

NS3@0_1206

6 5 2 1

R9525 MAINON

1 U5013

R9521 R9522 2

S3@100K_4 4

R9526

C

NS3@0_6 +3V_S5

[42] S3_1.5V

[46]

For S3 power Reduction VTT discharge

S3P/NS3P/CPU

+SMDDR_VTERM

R9534

6

S3@22_4

A

2

A

Q5016A 1

[46] MAINON_ON_G

S3@2N7002KDW_115MA

Quanta Computer Inc. PROJECT : Chief River Size

Docum ent Num ber

Rev A1A

S3 power Reduction Date: 5

4

3

2

Wednes day, February 01, 2012 1

Sheet

26

of

48

5

4

3

HDMI Conn HDM/HMU/HMV [16] EXT_HDMITX2P [16] EXT_HDMITX2N [7] INT_HDMITX2P [7] INT_HDMITX2N

2

HDMI CEC

C434 C426

[email protected]/10V_4X [email protected]/10V_4X

C2002 C2001

[email protected]/10V_4X [email protected]/10V_4X

1

CEC

27

HDMITX2_R HDMITX2#_R

E3A EXT_HDMITX2P

R4565

EHM@100_4

EXT_HDMITX2N

EXT_HDMITX1P

R4566

EHM@100_4

EXT_HDMITX1N

EXT_HDMITX0P

R4567

EHM@100_4

EXT_HDMITX0N

EXT_HDMICLK+

R4571

EHM@100_4

EXT_HDMICLK-

+3VPCU C418 C415

[16] EXT_HDMITX1P [16] EXT_HDMITX1N

C2004 C2003

[7] INT_HDMITX1P [7] INT_HDMITX1N

D

[16] EXT_HDMITX0P [16] EXT_HDMITX0N

[7] INT_HDMITX0P [7] INT_HDMITX0N

[email protected]/10V_4X [email protected]/10V_4X

C444 C440

[email protected]/10V_4X [email protected]/10V_4X

C2006 C2005

[email protected]/10V_4X [email protected]/10V_4X

C448 C446

[16] EXT_HDMICLK+ [16] EXT_HDMICLK-

HDMITX1_R HDMITX1#_R

[email protected]/10V_4X [email protected]/10V_4X

C5279

C5280

CEC@1U/6.3V_4X

[email protected]/10V_4X

U5014 7 16

HDMITX0_R HDMITX0#_R

+3VPCU

RP18 3 1

4 [email protected] 2

XIN_CEC XOUT_CEC

4 6

RP14 3 1

4 [email protected] 2

CEC-RESET# CEC-MODE

3 8 5 15 14 11

HDMICLK_R HDMICLK#_R

[email protected]/10V_4X [email protected]/10V_4X

VCC VCC XOUT XIN RESET MODE VSS NC NC NC

SCL SDA DDCSDA DDCSCL TEST1 TEST0 CEC OUT CEC IN HPDET NC

1 20 18 17

CEC_SCLK CEC_SDATA HDMI_CEC_DDCDATA HDMI_CEC_DDCCLK

13 12

CEC-TEST1 CEC-TEST2

10 9

CEC_OUT CEC_IN

19 2

HPDET

C2008 C2007

[email protected]/10V_4X [email protected]/10V_4X

CN2001 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

HDMITX2_R HDMITX2#_R HDMITX1_R HDMITX1#_R HDMITX0_R HDMITX0#_R HDMICLK_R HDMICLK#_R HDMI_CON_CEC

C3A

+5VPCU

R9545 R9543

NCEC@0_6

F1

DDC5V

*HM@SMD1206P110TFT

D2007

2

1 *HM@B130LAW-7-F_1A

+5V_HDMI HDMI_CON_HP

CEC@0_6

B2A

C3A

C

C5282 C5545 *HM@220P/50V_4X

Q2009 IN

OUT GND

C5287 1 2

20

*CEC@47K_4

22

CEC HotPlug CEC +3VPCU

21

C5283 CEC_EC_HP

[37] CEC_EC_HP

R9542

1 2 3

R9541

HDMI_CON_HP

CEC@1K/F_4

C

R9544

+3VPCU

2

*[email protected]/10V_4X

R9546

*CEC@1K_4

5

C5284

CEC Output 3

2 2

Q2004 HM@2N7002K_300MA

R9583 3HDMI_CON_HP HM@100K_4 Q2003 HM@2N7002K_300MA

IHM@680_4

HDMITX0#_R

R9548

IHM@680_4

HDMITX0_R

R9549

IHM@680_4

HDMITX1#_R

R9550

IHM@680_4

HDMITX1_R

R9551

IHM@680_4

HDMITX2#_R

R9552

IHM@680_4

HDMITX2_R

R9553

IHM@680_4

HDMICLK#_R

R9554

IHM@680_4

HDMICLK_R

R9584

EHM@499/F_4

HDMITX0#_R

R9570

EHM@499/F_4

HDMITX0_R

CEC

2 *CEC@TC7SH08FU(F)

+3V

CEC Input CEC +3VPCU

1 2 3

5

C5285

[email protected]/10V_4X

4

HDMI_CON_CEC

R9566

+3VPCU

HM@20K_4

+3VPCU

*CEC@47P/50V_4N 3

C5286

B

U5017

CEC@SN74LVC1G14DCKR

D2008

B

R9555

CEC@RB500V-40_100MA *CEC@10K_4 CEC_OUT

R9556

1

CEC@22K_4

EHM@499/F_4

HDMITX1#_R

R9573

EHM@499/F_4

HDMITX1_R

R9557

R9572

EHM@499/F_4

HDMITX2#_R

CEC@100K_4

R9587

EHM@499/F_4

HDMITX2_R

R9586

EHM@499/F_4

HDMICLK#_R

R9585

EHM@499/F_4

HDMICLK_R

CEC_IN

3

R9575

R9558 CEC@27K_4

Q5018 2

1

R9547

U5016 1

4 3

HDM/HMU/HMV

1

EHM@0_4

U5015

CEC@470K_4

+3V

HDMI_CON_HP_PCH_R

IHM@0_4

CEC@33_44

CEC@SN74LVC1G17DCKR

+5V

R4562

5

[email protected]/10V_4X

[email protected]/16V_4Y

HDMI_CON_HP_PCH_R

R4563

CEC-TEST2

23

HM@HMR2N-AK120N

HDMI LEVEL SHIFT

R9564 HM@1M_4

R9539 *CEC@0_4

CEC-MODE

*AZ5125-01J

HDMI-HPD HDM/HMU/HMV

[16] EXT_HDMI_HPD

R9538 *CEC@0_4

D32

*[email protected]/16V_4Y

HM@AP2331SA-7

+3V

CEC-TEST1

R9537

HPDET 3

[7] HDMI_CON_HP_PCH

+3VPCU

1

+5V

DDC5V_F

HDMI_CON_DDCCLK HDMI_CON_DDCDATA

SHELL1 D2+ D2 Shield D2D1+ D1 Shield D1D0+ D0 Shield D0GND CK+ CK Shield GND CKCE Remote NC DDC CLK DDC DATA GND +5V HP DET SHELL2

3 [email protected] 1

CEC-RESET#

CEC@R5F211B4D61SP#W4 [7] INT_HDMICLK+ [7] INT_HDMICLK-

4 2

RP13

D

3ND_MBCLK [16,37] 3ND_MBDATA [16,37]

1

HDMI_CON_CEC

CEC@2SK3541T2L_100MA

2

Q5019 *CEC@2SK3541T2L_100MA

CEC SMBus Level Shift

CEC

HDMI-SMBus HDM/HMU/HMV

+3VPCU

R9561

+3V

+3V

+3V

DDC5V_F

D3A

DDC5V_F

[email protected]_4

2

+3V

HDMI_CON_DDCDATA

D3A

3

1

Q2007

HDMI_CEC_DDCDATA

CEC@FDV301N_200MA

A

A

R9559

R9567

[email protected]_4

[email protected]_4

IHM@0_4

R4569

EHM@0_4

1 Q2005

3

HDMI_CON_DDCCLK

[7] HDMI_DDCDATA

R4570

IHM@0_4

R4564

EHM@0_4

HM@FDV301N_200MA

1 Q2006

[16] EV_HDMI_DDCDAT

3

HDMI_CON_DDCDATA

R9569 2

R4568

+3VPCU

2

R9560 [email protected]_4 2

[7] HDMI_DDCCLK

[16] EV_HDMI_DDCCLK

R9568 [email protected]_4

HM@FDV301N_200MA HDMI_CON_DDCCLK 3 Q2008

Quanta Computer Inc.

[email protected]_4 1

PROJECT : Chief River

HDMI_CEC_DDCCLK

CEC@FDV301N_200MA

Size

Docum ent Num ber

Rev A1A

HDMI CONN Date: 5

4

3

2

Wednes day, February 01, 2012 1

Sheet

27

of

48

5

Panel backlight control

4

3

LDS

LCD POWER SWITCH

2

1

LDS/LDU/LDV

HALL Sensor

HSR

28

+3V LCDVCC

DISPON_O

DISPON_O

C519 1U/6.3V_4X

[37]

U26 6 4

D

R422

[7] LVDS_DIGON

R9574

3

PIV@0_4

R9571

+3VPCU

IN

OUT

IN

GND

ON/OFF

GND

100K_4

1 2 C516

C518

0.1U/16V_4Y

*0.01U/25V_4X

D

C515 1

5

2

LID591#

LID591# [37]

*10U/6.3V_6X MR1

R421

[17] EV_LVDS_DIGON

AP2821KTR-G1

OEV@0_4

C5293

APX9132H AI-TRG

3

*100K_4

0.1U/16V_4Y R2033 PIV@100K_4

R2034 OEV@10K_4

CRT CRT/CRU/CRV

CRT_DDCCLK CRT_DDCDAT CRTDCLK CRTDDAT

[7] INT_CRT_RED [7] INT_CRT_GRN [7] INT_CRT_BLU

R415

ICRT@0_4

CRT_RED

R417

ICRT@0_4

CRT_GRN

R420

ICRT@0_4

CRT_BLU

C5294

[email protected]/16V_4Y

C5295

[email protected]/16V_4Y

C5297

[email protected]/10V_4X

+5V

C5299

[email protected]/16V_4Y

7 8

C

[16] EXT_CRT_GRN [16] EXT_CRT_BLU

[7] INT_CRT_DDCCLK [7] INT_CRT_DDCDAT [7] INT_HSYNC [7] INT_VSYNC

[16] EV_CRTDCLK [16] EV_CRTDDAT

B2A

R416

ECRT@0_4

R418

ECRT@0_4

E3A CRT_RED CRT_GRN CRT_BLU

L5021 L5022 L5023

[16] EV_CRTDDAT_aux

CRT_R1 CRT_G1 CRT_B1

ICRT@BLM18BA470SN1D_300MA ICRT@BLM18BA470SN1D_300MA ICRT@BLM18BA470SN1D_300MA

R419

ECRT@0_4

R103

ICRT@0_4

CRT_DDCCLK

R9580

C5300

R9581

C5301

R9582

C5304

C5302

C5303

C5305

R108

ICRT@0_4

CRT_DDCDAT

CRT@150/F_4

[email protected]/50V_4N

CRT@150/F_4

[email protected]/50V_4N

CRT@150/F_4

[email protected]/50V_4N

[email protected]/50V_4N

[email protected]/50V_4N

[email protected]/50V_4N

R102

ICRT@0_4

CRT_HSYNC

R113

ICRT@0_4

CRT_VSYNC

R112

ECRT@0_4

R107

ECRT@0_4

R114

*ECRT@0_4

R109

*ECRT@0_4

CRT_RED CRT_GRN CRT_BLU

[16] EV_CRTDCLK_aux

2

+3V

L5039 L5038 L5026

3 4 5 6

VCC_SYNCSYNC_OUT2 SYNC_OUT1 VCC_DDC BYP SYNC_IN2 VCC_VIDEO SYNC_IN1 VIDEO_1 VIDEO_2 VIDEO_3 GND

DDC_IN1 DDC_IN2 DDC_OUT1 DDC_OUT2

CRT@IP4772CZ16

15 13

CRT_VSYNC CRT_HSYNC

10 11

CRT_DDCCLK CRT_DDCDAT

9 12

CRTDCLK CRTDDAT C5306

C5307

CRT@10P/50V_4C

CRT@10P/50V_4C

E3A

6 1 7 2 8 3 9 4 10 5

CRT_R1

CRT_B1

R105

ECRT@0_4

+5V

D2011

CRT@SS14L_1A

+5V_CRT1 F2

CRT@SMD1206P110TFT 1

[16,18] EXT_VSYNC

ECRT@0_4

C5296

C5298

CRT@10P/50V_4C

CRT@10P/50V_4C

C

CRT_G1

R106

+5V_CRT

CRTVSYNC CRTHSYNC

+5V_CRT [16,18] EXT_HSYNC

[email protected]_4 [email protected]_4

16 14

CRT_R1 CRT_G1 CRT_B1

ECRT@BLM18BA470SN1D_300MA ECRT@BLM18BA470SN1D_300MA ECRT@BLM18BA470SN1D_300MA

+3V

R9578 R9579

16

[16] EXT_CRT_RED

[email protected]_4 [email protected]_4

U5018 1

+5V_CRT

R9576 R9577

11

D33 *AZ5125-01J

12

CRTDDAT

13

CRTHSYNC

14

CRTVSYNC

15

CRTDCLK

2

17

CN2002 CRT@DHR48-15K1200

B

B

[7] INT_TXLCLKOUT+ [7] INT_TXLCLKOUT[17] EV_TXLCLKOUT+ [17] EV_TXLCLKOUT-

CCD CCD

C3A

INT_TXLCLKOUT+ INT_TXLCLKOUT-

RP10

1 3

2 4

PIV@0X2

EV_TXLCLKOUT+ EV_TXLCLKOUT-

RP5

2 4

1 3

OEV@0X2

INT_TXLOUT2+ INT_TXLOUT2-

RP16

1 3

2 4

PIV@0X2

LCD_EDIDCLK LCD_EDIDDATA LCD_TXLCLKOUTLCD_TXLCLKOUT+

LCD_TXLCLKOUT+ LCD_TXLCLKOUT-

C5386 C5548 C5560 C5562

E@2200P/50V_4X E@2200P/50V_4X *6.8P/50V_4N *6.8P/50V_4N

CN2003 VIN

+3V

LCD_EDIDCLK LCD_EDIDDATA C5385

[7] INT_TXLOUT2+ [7] INT_TXLOUT2[17] EV_TXLOUT2+ [17] EV_TXLOUT2-

[7] INT_TXLOUT1+ [7] INT_TXLOUT1-

[17] EV_TXLOUT1+ [17] EV_TXLOUT1[7] INT_TXLOUT0+ [7] INT_TXLOUT0-

LCD_TXLOUT2+ LCD_TXLOUT2-

*47P/50V_4N

LCD_TXLOUT0LCD_TXLOUT0+ LCD_TXLOUT1LCD_TXLOUT1+

EV_TXLOUT2+ EV_TXLOUT2-

RP3

2 4

1 3

OEV@0X2

INT_TXLOUT1+ INT_TXLOUT1-

RP8

1 3

2 4

PIV@0X2

EV_TXLOUT1+ EV_TXLOUT1-

RP2

3 1

4 2

OEV@0X2

INT_TXLOUT0+ INT_TXLOUT0-

RP11

4 2

3 1

PIV@0X2

EV_TXLOUT0+ EV_TXLOUT0-

RP4

3 1

4 2

OEV@0X2

LCD_TXLOUT2LCD_TXLOUT2+ LCD_TXLOUT1+ LCD_TXLOUT1-

[7] LVDS_PWM [17] EV_LVDS_BRIGHT

R423

PIV@0_4

R424

OEV@0_4

LCD_TXLCLKOUTLCD_TXLCLKOUT+

DISPON_O

R9593

LVDS_PWM_R 1.2K/F_4 DISPON_O_R

LCDVCC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

USB_CCD_R USB_CCD#_R

R9594 R9595

*SHORT_4 *SHORT_4

USB_CCD [9] USB_CCD# [9]

E3A

CCD_POWER

+3V C5308

+

LCD Panel Module

*10U/6.3V_6X

LCD_TXLOUT0+ LCD_TXLOUT0-

A

A

[17] EV_TXLOUT0+ [17] EV_TXLOUT0[7] INT_LVDS_EDIDCLK [7] INT_LVDS_EDIDDATA

INT_LVDS_EDIDCLK INT_LVDS_EDIDDATA

RP17

4 2

3 1

CCD_POWER USB_CCD#_R USB_CCD_R PIV@0X2

LCD_EDIDCLK LCD_EDIDDATA DISPON_O_R

[16] EV_LVDS_DDCCLK [16] EV_LVDS_DDCDAT

+3V

EV_LVDS_DDCCLK EV_LVDS_DDCDAT

RP1

2 4

R9609

2.2K_4

LCD_EDIDCLK

R9610

2.2K_4

LCD_EDIDDATA

1 3

[34] INT_DMIC_DATA [34] INT_DMIC_CLK

L5024 L5025

FCM1005KF-221T03_300MA FCM1005KF-221T03_300MA

C3A

OEV@0X2 INT_DMIC_DATA

C5601

*0.1U/10V_4X

INT_DMIC_CLK

C5600

*0.1U/10V_4X

24 25 26 27 28 29 30

24 25 26 27 28 29 30

34 33 32 31

34 33 32 31

50373-03001-002

Quanta Computer Inc.

C3A

D2012 LCP0G050M0R2R

PROJECT : Chief River

(13246,6043)

Size

E3A 4

Rev A1A

LCD/LED Panel/CCD Date:

5

Docum ent Num ber

3

2

Wednes day, February 01, 2012 1

Sheet

28

of

48

5

4

3

2

1

MNW/DEG

29

[AOAC] WIMAX_P +3V

0.5A(30mils)

B2A

L10

2.75A(120mils) B2A

WIMAX_P

R9614 10K_4

C5371

C5310

C5311

C5312

C5313

C5314

C5315

C5316

C5383

*47P/50V_4N

[email protected]/10V_4X

[email protected]/10V_4X

*10U/6.3V_6X

0.1U/16V_4Y

*0.1U/16V_4Y

[email protected]/10V_4X

*10U/6.3V_6X

*47P/50V_4N

2

D

NAOAC@HCB1608KF-121T30_3A 1

+3V_S5

3

Q5031

+3V_S5

AOAC@ME1303_3A 2

WIMAX_P

WIMAX_P

D

C5572

C5571

[email protected]/25V_4X

*[email protected]/25V_4X R9730

1

Q5032 R9617

BT_DISABLE#_INTEL PLTRST#

[3,9,30,35,36,37] PLTRST# [9] PCLK_DEBUG

*0_4

R9616 R9618

NMP@0_4 NMP@0_4

PLTRST#_debug PCLK__debug_R

[9] PCIE_TXP_WLAN [9] PCIE_TXN_WLAN# WIMAX_P [9] PCIE_RXP_WLAN [9] PCIE_RXN_WLAN# R9620 10K_4 [9] CLK_PCIE_WLAN [9] CLK_PCIE_WLAN#

BT_DISABLE#_INTEL

3

PCIE_CLK_WLAN_REQ#_R

R9630

[7,30,35] PCIE_WAKE# 2

[37] BT_RFCTRL

AOAC@0_4

51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

CN2004 NC C-Link_RST C-Link_DAT C-Link_CLK GND NC NC GND GND PETp0 PETn0 GND GND PERp0 PERn0 GND NC NC

+3.3V GND +1.5V LED_WPAN# LED_WLAN# NC NC USB_D+ USB_DGND SMB_DATA SMB_CLK +1.5V GND +3.3Vaux PERST# W_DISABLE# GND

GND REFCLK+ REFCLKGND CLKREQ# BT_CHCLK BT_DATA WAKE#

NC NC NC NC NC +1.5V GND +3.3V

52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18

AOAC@LTC044EUBFS8TL_30MA

WMAX_P [37]

USB_WLAN [9] USB_WLAN# [9] SDATA_WLAN SCLK_WLAN WIMAX_P PLTRST# RF_EN

16 14 12 10 8 6 4 2

RF_EN [37]

LFRAME#_PCIE LAD3_PCIE LAD2_PCIE LAD1_PCIE LAD0_PCIE

R9621 R9624 R9626 R9627 R9629

NMP@0_4 NMP@0_4 NMP@0_4 NMP@0_4 NMP@0_4

LFRAME# [8,37] LAD3 [8,37] LAD2 [8,37] LAD1 [8,37] LAD0 [8,37]

6

[9,13,35] SDATA

[13,14,38] CGDAT_SMB

AAA-PCI-052-P01

Q5035

Q5033 2

R9622

R9623

[email protected]_4

[email protected]_4

1

SDATA_WLAN

Q5048A

AOAC@2N7002KDW_115MA

R9631

NAOAC@0_4 C

WIMAX_P

1

5

LTC044EUBFS8TL_30MA

[9,13,35]

3

SCLK

[13,14,38] CGCLK_SMB

4

SCLK_WLAN

Q5048B

AOAC@2N7002KDW_115MA

R9632

NAOAC@0_4

MNG

+1.5V +1.5V

C5317

*3G@47P/50V_4N

[email protected]/10V_4X

C5318

C5319

C5320

C5360

C5321

C5322

[email protected]/10V_4X

[email protected]/10V_4X

[email protected]/10V_4X

*3G@47P/50V_4N

[email protected]/10V_4X

[email protected]/10V_4X

C5578

C5323

C5576

[email protected]/10V_4X

[email protected]/10V_4X

*3G@10U/6.3V_6X

+3V

2.75A(120mils)

[9] PCIE_TXP_3G [9] PCIE_TXN_3G#

[9] PCIE_RXP_3G [9] PCIE_RXN_3G#

[9] CLK_PCIE_3G [9] CLK_PCIE_3G# [9] PCIE_CLK_3G_REQ#

15 13 11 9 7 5 3 1

CN2005 NC C-Link_RST C-Link_DAT C-Link_CLK GND +3.3V +3.3V CPEE# GND PETp0 PETn0 GND GND PERp0 RERn0 GND MMC_DAT MMC_CMD

+3.3V GND +1.5V LED_WPAN# LED_WLAN# LED_WWAN# CPUSB# USB_D+ USB_DGND SMB_DATA SMB_CLK +1.5V GND +3.3Vaux RESET# W_DISABLE# GND

GND REFCLK+ REFCLKGND CLKREQ# BT_CHCLK BT_DATA WAKE#

UIM_VPP UIM_RST UIM_CLK UIM_DATA UIM_PWR +1.5V GND +3.3V

3G@AAA-PCI-092-P05

52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2

CN2006 [9] USB_SIM# [9] USB_SIM

6 7 8 9 10

UIM_CLK USB_SIM# USB_SIM

CPUSB# [10] USB_3G [9] USB_3G# [9] CGDAT_SMB CGCLK_SMB

PLTRST# 3G_EN UIM_VPP UIM_RST UIM_CLK UIM_DATA UIM_PWR

CLK(C3) N/A(C8) N/A(C4) CT CD

3G@CE015

1 2 3 4 5

UIM_PWR UIM_VPP UIM_RST UIM_DATA B

[13,14,38] [13,14,38]

PLTRST# [3,9,30,35,36,37] 3G_EN [37]

C5326

GND(C5) VCC(C1) VPP(C6) RST(C2) DATA(C7) GND GND

B

51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17

54 53

B2A

UIM_CLK

C5324

3G@10P/50V_4C

UIM_VPP

C5325

*3G@33P/50V_4N

UIM_PWR C5327

[email protected]/16V_4Y

UIM_PWR C5328

*3G@27P/50V_4N

UIM_DATA C5329

3G@27P/50V_4N

UIM_RST

3G@10P/50V_4C

*3G@100P/50V_4N

UIM_PWR

54 53

B2A

GND GND

+3V

C5359

12 14

MINI Card Slot#2-3G

13 11

C

[email protected]/F_4

PCIE_CLK_WLAN_REQ#_R

ME2N7002E_200MA

2

3

[9] PCIE_CLK_WLAN_REQ#

R9615 [email protected]_4

3

+1.5V

1

MINI Card Slot#1(WiFi / Wimax / Combo)

R9633

3G@10K_4

C5330

A

A

Quanta Computer Inc. PROJECT : Chief River Size

Docum ent Num ber

Rev A1A

MINI CARD(WLAN/3G/SIM Card) Date: 5

4

3

2

Wednes day, February 01, 2012 1

Sheet

29

of

48

5

4

3

2

1

USB 3.0

30 U5019

B13

PLTRST#

C5331 C5332

[9] PCIE_RXP_USB30 [9] PCIE_RXN_USB30#

PCIE_RXP_USB30_C A23 PCIE_RXN_USB30#_C A24

[email protected]/10V_4X [email protected]/10V_4X

B15 B16

[9] PCIE_TXP_USB30 [9] PCIE_TXN_USB30#

D

R9637 CLK_PCIE_USB30 CLK_PCIE_USB30#

C5581 C5582

*[email protected]/50V_4C *[email protected]/50V_4C

A18

U3C@12K/F_4

C5334

[email protected]/16V_4X

B19

PERST# PCIECKP PCIECKM PCIETXP PCIETXM PCIERXP PCIERXM

U2DP0 U2DM0

PCI Express Interface

B17 B18

[9] CLK_PCIE_USB30 [9] CLK_PCIE_USB30#

SuperSpeed USB Port 0 Interface

[3,9,29,35,36,37]

100MHz

PCIEREXT PCIECAP

C3A

36mA A4 B45

AVCC33X

C5335

C5336

U3C@1U/6.3V_4X

[email protected]/16V_4Y

A3 A59 B6 B44

AVCC33X Typ

Max

3.15V

3.30V

3.45V

75mA +3V_S5

Current = 36mA

L5028

C5339

U3C@10U/6.3V_6X

PVCCA33X Min

Typ

Max

3.15V

3.30V

3.45V

Typ

Max

1.00V

1.05V

1.05V

C5343

C5344

U3C@1U/6.3V_4X

[email protected]/16V_4Y

Current = 170mA

33mA

AVCC10 1.00V

+1.05VSUS Typ

Min

1.05V

AVCC10X

U3C@HCB1608KF-181T15_1.5A

L5030

Max 1.05V

B14

AVCC10

U3C@HCB1608KF-181T15_1.5A C5346

C5347

U3C@1U/6.3V_4X

[email protected]/16V_4Y

A19 A61 A62 B8 B9 B20

72mA

Typ

Min 2.97V

3.30V

B11

PVCCA25OX

Max 3.63V

C5350

U3C@1U/6.3V_4X

[email protected]/16V_4Y

Min

Typ

Max

3.30V

3.63V

PVCCA25X

Current = 5mA

C5351

C5352

U3C@1U/6.3V_4X

[email protected]/16V_4Y

DVCC10X Typ

Max

1.05V

1.10V

5mA +3V_S5

Current = 23mA

R9655

DVCC10 Min

Typ

Max

1.00V

1.05V

1.10V

DVCC33X

U3C@0_6 C5353

C5354

U3C@1U/6.3V_4X

[email protected]/16V_4Y

A5 A21 B46

115mA +1.05VSUS

R9657

DVCC10X

U3C@0_6 C5356

U3C@1U/6.3V_4X

[email protected]/16V_4Y

A44 B12 B38

A11 A13 B40 B42 B52 A16 A25 A36 A41 A42 B23 B26 B32

A

XCKSEL[1:0] 00(default) 01 10 11 PPWRCTL 0 1

12MHz 30MHz 48MHz 24MHz

crystal oscillator crystal oscillator reference clock to reference clock to

117

to XSCI/XSCO to XSCI/XSCO XCK pin XCK pin

UREF1 UCAP1 UV1281 PPWR1 OVCN1

XCK

USB30_RX1+_R1 USB30_RX1-_R1

[31] [31]

RREF0

B47

SSCAP0 C5333

A58

V1280

A50

PPWR0

B39

USB_SC_OC0#

R9636

[31] [31]

U3C@12K/F_4 U3C@2200P/50V_4X

C5337

[email protected]/6.3V_6X R9638

R9720

U3C@0_4

USB20+_L1 USB20-_L1

A7 A8

USB30_TX2+_L1 USB30_TX2-_L1

A9 A10

USB30_RX2+_L1 USB30_RX2-_L1

RREF1

A6

SSCAP1 C5341

B5

V1281

A48

PPWR1

A46

USB_SC_EN#

*U3C@10K_4

B2 B3

B4

*U3C@0_4

R9639

USB_SC_EN#

[31,37]

+3V_S5 USB_SC_OC#

[9,31,37]

USB20+_L1 [32] USB20-_L1 [32]

R9640

USB30_TX2+_L1 USB30_TX2-_L1 USB30_RX2+_L1 USB30_RX2-_L1

[32] [32] [32] [32]

U3C@12K/F_4 U3C@2200P/50V_4X

C5342

[email protected]/6.3V_6X R9701

*U3C@0_4

USB_SC_OC1# R9641

USB_Normal_EN#

*U3C@10K_4 U3C@0_4

A51

XCKSEL0

R9642

*[email protected]_4

B41

XCKSEL1

R9643

*[email protected]_4

A52

XCK

B43

XIN

USB_Normal_EN#

[32,37]

USB_Normal_OC#

[9,32,37]

+3V_S5

C

+3V_S5

TP2033 C5345

U3C@22P/50V_4N

Y5001

B2A

*U3C@1M_4 U3C@12MHZ_30

XSCO

A53

XOUT

R9645

U3C@0_4

C5348

U3C@22P/50V_4N

PVCC25OX +3V_S5

PPWRCTL

AUXDET PVCC25X PVCC25X PVCC25X

WAKE#

PGND PGND PGND PGND

DVCC33X DVCC33X DVCC33X DVCC33 DVCC33 DVCC33

DVCC10X DVCC10X DVCC10X DVCC10X DVCC10X DVCC10 DVCC10 DVCC10 DVCC10 DVCC10 DVCC10 DVCC10 DVCC10

SMI# ROMSDA ROMSCL ROMPRES U2LNK# PCIELNK# SSLNK# DATTX# DATRX#

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC TESTN

Digital core power supply

C5355

SSRXP1 SSRXM1

CLKREQ#

A26 B25 B30

Current = 71mA

SSTXP1 SSTXM1

XSCI

Digital IO power supply

Min 1.00V

OVCN0

A57

ŇōIJııĺ

A1 A20 A54 B10

B

PPWR0

XCKSEL1

AGND10 AGND10 AGND10 AGND10 AGND10 AGND10

U3C@0_8

2.97V

USB30_RX1+_R1 USB30_RX1-_R1

R9700

AVCC10

R9647

DVCC33

UCAP0 UV1280

XCKSEL0

Internal POWER

Current = 0mA

C5349

AVCC10X AVCC10X AVCC10X AVCC10X

B50 B51

USB20+_R1 [31] USB20-_R1 [31] USB30_TX1+_R1 USB30_TX1-_R1

R9644

Current = 33mA

DVCC33X

A17 A22 A60 B7

Analog 1.0V power supply

L5029

AVCC10X Min

[email protected]/16V_4Y

170mA +1.05VSUS

PVCC33X

USB30_TX1+_R1 USB30_TX1-_R1

D

UREF0

U2DP1 U2DM1

C5340

U3C@1U/6.3V_4X

Current = 75mA

C

PVCCA33X

U3C@HCB1608KF-181T15_1.5A C5338

A12

AGND33 AGND33 AGND33 AGND33

SSRXP0 SSRXM0

USB20+_R1 USB20-_R1

B48 B49

Crystal

Min

AVCC33X AVCC33X

SuperSpeed USB Port 1 Interface

U3C@HCB1608KF-181T15_1.5A

EEPROM

L5027

Analog 3.3V power supply

+3V_S5

SSTXP0 SSTXM0

A55 A56

DGND

B34

R9646

*U3C@0_4 +3V_S5

R9648

*U3C@0_4

A39

R9649

R9650

R9651

[email protected]_4

*[email protected]_4

*[email protected]_4

AUXDET

A14

PCIE_WAKE#

A15 R9652

B27

ROMSDA

R9653

*[email protected]_4

A35

ROMSCL

R9654

*[email protected]_4

A33

ROMPRES

R9656

*[email protected]_4

U3C@0_4

USB30_SMI#

[9]

[9] B

+3V_S5

B2A

B22 B21 A27 A28 B24

A2 A29 A30 A31 A32 A34 A37 A38 A40 A43 A45 A47 A49 A63 A64 B1 B29 B31 B33 B35 B36 B37

[7,29,35]

PCIE_CLK_USB30_REQ#

B28

EEPROM +3V_S5

B2A

+3V_S5 U5020

6 5

ROMSCL ROMSDA

R9658

7

[email protected]_4 TESTN

SCL SDA WP

A0 A1 A2 VCC GND

1 2 3 8 4 C5357

*U3C@M24C08-WMN6TP *[email protected]/16V_4Y

A

U3C@FL1009-2Q0

VBus controllable, internal pull down VBus is not controlled by FL1009 VBus is controlled by FL1009

Quanta Computer Inc. V1280 V1281

R9659 R9660

U3C@0_4 U3C@0_4

PROJECT : Chief River

AVCC10X Size

Document Number

Rev A1A

USB 3.0(FL1009) Date: 5

4

3

2

Wednesday, February 01, 2012

Sheet 1

30

of

48

5

USB CONNECT RIGHT(UR)

4

3

2

1

31

D3A 4 1

[30] USB20-_R1 [30] USB20+_R1

3 2

RN16

USB20N_R USB20P_R

U3C@MCM2012B900GBE

1 4

[9] USBP0[9] USBP0+

2 3

RN17

U3C-N@MCM2012B900GBE

1 4

2 3

RN18

[30] USB30_RX1-_R1 [30] USB30_RX1+_R1

UR-2@MCM2012B900GBE

[9] USB30_RXN1_R [9] USB30_RXP1_R

+5V_S5

R9666 R9667

U3C@0_4 U3C@0_4

R9668 R9670

U3C-N@0_4 U3C-N@0_4

R9671 R9672

U3C@0_4 U3C@0_4

R9673 R9674

U3C-N@0_4 U3C-N@0_4

USB30_RX1-_RR USB30_RX1+_RR

D

D

[30] USB30_TX1-_R1 [30] USB30_TX1+_R1

C5358 [email protected]/16V_4Y

[9] USB30_TXN1_R [9] USB30_TXP1_R

U5022 R9862

D3A

*S&C@10K_4

5 [37] USB_BUS_SW4 [37] USB_BUS_SW3 [37] USB_BUS_SW2

R9861

*S&C@0_4

R9860

*S&C@0_4

VCC

1 8

TDP TDM

CB1(CEN#) CB DP DM

9

GND

GND

6 7

USB20P_R USB20N_R

R9853 R9854

USB30_TX1-_RR USB30_TX1+_RR

NS&C@0_4 NS&C@0_4

3 2

USB20P_CONN_C USB20N_CONN_C

4

S&C@MAX14600ETA+T

R9859

S&C@0_4

R9858

*S&C@0_4

USB_BUS_SW3

[37]

B2A

+3V_S5

+5V_S5

R9861 R9860

R9859

V

14566 14600 C

R9858

R9748

R9862

U5021

V

14617(with CB2) V

V

14617(no CB2)

V

2 3

UR-3@10K_4

V [30,37] USB_SC_EN#

4 1 9

USB_SC_EN# C5364

V

IN1 IN2 EN# GND GND-C

OUT3 OUT2 OUT1

8 7 6

+5VSUS_USBP0

C5362

+ C5361 R9750

OC#

5

UR-3@100U/6.3V_1206

*UR-3@100U/6.3V_3528P_E45b *UR-3@470/F_4

C

C3A

UR-3@UP7534BRA8-15

UR-3@1U/6.3V_4X

3

E3A 14566/14600

2

CB0

CB1

Status

0

0

Auto mode

0

1

Force dedicated charger mode

1

X

Pass-Through(USB) mode: Connect DP/DM to TDP/TDM for 14566

1

0

Pass-Through(USB) mode for 14600

1

1

pass-through(USB) with CDP Emulation for 14600

[9,30,37] USB_SC_OC#

1

Q5017 *UR-3@ME2N7002E_200MA

E3A B2A

+3V_S5

+5V_S5 R9751 U5032

14617 CB0

CB1

CB2

X

X

1

Force Apple 2A Charger Mode

0

0

0

Autodetection charger mode

0

1

0

Force-Dedicated Charger Mode

1

0

0

USB Pass-Through Mode(USB) Connect DP/DM to TDP/TDM USB Pass-Through Mode with CDP Emulation.Auto connect DP/DM to TDP/TDM depending on CDP status

B

1

0

Status [30,37] USB_SC_EN#

4 1 9

USB_SC_EN#

C5368

IN1 IN2 EN# GND GND-C

OUT3 OUT2 OUT1

8 7 6

+5VSUS_USBP0

C5367

+ C5363 R9753

OC#

5

UR-2@100U/6.3V_1206

*UR-2@100U/6.3V_3528P_E45b *UR-2@470/F_4

C3A

UR-2@UP7534BRA8-15

E3A

3

UR-2@1U/6.3V_4X

B

2 [9,30,37] USB_SC_OC#

Q5020 *UR-2@ME2N7002E_200MA

1

1

2 3

UR-2@10K_4

E3A

CN2021

[email protected]/10V_4X [email protected]/10V_4X

USB30_TX1-_C USB30_TX1+_C

8 USB20N_CONN_C USB20P_CONN_C D31 *AZ5125-01J

1 2 3 4

13 12 11 10

2

5

C5365 C5366

+5VSUS_USBP0

13 12 11 10

USB30_TX1-_RR USB30_TX1+_RR

VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+

7

USB30_RX1-_RR USB30_RX1+_RR

1 2 3 4 5 6 7 8 9

1

D3A

1 2 3 4 5 6 7 8 9

6

CN2007 +5VSUS_USBP0 USB20N_CONN_C USB20P_CONN_C

UR-3@TARAH-9V1391 UR-2@UARCF-4K1986

A

A

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Rev A1A

USB3 Redriver/S&C/USB2 Date: 5

4

3

2

Wednesday, February 01, 2012 1

Sheet

31

of

48

5

4

2 1

[30] USB20-_L1 [30] USB20+_L1 [9] USBP2[9] USBP2+

U3CL-N@MCM2012B900GBE

2 3

D

USB20N_L1_C USB20P_L1_C

1 4

RN14

1 4

U5023

C5375 C5377

[email protected]/10V_4X [email protected]/10V_4X

USB30_TX3-_CC USB30_TX3+_CC

8 9

USB30_RX3-_RRR USB30_RX3+_RRR

C5378 C5376

[email protected]/10V_4X [email protected]/10V_4X

USB30_RX3-_CC USB30_RX3+_CC

11 12

RX1RX1+

TX1TX1+

TX2TX2+

RX2RX2+

23 22

USB30_TX3-_RR USB30_TX3+_RR

20 19

USB30_RX3-_RR USB30_RX3+_RR

[30,37]

[30] USB30_TX2-_L1 [30] USB30_TX2+_L1 [9] USB30_TXN3_L1 [9] USB30_TXP3_L1

R9687 R9689

U3CL@0_4 U3CL@0_4

R9691 R9692

U3CL-N@0_4 U3CL-N@0_4

R9694 R9696

U3CL@0_4 U3CL@0_4

R9698 R9699

U3CL-N@0_4 U3CL-N@0_4

EQ1

1 13 2

EQ2

17

DE1

3

DE2

16

+USB_RE_PWR USB30_RX3-_RRR USB30_RX3+_RRR

USB30_TX3-_RRR USB30_TX3+_RRR

OS1

4

OS2

15

VCC VCC EQ1

EN_RXD CM

EQ2 NC1 NC2

DE1 DE2

GND GND GND GND

OS1

4 1 9

USB_Norm al_EN# C5372

14

EN# GND GND-C

OUT3 OUT2 OUT1

8 7 6

+5VSUS_USBP1

C5370

C5369

+

R9757

OC#

5

100U/6.3V_3528P_E45b

*100U/6.3V_1206

*470/F_4

C3A

UP7534BRA8-15

E3A

1U/6.3V_4X

5

IN1 IN2

R9710 R9711

*[email protected]/F_4 *[email protected]/F_4

C3A

R9712 R9713

*[email protected]/F_4 [email protected]/F_4

D

+USB_RE_PWR

2

C3A

7 24

[9,30,37]

USB_Norm al_OC#

Q5021 *ME2N7002E_200MA

1

ULU-2@MCM2012B900GBE

[9] USB30_RXN3_L1 [9] USB30_RXP3_L1

2 3

10K_4

U5024 USB30_TX3-_RRR USB30_TX3+_RRR

RN11

[30] USB30_RX2-_L1 [30] USB30_RX2+_L1

32

+5V_S5 R9721

U3CL@DLP11SN900HL2L_150MA

2 3

1

B2A

+3V_S5

USB3.0 re-driver IC

4 3

RN15

USB 3.0 Rrdriver IC

B2A

C3A

D3A

2

3

USB CONNECT LEFT1(ULU)

3

6 10 18 21

E3A

OS2 ULU-3@PI3EQX7502IZDE

B2A

D3A CN2008

1 2 3 4 5 6 7 8 9

+5VSUS_USBP1 USB20N_L1_C USB20P_L1_C

+USB_RE_PWR

ULU-3@0_4

ULU-3@0_4

R9705

R9706

R9707

R9708

*[email protected]/F_4

*[email protected]/F_4

*[email protected]/F_4

*[email protected]/F_4

EN_RXD 1(default) 0 EQ1 EQ2 DE1 DE2 OS1 OS2

C

C3A

Control pins setting Device function CM Device function 0(default) Normal Operation Normal Operation Compliance Test Mode 1 Sleep Mode

USB30_TX3-_RR USB30_TX3+_RR

C5373 C5374

USB30_TX3-_C USB30_TX3+_C

[email protected]/10V_4X [email protected]/10V_4X

1 2 3 4 5 6 7 8 9

VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+

13 12 11 10

R9704

USB30_RX3-_RR USB30_RX3+_RR

13 12 11 10

R9703

D3A

C

+USB_RE_PWR +3V ULU-3@TARA9-9V1391

R9714

R9715

R9716

R9717

C3A

R9702 R9718

*ULU-3@0_6

+USB_RE_PWR

R9719 C5379

C5380

C5381

C5382

ULU-3@1U/6.3V_4X

[email protected]/16V_4Y

[email protected]/6.3V_6X

ULU-3@470P/50V_4X

CN2022

+3V_S5 *ULU-3@75K/F_4

*ULU-3@75K/F_4

[email protected]/F_4

[email protected]/F_4

R9709

ULU-3@0_6

+5VSUS_USBP1 USB20N_L1_C USB20P_L1_C

1

1 2 3 4

2

D3A

7

D34 *AZ5125-01J

5

E3A

6

*[email protected]/F_4

8

*[email protected]/F_4

ULU-2@UARC6-4K1926

B

ULD

USB CONNECT LEFT2(ULD)

B

1

[9] USBP9[9] USBP9+

RN6

2 3

B2A 1 E@MCM2012B900GBE 4

USBP9-_C USBP9+_C

1 2 3 4

2

7

D30 *AZ5125-01J

5

EMI

+5VSUS_USBP1

6

8

CN2009

E3A

UARC6-4K1926

A

A

D3A

Quanta Computer Inc. PROJECT : Chief River Size

Docum ent Num ber

Rev A1A

USB3 Redriver/USB2_Left Date: 5

4

3

2

Wednes day, February 01, 2012 1

Sheet

32

of

48

5

SATA HDD

4

3

1

33

HDD CN2010 GND23

D

2

GND1 RXP RXN GND2 TXN TXP GND3 3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND RSVD GND 12V 12V 12V GND24

CN2023

23

GND23

1 2 3 4 5 6 7

SATA_TXP_1ST_HDD_C SATA_TXN_1ST_HDD#_C

C5387 C5388

0.01U/25V_4X 0.01U/25V_4X

SATA_RXN_1ST_HDD#_C SATA_RXP_1ST_HDD_C

C5389 C5390

0.01U/25V_4X 0.01U/25V_4X

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

GND1 RXP RXN GND2 TXN TXP GND3

SATA_TXP_1ST_HDD [8] SATA_TXN_1ST_HDD# [8] SATA_RXN_1ST_HDD# [8] SATA_RXP_1ST_HDD [8]

+5V_HDD1

3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND RSVD GND 12V 12V 12V

+5V

C5391

C5392

*0.1U/16V_4Y

*10U/6.3V_6X

+ C5393 *100U/6.3V_3528P_E45b

C3A

24

GND24

Capetown@SAT-22ESAB

23 1 2 3 4 5 6 7

SATA_TXP_1ST_HDD_C SATA_TXN_1ST_HDD#_C

D

SATA_RXN_1ST_HDD#_C SATA_RXP_1ST_HDD_C

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

+5V_HDD1

24

Luxor@SAT-22EH1B

C

C

SATA ODD

ODD Zero power . (Only for Intel)

CN2011

B

DP +5V +5V MD GND GND GND15

14 1 2 3 4 5 6 7

SATA_TXP_ODD_C SATA_TXN_ODD#_C

C5394 C5395

0.01U/25V_4X 0.01U/25V_4X

SATA_RXN_ODD#_C SATA_RXP_ODD_C

C5396 C5399

0.01U/25V_4X 0.01U/25V_4X

SATA_TXP_ODD [8] SATA_TXN_ODD# [8]

+5V

+5V_ODD

SATA_RXN_ODD# [8] SATA_RXP_ODD [8] L11

8 9 10 11 12 13

ODD_PRSNT# [10]

ZRP-N@HCB1608KF-121T30_3A

1

+5V_ODD

+5V

3

+5V_ODD ODD_MD# [9]

C5397 C5400

C5401

+ C5402 [email protected]/25V_4X

15

*0.1U/16V_4Y

*10U/6.3V_6X

Q5040

C5398

ZRP@ME1303_3A

*[email protected]/25V_4X

*100U/6.3V_3528P_E45b R9723

C3A

Capetown@C18526-11305-L

B

R9722 [email protected]_4 [email protected]/F_4 3

GND1 RXP RXN GND2 TXN TXP GND3

2

GND14

+5V_ODD

2 PCH_ODD_EN [10] 1

Q5041

CN2024

A

DP +5V +5V MD GND GND GND15

ZRP@LTC044EUBFS8TL_30MA ZRP@22_8 SATA_TXP_ODD_C SATA_TXN_ODD#_C

3

GND1 RXP RXN GND2 TXN TXP GND3

R9724 14 1 2 3 4 5 6 7

SATA_RXN_ODD#_C SATA_RXP_ODD_C 2

8 9 10 11 12 13

Q5042

ODD_PRSNT# [10] 1

GND14

+5V_ODD

ZRP@ME2N7002E_200MA ODD_MD# [9] A

15

Luxor@C185K3-11308-L

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Date:

Wednesday, February 01, 2012

Rev A1A

HDD/ODD 5

4

3

2

Sheet 1

33

of

48

5

4

3

2

1

External MIC

Codec (CX20671-21Z)

34

MIC1-VREFO

R9725 3.3K/F_4

FILT_1.65V

D

E3A

R9726 3.3K/F_4

C5403

C5404

MIC1_L1

R9727

100/F_6

MIC1_L2

L5031

HCB1608KF-121T20_2A

MIC1_L3

1U/6.3V_4X

0.1U/16V_4Y

MIC1_R1

R9728

100/F_6

MIC1_R2

L5032

HCB1608KF-121T20_2A

MIC1_R3

CN2012

1 2 6 3 4

7 8 9 10

D

5

Port_B# ADOGND

2SJ3013-009311F R9729

+3V

*SHORT_6

+3AVDD

C5405

C5406

C5407

100P/50V_4N

C5411

C5412

0.1U/16V_4Y

4.7U/6.3V_6X

0.1U/16V_4Y

C5408

C5410

4.7U/6.3V_6X

0.1U/16V_4Y

100P/50V_4N

Shield_GND

Normal Open Jack

AVDD_3.3 C5409

C3A

*0.1U/16V_4Y

E3A

ADOGND ADOGND

R9731

+3V_S5

*SHORT_6

+3AVDD_S5 C5413

C5414

*10U/6.3V_6X

0.1U/16V_4Y

(100mils)

+5AVDD

+5V C5415

C5416

*10U/6.3V_6X

0.1U/16V_4Y

MIC1_L3

C5597

*0.1U/10V_4X

MIC1_R3

C5596

*0.1U/10V_4X

E3A

+3AVDD C5417

C5418

*10U/6.3V_6X

0.1U/16V_4Y

(40mils)

CLASSD_5V

Headphone

C5419

C5420

C5421

C5422

0.1U/16V_4Y

0.1U/16V_4Y

10U/6.3V_6X

10U/6.3V_6X

FILT_1.8V C5424

C

R9855

C5423

C5425

1 2 6 3 4

0.1U/16V_4Y 0.1U/16V_4Y

[8] BIT_CLK_AUDIO [8] ACZ_SYNC_AUDIO [8] ACZ_SDIN0_AUDIO [8] ACZ_SDOUT_AUDIO

R9736

*SHORT_4

BIT_CLK_AUDIO_R

R9738

33_4

SDATA_IN

C5432

0.1U/16V_4Y

5 8 6 4

10

PCBEEP_C

39 AMP_MUTE#

[37] AMP_MUTE#

TP2037

LPWR_5.0

SENSE_A

DMIC INT_DMIC_DATA

38 37

PC_BEEP

C_BIAS PORTC_R PORTC_L

SPDIF GPIO0/EAPD# GPIO1/SPK_MUTE#

40 1

36

SENSE_A

35 34 33

MIC1-RR MIC1-LL MIC1-VREFO_B

PORTA_R PORTA_L

DMIC_CLK DMIC_1/2

*0.47U/6.3V_4X

DMIC

*0.47U/6.3V_4X

INT_DMIC_DATA

HPOUT-L3

HPOUT-R

R9733

5.1/F_6

HPOUT-R2

L5034

HCB1608KF-121T20_2A

HPOUT-R3

R9735 R9737

C5430 C5431 R9739

2.2U/6.3V_6X 2.2U/6.3V_6X *SHORT_4

C5427

C5428

C5429

*100P/50V_4N

*100P/50V_4N

*0.1U/16V_4Y

Shield_GND

Normal Open Jack

C3A

MIC1_R1 MIC1_L1 MIC1-VREFO

E3A

TP2034 TP2035 TP2036

HPOUT-L3 C5598

*0.1U/10V_4X

HPOUT-R3 C5599

*0.1U/10V_4X

25 24

E3A

23 22 AVEE FLY_N FLY_P

Internal Speaker C5433

C5434

C5435

0.1U/16V_4Y

4.7U/6.3V_6X

CN2014 SPK_R+ SPK_RSPK_LSPK_L+

*SHORT_6

R9746

*0_6

R9747

*SHORT_6

B

1U/6.3V_4X

EP_GND

21 20 19

HPOUT-R HPOUT-L

E3A

R9741 R9742 R9743 R9744

INSPKR+N INSPKR-N INSPKL-N INSPKL+N

BLM18PG471SN1D_1A BLM18PG471SN1D_1A BLM18PG471SN1D_1A BLM18PG471SN1D_1A

C3A

E3A

1 2 3 4

1 2 3 4 88266-040L

B2A

INSPKL-N INSPKL+N INSPKR-N INSPKR+N

ADOGND *10P/50V_4C

7 8 9 10

2SJ3013-009311F

Port_A# Port_B#

39.2K/F_4 20K/F_4

B2B

C5443

C

CN2013

5

Port_A#

41

RIGHT-

LEFT-

RIGHT+ 16

14

LEFT+ 11

32 31 30

R9745

C5437

HCB1608KF-121T20_2A

CX20671-21Z

AVEE FLY_N FLY_P

C5436

L5033

ADOGND

13

B

[28] INT_DMIC_CLK [28] INT_DMIC_DATA

100_4

HPOUT-L2

17

15 RPWR_5.0

27

12

29

28

3

BIT_CLK SYNC SDATA_IN SDATA_OUT

AVDD_5V

RESET#

NC_DR NC_DL R9740

5.1/F_6

5.11K/F_4

PORTB_R PORTB_L B_BIAS [8] PCBEEP

R9732

R9734

CLASSDREF

E3A

FILT_1.65

9

[8] ACZ_RST#_AUDIO

AVDD_3.3

GND

*0.1U/16V_4Y

2 7 18 26

U5026 C5426

HPOUT-L +3AVDD

FILT_1.8

4.7U/6.3V_6X

VAUX_3.3 VDD_IO DVDD_3.3 AVDD_HP

*10K_4

MIC1-RR

C5442

*0.47U/6.3V_4X

MIC1-LL

C5444

*0.47U/6.3V_4X

C5438 E@2200P/50V_4X

C5439 E@2200P/50V_4X

C5440 E@2200P/50V_4X

C5441 E@2200P/50V_4X

C5591 39P/50V_4N

C5592 39P/50V_4N

C5593 39P/50V_4N

C5594 39P/50V_4N

ACZ_RST#_AUDIO

C5445

*10P/50V_4C

BIT_CLK_AUDIO

SPK_R+

C5446

*10P/50V_4C

ACZ_SDOUT_AUDIO

SPK_RINSPKL-N INSPKL+N INSPKR-N INSPKR+N

SPK_LSPK_L+

A

A

E3A ADOGND

Quanta Computer Inc. PROJECT : Chief River Size

Docum ent Num ber

Rev A1A

Audio Codec (CX20671) Date: 5

4

3

2

Wednes day, February 01, 2012 1

Sheet

34

of

48

5

3

C5450

[email protected]/6.3V_6X

*LAN@10U/6.3V_6X

51@1000P/50V_4X

LAN@1U/6.3V_4X

[email protected]/16V_4Y

AVDD_CEN

AR8161/8162 Pin 5 30K/F to +3V S0

+3V

R9764 R9787

LAN@0_4 *30K/F_4

AVDD_CEN_LAN

5

AVDDL

6

LAN_XTLO

7

LAN_XTLI

8

LAN_VDD33

C3A

AVDD_CEN

[email protected]/16V_4Y

LAN@1U/6.3V_4X

Y5002

TX3P TX3N

20 21

*LAN@0_6

SB_SMBDATA1_LAN

*LAN@0_4

TRXP1 TRXN1 AVDDH AVDDL AVDDL

TRXP2 TRXN2 TRXP3 TRXN3

51_52@AR8151-AL1B-R

37 24 31 34

DVDDL DVDDL_LAN AVDDL AVDDL

33 32 36 35 30 29

CLK_PCIE_LAN CLK_PCIE_LAN#

C5452

LAN@1U/6.3V_4X

C5453

[email protected]/16V_4Y

C5455 C5456

[email protected]/16V_4Y [email protected]/16V_4Y

PCIE_RXP6_C PCIE_RXN6_C

C5458 C5459

[email protected]/25V_4X

Q5043

C195

LAN@ME1303_3A

*[email protected]/25V_4X

[email protected]_4

R91

PLACE NEAR LAN IC SIDE

75$16)250(5

26 25

TX1P TX1N 2 4

TX0P TX0N 2 4

RN8

[email protected]

[email protected]

C5482

C5485

LAN@1000P/50V_4X

[email protected]/16V_4Y

LAN@1000P/50V_4X

51@1000P/50V_4X

C5477

[email protected]/16V_4Y

C5478

RN7 1 3

1 3

C5481

C5476

51@1000P/50V_4X

C5479

[email protected]/16V_4Y

C5480

51@1000P/50V_4X

C5483

[email protected]/16V_4Y

C5486

C5484

51@1000P/50V_4X

[email protected]/16V_4Y

C5487

[email protected]/16V_4Y

AVDD_CEN_T TX1P TX1N

4 5 6

AVDD_CEN_T TX2P TX2N

7 8 9

AVDD_CEN_T TX3P TX3N

10 11 12

D

CLK_PCIE_LAN CLK_PCIE_LAN# PCIE_TXN_LAN# PCIE_TXP_LAN PCIE_RXP_LAN PCIE_RXN_LAN#

[email protected]/10V_4X [email protected]/10V_4X

[9] [9] [9] [9] [9] [9]

LX

L5035

AVDD_CEN

[email protected]_C_1A C5467

C5468

C5469

51@1000P/50V_4X

51@10U/6.3V_6X

[email protected]/16V_4Y

41

22

AVDDH

C5472

[email protected]/16V_4Y

16 19 13

AVDDH_C AVDDL

C5474

[email protected]/16V_4Y

AVDDL

C5475

[email protected]/16V_4Y

AR8161/18162 Pin 13 0.1U to GND

C754

*1U/6.3V_4X

C5473

[email protected]/16V_4Y

R743

51@0_4

R744

*0_6

AVDDH LAN_VDD33 C

AR8161/18162 :

AR8161 Pin 19 0.1U to GND

LAN@LTC044EUBFS8TL_30MA 1

Mount C754 ,C5473,R744

C3A

*,*$$5%/$5 $/ $5%/$5 $/

5-

LED0 = LAN_ACTLED

1 0

Over-clocking enable (default = 1) Over-clocking disable

CN2015

L5036

1 2 3

[email protected]/16V_4Y

B2A

Q10 3

[email protected]/F_4

AVDD_CEN_T TX0P TX0N

C5454

SB_SMBDATA1_LAN SB_SMBCLK1_LAN

40

AVDD_CEN_T

B

B2A

DVDDL

R81 2

C183

B2A

3

2

1

LAN@0_4

28 27

LAN_P [37]

SB_SMBCLK1_LAN

*LAN@0_4

AR8161/8162 Pin 24/28 NC R9763

+3V_S5 R9762

[9,13,29] SCLK

B2A

AR8162 Pin 23 for LAN LED, No use NC. CKREQ#

GND10

17 18

AVDDH

GND9

TX2P TX2N

TRXP0 TRXN0

GND8

14 15

LAN_LINKLED# LAN_ACTLED

50

R9761

C

TX1P TX1N

GND1

GND7

C3A

LAN_VDD33

11 12

RBIAS

49

LAN@1U/6.3V_4X

TX0P TX0N

39 38 23

AVDDH_REG

GND6

10

LX

48

[email protected]/F_4 RBIAS

C3A +3V_S5

SMDATA SMCLK

GND5

R9758

9

C5471

[email protected]/16V_4Y

XTLI

25MHZ_30 AVDDH

REFCLKP REFCLKN RX_N RX_P TX_P TX_N TEST_RST TESTMODE

47

33P/50V_4N

C5470

R9760

XTLO

GND4

C5466

[9,13,29] SDATA

AR8151/AR8152

AVDDL_REG

46

[email protected]/16V_4Y

33P/50V_4N

VDDCT

GND3

*52@10U/6.3V_6X

C5460

DVDD_REG DVDDL AVDDL AVDDL

Atheros

PERSTn WAKEn VDDCT_REG/CKRn

45

*52@1U/6.3V_4X

C5464

C5463

LED1/LED_LINK10/100n LED0/LED_ACTn LED2/CLKREQn

GND2

C5461

C5465

C5462

VDD33

44

*10K_4 52@0_4

2 3 4

PCIE_LAN_WAKE# CKREQ_G#

LAN@0_4 C5457

1 [email protected]/16V_4Y

43

R9755

C5451

42

CKREQ#

C5449

2

R9752

52@0_4

C5448

B2A

AR8162 Pin 4 10K to LAN power 51@0_4 CKREQ_G#

C5447

R9749

B2A

R9756

35

U5027

[3,9,29,30,36,37] PLTRST# [7,29,30] PCIE_WAKE#

R9754

1

LAN_VDD33

LAN_VDD33

D

[9] PCIE_CLK_LAN_REQ#

2

0.163A(20mils)

1

Atheros Lan

4

LAN@HCB1608KF-601T10_1A

U5028 TCT1 TD1+ TD1-

MCT1 MX1+ MX1-

TCT2 TD2+ TD2-

MCT2 MX2+ MX2-

TCT3 TD3+ TD3-

MCT3 MX3+ MX3-

TCT4 TD4+ TD4-

MCT4 MX4+ MX4-

24 23 22

TERM1

21 20 19

TERM2

18 17 16

TERM3

15 14 13

TERM4

AVDD_CEN

X-TX0P X-TX0N

U5038 TX0P

1 2

X-TX1P X-TX1N TX0N

3

X-TX2P X-TX2N

CH1

CH4

GND

VDD

CH2

CH3

6

LAN_VDD33

7

X-TX1N

6

X-TX2N

5

X-TX2P

4

X-TX1P

3

X-TX0N

2

X-TX0P

1

TX1N

*[email protected]

X-TX3P X-TX3N

51@GST5009BLF

X-TX3P

TX1P

5 4

X-TX3N

8

LED1 = LAN_LINKLED#

1

SWR switch-mode regulator select Giga LAN pull High (default = 1)

0

LDO linear regulator select 10/100M LAN pull Low

NC4/3NC/3+

B

RX-/1NC2/2-

CKREQ# or CKREQ_G#

NC1/2+ RX+/1+

1

Normal function

0

ATE test mode

TX-/0TX+/0+ GND GND

9 10

LAN@130456-031

C5488

C5489

C5490

C5491

[email protected]/100V_6X

[email protected]/100V_6X

[email protected]/100V_6X

[email protected]/100V_6X

C5492 51@1000P/50V_4X

[email protected]

C5497 [email protected]/16V_4Y

C5494 51@1000P/50V_4X

C5498 [email protected]/16V_4Y

1 2 3

AVDD_CEN_T TX1P TX1N

4 5 6

AVDD_CEN_T TX2P TX2N

7 8 9

AVDD_CEN_T TX3P TX3N

10 11 12

TCT1 TD1+ TD1-

MCT1 MX1+ MX1-

TCT2 TD2+ TD2-

MCT2 MX2+ MX2-

TCT3 TD3+ TD3-

MCT3 MX3+ MX3-

TCT4 TD4+ TD4-

MCT4 MX4+ MX4-

24 23 22

TERM1 X-TX0P X-TX0N

21 20 19

TERM2 X-TX1P X-TX1N

18 17 16

TERM3 X-TX2P X-TX2N

15 14 13

TERM4 X-TX3P X-TX3N

TX2P

R9783

R9768

R9784

R9769

R9771

51@75/F_8

52@0_8

51@75/F_8

52@0_8

LAN@75/F_8

LAN@75/F_8

3

CH1 GND CH2

CH4 VDD CH3

6

Power on Strapping pin

TX3N

5 4

LAN_ACTLED

LAN_VDD33

LAN_VDD33

*[email protected]

R9767

LAN_LINKLED# R9770

[email protected]/F_6

[email protected]/F_6

B2A

C5495 51@10P/3KV_1808N

Quanta Computer Inc.

C3A

C5496 52@220P/3KV_1808X TX0P TX0N TX1P TX1N

C5493 C5526 C5532 C5546

PROJECT : BLG

[email protected]/50V_4N [email protected]/50V_4N [email protected]/50V_4N [email protected]/50V_4N

Size

Docum ent Num ber

Date: 3

2

Rev A1A

Atheros Lan

NB7 4

[email protected]/F_6

A

52@TST1284ALF

5

R9765

TX3P

TERM9

RN10

[email protected]

AVDD_CEN_T TX0P TX0N

1 2

R9766

TERM9

TX3P TX3N

RN9 1 3

1 3

A

2 4

2 4

TX2P TX2N

U5033

TERM3_C

TERM1_C

TERM4_C

TERM2_C

U5039 TX2N

Wednes day, February 01, 2012Sheet 1

35

of

48

5

4

3

2

Card Reader (AU6437B53-GDL-GR)

B2A R9773

CTRL3

1

2 IN 1 Card Reader

36

EMI E@33_4 SD_CD#

D

D

+3V_Card C5500

CTRL2 DATA3

R9777 R9779

E@33_4 E@33_4

BLM15BD121SN1D_300MA

SD_WP SD_D2 SD_D1 SD_D0 SD_CLK SD_CMD SD_D3

10 9 8 7 6 5 3 2 1

4

W/P DATA2 DATA1 DATA0 VSS2 CLK VSS1 CMD DATA3

SDR009-11-F

EMI

0.1U/16V_4Y

B2A

C/D CD COM

E@33_4 E@33_4 E@33_4

VDD

R9781 R9774 R9776

WP COM

R9775

DATA2 DATA1 DATA0

15

GND3 GND2

NBMD CTRL1 CTRL3 DATA1 DATA0

+1.8V_Card C5499

CTRL0

BLM15BD121SN1D_300MA

E3A

14

*0_4 *0_4 XTALSEL

R9778 R9780

R9772

13

CN2016 CTRL1

11 12

VCC_XD

C5501

*33P/50V_4N

1 2 3 4 5 6 7 8 9 10 11 12

*10K_4 [9] 48M_CARD [3,9,29,30,35,37]

PLTRST#

R9785 C5506

330_4

+3V_Card C5505

*1U/6.3V_4X

[9] USB_CARD [9] USB_CARD#

4.7U/6.3V_6X +1.8V_Card

C

VDDHM2 GND2 VDD3 XTALSEL NC5 NBMD CTRL1 CTRL3 DATA1 DATA0 DATA7 NC4

U5029 R9782

GPON7 EXT48IN RSTN REXT VD33P DP DM VS33P XI XO VDD1 V18

C5507

13 14 15 16 17 18 19 20 21 22 23 24

4.7U/6.3V_6X

B

VCC_XD +3V

VCC_XD

36 35 34 33 32 31 30 29 28 27 26 25

NC3 DATA6 CTRL0 DATA5 AU6437B53-GDL-GR CTRL2 DATA4 DATA3 DATA2 XDWPN XDCEN EEPDATA EEPCLK

SD_CLK

C5502

*10P/50V_4C

CTRL0 C5503 4.7U/6.3V_6X

CTRL2

C5504 0.1U/16V_4Y

DATA3 DATA2

CF_V33 NC1 AVDD5V AGND5V V33 VDDHM1 NC2 GND1 VDD2 CTRL4 XDCDN SDWPEN

+3V C

48 47 46 45 44 43 42 41 40 39 38 37

0.1U/16V_4Y

AU6437B53-GDL-GR

SDWP R9786

B

*0_4

+3V_Card +1.8V_Card

+3V_Card +3V_Card C5508

C5509

4.7U/6.3V_6X

0.1U/16V_4Y

C5510

C5511

0.1U/16V_4Y

0.1U/16V_4Y

SDWPEN (SD write protect enable) 1 : decided by SDWP(default) 0 : SD always write-able NBMD (Power saving mode enable) 1 : enable (default) 0 : disable

A

A

XTALSEL (Clock input selection) 1 : 48MHz input (default) 0 : 12MHz input

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Rev A1A

Card Reader(AU6437) Date: 5

4

3

2

Wednesday, February 01, 2012

Sheet 1

36

of

48

5

4

3

2

EC B2A

+3VPCU R9788

+A3VPCU

HCB1608KF-601T10_1A

R9790 2.2_6

+3V_VDD_EC

R9794

C5512

C5513

C5521

C5522

0.1U/16V_4Y

10U/6.3V_6X

0.1U/16V_4Y

10U/6.3V_6X

1

SM BUS

PU/Address

+3V

SMBUS Devices

1

PCH(S5) +3VPCU

G-sensor(S0)

2.2_6 MBCLK MBDATA 2ND_MBCLK 2ND_MBDATA

C3A

R9791 R9792 R9795 R9796

2

4.7K_4 4.7K_4 4.7K_4 4.7K_4

CPU Thermal(A)

VGA Thermal(A or S0)

124

[27] CEC_EC_HP [3,9,29,30,35,36]

7

PLTRST#

123

[30,32] USB_Norm al_EN#

125

[8] SERIRQ

9

[9,30,32] USB_Norm al_OC#

C

[38] [38] [38] [38] [38] [38] [38] [38]

MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7

[38] [38] [38] [38] [38] [38] [38] [38] [38] [38] [38] [38] [38] [38] [38] [38] [38] [38]

MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MY16 MY17

[40] MBCLK [40] MBDATA [9] 2ND_MBCLK [9] 2ND_MBDATA [16,27] 3ND_MBCLK [16,27] 3ND_MBDATA

[38] TPCLK [38] TPDATA [7] AC_PRESENT [30,31] USB_SC_EN#

54 55 56 57 58 59 60 61 53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33 70 69 67 68 119 120

MBCLK MBDATA 2ND_MBCLK 2ND_MBDATA 3ND_MBCLK 3ND_MBDATA

72 71 10 11

TPCLK TPDATA

77

[7] SUSCLK

R9826

[3] EC_PECI

43_4

+VTT

12 13

EC_PECR_R

GPIO85/GA20

C5527

D/A LPC

ECSCI/GPIO54

GPIO24 GPIO01/TB2 GPIO02 GPIO06/IOX_DOUT GPIO16 GPIO30 GPIO36 GPIO41 GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO GPO47/SCL4 GPIO50/PSCLK3/TDO GPIO51 GPIO52/PSDAT3/RDY GPIO53/SDA4 GPIO70 GPIO71 GPIO72 GPIO75 GPO76/SHBM GPIO77 GPIO81 GPO82/IOX_LDSH/TEST GPO84/IOX_SCLK/XORTR GPIO97

GPIO10/LPCPD LREST GPIO67/PWUREQ SERIRQ GPIO65/SMI

KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7

KBSOUT0/JENK KBSOUT1/TCK KBSOUT2/TMS KBSOUT3/TDI KB KBSOUT4/JENO KBSOUT5/TDO KBSOUT6/RDY GPIO56/TA1 TIMER KBSOUT7 GPIO20/TA2/IOX_DIN_DIO KBSOUT8 GPIO14/TB1 KBSOUT9/SDP_VIS KBSOUT10/P80_CLK KBSOUT11/P80_DAT GPIO15/A_PWM KBSOUT12/GPIO64 GPIO21/B_PWM TIMER KBSOUT13/GPIO63 GPIO13/C_PWM KBSOUT14/GPIO62 GPIO32/D_PWM KBSOUT15/GPIO61/XOR_OUT GPIO45/E_PWM GPIO60/KBSOUT16 GPIO40/F_PWM GPIO57/KBSOUT17 GPIO66/G_PWM GPIO33/H_PWM GPIO17/SCL1 GPIO22/SDA1 GPIO73/SCL2 GPIO74/SDA2 GPIO23/SCL3 GPIO31/SDA3

GPIO34

SMB GPIO87/SIN_CR GPIO46/TRST GPO83/SOUT_CR/TRIST

IR

GPIO37/PSCLK1 GPIO35/PSDAT1 GPIO26/PSCLK2 GPIO27PSDAT2

PS/2

GPIO00/EXTCLK

FIU

VTT PECI

NPCE885LA0DX

E3A

F_SDI/F_SDIO1 F_SDIO&F_SDIO0 F_CS0 F_SCK

GPIO55/CLKOUT/IOX_DIN_DIO

*0.1U/16V_4Y *22_4

GPIO94/DA0 GPIO95/DA1 GPIO96/DA2

KBRST/GPIO86

PCLK_591

R9830

3

98H

CEC(A)

4

GPIO11/CLKRUN

L5037

*SHORT_6

VCORF

29

[9] SCI#

GPIO90/AD0 GPIO91/AD1 GPIO92/AD2 GPIO93/AD3 GPIO05/AD4 GPIO04/AD5 GPIO03/AD6 GPIO07/AD7

A/D

AGND

[10] RCIN#

LFRAME LAD0 LAD1 LAD2 LAD3 LCLK

GND1 GND2 GND3 GND4 GND5 GND6

121 122

H=1.6mm

5 18 45 78 89 116

8

[7] CLKRUN# [10] GATEA20

+3VPCU

VDD

VCC1 VCC2 VCC3 VCC4 VCC5

3 126 127 128 1 2

[8,29] LFRAME# [8,29] LAD0 [8,29] LAD1 [8,29] LAD2 [8,29] LAD3 [9] PCLK_591

8769AGND

MMB(A)

U5030

VCC_POR VREF

R9799

*100K/F_4

TEMP_MBAT [40] ICMNT [40] AC SET_EC [40] USB_BUS_SW4 [31] USB_SC_OC# [9,30,31] USB_BUS_SW2 [31]

101 105 106

USB_BUS_SW3 VFAN1 [3]

6 64 79 93 114 109 15 80 17 20 21 24 25 26 27 28 73 74 75 82 83 84 91 110 112 107

DISPON_O ACIN [40]

PWRLED# SKU_STRAP_3 H_PROCHOT_EC

*10U/6.3V_6X

AC SET_EC

C5524

*10U/6.3V_6X

3ND_MBCLK 3ND_MBDATA

C3A

B2A R9804

[31]

NBSWON#

B2A

R9798 R9800

4.7K_4 4.7K_4

TP

D

+3V TPCLK TPDATA

1.2K/F_4

HWPG

LED PU/PD

LAN_P [35]

DNBSWON#

R9803 R9805 R9806 R9807

10K_4 10K_4 10K_4 10K_4

INTERNAL KEYBOARD MY0 STRIP SET ID EEPROM

[7]

DGPU_PWROK

NAOAC@10K_4

R9810

AOAC@10K_4

R9808

D3A

10K_4

R9809

10K_4

7

SCL SDA WP

+3VPCU

+3VPCU

U5031 6 5

[10,25,47,48]

+5V_S5

1 2 3

A0 A1 A2

C

8 4

VCC GND

C5525

M24C08-WMN6TP 0.1U/16V_4Y

ADDRESS: A0H RF_LED# [39] SUSLED_EC# [39] BAT_SAT0# [39] BAT_SAT1# [39] SUSON [42] MAINON [26,43,46] CAPSLED [38] BT_RFCTRL

R9816

R9819

SPI FLASH

[29]

B2A

SPI_SDI_uR USB3.0_EN

1K_4

ACZ_SDOUT_R 3G_EN [29]

R9818

*100K/F_4

*10K_4

PCH_SPI_SI

SPI_SDO_uR

[42]

[8]

PCH_SPI_SO

SPI_SCK_uR

+3VPCU

SUS_PWR_ACK R9825 R9827

4.7K_4

[8]

PCH_SPI_CS0# R9820

30

[8]

PCH_SPI_CLK

SPI_CS0#_uR

SPI_SDI_uR SPI_SDO_uR SPI_CS0#_uR SPI_SCK_uR

VCC_POR#

R9802

2ND_MBCLK 2ND_MBDATA

TEMP_ALERT# [10] FANSIG1 [3]

14

104 VREF_uR

+5V

RF_EN

B2A

*4.7K_4 *4.7K_4

+5VPCU

RF_LED#

SUSLED_EC# BAT_SAT0# BAT_SAT1# PWRLED#

[28]

SUSC# [7] MPWROK [7,45] RSMRST# [7] SLP_SUS# [7] RF_EN [29]

RF_EN

R9793 R9801

[38]

H_PROCHOT_EC [3] AMP_MUTE# [34] ID [40] WMAX_P [29] D/C# [40] S5_ON [41] LVDS_BKLT [7,16]

32 RF_LED# 118 SUSLED_EC# 62 BAT_SAT0# 65 BAT_SAT1# 22 16 81 66

85

*10U/6.3V_6X

C5520

LID591# [28] GFX_MAINON [47,48] PWRLED# [39] VRON [45]

31 SKU_STRAP_1 117 63

86 87 90 92

C5523

ICMNT

SUSB# [7]

SKU_STRAP_2

113 23 111

TEMP_MBAT +3VPCU

97 98 ICMNT 99 AC SET_EC 100 108 96 95 94

10K_4

[8] [8]

+3V_S5

[7]

+3VPCU

*SHORT_4

+A3VPCU

E3A

HWPG circuit

B

44

*0.1U/16V_4Y

VCORF_uR

C5519

0.1U/16V_4Y

103

C5518

*0.1U/16V_4Y

102

C5517

0.1U/16V_4Y

AVCC

C5516

0.1U/16V_4Y

19 46 76 88 115

C5515

10U/6.3V_6X D

B

98H

IDROM(A)

+3VPCU_EC C5514

37

Address

Battery(A)

+3VPCU

R9828 C5528

L5037 Can't del, DG link GND/AGND w 0ohm or one point

C5529 *10P/50V_4C

10K_4 1U/6.3V_4X

8769AGND

[48] GFX_PG [45] GFX_PWRGD

R9834

*OEV@0_4

R9832

*PIV@0_4

E3A [44] HWPG_VCCSA

[46] HWPG_1.8V SKU_STRAP_1

Power Button

R5138 R5137

Luxor@10K_4

+3VPCU [7,41] SYS_HWPG

Capetown@10K_4

Capetown@/Luxor@ SKU_STRAP_2 DNBSWON#

C5530

*0.1U/16V_4Y

NBSWON#

C5531

*0.1U/16V_4Y

A

Place on easy use location

SKU_STRAP_3

MS Strap

SKU_STRAP_1

EV@ / IV@

SKU_STRAP_2

Capetown@10K_4

R5140

Luxor@10K_4

13'' UMA

0

0

0

R5142

*10K_4

13'' DIS

0

0

1

14'' Capetown UMA

0

1

0

14'' Capetown DIS

0

1

1

14'' Luxor UMA

1

0

0

14'' Luxor DIS

1

0

1

R5144

EV@10K_4

R5143

IV@10K_4

+3VPCU

[42] HWPG_1.5V

*SHORT_4

R9836

*SHORT_4

R9837

*SHORT_4

R9841

*SHORT_4

HWPG

SKU_STRAP_3

R5141

+3VPCU

R9833

A

Quanta Computer Inc. PROJECT : Chief River Size

Docum ent Num ber

Rev A1A

EC-NPCE885L Date: 5

4

3

2

Wednes day, February 01, 2012 1

Sheet

37

of

48

5

4

INT KeyBoard

C5533 C5534 C5535 C5536

*220P/50V_4X *220P/50V_4X *220P/50V_4X *220P/50V_4X

MX7 MX2 MX3 MX4

C5537 C5538 C5539 C5540

*220P/50V_4X *220P/50V_4X *220P/50V_4X *220P/50V_4X

MX0 MX5 MX6 MX1

C5541 C5542 C5543 C5544

*220P/50V_4X *220P/50V_4X *220P/50V_4X *220P/50V_4X

MY7 MY13 MY12 MY15

36

C5549 C5550 C5551 C5552

*220P/50V_4X *220P/50V_4X *220P/50V_4X *220P/50V_4X

MY3 MY5 MY14 MY6

C5553 C5554 C5555 C5556

*220P/50V_4X *220P/50V_4X *220P/50V_4X *220P/50V_4X

MY2 MY1 MY0 MY4

C5557

*100P/50V_4N

MY17

C5558

*100P/50V_4N

MY16

K_LED_P MY16

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

D

3

2

1

Power board w LED

TP board

CN2018

38

MY16 [37]

MY17

MY17 [37]

K_LED_P MY2 MY1 MY0 MY4 MY3 MY5 MY14 MY6 MY7 MY13 MY8 MY9 MY10 MY11 MY12 MY15 MX7 MX2 MX3 MX4 MX0 MX5 MX6 MX1 K_LED_P CAPSLED

MY2 [37] MY1 [37] MY0 [37] MY4 [37] MY3 [37] MY5 [37] MY14 [37] MY6 [37] MY7 [37] MY13 [37] MY8 [37] MY9 [37] MY10 [37] MY11 [37] MY12 [37] MY15 [37] MX7 [37] MX2 [37] MX3 [37] MX4 [37] MX0 [37] MX5 [37] MX6 [37] MX1 [37]

D

+5V

CN2019

[10] ID_Detect

C5547 [email protected]/10V_4X

CAPSLED [37]

1 2 3 4 5 6

+5V_TP TPCLK_L TPDATA_L

[37] TPCLK [37] TPDATA +3V

1 2 3 4 5 6

CN2020 1 2 3 4

[37] NBSWON#

88513-064N

B2A

35

D3A

91504-344N

ID_Detect

default

Metal/IMR

H

TEXTURE

L

C5561 E@2200P/50V_4X

88513-044N

C5575 [email protected]/10V_4X

B2A

+3VPCU

MX1 MX6 MX5 MX0

10 9 8 7 6

RP15

1 10KX8 2 3 4 5

B2B

(10mils)

C

+3V

R9842

150_4

MX7 MX2 MX3 MX4

C

K_LED_P

HOLE

TP board HOLE3

*H-TC315BC276D118P2

1

HOLE2

1

1

HOLE1

*H-TC315BC276D118P2

CN2025 *H-TC276BC236D118P2

+5V [37] TPCLK [37] TPDATA

+5V_TP TPCLK_L TPDATA_L

[10] ID_Detect +3V

HOLE4

[13,14,29] CGDAT_SMB [13,14,29] CGCLK_SMB

CGDAT_SMB CGCLK_SMB

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8

1

*50503-0080N-001

*H-TC236D142PB

HOLE5

HOLE6

HOLE7

*H-TC236D161PB

1

1

B

1

B

*H-TC236D161PB

*H-TC236D161PB

C3A

*H-TC276BC217I166D146P2

*H-TC276BC217I166D146P2

*H-C256D146PT

1

HOLE12

1

HOLE11

1

HOLE10

1

HOLE9

1

HOLE8

*H-TC276BC217I166D146P2

*H-C256D146PT

C3A

*HG-C276D118P2-A

C3A HOLE18 6 5 4

HOLE19 6 5 4

7 8 9 1 2 3

7 8 9 1 2 3

HOLE17 6 5 4

7 8 9 1 2 3

HOLE16 6 5 4

7 8 9 1 2 3

1 2 3

HOLE15 6 5 4

7 8 9 1 2 3

HOLE14 6 5 4

7 8 9

*HG-C276D118P2

*HG-C276D118P2

*HG-C276D118P2

*HG-C276D118P2

*HG-C276D118P2

HOLE20

HOLE21

HOLE22

HOLE23

HOLE24

*H-C276I138D118P2 *H-C91D91N

*H-C91D91N

1

1

1

1

1

A

1

C3A HOLE13

*H-TC197BC131D91P2

A

*H-TC197BC131D91P2

*H-C91D91N

HOLE26 HOLE25

1

1

Quanta Computer Inc. *h-c236d118p2

PROJECT : Chief River

*O-BY3C-1 Size

Docum ent Num ber

Rev A1A

KB/TP&TP/PB/FL/LEB/MMB/B-CAS Date: 5

4

3

2

Wednes day, February 01, 2012 1

Sheet

38

of

48

5

LED

4

3

œŇġōņŅ

LED

2

1

LED

39

ŃłŕņœœŚ +5V

3

+5V_S5

+5VPCU

RF_LED#

[37] RF_LED#

R9843

1.2K/F_4

3G_WIMAX_LED#

1

LED1

2

12-21/S2C-AQ2R2B/2C

D

2

-BATLED0

R9844

2.2K_4

BAT_SAT0#

R9845

1.2K/F_4

BAT_SAT1#

C3A

R9848

NAOAC@0_4

R9863

AOAC@0_4

D

D3A

BAT_SAT0# [37]

1 3

-BATLED1

BAT_SAT1# [37]

LED2 12-12Z/S2ST3D-C31/2C(QN)

B2A

C3A

őŐŘņœ LED

ņŔŅġőųŰŵŦŤŵ

LED

+5VPCU

ŇŐœġŃłŕŕņœŚġōņŅ 2

-PWRLED

R9846

*1.5K/F_4

3

-SUSLED

R9847

1.2K/F_4

B2A

PWRLED#

ŇŐœġŘĮōłŏ ōņŅ

[37]

C3A

1

C

PWRLED#_Q

-BATLED1

ŇŐœġőŰŸŦųġōņŅ

3G_WIMAX_LED#

1

-PWRLED

1

3

SUSLED_EC#

SUSLED_EC#

[37]

-BATLED0

2

LED3 12-11Z/T3D-CP2Q2B12Y/2C(QN)

1

3 2

D2033 *PJMBZ5V6

3 -SUSLED

2

D2034 *PJMBZ5V6

D2035 *PJMBZ5V6

C

C3A

B

B

ņŎŊ

EMI VIN

VIN

VIN

B2A

B2A

+3V

+3V_S5

+3VPCU

+5V_S5

C2136 E@1U/25V_6X

C2137 E@2200P/50V_4X

C2138 E@1U/25V_6X C2145 *0.1U/16V_4Y C2142 E@2200P/50V_4X

C2144 E@2200P/50V_4X

C2146 *0.1U/16V_4Y

C2147 *0.1U/16V_4Y

C2148 *0.1U/16V_4Y

C2149 *0.1U/16V_4Y

C2156 *0.1U/16V_4Y

C2157 *0.1U/16V_4Y

C2158 *0.1U/16V_4Y

C2150 *0.1U/16V_4Y

C2151 *0.1U/16V_4Y

C2152 *0.1U/16V_4Y

C2153 *0.1U/16V_4Y

C2154 *0.1U/16V_4Y

C2155 *0.1U/16V_4Y

C2143 E@2200P/50V_4X

E3A

E3A

VIN

(13644,1700) C2118 E@1U/25V_6X

C2129 E@1U/25V_6X

C2135 E@1U/25V_6X

C2139 E@1U/25V_6X

C2140 E@1U/25V_6X

(2776,6392)

(3884,6592)

(13254,5454) (13054,1828)

(4664,6694)

(5201,6650)

(13333,5677)

C2141 E@1U/25V_6X

(2702,5916) (3534,5878)

(6949,6677)

(7047,5660)

(7807,5563)

(7361,6182)

A

A

VIN

+3V

+5V_S5

+3V_S5

B2A C2114 E@2200P/50V_4X

C2115 E@2200P/50V_4X

+5V

B2A C2116 [email protected]/25V_6X

C2117 E@2200P/50V_4X

C2119 *0.1U/16V_4Y

C2120 *0.1U/16V_4Y

C2121 *0.1U/16V_4Y

C2122 *0.1U/16V_4Y

C2123 *0.1U/16V_4Y

C2124 *0.1U/16V_4Y

C2125 *0.1U/16V_4Y

+1.5VSUS

+1.5V

B2A

C2126 [email protected]/10V_4X

C2127 *0.1U/16V_4Y

C2128 *0.1U/16V_4Y

C2130 *0.1U/16V_4Y

C2131 [email protected]/10V_4X

C2132 *0.1U/16V_4Y

C2133 *0.1U/16V_4Y

Quanta Computer Inc.

C2134 *0.1U/16V_4Y

PROJECT : Chief River Size

Document Number

Rev A1A

LED/EMI/Green CLK Date: 5

4

3

2

Sheet

Wednesday, February 01, 2012 1

39

of

48

5

4

3

VA1

PCN1

B2A 4

PF1 F1206HA15V024TM 1 2

DC_JACK

0.01_3720 PR1

PD1 3

1

VA2

1

PQ5001 TPCA8109

R1

1 VA0

2

2

VA3

2

P1

PQ5002 TPCA8109

VIN

B2A

1 2 3

1 2 3

5

5

BAT-V

PC2 [email protected]/25V_4X

PC25 E@1U/25V_6X

PC3 0.1U/25V_6X

PR2 220K/F_4

PC4 E@1U/25V_6X

4

PC1 E@2200P/50V_4X

2

1

SBR1045SP5-13

4

3 PR3 33K_6

PD2

50322-0044L-001

PR4 10/F_6

D

PR5 10/F_6

( Near by sense R side)

1SS355_100MA

PR7 220K/F_4

1

6

2

5

3 PR8 82.5K/F_6

PR6 10K_6

PC5 E@2200P/50V_4X

CSIN

3

TVS_SMAJ20A

PD3

2

1

D

4 PQ5003 IMD2AT108

+3VPCU

PQ5004 2N7002K_300MA

2

[37] D/C#

[37] MBCLK

9

PD4 TVLST2304AD0 2 3

TEMP_MBAT

CH1

CH4

VN

VP

CH2

CH3

13 6

MBDATA

5 4

MBCLK

22

DCIN

3.2V

2

88731ACIN

3

PR19 22K/F_6

4

PR21 SHORT_4

VREF

AON7410 0.01_3720 PR13

B2A 23

PL1 1

88731A_PHASE

1

0.01U/25V_4X

2

1

*1U/6.3V_4X

PC31

2

2

PR27

PC30

1

47P/50V_4N PR26 100/F_4

2

BAT-V

88731A_L_GATE PQ5006

19

PR14 [email protected]/F_6

AON7410

4

B2A

PR16 10/F_6

PR17 10/F_6

PC23 E@1000P/50V_4X

18

17

( Near by IC side)

( Near by sense R side) CSOP CSON

16

NC VBF GND

15

PR22

100_4

BAT-V

(Please place this R near by battery pack side)

29

12

GND

VCOMP

PR23 2.21K/F_6

+3VPCU

PC28

20

3.3UH_7X7_TOK

B

ICOMP

ID [37]

M-DATA M-CLOCK

PC32 PR28

0.01U/25V_4X

ICMNT

100K_4 47P/50V_4N

88731A_U_GATE

PC24 0.1U/10V_4X

NC

BAT-V

PC15 *10U/25V_8X

5

21

26

CSSN

CSOP

14

C3A B2A

6

100/F_4 BTS1E-9K8040

24

ACIN

NC

1K_4

TEMP_MBAT_C

PC29

DCIN

7

PR30 BAT-GND

PR25

PGND

PU1 ISL88731CHRTZ-T

ICM

5 PF2 F1206HA15V024TM 1 2

MBAT+

11

LGATE

NC

PCN2 10

ACOK

CSON

E3A

PR20 *100K_4

PHASE

8

+3VPCU

SCL

PC20 0.1U/25V_6X

PR15 49.9/F_6

+3VPCU

PR18 82.5K/F_6

B

UGATE

4

3 2 1

1

ID

BOOT

SDA

PC19 0.1U/25V_6X

5

10

VDDSMB

PQ5005 PR12 2.7_6 25

PC22 10U/25V_8X

11

C

PC21 10U/25V_8X

[37] MBDATA

VDDP

0.1U/10V_4X

VCC

+3VPCU PC18

27

1 33 32 31 30 28

ACIN

[37] ACIN

PC17 1U/6.3V_4X 1 2

PC14 *10U/25V_8X

PR11 4.7_6

NC GND GND GND GND CSSP

C

1U/6.3V_4X 2 PC13 10U/25V_8X

1

PC12 10U/25V_8X

PC9

PC11 *2200P/50V_4X

PC16 0.1U/10V_4X

PC10 *0.1U/25V_4X

PR9 10K/F_4

3 2 1

PC8 10U/6.3V_6X

VIN PR10 10K/F_4

( Near by IC side)

1 2 3 4 5 6 7 8 9

1

CSIP [37] AC SET_EC

[37]

100_4

MBDATA [37] MBCLK [37]

PC33 10U/6.3V_6X

1K_4 TEMP_MBAT [37]

1

PR29

2

A

PC34 0.01U/25V_4X

A

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Date:

Wednesday, February 01, 2012

Rev

CHARGER-ISL88731C 5

4

3

2

Sheet 1

A1A 40

of

48

5

4

3

2

1

VIN

VIN

1 PR32 2.2/F_8

PGOOD

1

AON7702A

PR41 15.4K/F_4

1 2

5

17

3 REF

VREG5

8

VOUT1 FB1

23

PQ5009

PC48 *1000P/50V_4X

LGATE2 OUT2 FB2

PQ5008

4 10 9

1

OCP:15A

4 PC45

+3V_S5

2

11

2.2_6 3V_PHASE2

12

3V_LGATE2

0.1U/25V_6X

PL3 +3.3V_1 2.2UH_7X7_TOK

7

PR37

4 5

3V_FB2 PQ5010 AON7702A

PR39 *0_2/S

PR44

PR43 *0_4/S

+3VPCU

Rds(on) 13m ohm

1

169K/F_4

2

PR47 10K_4

B2A

PC50 0.1U/25V_6X

2 PD5 BAV99W-7-F_150MA

[37]

PR46 0_6

E3A C3A

6.8K/F_4

PC49

C

*1000P/50V_4X 158K/F_4

PR45 10K/F_4

+

PR40

*2.2/F_6

PR42

Rds(on) 13m ohm

(Peak 13.47A, AVG 9.43A)

AON7410 3V_UGATE2 PR35

PC47

24 2

DDPWRGD_R

PHASE2

TOP Side

LGATE1

4

B2A

220U/6.3V_7343P_E25b

5V_FB1

PHASE1

PR33 *0_2/S

3 2 1

19

BOOT2

RT8223P

PR36

PR38 *0_2/S

1 2

20

5V_LGATE1

*2.2/F_6

1 2 3

+

220U/6.3V_7343P_E25b

PC46

2.2UH_7X7_TOK

5

+5V_1

2.2_6 5V_PHASE1

UGATE2

BOOT1

SKIPSEL GND GND

PL2

TONSEL

UGATE1

EMC

0.1U/25V_6X

PC43 1U/6.3V_4X

14 25 15

PC44

21 5V_UGATE1 PR34 1 25V_BST1 22

18

B2A

1 2 3

+5V_S5

C

EN

4

VREG3

13

VIN

OCP:15A

PU2

2

AON7410

16

PR200 0_4

ENTRIP1

5

(Peak 12.85A ,AVG 9A)

PC42

0.1U/25V_6X

D

+2VREF

10U/6.3V_6X

1

PC41

+3VPCU

5

E3A

PQ5007

B2A

2

P2

10U/6.3V_6X

ENTRIP2

D

PC39 [3] SYS_SHDN#

6

PC37 0.1U/25V_6X

PC35 0.1U/25V_6X

3 2 1

PC38 10U/25V_8X

+5VPCU

PC36 10U/25V_8X

VIN

PR48

PR203 SHORT_4

10K/F_4 +3VPCU

S5_ON

3

2 PD6 BAV99W-7-F_150MA

PR49 *10K_4

B

3 PC52 0.1U/25V_6X

1

DDPWRGD_R

SYS_HWPG

[7,37]

PR50

+3V_S5 +5V_S5

+15V_ALWP

PC53

22_8

0.1U/25V_6X

+15V

PQ5011 AON7406

MAIND

3

3 2 1

PQ5012 AO6402A

TOP Side

4

MAIND

4

MAIND

1 2 5 6 MAIND [26,42,46]

5

B

0.1U/25V_6X

PC51

1

TOP Side +3V A

A

(Peak 9.3515A, AVG 6.55A)

Quanta Computer Inc.

+5V

(Peak 4.7683A, AVG 3.338A)

PROJECT : Chief River Size

Document Number

Rev

System 3V/5V(TPS51123A) Date: 5

4

3

2

Sheet

Wednesday, February 01, 2012 1

41

A1A of

48

4

3

C3A

+3VPCU

PR53

*100K_4

S3_1.5V [26] S5_1.5V

16

PR57

PC60

2

1

+ [email protected]/F_6

1.5SUS_LG

0_8

(Peak 0.1A, AVG 0.07A)

PC62 0.22U/10V_4X PC63

RDSon=3.3m ohm

PR58 10K/F_4

E@1000P/50V_4X

PC104 +

PC59 *0.1U/10V_4X

PC181

*330U/2V_7343P_E9c

2 1U/6.3V_4X

+1.5VSUS

1.5UH_10X10

330U/2V_7343P_E9c

PC61 1

+1.5VSUS_SRC

5

PGND

+5V_S5

f : 400k Hz

B2A PL4

6

VDDQSNS

REFIN

9

1.5SUS_PHASE

11

10

9

8

GND 7

12

7

S5

S3

18

17

TRIP

19 MODE

21

20 PGOOD

22

PwPad-2

PwPad VREF 6

PC58

ESR : 9mΩ

S2

24 25 26

DRVL

(Peak 17.81A, AVG 12.46A)

FDMS3660S

13

S2

10U/6.3V_6X

VTTREF

SW V5IN

1.5SUS_HG

S2

10U/6.3V_6X

PC57

VTTGND

14

B2A D1

DRVH

PQ5013

15

G2

PR56

+SMDDR_VREF

VBST

TPS51216RUKR

VTT

OCP:20A D1

5

2.2/F_6

S1/D2

4

D

0.1U/25V_6X

D1

3

VLDOIN

PC54

G1

2 +1.5VSUS_SRC

VTTSNS

PwPad-3 PwPad-4 PwPad-5

1

+SMDDR_VTERM

PwPad-1

23

PR52

PR55

PU3

C

PC55 0.1U/25V_6X

SUSON [37]

PR54 SHORT_4

[37] HWPG_1.5V

P3

VIN

PR51 SHORT_4

8

D

200K_4

PR214

1

E3A

29.4K/F_4

B2A

2

Be careful to this two net name.

PC56 10U/25V_8X

5

C

*10U/6.3V_6X

+1.5VSUS

R1 Vout = (R1/R2) X 0.75 + 0.75

PC64 0.1U/10V_4X

B

PC66 0.01U/25V_4X

1 2 5 6

B

PR59 52.3K/F_4

MAIND 3

[26,41,46] MAIND

PQ5015 AO6402A

4

R2 +5V_S5

Vout =0.8(1+PR1/PR2)

PU4 U3C@G9661-25ADJF12U

[37] USB3.0_EN

PR60

U3C@0_4

PR82

*U3C@0_4

2 3 8 9

+3V_S5

PC69 U3C@1U/6.3V_4X

A

4

PC67 U3C@10U/6.3V_6X

PC68 [email protected]/10V_4X

VPP PGOOD VEN VIN GND GND

VO

7

+3V_S5

[email protected]/10V_4X

ADJ

PC65

NC

(Peak 0.498A, AVG 0.342A)

1 6

5

+1.5V

(Peak 0.167A, AVG 0.117A)

+1.05VSUS PR61 [email protected]/F_4

R1

PC70 U3C@10U/6.3V_6X

A

Quanta Computer Inc.

PR62 U3C@100K/F_4

PROJECT : Chief River Size

R2 4

3

Rev A1A

DDR1.5V Date:

5

Document Number

2

Wednesday, February 01, 2012

Sheet 1

42

of

48

5

4

3

2

1

P4

+3V_S5

D

D

PR63 10K_4 10/F_6

2

1

PC74 10U/25V_8X

B2A

+

PC105

RT8240BFB

[26,37,46]

MAINON PC78

E@1000P/50V_4X PC79

0.1U/10V_4X

0.1U/10V_4X

PC108 10U/6.3V_6X

6

[email protected]/F_6

PR69 0_4

B

C

PC77

C3A PC76 330U/2V_7343P_E9c

8

FB

+VTT +1.05V

PR215

5

RGND

GND

RT8240BDL

S2

1

(Peak 18.05A, AVG 12.63A)

PL5 1.0UH_7X7_TOK S2

LGATE

9

S2

12

RT8240BLX

6

PHASE

OCP:20A

PC73 *2200P/50V_4X

0.1U/25V_6X

RT8240BZQW

EN PAD

2

2.2_6

G2

13

PGOOD

7

8

RT8240BBST_1

S1/D2

9

[44] HWPG_VCCIO

4

7

VCC

UGATE BOOST

PC72 *0.1U/25V_4X

D1

CS

RT8240BDH

D1

10

51.1K/F_4

3

PC75

D1

PR67 C

PR68

PU5

G0

5

C3A

B2A PQ5021 FDMS3660S

G1

PR66 10K_4

RT8240BTON

2

+3V_S5

VIN

11

PC71 1U/6.3V_4X

1

PR65

RT8240BVCC

+5V_S5

PR64 *0_4

B

PR71 *100P/50V_4N PR72 PR73

0_4

VCCP_SENSE

PR75

0_4

VSSP_SENSE [5]

100_4

[5]

0_4

*10K/F_4

PR74

R1 R2

PR76 *0_4

Quanta Computer Inc. PROJECT : Chief River

A

Size

VOUT=(1+R1/R2)*0.5 4

Rev A1A

+VCCIO(RT8240BGQW) Date:

5

Document Number

3

2

Wednesday, February 01, 2012

Sheet 1

43

of

48

A

1

2

3

4

PR77

5

P5

2.2K_4

[37] HWPG_VCCSA

A

+5V_S5

PC80

VCCSA_VID1

[5]

VCCSA_VID0

[5]

A

1U/6.3V_4X PR78

2.2K_4

PC81 HWPG_VCCIO

[43]

OCP:8.12A

2.2U/6.3V_6X

13

PC122

EN

14 VID0

15 VID1

16 PGOOD

V5FILT

PGND

V5DRV

19

B

17

18

(Peak 6.000A ,AVG 4.200A) *0.033U/10V_4X

Total capacitor : 66uF

12

E3A

0.1U/25V_6X 20

ESR : 9mΩ f : 300k Hz

PC82 BST

PGND

SW

PGND

SW

B

+VCCSA

11 PL6

SW

10 0.47UH_7X7

7 VCCSA_VCCSSENSE_R PR216

R

0

0.9V

0

1

*0.8V

0

1

1

0

0.725V

1

1

0.675V

*0.85V

0.22U/10V_4X

PC90 0.01U/25V_4X

0

PC89

PR81 5.1K/F_4

+VCCSA

PC92 3300P/50V_4X

VCCSA_VID1

PC88 22U/6.3V_8X

8

PR80 *33K/F_4

VCCSA_VID0

PC87 22U/6.3V_8X

PR79

PC86 22U/6.3V_8X

100_4

PC107 22U/6.3V_8X

9

6

1

C

5

VIN

+5V_S5

MODE

SW

VOUT

VIN SLEW

SW

4

24

VIN

COMP

23

TPS51462RGER PU6

3

22

VREF

10U/6.3V_6X

PC85 0.1U/10V_4X

2

PC84 PC83 10U/6.3V_6X

GND

21

OPEN 33K

R

VCCSA_VCCSSENSE

C

0_4

+VCCSA

B2A

*0.8V *0.85V

PR95 *10K_4

Quanta Computer Inc.

D

*0.8V FOR SV TYPE *0.85V FOR LV/ULV TYPE

PROJECT : Chief River Size

Document Number

Rev A1A

+VCCSA(TI51461) Date: 1

2

[5]

3

4

Wednesday, February 01, 2012

Sheet

44 5

of

48

D

5

4

3

2

1

P6

B2A 95836_UGATE1G

+5V_S5

PC180 PIV@560U/2V_7343P_E4.5a_3pin

PC179 PIV@560U/2V_7343P_E4.5a_3pin

PC103 PIV@10U/6.3V_6X

PR204 *0_2/S

PC102 *[email protected]/10V_4X

PR70

PC194 PIV@22U/6.3V_8X

PC143 [email protected]/10V_4X

PC142 [email protected]/10V_4X

95836_UGATE1

PC116 0.22U/25V_6X

PR119 1K/F_4

10P/50V_4C 95836_COMP

PR123 3.65K/F_6

1

C3A +

+

+

+VCC_CORE

560U/2V_7343P_E4.5a_3pin

95836_PWM3

PC188

24

PL8 0.24UH_7X7

E3A

PC187

9

95836_PHASE1

560U/2V_7343P_E4.5a_3pin

95836_LGATE1

41

PC189 100U/25V_105CE_f

(Peak 53A ,AVG 53A)

+5V_S5 23

2

95836_PHASE1

330U/2V_7343P_E9c

95836_UGATE1

22

+

PC186

95836_BOOT1

PC119 10U/25V_8X

PQ5019 FDMS3606S

PR206

20 21

C

VIN PR111 2.2/F_6

95836_BOOT1

95836_LGATE1

PC124

PC192 PIV@22U/6.3V_8X

PR205

ISEN3/FB2

95836_LGATE2

11

ISEN2

ISEN1 13

12

ISUMP 14

ISUMN

RTN

COMP

95836_PHASE2

27

S2

18

28

S2

PAD

E3A

B2A

C3A

S2

PR122 3.83K/F_4

FB

PWM3

95836_UGATE2

G2

PR118 27.4K/F_4

29

PC190 PIV@22U/6.3V_8X

*0_2/S

LGATE1

PC195 PIV@22U/6.3V_8X

PC193 PIV@22U/6.3V_8X

*0_2/S

PHASE1

95836_BOOT2

D1

NTC

95836_LGATE1G

30

D1

UGATE1

34

PC118 [email protected]/25V_4X

BOOT1

NTCG

+VCC_GFX TDC : 35A PEAK : 46A OCP : 55A Width : 1400mil

PR109 *PIV@619/F_4

[email protected]/F_6

LGATE2

95836_PHASE1G

PC123

PHASE2

SDA

PR117 NTC_470K_4 PR121 [email protected]/F_4

UGATE2

ALERT#

VR_SVID_CLK PR115 PIV@NTC_470K_4

PU7 ISL95836HRZ-T

SCKL

VR_SVID_ALERT# VR_SVID_DATA

BOOT2

95836_UGATE1G

PR120

2

40

3 ISEN2G

ISEN1G

ISUMNG

1

37 COMPG

LGATE1G

PGOOD

+

[email protected]/10V_4X 32 33

S1/D2

PR116 [email protected]/F_4

PGOODG

95836_BOOT1G

+

PC114

D1

10

95836_NTC

PHASE1G

PC191 PIV@22U/6.3V_8X PC113 *PIV@3300P/50V_4X

G1

4

+VAXG PR106 PIV@NTC_10K_6

E@1000P/50V_4X

7

[5] VR_SVID_DATA

VR_ON

VR_HOT#

C3A

35 31

D

GFX_CORE Load Line : -3.9mV/A for GT2

PIV@1/F_4

2

[5] VR_SVID_ALERT#

95836_NTCG

PR114 54.9/F_4

BOOT1G

PR99

5

6

+1.05V

PR113 *75/F_4

PWM2G

VSUMG-

6

5

[5] VR_SVID_CLK

PC115 43P/50V_4N

PR105 PIV@11K/F_4

[email protected]/16V_4X

1

8

[email protected]/10V_4X ISUMNG

7

19

[3] H_PROCHOT#

PR112 130/F_4

VCCP VDD

PC110

ISUMPG

8

36

[37] GFX_PWRGD [3,7] DELAY_VR_PWRGOOD

connect to +5V (disable AXG-2)

PR100 PIV@453/F_4

UGATE1G 9

95836_VRON

Check pull up resister to 1.05V for H_PROCHOT#

ISUMPG

RTNG

25

95836_VDD

38

39

PR107 *499/F_4

*0_4

PR104 1.91K/F_4

0_4

PR110

PR108 100K_4

26

15

C

PR211

PC111 1U/6.3V_4X 95836_VCCP

16

[37] VRON

+1.05V PC112 1U/6.3V_4X

PR103 *1.91K/F_4

[7,37] MPWROK

0.1U/10V_4X

PR102 *100K/F_4

C5574

B2A

+3V_S5

PR98 PIV@1K/F_4

C3A

PR94 [email protected]/F_4 PC109

17

B2A

PR97 SHORT_6

FBG

PR96 SHORT_6

+3V_S5

PR92 [email protected]/F_6 ISUMPG

PR93 OEV@1K_4

*0_2/S

PR91 PC106

+5V_S5 +5V_S5

E3A

PC94 PIV@10U/25V_8X

PC96 [email protected]/25V_4X

2 5

6

95836_LGATE1G ISUMNG

Max. DCR=1.4m

[email protected]_7X7

+VAXG

PIV@1000P/50V_4X [email protected]/F_6

PC101 PIV@47P/50V_4N

PL7

PC120 10U/25V_8X

PR90 PIV@499/F_4

7

8

ISUMPG PC100 PIV@390P/50V_4X

S2

PR89 PIV@0_4 [email protected]/25V_4X

E3A S2

PC98 PIV@150P/50V_4N

G2

PR87 PIV@267K/F_4

D1

9

95836_PHASE1G PR86 [email protected]/F_4

S2

[5] VSS_AXG_SENSE

VSS_AXG_SENSE_R PC99

D1

[5] VCC_AXG_SENSE

PC91 [email protected]/25V_6X

35.7K/F_4

S1/D2

PR88 VCC_AXG_SENSE_R

D1

C3A

PR85 PIV@0_4

D

PQ5018 PIV@FDMS3606S

95836_BOOT1G

1

PR83 [email protected]/F_6

PC95 PIV@330P/50V_4X

G1

PR84 PIV@2K/F_4

PC97 *PIV@330P/50V_4X

PC93 PIV@10U/25V_8X

VIN

E3A

VSUM+ 95836_COMP

ISEN2

PC126 390P/50V_4X

B

PR131

PC130 150P/50V_4N

ISEN1

PR124

10K/F_4

VSUM-

PR127

1/F_4

C3A PR128

PC128 0.22U/10V_4X

B

VSUM-

B2A

C3A

2K/F_4 PR129

VSUM+

95836_UGATE2

VIN

PR140

0_4

VCC_SENSE_R

[5] VSS_SENSE

PR142

0_4

VSS_SENSE_R

C3A

ISEN2

PR144

10K/F_4

VSUM-

PR145

1/F_4

PR207

PR208

*0_2/S

*0_2/S

PR141 3.65K/F_6 VSUM+

0.24UH_7X7

VCORE Load Line : 1.9mV/A

C3A PR143

PC146 0.01U/25V_4X

A

(Peak 53A ,AVG 53A)

Max. DCR=1.1m

+VCC_CORE [email protected]/F_6

PR139 E@1000P/50V_4X

95836_LGATE2

PC144 *330P/50V_4X

PL9

PC145

5

6

7

8

S2

S2

S2

PC140 0.1U/10V_4X

*619/F_4

[5] VCC_SENSE

PC136 [email protected]/25V_4X

D1

E3A G2

PR138

9

95836_PHASE2

S1/D2

VSUMPC141 *2200P/50V_4X

D1

PC131 0.22U/25V_6X

PR136 NTC_10K_6

PR137 470/F_4

FDMS3606S

2

95836_BOOT2

PR135 11K/F_4

PQ5020 1

PR130 2.2/F_6

D1

C3A

PC139 680P/50V_4X

PR134 2.61K/F_4

G1

PC135 0.1U/10V_4X

PR133 2K/F_4

PC138 0.1U/10V_4X

267K/F_4 PR132 20.5K/F_4

10K/F_4 ISEN2

PC133 10U/25V_8X

PR126 499/F_4

PC127 0.22U/10V_4X

ISEN1 PC125 68P/50V_4C

PC137 10U/25V_8X

C3A

10K/F_4 ISEN1 A

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Rev A1A

+VCC_CORE+VGFX (ISL95836) 35W Date:

5

4

3

2

Wednesday, February 01, 2012

1

Sheet

45

of

48

5

4

3

+5V_S5

+3V_S5

PR217

2

*10K_4

PU8 G9661-25ADJF12U 4

0.1U/10V_4X

2 PR146

D

0_4 3 8 9

VEN

VO

VIN GND GND

NC

1

PC149 PC151 0.1U/10V_4X *0.1U/10V_4X

P7

HWPG_1.8V [37]

6

+1.8V

5

7

PC150 10U/6.3V_6X

+3V_S5

VPP PGOOD

B2A

R1

(Peak 1.242A, AVG 0.869A)

D

PC148 10U/6.3V_6X

PC147

MAINON

ADJ

[26,37,43]

1

PR147 12.7K/F_4

Vout =0.8(1+R1/R2)

R2

PR148 10K/F_4

C

C

VIN

+3V

PR149 1M_4

B2A

+5V

PR151 22_8

+SMDDR_VTERM

PR155 22_8

+VTT

PR225 22_8

+1.5V

PR226 22_8

B2A

+15V

PR154 22_8

PR150 1M_4

[26,41,42]

MAIND

3

6

3

PQ5035B

PQ5026A

5

2N7002KDW_115MA

2

2N7002KDW_115MA

4

1

1

PQ5035A 2

PQ5026B 5

2N7002KDW_115MA

PC152 2200P/50V_4X

2N7002KDW_115MA

B

2N7002KDW_115MA

4

PQ5025B 5

2N7002KDW_115MA PQ5024

6

3

PQ5025A 2

1

PR152 1M_4

2

MAINON

4

[26,37,43]

1

B

6

3

[26] MAINON_ON_G

PR153 100K_4 LTC044EUBFS8TL_30MA

Quanta Computer Inc.

A

PROJECT :Chief River Size

Document Number

Rev A1A

+1.8V/Discharge Date: 5

4

3

2

Wednesday, February 01, 2012

46

Sheet 1

of

48

A

5

4

3

2

1

P8

+5V_S5 PC153 2 1

PR156

EV@1U/6.3V_4X

E3A

PR157 [email protected]/F_6

[email protected]/F_6

VIN

PQ5028 EV@FDMS3606S

*PX@10K/F_4 PX@0_4 OEV@0_4

PR169 Seymour@332K/F_4

13

PR165

12

11

FB

PR168

VO

DGPU_PWROK

*[email protected]/10V_4X

SET1

R2 PR222 [email protected]/F_4

EV@0_4

1

PC156 EV@10U/25V_8X

[email protected]_10X10-O 2

5

PR163 [email protected]/F_6

Max. DCR=1.4m

+

[10,25,37,48] PC161 EV@1000P/50V_4X

ISL95870A_AGND

+

C

B2A

B2A

[email protected]/F_4

PR221 Thames@590K/F_4

R4

R3

Roc

PR172 PR220 [email protected]/F_4 [email protected]/F_4

PR173 Seymour@590K/F_4

PR167 *EV@10K_4

PR166 *EV@10K_4

FSEL

14

95870A_FB

PC163 [email protected]/16V_4X

+3VPCU

SET0

E3A

+3V_S5 PX_MODE [25,48] GFX_MAINON [37,48]

1

PC160 EV@330U/2V_7343P_E6b

PR161 PR162 PR212

15

PC162

9

PGOOD

OCSET

8

PR164 [email protected]/F_4

C

SREF

10

PR223 [email protected]/F_4

R1

6

CORE-PHASE1

EV@ISL95870AHRUZ-T 7

+VGPU_CORE

PL10 16

PC159 EV@330U/2V_7343P_E6b

EN

B2A

17

4

PU9

VID0

C3A

7

PHASE

[email protected]/25V_6X

8

VID1

PR160 [email protected]/F_6

EV@1K_4

PR159

UGATE

3

6

2

20

LGATE

PVCC

1

GFX_CORE_CNTRL0

RTN

+VGPU_CORE Fs=300K TDC : 20.5A Imax :30A OCP :36A

S2

5

BOOT

18

S2

GFX_CORE_CNTRL1

GND

D1

[email protected]/25V_6X

ISL95870A_AGND S2

[16] GFX_CORE_CNTRL0

19

D1

[16] GFX_CORE_CNTRL1

VCC

G2

4

PC154

+3V 9

PGND

PC158 3

B2A S1/D2

2

D1

G1

PR158 EV@0_6 ISL95870A_AGND

PC157 [email protected]/6.3V_6X

PC155 EV@10U/25V_8X

2

D

1

D

PR174

PC164 [email protected]/25V_6X

[email protected]/F_4 GFX_CORE_CNTRL0

GFX_CORE_CNTRL1

PR175 ISL95870A_AGND

PR170 *EV@10K_4

PR171 *EV@10K_4

Csen

PR178 [email protected]/F_4

[email protected]/F_4 PR176 EV@10/F_6

B2A

PR177 EV@10/F_6

R5 B

PR179

[email protected]/F_4

PR219

[email protected]/F_4

PR180

[email protected]/F_4

PR218

[email protected]/F_4

GPU_CORE_SEN

[19]

GPU_CORE_RTN

[19]

B

R6 Seymous XT +VGPU_CORE

VIN

GFX_CORE_CNTRL0

+VGPU_CORE

1

1

0.9V

1

0

1V

0

1

1.05V

0

0

1.15V

PR182 EV@22_8

PR181 EV@1M_4 PR210

GFX_CORE_CNTRL1

OEV@22_8

PR183 EV@1M_4

PQ5029 EV@LTC044EUBFS8TL_30MA

2

GFX_CORE_CNTRL1

GFX_CORE_CNTRL0

1

1

0.875V

1

0

0.9V

0

1

1V

0

0

1V

PQ5030 EV@2N7002K_300MA

1

PX@22_8

+VGPU_CORE

Thames XT

68.1K

18.7K

R2

31.6K

66.5K

R3

590K

590K

R4

332K

71.5K

R5

2.49K

2.32K

R6

2.49K

2.32K A

1

A

Thames XT

2

PX_MODE PR209

3

3

GFX_MAINON

Seymous XT R1

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Rev A1A

GPU Core ( ISL62881C) Date: 5

4

3

2

Wednesday, February 01, 2012

Sheet 1

47

of

48

5

4

3

2

1

P9

+3V_S5 +1.5VSUS

PR184 *EV@100K_4

DGPU_PWROK

PR189 OEV@0_4

VPP PGOOD

2

VEN

3 8 9

VIN GND GND

+1V_GPU

6

R9530

+1.8V_GPU

1 2 3

*OEV@0_8

5

5 PR188

Rg

PC168

[email protected]/F_6

PC170 EV@10U/6.3V_6X

PC169 EV@10U/6.3V_6X

EV@10U/6.3V_6X

PR187 EV@10K/F_4

DRV

PGD

PC172 EV@10U/6.3V_6X

3

EN FB

PR192 EV@100/F_6

=1.8V

OEV@0_4

PR190

PX@0_4

GFX_MAINON [37,47] DGPU_PWR_EN

6 2

PR191 EV@10K/F_4

+1V_GPU_PG PR213

PC175

1

Vout =0.8(1+R1/R2)

Rh PR193 EV@34K/F_6

1

2

PC173 *[email protected]/10V_4X

4

D

+5V_S5

VCC

PC171 [email protected]/10V_4X

B2A

PR186 *EV@100K_4

PU11 EV@G9334TB1U

5 NC

+3V_S5

PQ5031 EV@AON7406

GFX_PG [37]

7

+3V_S5

VO

+1.05V

1

PC166 [email protected]/10V_4X

1

PU10 EV@G9661-25ADJF12U

4

GND

PC167 [email protected]/10V_4X

PC165 EV@10U/6.3V_6X

4

PR185 PX@0_4

ADJ

DGPU_PWR_EN D

2

+5V_S5

PC174 [email protected]/10V_4X

[email protected]/50V_6X

Vout1 = (1+Rg/Rh)*0.5

VIN

(Peak 6.000A ,AVG 4.200A)

B2A C

+15V PQ5027B EV@2N7002KDW_115MA

PC26 E@1U/25V_6X

PR194 EV@1M_4

PR195 EV@1M_4

4

PC6

PX5@22_8 PR224

E@2200P/50V_4X

C

Total capacitor : 22uF

+3V_D

PQ5032 EV@AON7202

5

B2A

+1.5VSUS

5

PR201

*PX5@0_4

PR196

OEV@0_4

DGPU_PWROK

+1.5V_GPU

3

3

6

2 PR197 EV@1M_4

PQ5033

EV@22_8 PR199

2

PC176

2

PQ5027A EV@2200P/50V_4X EV@2N7002KDW_115MA

PQ5034 PX5@2N7002K_300MA

B2A PC177 EV@10U/6.3V_6X

1

1

PR198 EV@100K_4

1

[10,25,37,47]

4

GFXPG_1.5V_EN_D

[25,47] PX_MODE [25] DGPU_PWR_EN

3 2 1

PX@0_4

3

PR202

+1.5V_GPU EV@LTC044EUBFS8TL_30MA

B

B

Power On Sequence 1. +3V_GPU connect +3V 2.PX_PWRGOOD Enable +VGPU_CORE 3.DGPU_PWROK Enable(Delay) +1.8V_GFX 4. DGPU_PWR_EN Enable(Delay) +1.5V_GFX 5.DGPU_PWR_EN Enable(Delay) +1V_GFX A

A

Quanta Computer Inc. PROJECT : Chief River Size

Document Number

Rev A1A

+VGACORE Date: 5

4

3

2

Wednesday, February 01, 2012

Sheet 1

48

of

48

5

4

3

2

1

TE5

MODEL

Model

REV

1A

BY3/BY4 D

CHANGE LIST PAGE 8: Dual SPI ROM circuit modify for Win8. PAGE 8: C2010 change value to 15P/C2013 change value to 12P. PAGE 9: SMBUS/CLK REQ pin PU/PD resister pallerel resister to single resister. PAGE 10: R2185 change power to +3V. PAGE 10: R2160 MB_ID9 change to GPIO34. PAGE 16/28: d-GPU CRT Port change from Port6 to Port3. PAGE 17: C5045/C5049 change to 22P. PAGE 25: Del PX Mode PERST#_BUF double drawing. PAGE 30: C5345/C5348 change value to 22P. PAGE 31: Add RN12/RN13 CHOCK for EMI test.. PAGE 32: Add RN11/RN6 CHOCK for EMI test.. PAGE 34: Stuff C5438/C5439/C5440/C5441 for EMI test. PAGE 35: Reserve LAN power circuit. PAGE 36: r9781/r9774/r9776/r9777/r9779/r9733 to 33ohm for EMI test. PAGE 37: Reserve GPIO for USB3.0 Power enable/LAN power/Inform VGA power status. PAGE 39: LED3 change to single white color for PRD1.0 PAGE 39: Add C2136/C2137/C2138/C2118/C2129/C2135/C2142/C2144/C2143/C2139/C2140/C2141 for EMI test.

C

PAGE

FROM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A

To

D

C

B

B

A

A

DOC NO. 204 5

PROJECT MODEL :

BY3,BY4

PART NUMBER:

APPROVED BY: DRAWING BY:

4

3

Quanta Computer Inc.

DATE: REVISON: 2

PROJECT : BY3,BY4 Size

Document Number

Date:

Wednesday, February 01, 2012

Rev 1A

Change list 1

Sheet

49

of

49