Quanta Zhpzsp Schematic Da0zhpmb8f0
5 4 3 2 1 01 EJ-11/13 ZHP/ZSP (11 and 13") Intel Apollo Platform Block Diagram D DDR3L SO‐DIMM CH0 Total Maximum
Views 166 Downloads 6 File size 1MB
Recommend stories
- Author / Uploaded
- Jakpar Sidik
Citation preview
5
4
3
2
1
01
EJ-11/13 ZHP/ZSP (11 and 13") Intel Apollo Platform Block Diagram
D
DDR3L SO‐DIMM CH0 Total Maximum 32GB
PAGE 11 DDR3L On‐Board RAM CH1
DDR3L 1600/ MT/s
DDI 0
HDMI Conn PAGE 14
EDP
eDP
PAGE 14
G sensor
PAGE 16
PCB 8L STACK UP LAYER 1 : TOP LAYER 2 : SGND LAYER 3 : IN1(High) LAYER 4 : SVCC LAYER 5 : IN2(Low) LAYER 6: IN3(High) LAYER 7 : SGND LAYER 8 : BOT
PAGE 12 EMMC 5.0 32GB/64GB
EMMC
D
Intel ApolloM
PAGE 17 Power : 4 ~ 6 Watt
C
SMBus
Package : FCBGA 1296
Port0
SATA ‐ HDD Package : 9.5 (mm) Power : PAGE 17
SATA0 3GB/s
Size : 31 x 24 (mm)
Tj : 80°C SDP/105°C TDP
I2C
Touch Pad
C
32.768KHz PAGE 6
ZHigh : 1.32 (mm)
19.2 Mhz PAGE 4
Die Size : 8.89 x 10 (mm)
PAGE 15 Touch panel PAGE 14
USB3.0 Port0
1.8V BIOS+TXE SPI ROM(64Mb) PAGE 5
USB3.0 Conn PAGE 18
SPI Interface PAGE 2~10
Port0
USB 2.0 Interface
Port4
TPM
PAGE 21 LPC Interface
Port3
Keyboard
PAGE 15
PCIE Gen 2 x 1 Lane
LAN RTL8111H‐CG
Power :
Power :
Power :
Package : LQPF128
Package : QFN‐48
Package : QFN‐32
Size : 6 x 6 (mm) PAGE 19
Size : 14 x 14 (mm) PAGE 13
Port6
Touch Screen
CAMERA PAGE 14
PAGE 14
Port2
KB
Port5
B
Audio Codec ALC255
Embedded Controller IT8987CX LQFP
1.8V EC code SPI ROM(1Mb) PAGE 13
Port2
Azalia
B
Port7
Port3
NGFF Card & Half Mini Card 25 Mhz PAGE 26
WLAN / BT Combo
Size : 4 x 4 (mm) PAGE 20
PAGE 21
BOM option
USB2.0 Port x2
Card Reader RTS5170 Power :
PAGE 18
Package : QFN‐24 Size : 4 x 4 (mm) PAGE 22
EMMC
TPS@
Touch Screen
GS@
G-Sensor
AC@
IOAC
NAC@
Non-IOAC
VL@
LED Backlight
DB@
Debug Conn.
*TSI@
13" FAN
Speaker
PAGE 16
A
Universal Jack Headphone + MIC
Analog MIC 5
Touch Screen I2C
PAGE 19
A
TPM@
PAGE 19
DTPM
Quanta Computer Inc. PROJECT : ZHP/ZSP
PAGE 19
www.vinafix.vn 4
Note
EM@
3
2
Size
Document Number
Date:
Tuesday, July 26, 2016
Rev 1A
Intel Block Diagram Sheet 1
1
of
36
5
4
+1.35VSUS M_A_A[15:0]
M_A_A[15:0]
M_A_DQ[63:0]
3
02
11
M_A_DQ[63:0]
11
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 11 11 11
C
VREFQD/VREFCA 0 Ohm resistor should be un-stuffed by default. PDG 0.9 10/23 modify it 11 11
11 11
M_A_BS#0 M_A_BS#1 M_A_BS#2
11 11 11
M_A_CAS# M_A_RAS# M_A_WE#
11
M_A_CS#0
11
M_A_CS#1
11 11
M_A_CKE0 M_A_CKE1
M_A_VREF_DQ M_A_VREF_CA
GND
11 11
M_A_CAS# M_A_RAS# M_A_WE#
BH47 BG47 BG48
M_A_CS#0
AR43 AT43 BB41 BA41 BH61 BH60 BH58 BJ58
M_A_ODT0 AW43 M_A_ODT1 AW41 *0/J_4 *0/J_4
MEM_CH0_VREFDQ AT34 MEM_CH0_VREFCA AR35 DRAM_RCOMP0
AV34
M_A_CLK0 M_A_CLK0#
M_A_CLK0 M_A_CLK0#
BD45 BE45
M_A_CLK1 M_A_CLK1#
M_A_CLK1 M_A_CLK1#
BB48 BD48
R173 11 11
BJ48 BG49 BH57
M_A_CKE0 M_A_CKE1
M_A_ODT0 M_A_ODT1 R271 R270
BG50 BG51 BH51 BD41 BE41 BJ52 BG53 BG55 BH53 BG52 BH49 BH55 BG54 BG46 BG56 BG57
M_A_BS#0 M_A_BS#1 M_A_BS#2
M_A_CS#1
會缺料
105/F_4
M_A_DRAMRST# AR34
U21A
BXT_P_SOC_BGA1296
DDR3L_CH0_MA0_LPDDR3_CH0_CAB7 DDR3L_CH0_MA1_LPDDR3_CH0_CAB9 DDR3L_CH0_MA2_LPDDR3_CH0_CAB5 DDR3L_CH0_MA3_LPDDR3_NC DDR3L_CH0_MA4_LPDDR3_NC DDR3L_CH0_MA5_LPDDR3_CH0_CAA2 DDR3L_CH0_MA6_LPDDR3_CH0_CAA0 DDR3L_CH0_MA7_LPDDR3_CH0_CAA3 DDR3L_CH0_MA8_LPDDR3_CH0_CAA1 DDR3L_CH0_MA9_LPDDR3_CH0_CAA4 DDR3L_CH0_MA10_LPDDR3_CH0_CAB6 DDR3L_CH0_MA11_LPDDR3_CH0_CAA6 DDR3L_CH0_MA12_LPDDR3_CH0_CAA5 DDR3L_CH0_MA13_LPDDR3_CH0_CAB0 DDR3L_CH0_MA14_LPDDR3_CH0_CAA8 DDR3L_CH0_MA15_LPDDR3_CH0_CAA9
DDR3L_CH0_DQ0_LPDDR3_CH0_DQA0 DDR3L_CH0_DQ1_LPDDR3_CH0_DQA1 DDR3L_CH0_DQ2_LPDDR3_CH0_DQA2 DDR3L_CH0_DQ3_LPDDR3_CH0_DQA3 DDR3L_CH0_DQ4_LPDDR3_CH0_DQA4 DDR3L_CH0_DQ5_LPDDR3_CH0_DQA5 DDR3L_CH0_DQ6_LPDDR3_CH0_DQA6 DDR3L_CH0_DQ7_LPDDR3_CH0_DQA7 DDR3L_CH0_DQ8_LPDDR3_CH0_DQA8 DDR3L_CH0_DQ9_LPDDR3_CH0_DQA9 DDR3L_CH0_DQ10_LPDDR3_CH0_DQA10 DDR3L_CH0_DQ11_LPDDR3_CH0_DQA11 DDR3L_CH0_DQ12_LPDDR3_CH0_DQA12 DDR3L_CH0_DQ13_LPDDR3_CH0_DQA13 DDR3L_CH0_DQ14_LPDDR3_CH0_DQA14 DDR3L_CH0_DQ15_LPDDR3_CH0_DQA15 DDR3L_CH0_DQ16_LPDDR3_CH0_DQA16 DDR3L_CH0_DQ17_LPDDR3_CH0_DQA17 DDR3L_CH0_DQ18_LPDDR3_CH0_DQA18 DDR3L_CH0_DQ19_LPDDR3_CH0_DQA19 DDR3L_CH0_DQ20_LPDDR3_CH0_DQA20 DDR3L_CH0_DQ21_LPDDR3_CH0_DQA21 DDR3L_CH0_DQ22_LPDDR3_CH0_DQA22 DDR3L_CH0_DQ23_LPDDR3_CH0_DQA23 DDR3L_CH0_DQ24_LPDDR3_CH0_DQA24 DDR3L_CH0_DQ25_LPDDR3_CH0_DQA25 DDR3L_CH0_DQ26_LPDDR3_CH0_DQA26 DDR3L_CH0_DQ27_LPDDR3_CH0_DQA27 DDR3L_CH0_DQ28_LPDDR3_CH0_DQA28 DDR3L_CH0_DQ29_LPDDR3_CH0_DQA29 DDR3L_CH0_DQ30_LPDDR3_CH0_DQA30 DDR3L_CH0_DQ31_LPDDR3_CH0_DQA31 DDR3L_CH0_DQ32_LPDDR3_CH0_DQB0 DDR3L_CH0_DQ33_LPDDR3_CH0_DQB1 DDR3L_CH0_DQ34_LPDDR3_CH0_DQB2 DDR3L_CH0_DQ35_LPDDR3_CH0_DQB3 DDR3L_CH0_DQ36_LPDDR3_CH0_DQB4 DDR3L_CH0_DQ37_LPDDR3_CH0_DQB5 DDR3L_CH0_DQ38_LPDDR3_CH0_DQB6 DDR3L_CH0_DQ39_LPDDR3_CH0_DQB7 DDR3L_CH0_DQ40_LPDDR3_CH0_DQB8 DDR3L_CH0_DQ41_LPDDR3_CH0_DQB9 DDR3L_CH0_DQ42_LPDDR3_CH0_DQB10 DDR3L_CH0_DQ43_LPDDR3_CH0_DQB11 DDR3L_CH0_DQ44_LPDDR3_CH0_DQB12 DDR3L_CH0_DQ45_LPDDR3_CH0_DQB13 DDR3L_CH0_DQ46_LPDDR3_CH0_DQB14 DDR3L_CH0_DQ47_LPDDR3_CH0_DQB15 DDR3L_CH0_DQ48_LPDDR3_CH0_DQB16 DDR3L_CH0_DQ49_LPDDR3_CH0_DQB17 DDR3L_CH0_DQ50_LPDDR3_CH0_DQB18 DDR3L_CH0_DQ51_LPDDR3_CH0_DQB19 DDR3L_CH0_DQ52_LPDDR3_CH0_DQB20 DDR3L_CH0_DQ53_LPDDR3_CH0_DQB21 DDR3L_CH0_DQ54_LPDDR3_CH0_DQB22 DDR3L_CH0_DQ55_LPDDR3_CH0_DQB23 DDR3L_CH0_DQ56_LPDDR3_CH0_DQB24 DDR3L_CH0_DQ57_LPDDR3_CH0_DQB25 DDR3L_CH0_DQ58_LPDDR3_CH0_DQB26 DDR3L_CH0_DQ59_LPDDR3_CH0_DQB27 DDR3L_CH0_DQ60_LPDDR3_CH0_DQB28 DDR3L_CH0_DQ61_LPDDR3_CH0_DQB29 DDR3L_CH0_DQ62_LPDDR3_CH0_DQB30 DDR3L_CH0_DQ63_LPDDR3_CH0_DQB31
DDR3L_CH0_BA0_LPDDR3_CH0_CAB2 DDR3L_CH0_BA1_LPDDR3_CH0_CAB8 DDR3L_CH0_BA2_LPDDR3_CH0_CAA7 DDR3L_CH0_CAS_N_LPDDR3_CH0_CAB1 DDR3L_CH0_RAS_N_LPDDR3_CH0_CAB3 DDR3L_CH0_WE_N_LPDDR3_CH0_CAB4 DDR3L_CH0_CS0_N_LPDDR3_CH0_CS0A_N DDR3L_NC_LPDDR3_CH0_CS1A_N DDR3L_NC_LPDDR3_CH0_CS0B_N DDR3L_CH0_CS1_N_LPDDR3_CH0_CS1B_N DDR3L_CH0_CKE0_LPDDR3_CH0_CKE0A DDR3L_CH0_CKE1_LPDDR3_CH0_CKE1A DDR3L_NC_LPDDR3_CH0_CKE0B DDR3L_NC_LPDDR3_CH0_CKE1B DDR3L_CH0_ODT0_LPDDR3_CH0_ODTA DDR3L_CH0_ODT1_LPDDR3_CH0_ODTB MEM_CH0_VREFDQ MEM_CH0_VREFCA MEM_CH0_RCOMP DDR3L_CH0_CLKP0_LPDDR3_CH0_CLKP_B DDR3L_CH0_CLKN0_LPDDR3_CH0_CLKN_B DDR3L_CH0_CLKP1_LPDDR3_CH0_CLKP_A DDR3L_CH0_CLKN1_LPDDR3_CH0_CLKN_A DDR3L_CH0_RESET_N_LPDDR3_NC
DRAMRST 1
+1.35VSUS
R323 1K/F_4
12/23 follow Intel PDG 1.0 change R322 to 0 ohm.
DRAM
2
CPU
R322
*short_4
M_A_DRAMRST#_R
Section 1 of 12
11
2
1
M_A_DRAMRST#
1
3,9,11,12,28
D
B
2
AW48 AW47 BB43 AW45 AV48 AV47 BD43 BA45
C252 *0.1u/16V_4
BD47 BB47
DDR3L_CH0_CB0_LPDDR3_NC DDR3L_CH0_CB1_LPDDR3_NC DDR3L_CH0_CB2_LPDDR3_NC DDR3L_CH0_CB3_LPDDR3_NC DDR3L_CH0_CB4_LPDDR3_NC DDR3L_CH0_CB5_LPDDR3_NC DDR3L_CH0_CB6_LPDDR3_NC DDR3L_CH0_CB7_LPDDR3_NC DDR3L_CH0_DQSP8_LPDDR3_NC DDR3L_CH0_DQSN8_LPDDR3_NC
DDR3L_CH0_DQSP0_LPDDR3_CH0_DQSPA0 DDR3L_CH0_DQSN0_LPDDR3_CH0_DQSNA0 DDR3L_CH0_DQSP1_LPDDR3_CH0_DQSPA1 DDR3L_CH0_DQSN1_LPDDR3_CH0_DQSNA1 DDR3L_CH0_DQSP2_LPDDR3_CH0_DQSPA2 DDR3L_CH0_DQSN2_LPDDR3_CH0_DQSNA2 DDR3L_CH0_DQSP3_LPDDR3_CH0_DQSPA3 DDR3L_CH0_DQSN3_LPDDR3_CH0_DQSNA3 DDR3L_CH0_DQSP4_LPDDR3_CH0_DQSPB0 DDR3L_CH0_DQSN4_LPDDR3_CH0_DQSNB0 DDR3L_CH0_DQSP5_LPDDR3_CH0_DQSPB1 DDR3L_CH0_DQSN5_LPDDR3_CH0_DQSNB1 DDR3L_CH0_DQSP6_LPDDR3_CH0_DQSPB2 DDR3L_CH0_DQSN6_LPDDR3_CH0_DQSNB2 DDR3L_CH0_DQSP7_LPDDR3_CH0_DQSPB3 DDR3L_CH0_DQSN7_LPDDR3_CH0_DQSNB3
AY62 AY61 BE62 BG62 BD63 AW62 AW63 BD62 AV59 AU63 AU62 AV58 AV57 AT55 AT54 AY59 AY57 BB57 BD59 BF59 AV54 AY55 AV52 BD58 BE56 BD54 BF58 BE50 BD50 BB50 BA50 BB54 AR39 AV37 AW37 AR37 AT37 AT41 AR41 AW35 BJ44 BG39 BG40 BJ40 BG43 BG44 BH45 BH41 BA34 BE34 BD34 BD37 BB37 BE39 BD39 BB34 BJ38 BG34 BG33 BH33 BG38 BH37 BG37 BJ34 BB63 BC62 AT59 AT58 BB59 BB58 BD52 BB52 AV39 AW39 BJ42 BG42 BB35 BD35 BG36 BH35
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
D
C
B
M_A_DQS0 M_A_DQS#0 M_A_DQS1 M_A_DQS#1 M_A_DQS2 M_A_DQS#2 M_A_DQS3 M_A_DQS#3 M_A_DQS4 M_A_DQS#4 M_A_DQS5 M_A_DQS#5 M_A_DQS6 M_A_DQS#6 M_A_DQS7 M_A_DQS#7
M_A_DQS0 M_A_DQS#0 M_A_DQS1 M_A_DQS#1 M_A_DQS2 M_A_DQS#2 M_A_DQS3 M_A_DQS#3 M_A_DQS4 M_A_DQS#4 M_A_DQS5 M_A_DQS#5 M_A_DQS6 M_A_DQS#6 M_A_DQS7 M_A_DQS#7
11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11
A
A
Configuration SODIMM
Speed (MT/s) 1333/1600/1867
Channels 2
Raw Card A(2Rx16) C(1Rx16) B(1Rx8) F(2Rx8)
Maximum Total Capacity (GB)
Quanta Computer Inc.
32
PROJECT : ZHP/ZSP 5
4
3
2
Size
Document Number
Date:
Tuesday, July 26, 2016
Rev 1A
Valley 1/9 (DDRA) Sheet 1
2
of
36
5
M_B_A[15:0]
4
M_B_A[15:0]
M_B_DQ[63:0]
M_B_DQ[63:0] +1.35VSUS
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 M_B_BS0 M_B_BS1 M_B_BS2
M_B_BS0 M_B_BS1 M_B_BS2
BH6 BG8 BH15
12 12 12
M_B_CAS# M_B_RAS# M_B_WE#
M_B_CAS# M_B_RAS# M_B_WE#
BH4 BJ6 BH7
12
M_B_CS#0
M_B_CS#0
BD17 BB17 AV17 AW17
12
M_B_CKE0
TP14
M_B_CS#1
TP16
M_B_CKE0 M_B_CKE1
BG18 BG17 BH17 BJ16
M_B_ODT0_R M_B_ODT1
AW16 AV16
MEM_CH1_VREFDQ MEM_CH1_VREFCA
AT30 AR29
Modify it 10/17 12
BG9 BG10 BH9 BD16 BB16 BG11 BJ12 BG14 BG12 BH11 BG7 BH13 BG13 BH3 BG15 BG16
12 12 12
VREFQD/VREFCA 0 Ohm resistor should be un-stuffed by default. PDG 0.9
R181 TP15
M_B_ODT0
M_B_VREF_DQ M_B_VREF_CA
R260 R261
10/23 modify it 12 12
*0/J_4
*0/J_4 *0/J_4 R166
GND
會缺料
105/F_4
DRAM_RCOMP1 M_B_CLKP0 M_B_CLKN0
M_B_CLKP0 M_B_CLKN0
AV30 BD19 BE19 BB21 BD21
M_B_DRAMRST#
AR30
U21B
BXT_P_SOC_BGA1296
DDR3L_CH1_MA0_LPDDR3_CH1_CAB7 DDR3L_CH1_MA1_LPDDR3_CH1_CAB9 DDR3L_CH1_MA2_LPDDR3_CH1_CAB5 DDR3L_CH1_MA3_LPDDR3_NC DDR3L_CH1_MA4_LPDDR3_NC DDR3L_CH1_MA5_LPDDR3_CH1_CAA2 DDR3L_CH1_MA6_LPDDR3_CH1_CAA0 DDR3L_CH1_MA7_LPDDR3_CH1_CAA3 DDR3L_CH1_MA8_LPDDR3_CH1_CAA1 DDR3L_CH1_MA9_LPDDR3_CH1_CAA4 DDR3L_CH1_MA10_LPDDR3_CH1_CAB6 DDR3L_CH1_MA11_LPDDR3_CH1_CAA6 DDR3L_CH1_MA12_LPDDR3_CH1_CAA5 DDR3L_CH1_MA13_LPDDR3_CH1_CAB0 DDR3L_CH1_MA14_LPDDR3_CH1_CAA8 DDR3L_CH1_MA15_LPDDR3_CH1_CAA9 DDR3L_CH1_BA0_LPDDR3_CH1_CAB2 DDR3L_CH1_BA1_LPDDR3_CH1_CAB8 DDR3L_CH1_BA2_LPDDR3_CH1_CAA7 DDR3L_CH1_CAS_N_LPDDR3_CH1_CAB1 DDR3L_CH1_RAS_N_LPDDR3_CH1_CAB3 DDR3L_CH1_WE_N_LPDDR3_CH1_CAB4 DDR3L_CH1_CS0_N_LPDDR3_CH1_CS0A_N DDR3L_NC_LPDDR3_CH1_CS1A_N DDR3L_NC_LPDDR3_CH1_CS0B_N DDR3L_CH1_CS1_N_LPDDR3_CH1_CS1B_N DDR3L_CH1_CKE0_LPDDR3_CH1_CKE0A DDR3L_CH1_CKE1_LPDDR3_CH1_CKE1A DDR3L_NC_LPDDR3_CH1_CKE0B DDR3L_NC_LPDDR3_CH1_CKE1B DDR3L_CH1_ODT0_LPDDR3_CH1_ODTA DDR3L_CH1_ODT1_LPDDR3_CH1_ODTB MEM_CH1_VREFDQ MEM_CH1_VREFCA MEM_CH1_RCOMP DDR3L_CH1_CLKP0_LPDDR3_CH1_CLKP_B DDR3L_CH1_CLKN0_LPDDR3_CH1_CLKN_B DDR3L_CH1_CLKP1_LPDDR3_CH1_CLKP_A DDR3L_CH1_CLKN1_LPDDR3_CH1_CLKN_A DDR3L_CH1_RESET_N_LPDDR3_NC
DRAMRST +1.35VSUS
1
B
R146 1K/F_4
12/23 follow Intel PDG 1.0 change R322 to 0 ohm.
DRAM
2
CPU
R150
*short_4
M_B_DRAMRST#_R
12
2
C103 *0.1u/16V_4
AR21 AT21 AW23 AW21 BA19 AW19 BA23 BB23 BD23 BE23
DDR3L SODIMM/Memory Down: Populating CH1 only Note: Not supported on A-step. Only supported on B-step.
DDR3L_CH1_DQ0_LPDDR3_CH1_DQA0 DDR3L_CH1_DQ1_LPDDR3_CH1_DQA1 DDR3L_CH1_DQ2_LPDDR3_CH1_DQA2 DDR3L_CH1_DQ3_LPDDR3_CH1_DQA3 DDR3L_CH1_DQ4_LPDDR3_CH1_DQA4 DDR3L_CH1_DQ5_LPDDR3_CH1_DQA5 DDR3L_CH1_DQ6_LPDDR3_CH1_DQA6 DDR3L_CH1_DQ7_LPDDR3_CH1_DQA7 DDR3L_CH1_DQ8_LPDDR3_CH1_DQA8 DDR3L_CH1_DQ9_LPDDR3_CH1_DQA9 DDR3L_CH1_DQ10_LPDDR3_CH1_DQA10 DDR3L_CH1_DQ11_LPDDR3_CH1_DQA11 DDR3L_CH1_DQ12_LPDDR3_CH1_DQA12 DDR3L_CH1_DQ13_LPDDR3_CH1_DQA13 DDR3L_CH1_DQ14_LPDDR3_CH1_DQA14 DDR3L_CH1_DQ15_LPDDR3_CH1_DQA15 DDR3L_CH1_DQ16_LPDDR3_CH1_DQA16 DDR3L_CH1_DQ17_LPDDR3_CH1_DQA17 DDR3L_CH1_DQ18_LPDDR3_CH1_DQA18 DDR3L_CH1_DQ19_LPDDR3_CH1_DQA19 DDR3L_CH1_DQ20_LPDDR3_CH1_DQA20 DDR3L_CH1_DQ21_LPDDR3_CH1_DQA21 DDR3L_CH1_DQ22_LPDDR3_CH1_DQA22 DDR3L_CH1_DQ23_LPDDR3_CH1_DQA23 DDR3L_CH1_DQ24_LPDDR3_CH1_DQA24 DDR3L_CH1_DQ25_LPDDR3_CH1_DQA25 DDR3L_CH1_DQ26_LPDDR3_CH1_DQA26 DDR3L_CH1_DQ27_LPDDR3_CH1_DQA27 DDR3L_CH1_DQ28_LPDDR3_CH1_DQA28 DDR3L_CH1_DQ29_LPDDR3_CH1_DQA29 DDR3L_CH1_DQ30_LPDDR3_CH1_DQA30 DDR3L_CH1_DQ31_LPDDR3_CH1_DQA31 DDR3L_CH1_DQ32_LPDDR3_CH1_DQB0 DDR3L_CH1_DQ33_LPDDR3_CH1_DQB1 DDR3L_CH1_DQ34_LPDDR3_CH1_DQB2 DDR3L_CH1_DQ35_LPDDR3_CH1_DQB3 DDR3L_CH1_DQ36_LPDDR3_CH1_DQB4 DDR3L_CH1_DQ37_LPDDR3_CH1_DQB5 DDR3L_CH1_DQ38_LPDDR3_CH1_DQB6 DDR3L_CH1_DQ39_LPDDR3_CH1_DQB7 DDR3L_CH1_DQ40_LPDDR3_CH1_DQB8 DDR3L_CH1_DQ41_LPDDR3_CH1_DQB9 DDR3L_CH1_DQ42_LPDDR3_CH1_DQB10 DDR3L_CH1_DQ43_LPDDR3_CH1_DQB11 DDR3L_CH1_DQ44_LPDDR3_CH1_DQB12 DDR3L_CH1_DQ45_LPDDR3_CH1_DQB13 DDR3L_CH1_DQ46_LPDDR3_CH1_DQB14 DDR3L_CH1_DQ47_LPDDR3_CH1_DQB15 DDR3L_CH1_DQ48_LPDDR3_CH1_DQB16 DDR3L_CH1_DQ49_LPDDR3_CH1_DQB17 DDR3L_CH1_DQ50_LPDDR3_CH1_DQB18 DDR3L_CH1_DQ51_LPDDR3_CH1_DQB19 DDR3L_CH1_DQ52_LPDDR3_CH1_DQB20 DDR3L_CH1_DQ53_LPDDR3_CH1_DQB21 DDR3L_CH1_DQ54_LPDDR3_CH1_DQB22 DDR3L_CH1_DQ55_LPDDR3_CH1_DQB23 DDR3L_CH1_DQ56_LPDDR3_CH1_DQB24 DDR3L_CH1_DQ57_LPDDR3_CH1_DQB25 DDR3L_CH1_DQ58_LPDDR3_CH1_DQB26 DDR3L_CH1_DQ59_LPDDR3_CH1_DQB27 DDR3L_CH1_DQ60_LPDDR3_CH1_DQB28 DDR3L_CH1_DQ61_LPDDR3_CH1_DQB29 DDR3L_CH1_DQ62_LPDDR3_CH1_DQB30 DDR3L_CH1_DQ63_LPDDR3_CH1_DQB31 DDR3L_CH1_DQSP0_LPDDR3_CH1_DQSPA0 DDR3L_CH1_DQSN0_LPDDR3_CH1_DQSNA0 DDR3L_CH1_DQSP1_LPDDR3_CH1_DQSPA1 DDR3L_CH1_DQSN1_LPDDR3_CH1_DQSNA1 DDR3L_CH1_DQSP2_LPDDR3_CH1_DQSPA2 DDR3L_CH1_DQSN2_LPDDR3_CH1_DQSNA2 DDR3L_CH1_DQSP3_LPDDR3_CH1_DQSPA3 DDR3L_CH1_DQSN3_LPDDR3_CH1_DQSNA3 DDR3L_CH1_DQSP4_LPDDR3_CH1_DQSPB0 DDR3L_CH1_DQSN4_LPDDR3_CH1_DQSNB0 DDR3L_CH1_DQSP5_LPDDR3_CH1_DQSPB1 DDR3L_CH1_DQSN5_LPDDR3_CH1_DQSNB1 DDR3L_CH1_DQSP6_LPDDR3_CH1_DQSPB2 DDR3L_CH1_DQSN6_LPDDR3_CH1_DQSNB2 DDR3L_CH1_DQSP7_LPDDR3_CH1_DQSPB3 DDR3L_CH1_DQSN7_LPDDR3_CH1_DQSNB3
Section 2 of 12
1
M_B_DRAMRST#
1
03
12
D
12 12
2
12
2,9,11,12,28
C
3
DDR3L_CH1_CB0_LPDDR3_NC DDR3L_CH1_CB1_LPDDR3_NC DDR3L_CH1_CB2_LPDDR3_NC DDR3L_CH1_CB3_LPDDR3_NC DDR3L_CH1_CB4_LPDDR3_NC DDR3L_CH1_CB5_LPDDR3_NC DDR3L_CH1_CB6_LPDDR3_NC DDR3L_CH1_CB7_LPDDR3_NC DDR3L_CH1_DQSP8_LPDDR3_NC DDR3L_CH1_DQSN8_LPDDR3_NC
BJ26 BG30 BH31 BG31 BH27 BG27 BG26 BJ30 BA30 BB30 BE30 BD30 BE25 BB27 BD25 BD27 BG24 BJ20 BH23 BJ24 BG20 BG21 BH19 BG25 AT27 AW29 AR27 AT23 AV27 AR25 AR23 AW27 BF6 BD10 BE14 BB10 BA14 BB14 BD14 BE8 AV12 BD6 BD5 BB7 AV10 AY9 AY7 BF5 AU2 AT10 AT9 AU1 AY5 AV5 AV6 AV7 AY2 BD2 BD1 BE2 AW1 AW2 AY3 BG2
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
BG28 BH29 BD29 BB29 BJ22 BG22 AV25 AW25 BB12 BD12 BB5 BB6 AT5 AT6 BC2 BB1
M_B_DQSP0 M_B_DQSN0 M_B_DQSP1 M_B_DQSN1 M_B_DQSP2 M_B_DQSN2 M_B_DQSP3 M_B_DQSN3 M_B_DQSP4 M_B_DQSN4 M_B_DQSP5 M_B_DQSN5 M_B_DQSP6 M_B_DQSN6 M_B_DQSP7 M_B_DQSN7
D
C
B
M_B_DQSP0 M_B_DQSN0 M_B_DQSP1 M_B_DQSN1 M_B_DQSP2 M_B_DQSN2 M_B_DQSP3 M_B_DQSN3 M_B_DQSP4 M_B_DQSN4 M_B_DQSP5 M_B_DQSN5 M_B_DQSP6 M_B_DQSN6 M_B_DQSP7 M_B_DQSN7
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
A
A
Quanta Computer Inc. PROJECT : ZHP/ZSP 5
4
3
2
Size
Document Number
Date:
Tuesday, July 26, 2016
Rev 1A
Valley 2/9 (DDRB) Sheet 1
3
of
36
5
4
5,6,11,13,14,16,17,19,20,21,22,23,26,27,28,29,31,32,33 5,6,8,10,13,14,15,21,23,25,29,31
3
2
1
+3V +1.8V_S5
04
ZHP CPU P/N A-stage +3V
defalut
AJ0QKG2VT00 AJ0QKG3VT00
D
10K_4
14 14 14 14
14
C50 A50
HDMI_HPD_CON
AG7 AG9 AG12 AG10 AC6 AC5 AC7 AC9
INT_EDP_TXP0 INT_EDP_TXN0 INT_EDP_TXP1 INT_EDP_TXN1
AG6 AG5
EDP_RCOMP_P EDP_RCOMP_N
R147 402/F_4 14 14
AH10 AH9
INT_eDP_AUXP INT_eDP_AUXN
C54 A54
HDMI
14 14
C49 B49
SDVO_DATA SDVO_CLK
C52 B53 C53 B
C47 PCH_DISP_ON_C PCH_EDP_BLON_C B47 PCH_DPST_PWM_C C46 AG62 AF61 AG63 AE60 AF62 P29 R27
XTAL19_OUT XTAL19_IN
MDSI_A_DP_0 MDSI_A_DN_0 MDSI_A_DP_1 MDSI_A_DN_1 MDSI_A_DP_2 MDSI_A_DN_2 MDSI_A_DP_3 MDSI_A_DN_3 MDSI_A_CLKP MDSI_A_CLKN
MCSI_DPHY1.2_RCOMP DDI0_RCOMP_P DDI0_RCOMP_N MCSI_RX_DATA0_P MCSI_RX_DATA0_N GPIO_200 MCSI_RX_CLK0_P GPIO_199 MCSI_RX_CLK0_N MCSI_RX_DATA1_P EDP_TXP_0 MCSI_RX_DATA1_N EDP_TXN_0 MCSI_RX_DATA2_P EDP_TXP_1 MCSI_RX_DATA2_N EDP_TXN_1 MCSI_RX_CLK1_P EDP_TXP_2 MCSI_RX_CLK1_N EDP_TXN_2 MCSI_RX_DATA3_P EDP_TXP_3 MCSI_RX_DATA3_N EDP_TXN_3 MCSI_DPHY1.1_RCOMP EDP_RCOMP_P EDP_RCOMP_N MCSI_DP_0 MCSI_DN_0 EDP_AUXP MCSI_DP_1 EDP_AUXN MCSI_DN_1 MCSI_DP_2 DDI1_DDC_SDA MCSI_DN_2 DDI1_DDC_SCL MCSI_DP_3 MCSI_DN_3 DDI0_DDC_SDA DDI0_DDC_SCL MCSI_CLKP_0 MCSI_CLKN_0 PNL1_VDDEN MCSI_CLKP_2 PNL1_BKLTEN MCSI_CLKN_2 PNL1_BKLTCTL GP_CAMERASB0 PNL0_VDDEN GP_CAMERASB1 PNL0_BKLTEN GP_CAMERASB2 PNL0_BKLTCTL GP_CAMERASB3 GP_CAMERASB4 OSC_CLK_OUT_0 GP_CAMERASB5 OSC_CLK_OUT_1 GP_CAMERASB6 OSC_CLK_OUT_2 GP_CAMERASB7 OSC_CLK_OUT_3 GP_CAMERASB8 OSC_CLK_OUT_4 GP_CAMERASB9 GP_CAMERASB10 GP_CAMERASB11 OSCOUT OSCIN MDSI_A_TE Section 4 of 12 MDSI_C_TE
GND
PCH_DISP_ON
3
10K_4
AK7 AK6 AM5 AM6 AM12 AM10 AK13 AM13
14
Q3 PJA138K
3
2
2
1
AM9 AM7
1
PCH_DISP_ON_C
Q9 PJA138K
AP12 AP10 AR2 AR1 AP15 AP13 AP6 AP5
GND
+3V
AP2 AP3 F27
MNPH_RCOMP
150/F_4
H27 MCSI_RCOMP P17 M17 P21 R21 L17 J17 F17 E17
C
R104
M23 P23 L23 J23 J21 H21 M25 L25 F25 E25 H25 J25
R36 GND
10K_4 R49 10K_4
14
Q4 PJA138K
2
150/F_4
PCH_EDP_BLON_C
R109
Q8 PJA138K
2
GND
GND
+1.8V_S5
M19 L19 H19 F19 L37 P34 J34 H30 M37 F30 R35 L34 M34 M35 R34 E30
PCH_EDP_BLON
3
DDI0 HPD DDI1 HPD
eDP
AG1 AG2
SOC_DDI0_RCOMP_P SOC_DDI0_RCOMP_N
MIPI_I2C_SDA MIPI_I2C_SCL
MDSI_C_CLKP MDSI_C_CLKN
R45 R492
1
R486 402/F_4
DDI0_AUXP DDI0_AUXN
MDSI_C_DP_0 MDSI_C_DN_0 MDSI_C_DP_1 MDSI_C_DN_1 MDSI_C_DP_2 MDSI_C_DN_2 MDSI_C_DP_3 MDSI_C_DN_3
AP7 MDSI_RCOMP 150/F_4
PCH_DISP_ON_C PCH_EDP_BLON_C PCH_DPST_PWM_C
R86 R85 R87
*100K_4 *100K_4 *100K_4
+3V B
follow CRB v1.0 R30 10K_4 R46
PCH_DPST_PWM
10K_4
M45 M43
PCH_DPST_PWM
14
3
C
B51 C51
DDI0_TXP_0 DDI0_TXN_0 DDI0_TXP_1 DDI0_TXN_1 DDI0_TXP_2 DDI0_TXN_2 DDI0_TXP_3 DDI0_TXN_3
MDSI_RCOMP
Q5 PJA138K
2
2
1
PCH_DPST_PWM_C
Q6 PJA138K
1
AM16 AM15
DDI1_AUXP DDI1_AUXN
BXT_P_SOC_BGA1296
3
HDMI
AK3 AK2 AM3 AM2 AH3 AH2 AL2 AL1
IN_D2 IN_D2# IN_D1 IN_D1# IN_D0 IN_D0# IN_CLK IN_CLK#
DDI1_TXP_0 DDI1_TXN_0 DDI1_TXP_1 DDI1_TXN_1 DDI1_TXP_2 DDI1_TXN_2 DDI1_TXP_3 DDI1_TXN_3
1
AK16 AK15
U21D
3
AF2 AF3 AD3 AD2 AC1 AC2 AB3 AB2
14 14 14 14 14 14 14 14
D
R35
AJ0QKG4VT00
15P/50V_4 C320
1 2
XTAL19_OUT GND
Remove barswell hardware strap pin GP_CAMERASB08/GP_CAMERASB09/GP_CAMERASB11 10/22
A
XTAL19_IN
3 4
Y3 R431 200K/F_4 19.2MHZ +-20PPM
GND
GND
A
15P/50V_4 C319
2nd source:BG619200014 (TXC)
Quanta Computer Inc. PROJECT : ZHP/ZSP 5
4
3
2
Size
Document Number
Date:
Tuesday, July 26, 2016
Rev 1A
Valley 3/9 (Display) Sheet 1
4
of
36
5
4
Direct Connect Interface (DCI) then only USB Port 0 and Port 1 can be used MoW_WW42
+1.8V_S5
10/22 change USB3.0 to port
D
R136 *10K/F_4
USB3.0 Port
18 18 18 18
USB30_TX1+ USB30_TX1USB30_RX1+ USB30_RX1-
J1 J2 K9 1 K10 K3 K2 F2 G2 AC16
USB_VBUSSNS R142
R145 10K/F_4
137/F_4
R129
113/F_4
Y15
USB_RCOMP R137 Dualrole
*0_4
GND
GND
USB_SSIC_RCOMP AB15
+1.8V_S5 R68 R83
+1.8V_S5 18
SOC_USB_OC0 SOC_USB_OC1
10K_4 10K_4
B55 C55
SOC_USB_OC1 V12 V10 V16 V15 Y13 V13 V9 V7
TP9 TP8
USB3.0
Dualrole
18 18 18 18
USBP1+ USBP1USB2_CN2_P USB2_CN2_N USB2_CN3_P USB2_CN3_N
21 21 14 14 14 14 22 22
USB_BT4_P USB_BT4_N USB_TS5_P USB_TS5_N USB_CCD6_P USB_CCD6_N USB_CAR7_P USB_CAR7_N
Y9 Y10 AB6 AB7 AC12 AC10 V5 V6
TP62 TP61 TP6 TP7
W1 W2 T5 T6 Y3 Y2 T9 T7
USB 2.0 Port 1 USB 2.0 Port 2 C
AC15 AH13 AH12 AG16 AG15
GND
R615 *10K/F_4
3
2
Bluetooth Touch Screen CCD Card Reader
18 18
SATA ODD 17 17 17 17
SATA HDD
SATA_TXP0 SATA_TXN0 SATA_RXP0 SATA_RXN0
FST_SPI_D3_R FST_SPI_D2_R
R436 R437
*short_4 *short_4
A58 B58 B61 B60 C57 B57 C56
FST_SPI_D0 FST_SPI_D1 FST_SPI_D3 FST_SPI_D2 SOC_SPI_CS# SOC_SPI_CLK
U21C
BXT_P_SOC_BGA1296
USB3_P0_TXP USB3_P0_TXN USB3_P0_RXP USB3_P0_RXN USB3_P1_TXP USB3_P1_TXN USB3_P1_RXP USB3_P1_RXN
PCIE_WAKE3_N PCIE_WAKE2_N PCIE_WAKE1_N PCIE_WAKE0_N PCIE2_USB3_SATA3_RCOMP_P
USB2_VBUS_SNS
PCIE2_USB3_SATA3_RCOMP_N
USB_SSIC_RCOMP USB2_RCOMP USB2_OTG_ID USB_SSIC_0_TX_P USB_SSIC_0_TX_N USB_SSIC_0_RX_P USB_SSIC_0_RX_N USB2_OC0_N USB2_OC1_N
PCIE_P3_USB3_P4_TXP PCIE_P3_USB3_P4_TXN PCIE_P3_USB3_P4_RXP PCIE_P3_USB3_P4_RXN PCIE_P4_USB3_P3_TXP PCIE_P4_USB3_P3_TXN PCIE_P4_USB3_P3_RXP PCIE_P4_USB3_P3_RXN PCIE_P5_USB3_P2_TXP PCIE_P5_USB3_P2_TXN PCIE_P5_USB3_P2_RXP PCIE_P5_USB3_P2_RXN PCIE_P0_TXP PCIE_P0_TXN PCIE_P0_RXP PCIE_P0_RXN
USB2_DP0 USB2_DN0 USB2_DP1 USB2_DN1 USB2_DP2 USB2_DN2 USB2_DP3 USB2_DN3
PCIE_P1_TXP PCIE_P1_TXN PCIE_P1_RXP PCIE_P1_RXN
USB2_DP4 USB2_DN4 USB2_DP5 USB2_DN5 USB2_DP6 USB2_DN6 USB2_DP7 USB2_DN7
PCIE_P2_TXP PCIE_P2_TXN PCIE_P2_RXP PCIE_P2_RXN PCIE_CLKREQ0_N PCIE_CLKREQ1_N PCIE_CLKREQ2_N PCIE_CLKREQ3_N
SATA_P1_USB3_P5_TXP SATA_P1_USB3_P5_TXN SATA_P1_USB3_P5_RXP SATA_P1_USB3_P5_RXN SATA_P0_TXP SATA_P0_TXN SATA_P0_RXP SATA_P0_RXN
PCIE_CLKOUT0P PCIE_CLKOUT0N PCIE_CLKOUT1P PCIE_CLKOUT1N PCIE_CLKOUT2P PCIE_CLKOUT2N PCIE_CLKOUT3P PCIE_CLKOUT3N
FST_SPI_MOSI_IO0 FST_SPI_MISO_IO1 FST_SPI_IO3 FST_SPI_IO2 FST_SPI_CS1_N FST_SPI_CS0_N FST_SPI_CLK Section 3 of 12
RSVD_C1 RSVD_F1 RSVD_B4 RSVD_A4 RSVD_A18 RSVD_C19
PU@ page23 N62 P61 P62 R62
PCIE_WAKE3_N PCIE_WAKE2_N
F6
SOC_PCIE_COMP
F5
SOC_PCIE_COMN PCIE_TXP3_WLAN_C C345 PCIE_TXN3_WLAN_C C344
23 23
WLAN LAN
U21E
0.1U/16V_4 0.1U/16V_4
PCIE_TXP3_WLAN PCIE_TXN3_WLAN PCIE_RXP3_WLAN PCIE_RXN3_WLAN
PCIE_CLKREQ3_WLAN# PCIE_CLKREQ2_LAN# PCIE_CLKREQ1# PCIE_CLKREQ0#
R188 R187 R579 R581
21 21 21 21
WLAN x1
10
10K_4 10K_4 10K_4 10K_4
need check
R1 R2 T10 T12 T2 T3 M5 M6
PCIE_TXP2_LAN_C PCIE_TXN2_LAN_C
AK62 AH62 AH61 AJ62
C355 C354
PCIE_CLKREQ0# PCIE_CLKREQ1# PCIE_CLKREQ2_LAN# PCIE_CLKREQ3_WLAN#
0.1U/16V_4 0.1U/16V_4
PCIE_TXP2_LAN PCIE_TXN2_LAN PCIE_RXP2_LAN PCIE_RXN2_LAN
20 20 20 20
3.3V 3.3V 3.3V 3.3V
LAN x1
20 20 21 21
GPIO_110
GPIO_110
GPIO_111 GPIO_112 GPIO_113
GPIO_111 GPIO_112 GPIO_113
10
GPIO_117
GPIO_117
R164 TP3
10 10
GPIO_120 GPIO_121 TP57
10
GPIO_123
Modify LPC 10/27
R482 R483
CLK_24M_DEBUG 21 CLK_TPM 13,21 CLKRUN# 13,21 LPC_LFRAME# 21,23 SOC_SERIRQ
DB@20_4 TPM@20_4
Modify LPC 11/02 CLK_PCIE_LANP CLK_PCIE_LANN CLK_PCIE_WLANP CLK_PCIE_WLANN
GPIO_104 GPIO_105 GPIO_106
13,21 LPC_LAD0 13,21 LPC_LAD1 13,21 LPC_LAD2 13,21 LPC_LAD3 13 CLK_PCI_EC
21
20 21
GPIO_104 GPIO_105 GPIO_106
10 10 10
+1.8V_S5
LPC Signal As same as Braswell 1.8V/3.3V
PCIE_CLKREQ2_LAN# PCIE_CLKREQ3_WLAN#
C11 B11 C10 A10 A7 B8 B7 B5
up & Low Resitance
LAN WLAN
F58 K55 F61 H57 H58 F62 D61 E56 D59 C62 E62
SOC_Override GPIO_120 GPIO_121 GPIO_123
Y61 Y62 W62 W63
20_4 20_4 20_4 20_4
LPC_LAD0_R LPC_LAD1_R LPC_LAD2_R LPC_LAD3_R
R484
20_4
SOC_CLKOUT_0 AB61 SOC_CLKOUT_1 AA62
R475 R128 R130
20_4 20_4 20_4
10
GPIO_39 TP53
10
GPIO_40
10
GPIO_43 TP2
10
GPIO_44
10
GPIO_47 TP4
10
GPIO_48
TP58
A18 C19
2.2K_4
F54 F52 H52 H54 J52
R477 R479 R473 R476
TP51
C1 F1 B4 A4
V58 T58 T59 V51 V52 Y49 V55 V57 V54 Y51 Y58
EMMC_DATA_0 EMMC_DATA_1 EMMC_DATA_2 EMMC_DATA_3 EMMC_DATA_4 EMMC_DATA_5 EMMC_DATA_6 EMMC_DATA_7 EMMC_RCLK EMMC_CMD EMMC_CLK 10 10 10
+1.8V_S5
Swap WLAN / LAN PCIE Port 10/17
V3 V2 P7 P6
17 17 17 17 17 17 17 17 17 17 17
R107 402/F_4
N2 M2 H5 H6 L2 L1 K7 M7
V62 SOC_CLKRUN# LPC_LFRAME#_R V61 SOC_SERIRQ_R AB62 B45 C45 A46 C44
GPIO_39 GPIO_40
B43 C43 A42 C42
GPIO_43 GPIO_44 GPIO_47 GPIO_48 SOC_EXT_SMI#
H41 J41 L41 M41
TP5
B
VCC_SPI_BIOS
11/28
1/27 Modify
SPI NOR FLASH
Add it 0/J_4
3
R138
C23
R417
GND 3.3K/F_4
FST_SPI_D2_R 3
R416
3.3K/F_4
FST_SPI_D3_R 7
VCC WP#
SPI_SI SPI_SO CS# SPI_SCK
SPI_HOLD GND
5 2 1 6
SOC_SPI_MOSI_R SOC_SPI_MISO_R SOC_SPI_CS#_R SOC_SPI_CLK_R
R55 R50 R51 R48
*short_4 *short_4 *short_4 33/J_4
FST_SPI_D0 FST_SPI_D1 SOC_SPI_CS# SOC_SPI_CLK
13
ME_WR#
R163
*short_4
SOC_Override_NM 2 2N7002K Q17
0 = No Override (Normal Operation) 1 = Override
4
1
8
SOC_Override
P51 T52 P57 T54 T55 T57 P58 AB55 AC49 AC48 AC51 AB51 AC52 AB58 AB54
U19
0.1U/16V_4 VCC_SPI_BIOS
EMMC_D0 EMMC_D1 EMMC_D2 EMMC_D3 EMMC_D4 EMMC_D5 EMMC_D6 EMMC_D7 EMMC_RCLK EMMC_CMD EMMC_CLK
GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_20 GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 GPIO_30 GPIO_31 GPIO_32 GPIO_33
SIO_SPI_0_CLK SIO_SPI_0_FS0 SIO_SPI_0_FS1 SIO_SPI_0_RXD SIO_SPI_0_TXD SIO_SPI_1_CLK SIO_SPI_1_FS0 SIO_SPI_1_FS1 SIO_SPI_1_RXD SIO_SPI_1_TXD SIO_SPI_2_CLK SIO_SPI_2_FS0 SIO_SPI_2_FS1 SIO_SPI_2_FS2 SIO_SPI_2_RXD SIO_SPI_2_TXD LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_CLKOUT0 LPC_CLKOUT1 LPC_CLKRUN_N LPC_FRAME_N LPC_SERIRQ Section 5 of 12
ISH_GPIO_0 ISH_GPIO_1 ISH_GPIO_2 ISH_GPIO_3 ISH_GPIO_4 ISH_GPIO_5 ISH_GPIO_6 ISH_GPIO_7 ISH_GPIO_8 ISH_GPIO_9
LPSS_UART0_TXD LPSS_UART0_RXD LPSS_UART0_RTS_N LPSS_UART0_CTS_N LPSS_UART1_TXD LPSS_UART1_RXD LPSS_UART1_RTS_N LPSS_UART1_CTS_N
LPSS_I2C0_SDA LPSS_I2C0_SCL
LPSS_UART2_TXD LPSS_UART2_RXD LPSS_UART2_RTS_N LPSS_UART2_CTS_N
LPSS_I2C1_SDA LPSS_I2C1_SCL LPSS_I2C2_SDA LPSS_I2C2_SCL
SDIO_PWR_DWN_N SDIO_D0 SDIO_D1 SDIO_D2 SDIO_D3 SDIO_CMD SDIO_CLK
LPSS_I2C3_SDA LPSS_I2C3_SCL LPSS_I2C4_SDA LPSS_I2C4_SCL
SDCARD_LVL_WP SDCARD_D0 SDCARD_D1 SDCARD_D2 SDCARD_D3 SDCARD_CMD SDCARD_CLK SDCARD_CD_N
LPSS_I2C5_SDA LPSS_I2C5_SCL LPSS_I2C6_SDA LPSS_I2C6_SCL LPSS_I2C7_SDA LPSS_I2C7_SCL
6,23
E34 SOC_GPIO_RCOMP
200/F_4
R102
V59
EMMC_RCOMP
200/F_4
R127
A38 B33 C39 B39 B35 A34 B31 H39 B29 A30 L39 C34 E39 C30 C38 F39 C36 C35 J39 C33 B27 C26 A26 B25 C25 C27 C31 C29 B37 H35 C37 H34 F35 F34
BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 BOARD_ID4 BOARD_ID5 Gsensor_INT
*short_4
5
R91 R96 R76 R409 R103
Add R1011 10/27 GND
D
BOARD_ID0
0_4
+1.8V_S5 Gsensor_INT
PCH_ODD_EN
23
*short_4
R403
SOC_KBC_SCI
23
PU@ page23
TP_INT#
TP_INT#
TP_INT_C SATA_GP1 SATA_GP0 SATA_DEVSLP0
TP_INT_C
TP56 TP55 *0_4
R411
SATA_LED#
15 23
Touch panel
DEVSLP0_R
Add RAM ID 10/15 the trace need >1000 mil
Follow APL PDG 0.9 33 ohm +-5%
10/29 Modify it
SPI ROM
Vender Size
Quanta P/N
Vender P/N
1 Q35
1.8V
B-Test Use
GGD WND
*10K_4 10K_4 10K_4 10K_4 10K_4 10K_4
Touch Screen function 0 = Non Touch Screen 1 = Touch Screen
Borad id1 =0 Borad id1 =1
Board ID 2
0 = Both onboard RAM and SODIMM 1 = SODIMM only
有EMMC 沒有EMMC
Board ID 3
G-Senor function 0 = Non G-Senor 1 = G-Senor
Board ID 4
DTPM function 0 = Non DTPM 1 = DTPM
Board ID 5
Reserve for UMA and GPU 0 = Reserve 1 = Reserve
C
AR62 AR63
I2C_0_SDA I2C_0_SCL
AN62 AM61
I2C_1_SDA I2C_1_SCL
AP59 AP58
I2C_2_SDA I2C_2_SCL
AM62 AL62
I2C_3_SDA I2C_3_SCL
R501 R494
*TSI@0_4 *TSI@0/J_4
AP52 AP54
I2C_4_SDA I2C_4_SCL
R193 R190
*short_4 *short_4
AP49 AP51
I2C_5_SDA I2C_5_SCL
I2C_0_SDA I2C_0_SCL
R508 R507
*1K/J_4 *1K/J_4
AL63 AK61
I2C_6_SDA I2C_6_SCL
I2C_1_SDA I2C_1_SCL
R503 R497
*1K/J_4 *1K/J_4
AP62 AP61
I2C_NFC_SOC_SDA I2C_NFC_SOC_SCL
I2C_2_SDA I2C_2_SCL
R175 R180
*1K/J_4 *1K/J_4
I2C_3_SDA I2C_3_SCL
R502 R495
*TSI@1K/J_4 *TSI@1K/J_4
I2C_4_SDA I2C_4_SCL
R192 R191
1K/J_4 1K/J_4
I2C_5_SDA I2C_5_SCL
R204 R197
*1K/J_4 *1K/J_4
I2C_6_SDA I2C_6_SCL
R496 R491
*1K/J_4 *1K/J_4
I2C_NFC_SOC_SDA I2C_NFC_SOC_SCL
R506 R505
*1K/J_4 *1K/J_4
R203 R200 R186 R198
TP13 TP12 TP10 TP11
33_4 33_4 33_4 33_4
PCH_AZ_CODEC_BITCLK PCH_AZ_CODEC_SYNC PCH_AZ_CODEC_SDIN0 PCH_AZ_CODEC_SDOUT
19 19 19 19
PCH_AZ_CODEC_SDIN0
SPKR
ACZ_SYNC
I2C_3_SDA_R I2C_3_SCL_R
14 14
I2C_4_SDA_R I2C_4_SCL_R
15 15
2016/01/21 Intel request change to 680ohm Can remove (un-stuff) for QS sample
Touch panel Touch pad
change RAM ID PU to +1.8V_S5 11/02 *10K_4 10K_4 10K_4 10K_4
RAM_ID0 RAM_ID1 RAM_ID2 RAM_ID3
R72 R70 R74 R71
Q PN
+1.8V_S5 10K_4 *10K_4 *10K_4 *10K_4
Mfr. PN
B
+1.8V_S5
T3 T2
Vender RAM_ID 17
*2N7002K
R201
GND
R395 *10K_4
DEVSLP0
*249/F_4
R202 *680/F_4
19
R92 R88 R93 R89
8M QE=1 AKE5EG-0Q01 GD25LB64CSIGR 8M QE=1 AKE5EZN0N01 W25Q64FWSSIQ
4
R426 R407 R425 R422 R428 R429
ACZ_BCLK ACZ_SYNC ACZ_SDIN0 ACZ_SDOUT UART2_RXD UART2_TXD UART2_RTS UART2_CTS
RAM ID
3
BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 BOARD_ID4 BOARD_ID5
Board ID 1
2
A-stage stuff Socket
23
AM48 AK58 AK51 AM54 AM51 AM49 AM57 AM55 AM52 AK57
+3V
R396 *100K/F_4
TPS_SEL
BIOS Strap Description
Board ID 0
TP54
RAM_ID0 RAM_ID1 RAM_ID2 RAM_ID3
10K_4 *10K_4 *10K_4 GS@10K_4 *10K_4 *10K_4
Hardware ID
Touch pad
R401
BOARD ID R404 R399 R406 R405 R427 R402
TP52
GPIO_11
Add it, follow CRB V1.0 11/5 R387
TP_RST#_Q
LSB:RAM_ID0,MSB:RAM_ID3
DEVSLP0_R VCC_SPI_BIOS
GPIO_RCOMP EMMC_RCOMP
+1.8V_S5
SPI Socket P/N:DFHS08FS023
SOC_SPI_CS#
A
VSTBY_FSPI
V49
RSVD_V49
10K_4 10K_4 10K_4 10K_4 10K_4
GND
VCC_SPI_BIOS *3.3K/F_4
TP_INT# TP_INT_C TP_RST#_Q Gsensor_INT SOC_EXT_SMI#
BXT_P_SOC_BGA1296
SPI_FLASH GND soic8-7_9-1_27 AKE5EG-0Q01 CONN SMD HOUSING 8P 2R FS(P1.27,H5.0)
R44
05
+1.8V_S5
11/02 modify
PCIE_WAKE3_N PCIE_WAKE2_N
P3 P2 P12 P10
1
BXT-P - eMMC / LPC / SD / XDP / I2C
When USB OTG feature is not required, USB2_OTG_ID needs to be connected to GND, and USB2_VBUS_SNS needs to be pull up to V1p8A with external 8-10kohm resistor PDG 0.9 10/27
4,6,8,10,13,14,15,21,23,25,29,31 +1.8V_S5 6,8,13,15,20,21,23,26,31 +3V_S5 13 VSTBY_FSPI 14,17,21,31,32 +1.8V 7,19,20,21,22,23,26,27,28,29,31,32,33 +3V
Freq.
Samsung
0000 AKD5JG0T504
K4B4G1646E-BYK0
1600
Hynix
0001 AKD5PGSTW13
H5TC4G63CFR-PBA
1600
Micro
0010 AKD59GSTL12 MT41K256M16TW-107 1600
A
change to 1K as CRB
Quanta Computer Inc. PROJECT : ZHP/ZSP
3
2
Size
Document Number
Date:
Tuesday, July 26, 2016
Rev 1A
Valley 4/9 (SD/PCIE/SATA)
1
Sheet
5
of
36
5
4
+3V_S5 +1.8V_S5
CORE_PWROK
R171
23 SLP_S4# 23 SLP_S3# 15 SLP_S0IX# SOC_REST_BTN# R490
R151
SOC_RSMRST#
*10K_4
R149
SUS_PWRDNACK
*10K_4
R161
PCH_SUS_STAT#
200/F_4
SOC_PWRBTN# SOC_PLTRST#
23
*20K_4
CORE_PWROK
SOC_RTEST# SOC_RSMRST# SOC_PROCHOT# SOC_PMC_WAKE PMU_WIFI_SUSCLK SLP_S4# SLP_S3# SLP_S0IX# SOC_REST_BTN# PMU_RCOMP SOC_PWRBTN# SOC_PLTRST# PMU_BATLOW# AC_PRESENT
AH49 AC57 E47 AG55 AE62 AK54 AC62 AD61 AD62 AG59 AK55 AG57 AH51 AK49
CORE_PWROK
AG49 J47 J45 M47 F48 H48 F47 H45 L47 P47
PMIC_THERMTRIR_N
*20K_4
R177
PMU_BATLOW#
1K/J_4
R153
SOC_PMC_WAKE
10K_4
R182
AC_PRESENT
*10K_4
R489
SLP_S0IX#
R488
SOC_REST_BTN#
10K_4
R160
SOC_PLTRST#
*10K_4
R185
AC_PRESENT
10K_4
TP63
15 GND 23 17,23
Modify 11/04
20K_4
GND
1K/J_4
10/28 Modify PMU Voltage to 3.3V
R158 *0/J_4
SOC_RSMRST#
14
H50 J50 M48 P48 L48 E52
DDI1_EDP_HPD_R
GPIO_34 GPIO_35 GPIO_36 R75
10 GPIO_34 10 GPIO_35 10 GPIO_36 TP_RST#_Q
5,23
B41 C41 F41 E41
*0_4
10/21 change TP_RST to GPIO follow CRB +3V_S5
Touch panel
R169 R172 R471
C
16
330K_4 INTRUDER#
T61 T62 R63
SMB_SOC_DATA SMB_SOC_CLK SMB_SOC_ALERTB
1K/J_4 1K/J_4 1K/J_4
R304
SMB1ALERT#
R139
+3V_RTC
B21 AC54
H43 AG52 J43 AG54
*short_4
SMB can set to 3.3V
U21F
BXT_P_SOC_BGA1296
RTC_TEST_N RSM_RST_N PROCHOT_N PMU_WAKE_N PMU_SUSCLK PMU_SLP_S4_N PMU_SLP_S3_N PMU_SLP_S0_N PMU_RSTBTN_N PMU_RCOMP PMU_PWRBTN_N PMU_PLTRST_N PMU_BATLOW_N PMU_AC_PRESENT
RTC_RST_N SUSPWRDNACK SUS_STAT_N AVS_I2S1_WS_SYNC AVS_I2S1_SDO AVS_I2S1_SDI AVS_I2S1_MCLK AVS_I2S1_BCLK
PMU Block
R159 *short_4
23
AVS_I2S2_SDO AVS_I2S2_SDI AVS_I2S2_MCLK AVS_I2S2_BCLK AVS_I2S2_WS_SYNC
SOC_PWROK
AVS_I2S3_WS_SYNC AVS_I2S3_SDO AVS_I2S3_SDI AVS_I2S3_BCLK
PMIC_THERMTRIP_N PMIC_STDBY PMIC_SDWN_B_GPIO_213 PMIC_RESET_N PMIC_PWRGOOD PMIC_I2C_SDA PMIC_I2C_SCL GPIO_214 GPIO_215
AVS_DMIC_DATA_2 AVS_DMIC_DATA_1 AVS_DMIC_CLK_B1 AVS_DMIC_CLK_AB2 AVS_DMIC_CLK_A1
PMC_SPI_TXD PMC_SPI_RXD PMC_SPI_FS2 PMC_SPI_FS1 PMC_SPI_FS0 PMC_SPI_CLK
VCC_RTC_EXTPAD RTC_X2 RTC_X1 JTAG_PREQ_N JTAG_PRDY_N JTAG_PMODE JTAG_TRST_N JTAG_TMS JTAG_TDO JTAG_TDI JTAG_TCK
PWM0 PWM1 PWM2 PWM3 JTAGX INTRUDER SMB_DATA SMB_CLK SMB_ALERT_N
GPIO_219 GPIO_218 GPIO_217 GPIO_216 PCIE_REF_CLK_RCOMP
RSVD_H43 RSVD_AG52 RSVD_J43 RSVD_AG54
SVID0_DATA SVID0_CLK SVID0_ALERT_N
AC55 AC63 AG58 J62 K62 K61 G62 H63 M58 K59 K58 H59 M57
SRT_CRST# R487 R144
SUS_PWRDNACK PCH_SUS_STAT# GPIO_78
GPIO_78
+1.8V_S5 PCH_SUSPWRDNACK
13
10 D
GPIO_88
GPIO_88
ACZ_RST#
R122
10
33_4
PCH_AZ_CODEC_RST#
Follow CRB the trace need >1000 mil33 ohm +-5%
M61 L63 L62 M62 M52 M54 P52 M55 P54
GPIO_92
GPIO_92
19
10
Apollo EDS pin腳有錯 need check
RTC Clock 32.768KHz
GPIO_82
GPIO_82
10 RTC_X2
AG51 AC58 AC59
BRTC_EXTPAD C109 RTC_X2 RTC_X1
C20 C21 B19 C24 C23 A22 C22 B23
XDP_H_PREQ# XDP_H_PRDY# XDP_H_TRST# XDP_H_TMS XDP_H_TDO XDP_H_TDI XDP_H_TCK
0.1U/16V_4
EMMC_RST
E21 PCIE_REF_CLK_RCOMP
R106
60.4/F_4
VR_SVID_DATA VR_SVID_CLK VR_SVID_ALERT# 220_4 R617
Section 6 of 12
15P/50V_4
R141 10M_4
Y2 32.768KHZ
Unstuff R740 10/17 WoM_WW31RTC_X1
15P/50V_4
C90
GND 2013/07/25 change package , P/N change from BG332768224 to BG332768453 Add 10P to GND for layout length too long 11/26
GND 17
GND GND
VR_SVID_DATA 29 VR_SVID_CLK 29 VR_SVID_ALERT# 29
GND Change from +1.0V to +1.05V
+1.05V
C321
*10p/50V_4
VR_SVID_DATA
R94
169/F_4
C322
*10p/50V_4
VR_SVID_ALERT#
R64
68/F_4
C323
*10p/50V_4
VR_SVID_CLK
R65
*86.6/F_4
C32 *0.1u/16V_4
C
GND
可能缺料
For Intel MoW04
SVID_CLK : UP:85 ohm SVID_ALERT : UP:68 ohm SVID_DATA : UP:170 ohm
+1.8V_S5 *10K_4
C76
GND +1.8V_S5
100/J_4 R414 100/J_4 R430 Add R1371 11/9 *51/F_4 R432 51/F_4 R433 100/J_4 R413 51/F_4 R434 51/F_4 R412
L30 M30 M29 P30
C18 C17 B17
*10K_4 *short_4
1
D
06
Modify 11/14
2
R435
+1.8V_S5
1
Pin AG55 is EMMC_PWR_EN_N (CRB 1.0)
12/23 follow Intel PDG 1.0 change R435 to 1K ohm. R418 *short_4
H_PROCHOT#
2
All PMU can set to 1.8/3.3V ZHP set to3.3V
+1.8V_S5 4,5,8,10,13,14,15,21,23,25,29,31 +3V_S5 8,13,15,20,21,23,26,31 +1.05V 8,27,29 +3V 4,5,11,13,14,16,17,19,20,21,22,23,26,27,28,29,31,32,33
13,25,29
3
Series:95 ohm Series:220 ohm Series:20 ohm
R574 PMIC_THERMTRIR_N
20 mils
RTC Circuitry(RTC)
+3V_RTC
20MIL SOC_RTEST#
20K/J_4 1
R368 +3V_RTC_0
A
B
4 5 R619
THERMTRIP# [13] *10K_4
3
Q51 MMBT3904-7-F_200MA AC_PRESENT
R375 *10K_4
+1.8V_S5
Modify it 10/28
R571 68.1K/F_4
1
R362
1K/J_4
20MIL
0_4 2
ACPRESENT
12/25
1
25
*2N7002K Q27
Q28 *2N7002K
2
*SHORT_ PAD1
VCCRTC_1 R367
20MIL
SRT_CRST#
20K/J_4
BAT54CW C287 1u/6.3V_4
C272 1u/6.3V_4
G1 *SHORT_ PAD1
B
20MIL Change G1、G2 footprint from "SOLDERJUMPER-2" to "RC0603-C" for SMT request
R569 150K/F_4
2
3
*G2129TL1U R620
VCCRTC_2
3
OE
R572
G2
CN13 RTC_SOCKET
1
GND
VCCRTC_3 4.7K/J_4
+3V_S5
6
B
2
R570
C273 1u/6.3V_4
30mils
2
3
VCCB
4.7K/J_4
D16
+3VPCU
1
PMIC_THERMTRIR_N
VCCA
20 mils
2
1
U33
20mils
+5V_S5
+3V_LDO_EC
2
+1.8V_S5
1
THERMALTRIP#
PE Request change to ML1220
GND R376
*short_4
+3V_RTC +3V_RTC
EC RSET RTC
R363 20K/J_4
+3V
12/17 Modify
SRT_CRST#
3 A
R176
4.7K_4
4.7K_4
13
CLR_CMOS
CLR_CMOS 2
3
4
SMB_RUN_DAT
SMB_RUN_DAT
2
C290 *1u/6.3V_4
15
C291 *1u/6.3V_4
11,16
A
GND GND
2 SMB_SOC_CLK
CLR_CMOS
SOC_RTEST#
Q30 2N7002K
1
5 SMB_SOC_DATA
R170
Q29 2N7002K
1
Q54
R364 20K/J_4 SOC_RTEST#
3
AC Present: This input pin indicates when the platform is plugged into AC power.
6
1
SMB_RUN_CLK
SMB_RUN_CLK
11,16
Quanta Computer Inc.
2N7002DW
PROJECT : ZHP/ZSP Size
Document Number
Rev 1A
Valley 6/9 (USB/LPC/I2C)
Tuesday, July 26, 2016 Date: 5
4
3
2
Sheet 1
6
of
36
5
4
R29 A12 A16 A20 A24 A28 A32 A36 A40 A44 A48 A5 A52 A56 A62 A9 AA1 AA2 AA27 AA34 AA41 AA63 AB10 AB12 AB16 AB48 AB5 AB52 AB57 AB59 AB9 AC18 AC27 AC34 AC39 AE1 AE10 AE11 AE13 AE14 AE16 AE17 AE2 AE23 AE27 AE34 AE39 AE4 AE41 AE47 AE48 AE5 AE50 AE51 AE53 AE54 AE56 AE57 AE59 AE63 AE7 AE8 AG13 AG18 AG23 AG27 AG34 AG37 AG39 AG41 AG42 AG44 AG46 AH15 AH16 AH48 AH5 AH52 AH54 AH55 AH57
D
C
B
A
U21J
3
AV19 AV2 AV21 AV23 AV29 AV3 AV32 AV35 AV41 AV43 AV45 AV55 AV61 AV62 AV9 AW14 AW30 AW34 AW50 AY10 AY32 AY54 AY58 AY6 B2 B3 B62 B63 B9 BA1 BA12 BA16 BA17 BA2 BA21 BA25 BA27 BA29 BA32 BA35 BA37 BA39 BA43 BA47 BA48 BA52 BA62 BA63 BB19 BB25 BB3 BB39 BB45 BB61 BC32 BD3 BD32 BD56 BD61 BD8 BE1 BE10 BE12 BE16 BE17 BE21 BE27 BE29 BE35 BE37 BE43 BE47 BE48 BE52 BE54 BE63 BF3 BF32 BF61 BG19 BG23
BXT_P_SOC_BGA1296 AH58 AH59 AH6 AH7 AJ1 AJ18 AJ2 AJ23 AJ27 AJ34 AJ36 AJ63 AK10 AK12 AK18 AK23 AK27 AK36 AK48 AK5 AK52 AK59 AK9 AM18 AM22 AM27 AM34 AM36 AM39 AM46 AN1 AN10 AN11 AN13 AN14 AN16 AN17 AN2 AN25 AN27 AN28 AN30 AN34 AN36 AN37 AN39 AN47 AN48 AN5 AN50 AN51 AN53 AN54 AN56 AN57 AN59 AN63 AN7 AN8 AP55 AP9 AR19 AR32 AR45 AT12 AT16 AT19 AT2 AT25 AT29 AT3 AT35 AT39 AT45 AT48 AT52 AT57 AT61 AT62 AT7 AU32
VSS_1 VSS_82 VSS_2 VSS_83 VSS_3 VSS_84 VSS_4 VSS_85 VSS_5 VSS_86 VSS_6 VSS_87 VSS_7 VSS_88 VSS_8 VSS_89 VSS_9 VSS_90 VSS_10 VSS_91 VSS_11 VSS_92 VSS_12 VSS_93 VSS_13 VSS_94 VSS_14 VSS_95 VSS_15 VSS_96 VSS_16 VSS_97 VSS_17 VSS_98 VSS_18 VSS_99 VSS_19 VSS_100 VSS_20 VSS_101 VSS_21 VSS_102 VSS_22 VSS_103 VSS_23 VSS_104 VSS_24 VSS_105 VSS_25 VSS_106 VSS_26 VSS_107 VSS_27 VSS_108 VSS_28 VSS_109 VSS_29 VSS_110 VSS_30 VSS_111 VSS_31 VSS_112 VSS_32 VSS_113 VSS_33 VSS_114 VSS_34 VSS_115 VSS_35 VSS_116 VSS_36 VSS_117 VSS_37 VSS_118 VSS_38 VSS_119 VSS_39 VSS_120 VSS_40 VSS_121 VSS_41 VSS_122 VSS_42 VSS_123 VSS_43 VSS_124 VSS_44 VSS_125 VSS_45 VSS_126 VSS_46 VSS_127 VSS_47 VSS_128 VSS_48 VSS_129 VSS_49 VSS_130 VSS_50 VSS_131 VSS_51 VSS_132 VSS_52 VSS_133 VSS_53 VSS_134 VSS_54 VSS_135 VSS_55 VSS_136 VSS_56 VSS_137 VSS_57 VSS_138 VSS_58 VSS_139 VSS_59 VSS_140 VSS_60 VSS_141 VSS_61 VSS_142 VSS_62 VSS_143 VSS_63 VSS_144 VSS_64 VSS_145 VSS_65 VSS_146 VSS_66 VSS_147 VSS_67 VSS_148 VSS_68 VSS_149 VSS_69 VSS_150 VSS_70 VSS_151 VSS_71 VSS_152 VSS_72 VSS_153 VSS_73 VSS_154 VSS_74 VSS_155 VSS_75 VSS_156 VSS_76 VSS_157 VSS_77 VSS_158 VSS_78 VSS_159 VSS_79 VSS_160 VSS_80 VSS_161 VSS_81 VSS_162 Section 10 of 12
U21K VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 Section
GND GND
2
BXT_P_SOC_BGA1296 BG29 VSS_244 BG32 VSS_245 BG35 VSS_246 BG41 VSS_247 BG45 VSS_248 BH1 VSS_249 BH2 VSS_250 BH21 VSS_251 BH25 VSS_252 BH39 VSS_253 BH43 VSS_254 BH62 VSS_255 BH63 VSS_256 BJ10 VSS_257 BJ14 VSS_258 BJ18 VSS_259 BJ28 VSS_260 BJ32 VSS_261 BJ36 VSS_262 BJ4 VSS_263 BJ46 VSS_264 BJ50 VSS_265 BJ54 VSS_266 BJ56 VSS_267 BJ60 VSS_268 BJ8 VSS_269 C12 VSS_270 C16 VSS_271 C28 VSS_272 C32 VSS_273 C40 VSS_274 C48 VSS_275 D32 VSS_276 D58 VSS_277 D6 VSS_278 E12 VSS_279 E14 VSS_280 E19 VSS_281 E27 VSS_282 E4 VSS_283 E54 VSS_284 F10 VSS_285 F21 VSS_286 F3 VSS_287 F32 VSS_288 F37 VSS_289 F43 VSS_290 F45 VSS_291 F50 VSS_292 F56 VSS_293 F59 VSS_294 F63 VSS_295 G1 VSS_296 G32 VSS_297 H17 VSS_298 H23 VSS_299 H29 VSS_300 H3 VSS_301 H37 VSS_302 H47 VSS_303 H61 VSS_304 H7 VSS_305 J12 VSS_306 J14 VSS_307 J19 VSS_308 J27 VSS_309 J30 VSS_310 J32 VSS_311 J35 VSS_312 J37 VSS_313 J48 VSS_314 J63 VSS_315 K32 VSS_316 K5 VSS_317 K54 VSS_318 K57 VSS_319 K6 VSS_320 L21 VSS_321 L27 VSS_322 L29 VSS_323 L35 VSS_324 11 of 12
U21L L43 L45 L50 M14 M21 M27 M3 M32 M50 M59 M9 N1 N32 N63 P13 P19 P35 P37 P41 P43 P45 P5 P55 P59 P9 R23 R32 T49 U1 U10 U11 U13 U14 U16 U17 U18
GND
07 D
C
GND
B
A
Quanta Computer Inc.
GND
PROJECT :ZHP/ZSP
GND
5
1
BXT_P_SOC_BGA1296 U2 VSS_325 VSS_361 U27 VSS_326 VSS_362 U34 VSS_327 VSS_363 U5 VSS_328 VSS_364 U50 VSS_329 VSS_365 U51 VSS_330 VSS_366 U53 VSS_331 VSS_367 U54 VSS_332 VSS_368 U56 VSS_333 VSS_369 U57 VSS_334 VSS_370 U59 VSS_335 VSS_371 U62 VSS_336 VSS_372 U63 VSS_337 VSS_373 U7 VSS_338 VSS_374 U8 VSS_339 VSS_375 V20 VSS_340 VSS_376 V27 VSS_341 VSS_377 V34 VSS_342 VSS_378 V42 VSS_343 VSS_379 Y12 VSS_344 VSS_380 Y16 VSS_345 VSS_381 Y22 VSS_346 VSS_382 Y27 VSS_347 VSS_383 Y34 VSS_348 VSS_384 Y42 VSS_349 VSS_385 Y46 VSS_350 VSS_386 Y48 VSS_351 VSS_387 Y5 VSS_352 VSS_388 Y52 VSS_353 VSS_389 Y54 VSS_354 VSS_390 Y55 VSS_355 VSS_391 Y57 VSS_356 VSS_392 Y59 VSS_357 VSS_393 Y6 VSS_358 VSS_394 Y7 VSS_359 VSS_395 VSS_360 Sect 12/12
4
3
2
Size
Document Number
Date:
Tuesday, July 26, 2016
Rev 1A
Valley 7/9 (Power 1) Sheet 1
7
of
36
5
4
3
2
Add it 10/17
C66 47u/6.3V_8
C68 47u/6.3V_8
C85 47u/6.3V_8
C87 47u/6.3V_8
C69 47u/6.3V_8
C84 47u/6.3V_8
C67 47u/6.3V_8
1uFx3
0402
BOT, inside socket cavity
22uFx4
0603
TOP, inside socket cavity
47uFx7
0805
TOP, inside socket cavity
U21H
AJ44 GND
+VNN
AJ37 AJ39 AJ41 AJ42 AJ46 AK37 AK39 AK41 AK42 AK44 AK46 AM44
D
C91 1u/6.3V_4
C92 1u/6.3V_4
C96 1u/6.3V_4
C357 22uF/6.3VT_6
GND
29
C62 22uF/6.3VT_6
C358 22uF/6.3VT_6
C113 22uF/6.3VT_6
*short_4 R126 Fixed Vnn Sense
VNN_SENSE
VNN_SVID_1 VNN_SVID_2 VNN_SVID_3 VNN_SVID_4 VNN_SVID_5 VNN_SVID_6 VNN_SVID_7 VNN_SVID_8 VNN_SVID_9 VNN_SVID_10 VNN_SVID_11 VNN_SVID_12
AG48
VNN_REFIN_R
60mil R208
RSVD_BG63
AC41 AA42 Y44 V44 V46 AJ25 AK25
VDD3_3P3_USB
*short_6
VCC_3P3V_A_1 VCC_3P3V_A_2 VCC_3P3V_A_3 VCC_3P3V_A_4 VCC_3P3V_A_5 VCC_3P3V_A_USB_1 VCC_3P3V_A_USB_2
AG20
VDD2_1P24_AUD_ISH_PLL
AJ20 AJ22
VDD2_1P24_MPHY
AE18 AE20 AE22 AG22
+VDD1_1P8 Output Decoupling Recommendations 1uFx4
0402
TOP*2 / BOT*2, inside socket cavity
22uFx1
0603
TOP, inside socket cavity
VCC_1P24V_1P35V_A_USB2 VCC_1P24V_1P35V_A_PLL_1 VCC_1P24V_1P35V_A_PLL_2 VCC_1P24V_1P35V_A_MPHY_1 VCC_1P24V_1P35V_A_MPHY_2 VCC_1P24V_1P35V_A_MPHY_3 VCC_1P24V_1P35V_A_MPHY_4
TBD
VCC_1P24V_1P35V_A_GLML2LDO_1 VCC_1P24V_1P35V_A_GLML2LDO_2 VCC_1P24V_1P35V_A_GLML2LDO_3 VCC_1P24V_1P35V_A_GLML2
AA18 AA20
VDD2_1P24_DSI_CSI +1.8V_S5
RSVD_AC20
AM20 AM28 AM37 AK20
VDD2_1P24_GLML
C
RSVD_AC22
AC20
40mil
VCC_1P24V_A_1 VCC_1P24V_A_2
AK22
VDD2_1P24_AUD_ISH_PLL
21A
0.15A
AC22
VDD2_1P24_USB2
4.8A
VNN_SENSE
BG63
+3V_S5
VCC_1P24V_1P35V_A_AUD_ISH
V48
RSVD_V48
Del it 10/17 *short_8
AA46 AC46 AE44 AE42 AC42 AC44 AE46 AG25
+VDD1_1P8
R174
C121 22uF/6.3VT_6
C97 1u/6.3V_4
C78 1u/6.3V_4
C86 1u/6.3V_4
C77 1u/6.3V_4
CAPS PLACE NEAR SOC PIN
GND
R206
*short_6
GND
C130
*22uF/6.3VT_6
VCCRAM_1P05_IO_3PHASEIO
B
TOP*2 / BOT*2, inside socket cavity
22uFx1
0603
TOP, inside socket cavity
RSVD_D1
AA22 AC23 V18 Y18 Y20
VDD3_3P3_USB Output Decoupling Recommendations 0402
VCCRTC_3P3V
D1
100mil
VCC_1P05V_IO_1 VCC_1P05V_IO_2 VCC_1P05V_IO_3 VCC_1P05V_IO_4 VCC_1P05V_IO_5
AA23
VCC_1P05V_3PHASEIO
P16 T15 T13
VCCRAM_1P05_FUSE VCCRAM_1P05_FHV1 VCCRAM_1P05_FHV0
0.4A
VCC_VCGI_1 VCC_VCGI_2 VCC_VCGI_3 VCC_VCGI_4 VCC_VCGI_5 VCC_VCGI_6 VCC_VCGI_7 VCC_VCGI_8 VCC_VCGI_9 VCC_VCGI_10 VCC_VCGI_11 VCC_VCGI_12 VCC_VCGI_13 VCC_VCGI_14 VCC_VCGI_15 VCC_VCGI_16 VCC_VCGI_17 VCC_VCGI_18 VCC_VCGI_19 VCC_VCGI_20 VCC_VCGI_21 VCC_VCGI_22 VCC_VCGI_23 VCC_VCGI_24 VCC_VCGI_25 VCC_VCGI_26 VCC_VCGI_27 VCC_VCGI_28 VCC_VCGI_29 VCC_VCGI_30 VCC_VCGI_31 VCC_VCGI_32 VCC_VCGI_33 VCC_VCGI_34 VCC_VCGI_35 VCC_VCGI_36 VCC_VCGI_37 VCC_VCGI_38 VCC_VCGI_39 VCC_VCGI_40 VCC_VCGI_41 VCC_VCGI_42 VCC_VCGI_43 VCC_VCGI_44 VCC_VCGI_45 VCC_VCGI_46 VCC_VCGI_47 VCC_VCGI_48 VCC_VCGI_49 VCC_VCGI_50 VCC_VCGI_51 VCC_VCGI_52 VCC_VCGI_53 VCC_VCGI_54 VCC_VCGI_55 VCC_VCGI_56 VCC_VCGI_57 VCC_VCGI_58 VCC_VCGI_59 VCC_VCGI_60 VCC_VCGI_61 VCC_VCGI_62 VCC_VCGI_63 VCC_VCGI_64
AA36 AA37 AA39 AC36 AC37 AE36 AE37 AG36 E43 E45 E48 E50 R45 R47 U36 U37 U39 U41 U42 U44 U46 U47 U48 V36 V37 V39 V41 Y36 Y37 Y39 Y41 AA28 AA30 AA32 AC28 AC30 AC32 AE28 AE30 AE32 AG28 AG30 AG32 AJ28 AJ30 AJ32 AK28 AK30 AK32 AK34 AM30 E29 E35 E37 F29 U28 U30 U32 V28 V30 V32 Y28 Y30 Y32
2.7A
VCC_1P05V_1 VCC_1P05V_2 VCC_1P05V_3 VCC_1P05V_4 VCC_1P05V_5 VCC_1P05V_6 VCC_1P05V_7 VCC_1P05V_8 VCC_1P05V_9 VCC_1P05V_10 VCC_1P05V_11 VCC_1P05V_12
1uFx12
0402
22uFx8
0603
TOP, inside socket cavity
47uFx3
0805
TOP, inside socket cavity
330uFx1
7343
TOP, inside socket cavity
08
BOT, inside socket cavity
+VCC_VCCGI
+VCC_VCCGI C44 22uF/6.3VT_6
C43 22uF/6.3VT_6
C40 22uF/6.3VT_6
C39 22uF/6.3VT_6
C52 22uF/6.3VT_6
C49 22uF/6.3VT_6
C56 22uF/6.3VT_6
C54 22uF/6.3VT_6 D
GND Add it 10/17
+VCC_VCCGI + C29 47u/6.3V_8
C34 47u/6.3V_8
C35 47u/6.3V_8
C316 330u/2V_7343
GND
+VCC_VCCGI +VCC_VCCGI C59 1u/6.3V_4
C70 1u/6.3V_4
C60 1u/6.3V_4
C72 1u/6.3V_4
C57 1u/6.3V_4
C73 1u/6.3V_4
C42 1u/6.3V_4
C36 1u/6.3V_4
C45 1u/6.3V_4
C63 1u/6.3V_4
C37 1u/6.3V_4
C51 1u/6.3V_4
GND +1.05V R105
*short_6
VCCRAM_1P05_IO_3PHASEIO
R117
*short_6
VCCRAM_1P05_FUSE
R118
*short_6
VCCRAM_1P05_FHV1
R119
*short_6
VCCRAM_1P05_FHV0
C
+VCCRAM_1P05 Output Decoupling Recommendations 1uFx4
0402
TOP*2 / BOT*2, inside socket cavity
22uFx2
0603
TOP, inside socket cavity
100mil +1.05V
100mil
RSVD_BJ3 RSVD_BJ61
AA44
VRTC_3P3
+3V_RTC
1uFx3
VCC_1P8V_A_1 VCC_1P8V_A_2 VCC_1P8V_A_3 VCC_1P8V_A_4 VCC_1P8V_A_5 VCC_1P8V_A_6 VCC_1P8V_A_7 VCC_1P8V_A_8
BJ3 BJ61
+VNN 9,29,30 +3V_S5 6,13,15,20,21,23,26,31 +1.05V 6,27,29 +1.24V_S5 31 +VCC_VCCGI 29,30 +3V_RTC 6,13
BXT_P_SOC_BGA1296
RSVD_AJ44
1
+VCC_VCCGI Output Decoupling Recommendations
+VNN Output Decoupling Recommendations
AA25 AC25 AE25 U22 U23 V22 V23 V25 Y23 Y25 U25 U20
+VCCRAM_1P05
C50 22U/6.3V_6
C48 22U/6.3VS_6
*short_6
C81 1u/6.3V_4
C61 1u/6.3V_4
C58 1u/6.3V_4
R116
C55 1u/6.3V_4
GND
VCC_1P05V_FUSE VCC_1P05V_FHV1 VCC_1P05V_FHV0
B
60mil +1.24V_S5 Section 8 of 12
Add it 10/27
40mil
VDD3_3P3_USB
Add it 10/27
VDD2_1P24_GLML C71 1u/6.3V_4
C65 1u/6.3V_4
C74 1u/6.3V_4
C100 1u/6.3V_4
GND
C107 1u/6.3V_4
40mil
40mil
VDD2_1P24_GLML Output Decoupling Recommendations
C132 22uF/6.3VT_6
C111 1u/6.3V_4
C108 1u/6.3V_4
C110 1u/6.3V_4
C363 22uF/6.3VT_6
0402
TOP*1 / BOT*3, inside socket cavity
22uFx1
0603
TOP, inside socket cavity
VDD2_1P24_DSI_CSI
VDD2_1P24_DSI_CSI Output Decoupling Recommendations C369 1u/6.3V_4
C364 1u/6.3V_4
R478
*short_6
VDD2_1P24_USB2
R485
*short_8
VDD2_1P24_AUD_ISH_PLL
R474
*short_6
VDD2_1P24_MPHY
R481
*short_6
VDD2_1P24_GLML
R472
*0/J_6
VDD2_1P24_DSI_CSI
GND
VDD2_1P24_AUD_ISH_PLL
40mil
1uFx3
C352 *1u/6.3V_4
C365 22uF/6.3VT_6
C347 *1u/6.3V_4
C351 *22uF/6.3VT_6
C47 1u/6.3V_4
C38 1u/6.3V_4
1uFx2
0402
TOP*1 / BOT*1, inside socket cavity
22uFx1
0603
TOP, inside socket cavity
C88 1u/6.3V_4
GND
GND GND
VCCRAM_1P05_IO_3PHASEIO
VDD2_1P24_MPHY C356 1u/6.3V_4
C361 1u/6.3V_4
C82 1u/6.3V_4
C64 1u/6.3V_4
C360 22uF/6.3VT_6
A
C75 *1u/6.3V_4
C46 22uF/6.3VT_6
A
GND
GND
VDD2_1P24_AUD_ISH_PLL Output Decoupling Recommendations 1uFx2
0402
TOP*1 / BOT*1, inside socket cavity
22uFx1
0603
TOP, inside socket cavity
VCCRAM_1P05_IO_3PHASEIO Output Decoupling Recommendations 1uFx4
0402
TOP*2 / BOT*2, inside socket cavity
22uFx1
0603
TOP, inside socket cavity
Quanta Computer Inc.
VDD2_1P24_MPHY Output Decoupling Recommendations 1uFx3
0402
TOP*1 / BOT*2, inside socket cavity
22uFx1
0603
TOP, inside socket cavity 5
PROJECT : ZHP/ZSP 4
3
2
Size
Document Number
Date:
Tuesday, July 26, 2016
Rev 1A
Valley 8/9 (Power 2) Sheet 1
8
of
36
5
4
3
2
1
09
+1.05V 6,8,27,29 +1.35VSUS 2,3,11,12,28 +VNN 8,29,30
+VCCDDQ Output Decoupling Recommendations +1.35VSUS
+VCCDDQ
1uFx2
0402
BOT, inside socket cavity
22uFx8
0603
TOP, inside socket cavity
U21I
D
R257
*SHORT_1206
R256
*SHORT_1206
R480
*short_8
AN18 AN20 AN22 AN23 AN41 AN42 AN44 AN46 AR17 AR47 AT13 AT17 AT47 AT51 AV14 AV50
+VCCDDQ
C158 22U/6.3_8
C164 22U/6.3_8
C165 22U/6.3_8
C118 22U/6.3_8
C163 22U/6.3_8
C157 22U/6.3_8
C166 22U/6.3_8
C112 22U/6.3_8
Add R1351 10/29 GND
Add it 10/17 C145 1u/6.3V_4
C144 1u/6.3V_4
AM32
BXT_P_SOC_BGA1296
BJ62
RSVD_BJ62 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16
VCC_VCGI_SENSE_P VCC_VCGI_SENSE_N
D
R41
VCC1_SENSEP_R
R125
*short_4
R43
VCC1_SENSEN_R
R123
*short_4
2.8A
29
VCCGISS_SENSE
29
+VNN AM23 AM25 AM41 AM42
VCCIOA_1 VCCIOA_2 VCCIOA_3 VCCIOA_4
RSVD_AM32
VCCGI_SENSE
Section 9 of 12
VCCIOA
R157
*short_8
AN32
RSVD_AN32
C117 1u/6.3V_4
C114 1u/6.3V_4
C115 22uF/6.3VT_6
C116 22uF/6.3VT_6
GND C
C
GND
VCCIOA Output Decoupling Recommendations
B13 C13 L16 M16 E23 F23 R25 AB49 AC13 AB13 AM59 AM58
B
T51 L14 R19 E6 R17 E3 D4 A60 A61 BJ2 BG1 P27 A3 M10 B15
U21G
BXT_P_SOC_BGA1296
NCTF_B13 NCTF_C13 NCTF_L16 NCTF_M16 NCTF_E23 NCTF_F23 NCTF_R25 NCTF_AB49 NCTF_AC13 NCTF_AB13 NCTF_AM59 NCTF_AM58 NCTF_T51 NCTF_L14 NCTF_R19 NCTF_E6 NCTF_R17 NCTF_E3 NCTF_D4 NCTF_A60 NCTF_A61 NCTF_BJ2 NCTF_BG1 NCTF_P27 NCTF_A3 NCTF_M10 NCTF_B15 Section 7 of 12
NCTF_M12 NCTF_C15 NCTF_F16 NCTF_J16 NCTF_D8 NCTF_E8 NCTF_H16 NCTF_C9 NCTF_F8 NCTF_E10 NCTF_E16 NCTF_F14 NCTF_F12 NCTF_H10 NCTF_H14 NCTF_H12 NCTF_A14 NCTF_C14 NCTF_M39 NCTF_P39 NCTF_R39 NCTF_R37 NCTF_C2 NCTF_J29 NCTF_P25 NCTF_R30 NCTF_C63 NCTF_E63 NCTF_D2 NCTF_AP57
1uFx2
0402
TOP, inside socket cavity
22uFx2
0603
TOP, inside socket cavity
M12 C15 F16 J16 D8 E8 H16 C9 F8 E10 E16 F14 F12 H10 H14 H12 A14 C14 M39 P39 R39 R37 C2 J29 P25 R30 C63 E63 D2 AP57
B
A
A
Quanta Computer Inc. PROJECT :ZHP/ZSP 5
4
3
2
Size
Document Number
Date:
Tuesday, July 26, 2016
Rev 1A
Valley 9/9 (GND) Sheet 1
9
of
36
5
4
+1.8V_S5
3
2
1
10
4,5,6,8,13,14,15,21,23,25,29,31
+1.8V_S5
Hardware Strap
R84 *4.7K/F_4
D
R415 *4.7K/F_4
R410 *4.7K/F_4
R408 4.7K/F_4
R90 *4.7K/F_4
R114 *10K_4
R470 *10K_4
R113 *4.7K/F_4
R69 *4.7K/F_4
R461 *10K_4
C
R95 10K_4
R441 10K_4
R423 10K_4
R424 *10K_4
R99 10K_4
R115 4.7K/F_4
R469 4.7K/F_4
R121 10K_4
R82 4.7K/F_4
R456 4.7K/F_4
R66 *4.7K/F_4
GPIO_36
GPIO_36
6
GPIO_39
GPIO_39
5
GPIO_43
GPIO_43
5
GPIO_44
GPIO_44
5
GPIO_47
GPIO_47
5
GPIO_78
GPIO_78
6
GPIO_88
GPIO_88
6
GPIO_92
GPIO_92
6
GPIO_110
GPIO_110
5
GPIO_111
GPIO_111
5
GPIO_120
GPIO_120
5
R67 10K_4
Strap Description
GPIO_36
VCC_1P24V_1P35V_A voltage select 0 = 1.24V 1 = 1.35V
GPIO_39
Enable CSE(TXE3.0) ROM Bypass 0 = Disable bypass 1 = Enable Bypass
GPIO_43
Allow eMMC as a boot source 0 = Disable 1 = Enable
GPIO_44
Allow SPI as a boot source 0 = Disable 1 = Enable
GPIO_47
Force DNX FW Load 0 = Do not force 1 = Force
GPIO_78
SMBus 1.8V/3.3V mode select 0=buffers set to 3.3V 1=buffers set to 1.8V
GPIO_88
PMU 1.8V/3.3V mode select 0=buffers set to 3.3V mode 1=buffers set to 1.8V mode
GPIO_92
SMBus No Re-Boot 0 = Disable (default) 1 = Enable
GPIO_110
LPC 1.8V/3.3V mode select 0=buffers set to 3.3V mode 1=buffers set to 1.8V mode
GPIO_111
Boot BIOS Strap 0 = Boot from SPI 1 = Do not boot from SPI
GPIO_120
Top swap override 0 = Disable 1 = Enable
GND
Note: This strap will only be used for B-step. For A-step this rails should only be set at 1.24V D
B Stage change to 3.3V
C
+1.8V_S5
GPIO_106
GPIO_106
R438
4.7K/F_4
5
GPIO_123
GPIO_123
R455
10K_4
6
GPIO_34
GPIO_34
R442
10K_4
6
GPIO_35
GPIO_35
R421
10K_4
5
GPIO_40
GPIO_40
R440
4.7K/F_4
5
GPIO_48
GPIO_48
R112
10K_4
6
GPIO_82
GPIO_82
R124
10K_4
5
GPIO_104
GPIO_104
R111
10K_4
5
GPIO_105
GPIO_105
R108
10K_4
5
GPIO_117
GPIO_117
R466
10K_4
5
GPIO_112
GPIO_112
R120
4.7K/F_4
5
GPIO_113
GPIO_113
R110
4.7K/F_4
5
GPIO_121
GPIO_121
R439
10K_4
5 B
A
Hardware Strap to enable boot from SPI If the platform design wants to have BIOS Boot form SPI then please ensure you have the following setting for hardware strap: GPIO_43 = 0 [Disable eMMC boot] GPIO_44 = 1 [Enable SPI Boot] MoW_WW36
B
Please ensure that this strap is pulled LOW when RSM_RST_N de-asserts for normal platform operation. GPIO_40/GPIO_48/GPIO_104/GPIO_105/GPIO_112/GPIO_113/GPIO_117/GPIO_121 PD GPIO_106/GPIO_123 PU A
Quanta Computer Inc. GND
PROJECT : ZHP/ZSP Size
Document Number
Rev 1A
Hardware Strap Date: 5
4
3
2
Tuesday, July 26, 2016
Sheet 1
10
of
36
M_A_A[15:0]
D
R300 R301
10K/F_4 10K/F_4 6,16 6,16
VDDSPD 3.0V~3.6V
2 2 2 2 2 2 2 2 2 2 2 2 2 2
M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CS#0 M_A_CS#1 M_A_CLK0 M_A_CLK0# M_A_CLK1 M_A_CLK1# M_A_CKE0 M_A_CKE1 M_A_CAS# M_A_RAS# M_A_WE#
DIMM0_SA0 DIMM0_SA1
SMB_RUN_CLK SMB_RUN_DAT 2 2
116 120
M_A_ODT0 M_A_ODT1
11 28 46 63 136 153 170 187
Channel A default SA [1:0] :00
2
M_A_DQS[7:0]
2
M_A_DQS#[7:0]
109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200
M_A_DQS1 M_A_DQS0 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS7 M_A_DQS6 M_A_DQS#1 M_A_DQS#0 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#7 M_A_DQS#6
12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186
3
M_A_DQ[63:0]
JDIM1A
5 DQ0 7 DQ1 15 DQ2 17 DQ3 4 DQ4 6 DQ5 16 DQ6 18 DQ7 21 DQ8 23 DQ9 33 DQ10 35 DQ11 22 DQ12 24 DQ13 34 DQ14 36 DQ15 39 DQ16 41 BA0 DQ17 51 BA1 DQ18 53 BA2 DQ19 40 S0# DQ20 42 S1# DQ21 50 CK0 DQ22 52 CK0# DQ23 57 CK1 DQ24 59 CK1# DQ25 67 CKE0 DQ26 69 CKE1 DQ27 56 CAS# DQ28 58 RAS# DQ29 68 WE# DQ30 70 SA0 DQ31 129 SA1 DQ32 131 SCL DQ33 141 SDA DQ34 143 DQ35 130 ODT0 DQ36 132 ODT1 DQ37 140 DQ38 142 DM0 DQ39 147 DM1 DQ40 149 DM2 DQ41 157 DM3 DQ42 159 DM4 DQ43 146 DM5 DQ44 148 DM6 DQ45 158 DM7 DQ46 160 DQ47 163 DQS0 DQ48 165 DQS1 DQ49 175 DQS2 DQ50 177 DQS3 DQ51 164 DQS4 DQ52 166 DQS5 DQ53 174 DQS6 DQ54 176 DQS7 DQ55 181 DQS#0 DQ56 183 DQS#1 DQ57 191 DQS#2 DQ58 193 DQS#3 DQ59 180 DQS#4 DQ60 182 DQS#5 DQ61 192 DQS#6 DQ62 194 DQS#7 DQ63 EZIW DDR3-DIMM0_H=5.2_RVS ddr-600025fb204g103zl-rvs-smt DGMK4000108 IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15
M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ8 M_A_DQ11 M_A_DQ12 M_A_DQ10 M_A_DQ9 M_A_DQ6 M_A_DQ5 M_A_DQ2 M_A_DQ3 M_A_DQ1 M_A_DQ0 M_A_DQ4 M_A_DQ7 M_A_DQ21 M_A_DQ20 M_A_DQ23 M_A_DQ22 M_A_DQ17 M_A_DQ16 M_A_DQ18 M_A_DQ19 M_A_DQ25 M_A_DQ26 M_A_DQ28 M_A_DQ27 M_A_DQ31 M_A_DQ24 M_A_DQ30 M_A_DQ29 M_A_DQ35 M_A_DQ37 M_A_DQ34 M_A_DQ39 M_A_DQ38 M_A_DQ32 M_A_DQ36 M_A_DQ33 M_A_DQ40 M_A_DQ44 M_A_DQ42 M_A_DQ43 M_A_DQ46 M_A_DQ45 M_A_DQ47 M_A_DQ41 M_A_DQ62 M_A_DQ61 M_A_DQ63 M_A_DQ57 M_A_DQ56 M_A_DQ60 M_A_DQ59 M_A_DQ58 M_A_DQ53 M_A_DQ54 M_A_DQ50 M_A_DQ49 M_A_DQ51 M_A_DQ52 M_A_DQ48 M_A_DQ55
2
+1.35VSUS
2.48A
75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124
+1.35VSUS 2,3,9,12,28 +VDDQ_VTT 12,28 +3V 4,5,6,13,14,16,17,19,20,21,22,23,26,27,28,29,31,32,33
199
+3V
+3V 2
R317
TP44
M_A_DRAMRST#_R
+SMDDR_VREF_DQ0 +SMDDR_VREF_DIMM0
Swap DQ & DQS 10/27
1
77 122 125
10K/F_4
198 30
PM_EXTTS#0 C240
*0.1U/16V_4
1 126 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43
10/16 change to footprint
JDIM1B VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDDSPD NC1 NC2 NCTEST EVENT# RESET#
VREF_DQ VREF_CA VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15
VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52
11
44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196
D
C
VTT1 VTT2 GND GND
203 204
+VDDQ_VTT
205 206
Modify 10/29
DDR3-DIMM0_H=5.2_RVS ddr-600025fb204g103zl-rvs-smt DGMK4000108 IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS)
Other one: DGMK4000109
Other one: DGMK4000109
B
EC4
*120P/50V_4
EC6
*120P/50V_4
EC3
*120P/50V_4
EC5
*120P/50V_4
+
C426 *330u/2V_7343
Near SO-DIMM
+VDDQ_VTT
+1.35VSUS
+VDDQ_VTT 0.1U/16V_4
C228
1u/6.3V_4
C215
0.1U/16V_4
C235
1u/6.3V_4
C213
0.1u/16V_4
C219
1u/6.3V_4
C248
0.1U/16V_4
C223
1u/6.3V_4
C251
0.1U/16V_4
C238
10U/6.3V_6
C211
0.1U/16V_4
C249
0.1U/16V_4
C209
0.1U/16V_4
C250
10U/6.3V_6
C212
10U/6.3V_6
EC1
*120P/50V_4
C210
10U/6.3V_6
EC2
*120P/50V_4
C216
10U/6.3V_6
C208
10U/6.3V_6
C214
10U/6.3V_6
C246 C245
VREF DQ0 M1 Solution
Modify 10/29
C247
R296 3.65K/F_4
10 mils +VDDQ
4
R298
R295 3.65K/F_4
+SMDDR_VREF_DIMM0 0.1U/16V_4
C226
*2.2U/6.3V_6
+VDDQ R297
*0_6
10 mils +SMDDR_VREF_DQ0 0.1U/16V_4
C205
*2.2U/6.3V_6
10U/6.3V_6
C222
0.1U/16V_4
10U/6.3V_6
C225
0.1U/16V_4
+3V
3
*2/F_6
M_A_VREF_DQ
2
C180 *0.022U/25V_4
*24.9/F_4
change to 3.65K Voltage Divider circuit 11/5 Need to check stuff the BOM 10/17 10 mils
+SMDDR_VREF_DIMM0
R279
*2/F_6
R286 3.65K/F_4
C218
R280
R289 3.65K/F_4 R288
10 mils C232
+SMDDR_VREF_DQ0
*0_6
+1.35VSUS
R287
M_A_VREF_CA
2
C179 *0.022U/25V_4
A
*24.9/F_4
Quanta Computer Inc.
Correct CHA VREF_DQ/CA net name 10/29
Follow CHK list 5
10 mils
+VDDQ
1
+1.35VSUS +1.35VSUS
2
For EMI RESERVE +1.35VSUS
+1.35VSUS
Place these Caps near So-Dimm0. 0.1uF/10uF 4pcs on each side of connector
1
B
A
2
2
C
98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
PC2100 DDR3 SDRAM SO-DIMM (204P)
2
4
PC2100 DDR3 SDRAM SO-DIMM (204P)
5
2
PROJECT : ZHP/ZSP
Size
Document Number
Date:
Tuesday, July 26, 2016
Rev 1A
DDR3 DIMM0-STD(5.2H) Sheet 1
11
of
36
5
4
3
+V_SMDDR_VREF_DIMM +V_SMDDR_VREF_DQ1 +V_SMDDR_VREF_DIMM +V_SMDDR_VREF_DQ1 3
D
M_B_A[15:0]
M_B_BS[2:0]
3 3 3
M_B_CLKP0 M_B_CLKN0 M_B_CKE0
3 3 3 3 3
M_B_ODT0 M_B_CS#0 M_B_RAS# M_B_CAS# M_B_WE#
3 3
M_B_DQSP3 M_B_DQSP2
3 3
C
3
M_B_DQSN3 M_B_DQSN2
M8 H1
M_B_BS0 M_B_BS1 M_B_BS2
M2 N8 M3
M_B_CLKP0 M_B_CLKN0 M_B_CKE0
J7 K7 K9
M_B_ODT0 M_B_CS#0 M_B_RAS# M_B_CAS# M_B_WE#
K1 L2 J3 K3 L3
M_B_DQSP3 M_B_DQSP2
F3 C7
M_B_DM2 M_B_DM3
E7 D3
M_B_DQSN3 M_B_DQSN2
G3 B7
M_B_DRAMRST#_R
M_B_DRAMRST#_R
BYTE2_16-23 BYTE3_24-31
U9
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
Swap DQ&DQS 10/27
3
2
1
DDR3L MEMORY CHANNEL B
On board memory(OBM)
M_B_ZQ1
T2 L8
VREFCA VREFDQ
J1 L1 J9 L9
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9
CK CK CKE ODT CS RAS CAS WE DQSL DQSU
VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9
DML DMU
VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9
DQSL DQSU
RESET ZQ
NC#J1 NC#L1 NC#J9 NC#L9
E3 F7 F2 F8 H3 H8 G2 H7
M_B_DQ31 M_B_DQ27 M_B_DQ24 M_B_DQ29 M_B_DQ28 M_B_DQ26 M_B_DQ25 M_B_DQ30
D7 C3 C8 C2 A7 A2 B8 A3
M_B_DQ19 M_B_DQ20 M_B_DQ18 M_B_DQ21 M_B_DQ23 M_B_DQ17 M_B_DQ16 M_B_DQ22
M_B_DQ31 M_B_DQ27 M_B_DQ24 M_B_DQ29 M_B_DQ28 M_B_DQ26 M_B_DQ25 M_B_DQ30 M_B_DQ19 M_B_DQ20 M_B_DQ18 M_B_DQ21 M_B_DQ23 M_B_DQ17 M_B_DQ16 M_B_DQ22
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+1.35VSUS
BA0 BA1 BA2
R243 CHB@240/F_4
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15
VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9
+V_SMDDR_VREF_DIMM M8 +V_SMDDR_VREF_DQ1 H1
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
B2 D9 G7 K2 K8 N1 N9 R1 R9
M_B_BS0 M_B_BS1 M_B_BS2
M2 N8 M3
M_B_CLKP0 M_B_CLKN0 M_B_CKE0
J7 K7 K9
A1 A8 C1 C9 D2 E9 F1 H2 H9
M_B_ODT0 M_B_CS#0 M_B_RAS# M_B_CAS# M_B_WE#
K1 L2 J3 K3 L3
M_B_DQSP1 M_B_DQSP0
F3 C7
M_B_DM1 M_B_DM0
E7 D3
M_B_DQSN1 M_B_DQSN0
G3 B7
3 3
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
M_B_DQSP1 M_B_DQSP0
3 3
BYTE0_8-15 BYTE1_0-7
U30
M_B_DQSN1 M_B_DQSN0
M_B_DRAMRST#_R T2 M_B_ZQ2
B1 B9 D1 D8 E2 E8 F9 G1 G9
L8
VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
100-BALL SDRAM DDR3 CHB@RAM _DDR3L
J1 L1 J9 L9
E3 F7 F2 F8 H3 H8 G2 H7
M_B_DQ15 M_B_DQ9 M_B_DQ14 M_B_DQ11 M_B_DQ13 M_B_DQ8 M_B_DQ12 M_B_DQ10
M_B_DQ15 M_B_DQ9 M_B_DQ14 M_B_DQ11 M_B_DQ13 M_B_DQ8 M_B_DQ12 M_B_DQ10
D7 C3 C8 C2 A7 A2 B8 A3
M_B_DQ7 M_B_DQ5 M_B_DQ2 M_B_DQ4 M_B_DQ1 M_B_DQ0 M_B_DQ3 M_B_DQ6
M_B_DQ7 M_B_DQ5 M_B_DQ2 M_B_DQ4 M_B_DQ1 M_B_DQ0 M_B_DQ3 M_B_DQ6
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+1.35VSUS
BA0 BA1 BA2
VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9
CK CK CKE ODT CS RAS CAS WE
VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9
DQSL DQSU DML DMU
VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9
DQSL DQSU
RESET ZQ
VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9
R563 CHB@240/F_4
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
NC#J1 NC#L1 NC#J9 NC#L9
+V_SMDDR_VREF_DIMM +V_SMDDR_VREF_DQ1
M8 H1
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7
B2 D9 G7 K2 K8 N1 N9 R1 R9
M_B_BS0 M_B_BS1 M_B_BS2
M2 N8 M3
M_B_CLKP0 M_B_CLKN0 M_B_CKE0
J7 K7 K9
A1 A8 C1 C9 D2 E9 F1 H2 H9
M_B_ODT0 M_B_CS#0 M_B_RAS# M_B_CAS# M_B_WE#
K1 L2 J3 K3 L3
M_B_DQSP4 M_B_DQSP6
F3 C7
M_B_DM6 M_B_DM4
E7 D3
M_B_DQSN4 M_B_DQSN6
G3 B7
3 3
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
BYTE6_48-55 BYTE4_32-39
U5
3 3
M_B_DQSP4 M_B_DQSP6
M_B_DQSN4 M_B_DQSN6
VREFCA VREFDQ
B1 B9 D1 D8 E2 E8 F9 G1 G9
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9
CK CK CKE ODT CS RAS CAS WE
VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9
DQSL DQSU DML DMU
VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9
DQSL DQSU
RESET
L8
ZQ
VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9
R148 CHB@240/F_4
100-BALL SDRAM DDR3 CHB@RAM _DDR3L
J1 L1 J9 L9
E3 F7 F2 F8 H3 H8 G2 H7
M_B_DQ33 M_B_DQ37 M_B_DQ32 M_B_DQ38 M_B_DQ39 M_B_DQ36 M_B_DQ34 M_B_DQ35
M_B_DQ33 M_B_DQ37 M_B_DQ32 M_B_DQ38 M_B_DQ39 M_B_DQ36 M_B_DQ34 M_B_DQ35
3 3 3 3 3 3 3 3
D7 C3 C8 C2 A7 A2 B8 A3
M_B_DQ48 M_B_DQ50 M_B_DQ49 M_B_DQ52 M_B_DQ51 M_B_DQ53 M_B_DQ55 M_B_DQ54
M_B_DQ48 M_B_DQ50 M_B_DQ49 M_B_DQ52 M_B_DQ51 M_B_DQ53 M_B_DQ55 M_B_DQ54
3 3 3 3 3 3 3 3
+1.35VSUS
BA0 BA1 BA2
M_B_DRAMRST#_R T2 M_B_ZQ3
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15
NC#J1 NC#L1 NC#J9 NC#L9
+V_SMDDR_VREF_DIMM +V_SMDDR_VREF_DQ1
M8 H1
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7
B2 D9 G7 K2 K8 N1 N9 R1 R9
M_B_BS0 M_B_BS1 M_B_BS2
M2 N8 M3
M_B_CLKP0 M_B_CLKN0 M_B_CKE0
J7 K7 K9
A1 A8 C1 C9 D2 E9 F1 H2 H9
M_B_ODT0 M_B_CS#0 M_B_RAS# M_B_CAS# M_B_WE#
K1 L2 J3 K3 L3
M_B_DQSP5 M_B_DQSP7
F3 C7
M_B_DM5 M_B_DM7
E7 D3
M_B_DQSN5 M_B_DQSN7
G3 B7
3 3
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
3 3
M_B_DQSP5 M_B_DQSP7
M_B_DQSN5 M_B_DQSN7
M_B_DRAMRST#_R T2
L8
M_B_ZQ4
B1 B9 D1 D8 E2 E8 F9 G1 G9
VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15
J1 L1 J9 L9
100-BALL SDRAM DDR3 CHB@RAM _DDR3L
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
E3 F7 F2 F8 H3 H8 G2 H7
M_B_DQ46 M_B_DQ43 M_B_DQ44 M_B_DQ41 M_B_DQ45 M_B_DQ47 M_B_DQ40 M_B_DQ42
M_B_DQ46 M_B_DQ43 M_B_DQ44 M_B_DQ41 M_B_DQ45 M_B_DQ47 M_B_DQ40 M_B_DQ42
3 3 3 3 3 3 3 3
D7 C3 C8 C2 A7 A2 B8 A3
M_B_DQ59 M_B_DQ62 M_B_DQ63 M_B_DQ60 M_B_DQ57 M_B_DQ61 M_B_DQ58 M_B_DQ56
M_B_DQ59 M_B_DQ62 M_B_DQ63 M_B_DQ60 M_B_DQ57 M_B_DQ61 M_B_DQ58 M_B_DQ56
3 3 3 3 3 3 3 3
D
+1.35VSUS
BA0 BA1 BA2
B2 D9 G7 K2 K8 N1 N9 R1 R9
VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9
CK CK CKE ODT CS RAS CAS WE
A1 A8 C1 C9 D2 E9 F1 H2 H9
VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9
DQSL DQSU DML DMU
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9
DQSL DQSU
RESET ZQ
NC#J1 NC#L1 NC#J9 NC#L9
C
B1 B9 D1 D8 E2 E8 F9 G1 G9
VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9
R511 CHB@240/F_4
12
BYTE5_40-47 BYTE7_56-63
U24
100-BALL SDRAM DDR3 CHB@RAM _DDR3L
Hynix AKD5JGETW00--H5TC4G63AFR-PBA
VTT TERMINATIONS +VDDQ_VTT
C101 CHB@10U/6.3V_6
C393 CHB@10U/6.3V_6
C102 CHB@10U/6.3V_6
C371 CHB@10U/6.3V_6
C370 CHB@10U/6.3V_6
C183 CHB@10U/6.3V_6
C380 [email protected]/10V_4
C154 [email protected]/10V_4
C99 [email protected]/10V_4
C399 [email protected]/10V_4
C178 *10U/6.3V_6
Place these Caps near each X16 Memory Down C396 CHB@1U/6.3V_4
C129 CHB@1U/6.3V_4
C94 CHB@1U/6.3V_4
C394 CHB@1U/6.3V_4
C193 CHB@1U/6.3V_4
C378 CHB@1U/6.3V_4
C366 CHB@1U/6.3V_4
C120 CHB@1U/6.3V_4
C191 CHB@1U/6.3V_4
C397 CHB@1U/6.3V_4
C398 CHB@1U/6.3V_4
C95 CHB@1U/6.3V_4
Place these Caps near Memory Down CA & DQ pin +V_SMDDR_VREF_DQ1
C137 [email protected]/10V_4
C197 [email protected]/10V_4
C98 [email protected]/10V_4
C177 *10U/6.3V_6
C195 CHB@1U/6.3V_4
C367 CHB@1U/6.3V_4
C395 CHB@1U/6.3V_4
C192 CHB@1U/6.3V_4
C161 CHB@1U/6.3V_4
C93 CHB@1U/6.3V_4
C194 CHB@1U/6.3V_4
C200 CHB@1U/6.3V_4
C199 CHB@1U/6.3V_4
C187
B
R266 R292 [email protected]/F_4
R220
*80.6/F_4
R226
1K/F_4
*2/F_6
C196 [email protected]/16V_4
PLACE 'CA' CAPACITOR AT GENERATION POINT
+VDDQ_VTT +1.35VSUS M_B_ODT0
C368 CHB@1U/6.3V_4
Vref_DQ
R291 [email protected]/F_4 +V_SMDDR_VREF_DQ1
R564 [email protected]/F_4
R274
*24.9/F_4
Vref_CA +V_SMDDR_VREF_DIMM
A
+VDDQ_VTT
C385 CHB@1U/6.3V_4
C206 CHB@1U/6.3V_4
C207 CHB@1U/6.3V_4
C404 CHB@1U/6.3V_4
1
C138 [email protected]/25V_4
*80.6/F_4 *80.6/F_4
1
C400 [email protected]/16V_4
M_B_VREF_CA
3
C170 *0.022U/25V_4
2
22uF/6.3V_6
*2/F_6
2
R267 R565 [email protected]/F_4
R223 R224
3
+1.35VSUS
+VDDQ_VTT
M_B_CLKP0 M_B_CLKN0
M_B_VREF_DQ C171 *0.022U/25V_4
change to 3.65K Voltage Divider circuit 11/5 Modify VRFEDQ/VREFCA circuit follow SO-DIMM 11/02
Add +1.35VSUS 10/17 C146 [email protected]/10V_4
C373 CHB@1U/6.3V_4
+1.35VSUS
1
B
PLACE 2 CAPS NEAR EACH DDR3L IC
[email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4
2
+V_SMDDR_VREF_DIMM
Distributed around all DRAM devices (CHB)
R212 R213 R221 R516 R521 R518 R239 R231 R211 R215 R222 R241 R524 R227 R218 R526 R517 R240 R216 R530 R217 R513 R527 R232
2
+1.35VSUS
M_B_RAS# M_B_CAS# M_B_WE# M_B_BS0 M_B_BS1 M_B_BS2 M_B_CKE0 M_B_CS#0 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
VREF_DQ CIRCUIT VREF_CA_CIRCUIT
1
DE-CAPS FOR MEMORY CHANNEL B
R272
*24.9/F_4
M_B_CLKP0_N0_C A
20 mils
C387 CHB@1U/6.3V_4
C198 CHB@1U/6.3V_4
C403 CHB@1U/6.3V_4
C410 CHB@1U/6.3V_4
C411 CHB@10U/6.3V_6
M_B_CLKP0
C143
*0.2P/50V_4
R251
80.6/F_4
M_B_CLKN0
Quanta Computer Inc. PROJECT : ZHP/ZSP 5
4
3
2
Size
Document Number
Date:
Tuesday, July 26, 2016
DDR3L MEMORY DOWNx16 CHB Sheet 1
12
of
36
Rev 1A
4
3
C168
0.1U/16V_4
0.1u/16V_4
0.1u/16V_4
0.1U/16V_4
0.1U/16V_4
0.1u/16V_4
2
6
C181 1u/6.3V_4
TP20 IOAC_WLAN_WAKE#
21
PROCHOT_EC
17
126 GPB5 5 IRQ_SERIRQ 15 PCH_SUSPWRDNACK 23 SIO_EXT_SCI# 14 WRST# 4 SIO_RCIN# IOAC_WLAN_WAKE# 16
TP26 23 IRQ_SERIRQ PCH_SUSPWRDNACK 23 SIO_EXT_SCI#
LAD0/GPM0(3) LAD1/GPM1(3) LAD2/GPM2(3) LAD3/GPM3(3) LPCRST#/GPD2 LPCCLK/GPM4(3) LFRAME#/GPM5(3)
24 15,23
*short_4KB_BL_LED DNBSWON#
R545
PANEL_LED_EN DNBSWON#
113 123
GA20/GPB5(3) SERIRQ/GPM6(3) LPC ECSMI#/GPD4(3) ECSCI#/GPD3 WRST# KBRST#/GPB6(3) PWUREQ#/BBO/SMCLK2ALT/GPC7(3)
CRX0/GPC0 CTX0/TMA0/GPB2(3)
CIR
SMCLK0/GPB3 SMDAT0/GPB4 SMCLK1/GPC1 SMDAT1/GPC2 PECI/SMCLK2/GPF6(3) SMDAT2/PECIRQT#/GPF7(3)
SM BUS
PS2CLK0/CEC/TMB0/GPF0 PS2DAT0/TMB1/GPF1 PS2CLK2/GPF4 PS2DAT2/GPF5
GPIO
IT8987 LQFP
PWM0/GPA0 PWM1/GPA1 PWM2/GPA2 PWM3/GPA3 PWM4/GPA4 PWM5/GPA5
Active H
14 15
15 15
MY16 MY17 TS_EN
SPIVCC_ON PTP_PWR_EN#
PTP_PWR_EN# 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15
36 37 38 39 40 41 42 43 44 45 46 51 52 53 54 55
MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15
MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15
100 125
EXTERNAL SERIAL FLASH ADC0/GPI0(3) ADC1/GPI1(3) ADC2/GPI2(3) ADC3/GPI3(3) ADC4/GPI4(3)
KSO16/SMOSI/GPC3(3) KSO17/SMISO/GPC5(3) PWM6/SSCK/GPA6 SSCE0#/GPG2 SSCE1#/GPG0 KSO0/PD0 KSO1/PD1 KSO2/PD2 KSO3/PD3 KSO4/PD4 KSO5/PD5 KSO6/PD6 KSO7/PD7 KSO8/ACK# KSO9/BUSY KSO10/PE KSO11/ERR# KSO12/SLCT KSO13 KSO14 KSO15
TACH2/GPJ0(3) GPJ1(3) DAC2/TACH0B/GPJ2(3) DAC3/TACH1B/GPJ3(3)
85 86 89 90
IOAC_RST# EC_FPBACK# TPCLK TPDATA
24 25 28 29 30 31
PWRLED# BATLED1# SUSLED# BATLED0# MAINON GPA5
47 48
FAN1_RPM GPD7
120 124
SUSON GPC6
107 18 21
NBSWON# SUSC# HWPG
112
RSMRST#
66 67 68 69 70
76 77 78 79
100K_4
R552
100K_4
S5_ON
R588
10K_4
R589
33/J_4
LID#
PWRLED# BATLED1# SUSLED# BATLED0# MAINON TP41
GPJ7 GPJ6
CLOCK
C224
RF_EN ICMNT GPI2 S5_ON_R LANPWR#
SUSON GPC6
28
NBSWON# SUSC#
15,16 15,23
RF_EN ICMNT TP42
0/J_4
Power auto recovery
23
+3V_LDO_EC R237
*0/J_4
+1.8V_S5
R235
*0/J_4
3V_LDO
R236
*short_4
1.8V_LDO
R249
*short_4
S5_ON
S5_ON
20
0/J_4 0/J_4
29
2 128
1.8V_LDO
1
26
2
6 SPIVCC_ON R244 S5_ON R305
*short_4
*0/J_4
R259
0/J_4 TPD_INT#
15
SYS_SHDN#
3
20 mils
U8
4
VIN
NC
GND 5
EN
1.8V_LDO
VOUT
C147 2.2U/6.3V_4
G9090-180T11U
C169 1u/6.3V_4
26,32
SM BUS ARRANGEMENT TABLE
0.1u/16V_4
+3V_RTC
SM Bus 1
Battery
SM Bus 2
CPU Thermal
+3VPCU
Battery B/I SW R539 *0_4
To battery B/I pin
SM Bus 3
25
SM Bus 4
VCC_SPI R515
R541 *10K_4 LID_SW
3.3K/F_4
SPI_CS0#_UR_ME
GND 3.3K/F_4
SPI_WP#
3
R522
3.3K/F_4
SPI_Hold#
7
VCC WP#
SPI_SI SPI_SO CS# SPI_SCK
PCH_SPI_SI_EC
R531
*10K_4
PCH_SPI_SO_EC
R523
*10K_4
PJA138K 2
Vgs = 1.5V
1
R528
PCH_SPI_SI_EC PCH_SPI_SO_EC SPI_CS0#_UR_ME PCH_SPI_CLK_EC
SPI Socket P/N:DFHS08FS023 A-stage stuff Socket
4
C390 *0.1U/25V_4
Vgs = 1.5V
Q45 *PJ4N3KDW SW3 Reset_SW_H1.5
VCC_SPI
GND
C386
BI_GATE
2
SPI_HOLD GND SPI_FLASH soic8-7_9-1_27
*0.1U/16V_4 R547 100K_4
Q46
1
VCC_SPI
5 2 1 6
WRST#
+3V_RTC 1
U28 8
R537 *0_4
BI#
BI#
Battery disable when shell opened
0.1U/16V_4
*short_4
B-Test mount
680_LDO
100K_4
IOAC_WIGIG_RST# TPD_INT#
R229
Modify 12/16
26,31,32
3V_LDO
680_LDO
B
SPI NOR FLASH
A
Reset Battery
CONN SMD HOUSING 8P 2R FS(P1.27,H5.0) VSTBY_FSPI
R534
*short_4 VCC_SPI 2 4 5 6
R568 10K_4
VSTBY_FSPI
+3VPCU
20 mils
C383
HWPG(KBC)
2N7002K
C
21 25
VNN_ON SYS_HWPG TP38 CLR_CMOS
6,25,29
14
LANPWR#
VNN_ON GPJ1 R290 PCH_PWROK GPJ3 R284
Change 2nd SMBUS PU to +3V 11/3
2
100K_4
ECAGND
10u/6.3V_6
R325
L6 BLM15AG121SN1D(120,500MA)_4
12/09 EC request ZHP/ZSP ID PD. ZHP(11" KB)---L (eDP Cable pull-low) ZHP(13" KB)---H
A
4.7K_4 4.7K_4
PROCHOT_EC
16
RSMRST#
IT8987E/CX
VCC_SPI
+3V
R247 R246
1/20 Swap with pin 79
FAN1_RPM TP45
C174
*200K_6
GND
2ND_MBCLK 2ND_MBDATA
3 4
R611
4.7K_4 4.7K_4
Q44
3
GPC6
R234 R233
H_PROCHOT#
22 22 22 22 26,27,28,31,32
15 mil 200K_6
MBCLK MBDATA
+3V
IOAC_RST# 20,21 EC_FPBACK# 14 TPCLK 15 TPDATA 15
SW2
R610
+3V_LDO_EC
14,16
Add SYS_SHDN# 10/27
MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7
D
SM BUS PU(KBC)
MBCLK 25 MBDATA 25 2ND_MBCLK 16 2ND_MBDATA 16 TP27 LID#_R
Add CLR_CMOS PD 10/30
KBMX
HWID +3V
R303
SUSON
1 2
The sequence requirement for "VCC_1P05 High (90%) to SOC_PWROK (PCH_PWROK)" assertion timing is minimum of 5mS (Min = 5mS). There is no maximum timing requirement for this sequence. This will be updated in the next revision of Apollo Lake EDS MoW_WW39
MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7
MBCLK MBDATA 2ND_MBCLK 2ND_MBDATA GPF6
R285
ECAGND
15 15 15 15 15 15 15 15
MAINON
A/D D/A
SPI ENABLE
58 59 60 61 62 63 64 65
B
56 57 32
MY16 MY17 TS_EN
110 111 115 116 117 118
ICMNT
FSCK/GPG7 FSCE#/GPG3 FMOSI/GPG4 FMISO/GPG5
VCORE
PANEL_LED_EN
GPC0 Only for 2 cell battery
WAKE UP
12
PIN
PCH_SPI_CLK_EC 105 SPI_CS0#_UR_ME 101 102 PCH_SPI_SI_EC PCH_SPI_SO_EC 103
PWRSW/GPE4 RI1#/GPD0(3) RI2#/GPD1
RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7
AVSS
Sawp TS_EN and CPUFAN# 10/23
UART port
75
AC_Protect TP28
ADC5/DCD1#/GPI5(3) ADC6/DSR1#/GPI6(3) ADC7/CTS1#/GPI7(3) RTS1#/GPE5 PWM7/RIG1#/GPA7 DTR1#/SBUSY/GPG1/ID7 CTX1/SOUT1/GPH2/SMDAT3/ID2 CRX1/SIN1/SMCLK3/GPH1/ID1
VSS VSS VSS VSS
25
R573 R255
TMRI0/GPC4(3) TMRI1/GPC6(3)
27 49 91 104
6 THERMTRIP#
TP40 25 ACIN 25 TEMP_MBAT# WLANPWR# 19 PCBEEP_EC
71 ODD_POWER 72 ACIN 73 TEMP_MBAT# 35 WLANPWR# 34 PCBEEP_EC *short_4 HWPG_1.05V_EC# 122 95 *short_4 GPH2 94 GPH1
10K_4
R546 TACH0A/GPD6(3) TACH1A/TMA1/GPD7(3)
VSS
21
R248
DAC4/DCD0#/GPJ4(3) DSR0#/GPG6 GINT/CTS0#/GPD5 PS2DAT1/RTS0#/GPF3 DAC5/RIG0#/GPJ5(3) PS2CLK1/DTR0#/GPF2 TXD/SOUT0/GPB1 RXD/SIN0/GPB0
1
C176 *10p/50V_4
*0/J_4
*10K_4
R587
開EC對底下SPI ROM的interface
PWM
KSI0/STB# KSI1/AFD# KSI2/INIT# KSI3/SLIN# KSI4 KSI5 KSI6 KSI7
*22_4 C
80 NUMLED# 119 SUSB# 33 EC_PWROK 88 PCH_BLON_EC 81 FAN1_DAC IOAC_LAN_WAKE# 87 109 *short_4 FAN2_RPM 108 AMP_MUTE#
R281
TP36 15,23 SUSB# 23 EC_PWROK 14 PCH_BLON_EC 16 FAN1_DAC 20 IOAC_LAN_WAKE# 5 ME_WR# 19 AMP_MUTE#
R250
SPIVCC_ON
D35 VPORT_4
PS/2
CLK_PCI_EC
R277
S5_ON
3 99 98 97 96 93
19 20
LPCPD#/GPE6
3/4 Modify to RB500V-40
SB_ACDC 25 TP43 BT_EN 21
2
RB500V-40 D30
10 9 8 7 22 13 6
*short_4 *0/J_4
5
R283 100K_4
LAD0 LAD1 LAD2 LAD3 PLTRST# CLK_PCI_EC LPC_LFRAME#
GPH7 ID6/GPH6 ID5/GPH5 ID4/GPH4 ID3/GPH3 CLKRUN#/ID0/GPH0
1
2
+3V_LDO_EC
1
0.1u/16V_4 U10
5,21 LPC_LAD0 5,21 LPC_LAD1 5,21 LPC_LAD2 5,21 LPC_LAD3 17,20,21,23 PLTRST# 5 CLK_PCI_EC 5,21 LPC_LFRAME#
L80HLAT/BAO/GPE0 L80LLAT/GPE7
10/29 Modify it
127
C175
84 83 82
2.2_6
EGCLK/GPE3 EGCS#/GPE2 EGAD/GPE1
R264
+3V_EC
106 74
+3V_S5
12 mils
VSTBY(PLL)
*2.2_6
R273 R278 BT_EN
GPE0 TP37 GPE7 TP39 D/C# D/C# 25 11/11 swap to pin 125 GPH6 R252 *short_4 USBON# 18 GPH5 R253 *short_4 TPD_EN 15 GPH4 TP29 GPH3 TP30 GPH0 R258 *short_4 CLKRUN# 5,21
VSTBY_FSPI AVCC
R268
PCH_ACPRESENT VCCDSW
0.1u/16V_4
10K_4
6
C244
R551
2
C153
NBSWON#
1
C149
13
+3V_LDO_EC
Modify 10/27
6,8,15,20,21,23,26,31
0.1U/16V_4 C151
C204
+3V_S5
3
+3VPCU_EC
C150
+3V
D
2.2_6
+3VPCU_EC
(For PLL Power)
1 3
12 mils
2.2_6 2
L4 BLM15AG121SN1D(120,500MA)_4
C152
3
R343
11 26 50 92 114 121
R245 1
12 mils
VCC VSTBY VSTBY VSTBY VSTBY VSTBY
+3V_LDO_EC
+3VPCU_ECPLL
VSTBY_FSPI
2
+3VPCU_EC and +3V_RTC minimum trace width 12mils.
12 mils
+A3VPCU C202 0.1U/16V_4 ECAGND
1
1
L8 BLM15AG121SN1D(120,500MA)_4
EC(KBC)
2
+1.8V_S5 4,5,6,8,10,14,15,21,23,25,29,31 +3V 4,5,6,11,14,16,17,19,20,21,22,23,26,27,28,29,31,32,33 +3VPCU 6,14,15,16,19,20,21,22,25,26,27,31,33
4
12 mils
1
5
27 29
HWPG_1.05V IMVP_PWRGD
D31
RB500V-40
D29
*RB500V-40
HWPG
SPI ROM
Remove SYS_HWPG for HWPG 10/26 31
HWPG_1.24V
28
HWPG_1.35V
31
HWPG_1.5V
D34
*RB500V-40
D33
*RB500V-40
D28
*RB500V-40
5
1.8V
Vender
Size
WND
1M 1M 1M
EON Giga
4
Quanta P/N
Vender P/N
AKE5GZP0N00
W25Q80BWSSIG
AKE5GFN0Q00
EN25S80A-104HIP
AKE5GZN0Q00
GD25LQ80BSIGR
Quanta Computer Inc. PROJECT :ZHP/ZSP 3
2
Size
Document Number
Date:
Tuesday, July 26, 2016
Rev 1A
KBC IT8987CX Sheet 1
13
of
36
5
4
3
+VIN 25,26,28,29,30,32,33 +5V 16,17,19,24,26,32 +3V 4,5,6,11,13,16,17,19,20,21,22,23,26,27,28,29,31,32,33 +1.8V 17,21,31,32 +1.8V_S5 4,5,6,8,10,13,15,21,23,25,29,31 +3VPCU 6,13,15,16,19,20,21,22,25,26,27,31,33
1
R468
10mil
20mil
CCD_PWR
TOUCH_SCREEN_PWR
2
+VIN
4
D
4
3
PCH_DISP_ON
IN
1
OUT
IN
+LCDVCC_1
R52
C334
*10p/50V_4
1000p/50V_4
*10p/50V_4
1000p/50V_4
+12V_Panel
INT
C26
C24
C25
*0.1u/16V_4
0.1U/16V_4
33p/50V_4
+VIN_BLIGHT
PCH_DPST_PWM
Follow ZQF pin defined
BL_ON
R81
*short_4
BL_Enable
PCH_DPST_PWM
R80
*short_4
BL_PWM_DIM
LCDVCC Modify TPS Power 10/30 R454 R457 R459
10K_4
10K_4
USB
3
EC_FPBACK#
USB_TS5_P R446 USB_TS5_N R447
USB_TS5_P USB_TS5_N
TPS@0_4 TPS@0_4
USB_TS5_P_R USB_TS5_N_R
I2C
13
I2C_3_SCL_CONN I2C_3_SDA_CONN
Q11 DTC144EUA
1
C337
R57 R58
CCD *TSI@0_4 *TSI@0_4
USB_TS5_P_R USB_TS5_N_R
180P/50V_4 R450
4 4
INT_EDP_AUXP INT_EDP_AUXN
INT_EDP_AUXP INT_EDP_AUXN
C336 C338
0.1u/16V_4 0.1u/16V_4
EDP_AUXP EDP_AUXN
4 4
INT_EDP_TXP1 INT_EDP_TXN1
INT_EDP_TXP1 INT_EDP_TXN1
C326 C327
0.1u/16V_4 0.1u/16V_4
EDP_TXP1 EDP_TXN1
4 4
INT_EDP_TXP0 INT_EDP_TXN0
INT_EDP_TXP0 INT_EDP_TXN0
C328 C329
0.1u/16V_4 0.1u/16V_4
5 5
USB_CCD6_P USB_CCD6_N
USB_CCD6_P USB_CCD6_N
R444 R445
USB_TS5_P_R USB_TS5_N_R C333
13
TPS@180P/50V_4Touch screen (I2C) R452
TS_EN
TPS@33/J_4 13
Touch screen SEL.23
3/4 Modify to 4.7K
U3
C33
GND
2
*[email protected]/25V_4
5
I2C_3_SDA_R
I2C_3_SDA_R
4
5
I2C_3_SCL_R
I2C_3_SCL_R
3
VREF1 SDA1 SCL1
8
EN
C31
*[email protected]/25V_4
6
R60
R61
*[email protected]_4
*[email protected]_4
+3V
TPS@10K_4
R448
TP_INT
TP_INT
G_4
G_1 C
EDP@50398-04071-001
2nd source:DFHS40FS150 R451
*100K/F_4
EDP_AUXP
R443
*100K/F_4
EDP_AUXN
DDI1_EDP_HPD_R +3V
Q12
2
GND
EDP_HPD_R
7
VREF2 SDA2 SCL2
5
I2C_3_SDA_CONN
6
I2C_3_SCL_CONN
PJA138K 1
1
GND
TPS@33/J_4
TPS@180P/50V_4
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
3
R77 *TSI@200K_4
+1.8V_S5
23
GPC6
R100 *10K_4
+3V
11/03 Modify
R449
GPIO8 C330
+1.8V
Touch screen level shift I2C(reserve)
EDP_TXP0 EDP_TXN0 USB_CCD6_P_R USB_CCD6_N_R
*short_4 *short_4
TS
1
4
5 5
LID591#,EC intrnal PU 2
PJ4N3KDW
C
Touch screen
BL_ON
100K_4 Q10
13,16
D5 1N4148WS
BL# 6
R62
2
PCH_BLON_R 3
*short_4
R73
5
*short_4
R59
R63
LID#
TOUCH_SCREEN_PWR TP_RST# TPS@10K_4 R79 BL_PWM_DIM BL_Enable EDP_HPD_R_C 33/J_4
+3V EDP_HPD_R
LID#
*0_4 TPS@0_6
TP_RST#
R78 *100K_4
+3V
CCD_PWR
*short_6
+3V +5V
R53
0.01U/25V_4
D
23
PCH_BLON_EC
0.1U/50V_6
C324
CN5
4
PCH_EDP_BLON
*4.7U/25V_8
C335
10U/6.3V_6
+3VPCU
13
C340
C27
R56 *100K/F_4
4
C341 0.1U/50V_6
*VL@DFLS240-7-F
LCDVCC
*short_8
2
GND
ON/OFF
C325
+VIN_BLIGHT
60mil 1
5
*1U/6.3V_4
60mil
2
C28
C332
40mil
G_5
U2 G5245AT11U
C331
40mil 1
*VL@DFLS240-7-F D6 2 1
+3V
14
*short_8 D24
G_0
EDP Conn.
2
R97 100K/F_4
*TSI@PCA9306 GND
B
GND
EMI (EMC)
HDMI Conn.
B
C_TX0_HDMI+ R7
+1.8V
HDMI SMBus Isolation
CN1 *100/F_4 C_TX0_HDMI-
C_TX1_HDMI+ +1.8V 4
R34
*2.2K_4
Q34
4
SDVO_CLK
R9
5 3
HDMI_SCLK
4
1
SDVO_DATA +1.8V
6
C13
0.1U/16V_4
C_TX2_HDMI+
4
C14 C15
0.1u/16V_4 0.1U/16V_4
C_TX2_HDMIC_TX1_HDMI+
4
IN_D1# IN_D0
C16 C11
0.1u/16V_4 0.1U/16V_4
C_TX1_HDMIC_TX0_HDMI+
IN_D0# IN_CLK
C12 C17
0.1U/16V_4 0.1U/16V_4
C_TX0_HDMIC_TXC_HDMI+
IN_CLK#
C18
0.1u/16V_4
C_TXC_HDMI-
4 4
C_TX2_HDMI+ R8
IN_D2 IN_D2# IN_D1
4
*100/F_4 C_TX1_HDMI-
2
4 4
4
*100/F_4
HDMI_SDATA
C_TX2_HDMI-
D19
+5V
C_TXC_HDMI+ R33
*2.2K_4
SSM6N43FU
R10
D21
2 2
RB500V-40 1 5V_HSMBCK 1 5V_HSMBDT RB500V-40
R5 R4 C6 C7
*100/F_4
Intel Requesrt Rds_ON