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Topstar Digital technologies Co.,LTD D

D

Board name: Mother Board Schematic Project name:

1. System Block Diagram & Schematic page description; 2. Power Block Diagram & Discription;

N01

Version: VerA

3. Annotations & information;

initial Date:

4. Schematic modify Item and history;

New update:

5. Power on & off Sequence; 6. ACPI Mode Switch Timings; 7. Power On Sequence Map; 8. CLOCK Distribution;

C

C

9. Power Distribution;

Topstar Confidential

Hardware drawing by:

Hardware check by:

Power drawing by:

Power check by:

EMI Check by:

B

B

Manager Sign by:

A

A

TOPSTAR TECHNOLOGY Swain Xu Page Name

Title

Size A3

N01

Project Name

Rev A

Date: Wednesday, July 16, 2008 Sheet 1 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

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CONTENT

Topstar Confidential

1 Title 2 System Block & Sch Page 3 PWR Block & description 4 NOTE and Annotations 5 Sch Modify and history 6 CK-505M 7 Diamondvill (1of2)(Host BUS) 8 Diamondvill (2of2)(Power &GND) 9 Calistoga(HOST) 10 Calistoga(Graphic) 11 Calisoga(DDRII& NCTF) 12 Calisoga(Power) 13 Calistoga(VSS&NC) 14 DDRII SODIMM0 15 LVDS Inverter CONN 16 CRT CONN 17 ICH7_M(1 of 4) 18 ICH7_M(2 of 4) 19 ICH7_M(3 of 4) 20 ICH7_M(4 of 4 21 SATA HDD 22 Card Reader(UB6232 USB) 23 PCIE MINI SLOT 1 24 PCIE MINI SLOT 2 25 USB Port & FAN 26 Audio (ALC662) 27 LED 28 OTP 29 KBC(W83L951DG) 30 LAN(RTL8101E) 31 ADAPTER IN 32 BATTERY JACK 33 V3.3AL/+V5AL POWER 34 DDR V1.8/+V0.9S POWER 35 V1.5S/+V1.05S POWER 36 Power Good Logic_OVP 37 Power Discharge Circuit 38 System 2.5V 39 VCORE POWER 40 CHARGER 41 Power On Secquence & Reset M 42 Power ON/OFF

ShenZhen Topstar Industry Co.,LTD D

N01 SYSTEM BLOCK Ver:A CK505M Clocking

Diamondville SC FCBGA 437PIN

CY28548

+VCC_CORE,+VCCP +VCCA1.5

+V3.3S

PG 6

PG 7,8

Backlight Connector +VDC

PG 15

FSB 533MHz

10.21' TFT

LVDS

+V3.3S

C

DDR2 400/533

Calistoga GSE

PG 15

998 FCBGA VGA

+V3.3S,+V1.5S, +V1.05S,+V1.8 +V2.5S

R/G/B

+V5S

PG 16 PCIE mini Card

PG 9,10,11, 12,13

PCIE mini Card

PG 24

DDR2 SODIMM1 400/533 +V0.9S,+V1.8,+V3.3S PG 14

10/100M

PG 23

PCIE X1

DMI x2

LAN RTL8101E

RJ45

+V5S,+V3.3S

PG 30 PCIE 1X

ICH7-M

82801GBM 652 BGA

USB1.1/2.0

8Mbit

B

S-ATA

+V1.05S,+V3.3S +V3.3AL,+V5AL +V1.5S,+V5S +V3.3A_RTC

BIOS +V3.3AL

2.5" HHD

SATAO(R1.0)

PG 21

PG 17,18,19,20

PG 18

HDA

USB PORT1

C

B

Speaker

L

+V5S

PG 25

KB Controller/EC +V5AL

AMP TPS6017A2

+V5AL

USB PORT2

+V5S,+V3.3S

D

KB Matrix

PG 26

R

W83L951DG +V3.3AL

PG 29

LED & TouchPAD

AZALIA ALC662 +V5S,+V3.3S

USB PORT3

MiC

PG 26

Audio Jack

PG 26

+V5AL

Daught Board TOPSTAR TECHNOLOGY

A

Swain Xu Page Name SD/MMC/MS/XD CARD

Size A3

Rev N01 A of Wednesday, July 16, 2008 2 42 Date: Sheet PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

PG 22

5

System Block & Index

4

3

2

Project Name

1

A

5

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N01

2

1

POWER BLOCK Ver:A

D

D

Charger power ISL6251 PU9

Adapter 12V 2.5A

Battery 7.4V-8.4V 4A

Power Switch

VCC_CORE ISL6545

+VDC

PU8

+VCC_CORE 1.1V，5A

C

C

Always power ISL6545 PU1/PU2

+V3.3AL，2A /+V5AL，3A MOSFET Switch

B

Chipset Power ISL6545

DDR Power TPS51116

PU4/PU5

PU3

+V1.8 +V0.9S

+V1.5S，3A /+V1.05S，3A

B

+V3.3S，2A /+V5S，3A LDO

+V2.5S，0.5A

A

A

TOPSTAR TECHNOLOGY Swain Xu Page Name Size A3

Project Name

PWR Block & description Rev A

N01

Wednesday, July 16, 2008 3 42 Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

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1

Voltage Rails

D

+VDC

Primary DC system power supply (6V-9.5V)

+VBATTERY

Battery Power supply (6-8.4V)

+VCC_CORE

Core Voltage for CPU

+V1.05S

1.05V for Calistoga & ICH7M core / FSB VTT

+V1.8

1.8V power rail for DDR2

+V0.9S

0.9V DDR2 Termination voltage

+V3.3AL

3.3V always on power rail

+V5AL

5V for ICH7-M's VCC5 Refsus

+V3.3S

3.3V main power rail

+V5S

5V main power rail

I2C SMB Address Device

Address

Hex

Master

Clock Generator

D2

CPU Thermal Sensor

1101 001x 1010 000x 1001 100x

Smart Battery

0001 011x

A0 98 16

ICH7-M ICH7-M KBC KBC

PCIE Slot

TBD

TBD

ICH7-M

SO-DIMM0

D

Power States

+V2.5S

2.5V power rail for 945GMS

C

Board stack up description

Signal

SLP_S3#

SLP_S4#

SLP_S5#

+V*ALW

S0(Full On)

HIGH

S3(STM)

LOW

S4(STD) S5(SoftOff)

+V*S

Clock

HIGH

HIGH

ON

HIGH

HIGH

ON

ON

ON

ON

ON

OFF

OFF

LOW

LOW

HIGH

ON

OFF

OFF

OFF

LOW

LOW

LOW

ON

OFF

OFF

OFF

+V*

C

PCB Layers Top(Signal1) VCC 2 Signal 3

Trace Impedence:55ohm +/-15%

Wake up Events LID switch from EC

Signal4

Power switch from EC

Ground 5 Bottom(Signal6)

B

5

3

USB Table

SOT23 USB Port#

A

B

PCB Footprints

Function Description

0

Standard USB2.0 Port

1

Standard USB2.0 Port

2

Standard USB2.0 Port

3

MINICARD_USB

4

CAM_USB

5

MINICARD_USB

6

CR_USB

7

NC

1

2

4

SOT23_5 1 2 3

ns: Component marked "ns" is not stuff

A

TOPSTAR TECHNOLOGY Swain Xu Page Name Size A3

Project Name

NOTE N01

Rev A

Date: Wednesday, July 16, 2008 Sheet 4 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

5

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Schematic modify Item and history:

D

D

C

C

B

B

A

A

TOPSTAR TECHNOLOGY Swain Xu Page Name Size A3

Project Name

Sch Modify and history Rev A

A

Date: Wednesday, July 16, 2008 Sheet 5 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

+V3.3S

3

2

FB28 FB0805 100ohm@100MHz,3A 2

1

D

4

C391 0.1uF/10V,X5R C0402

C389 0.1uF/10V,X5R C0402

+V3.3S_CK_VDD

+V3.3S_CK_VDD C388 10UF/6.3V,X5R C0805

C392 4.7UF/10V,Y5V C0805

C393 0.047uF/16V,X7R C0402

C398 0.047uF/16V,X7R C0402

C397 0.1UF/25V,Y5V C0402

+VDDIO_CLK +VDDIO_CLK +VDDIO_CLK

2 9 16 61

VDD_PCI VDD_48 VDD_PLL3 VDD_REF

39 55

VDD_SRC VDD_CPU

48

SMB_DATA SMB_CLK

63 64 38 37

3

SRC5/PCI_STOP# VDD_IO SRC5#/CPU_STOP# VDD_PLL3_IO VDD_SRC_IO_1 CPU0 VDD_SRC_IO_2 CPU0# VDD_SRC_IO_3 VDD_CPU_IO CPU1 CPU1# PCI0/OE#_0/2_A SRC8/CPU2_ITP PCI1/OE#_1/4_ASRC8#/CPU2#_ITP

4

PCI2/TME

5

PCI3/FSD

6

PCI4/SRC5_SEL

1

+V3.3S

TME FB29 100ohm@100MHz,3A FB0805

29

PCI_CLK_EC

23 PCI_CLK_DEBUG

2

1

7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39 7,8,9,11,12,17,20,28,35,36,37

C395 10UF/6.3V,X5R C0805

18

+VDDIO_CLK C396 0.1uF/10V,X5R C0402

PCI_CLK_ICH

R631

22

R0402

R632

22

R0402

R635

22

R0402

R640

10K R0402

CLK_XTAL_IN

C401 10UF/6.3V,X5R C0805

+VDDIO_CLK C400 0.1uF/10V,X5R C0402

C402 0.1uF/10V,X5R C0402

R636 33

19

10

CLK_BSEL0 R637 2.2K R0402 CLK_BSEL1 CLK_BSEL2 R639 10K R0402

57 62

R638 33

CLK_ICH14

R0402

C404 0.1uF/10V,X5R C0402

8 11 15 19 52 23 29 58 42

+VDDIO_CLK C406 0.1uF/10V,X5R C0402

C407 27pF/50V,NPO C0402

B

SRC10 SRC10#

R345 0 R347 0

R0402 R0402

D

SMB_DATA_S SMB_CLK_S

14,19,23,24 14,19,23,24

PM_STP_PCI# 19 PM_STP_CPU# 19

54 53

CPU0 CPU#0

RN7

51 50

CPU1 CPU#1

RN8

47 46

1 3

2 33 4 RA0402_4

CLK_CPU_BCLK 7 CLK_CPU_BCLK# 7

1 3

2 33 4 RA0402_4

CLK_MCH_BCLK 9 CLK_MCH_BCLK# 9

RN18 1 3

2 33 4 RA0402_4

CLK_PCIE_EXPCARD2 24 CLK_PCIE_EXPCARD2# 24

4 33 2 RA0402_4

CLK_PCIE_EXPCARD 23 CLK_PCIE_EXPCARD# 23

RN10 3 1

34 35

MPCIE_CLKREQ MCH_CLKREQ

R643 475,1% R634 475,1%

R0402 ns R0402 ns

SRC11/OE#_10 SRC11#/OE#_9

33 32

SRC9 SRC9#

30 31

SRC7/OE#_8 SRC7#/OE#_6

44 43

SRC6 SRC6#

41 40

1 3

SRC4 FSB/TEST_MODE SRC4# REF0/FSC/TEST_SEL SRC3/OE#_0/2_B SRC3#/OE#_1/4_B

27 28

RN17 3 1

2 RN16 4 33 RA0402_4 4 33 2 RA0402_4

24 25

RN12 3 1

4 33 2 RA0402_4

CLK_PCIE_LAN 30 CLK_PCIE_LAN# 30

21 22

RN13 3 1

4 33 2 RA0402_4

CLK_ICH_SATA 17 CLK_ICH_SATA# 17

4 33 2 RA0402_4

DREFCLK DREFCLK#

PCIF5/ITP_EN XTAL_IN

USB_48/FSA

VSS_PCI SRC2/SATA VSS_48 SRC2#/SATA# VSS_IO VSS_PLL3 SRC1/SE1 VSS_CPU SRC1#/SE2 VSS_SRC_1 VSS_SRC_2 SRC0/DOT96 VSS_REF SRC0#/DOT96# VSS_SRC3 CK_PWRGD/PWRDWN#

3 1

4 2 RN11 33 RA0402_4

PCIE_CLKREQ# 23,24 MCH_CLKREQ# 10 CLK_MCH_3GPLL 10 CLK_MCH_3GPLL# 10 C

DREFSSCLK DREFSSCLK#

10 10

CLK_PCIE_ICH 18 CLK_PCIE_ICH# 18

17 18 RN14 3 1

13 14

R734 0

56

R0402

10 10

VR_PWRGD_CLK_EN

19

CLK_XTAL_IN

1

C405 10UF/6.3V,X5R C0805 ns

60

R0402

19 CLK_USB48

+VDDIO_CLK C403 0.1uF/10V,X5R C0402

7

CLK_XTAL_OUT 59 No more than 500 milXTAL_OUT

Set to SRC8

C399 10UF/6.3V,X5R C0805

27M_SEL PCIF_ITP_EN

SMBUS ADD:1101 001X IO_VOUT

12 20 26 36 45 49

+VDDIO_CLK

C394 10UF/6.3V,X5R C0805

+V3.3S +V1.05S

U36 CY28548 TSSOP64_0D5_6D1 C390 0.1uF/10V,X5R C0402

C

1

B

C408 27pF/50V,NPO C0402

2

Y5 14.318180MHz XS2 CLK_XTAL_OUT

+V3.3S CLK_ICH14

C410

R675 10K

R0402

CLK_USB48

C411

MPCIE_CLKREQ R646 10K

R0402

PCI_CLK_DEBUG C412

BUS FREQUENCE SELECT MCH_CLKREQ

+V1.05S

R641 56 R0402

7

CPU_BSEL0

7

CPU_BSEL1

7

CPU_BSEL2

R650 1K R0402 ns

R649 1K R0402 ns

C409 0.1UF/25V,Y5V C0402

TME +V3.3S

R642 0

R0402 ns

CLK_BSEL0

R670 1K

R0402

R651 0

R0402 ns

CLK_BSEL1

R671 1K

R0402

R652 0

R0402 ns

CLK_BSEL2

R672 1K

R0402

R645 1K R0402 ns

A

R653 0 R0402

R655 0 R0402

FSC FSB BSEL2 BSEL1

0 1 5

MCH_BSEL0

10

MCH_BSEL1

10

MCH_BSEL2

10

FSA HOST Clock BSEL0 frequency

0

1

0

1 4

R648 10K

R0402

PCI_CLK_EC

C413

PCI_CLK_ICH

C414

10PF/50V,NPO C0402 10PF/50V,NPO C0402 10PF/50V,NPO C0402 10PF/50V,NPO C0402 10PF/50V,NPO C0402

ns ns ns ns ns

0:Normal mode 1:No Overclocking

R647 10K R0402 27M_SEL

A

TOPSTAR TECHNOLOGY Swain Xu R654 10K R0402 ns

133MHz

Page Name

CK505M

Size A3

A

Project Name

Rev A

of Date: Wednesday, July 16, 2008 Sheet 6 42 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

100MHz 3

2

1

3

+V1.05S +V3.3S

2

+V1.05S

6,8,9,11,12,17,20,28,35,36,37

+V3.3S

6,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39 9

U22A

9

H_A#[31:3]

9

H_ADSTB#1 17 17 17 17 17 17 17

T14

ICTP

H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# R74 1K,1% R0402 ns

R75 1K,1% R0402 ns

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# AP1

U18 T16 J4 R16 T15 R15 U17

A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI#

D6 G6 H6 K4 K5 M15 L16

NC1 NC2 NC3 NC4 NC5 NC6 NC7

9 9 9

DEFER# DRDY# DBSY#

T21 T19 Y18

H_DEFER# H_DRDY# H_DBSY#

9 9 9

BR0#

T20

IERR# INIT#

F16 V16

LOCK#

W20

RESET# RS[0]# RS[1]# RS[2]# TRDY#

D15 W18 Y17 U20 W19

HIT# HITM#

H_BREQ#0 R65

H_IERR# 1K,1%

AA17 V20

H_BPM#0 H_BPM#1 H_BPM#2 H_BPM#3 H_BPM#4 H_BPM#5 H_TCK H_TDI H_TDO H_TMS H_TRST# H_DBR# R674 0

PROCHOT# THRMDA THRMDC

G17 E4 E5

R104 22 H_THERMDA H_THERMDC

THERMTRIP#

H17

BCLK[0] BCLK[1]

V11 V12

RSVD3 RSVD2 RSVD1

C21 C1 A3

T7 T6 T8 T9 T10 T11

R63 56 R0402

9 9 9 9 9 9

H_INIT#

17

Place testpoint on H_IERR# with a GND 0.1" away

9 9 9

H_DSTBN#0 H_DSTBP#0 H_DINV#0

9

H_D#[63:0]

T4

9 9

+V1.05S

R0402

PM_SYSRST#

19

VR_PROCHOT# R66 1K,1% R0402

9 Layout Note: Z=55ohm, 9 9 0.5" max for GTLREF

Y11 W10 Y12 AA14 AA11 W12 AA16 Y10 Y9 Y13 W15 AA13 Y16 W13 AA9 W9 Y14 Y15 W16 V9

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# DP#0

AA5 Y8 W3 U1 W7 W6 Y7 AA6 Y3 W2 V3 U2 T3 AA8 V2 W4 Y4 Y5 Y6 ICTP R4

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# DP#1

ICTP H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

ICTP ICTP ICTP ICTP ICTP ICTP

R0402 ns

H_DSTBN#1 H_DSTBP#1 H_DINV#1

T12

A7 1K,1% R0402 ns ACLKPH U5 1K,1% R0402 ns DCLKPH V5 T15 ICTP T17 T16 ICTP R6 EXTBGREF M6 T17 ICTP N15 T18 ICTP N6 T20 ICTP P17 T19 ICTP T6 J6 CPU_BSEL0 H5 CPU_BSEL1 G5 CPU_BSEL2

PM_THRMTRIP# 10,17,28

GTLREF ACLKPH DCLKPH BINIT# MISC EDM EXTBGREF FORCEPR# HFPLL MCERR# RSP# BSEL[0] BSEL[1] BSEL[2]

R67 R69 R71 2K,1% R0402

CLK_CPU_BCLK 6 CLK_CPU_BCLK# 6

C19 0.1uF/10V,X5R C0402

6 6 6

+V1.05S

1

U22B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

R64 330 R0402

R0402

H_HIT# H_HITM#

K17 J18 H15 J15 K18 J16 M17 N16 M16 L17 K16 V15

H_D#[63:0]

+V1.05S

9

H_LOCK# T3 ICTP H_CPURST# H_RS#0 H_RS#1 H_RS#2 H_TRDY#

BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# BR1#

ADDR GROUP 1

C

C19 F19 E21 A16 D19 C14 C18 C20 E20 D20 B18 C15 B16 B17 C16 A17 B14 B15 A14 B19 M18

ADS# BNR# BPRI#

ICTP T1 H_ADS# H_BNR# H_BPRI#

DATA GRP 1

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

CONTROL

T2 ICTP H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

XDP/ITP SIGNALS

H_ADSTB#0 H_REQ#[4:0]

THERM

9 9

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# AP0 REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

V19 Y19 U21

DATA GRP 0

D

P21 H20 N20 R20 J19 N19 G20 M19 H21 L20 M20 K19 J20 L21 K20 D17 N21 J21 G19 P20 R19

ADDR GROUP 0

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H CLK

H_A#[31:3]

NC

9

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# DP#2

R3 R2 P1 N1 M2 P2 J3 N3 G3 H2 N2 L2 M3 J2 H1 J1 K2 K3 L1 M4

D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# DP#3

C2 G2 F1 D3 B4 E1 A5 C3 A6 F2 C6 B6 B3 C4 C7 D2 E2 F3 C5 D4

DATA GRP 2

4

DATA GRP 3

5

COMP[0] COMP[1] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# CORE_DET CMREF[1]

R76 1K,1% R0402

ICTP

R0402 R0402 R0402 R0402

H_TDO H_BPM#5 H_TMS H_TDI

R90 R92 R91 R93

1K,1% 1K,1% 1K,1% 1K,1%

R0402 R0402 R0402 R0402

ns ns ns ns

H_NMI H_SMI# H_INTR H_STPCLK#

R99 R96 R95

1K,1% 1K,1% 1K,1%

R0402 ns R0402 ns R0402 ns

H_DPSLP# H_DPRSTP# H_PWRGD

R80 R83

56 56

R0402 R0402

For defensive design reservation only in this initial release

T1 T2 F20 F21

R18 R17 U4 V17 N18 A13 CPU_CMREF B7

C22 2200pF/25V,X7R C0402

R97 1K,1% R0402 ns

H_THERMDC

2

DXP

SMBCLK

8

3

DXN SMBDATA G781 ADM1032AR ALERT# LM86CIM MAX6657MSA THERM# SOIC-8

7

GND

2 R103 56 R0402

Q4 R147 MMBT3904-F 1K SOT23 R0402 1

H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGD H_CPUSLP# T21ICTP

Layout note: Comp0,2 connec with Zo=27.4ohm,make trace length shorter than 0.5" Comp1,3 connec with Zo=55ohm,make trace length shorter than 0.5"

17 17 9 17 9,17

Layout Note: Zo=55ohm, 0.5" max for GTLREF B

R85 2K,1% R0402

+V3.3S

C21 0.1uF/10V,X5R C0402

U4 F75383S SO8_50_150

EC SMBUS ADD:1001 100X

6 4

+V1.05S

29

I2C_DATA

29

OVT_SHUTDOWN# 28

R100 10K R0402

R101 10K R0402

C24 27pF/50V,NPO C0402

C25 27pF/50V,NPO C0402

A

TOPSTAR TECHNOLOGY Swain Xu Page Name

1.H_THERMDA/C线宽10 MILS,并配对走线, 然后再包地处理.

Size A3

+V3.3S

2.H_THERMDA/C走线远离19V及VGA或高速线走线

3

Project Name

Diamondville(1of2)(Host BUS) Rev A

A

Date: Wednesday, July 16, 2008 Sheet 7 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

VR_PROCHOT#

4

I2C_CLK

THERM#

NOTE

3

3 2

R0402 R0402 R0402 R0402

CPU_CMREF

H_THERMDA

+V1.05S

5

27.4,1% 54.9,1% 27.4,1% 54.9,1%

C23 0.1uF/10V,X5R C0402

R94 1K,1% R0402 ns H_DPWR#

EC_PROCHOT# 29

1

R68 R70 R72 R73

R77 1K,1% R0402

R89 220 R0402

A

+V1.05S

9

C

COMP0 COMP1 COMP2 COMP3

H_TCK H_TRST#

R98 330 R0402

Q1 MMBT3904-F SOT23

H_D#[63:0]

H_DSTBN#3 9 H_DSTBP#3 9 H_DINV#3 9 T13ICTP

C20 0.1uF/10V,X5R C0402

+V1.05S

+V3.3S

R102 1K R0402

T5

1

56 56 56 56

R78 2K,1% R0402

VCC

R150 R87 R86 R88

H_DSTBN#2 9 H_DSTBP#2 9 H_DINV#2 9

+V1.05S

Layout Note: Z=55ohm, 0.5" max for GTLREF

5

H_A#32 H_A#33 H_A#34 H_A#35

H_DSTBN#/H_DSTBP# should route as differential pair

EXTBGREF

Diamondville

R0402 R0402 R0402 R0402

D

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

+V1.05S B

1K,1% 1K,1% 1K,1% 1K,1%

9

Diamondville

+V1.05S

R79 R82 R81 R84

H_D#[63:0]

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

2

1

5

4

3

2

1

+VCC_CORE 36,39

U22D

C

B

N5 N7 N9 N13 N17 P3 P4 P5 P6 P7 P9 P13 P15 P16 P18 P19 R1 R5 R7 R9 R13 R21 T4 T5 T7 T9 T10 T11 T12 T13 T18 U3 U6 U7 U15 U16 U19 V1 V4 V6 V7 V8 V13 V14 V18 V21 W1 W5 W8 W11 W14 W17 W21 Y1 Y2 Y20 Y21 AA2 AA3 AA4 AA7 AA10 AA12 AA15 AA18 AA19 AA20

U22C

A9 B9

VCCF VCCQ1 VCCQ2

+VCC_CORE

A10 A11 A12 B10 B11 B12 C10 C11 C12 D10 D11 D12 E10 E11 E12 F10 F11 F12 G10 G11 G12 H10 H11 H12 J10 J11 J12 K10 K11 K12 L10 L11 L12 M10 M11 M12 N10 N11 N12 P10 P11 P12 R10 R11 R12

VCCP1 VCCP2 VCCP3 VCCP4 VCCP5 VCCP6 VCCP7 VCCP8 VCCP9 VCCP10 VCCP11 VCCP12 VCCP13 VCCP14 VCCP15 VCCP16 VCCP17 VCCP18 VCCP19 VCCP20 VCCP21 VCCP22 VCCP23 VCCP24 VCCP25 VCCP26 VCCP27 VCCP28 VCCP29 VCCP30 VCCP31 VCCP32 VCCP33 VCCP34 VCCP35 VCCP36 VCCP37 VCCP38 VCCP39 VCCP40 VCCP41 VCCP42 VCCP43 VCCP44 VCCP45

10,11,12,20,23,24,35,36,37

+V1.05S

6,7,9,11,12,17,20,28,35,36,37

+V1.05S

+V1.05S

V10

+V1.5S

VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32

C9 D9 E9 F8 F9 G8 G14 H8 H14 J8 J14 K8 K14 L8 L14 M8 M14 N8 N14 P8 P14 R8 R14 T8 T14 U8 U9 U10 U11 U12 U13 U14

VCCPC64 VCCPC63 VCCPC62 VCCPC61

F14 F13 E14 E13

C26 0.1uF/10V,X7R C0402

C27 0.1uF/10V,X7R C0402

C28 0.1uF/10V,X7R C0402 ns

C29 0.1uF/10V,X5R C0402

C30 0.1uF/10V,X5R C0402 ns

C31 0.1uF/10V,X5R C0402

C32 10uF/6.3V,X5R C0805

C33 10uF/6.3V,X5R C0805 ns

1

VSS162 VSS161 VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131 VSS130 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100 VSS99 VSS98 VSS97 VSS96 VSS95

2

D

VSS1 VSS2 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS41 VSS42 VSS45 VSS46 VSS48 VSS49 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84

1

A2 A4 A8 A15 A18 A19 A20 B1 B2 B5 B8 B13 B20 B21 C8 C17 D1 D5 D8 D14 D18 D21 E3 E6 E7 E8 E15 E16 E19 F4 F5 F6 F7 F17 F18 G1 G4 G7 G9 G13 G21 H3 H4 H7 H9 H13 H16 H18 H19 J5 J7 J9 J13 J17 K1 K6 K7 K9 K13 K15 K21 L3 L4 L5 L6 L7 L9 L13 L15 L18 L19 M1 M5 M7 M9 M13 M21 N4

+ C34 220uF/2.5V,POSCAP CT7343_19 ns

D

C

+V1.5S

C35 0.1uF/10V,X5R C0402

C36 10uF/6.3V,X5R C0805 ns

Place near PIN D7

VCCA

D7

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

F15 D16 E18 G15 G16 E17 G18

VCCSENSE

C13

VSSSENSE

D13

+VCC_CORE

R106 100,1% R0402

Layout Note: VCCSENSE and VSSSENSE lines should be of equal length

Diamondville

B

R107 100,1% R0402

Route VCCSENSE and VSSSENSE traces at 27.4 Ohms with 50 mil spacing

Diamondville

+VCC_CORE

A

C37

C38

C39

C40

C41

C42

C43

C44

C45

C46

C47

C48

C49

C50

C51

C52

0.1uF/10V,X5R C0402

0.1uF/10V,X5R C0402

0.1uF/10V,X5R C0402

0.1uF/10V,X5R C0402

0.1uF/10V,X5R C0402

0.1uF/10V,X5R C0402

0.1uF/10V,X5R C0402

0.1uF/10V,X5R C0402

0.1uF/10V,X5R C0402

0.1uF/10V,X5R C0402

0.1uF/10V,X5R C0402

0.1uF/10V,X5R C0402

0.1uF/10V,X5R C0402

0.1uF/10V,X5R C0402

0.1uF/10V,X5R C0402

0.1uF/10V,X5R C0402

A

+VCC_CORE

TOPSTAR TECHNOLOGY Swain Xu Page Name

C53

C54

C55

C56

C57

C58

C59

C60

C61

C62

10uF/6.3V,X5R C0805

10uF/6.3V,X5R C0805

10uF/6.3V,X5R C0805

10uF/6.3V,X5R C0805

10uF/6.3V,X5R C0805

10uF/6.3V,X5R C0805

10uF/6.3V,X5R C0805

10uF/6.3V,X5R C0805

10uF/6.3V,X5R C0805

10uF/6.3V,X5R C0805

C64 C63 10uF/6.3V,X5R 10uF/6.3V,X5R C0805 C0805

Size A3

Project Name

Diamondville (PWR&GND)(2of2) Rev A

N01

of Date: Wednesday, July 16, 2008 Sheet 8 42 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

+V1.05S

+V1.05S

6,7,8,11,12,17,20,28,35,36,37

+V1.05S D

D

H_XSWING

R109 100,1% R0402

Trace should be 10mil wide with 20mil spacing!

C65 0.1uF/10V,X5R C0402

+V1.05S

R110 221,1% R0603

C

H_YSWING

R111 100,1% R0402

Trace should be 10mil wide with 20mil spacing!

C66 0.1uF/10V,X5R C0402

+V1.05S

R114 54.9,1% R0402

R115 54.9,1% R0402

B

H_XSCOMP H_YSCOMP

H_XRCOMP

H_D#[63:0]

U23A H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

C4 F6 H9 H6 F7 E3 C2 C3 K9 F5 J7 K7 H8 E5 K8 J8 J2 J3 N1 M5 K5 J5 H3 J4 N3 M4 M3 N8 N6 K3 N9 M1 V8 V9 R6 T8 R2 N5 N2 R5 U7 R8 T4 T7 R3 T5 V6 V3 W2 W1 V2 W4 W7 W5 V5 AB4 AB8 W8 AA9 AA8 AB1 AB7 AA2 AB5

HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#

HOST

7 R108 221,1% R0603

H_YRCOMP

R116 24.9,1% R0402

R117 24.9,1% R0402

H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING

Trace should be 10mil wide with 20mil spacing!

A10 A6 C15 J1 K1 H1

HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWING

H_A#[31:3]

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#

F8 D12 C13 A8 E13 E12 J12 B13 A13 G13 A12 D14 F14 J13 E17 H15 G15 G14 A15 B18 B15 E14 H13 C14 A17 E15 H17 D17 G17

HADS# HADSTB0# HADSTB1# H_AVREF HBNR# HBPRI# HBREQ0# HCPURST# HDVREF

F10 C12 H16 E2 B9 C7 G8 B10 E1

H_ADS# 7 H_ADSTB#0 7 H_ADSTB#1 7

HCLKN HCLKP HDBSY# HDEFER# HDINV0# HDINV1# HDINV2# HDINV3# HDPWR# HDRDY# HDSTBN0# HDSTBN1# HDSTBN2# HDSTBN3# HDSTBP0# HDSTBP1# HDSTBP2# HDSTBP3#

AA6 AA5 C10 C6 H5 J6 T9 U6 G7 E6 F3 M8 T1 AA3 F4 M7 T2 AB3

CLK_MCH_BCLK# 6 CLK_MCH_BCLK 6 H_DBSY# 7 H_DEFER# 7 H_DINV#0 7 H_DINV#1 7 H_DINV#2 7 H_DINV#3 7 H_DPWR# 7 H_DRDY# 7 H_DSTBN#0 7 H_DSTBN#1 7 H_DSTBN#2 7 H_DSTBN#3 7 H_DSTBP#0 7 H_DSTBP#1 7 H_DSTBP#2 7 H_DSTBP#3 7

HHIT# HHITM# HLOCK# HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HRS0# HRS1# HRS2# HCPUSLP# HTRDY#

C8 B4 C5 G9 E9 G12 B8 F12 A5 B6 G10 E8 E10

7

C

+V1.05S

R112 100,1% R0402

H_BNR# 7 H_BPRI# 7 H_BREQ#0 7 H_CPURST# 7

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_HIT# H_HITM# H_LOCK#

H_RS#0 H_RS#1 H_RS#2 H_CPUSLP# H_TRDY#

C67 0.1uF/10V,X5R C0402

C68 0.1uF/10V,X5R C0402 ns

R113 200,1% R0402

Place close to PIN-E1/E2

B

7 7 7

H_REQ#[4:0]

7

7 7 7 7,17 7

945GMS

A

A

TOPSTAR TECHNOLOGY Swain Xu Page Name

Calistoga(HOST)

Size A3

N01

Project Name

Rev A

Date: Wednesday, July 16, 2008 Sheet 9 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

+V3.3S

6,7,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39

+V1.5S_PCIE 12

+V1.8

+V1.5S

8,11,12,20,23,24,35,36,37

+V1.8

12,14,34,36,37

+V1.5S_PCIE

U23F U23B

SM_CK0# SM_CK1#

AK1 AN30

SM_CK2# SM_CK3# SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3

14 14

M_CS#0 M_CS#1

AG14 AF12 AK14 AH12

SM_CS0# SM_CS1# SM_CS2# SM_CS3#

AJ21 AF11

SMOCDCOMP0 SMOCDCOMP1

AE12 AF14 AJ14 AJ12

SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3

AN12 AN14 AA33 AE1

SMRCOMPN SMRCOMPP SMVREF0 SMVREF1

M_ODT0 M_ODT1

2

M_RCOMPN M_RCOMPP

C70 0.1uF/10V,X5R C0402

C71 0.1uF/10V,X5R C0402

R131 2.2K R0402

H20 H22 A24 A23 E25 F25 C25 D25 F27 D27 H25

DDCCLK DDCDATA BLUE BLUE# GREEN GREEN# RED RED# VSYNC HSYNC REFSET

H30 G29 F28 E28 G28 H28 K30 K27 J29 J30 K29

LBKLT_CTRL LBKLT_EN LCTLA_CLK LCTLB_CLK LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL

D30 C30 A30 A29

LACLKN LACLKP LBCLKN LBCLKP

15 MCH_LVDS_YAN0 15 MCH_LVDS_YAN1 15 MCH_LVDS_YAN2

G31 F32 D31

LADATAN0 LADATAN1 LADATAN2

15 MCH_LVDS_YAP0 15 MCH_LVDS_YAP1 15 MCH_LVDS_YAP2

H31 G32 C31

LADATAP0 LADATAP1 LADATAP2

F33 D33 F30

LBDATAN0 LBDATAN1 LBDATAN2

E33 D32 F29

LBDATAP0 LBDATAP1 LBDATAP2

16 CRT_DDC_CLK 16 CRT_DDC_DATA 16 CRT_BLUE

R132 2.2K R0402 ns

16

K32 K31 C17 F18 A3

16 16 16

CRT_GREEN CRT_RED R125 39 R0402 R120 39 R0402 R121 255,1%R0603

CRT_VSYNC CRT_HSYNC

15 LVDS_BKLTCTL 15,29 LVDS_BKLTEN

15

LVDS_VDDEN

LCTLA_CLK LCTLB_DATA L_DDC_CLK L_DDC_DATA R122 1.5K,1% R0402

15 MCH_LVDS_CLKAN 15 MCH_LVDS_CLKAP

ICHSYNC# BM_BUSY# EXT_TS0# EXT_TS1#/DPRSLPVR THRMTRIP# PWROK RSTIN#

DREF_CLKN DREF_CLKP DREF_SSCLKN DREF_SSCLKP CLKREQB

E31 G21 F26 H26 J15 AB29 W27

MISC

6 CLK_MCH_3GPLL# 6 CLK_MCH_3GPLL

SDVOCTRL_DATA SDVOCTRL_CLK GCLKN GCLKP

R_PM_EXTTS#0 PM_EXTTS#1 R141 100 R0402

A27 A26 J33 H33 J22

MCH_ICH_SYNC# 18 PM_BMBUSY# 19 PM_THRMTRIP# 7,17,28 IMVP_PWRGD 19,29,39 BUF_PLT_RST# 18,19,23,24,29,30

DREFCLK# 6 DREFCLK 6 DREFSSCLK# 6 DREFSSCLK 6 MCH_CLKREQ# 6

EXP_COMPI EXP_ICOMPO

R28 M28

SDV0_TVCLKIN# SDVO_INT# SDVO_FLDSTALL#

N30 R30 T29

SDVO_TVCLKIN SDVO_INT SDVO_FLDSTALL

M30 P30 T30

SDVOB_RED# SDVOB_GREEN# SDVOB_BLUE# SDVOB_CLKN

P28 N32 P32 T32

SDVOB_RED SDVOB_GREEN SDVOB_BLUE SDVOB_CLKP

N28 M32 P33 R32

R123 24.9,1% R0402

C

+V1.5S

TVDAC_A TVDAC_B TVDAC_C TV_REFSET TV_IRTNA TV_IRTNB TV_IRTNC

A21 C20 E20 G23 B21 C21 D21

TV_DCONSEL0 TV_DCONSEL1

G26 J26

2

C69 2.2uF/10V,X7R C0805

H27 J27 Y26 AA26

SDVO

AG33 AF1

MCH_RSVD1 MCH_RSVD2 MCH_RSVD7 MCH_RSVD8 MCH_RSVD9

PM

1

SM_CK2 SM_CK3

AN21 AN22 AF26 AF25

R140 10K,1%

1

AJ1 AM30

M_CKE0 M_CKE1

14 14

R142 10K,1%

SM_CK0 SM_CK1

6 6 6

GMS_CFG5

R130 2.2K R0402 ns

14 14 C

+V1.8

AF33 AG1

MCH_BSEL0 MCH_BSEL1 MCH_BSEL2

TV

14 M_CLK_DDR#0 14 M_CLK_DDR#1

DMI_TXN0 DMI_TXN1 DMI_TXP0 DMI_TXP1

C18 E18 G20 G18 J20 J18

VGA

14 M_CLK_DDR0 14 M_CLK_DDR1

V28 V31 V29 V32

D

CFG0 CFG1 CFG2 CFG3 CFG5 CFG6

LVDS

DMI_RXN0 DMI_RXN1 DMI_RXP0 DMI_RXP1

DMI_RXN0 DMI_RXN1 DMI_RXP0 DMI_RXP1

CFG/RSVD

18 18 18 18

Y29 Y32 Y28 Y31

CLK

DMI_TXN0 DMI_TXN1 DMI_TXP0 DMI_TXP1

DMI

18 18 18 18

DDR2 MUXING

D

945GMS 945GMS

Close to GMCH ONE PIN, ONE CAP B

B

R733 0 R0402

SM_VREF_L 14,34 +V3.3S R118 150,1%

R0402

CRT_BLUE

R119 150,1%

R0402

CRT_GREEN

R124 150,1%

R0402

CRT_RED

+V3.3S

R126 10K R0402

+V1.8

R136 80.6,1% R0603

R133 10K R0402 ns

R134 10K R0402

150ohm电阻到GMCH 走线阻抗37.5ohm 150ohm电阻到VGA口 走线阻抗50ohm PLACE 150 OHM RESISTORS CLOSE TO GMCH

R151 10K R0402 MCH_CLKREQ#

M_RCOMPN R_PM_EXTTS#0

R138 0

R0402

PM_EXTTS#1

R139 0

R0402

PM_EXTTS#0

14

M_RCOMPP

R127 10K R0402

R128 10K R0402

R129 10K R0402

LCTLA_CLK LCTLB_DATA 15

L_DDC_CLK

15

L_DDC_DATA

PM_DPRSLPVR 19

R137 80.6,1% R0603 A

A

TOPSTAR TECHNOLOGY Swain Xu Page Name

Calistoga(Graphic)

Size A3

N01

Project Name

Rev

A

Date: Wednesday, July 16, 2008 Sheet 10 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

+V1.05S

6,7,8,9,12,17,20,28,35,36,37

+V1.5S

8,10,12,20,23,24,35,36,37

+V3.3S

6,7,10,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39

+V1.05S

+V1.5S U23H

U23C 14 MA_DATA[63:0]

C

B

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

AC31 AB28 AE33 AF32 AC33 AB32 AB31 AE31 AH31 AK31 AL28 AK27 AH30 AL32 AJ28 AJ27 AH32 AF31 AH27 AF28 AJ32 AG31 AG28 AG27 AN27 AM26 AJ26 AJ25 AL27 AN26 AH25 AG26 AM12 AL11 AH9 AK9 AM11 AK11 AM8 AK8 AG9 AF9 AF8 AK6 AF7 AG11 AJ6 AH6 AN6 AM6 AK3 AL2 AM5 AL5 AJ3 AJ2 AG2 AF3 AE7 AF6 AH5 AG3 AG5 AF5

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

AG19 AG21 AG20

SB_CAS# SB_RAS# SB_WE#

DDR2 SYSTEM MEMORY

D

SA_BS_0 SA_BS_1 SA_BS_2

AK12 AH11 AG17

SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7

AB30 AL31 AF30 AK26 AL9 AG7 AK5 AH3

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

AC28 AJ30 AK33 AL25 AN9 AH8 AM2 AE3

MA_DQS0 MA_DQS1 MA_DQS2 MA_DQS3 MA_DQS4 MA_DQS5 MA_DQS6 MA_DQS7

SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#

AC29 AK30 AJ33 AM25 AN8 AJ8 AM3 AE2

MA_DQS#0 MA_DQS#1 MA_DQS#2 MA_DQS#3 MA_DQS#4 MA_DQS#5 MA_DQS#6 MA_DQS#7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13

AJ15 AM17 AM15 AH15 AK15 AN15 AJ18 AF19 AN17 AL17 AG16 AL18 AG18 AL14

MA_A_A0 MA_A_A1 MA_A_A2 MA_A_A3 MA_A_A4 MA_A_A5 MA_A_A6 MA_A_A7 MA_A_A8 MA_A_A9 MA_A_A10 MA_A_A11 MA_A_A12 MA_A_A13

SA_CAS# SA_RAS# SA_RCVENINB SA_RCVENOUTB SA_WEB

AJ17 AK18 AN28 AM28 AH17

TP_MA_RCVENIN# TP_MA_RCVENOUT#

SB_BS_0 SB_BS_1 SB_BS_2

AH21 AJ20 AE27

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13

AN20 AL21 AK21 AK22 AL22 AH22 AG22 AF21 AM21 AE21 AL20 AE22 AE26 AE20

MA_A_BS#0 MA_A_BS#1 MA_A_BS#2 MA_DM[7:0]

14 14 14 14

MA_DQS[7:0] 14

MA_DQS#[7:0] 14

MA_A_A[13:0]

14

MA_A_CAS# 14 MA_A_RAS# 14 T23 ICTP ns T22 ICTP ns MA_A_WE# 14

T25 R25 P25 N25 M25 P24 N24 M24 Y22 W22 V22 U22 T22 R22 P22 N22 M22 Y21 W21 V21 U21 T21 R21 P21 N21 M21 Y20 W20 V20 U20 T20 R20 P20 N20 M20 Y19 P19 N19 M19 Y18 P18 N18 M18 Y17 P17 N17 M17 Y16 P16 N16 M16 Y15 P15 N15 M15 Y14 W14 V14 U14 T14 R14 P14 N14 M14

VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64

T10 R10 P10 N10 L10 D1

VTT_NCTF1 VTT_NCTF2 VTT_NCTF3 VTT_NCTF4 VTT_NCTF5 VTT_NCTF6

M10 A18 AB10 AA10

945GMS

NCTF

MCH_RSVD3 MCH_RSVD4 MCH_RSVD5 MCH_RSVD6

VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8 VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12 VSS_NCTF13 VSS_NCTF14 VSS_NCTF15 VSS_NCTF16 VSS_NCTF17 VSS_NCTF18 VSS_NCTF19

AD25 AC25 AB25 AD24 AC24 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 K14 AD13 Y13 W13 V13 U13 T13 R13 P13 N13 M13 AD12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 AD11 AD10 K10 AN33 AA25 V25 U25 AA22 AA21 AA20 AA19 AA18 AA17 AA16 AA15 AA14 AA13 A4 A33 B2 AN1 C1

CFG19

K28

MCH_RSVD10 MCH_RSVD11 MCH_RSVD12 MCH_RSVD13 MCH_RSVD14 MCH_RSVD15 MCH_RSVD16 MCH_RSVD17 MCH_RSVD18 MCH_RSVD19 MCH_RSVD20 MCH_RSVD21 MCH_RSVD22 MCH_RSVD23 MCH_RSVD24 MCH_RSVD25

K25 K26 R24 T24 K21 K19 K20 K24 K22 J17 K23 K17 K12 K13 K16 K15

945GMS

D

C

+V3.3S

R143 1K R0402 ns GMS_CFG19

B

LOW=Normal High=LANES REVERSED(945GMS no support.

A

A

TOPSTAR TECHNOLOGY Swain Xu Page Name Size A3

Project Name

Calisoga(DDRII&NCTF) Rev A

N01

of Date: Wednesday, July 16, 2008 Sheet 11 42 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

+V1.05S

+V3.3S

6,7,10,11,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39

+V1.05S

6,7,8,9,11,17,20,28,35,36,37

+V1.5S

8,10,11,20,23,24,35,36,37

3A C73 10uF/6.3V,X5R C0805

D

C77 10uF/6.3V,X5R C0805

C81 0.1uF/10V,X5R C0402

C78 4.7uF/10V,X5R C0805

C82 0.1uF/10V,X5R C0402

C522 10uF/6.3V,X5R T26 C0805 R26 P26 N26 M26 V19 U19 C74 T19 1uF/10V,X7R W18 C0603 V18 T18 R18 W17 U17 R17 C75 W16 0.1uF/10V,X5R V16 C0402 T16 R16 V15 U15 T15

+V1.5S C

TBD C85 0.1uF/10V,X5R C0402

C97 0.47uF/25V,Y5V C0603 +V1.05S

780mA C477 4.7uF/10V,X5R C0805

C478 4.7uF/10V,X5R C0805

B

C276 10uF/6.3V,X5R C0805

C103 0.47uF/25V,Y5V C0603

A

AD33 AD32 AD31 AD30 AD29 AD28 AD27 AC27 AD26 AC26 AB26 AE19 AE18 AF17 AE17 AF16 AE16 AF15 AE15 J14 J10 H10 AE9 AD9 U9 AD8 AD7 AD6 A14 D10 P9 L9 D9 P8 L8 D8 P7 L7 D7 A7 P6 L6 G6 D6 U5 P5 L5 G5 D5 Y4 U4 P4 L4 G4 D4 Y3 U3 P3 L3 G3 D3 Y2 U2 P2 L2 G2 D2 AA1 F1

+V1.5S

U23D

VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC_AUX1 VCC_AUX2 VCC_AUX3 VCC_AUX4 VCC_AUX5 VCC_AUX6 VCC_AUX7 VCC_AUX8 VCC_AUX9 VCC_AUX10 VCC_AUX11 VCC_AUX12 VCC_AUX13 VCC_AUX14 VCC_AUX15 VCC_AUX16 VCC_AUX17 VCC_AUX18 VCC_AUX19 VCC_AUX20 VCC_AUX21 VCC_AUX22 VCC_AUX23 VCC_AUX24 VCC_AUX25 VCC_AUX26 VCC_AUX27 VCC_AUX28 VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32 VTT33 VTT34 VTT36 VTT35 VTT37 VTT38 VTT39 VTT40

POWER

C520 10uF/6.3V,X5R C0805

VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1 VCCA_TVBG VSSA_TVBG VCCD_TVDAC VCCDQ_TVDAC VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2 VCCHV0 VCCHV1 VCCHV2 VCCSM0 VCCSM1 VCCSM2 VCCSM3 VCCSM4 VCCSM5 VCCSM6 VCCSM7 VCCSM8 VCCSM9 VCCSM10 VCCSM11 VCCSM12 VCCSM13 VCCSM14 VCCSM15 VCCSM16 VCCSM17 VCCSM18 VCCSM19 VCCSM20 VCCSM21 VCCSM22 VCCSM23 VCCSM24 VCCSM25 VCCSM26 VCCSM27 VCCSM28 VCCSM29 VCCSM30 VCCSM31 VCCSM32 VCCSM33 VCCSM34 VCCSM35 VCCSM36 VCCSM37 VCCSM38 VCCSM39 VCCSM40 VCCSM41 VCCSM42 VCCSM43 VCCSM44 VCCSM45 VCCSM46 VCCSM47 VCCSM48 VCCSM49 VCCSM50 VCCSM51 VCCA_MPLL VCCA_HPLL VCCA_DPLLA VCCA_DPLLB VCCD_HMPLL1 VCCD_HMPLL2 VCCTX_LVDS0 VCCTX_LVDS1 VCC3G0 VCC3G1 VCCA_3GPLL VCCA_3GBG VSSA_3GBG VCC_SYNC VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC VCCA_LVDS VSSALVDS VTT41 VTT42 VTT43 VTT44 VTT45

B20 A20 B22 A22 D22 C22 D23 E23 F20 F22 C28 B28 A28 E26 D26 C26 AB33 AM32 AN29 AM29 AL29 AK29 AJ29 AH29 AG29 AF29 AE29 AN24 AM24 AL24 AK24 AJ24 AH24 AG24 AF24 AE24 AN18 AN16 AM16 AL16 AK16 AJ16 AN13 AM13 AL13 AK13 AJ13 AH13 AG13 AF13 AE13 AN4 AM10 AL10 AK10 AH1 AH10 AG10 AF10 AE10 AN7 AM7 AL7 AK7 AJ7 AH7 AN10 AJ10 AD1 AD2 B26 J32 AE5 AD5 D29 C29 U33 T33 V26 N33 M33 J23 C24 B24 B25 B31 B32

+V1.5S_PCIE 10

120mA

+V2.5S

37,38

+V1.8

10,14,34,36,37 D

+V1.5S

20mA

FB8 100ohm@100MHz,3A FB0805 1 2

+V1.5S C79 0.1uF/10V,X5R C0402

C80 10uF/6.3V,X5R C0805

+V1.5S_DPLLA

50mA

C84 10uF/6.3V,X5R C0805

40mA

C86 0.1uF/10V,X5R C0402

+V3.3S

C529 1uF/10V,X7R C0603

C76 0.1uF/10V,X5R C530 C0402 1uF/10V,X7R C0603

FB10 100ohm@100MHz,3A FB0805 1 2

C83 10uF/6.3V,X5R C0805

+V1.5S_DPLLB

50mA

C88 10uF/6.3V,X5R C0805

C521 10uF/6.3V,X5R C0805

C89 0.1uF/10V,X5R C0402 +V1.5S_MPLL

1

45mA

2

C

C87 1uF/10V,X7R C0603

FB3 100ohm@100MHz,3A FB0805

C95 10uF/6.3V,X5R C0805

C96 0.1uF/10V,X5R C0402

+V1.8

+V1.5S_HPLL

1 C90 1uF/10V,X7R C0603

C91 4.7uF/10V,Y5V C0805

C92 4.7uF/10V,Y5V C0805

45mA

2 FB4 100ohm@100MHz,3A FB0805

C93 10uF/6.3V,X5R C0805

C98 1uF/10V,X7R C0603

C99 10uF/6.3V,X5R C0805

FB5 100ohm@100MHz,3A FB0805 1 2

+V1.5S

C102 1uF/10V,X7R C0603

C100 10uF/6.3V,X5R C0805

+V1.5S_PCIE

400mA

C156 10uF/6.3V,X5R C0805

C105 10uF/6.3V,X5R C0805

C120 0.47uF/25V,Y5V C0603

945GMS

C106 10uF/6.3V,X5R C0805

+V1.5S_3GPLL +V1.5S_MPLL

1

+V1.5S_HPLL +V1.5S_DPLLA

400mA

2

B

FB6 100ohm@100MHz,3A FB0805

+V1.5S_DPLLB +V2.5S

45mA

45mA

400mA

50mA

+V1.5S

50mA 150mA 60mA

+V2.5S C107 0.1uF/10V,X5R C0402

C108 4.7uF/10V,Y5V C0805 +V1.5S_3GPLL

D1 1N4148WS SOD323 R144 10

R0402

+V2.5S_CRTDAC

1 +V1.5S_PCIE

400mA

C109 0.1uF/10V,X5R C0402

+V1.05S

C110 10uF/6.3V,X5R C0805

70mA

2

FB7 100ohm@100MHz,3A FB0805

C111 10uF/6.3V,X5R C0805

+V2.5S

10mA +V2.5S

P1 L1 G1 U1 Y1

+V2.5S_CRTDAC

+V2.5S

10mA

70mA

70mA

C112 C113 0.01uF/25V,X7R 0.1uF/10V,X5R C0402 C0402

C114 C115 C116 C117 0.022uF/16V,X7R0.1uF/10V,X5R0.1uF/10V,X5R10uF/6.3V,X5R C0402 C0402 C0402 C0805

C118 0.1uF/10V,X5R C0402 A

TOPSTAR TECHNOLOGY Swain Xu Page Name

C119 0.47uF/25V,Y5V C0603

C101 0.1uF/10V,X5R C0402

1

C72 10uF/6.3V,X5R C0805

+V1.05S Size A3

Project Name

Calistoga(POWER) Rev A

N01

of Date: Wednesday, July 16, 2008 Sheet 12 42 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5 4

NC72 NC71 NC70 NC69 NC68 NC67 NC66 NC65 NC64 NC63 NC62 NC61

MCH_RSVD42 MCH_RSVD41 MCH_RSVD40 MCH_RSVD39 MCH_RSVD38 MCH_RSVD37 MCH_RSVD36 MCH_RSVD35 MCH_RSVD34 MCH_RSVD33 MCH_RSVD32 MCH_RSVD31 MCH_RSVD30 MCH_RSVD29 MCH_RSVD28 MCH_RSVD27 MCH_RSVD26

AM1 AE4 AG4 AH4 AJ4 W31 AK4 AL4 AD4 AF4 AM4 Y7 A16 AN2 B16 C16 D16 E16 F16 G16 Y8 A19 B19 C19 D19 E19 F19 G19 H19 J19 Y9 AN3 AH19 AJ19 AK19 AL19 AM19 AN19 C23 E21 A31 K33 D24 E24 F24 G24 W32 H24 J24 W29 V27 W28 AN31 A32 AN32 B33 C33 AL33 AM33 W33 R1 V1 F2 H2 K2 M2 AB2 AF2 AH2 AK2 B3 T3 W3 AD3 AL3 E4 H4 K4 N4 R4 V4 AA4 B5 AJ5 AN5 K6 M6 T6 W6 AB6 AE6 AG6 AL6 B7 E7 H7 N7 R7 V7 AA7 U8 AE8 AG8 AL8 A9 C9 F9 J9 M9 R9 W9 AB9 AJ9 AM9 AE11 AJ11 AN11 B12 H12 AG12 AL12 D13 F13 B14 H14 AE14 AH14 AM14 D15 F15 R15 W15 AG15 AL15 J16

C

K18 U10 V10 U24 V24 W25 W10 Y10 Y5 AL1 Y6 W30

AB17 AB12 AB13 AB15 AB18 AB20 AB24 AA24 W24 AA12 AB14 AB16 AB19 AB21 AB22 Y24 Y25

NC60 NC59 NC58 NC57 NC56 NC55 NC54 NC53 NC52 NC51 NC50 NC49 NC48 NC47 NC46 NC45 NC44 NC43 NC42 NC41 NC40 NC39 NC38 NC37 NC36 NC35 NC34 NC33 NC32 NC31 NC30 NC29 NC28 NC27 NC26 NC25 NC24 NC23 NC22 NC21 NC20 NC19 NC18 NC17 NC16 NC15 NC14 NC13 NC12 NC11 NC10 NC9 NC8 NC7 NC6 NC5 NC4 NC3 NC2 NC1 VSS185 VSS184 VSS183 VSS182 VSS181 VSS180 VSS179 VSS178 VSS177 VSS176 VSS175 VSS174 VSS173 VSS172 VSS171 VSS170 VSS169 VSS168 VSS167 VSS166 VSS165 VSS164 VSS163 VSS162 VSS161 VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS150 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131 VSS130 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111

VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100 VSS99 VSS98 VSS97 VSS96 VSS95 VSS94 VSS93 VSS92 VSS91 VSS90 VSS89 VSS88 VSS87 VSS86 VSS85 VSS84 VSS83 VSS82 VSS81 VSS80 VSS79 VSS78 VSS77 VSS76 VSS75 VSS74 VSS73 VSS72 VSS71 VSS70 VSS69 VSS68 VSS67 VSS66 VSS65 VSS64 VSS63 VSS62 VSS61 VSS60 VSS59 VSS58 VSS57 VSS56 VSS55 VSS54 VSS53 VSS52 VSS51 VSS50 VSS49 VSS48 VSS47 VSS46 VSS45 VSS44 VSS43 VSS42 VSS41 VSS40 VSS39 VSS38 VSS37 VSS36 VSS35 VSS34 VSS33 VSS32 VSS31 VSS30 VSS29 VSS28 VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1

U16 AH16 B17 F17 T17 V17 AK17 D18 H18 U18 AF18 AH18 AM18 R19 W19 D20 AF20 AH20 AK20 AM20 F21 H21 J21 E22 G22 AF22 AJ22 AM22 B23 F23 H23 A25 G25 J25 AE25 AG25 AK25 AN25 U26 W26 AH26 AL26 B27 C27 E27 G27 M27 N27 P27 R27 T27 U27 Y27 AA27 AB27 AF27 AM27 D28 J28 T28 U28 AA28 AE28 AH28 AK28 B29 E29 H29 M29 N29 P29 R29 U29 AA29 B30 E30 G30 U30 V30 Y30 AA30 AC30 AE30 AG30 AL30 F31 J31 M31 N31 P31 R31 T31 U31 AA31 AJ31 AM31 C32 E32 H32 U32 AA32 AC32 AE32 AG32 AK32 G33 R33 V33 Y33 AH33

5 4 3

3

2

2

1

D D

U23E 945GMS

VSS

C

U23G 945GMS

B B

NC

A

TOPSTAR TECHNOLOGY Swain Xu

A

Page Name Size A3 Project Name

Calistoga (VSS NC)

of Date: Wednesday, July 16, 2008 Sheet 13 42 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

N01 Rev A

1

5

4

+V1.8

3

DIM1 DDR2_SODIMM200 DDR200STD_5D2

2

1

SO-DIMM 0

+V0.9S

34,37

+V1.8

10,12,34,36,37

+V3.3S

6,7,10,11,12,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39

187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162

112 111 117 96 95 118 81 82 87 103 88 104

+V1.8

MA_A_BS#2

11 11

MA_A_BS#0 MA_A_BS#1

107 106

BA0 BA1

110 115

CS0 CS1

10 26 52 67 130 147 170 185

DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7

109 113 108

WE CAS RAS

M_CKE0 M_CKE1

79 80

CKE0 CKE1

M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1

30 32 164 166

CK0 CK0 CK1 CK1

114 119

ODT0 ODT1

13 31 51 70 131 148 169 188

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

10 10

M_CS#0 M_CS#1 MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

C

11 MA_DM[7:0] 11 11 11 10 10 10 10 10 10

10 10

MA_A_WE# MA_A_CAS# MA_A_RAS#

M_ODT0 M_ODT1 MA_DQS0 MA_DQS1 MA_DQS2 MA_DQS3 MA_DQS4 MA_DQS5 MA_DQS6 MA_DQS7

11 MA_DQS[7:0]

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2

DDRII

B

R145 R146

10K R0402 10K R0402

+V3.3S

C137 2.2UF/10V,X7R C135 C0805 0.1uF/25V,Y5V C0402

0.1uF/25V,Y5V C0402

SDA SCL

198 200

SA0 SA1

199

VDDSPD

1

10,34 SM_VREF_L

C136

195 197

C138 2.2UF/10V,X7R C0805

VREF1 NC1 NC2 NC3 NC4 NCTEST

47 133 183 77 12 48 184 78 71 72 121 122 196 193 8 18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177

close to DDR pin

83 120 50 69 163

1010 000x

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33

6,19,23,24 SMB_DATA_S 6,19,23,24 SMB_CLK_S

MA_DATA[63:0] 11

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63

5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7

11 29 49 68 129 146 167 186

MA_DQS#0 MA_DQS#1 MA_DQS#2 MA_DQS#3 MA_DQS#4 MA_DQS#5 MA_DQS#6 MA_DQS#7

C527 10uF/6.3V,X5R C0805

C121 10uF/6.3V,X5R C0805

+V1.8

C528 10uF/6.3V,X5R C0805

C123 2.2uF/10V,X7R C0805

C122 0.1uF/10V,X5R C0402

C124 2.2uF/10V,X7R C0805

D

Layout note:电容靠近DDR slot VDD PIN

C125 0.1uF/10V,X5R C0402

C126 2.2uF/10V,X7R C0805

C127 0.1uF/10V,X5R C0402

C128 2.2uF/10V,X7R C0805

C129 0.1uF/10V,X5R C0402

C131 0.1uF/10V,X5R C0402

C132 2.2uF/10V,X7R C0805

C133 0.1uF/10V,X5R C0402

C134 2.2uF/10V,X7R C0805

+V1.8

C130 2.2uF/10V,X7R C0805

C

+V0.9S RN1

56x4

1 3 5 7 RN2

56x4

1 3 5 7 RN3

56x4

1 3 5 7 RN4

56x4

1 3 5 7 RN5

56x4

1 3 5 7 R149 R148 R152 R154 R155 R157 R159

56 56 56 56 56 56 56

RA0402_8 2 4 6 8 RA0402_8 2 4 6 8 RA0402_8 2 4 6 8 RA0402_8 2 4 6 8 RA0402_8 2 4 6 8

MA_A_A6 MA_A_A11 MA_A_A7 MA_A_A12 MA_A_A9 MA_A_A8

MA_A_A13

MA_A_BS#2

11

MA_A_WE# MA_A_BS#1

11 11

MA_A_CAS#

11

MA_A_RAS#

11

M_CS#1 M_ODT1 M_CKE0 M_CKE1 MA_A_BS#0 M_ODT0 M_CS#0

10 10 10 10 11 10 10

MA_A_A3 MA_A_A1 MA_A_A10 MA_A_A5

MA_A_A0 MA_A_A2 MA_A_A4

R0402 R0402 R0402 R0402 R0402 R0402 R0402

B

MA_DQS#[7:0] 11

GND0 GND1

11

102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85

201 202

MA_A_A0 MA_A_A1 MA_A_A2 MA_A_A3 MA_A_A4 MA_A_A5 MA_A_A6 MA_A_A7 MA_A_A8 MA_A_A9 MA_A_A10 MA_A_A11 MA_A_A12 MA_A_A13

VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12

11 MA_A_A[13:0] D

10 PM_EXTTS#0

A

每4个电阻两个0.1UF电容

+V0.9S

A

TOPSTAR TECHNOLOGY Swain Xu Page Name

C139 0.1uF/10V,X5R C0402

C140 0.1uF/10V,X5R C0402

C141 0.1uF/10V,X5R C0402

C142 0.1uF/10V,X5R C0402

C144 0.1uF/10V,X5R C0402

C143 0.1uF/10V,X5R C0402

C145 0.1uF/10V,X5R C0402

C146 0.1uF/10V,X5R C0402

C147 0.1uF/10V,X5R C0402

C148 0.1uF/10V,X5R C0402

C149 0.1uF/10V,X5R C0402

C150 0.1uF/10V,X5R C0402

C151 0.1uF/10V,X5R C0402

Size A3

Project Name

DDRII SODIMM0 Rev A

N01

Date: Wednesday, July 16, 2008 Sheet 14 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

+V3.3AL +V3.3S +V5AL +VDC +V5S

High : Enable Low : Disable

2

10,29 LVDS_BKLTEN

25,29

+V3.3S

R160 100K R0402

D

2

LIDR#

2

29 HW_OFF_BKLT#

2

19,29 PM_SUS_STAT#

D2 1 1N4148WS SOD323 D3 1 1N4148WS SOD323 D4 1 1N4148WS SOD323 D5 1 1N4148WS SOD323 ns

R161 1K R0402

LCDVDD

500mA

CLOSE TO INTCON

BKLT_ON C152 1000pF/50V,X7R C0402

LCDVDD

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

10 MCH_LVDS_YAN1 10 MCH_LVDS_YAP1

EDID_PWR +V5AL_CAM

29 Q2 AO6409 TSOP6_0D95_1D6

+VDC

4 5 6

+V3.3S

BKLT_PWM BKLT_ON

IVT_I_ADJ 0

R0805

INVT_VDD C275 0.1UF/25V,Y5V C0402

41 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

500mA

41 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

MCH_LVDS_YAN0 10 MCH_LVDS_YAP0 10 MCH_LVDS_YAN2 10 MCH_LVDS_YAP2 10 L_DDC_CLK L_DDC_DATA

10 10

USB_CAM_PN5 18 USB_CAM_PP5 18 R714 0

R0805 +V5S

C

D

G

C153 0.047uF/16V,X7R C0402

FB34

LCDVDD

S

R162 100K R0402

C154 0.1uF/10V,X5R C0402

3 2 1

C

D

LCDCON 88242-4001 CNS40_LCD_R1

10 MCH_LVDS_CLKAP 10 MCH_LVDS_CLKAN

+V3.3AL

17,18,19,20,23,24,25,27,29,30,31,32,33,34,35,36,37,39 6,7,10,11,12,14,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39 20,22,25,33,34,36,37 23,25,31,33,34,35,37,39 16,19,20,21,25,26,27,29,35,37,38,39

R164 100K R0402

C155 R163 10UF/6.3V,X5R 2.2K C0805 R0402 ns

+VDC

R727 100 R0603

ns

PQ76 2N7002 ns SOT23 100pF/50V,NPO

3

3

LVDS_VDDEN 1

2

R165 100K R0402

2

1

10 LVDS_VDDEN

Q3 2N7002E-T1 SOT23

PQ75 2N7002 SOT23

2

3

ns

SPWG Require LCDVDD rising time is 0.5-10ms,1-10ms is better

R728 100K ns

1 C515 ns

R729 100K ns

+V5AL

R712 0

R0805 +V5AL_CAM

B

2

3 Q15 SOT23 AO3415 ns

1

R204 10K R0402 ns

500mA C313 0.1uF/10V,X5R C0402

C296 10UF/6.3V,X5R C0805

B

R730 10K R0402 R0402 ns

R697 0

R0402

ns

3

R696 0

BKLT_PWM R168 10K R0402

C158 100pF/50V,NPO C0402

29 CAM_PWRON

1 R213 100K R0402 ns

+V3.3AL

R699 0

R0402 ns

+V3.3S

R700 0

R0402

2

29 EC_BKLT_PWM 10 LVDS_BKLTCTL

Q16 2N7002E-T1 SOT23 ns

EDID_PWR C182 100pF/50V,NPO C0402

A

A

TOPSTAR TECHNOLOGY Swain Xu Page Name Size A3

Project Name

LVDS Rev A

N01

Date: Wednesday, July 16, 2008 Sheet 15 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

+V5S +V3.3S

Cross moat place

Cross moat place +V5S

CRT_RED

ROUT

1N5819HW-F SOD123

C162

5.6pF/50V NPO C0402

5.6pF/50V NPO C0402

D7 BAT54S SOT23

CRT_GREEN

GND_VGA R182 100K R0402

GND_VGA

6 1 7 2 8 3 9 4 10 5

GOUT

GND_VGA+V5_VGA

BOUT GOUT

3

10

FB13 GND_VGA 47ohm@100MHz,500mA 1FB0603 2

GND_VGA ROUT

2

C164

1

R172 150,1% R0402

+V5_VGA

C163 0.1uF/10V,X5R C0402

3

10

D6 1

FB12 47ohm@100MHz,500mA 1FB0603 2

D

FB11 75ohm@100MHz,500mA FB0603 2 1 2

5.6pF/50V NPO C0402

5.6pF/50V NPO C0402

D8 BAT54S SOT23

CONNECTOR TOP VIEW

GND NC

11

SDA G GND HSYNC B

12

5VDDCDA

13

HSYNC

14

VSYNC

15

5VDDCCK

R GND

NC NC VSYNC GND GND shell

CLK shell

16

C166

2

C165

1

R173 150,1% R0402

VGA

17

D

D-Sub VGADMA C167 15PF/50V,NPO C0402 ns

GND_VGA GND_VGA+V5_VGA

C

C168 15PF/50V,NPO C0402

C169 15PF/50V,NPO C0402

C170 15PF/50V,NPO C0402 ns

C

BOUT GND_VGA +V3.3S

C171

C172

5.6pF/50V NPO C0402

5.6pF/50V NPO C0402

D9 BAT54S SOT23

1

R174 150,1% R0402

2 FB14 FB0603 47ohm@100MHz,500mA

2

1

CRT_BLUE

3

10

15,19,20,21,25,26,27,29,35,37,38,39 6,7,10,11,12,14,15,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39

GND_VGA C173 0.1uF/10V,X5R C0402

GND_VGA

150ohm电阻前 走线阻抗50ohm

+V5_VGA GND_VGA GND_VGA +V3.3S

+V5_VGA

+V5_VGA R175 2.2K R0402

A

3

GND

VCC

5

Y

4

10

CRT_VSYNC

2

A

3

GND

R179 2.2K R0402

Near U11/U12 ASAP

U7

OE#

D26 BAT54S SOT23

+V5_VGA

GND_VGA

74AHCT1G125 SOT23_5

1

3 +V3.3S +V3.3S

VCC

5

Y

4

R178

39

R0402 HSYNC

R180

39

R0402 VSYNC

2

10 CRT_DDC_DATA

R177 2.2K R0402

Q6 BSS138

+V5_VGA GND_VGA 5VDDCDA

3

+V3.3S

D27 BAT54S SOT23

1

74AHCT1G125 SOT23_5 GND_VGA

+V5_VGA GND_VGA R731 0 R0805 R732 0 R0805

+V5_VGA +V5_VGA

D10

2 HSYNC

3

A

D11 C176 0.1uF/10V,X5R C0402

2 VSYNC

3

1 1 BAT54S SOT23

B

2

OE#

2

2

1

1

CRT_HSYNC

5VDDCCK

3

3

10

2

10 CRT_DDC_CLK

1

B

C175 0.1uF/10V,X5R C0402

1

C174 0.1uF/10V,X5R C0402

U6

R176 2.2K R0402

Q5 BSS138

C177 0.1uF/10V,X5R C0402 GND_VGA

Swain Xu Page Name

GND_VGA

BAT54S SOT23

A

TOPSTAR TECHNOLOGY

Size A3

GND_VGA

Project Name

CRT CONN & S TV OUT & LIDR SWITCH Rev A

N01

Wednesday, July 16, 2008 16 42 of Date: Sheet PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

+V3.3A_RTC +V3.3AL +V3.3A_RTC

1

C179 15pF/50V,NPO C0402

3 D12 BAT54C SOT23

2

ICH_INTVRMEN

CMOS Settings Clear CMOS Keep CMOS

J1 Shunt Open

+V3.3AL

15,18,19,20,23,24,25,27,29,30,31,32,33,34,35,36,37,39

+V3.3S

6,7,10,11,12,14,15,16,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39 D

2 3

1 4

R190 0 R0402 ns

R184 10M R0402

32.768KHz XS4_8038

+V3.3S

SPONGE_RTC1 RTCBAT GLUE ns

+ -

RTC_BAT1 RTCBAT with Cable ns

26 HDA_BITCLK 26 HDA_SYNC

根据机构 定Cable尺寸

+V3.3S

26

HDA_RST#

27

26

HDA_SDOUT

RTCRST#

Y5 W4

INTRUDER# INTVRMEN

W1 Y1 Y2 W3

EE_CS EE_SHCLK EE_DOUT EE_DIN

V3

LAN_CLK

U3

LAN_RSTSYNC

U5 V4 T5

LAN_RXD0 LAN_RXD1 LAN_RXD2

U7 V6 V7

LAN_TXD0 LAN_TXD1 LAN_TXD2

R0402 R0402

U1 R6

ACZ_BIT_CLK ACZ_SYNC

R195 39

R0402

R5

ACZ_RST#

T2 T3 T1

ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2

T4

ACZ_SDOUT

R206 39

R0402

AF18

SATALED#

AF3 AE3 3300pF/50V,X7R C0402AG2 3300pF/50V,X7R C0402AH2

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

AF7 AE7 AG6 AH6

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

AF1 AE1

SATA_CLKN SATA_CLKP

HDD_LED# 21 21 21 21

AA3

R193 39 R203 39

26 HDA_SDATA_IN0 R197 10K R0402

RTCX1 RTCX2

SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0

C505 C506

B

6 CLK_ICH_SATA# 6 CLK_ICH_SATA R211 24.9,1% R0402 within 500 mils of the ICH7-M

+V3.3S R194 R205

10K R0402 10K R0402

AH10 AG10

SATARBIASN SATARBIASP

AF15 AH15 AF16 AH16 AG16 AE15

DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ

LAN CPU

RTC_RST#

AB1 AB2

RTC LPC

U24A

C181 15pF/50V,NPO C0402

AC-97/AZALIA

J1 JOPEN RESISTOR_1 ns

SATA

C180 1uF/10V,X7R C0603

R185 1M R0402

1 2

SM_INTRUDER# ICH_INTVRMEN

C

6,7,8,9,11,12,20,28,35,36,37

Y2

2

1 2

R186 20K R0402

R183 1K R0402

+V1.05S

+V3.3A_RTC 20

1

RTCBAT1 CONN2_R CNS2_R ns

C178 1uF/10V,X7R C0603

4

4

3

3

D

R198 332K,1% R0402

332K 1% PULL HIGH TO VBAT_RTC FOR ICH7 INTRNAL VR ENABLE(PULL LOW DISABLE)

1

IDE

LAD0 LAD1 LAD2 LAD3

AA6 AB5 AC4 Y6

LDRQ0# LDRQ1#/GPIO23

AC3 AA5

LFRAME#

AB3

A20GATE A20M#

AE22 AH28

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME#

CPUSLP#

AG27

R199 0

R0402 ns

TP1/DPRSTP# TP2/DPSLP#

AF24 AH25

R189 0 R191 0

R0402 R0402

R187 10K R0402

23,29 23,29 23,29 23,29

+V1.05S

23,29

H_A20GATE H_A20M#

29 7

H_CPUSLP#

7,9

R200 56 R0402 ns

FERR# GPIO49/CPUPWRGD

AG24

H_PWRGD

7

IGNNE# INIT3_3V# INIT# INTR

AG22 AG21 AF22 AF25

H_IGNNE#

7

H_INIT# H_INTR

7 7 +V1.05S

H_NMI H_SMI#

7 7

H_STPCLK#

7

AG23

NMI SMI#

AH24 AF23

STPCLK#

AH22

THERMTRIP#

AF26

DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15

AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15

DA0 DA1 DA2

AH17 AE17 AF17

DCS1# DCS3#

AE16 AD16

R188 56 R0402 ns

Place near to ICH7-M

AG26

RCIN#

R196 10K R0402

H_DPRSTP# H_DPSLP#

7 7

H_FERR#

7

R201 56 R0402 R192 10K R0402 H_RCIN#

R210 24.9,1% R0402

C

+V3.3S

29

PM_THRMTRIP# 7,10,28 R209 56 R0402

+V1.05S R209 NEEDS BE PLACE WITHIN 2" OF ICH7, R210NEEDS BE PLACED WITHIN 2" OF R230 WITHOUT STUB

B

ICH7M

A

A

TOPSTAR TECHNOLOGY Swain Xu Page Name Size A3

Project Name

ICH7_M(1 of 4) Rev A

N01

of Date: Wednesday, July 16, 2008 Sheet 17 42 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

+V1.5S_PCIE_ICH

20

+V3.3S

6,7,10,11,12,14,15,16,17,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39

+V3.3AL

15,17,19,20,23,24,25,27,29,30,31,32,33,34,35,36,37,39

D

D

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

A3 B4 C5 B5 AE5 AD5 AG4 AH4 AD9

D7 E7 C16 D16 C17 D17 E13 F13 A13 A14 C8 D8

C/BE0# C/BE1# C/BE2# C/BE3#

B15 C12 D12 C15

IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME#

A7 E10 B18 A12 C9 E11 B10 F15 F14 F16

PCI_IRDY#

PLTRST# PCICLK PME#

C26 A9 B19

PLT_RST#

Interrupt I/F PIRQA# PIRQB# PIRQC# PIRQD#

GPIO2/PIRQE# GPIO3/PIRQF# GPIO4/PIRQG# GPIO5/PIRQH#

MISC RSVD[1] RSVD[2] RSVD[3] RSVD[4] RSVD[5]

PCI_REQ#0

REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3# REQ4#/GPIO22 GNT4#/GPIO48 REQ5#/GPIO1 GNT5#/GPIO17

RSVD[6] RSVD[7] RSVD[8] TP3 MCH_SYNC#

G8 F7 F8 G7

PCI_REQ#1

PCI_DEVSEL# PCI_REQ#4 PCI_REQ#3 PCI_TRDY#

RN21 10K RA0402_8 1 3 5 7

2 4 6 8

INT_PIRQB# INT_PIRQC# INT_PIRQD#

RN23 10K RA0402_8 1 3 5 7

2 4 6 8

U24D

PCI_REQ#2 PCI_REQ#3 PCI_GNT#3 PCI_REQ#4 PCI_GNT#4 PCI_REQ#5 PCI_GNT#5

BIOS strap pin

R226 1K R0402

R227 1K R0402 ns

R280 1K R0402 ns

R228 1K R0402 ns

PCI_DEVSEL# PCI_PERR# PCI_LOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#

PCI_CLK_ICH

T33

F26 F25 C184 0.1UF/10V,X7R C0402 E28 C185 0.1UF/10V,X7R C0402 E27

PERn1 PERp1 PETn1 PETp1

23 23 23 23

PCIE_RXN1_SLOT PCIE_RXP1_SLOT PCIE_TXN1_SLOT PCIE_TXP1_SLOT

H26 H25 C186 0.1UF/10V,X7R C0402G28 C187 0.1UF/10V,X7R C0402G27

PERn2 PERp2 PETn2 PETp2

24 24 24 24

PCIE_RXN2_SLOT PCIE_RXP2_SLOT PCIE_TXN2_SLOT PCIE_TXP2_SLOT

K26 K25 C225 0.1UF/10V,X7R C0402 J28 C226 0.1UF/10V,X7R C0402 J27

PERn3 PERp3 PETn3 PETp3

M26 M25 L28 L27

PERn4 PERp4 PETn4 PETp4

P26 P25 N28 N27

PERn5 PERp5 PETn5 PETp5

T25 T24 R28 R27

PERn6 PERp6 PETn6 PETp6

Place AC coupling caps need to be within 250mils of the driver.

RA0402_8 10K +V3.3S RN19 8 6 4 2

PCI_LOCK# PCI_SERR# INT_PIRQG# PCI_PERR#

7 5 3 1

INT_PIRQH# INT_PIRQE# PCI_IRDY# PCI_REQ#5

RN20 10K RA0402_8 1 3 5 7 RN24 10K RA0402_8 1 3 5 7

ICTPns MCH_ICH_SYNC#

+V3.3S

PCIE_RXN0_LAN PCIE_RXP0_LAN PCIE_TXN0_LAN PCIE_TXP0_LAN

6

INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#

AE9 AG8 AH8 F21 AH20

+V3.3S

30 30 30 30

10

INT_PIRQF# INT_PIRQA# PCI_REQ#0

ICH7M

SPI_SCK_ICH SPI_CE#_ICH

R2 P6 P1

SPI_CLK SPI_CS# SPI_ARB

SPI_SI_ICH SPI_SO_ICH

P5 P2

SPI_MOSI SPI_MISO

D3 C4 D5 D4 E5 C3 A2 B3

OC0# OC1# OC2# OC3# OC4# OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31

+V3.3S

2 4 6 8

25 USB_PORT_OC1# 25 USB_PORT_OC0# +V3.3S

R455 10K R0402

2 4 6 8

PCI-Express

PCI

+V3.3S

+V3.3AL

Direct Media Interface

C

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

2 4 6 8

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

V26 V25 U28 U27

DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0

10 10 10 10

DMI1RXN DMI1RXP DMI1TXN DMI1TXP

Y26 Y25 W28 W27

DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1

10 10 10 10

DMI2RXN DMI2RXP DMI2TXN DMI2TXP

AB26 AB25 AA28 AA27

DMI3RXN DMI3RXP DMI3TXN DMI3TXP

AD25 AD24 AC28 AC27

DMI_CLKN DMI_CLKP

AE28 AE27

DMI_ZCOMP DMI_IRCOMP

C25 D25

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P

F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3

USBRBIAS# USBRBIAS

D2 D1

SPI

E18 C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12 C13 G15 G13 E12 C11 D11 A11 A10 F11 F10 E9 D9 B9 A8 A6 C7 B6 E6 D6

PCI_STOP# PCI_REQ#1 PCI_REQ#2 PCI_FRAME#

USB

U24B

RN22 10K RA0402_8 1 3 5 7

+V1.5S_PCIE_ICH Place within 500 mils of ICH CLK_PCIE_ICH# 6 CLK_PCIE_ICH 6

C

DMI_IRCOMP_RR240 24.9,1% R0402 USB_PORT_PN1 25 USB_PORT_PP1 25 USB_PORT_PN0 25 USB_PORT_PP0 25 USB_PORT_PN2 25 USB_PORT_PP2 25 MINICARD_USB_PN3 MINICARD_USB_PP3

24 24

USB_CAM_PN5 15 USB_CAM_PP5 15 MINICARD_USB_PN4 MINICARD_USB_PP4

23 23

USB_CR_PN6 USB_CR_PP6

22 22

USB_RBIAS_PN R245 22.6,1% R0402 Place within 500 mils of ICH

ICH7M

B

B

+V3.3AL

R238 10K R0402

+V3.3AL C188 0.1uF/10V,X5R C0402

5

U9 W25X40 SO8_50_150

VCC 10,19,23,24,29,30

BUF_PLT_RST#

1

R241 3.3K R0402

4

3

GND R713 100K R0402

8

VDD

SPI_WP# 3

WP#

SPI_HD# 7

HOLD#

PLT_RST#

2

R243 3.3K R0402

U11 SN74AHC1G08DBV SOT23_5

C499 0.1uF/10V,X5R C0402

ns

SI SO CE# SCK

5 2 1 6

VSS

4

CS# Q W# VSS

1 2 3 4

SPI_SI SPI_SO SPI_CE# SPI_SCK

R239 22 R242 22 R244 22

R0402 SPI_SI_ICH R0402 SPI_SO_ICH SPI_CE#_ICH R0402 SPI_SCK_ICH

GNT5# 0 1 1

GNT4# 1 0 1

Boot BIOS SPI PCI LPC

+V3.3AL SPI_HD# SPI_SCK SPI_SI

8 7 6 5

VCC HOLD# CLK D

SPI_CE# SPI_SO SPI_WP#

U10 W25X80A SOIC8_50_208

A

A

TOPSTAR TECHNOLOGY Swain Xu Page Name

ICH7_M(2 of 4)

Size A3

N01

Project Name

Rev A

of Date: Wednesday, July 16, 2008 Sheet 18 42 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

+V3.3S +V3.3AL +V5S

+V3.3AL

+V3.3S

3

2

SMB_DATA_S

6,14,23,24 +V3.3S

2

SMB_CLK_S

6,14,23,24

R246 8.2K R0402

1

+V5S

PM_RI# 26 PC_BEEP 15,29 PM_SUS_STAT# 7 PM_SYSRST#

C

6 PM_STP_PCI# 6 PM_STP_CPU#

+V3.3S

R256 10K R0402

3

VR_PWRGD_CLK_EN

1 2

39 CK505_CLK_EN#

C504 0.1uF/10V,X5R C0402 ns

RI#

A19 A27 A22

SPKR SUS_STAT# SYS_RST#

B23

PM_STPPCI# PM_STPCPU#

AC20 AF21

GPIO0/BM_BUSY# GPIO11/SMBALERT# GPIO18/STPPCI# GPIO20/STPCPU#

A21

GPIO26

B21 E23

GPIO27 GPIO28

AG18

GPIO32/CLKRUN#

AC19 U2

GPIO33/AZ_DOCK_EN# GPIO34/AZ_DOCK_RST#

PM_THRM#

F20 AH21 AF20

WAKE# SERIRQ THRM#

VR_PWRGD_CLK_EN

AD22

VRMPWRGD

AC21 AC18 E21

GPIO6 GPIO7 GPIO8

6

23,24,29,30 PCIE_WAKE# 29 INT_SERIRQ

SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1

A28

SMB_ALERT#

29 PM_CLKRUN#

Q9 2N7002 SOT23

C22 B22 A26 B25 A25

AB18

10 PM_BMBUSY#

R261 1K R0402

R247 8.2K R0402

R248 8.2K R0402

R249 8.2K R0402

U24C SMB_CLK SMB_DATA SMB_LINK_ALERT# SMLINK0 SMLINK1

29 EC_RUNTIME_SCI# 29 EXT_SMI#

SATA GPIO

3

D

1

Q8 2N7002 SOT23 SMB_CLK

R265 2.2K R0402

Clocks

SMB_DATA

R266 2.2K R0402

Q7 2N7002 SOT23

SMB

R263 2.2K R0402

SYS GPIO Power MGT

R262 2.2K R0402

D

6,7,10,11,12,14,15,16,17,18,20,21,23,24,25,26,27,28,29,30,35,36,37,39 15,17,18,20,23,24,25,27,29,30,31,32,33,34,35,36,37,39 15,16,20,21,25,26,27,29,35,37,38,39

GPIO

GPIO21/SATA0GP GPIO19/SATA1GP GPIO36/SATA2GP GPIO37/SATA3GP

+V3.3AL

AF19 AH18 AH19 AE19

CLK14 CLK48

AC1 B2

SUSCLK

C20

SLP_S3# SLP_S4# SLP_S5#

B24 D23 F22

PM_SLP_S5#

PWROK

AA4

PM_ICH_PWROK

GPIO16/DPRSLPVR

ICH_SUSCLK

T24

C21

PWRBTN#

C23

LAN_RST#

C19

RSMRST#

Y4 E20 A20 F19 E19 R4 E22 R3 D20 AD21 AD20 AE20

6 6

PC_BEEP

R250 1K

PM_RI#

R251 10K

ns

R0402 R0402

SMB_ALERT#

R252 10K

R0402

SMB_LINK_ALERT# R253 10K

R0402

SMLINK0

R254 10K

R0402

SMLINK1

R255 10K

R0402

PM_SLP_S3#

R257 10K

R0402

PM_BATLOW#

R258 8.2K

R0402

PM_SYSRST#

R260 10K

R0402

PCIE_WAKE#

R264 1K

R0402

PM_CLKRUN#

R301 10K

R0402

ICTPns

PM_SLP_S3# PM_SLP_S4# T30 ICTPns

AC22

TP0/BATLOW#

GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15 GPIO24 GPIO25 GPIO35 GPIO38 GPIO39

CLK_ICH14 CLK_USB48

29,36 29,37

PM_DPRSLPVR 10

C

PM_BATLOW# PM_PWRBTN# 29 R293

0

R0402

BUF_PLT_RST# 10,18,23,24,29,30 PM_RSMRST# 29,36

R344 10K R0402

ICH7M

B

B

PM_RSMRST#

3

+V3.3AL

1

ns R298 10K R0402

EC_RUNTIME_SCI#

R294 10K R0402

EXT_SMI#

R267 10K R0402 ns

PM_STPPCI#

R268 10K R0402 ns

PM_STPCPU#

R270 10K R0402

INT_SERIRQ

R271 8.2K R0402

PM_THRM#

R274 100KR0402

PM_DPRSLPVR

10,29,39 IMVP_PWRGD

R269

0

2

R389 100K +V3.3S

Q25 2N2222 SOT23 ns

EC_PWROFF#

29

R0402 PM_ICH_PWROK R272 10K R0402

A

A

TOPSTAR TECHNOLOGY Swain Xu Page Name Size A3

Project Name

ICH7_M(2 of 3) Rev A

N01

of Date: Wednesday, July 16, 2008 Sheet 19 42 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

+V3.3AL +V3.3S +V1.05S +V5AL

+V3.3S

V5REF[2]

+V5AL

+V3.3AL

1

10mA

770mA

B27

50mA Place within 100 mils on the bottom or 140 mil on the top of ICH

+V1.5S

+V3.3S

1.01A C214 0.1UF/10V,X7R C0402

50mA 270mA

Place within 100 mils on the bottom or 140 mil on the top of ICH

+V1.5S

+V1.5S

A

C219 0.1UF/10V,X7R C0402

1.01A C218 0.1UF/10V,X7R C0402

45mA 10mA

ns ICTP ns ICTP C222 0.1UF/10V,X7R C0402

T26 T29

AB7 AC6 AC7 AD6 AE6 AF5 AF6 AG5 AH5

Vcc1_5_A[1] Vcc1_5_A[2] Vcc1_5_A[3] Vcc1_5_A[4] Vcc1_5_A[5] Vcc1_5_A[6] Vcc1_5_A[7] Vcc1_5_A[8] Vcc1_5_A[9]

AD2

VccSATAPLL Vcc3_3[2] Vcc1_5_A[10] Vcc1_5_A[11] Vcc1_5_A[12] Vcc1_5_A[13] Vcc1_5_A[14] Vcc1_5_A[15] Vcc1_5_A[16] Vcc1_5_A[17] Vcc1_5_A[18]

E3

VccSus3_3[19]

C1

VccUSBPLL

AA2 Y7

4

A5 B13 B16 B7 C10 D15 F9 G11 G12 G16

A24 C24 D19 D22 G19

VccSus3_3[7] VccSus3_3[8] VccSus3_3[9] VccSus3_3[10] VccSus3_3[11] VccSus3_3[12] VccSus3_3[13] VccSus3_3[14] VccSus3_3[15] VccSus3_3[16] VccSus3_3[17] VccSus3_3[18]

K3 K4 K5 K6 L1 L2 L3 L6 L7 M6 M7 N7

Vcc1_5_A[19] Vcc1_5_A[20]

AB17 AC17

Vcc1_5_A[21] Vcc1_5_A[22] Vcc1_5_A[23]

T7 F17 G17

Vcc1_5_A[24] Vcc1_5_A[25]

AB8 AC8

VccSus1_05[1]

C193 0.1UF/10V,X7R C0402

+V1.05S

+V3.3S Place within 100 mils on the bottom or 140 mil on the top of ICH

C198 0.1UF/10V,X7R C0402

330mA

C205 0.1UF/10V,X7R C0402

C200 0.1UF/10V,X7R C0402

330mA

C199 4.7UF/10V,Y5V C0805

+V3.3S

C201 C202 C203 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R C0402 C0402 C0402 +V3.3A_RTC

C209 0.1UF/10V,X7R C0402

6uA

C210 0.1UF/10V,X7R C0402 +V3.3AL

52mA C211 0.1UF/10V,X7R C0402

C212 0.1UF/10V,X7R C0402

+V3.3AL

52mA C215 0.1UF/10V,X7R C0402

C216 0.1UF/10V,X7R C0402

+V1.5S

1.01A

K7

T25 ICTP

ns

C28 G20

T28 ICTP T27 ICTP

ns ns

A1 H6 H7 J6 J7

C194 0.1UF/10V,X7R C0402

14mA

Vcc3_3[12] Vcc3_3[13] Vcc3_3[14] Vcc3_3[15] Vcc3_3[16] Vcc3_3[17] Vcc3_3[18] Vcc3_3[19] Vcc3_3[20] Vcc3_3[21]

VccSus3_3[2] VccSus3_3[3] VccSus3_3[4] VccSus3_3[5] VccSus3_3[6]

+V3.3AL

50mA 10mA

AA7 AB12 AB20 AC16 AD13 AD18 AG12 AG15 AG19

P7

+V3.3S

30mA

Vcc3_3[3] Vcc3_3[4] Vcc3_3[5] Vcc3_3[6] Vcc3_3[7] Vcc3_3[8] Vcc3_3[9] Vcc3_3[10] Vcc3_3[11]

W5

C224 10UF/6.3V,X5R C0805 + C524 220UF/6.3V,OSCON CAP6_6x7_3

C192 0.1UF/10V,X7R C0402

R7

VccRTC

C223 10UF/6.3V,X5R C0805

ns

AE23 AE26 AH26

VccSus3_3[1]

C190 1UF/10V,X7R C0603

+V3.3S

V_CPU_IO[1] V_CPU_IO[2] V_CPU_IO[3]

VccSus1_05[2] VccSus1_05[3] VccSus1_05/VccLAN1_05[1] VccSus1_05/VccLAN1_05[2]Vcc1_5_A[26] Vcc1_5_A[27] Vcc1_5_A[28] Vcc1_5_A[29] Vcc1_5_A[30] ICH7M

5

VccSus3_3/VccSusHDA

ATX

C217 0.1UF/10V,X7R Place within 100 C0402 mils on the bottom or 140 mil on the top of ICH near AG9 +V3.3AL

VccDMIPLL

AB10 AB9 AC10 AD10 AE10 AF10 AF9 AG9 AH9

U6

Vcc3_3[1]

AG28

AH11

Vcc3_3/VccHDA

ARX

Place within 100 mils on the C213 0.1UF/10V,X7Rbottom or 140 mil on the top of ICH C0402 near AG5

V5 V1 W2 W7

PCI

+V1.5S

B

VccSus3_3/VccLAN3_3[1] VccSus3_3/VccLAN3_3[2] VccSus3_3/VccLAN3_3[3] VccSus3_3/VccLAN3_3[4]

C189 0.1UF/10V,X7R C0402

IDE

270mA

Vcc1_5_B[1] Vcc1_5_B[2] Vcc1_5_B[3] Vcc1_5_B[4] Vcc1_5_B[5] Vcc1_5_B[6] Vcc1_5_B[7] Vcc1_5_B[8] Vcc1_5_B[9] Vcc1_5_B[10] Vcc1_5_B[11] Vcc1_5_B[12] Vcc1_5_B[13] Vcc1_5_B[14] Vcc1_5_B[15] Vcc1_5_B[16] Vcc1_5_B[17] Vcc1_5_B[18] Vcc1_5_B[19] Vcc1_5_B[20] Vcc1_5_B[21] Vcc1_5_B[22] Vcc1_5_B[23] Vcc1_5_B[24] Vcc1_5_B[25] Vcc1_5_B[26] Vcc1_5_B[27] Vcc1_5_B[28] Vcc1_5_B[29] Vcc1_5_B[30] Vcc1_5_B[31] Vcc1_5_B[32] Vcc1_5_B[33] Vcc1_5_B[34] Vcc1_5_B[35] Vcc1_5_B[36] Vcc1_5_B[37] Vcc1_5_B[38] Vcc1_5_B[39] Vcc1_5_B[40] Vcc1_5_B[41] Vcc1_5_B[42] Vcc1_5_B[43] Vcc1_5_B[44] Vcc1_5_B[45] Vcc1_5_B[46] Vcc1_5_B[47] Vcc1_5_B[48] Vcc1_5_B[49] Vcc1_5_B[50] Vcc1_5_B[51] Vcc1_5_B[52] Vcc1_5_B[53]

VCCA3GP

AA22 AA23 AB22 D14 AB23 Layout note: R275 1N4148WS AC23 SOD323 10 0.1uF needs be placed AC24 R0402 within 100mils of pin AC25 Place above cap F6 of ICH7M AC26 with 100milof AD26 ICH on the AD27 bottom or 140 AD28 mil on the top D26 near D28 T28 C191 D27 AD28 0.1uF/10V,X5R D28 C0402 E24 E25 +V1.5S E26 100 OHM@100MHz BEAD +V1.5S_PCIE_ICH F23 IN INTEL DEMO CIRCUIT F24 FB15 0 R0805 G22 G23 C523 C525 C526 C195 C197 H22 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 0.1UF/10V,X7R C196 0.1UF/10V,X7R H23 0.1UF/10V,X7R C0402 C0805 C0805 C0805 C0402 J22 C0402 J23 K22 K23 L22 L23 M22 M23 N22 N23 P22 P23 R22 R23 R24 Place within 100 R25 mils on the R26 bottom or 140 mil +V1.5S T22 on the top of ICH +V3.3S T23 FB16 0 R0805 T26 T27 T28 U22 C207 U23 0.01uF/25V,X7R V22 C0402 C206 C208 V23 10UF/6.3V,X5R 0.1UF/10V,X7R W22 C0805 C0402 W23 Y22 Y23

V5REF_Sus

L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18

1

F6

Vcc1_05[1] Vcc1_05[2] Vcc1_05[3] Vcc1_05[4] Vcc1_05[5] Vcc1_05[6] Vcc1_05[7] Vcc1_05[8] Vcc1_05[9] Vcc1_05[10] Vcc1_05[11] Vcc1_05[12] Vcc1_05[13] Vcc1_05[14] Vcc1_05[15] Vcc1_05[16] Vcc1_05[17] Vcc1_05[18] Vcc1_05[19] VCC PAUX Vcc1_05[20]

+V1.05S

860mA

2

V5REF[1]

CORE

G10 AD17

1

A4 A23 B1 B8 B11 B14 B17 B20 B26 B28 C2 C6 C27 D10 D13 D18 D21 D24 E1 E2 E4 E8 E15 F3 F4 F5 F12 F27 F28 G1 G2 G5 G6 G9 G14 G18 G21 G24 G25 G26 H3 H4 H5 H24 H27 H28 J1 J2 J5 J24 J25 J26 K24 K27 K28 L13 L15 L24 L25 L26 M3 M4 M5 M12 M13 M14 M15 M16 M17 M24 M27 M28 N1 N2 N5 N6 N11 N12 N13 N14 N15 N16 N17 N18 N24 N25 N26 P3 P4 P12 P13 P14 P15 P16 P17 P24 P27

15,17,18,19,23,24,25,27,29,30,31,32,33,34,35,36,37,39 +V5S 15,16,19,21,25,26,27,29,35,37,38,39 6,7,10,11,12,14,15,16,17,18,19,21,23,24,25,26,27,28,29,30,35,36,37,39 +V1.5S 8,10,11,12,23,24,35,36,37 6,7,8,9,11,12,17,28,35,36,37 +V3.3A_RTC 17 +V1.5S_PCIE_ICH 18 15,22,25,33,34,36,37

U24F

IDE

6mA

D

C204 1uF/10V,X7R C0603

2

Layout note:Distribute near pin ICH7 Package edge

Layout note: 0.1uF needs be placed within 100mils of ICH7M PIN AD17

PCI

D13 1N4148WS SOD323

USB

1

R276 100 R0402

C

3

USB CORE

+V5S

4

1

5

C220 0.1UF/10V,X7R C0402

VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97]

D

C

B

U24E ICH7M

A

TOPSTAR TECHNOLOGY

+V1.5S

Swain Xu Page Name

1.01A

VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194]

P28 R1 R11 R12 R13 R14 R15 R16 R17 R18 T6 T12 T13 T14 T15 T16 T17 U4 U12 U13 U14 U15 U16 U17 U24 U25 U26 V2 V13 V15 V24 V27 V28 W6 W24 W25 W26 Y3 Y24 Y27 Y28 AA1 AA24 AA25 AA26 AB4 AB6 AB11 AB14 AB16 AB19 AB21 AB24 AB27 AB28 AC2 AC5 AC9 AC11 AD1 AD3 AD4 AD7 AD8 AD11 AD15 AD19 AD23 AE2 AE4 AE8 AE11 AE13 AE18 AE21 AE24 AE25 AF2 AF4 AF8 AF11 AF27 AF28 AG1 AG3 AG7 AG11 AG14 AG17 AG20 AG25 AH1 AH3 AH7 AH12 AH23 AH27

Place within 100 C221 0.1UF/10V,X7R mils on the bottom or 140 mil C0402 on the top of ICH

3

Size A3

Project Name

ICH7_M(3 of 3) Rev A

N01

of Date: Wednesday, July 16, 2008 Sheet 20 42 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 2

1

5

4

D

3

2

1

+V5S

15,16,19,20,25,26,27,29,35,37,38,39

+V3.3S

6,7,10,11,12,14,15,16,17,18,19,20,23,24,25,26,27,28,29,30,35,36,37,39

D

SATA HDD +V5S

V_HDD FB32 0

C444 4.7uF/10V,Y5V C0805

C301 0.1uF/25V,Y5V C0402

+V3.3S

C300 0.1uF/25V,Y5V C0402

17 17 17 17

V3.3_SATA FB31 0

SATA_HDD SATA_HDD CONN SATA_S_50E

Close to connector as possible the same distance to connector

R0805

R0805 ns

SATA_TXP0 SATA_TXN0 C508 SATA_RXN0 C507 SATA_RXP0

P2 P3 3300pF/50V,X7RC0402 P5 3300pF/50V,X7RC0402 P6

V3.3_SATA

V_HDD

TX TX# RX# RX

GND0 GND1 GND2

P1 P4 P7

P8 P9 P10

VCC3_0 VCC3_1 VCC3_2

GND3 GND4 GND5

P11 P12 P13

P14 P15 P16 P18

VCC5_0 VCC5_1 VCC5_2 REEVE

GND6

P17

GND7

P19

P20 P21 P22

VCC12_0 VCC12_1 VCC12_2

GND8 GND9

23 24

C

C441 4.7uF/10V,Y5V C0805 ns

C295 0.1UF/16V,Y5V C0402 ns

C294 0.1UF/16V,Y5V C0402 ns

C

B

B

TOPSTAR TECHNOLOGY Swain Xu Page Name

A

Size A4

Project Name

SATA HDD

A

Rev A

N01

21 42 of Date: Wednesday, July 16, 2008 Sheet PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

+V5AL

15,20,25,33,34,36,37

FB19 600ohm@100MHz,1.5A FB0805 VCC3VA

VCC3V

D

D

C231 4.7UF/10V,Y5V C0805

C232 0.1UF/25V,Y5V C0402

CFD2/SMD2/SDD2 CFD3/SMD3/SDD3

C237 4.7UF/10V,Y5V C0805 CFD4/SMD4/MSD0

1 2 3 4 5 6 7 8 9 10 11 12

SDCLK VREF C229 0.1UF/25V,Y5V C0402

VBUS_5V

C234 10uF/10V,Y5V C1206 ns

CARD_3V3

C235 0.1UF/25V,Y5V C0402

SMD6/MSD2 SMD7/MSD3 SMCLE/SDCMD VCC33_2 SDCDZ GND_3 SDWPD SMWPZ VCC18 SMBSYZ/MMCD7 SDA/TEST3/UARX SCL/TESTINTR

R279 0 R0805

VBUS_5V

1

C238 C239 27pF/50V,NPO27pF/50V,NPO C0402 C0402

VCC3VA

Y3 12.000MHz XS2 XO 2

REXT

R282 0 R0402

VCC3VA

XI

+V5AL

CFD0/SMD0/SDD0 CFD1/SMD1/SDD1 SDCD# EROM15/SDWPD

36 35 34 33 32 31 30 29 28 27 26 25

CFD6/SMD6/MSD2 CFD7/SMD7/MSD3 CFA1/SMCLE/SDCMD VCC3V SDCD#

DAT2_SD DAT3_SD CMD_SD

7

CLK_SD

9 10 1 11

VDD_SD

6

CARD_3V3 C516 0.1uF/10V,X7R

SD+MMC

DAT0_SD DAT1_SD CD_SD# WP_SD#

VSS_SD2

8

VSS_SD1

5

VCC_MS

13

C517 1uF/10V,X7R C0603

3IN1 J6B

EROM15/SDWPD VCC18

MSCLK1

14

CLK_MS

CFD7/SMD7/MSD3 MSINS CFD6/SMD6/MSD2 CFD4/SMD4/MSD0 MSD1 CFA0/SMALE/MSBS

15 16 17 18 19 20

DAT3_MS INS_MS DTA2_MS DTA0_MS DTA1_MS BS_MS

CARD_3V3

MS VSS_MS1 VSS_MS2 GND1 GND2

12 21 22 23

3IN1

C

C518 0.1uF/10V,X7R

C519 1uF/10V,X7R C0603

13 14 15 16 17 18 19 20 21 22 23 24

C233 1uF/25V,Y5V C0805

SDCLK

2 3 4

USB_CR_PP6 USB_CR_PN6

18 18

R281 12.1K,1% R0402

PWR SW

4 5 6

C

VCC3V CARD_3V3 VCC18 VCC3V VCC5V

SMD4/MSD0 SMD5/MMCD6 SDCLK SMWEZ/MMCD5 GND_1 SMCDZ VCC33_1 CRDVCC REG18_O REG33_O VBUS GND_2

SMCEZ LEDZ/TESTEN/UATX SMWPDZ/TEST0 XI XO VCC33A_1 GNDA_1 REXT DM DP VCC33A_2 GNDA_2

C236 0.1UF/25V,Y5V C0402

J6A CFD2/SMD2/SDD2 CFD3/SMD3/SDD3 CFA1/SMCLE/SDCMD

SMALE/MSBS MSCLK MSD1 SMREZ/MMCD4 SMD3/SDD3 SMD2/SDD2 VREF GND_4 VCC33_3 MSINSZ SMD1/SDD1 SMD0/SDD0

U25 UB6232 QFPS48_0D5_1D6

VCC18

OLD 3IN1 CONN.

MSINS CFD1/SMD1/SDD1 CFD0/SMD0/SDD0

48 47 46 45 44 43 42 41 40 39 38 37

R278 0 R0603

VREF

MSD1 MSCLK1 CFA0/SMALE/MSBS

VCC3V

C230 0.1UF/25V,Y5V C0402

S

R735

0 R0805 CR_Nops

Q27 AO6409

+V5AL

VBUS_5V

D

3 2 1

G

B

SDCD#

MSINS

3

SDCD_D# 1 D37 BAT54C SOT23 2 CR_PS

3

2 D38 BAT54C SOT23 MSINS_D# 1 CR_PS

R738 0

TSOP6_0D95_1D6 CR_PS B

R736 4.7K R0402 CR_PS

R737

C531 C0402 0.01uF/25V,X7R CR_PS

C532 C0402 0.01uF/25V,X7R CR_PS

100K R0402 CR_PS

R0805 CR_Nops

A

A

TOPSTAR TECHNOLOGY Swain Xu Page Name

Card Reader(UB6232 USB)

Size A3

N01

Project Name

Rev A

Date: Wednesday, July 16, 2008 Sheet 22 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

+V3.3S +V3.3AL +V1.5S +VDC

1

6,7,10,11,12,14,15,16,17,18,19,20,21,24,25,26,27,28,29,30,35,36,37,39 15,17,18,19,20,24,25,27,29,30,31,32,33,34,35,36,37,39 8,10,11,12,20,24,35,36,37 15,25,31,33,34,35,37,39

+DATA4 -DATA4

D

D

+V3.3S

PCIE_NUT1 Hole+Dowel TH_200_132_112

R283 0 R0603 ns

R284 0 R0603

+V3.3AL_PCIE

CHK1 90ohm@100MHz,0.5A L4_0805 ns 3 4 2 1

-DATA4 +DATA4

36 38

6 CLK_PCIE_EXPCARD# 6 CLK_PCIE_EXPCARD

11 13

REFCLKREFCLK+

18 PCIE_TXN1_SLOT 18 PCIE_TXP1_SLOT

31 33

PETN0 PETP0

18 PCIE_RXN1_SLOT 18 PCIE_RXP1_SLOT

23 25

PERN0 PERP0

10,18,19,24,29,30

6 PCI_CLK_DEBUG +V3.3AL

R296 0 R302 0

R0402 R0402

Debug Debug

17 19

RESERVED0 RESERVED1

R323 0 R295 0

R0402 R0603

Debug

37 39 41 43 45 47 49 51

RESERVED_PCIE0 RESERVED_PCIE1 RESERVED_PCIE2 RESERVED_PCIE3 RESERVED_PCIE4 RESERVED_PCIE5 RESERVED_PCIE6 RESERVED_PCIE7

R304 R322 R330 R331 R332

0 0 0 0 0

R0402 R0402 R0402 R0402 R0402

Debug Debug Debug Debug Debug

+V3.3S

LED_WPAN# LED_WLAN# LED_WWAN#

46 44 42

PERST# WAKE# CLKREQ#

22 1 7

SMB_DATA SMB_CLK

32 30

CHANNEL_CLK CHANNEL_DATA

ICTP ns

Wireless_LED# 27 ICTP ns

T32

20

RESERVED_SIM0 RESERVED_SIM1 RESERVED_SIM2 RESERVED_SIM3 RESERVED_SIM4

16 14 12 10 8

9 15 21 27 29 35 4 18 26 34 40 50 53 54

B

R287 10K R0402 ns

minicard_CLKREQ# C

minicard_Wake# minicard_CLKREQ#

R290 0 R299 0

R0402 R0402

R292 0 R291 0

R0402 R0402

minicard_Wake#

BUF_PLT_RST# 10,18,19,24,29,30 PCIE_WAKE# 19,24,29,30 PCIE_CLKREQ# 6,24

ns ns ns ns +V3.3AL

5 3

RESERVED_DISABLE

+V3.3AL

R286 10K R0402 ns

T31

SMB_DATA_S 6,14,19,24 SMB_CLK_S 6,14,19,24

R0402 10K R300 R297 0 R333 R338 R339 R340 ns

T37

0 0 0 0

R0402 R0402 R0402 R0402

R0402 Debug Debug Debug Debug

HW_RATIO_OFF1#

29

EC_DEBG_Enable 29 PWR_SW_VCC2 25,31 EC_DEBG_UTXD 29 EC_DEBG_URXD 29

ICTP

GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13

17,29 LPC_FRAME# 17,29 LPC_AD0 17,29 LPC_AD1 17,29 LPC_AD2 17,29 LPC_AD3

48 28 6

USB_DUSB_D+

C

+VDC BUF_PLT_RST#

+1.5V0 +1.5V1 +1.5V2

2 52

R0402 R0402

PCIE mini Card

18 MINICARD_USB_PN4 18 MINICARD_USB_PP4

+3.3V0 +3.3V1

Keep USB2.0 Signal stub short R288 0 R289 0

+V1.5S

1

+V3.3S_PCIE MPCIE1 MINIPCIE_TEMP1

R285 0 R0603

24

D16 ESDPAD_R0603 EGA1-0603-V05 ns

+3.3VAUX

1 2

2

1

+V3.3AL D15 ESDPAD_R0603 EGA1-0603-V05 ns

+V3.3S_PCIE C243 10UF/6.3V,X5R C0805

PCIE MINI CARD

B

+V3.3AL_PCIE C244 0.1UF/25V,Y5V C0402

C245 10UF/6.3V,X5R C0805

C246 0.1UF/25V,Y5V C0402

+V1.5S

C247 10UF/6.3V,X5R C0805

C248 0.1UF/25V,Y5V C0402

C249 0.1UF/25V,Y5V C0402

C250 0.1UF/25V,Y5V C0402

C251 0.1UF/25V,Y5V C0402

A

A

TOPSTAR TECHNOLOGY Swain Xu Page Name Size A3

Project Name

PCIE MINI SLOT 1 Rev A

N01

Date: Wednesday, July 16, 2008 Sheet 23 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

+V3.3S +V1.5S +V3.3AL

6,7,10,11,12,14,15,16,17,18,19,20,21,23,25,26,27,28,29,30,35,36,37,39 8,10,11,12,20,23,35,36,37 15,17,18,19,20,23,25,27,29,30,31,32,33,34,35,36,37,39

D

D

+DATA8 -DATA8

+V3.3S

+3.3V0 +3.3V1

R495 R496

0 0

CHK6 90ohm@100MHz,0.5A L4_0805 3 4 2 1

18 MINICARD_USB_PN3 18 MINICARD_USB_PP3

-DATA8 36 +DATA8 38

11 13

REFCLKREFCLK+

18 PCIE_TXN2_SLOT 18 PCIE_TXP2_SLOT

31 33

PETN0 PETP0

18 PCIE_RXN2_SLOT 18 PCIE_RXP2_SLOT

23 25

PERN0 PERP0

17 19

RESERVED0 RESERVED1

37 39 41 43 45 47 49 51

RESERVED_PCIE0 RESERVED_PCIE1 RESERVED_PCIE2 RESERVED_PCIE3 RESERVED_PCIE4 RESERVED_PCIE5 RESERVED_PCIE6 RESERVED_PCIE7

ns ns

+V3.3AL

R533 0

ICTP ICTP

T150 T146

R532 0 R0603

R0603

B

+V3.3S

R540 10K ns

USB_DUSB_D+

ns 6 CLK_PCIE_EXPCARD2# 6 CLK_PCIE_EXPCARD2

+V1.5S

48 28 6

MPCIE2 MINIPCIE_TEMP1

R504 0 R0603

+V3.3AL

+1.5V0 +1.5V1 +1.5V2

2

R506 0 R0603

24

R500 0 R0603 ns

ESDPAD_R0603 ns

+3.3VAUX

D35 EGA10603V05A1-B

Keep USB2.0 Signal stub short

C

+V3.3AL

PCIE mini Card

D36 EGA10603V05A1-B

ESDPAD_R0603 ns 2

+V3.3AL

1

2 52

1

LED_WPAN# LED_WLAN# LED_WWAN#

46 44 42

PERST# WAKE# CLKREQ#

22 1 7

SMB_DATA SMB_CLK

32 30

T148 T155

ns ns

T147

ns

R502 10K ns

R539 10K ns C

MiniPCIE_REQ# HW_RATIO_OFF2#

CHANNEL_CLK CHANNEL_DATA

WAKE# R538 0 MiniPCIE_REQ#

BUF_PLT_RST# 10,18,19,23,29,30 PCIE_WAKE# 19,23,29,30 PCIE_CLKREQ# 6,23

ns

R402 0 R394 0

ns ns

WAKE#

SMB_DATA_S 6,14,19,23 SMB_CLK_S 6,14,19,23

5 3

RESERVED_DISABLE

20

RESERVED_SIM0 RESERVED_SIM1 RESERVED_SIM2 RESERVED_SIM3 RESERVED_SIM4

16 14 12 10 8

R503

0

HW_RATIO_OFF2#

T152ICTP ns T151ICTP ns T149ICTP ns T154ICTP ns T153ICTP ns

29

R491 R492 10K 10K ns ns B

9 15 21 27 29 35 4 18 26 34 40 50 53 54

GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13

+V3.3S +V3.3AL

+V1.5S

PCIE MINI CARD

+V3.3S +V3.3AL

C458 10UF/6.3V,X5R C0805

C459 0.1UF/25V,Y5V C0402

C450 0.1UF/25V,Y5V C0402

C445 C449 0.1UF/25V,Y5V 0.1UF/25V,Y5V C0402 C0402

C452 10UF/6.3V,X5R C0805

C469 0.1UF/25V,Y5V C0402

C457 10UF/6.3V,X5R C0805

C460 0.1UF/25V,Y5V C0402

A

A

TOPSTAR TECHNOLOGY Swain Xu Page Name Size A3

Project Name

USB Port Rev A

N01

of Date: Wednesday, July 16, 2008 Sheet 24 42 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

4

3

2

1

+V3.3S +V3.3AL +V5S +V5AL +VDC

S3

FUSE 1.1A FUSE1812 1 2

C288 C289 330PF/50V,X7R + 100uF/10V,TAN R484 C0402 CT7343_28 300K R0402

D

R483 560K

+V5AL +V3.3AL

R0402

D

C429 1000pF/50V,X7R C0402 ns

USB1

GND

4

L4_0805

4 1

3 2

USB_PORT_PN0 18 USB_PORT_PP0 18 SWVCC2_SW_1

D30 ESDPAD_R0603 EGA1-0603-V05

2

SINGLE USB PORT USB1

PWRSW#

3

2 3

USB_PORT_OC0# 18 ns

1

90ohm@100MHz,0.5A CHK4 R335 0 R0603

D29 ESDPAD_R0603 EGA1-0603-V05

R334 0

PR163 1M R0402

GND_USB

R0603

29

+V3.3AL

PQ59 2N7002E-T1 SOT23 PC133 1000pF/50V,X7R C0402

2

-DATA1 +DATA1

Keep USB2.0 Signal stub short

GND_USB -DATA0 +DATA0

1

1

2

HOLE0 HOLE1 HOLE2 HOLE3

PR161 20K R0402

GND_USB

VCC1

1

5 6 7 8

6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,26,27,28,29,30,35,36,37,39 15,17,18,19,20,23,24,27,29,30,31,32,33,34,35,36,37,39 15,16,19,20,21,26,27,29,35,37,38,39 15,20,22,33,34,36,37 15,23,31,33,34,35,37,39

2

5

PD32 BAT54S SOT23

3 GND_USB GND_USB

1

GND_USB

PWR_SW_VCC2

23,31

C

C

+V3.3AL

+V5S

R359 10K

+V3.3S

R135 10K ns

R357 10K

ns 29

3

FAN_BACK

R351

1K

FAN_TACH_ON

1

ns

C286

2

+V5S

1000pF/50V,X7R

Q23 2N2222 SOT23 ns

R352 0

ns

Q13 BCP69-16 SOT223 4 3 2

Vfan

1

1 R36 1K

VCC_358 C161

R346

FAN_FB

USBCONN1

5.11K,1% U1A LM358 so8_50_150 + 3

21 2 4 FAN_FB 6 8 +VDC SWVCC2_SW_1 10 12 14 18 USB_PORT_OC1# 16 +V3.3AL 18 15,29 LIDR# 20 22 Vfan

2

1

2

R24 10 R0603

1

B

R35 1K

2

8

0.1UF/25V,Y5V

Shut-Down

+V3.3S

1

1

2

R349

4

C183 0.1UF/25V,Y5V R26 100K 2 1

R22 4.7K R0402

10K,1%

2

B

R25 200K

FAN1_V

R0402

Throttling/ Un-throttling

High-5V 29

21 2 4 6 8 10 12 14 16 18 20 22

1 3 5 7 9 11 13 15 17 19

1 3 5 7 9 11 13 15 17 19

USB_PORT_PP2 18 USB_PORT_PN2 18 +V5AL

USB_PORT_PP1 18 USB_PORT_PN1 18

88242_2001 CNS2x10_1_R

Middle-4V

Low-3V

A

FAN1_V=3.30V,Vfan=5V FAN1_V=2.65V,Vfan=4V FAN1_V=1.98V,Vfan=3V

C104 4.7UF/10V,Y5V C0805

C94 0.1uF/25V,Y5V C0402

A

TOPSTAR TECHNOLOGY 50

55

60

65

70

75

80

85

90

95

100 Swain Xu Page Name

Output Board

Size A3

N01

Project Name

Rev A

Date: Wednesday, July 16, 2008 Sheet 25 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

4

3

2

VCC5CDC

1

+V5S FB20

C255 C0402 0.1UF/25V,Y5V

5

PC_BEEP

R0402

C260

1uF/10V,Y5V C0603

C261

10pF/50V,NPO

75K R0402

C262

1uF/10V,Y5V C0603

C263 100pF/50V,NPO C0402

R312 4.7K R0402

R311 4.7K R0402

12

PC-BEEP

13

JD1

14

LINE2-L

15

LINE2-R

MIC2_L

C272

4.7uF/10V,X5R

C0805 16

MIC2_R

C273

4.7uF/10V,X5R

C0805 17

REMOVE SHUTDOWN# INT_MIC_L update internal MIC circuit

MIC1-VREFO-L

28

LINE1-VREFO-L

29

MIC2-VREFO

30

LINE2-VREFO

31

MIC1-VREFO-R

32

DCVOL

33

ALC662

MIC2-L

JD2

34

CEN-OUT

43

LFE-OUT

44

SIDESURR-OUT-L

45

SIDESURR-OUT-R

46

18

CD-L

SPDIFI/EAPD

47

20

CD-R

SPDIFO

48

SURR-OUT-L

39

JDREF

40

SURR-OUT-R

41

MIC2-R

C267

1uF/10V,X7R

C0603 21

MIC1-L

C268

1uF/10V,X7R

C0603 22

MIC1-R

C

23

LINE1-L

24

LINE1-R

C259

0.1UF/25V,Y5V

C265

10UF/6.3V,X5R C0805

VREFOUT

R303

4.7K

R0402 ns

C0402

HP_OUT_L

R319

75

R0402

HP_OUT_R

R320

75

R0402

R308

R317

2.2K

R0402

R306

4.7K

R0402

10K R0402 ns

FB23 1 FB24

1

2300ohm@100MHz,1.5A FB0805 2300ohm@100MHz,1.5A FB0805

2

D18 ESDPAD_R0603 EGA1-0603-V05

INT_MIC_L_R

0.1UF/25V,Y5V C278 C277 C0402 100pF/50V,NPO C0402

D32 C279 ESDPAD_R0603 EGA1-0603-V05 100pF/50V,NPO C0402

L

3 4 5 1

HP_JD

GND_AUD

D

R

D31 ESDPAD_R0603 AZALIAJACK EGA1-0603-V05 AUDIO5A

MIC2_REF

INT_MIC_L_R

GND_AUD

VCC5CDC JACK_DET_B

Stereo Microphone Jack INPUT:STEREO MIC-IN OUTPUT:CENT/LFE

D20

1N4148WS 2 SOD323 D24 1N4148WS 1 2 SOD323

MIC2_REF 1 EAPD

R721

0

R0402 SHUTDOWN# ns

R202 4.7K R0402

SURR_OUT_L R315

20K,1%

R0402

R220 4.7K R0402

MIC_IN1 C

GND_AUD

MIC2_L

R310

75

R0402

FB21 1

MIC2_R

R313

75

R0402

FB22 1

SURR_OUT_R

2300ohm@100MHz,1.5A FB0805 2300ohm@100MHz,1.5A FB0805

2

C269

C0402 0.1UF/25V,Y5V

C270

C271

D33 ESDPAD_R0603 EGA1-0603-V05

100pF/50V,NPO 100pF/50V,NPO C0402 C0402

L

3 4 5 1

MIC2_JD D17 ESDPAD_R0603 EGA1-0603-V05

2

4 7

Layout Note: All of JD resistors should be placed as close as possible to the sense pin of codec.

27

SDIN

C0402

JACK_DET_A R309

VREF

SDOUT

AGND1 AGND2

19

51K

8

37

26 42

BTL_BEEP

R0402

LINE1-VREFO-R

SYNC

CD-GND

17 HDA_SDATA_IN0 R307 29

33

HP_OUT_R

??

GND1 GND2

R305

HP_OUT_L

C0805

1

10

17 HDA_SDOUT

C0805

4.7uF/10V,X5R

1

17 HDA_SYNC

4.7uF/10V,X5R

C266

2

BITCLK

C264

2

REST#

6

17 HDA_RST#

35 36

1

11

17 HDA_BITCLK

LINE_OUT1 FRONT-OUT-L FRONT-OUT-R

1

T40 ICTP

INPUT:HEADPHONE/LINE-OUT OUTPUT:FRONT L/R

D34 ESDPAD_R0603 EGA1-0603-V05

R

AZALIAJACK AUDIO5A

2

GPIO1

6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,27,28,29,30,35,36,37,39 15,16,19,20,21,25,27,29,35,37,38,39

Headphone Jack

0.1UF/25V,Y5V C0402

Cross moat place GND_AUD

2

GPIO0

3

C258

1

2

A_GPIO1

C257 C0805 10UF/6.3V,X5R

U26 ALC662 QFPS48_0D5_1D6

AVDD1 AVDD2

A_GPIO0

ns

VDD1 VDD2

ns

19

T39 ICTP D

C256 C0402 0.1UF/25V,Y5V

1

C254 C0805 10UF/6.3V,X5R

25 38

C253 C0402 0.1UF/25V,Y5V

1 9

C252 C0402 0.1UF/25V,Y5V

+V3.3S +V5S

2300ohm@100MHz,1.5A FB0805

1

+V3.3S

2

5

GND_AUD

GND_AUD

GAIN0 GAIN1

Adjust Gain to 10dB BY K' 080118 R724 10K R0402 ns

B

1

1

Av(inv) 6dB 10dB

3

6

15.6dB 21.6dB

Q10 2N7002DW SC70_6

JACK_DET_B

R314

20K,1%

JACK_DET_A

R318

5.11K,1% R0402

R0402

MIC2_JD HP_JD

5 1

GAIN0 GAIN1 0 0 0 1 1 0

2

4

R723 10K R0402 ns

AMP_SHDW

5 1

R722 10K R0402

2

GND_AUD

Q11 2N7002DW SC70_6

3

6

VCC5CDC VCC5CDC AMP_SHDW

HP_OUT_R

GND_AUD

4

HP_OUT_L

VCC5CDC

R725 10K R0402

D25

R325 10K R0402 SHUTDOWN#

De-pop Solution

C291

3

GND_AUD GND_AUD

Q12 2N7002 AMP_SHDW

R327

1K

R0402

C0402

ns

0.1UF/25V,Y5V C0402 ns 0.1UF/25V,Y5V

1 R328 10K R0402

Layout Note: Tied at three points under the codec and near the codec

R329 100K R0402

2

29

C287

B

2 JOPEN_3 ns

1

FB26 1

2 FB0805 ns 300ohm@100MHz,1.5A

C285

C0402

ns

0.1UF/25V,Y5V

GND_AUD GND_AUD

Onboard Amp

ROUT+

18

INTSPR+

RIN+

ROUT-

14

INTSPR-

LIN+

LOUT+

4

INTSPL+

10

BYPASS LOUT-

8

5 12

LINNC

16 6 15 1 11 13 20 21

RIN-

7 9

20K R726 GND_AUD GND_AUD A

SURR_OUT_L C281 0.22uF/10V,X7R C0603

C282 C283

R0402

0.22uF/10V,X7R R326 10K R0402 C0603 0.22uF/10V,X7R C0603 R324 20K R0402 ns SHUTDOWN#

19

GAIN0

2

GAIN1

3

VDD PVDD1 PVDD2 SHDWN# GND1 GND2 GAIN0 GND3 GND4 GAIN1 GND5

INTSPLINTSPL+ INTSPR+ INTSPR-

INTSPLVCC5CDC C513 C0402

C284 C0805

C514 C0402

INTSPK1 INT_spkR 4Pin CNS4_R 4 4 6 6 3 3 2 2 1 1 5 5

onboard stereo microphone

INT_MIC_L_R

INT_MIC_L

R321 1K

R0402 FB25 1

C319 100pF/50V,NPO C0402

GND_AUD

300ohm@100MHz,1.5A 2 1 FB0805 2 1

U27 TPA6017A2 sop20_0d65_4d4g 17

2

C290 R336 0.22uF/10V,X7R 20K C0603 R0402 SURR_OUT_R

4.7uF/10V,Y5V

+

MIC1 Microphone BZ_D6027 ASSY

D23 ESDPAD_R0603 EGA1-0603-V05 ns

A

TOPSTAR TECHNOLOGY

0.1UF/10V,X7R 0.1UF/10V,X7R

Swain Xu Page Name GND_AUD

Size C

GND_AUD

Project Name

Audio N01

Rev A

Date: Sheet Wednesday, July 16, 2008 26 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

LED D

D

+V5S +V3.3S +V3.3AL

+V3.3S WIRELS R677 220 R0402 WIRE+

1

R678 220 R0402 IDE+

1

TP_WIRELESS_LED# 2 BL-HB335A-TRB TP_HDD_LED# 2

15,16,19,20,21,25,26,29,35,37,38,39 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,28,29,30,35,36,37,39 15,17,18,19,20,23,24,25,29,30,31,32,33,34,35,36,37,39

WIRELESS_LED# 23 HDD_LED#

17

HDD BL-HB335A-TRB

TCHARGE LED4_1210B HA1B333B AMP&BLUE

+V3.3AL

Blue Color 2

TP_CHG_LED#

R

C470 0.1UF/25V,Y5V C0402

4

R682 220 R0402 BAT_STATE_LED 3

B

R680 220 R0402 CHARGE_LED

1

TP_BTL_LED#

Orange color R684 220 R0402 PWR+

1

TP_POWERLED#

2

CHG_LED#

29

BTL_LED#

29

POWERLED#

29

TP INT_spkR 6Pin CNS6_0D5_RA1

POWER BL-HB335A-TRB

8 C

TP_WIRELESS_LED#TESD11 1 ns

2 EGA1-0603-V05 ESDPAD_R0603

TP_HDD_LED#

7

8 7

+V3.3AL

TESD8 ns

1

2 EGA1-0603-V05 ESDPAD_R0603

TP_CHG_LED#

R709 10K R0402 ns

TP_CHG_LED#

TESD9 ns

1

2 EGA1-0603-V05 ESDPAD_R0603

TP_BTL_LED#

R710 10K R0402 ns

TP_BTL_LED#

TESD10 1 ns

2 EGA1-0603-V05 ESDPAD_R0603

TP_POWERLED#

TESD12 1 ns

2 EGA1-0603-V05 ESDPAD_R0603

WIRE+

C472

1000pF/50V,X7R C0402

IDE+

C473

1000pF/50V,X7R C0402

CHARGE_LED

C474

1000pF/50V,X7R C0402

BAT_STATE_LED

C475

1000pF/50V,X7R C0402

PWR+

C476

1000pF/50V,X7R C0402

6 5 4 3 2 1

6 5 4 3 2 1

+V5S TPCLK TPDAT

C

29 29

TP_POWERLED# R711 10K R0402 ns

H8 H1

H2

H4

H6

H9

H7

HOLE TH_256_118

HOLE TH_256_118

HOLE TH_256_118

HOLE TH_256_118

HOLE TH_256_118

HOLE TH_256_118

B

HOLE TH_256_118

ns

ns

ns

ns

ns

1

1

1

1

1

1

1

B

ns

CASE_GND

HOLE TH_200_118

HOLE TH_200_118

1

H5

1

H3

A

ns

ns GND_USB

GND_BAT

A

TOPSTAR TECHNOLOGY

ns

Swain Xu Page Name Size A3

Project Name

MDC/SSD Rev A

N01

Date: Wednesday, July 16, 2008 Sheet 27 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

+V1.05S +V3.3S +V3.3AL

6,7,8,9,11,12,17,20,35,36,37 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,29,30,35,36,37,39 15,17,18,19,20,23,24,25,27,29,30,31,32,33,34,35,36,37,39

D

D

+V3.3S +V1.05S R362 10K R0402

R363 4.7K R0402 ns SHDN_LOCK#

ALT_ON

6

3 R370 100K R0402 ns

2

C298 0.1uF/10V,X5R C0402 ns

1

5

ns

4

7,10,17 PM_THRMTRIP# Q18 2N7002E-T1 SOT23

1 R372 100K R0402

SHDN_LOCK# 36

R369 470 R0402

2

29

R367 4.7K R0402 ns

2 Q17 MMDT3904 SC70_6

3

4

R366 100K R0402

C

C297 1000pF/50V,X7R C0402

1

5

7 OVT_SHUTDOWN#

R368 100 R0402 ns

6

3

R365 10K R0402

R371 1K R0402 ns

Q19 MMDT3904 SC70_6 ns

C

C299 2.2uF/10V,X7R C0805 ns

OVP CIRCUIT

B

B

VIN

CPU THRMTRIP# AND

SHDN#

THERM_ALERT# Thermal sensor

VDC

TOPSTAR TECHNOLOGY Swain Xu Page Name

A

Size A4

Project Name

MDC&BT/FAN/OTP

A

Rev A

N01

28 42 of Date: Wednesday, July 16, 2008 Sheet PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

4

3

+V3.3S +V3.3AL +V5S +VDC

+V5S

3

EC_RESET#

RCIN#

6 PCI_CLK_EC 17,23 LPC_FRAME#

1

19 PM_CLKRUN#

+V3.3AL R376 4.7K R0402

EC_LPCSTS

R448 4.7K R0402

EC_PCI_RST#

1 3 5 7

RN6 4.7K RA0402_8 2 4 6 8

SCANIN3 SCANIN2 SCANIN1 SCANIN0

7 5 3 1

8 6 4 2

SCANIN4 SCANIN5 SCANIN6 SCANIN7

10,18,19,23,24,30

BUF_PLT_RST#

EC Input Signal! R391 0

R0402 EC_BUF_PLT_RST#

Fuction P.M2 P.M1 P.M0

19

EXT_SMI#

A20GATE RCIN#

62 63 64

GP46/CLKRUN# GP45/GATE_A20 GP44/KBRST#

104 105 106 107 108 109 110 111

DA2/GP57 DA1/GP56

23 49 78

113 114

SET_I IVT_I_ADJ

40 15

GP24/PWM0 GP25/PWM1 GP26/PWM2 GP27/PWM3

73 72 71 70

BTL_BEEP 26 POWERLED# 27 FAN1_V 25 EC_BKLT_PWM 15

AVCC

GP30/M_KR0/(FD0) GP31/M_KR1/(FD1) GP32/M_KR2/(FD2) GP33/M_KR3/TS(FD3) GP34/M_KR4/ALE(FD4) GP35/M_KR5/FWEN#/(FD5) GP36/M_KR6/FOEN#/(FD6) GP37/M_KR7/FCEN#/(FD7) GP00/M_KC0/FD0 GP01/M_KC1/FD1 GP02/M_KC2/FD2 GP03/M_KC3/FD3 GP04/M_KC4/FD4 GP05/M_KC5/FD5 GP06/M_KC6/FD6 GP07/M_KC7/FD7 GP10/M_KC8/FA8 GP11/M_KC9/FA9 GP12/M_KC10/FA10 GP13/M_KC11/FA11 GP14/M_KC12/FA12 GP15/M_KC13/FA13 GP16/M_KC14/FA14 GP17/M_KC15/FA15 GP20/nM_KC16 GP21/nM_KC17 GP22/nM_KC18 GP23/nM_KC19

GP70/KPS2_CLK GP71/KPS2_DAT GP72/MPS2_CLK GP73/MPS2_DAT GP74 GP75

48 47 46 45 44 43

GP76/SDA0 GP77/SCL0 GP80/SDA1 GP81/SCL1

42 41 40 39

CNTR0/GP82 CNTR1/GP83 CIR_RX/GP84

38 37 36

TIMER IR

15,25 LIDR# 19,23,24,30 PCIE_WAKE# 31 32

R428 10K R0402

LABEL1 Topstar Soft BIOS Ver: X.XX EC Ver: X.XX XXXX年XX月XX日

15,19 PM_SUS_STAT# +V3.3AL

R434

1

Q26 2N7002E-T1 SOT23 EC Input Signal!

2

3

R454 0

5

PROCHOT#

R432 1K R0402 31 37 34 34 35 35 39 28

+V5S

7 EC_PROCHOT#

EXTINT20/GPB0 EXTINT21/GPB1 EXTINT22/GPB2 EXTINT23/GPB3 EXTINT24/GPB4 EXTINT25/GPB5 EXTINT26/GPB6 EXTINT27/GPB7

19,36 PM_RSMRST# 25 PWRSW# 19,36 PM_SLP_S3# 19,37 PM_SLP_S4# 36 MAIN_PWROK 10,19,39 IMVP_PWRGD

BIU configuration should match flash speed used EC/BIOS Label 740621500101 A

14 R431 1K R0402 13 12 11 10 9 EC_BUF_PLT_RST# 8 0 R0402 EC_PM_SUS_STAT#7

AC_IN BATT_IN#

ALWAYS_ON MAIN_ON V1_8_ON V0_9S_ON V1_05S_ON V1_5S_ON IMVP_ON ALT_ON

R437 1K

6 5 4 3 2 1 R0402 128 127

EXTINT30/GPC0 EXTINT31/GPC1 EXTINT32/GPC2 EXTINT33/GPC3 EXTINT34/GPC4 EXTINT35/GPC5 EXTINT36/GPC6 EXTINT37/GPC7

BAT_TEM

GP42/RXD GP43/TXD

66 65

SCS/GP50 MOSI/GP51 MISO/GP52 SCK/GP53

121 120 119 118

GP47 GP54 GP55 GP85 GP86 GP87 GP90 GP91 GP92 GP93 GP94 GP95 GP96 GP97

61 117 116 35 34 33 31 30 29 28 27 26 25 24

FAN_TACH

RTC CLK

ns ICTP

EC_IR_IN

R446 0

R0603

TPCLK 27 TPDAT 27 CAM_PWRON 15 HW_RATIO_OFF1#

10K 10K 10K 10K 10K 10K

BAT_TEM

R388 10K R0402

CHG_ON

R390 10K R0402

R0402 R0402 R0402 R0402 R0402 R0402

C312 3300pF/50V,X7R C0402

23

7 7 32 32

EC_V3.3AL EC_V3.3AL EC_SPI_SCK EC_SPI_MOSI

EC_SPI_CS# EC_SPI_MOSI EC_SPI_MISO EC_SPI_SCK

PROCHOT#

10K R0402 10K R0402 10K R0402 10K R0402 4.7K R0402 4.7K R0402 5.6K R0402 5.6K R0402 10K R0402 10K R0402 10K R0402 10K R0402 10K R0402 10K R0402 10K R0402 10K R0402 10K R0402 10K R0402 10K R0402

C

ns

ns

8 7 6 5

VCC HOLD# CLK D

1 2 3 4

CS# Q W# VSS

EC_SPI_CS# EC_SPI_MISO EC_V3.3AL

U12 W25X80A SOIC8_50_208

B

ns

EC_RUNTIME_SCI# 19 BTL_LED# 27 CHG_LED# 27 HW_RATIO_OFF2# 24

AC_OFF

R393 R392 R396 R395 R397 R398 R399 R400 R401 R422 R403 R405 R410 R409 R413 R415 R416 R421 R424

LVDS_BKLTEN 10,15 EC_DEBG_Enable 23

PM_PWRBTN# 19 EC_PWROFF# 19 AMP_SHDW 26 CHG_ON BAT_OV_REV

40 32

XOUT24M

C315 22pF/50V,NPO C0402

R449 200,1% R0402

HW_OFF_BKLT# 15

EC_FAN_BACK

XIN XOUT

123 122

XIN24M XOUT24M

XCIN XCOUT

126 125

TEST#

124

ALW_PWROK 33 1 D19 1N4148WS

FAN_BACK

Y4 24MHZ XS2

25 XIN24M

SOD323 R435 100K R0402

R452 1M R0603

C318 22pF/50V,NPO C0402

+V3.3AL TEST#

R440 4.7K R0402

A

TOPSTAR TECHNOLOGY

R0402 ns

Swain Xu

W83L951DG

Stuff for DG burn BIOS ROM, Place near to keyboard connector.

Page Name

KBC(W83L951ADG)

Size A3

N01

Project Name

Rev A

Date: Wednesday, July 16, 2008 Sheet 29 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

R0402 ns

4

R380 R381 R384 R386 R385 R387

EC_SPI_CS# EC_SPI_MOSI EC_SPI_MISO EC_SPI_SCK I2C_CLK I2C_DATA SM_BAT_SDA2 SM_BAT_SCL2 LIDR# EC_IR_IN EC_PWROFF# PCIE_WAKE#_EC VOLUP VOLDM MEDIA MUTE ALT_ON PWRSW# AC_OFF

EC_DEBG_URXD 23 EC_DEBG_UTXD 23

R438 0 The 0ohm RES will across the isolate island of anolog GND and digital GND

NB_OVT# AD7 AD6 HDD_ZOUT HDD_YOUT HDD_XOUT

SYS_I_Sense

OV_BAT_ALART 32

I2C_DATA I2C_CLK SM_BAT_SDA2 SM_BAT_SCL2

68 67

GP40/FAN_TACH0 GP41/FAN_TACH1

SYSTEM CLK

T42

GND GND GND

R419 10K R0402 ns PCB_Mark0 PCB_Mark1 PCB_Mark2

R423 1K R429 0

55 69 32

0

GPIOA

1

1

EXTINT10/GPA0 EXTINT11/GPA1 EXTINT12/GPA2 EXTINT13/GPA3 EXTINT14/GPA4 EXTINT15/GPA5 EXTINT16/GPA6 EXTINT17/GPA7

GPIOB

0

0

22 21 20 19 R0402 18 R0402 PCIE_WAKE#_EC17 ns 16 15

GPIOC

R427 10K R0402

0

Verc

MEDIA MUTE VOLUP VOLDM

AGND

R426 10K R0402

R418 10K R0402 ns

0

GPIO

R417 10K R0402 ns

0

115

+V3.3AL

0

C307 0.1UF/25V,Y5V C0402

+V3.3AL

B

VerA VerB

C317 100pF/50V,NPO C0402

AD7 AD6 NB_OVT# HDD_ZOUT HDD_YOUT HDD_XOUT 40

SPI

CNS26_1_R_UP ACES 85201-2402 KBCON1

EC_LPCSTS

AD7/GP67 AD6/GP66 AD5/GP65 AD4/GP64 AD3/GP63 AD2/GP62 AD1/GP61 AD0/GP60

SYS_I_Sense

UART

RA0402_8 4.7K RN9

C316 100pF/50V,NPO C0402

PS/2

+V3.3AL

C306 0.1UF/25V,Y5V C0402

Should have a 0.1uF capacitor close to every GND-VCC pair + one larger cap on the supply.

LQFPS128_0D4_1D6 U29

RESET#

LCLK LFRAME# LRESET# SERIRQ LAD0 LAD1 LAD2 LAD3 LPCSTS

SCANIN0 102 SCANIN1 101 SCANIN2 100 SCANIN3 99 SCANIN4 98 SCANIN5 97 SCANIN6 96 SCANIN7 95 SCANOUT0 94 SCANOUT1 93 SCANOUT2 92 SCANOUT3 91 SCANOUT4 90 SCANOUT5 89 SCANOUT6 88 SCANOUT7 87 SCANOUT8 86 SCANOUT9 85 SCANOUT10 84 SCANOUT11 83 SCANOUT12 82 SCANOUT13 81 SCANOUT14 80 SCANOUT15 79 PCB_Mark0 77 PCB_Mark1 76 PCB_Mark2 75 R420 0 R0402 ns 74

C305 0.1UF/25V,Y5V C0402

D

PWM

C

EC_RESET# TEST#

C304 0.1UF/25V,Y5V C0402

PM_SLP_S3#

51 52 53 54 56 57 58 59 60

EC_PCI_RST#

C303 0.1UF/25V,Y5V C0402

PM_SLP_S4#

W83L951DG

27 28

R404 0 R0402 R406 0 R0402 SCANOUT15 SCANOUT14 SCANOUT13 SCANOUT12 SCANOUT11 SCANOUT10 SCANOUT9 SCANOUT8 SCANOUT7 SCANOUT6 SCANOUT5 SCANOUT4 SCANIN0 SCANOUT3 SCANIN1 SCANIN2 SCANOUT2 SCANOUT1 SCANIN3 SCANIN4 SCANIN5 SCANOUT0 SCANIN6 SCANIN7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

19 INT_SERIRQ 17,23 LPC_AD0 17,23 LPC_AD1 17,23 LPC_AD2 17,23 LPC_AD3

+V3.3AL

SMBUS

D22 1N4148WS SOD323

50

C302 10UF/6.3V,X5R C0805

C310 0.1UF/25V,Y5V C0402

VREF

Q22 2N7002E-T1 SOT23 ns

EC Output Signal!

1 2 3 4 27 5 28 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

C309 0.1UF/25V,Y5V C0402

KB ARRAY

R382 10K R0402 2

H_RCIN#

R383 10K R0402

Stuff for DG burn BIOS ROM, Place near to keyboard connector.

ANALOG

17

R379 0 R0402 C311 ns 0.01uF/25V,X7R C0402

+V5S

1

+V3.3S

Q21 MMBT3904-F SOT23

R377 0 R0805

EC_V3.3AL

VCC1 VCC1 VCC1

D21 1N4148WS SOD323

1

100,1% 1 R0402

112

R739

EC Output Signal!

103

A20GATE

3

FB27 120ohm/100MHz,500mA FB0603 EC_V3.3AL 1 2

EC_RESET#

HOST BUS

2

H_A20GATE

D

C308 4.7UF/10V,Y5V C0805

3

Q20 2N7002E-T1 SOT23 ns

2

17

1

R373 8.2K R0402

R375 10K R0402

6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,30,35,36,37,39 15,17,18,19,20,23,24,25,27,30,31,32,33,34,35,36,37,39 15,16,19,20,21,25,26,27,35,37,38,39 15,23,25,31,33,34,35,37,39

1

2

EC_V3.3AL +V3.3S

2

1

5

3

2

1

5

4

3

2

1

Power domain chart R658 3.6K

R0402

C

BUF_PLT_RST#

19,23,24,29 PCIE_WAKE# +V3.3S

R660 1K

CS SK DI DO

VCC NC1 NC2 GND

C419 C420 10UF/6.3V,X5R 10UF/6.3V,X5R C0805 C0805 ns

VCTRL15 VCTRL18

63 1

MDIP0 MDIN0 MDIP1 MDIN1 NC1 NC2 NC4 NC5

3 4 6 7 9 10 12 13

CKTAL2 CKTAL1

61 60

LANWAKEB

36

ISOLATEB

R661 15K R0402

54 55 56 57

LED3 LED2 LED1 LED0

64

RSET NC20

25 31

C422 0.1uF/10V,X5R C0402

C423 0.1uF/10V,X5R C0402

C424 0.1uF/10V,X5R C0402

AVDD18

R666 49.9,1% R0402

C426 0.1uF/10V,X5R C0402

AVDD18 R667 49.9,1% R0402 C433 10UF/6.3V,X5R C0805 ns

C447 0.01uF/25V,X7R C0402

DVDD15 AVDD18 LAN_TX0+ LAN_TX0LAN_TX1+ LAN_TX1-

LAN_TX0-

LAN_TX0+

14 11 8 5

PERSTB

C421 0.1uF/10V,X5R C0402

48 47 45 44 NC6 NC3 AVDD18_02 AVDD18_01

19

VDD3D3_LAN

C425 0.1uF/10V,X5R C0402

EESK EEDI EEDO EECS

HSIP HSIN HSOP HSON

R0402

R662 2K,1% R0402 RSET

52 49 43 41 38 32 21 15

28 22

20

If use 8102E, R662 install 2.49K 1% Swain 080709 62

NC18 VDD15_07 VDD15_06 NC14 NC11 NC7 VDD15_02 VDD15_01

EVDD18_02 EVDD18_01

C434 10UF/6.3V,X5R C0805

C435 0.1uF/10V,X5R C0402

C437 0.1uF/10V,X5R C0402

C438 0.1uF/10V,X5R C0402

C439 0.1uF/10V,X5R C0402

Place close to AVDD18 PINS.

Place close to AVDD18 Power Output PIN1

Place Close to Chip

C436 0.1uF/10V,X5R C0402

C

DVDD15

Y6 25MHz XS2

1

NC17 NC16 NC15 NC13 NC12 NC10 NC9 NC21 NC22

10,18,19,23,24,29

23 24 0.1UF/10V,X7RC040229 0.1UF/10V,X7RC040230

C430 C428

REFCLK_P REFCLK_N

EGND1 EGND2

PCIE_TXP0_LAN PCIE_TXN0_LAN PCIE_RXP0_LAN PCIE_RXN0_LAN

2 300ohm@100MHz,1.5A ns FB0805

1

Place close to VDD33_LAN PINS.

C440 10UF/6.3V,X5R C0805

2

C442 27pF/50V,NPO C0402

51 50 42 40 39 35 34 18 17

26 27

6 CLK_PCIE_LAN 6 CLK_PCIE_LAN#

58 33

U38 RTL8101E QFNS64_0D5_1G

18 18 18 18

D

8 7 6 5

93C46 so8_50_150

VDD15_10 NC8

1.5V 59 2

DVDD15

1 2 3 4

2 300ohm@100MHz,1.5A FB0805

FB33

U37 EECS EESK EEDI/AUX EEDO

NC19 AVDD33_01

1.8V

DVDD15

GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9

EVDD18

FB9 1

+V3.3AL

ns

+V3.3S

VDD3D3_LAN

G1 G2 G3 G4 G5 G6 G7 G8 G9

1.8V

R659 10K R0402 10K is used only when 93C56 is used.

53 46 37 16

AVDD18

6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,35,36,37,39

VDD3D3_LAN

VDD33_04 VDD33_03 VDD33_02 VDD33_01

D

3.3V

15,17,18,19,20,23,24,25,27,29,31,32,33,34,35,36,37,39

+V3.3S +V3.3AL

RTL8101E

AVDD33

+V3.3AL

C451 10UF/6.3V,X5R C0805 ns

C443 27pF/50V,NPO C0402

C453 0.1uF/10V,X5R C0402

C454 0.1uF/10V,X5R C0402

C446 0.1uF/10V,X5R C0402

C455 0.1uF/10V,X5R C0402

Place close to DVDD15

Place close to DVDD15 Power Output PIN63

C456 0.1uF/10V,X5R C0402

PINS

AVDD18

TD-

TX-

8

TX0MCT1

11

TDC

CMT

6

LAN_TX0+

10

TD+

TX+

7

TX0+

LAN_TX1-

15

RD-

RX-

2

TX1-

RDC

RXC

3

MCT2

RX+

1

TX1+

C463 0.01uF/25V,X7R C0402

16

RD+

1CT:1CT

14 LAN_TX1+

1 3 5 7

TX1TX1+ TX0TX0+

4 3 2 1

9

9

CASE_GND

RN15 0x4 RA0603_8 2 4 6 8

RJ45_TX0+ RJ45_TX0RJ45_TX1+ MCT3

CHK5 90ohm@100MHz CMC8 ns L2+ L3+ 5 L2L3- 6 L1+ L4+ 7 L1L4- 8

RJ45_TX1RJ45_TX1+ RJ45_TX0RJ45_TX0+

1 2 3 4 5 6 7 8

RJ45_TX1-

B

MCT4

TX0+ TX0TX1+ TX2+

TX0+ TX0TX1+ TX2+ TX2TX1TX3+ TX3-

TX2TX1TX3+ TX3-

10

C465 0.01uF/25V,X7R C0402

VDD3D3_LAN

6

4

LD9 AZC099-04S SOT23_6 ns

LAN_TX1-

5

LAN_TX1-

LAN_TX1+

LAN_TX1+

R692 75 R0402

R693 75 R0402

R694 75 R0402

R695 75 R0402

CASE_GND

C498 1000pF/2000V C1206

C464

330pF/50V,X7R C0603

C466

4.7uF/10V,Y5V

C467

330pF/50V,X7R C0603

Page Name

RTL8101E/8111C(GLAN)

C468

330pF/50V,X7R C0603

Size A3

N01

CASE_GND

5

A

R669 49.9,1% R0402

C448 0.01uF/25V,X7R C0402

4

TOPSTAR TECHNOLOGY

CASE_GND

1

R668 49.9,1% R0402

2

C0805

3

A

J5 RJ45 RJ45_S

RJ45

MCT4

5 4

MCT3

N2 N1

MCT2

LAN_TX0-

N4 N3

1CT:1CT

B

13 12

MCT1

U39 TRAN16_50_272 R348 0 R0402

LAN_TX0+

Rev A

Date: Wednesday, July 16, 2008 Sheet 30 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained with the expressed written consent of TOPSTAR

LAN_TX0-

3

Project Name

2

1

BATT+ +V3.3AL +VDC

change from

PR1 5.1K R0402

32,40 15,17,18,19,20,23,24,25,27,29,30,32,33,34,35,36,37,39 15,23,25,33,34,35,37,39

15k to 12k 0417

PR2 12K R0402

PR3 10 R0402

3A

1

PFB1 100ohm@100MHz,3A FB0805 1 2

3A

PR4 0.025,1% R2512

3A

1

PQ2 AO4419 SO8_50_150

5A

S

PF1 7A FUSE1206 1 2

ns

PD1 SSM34PT SMA

G

AD+

D

PC1 0.1uF/25V,X7R C0603

4

ALW_EN POWER_HOLD Hole+Dowel TH_61_45

3 2 1

5A

5 6 7 8

BATT+

1

2

PD2 SSM34PT SMA

PFB2 100ohm@100MHz,3A FB0805 GND_HOLD Hole+Dowel TH_61_45 ns

40 PC5 1uF/25V,Y5V C0805

PC3 0.1uF/25V,Y5V C0402

Isense_SYSP

36,40 Isense_SYSN

5A

1 2 3

PQ3 S AO4419 SO8_50_150 G

铜皮连接 Jack_GND

PR10 510K R0402

PC7 1000pF/50V,X7R C0402

23,25 PWR_SW_VCC2 AC_IN

2

PR11 51K R0402

+VDC

D PC6 0.01uF/25V,X7R C0402

PR15 20K R0402

PR12 1K R0402

29 29

ALWAYS_ON

3

PD5 1N4148WS SOD323

PQ4 2N7002 SOT23

1

5A

32,36

1

2

PC9 1000pF/50V,X7R C0402

3 ALW_EN

PQ7 2N7002 SOT23

SHDN#

1 PR144 1K R0402

2

PR9 20K R0402

8 7 6 5

PR135 0 R0402

+V3.3AL

3

AD+

PD3 SSM34PT SMA

4

1

PC4 1uF/25V,Y5V C0805

1

1

1 PD4 BAT54C SOT23

PR18 100K R0402

TOPSTAR TECHNOLOGY Mayc Page Name

ADAPTER IN

Size A3

N01

Project Name

Rev A

Date: Wednesday, July 16, 2008 Sheet 31 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

BATT+ +V3.3AL

BATT+

PFB5 100ohm@100MHz,3A 1 2 FB0805

PC10 1000pF/50V,X7R

29 SM_BAT_SDA2

PF2 7A FUSE1206 1 2

7 C157 0.1uF/25V,Y5V C0402 ns 6

GND_BAT

SM_BAT_SDA2

PR20 100 R0402

SM_BAT_SDA

SM_BAT_SCL2

PR19 100 R0402

SM_BAT_SCL

BATT+ BAT_B1

BAT_B2

Screw 2*8mm Assembly 711000000013

Screw 2*8mm Assembly 711000000013

KEY SDAT SCLK

5 4

TEMP

3

BAT_IN#

2

GND

1

GND

8

29 SM_BAT_SCL2

GND_BAT

5A

9

5A

BATCON1 BATT_CONN BATJ7_MC

PD6 1N4148WS SOD323

29 BAT_OV_REV

1

PFB4 100ohm@100MHz,3A 1 2 FB0805

31,40 15,17,18,19,20,23,24,25,27,29,30,31,33,34,35,36,37,39

ns

31,36

SHDN#

+V3.3AL

GND_BAT

2

+V3.3AL

3

1

PQ8 2N2907 SOT23 ns

3

PR22 1K R0402 BATT_IN#

SM_BAT_SDA2

29

PQ9 2N2222 SOT23 ns

PR23 1K R0402 ns

PR24 51K R0402

1 2

PR21 300K R0402

PR25 2K R0402 ns

PC11 0.1UF/25V,X7R C0603 ns

OV_BAT_ALART 29

SM_BAT_SCL2 PR26 0 R0402 layout注意将此部分电路尽量放在板子上不热的地方 PC12 5.6pF/50V,NPO C0402

PC13 5.6pF/50V,NPO C0402

PR27 0 R0402

Battery Over Voltage Protection

PR28 0 R0402 GND_BAT

GND_BAT GND_BAT

PZD1 BAT54S SOT23

+V3.3AL

+V3.3AL

PZD2 BAT54S SOT23

2 PC14 0.1uF/25V,Y5V C0402

3 1

2

SM_BAT_SDA PC15 0.1uF/25V,Y5V C0402

3

SM_BAT_SCL

1

GND_BAT

TOPSTAR TECHNOLOGY

GND_BAT Page Name

BATTERY IN

Size A3

N01

Project Name

Mayc

Rev A

Date: Wednesday, July 16, 2008 Sheet 32 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

5

4

mayc for L6783

3

0320

PR164 0 R0402

+V3.3AL +V5AL +VDC

PD33 1N4148WS SOD323

2

1

15,17,18,19,20,23,24,25,27,29,30,31,32,34,35,36,37,39 15,20,22,25,34,36,37 15,23,25,31,34,35,37,39

1 ns

ns +VDC

+V5AL

D

BOOT

1

PC16 4.7uF/10V,X5R C0805

PC17

3

PR165 20K R0402 ns

GND

PHASE

PC18 1000pF/50V,X7R C0402

0.1uF/25V,Y5V C0402

8

D

PR145 0 R0402

2

3 2 1

UGATE

PR32 5.11K,1% R0402 PU1 ISL6545 SOIC8_50_150

mayc for L6783

29 ALW_PWROK

V3_3AL TestP TPC60 ns

PD9 BZT52C3V6S-F/3.6 SOD323

2

3 2 1

PQ61 AO4468 SO8_50_150

LS2_1040 PD27 1N5819 + SOD123 ns PC134 220UF/6.3V,OSCON CAP6_6x7_3

1

S

PR31 1K,1% R0402

C

+V3.3AL

1

4

4

1

LGATE

G

PC22 47pF/50V,NPO C0402 6 FB

1

5.2uH/5.5A

D

PR146 0 R0402

2A

PL1

5 6 7 8

PR29 20K R0402 PC23 0.022uF/16V,X7R C0402

PR30 100K R0402

S

COMP/SD

+V3.3AL PQ60 AO4468 SO8_50_150

G

4 7

PC21 4.7uF/25V,X7R C1206

PC19 0.1uF/25V,X7R C0603

2

VCC

ALW_PWROK

1

5

5 6 7 8

D

C

PC117 0.1uF/10V,X5R C0402

PR33 4.53K,1% R0402

0320

PR166 0 R0402

PD34 1N4148WS SOD323 1

ns

ns

+VDC

+VDC

VCC

BOOT

1

PC27 1000pF/50V,X7R C0402

0.1uF/25V,Y5V C0402

PHASE

8

COMP/SD

UGATE

PQ62 AO4468 SO8_50_150 S

4

PR35 412,1% R0402

PR36 6.34K,1% R0402

PU2 SOIC8_50_150 ISL6545

PD12 BZT52C5V6S-F/5.6 SOD323

+

1

3 2 1

PQ63 AO4468 SO8_50_150

1

S

PD29 1N5819 SOD123 ns

2

4

1

LGATE

+V5AL

5.2uH/5.5A LS2_1040

G

PC31 47pF/50V,NPO C0402 6 FB

1

D

PR148 0 R0402

3A

PL2

5 63 72 81

PR34 20K R0402

PC32 0.022uF/16V,X7R C0402

4

2

G

7

D

PR147 0 R0402

2

GND

B

PC28 0.1uF/25V,X7R C0603

1

3

PR167 20K R0402 ns

PC30 4.7uF/25V,X7R C1206

PC26

5 6 7 8

5 PC25 4.7uF/10V,X5R C0805

B

PC135 220UF/6.3V,OSCON CAP6_6x7_3

V5AL TestP TPC60 ns

PC118 0.1uF/10V,X5R C0402

PR37 3.01 KOHM +/-1% R0402

A

A

TOPSTAR TECHNOLOGY Page Name

+V3.3V +V5V ALWAYS

Size A3

N01

Project Name

Mayc

Rev A

Date: Wednesday, July 16, 2008 Sheet 33 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

4

+V0.9S

3

+V0.9S +V5AL +V3.3AL +VDC +V1.8

2.5A

+V1.8

2A +VDC PC40 4.7uF/25V,X7R C1206

D

10K

R0402

12

200K

R0402

2A +V0.9S PC45 PC46 10uF/6.3V,X5R10uF/6.3V,X5R C0805 C0805 ns

S3

COMP

8

S5

VDDQSET

10

CS

15

V5IN

14

PGOOD

13

PGND

16

4

VTTSNS

2

VTT

3

VTTGND

5

GND

21 2

1

ns V1_8_ON

+V3.3AL

5A

5A +V1.8

1

500mA 0

5 6 7 8

R0402 PR77

4

D-CAP

PL3

PC44 1000pF/50V,X7R C0402

PC43 C0402 0.1uF/10V,X7R

3.3uH/4.8A LS2_8836 AO4468 PQ15

PD13 SSM34PT SMA

F_5VAL

PC136 220UF/6.3V,OSCON CAP6_6x7_3

PZ1 BZT52C2V0S-F/2.0V SOD323

PR44 R0402 10

PR43 R0402 20K PR45 100K R0402 ns

+

+V5AL PC47 4.7uF/10V,X5R C0805

+V3.3AL

C

F_5VAL

TGND

DDR_GND

17

D

V1_8 TestP TPC60 ns

1

PR39

V0_9S1 TestP TPC60

5A

18

DRVL

VTTREF

1

1

11

PL8 2.2UH/14A LS2_6530 ns

1

R0402 R0402

LL

S

10K 200K

PR42

C

7

PR40 PR41

MODE

AO4468 PQ14

G

V1_8_ON

PR38 10K

D

29

PR76 R0402

3 2 1

6 DDR_GND

V0_9S_ON

DRVH

0

500mA

PC38 0.1uF/10V,X7R C0402

29

VDDQSNS

19

1

9

10,14 SM_VREF_L

4

S

500mA

PC37 1000pF/50V,X7R C0402

2

VBST

3 2 1

VLDOIN

PC41 0.1uF/25V,X7R C0603

20

PC36 0.1uF/25V,X7R C0603

G

1

5 6 7 8

PU3 TPS51116 SOP20_0D65_4D4G

D

PC34 0.1UF/10V,X7R C0402

1

14,37 15,20,22,25,33,36,37 15,17,18,19,20,23,24,25,27,29,30,31,32,33,35,36,37,39 15,23,25,31,33,35,37,39 10,12,14,36,37

DDR2用电源

PC35 4.7uF/10V,X5R C0805

14,37

2

2

5

400KHz

DDR_PWG

DDR_PWG

PC48 1uF/10V,X7R C0603

R0402 PR46 0

PJ2 JOPEN RESISTOR_1 ns

36

DDR_GND +V3.3AL +V5AL

DDR_GND

DDR_PWG

PR49 1K R0402

PQ16 2N7002E-T1-E3 SOT23

B

J4 JOPEN RESISTOR_1 ns

3

2

2

1

1

B

PR47 51K R0402

3

+V0.9S

PR48 20K R0402

PQ17 MMBT2222A SOT23

2

1

PR50 20K R0402

A

TOPSTAR TECHNOLOGY

Mayc

Swain Xu Page Name

+V1.8/+V0.9S DDR

Size A3

N01

Project Name

Rev A

Date: Wednesday, July 16, 2008 Sheet 34 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

A

5

4

3

2

1

+V3.3AL +V3.3S +VDC +V1.5S +V1.05S +V5S

15,17,18,19,20,23,24,25,27,29,30,31,32,33,34,36,37,39 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,36,37,39 15,23,25,31,33,34,37,39 8,10,11,12,20,23,24,36,37 6,7,8,9,11,12,17,20,28,36,37 15,16,19,20,21,25,26,27,29,37,38,39

D

D

mayc for L6783

0320

PR168 0 R0402

PD35 1N4148WS SOD323 1

ns

ns

+V5S

+VDC

VCC

BOOT

1

GND

PHASE

8

PC49 4.7uF/10V,X5R C0805 PR169 20K R0402 ns

3

PC51 1000pF/50V,X7R C0402

+V3.3AL

3 2 1

+V1.5S

2 1

PD16 SOD323 BZT52C2V0S-F/2.0V

+

1

2

3 2

PR55 6.34K,1% R0402

V1_5S TestP TPC60 ns

PC121 PC138 0.1uF/10V,X5R C0402 220UF/6.3V,OSCON CAP6_6x7_3

ISL6545 SOIC8_50_150 PU4

PR172 30K R0402

C

PR57 3.01 KOHM +/-1% R0402

PC137 0.1uF/25V,Y5V C0402 ns

+V3.3AL

4

PQ66 AO4468 SO8_50_150 PR54 2K,1% R0402

1 2

J7 JOPEN RESISTOR_1 ns

4

1

C

LGATE

3A

1

PC56 0.022uF/16V,X7R C0402

080716VA:Co_lay.

PL4 3.3uH/4.8A PD30 LS2_8836 1N5819 SOD123 ns

S

V1_5S_ON

PC55 47pF/50V,NPO C0402 6 FB

G

1

C1206 4.7uF/25V,X7R

1

5 6 7 8

3 PQ65 2N7002 SOT23

PC54

PL10 2.2UH/14A LS2_6530 ns 1

PR152 0 R0402

D

29

2

PR51 20K R0402

PQ67 MMBT3904-F

1

UGATE

PC52 0.1uF/25V,X7R C0603

S

PR170 4.7K R0402

COMP/SD

PQ64 AO4468 SO8_50_150

G

4 7

PR171 1K R0402

D

PR150 0 R0402

2

0320

3 2 1

mayc for L6783

1.5A

PC50 0.1uF/25V,Y5V C0402

5 6 7 8

5

mayc

0324

Enable

+V3.3AL +V3.3S

PR52 10K R0402

signal

PR53 10K R0402 ns

CHIPPWROK#

CHIPPWROK

3

PR60 1K R0402

1

PR173 0 R0402

B

PR59 100K R0402

0320

2

+V1.05S mayc for L6783

CHIPPWROK#

1

2 4

5 PR58 100K R0402

36

PQ20 MMDT3904 SC70_6

6

3

+V1.5S

PR56 1K R0402

PQ21 MMBT2222A SOT23

PD36 1N4148WS SOD323

B

1 ns

ns

+V5S

+VDC

PC58 4.7uF/10V,X5R C0805

2

PR156 0 R0402

4

4

2

0324

Enable

080716VA:Co_lay.

3A

1

+

1

3 2 1

PD31 1N5819 SOD123 ns

+V1.05S

V1_05S TestP TPC60 ns

PC124 0.1uF/10V,X5R PC140 C0402 220UF/6.3V,OSCON CAP6_6x7_3 PD19 SOD323 BZT52C2V0S-F/2.0V

PR64 3.01 KOHM +/-1% R0402

PC139 0.1uF/25V,Y5V C0402 ns

1

PL5

PR63 6.34K,1% R0402

PU5 SOIC8_50_150 ISL6545

PC63 4.7uF/25V,X7R C1206

PL11 2.2UH/14A LS2_6530 ns

1

PQ70 AO4468 SO8_50_150 PR62 4.02K,1% R0402

PC61 0.1uF/25V,X7R C0603

3.3uH/4.8A

1

LGATE

PC65 0.022uF/16V,X7R C0402

2

PQ68 AO4468 SO8_50_150

5 63 72 81

3

4

S

3

5 6 7 8

UGATE

G

1

COMP/SD

D

2

7

PC64 47pF/50V,NPO C0402 6 FB

PR177 30K R0402

mayc

+V3.3AL

8

S

A

J8 JOPEN RESISTOR_1 ns

PHASE

G

PR176 1K R0402

GND

PR61 20K R0402

PQ71 MMBT3904-F

1

V1_05S_ON

3

PR154 0 R0402

PQ69 2N7002 SOT23

1

PC60 1000pF/50V,X7R C0402

D

PR175 4.7K R0402

29

PC59 0.1uF/25V,Y5V C0402

PR174 20K R0402 ns

+V3.3AL

1.5A

1

2

BOOT

1

VCC

2

5

A

signal TOPSTAR TECHNOLOGY Page Name

1.5S 1.05S

Size A2

N01

Project Name

mayc

Rev A

Wednesday, July 16, 2008 35 42 Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,37,39 +V5AL 15,20,22,25,33,34,37 +V3.3AL 15,17,18,19,20,23,24,25,27,29,30,31,32,33,34,35,37,39 +V1.05S 6,7,8,9,11,12,17,20,28,35,37 +V1.5S 8,10,11,12,20,23,24,35,37 +VCC_CORE 8,39 +V1.8 10,12,14,34,37 +VDC 15,23,25,31,33,34,35,37,39

D

D

OVP CIRCUIT

Power Good Logic CIRCUIT

PQ24 DTB114EK SOT23 2 3

+V3.3S 31,40 Isense_SYSN

34

DDR_PWG

28 SHDN_LOCK#

0 R0402

PR71 20K R0402

1

1 3

1 1N4148WS SOD323

19,29 PM_SLP_S3#

+V5AL

5

BZT52C5V6S-F/5.6 PD22 1 1N4148WS SOD323 PC69 0.1uF/10V,X7R C0402

PZ3 2

+V3.3AL

SOD323 1

BZT52C3V6S-F/3.6

6

1 1N4148WS SOD323

3

PR72 1K R0402

SOD323 1

1

PD21

19,29 PM_RSMRST#

PZ2 2

4

C

PC70 1uF/10V,X7R C0603

PR74 100 R0402

PQ27 MMDT3904 SC70_6 2

PC71 1000pF/50V,X7R C0402

PQ25 DTB114EK PC68 SOT23 0.01uF/25V,X7R C0402 1

PQ26 2N7002 SOT23 C

2

PR70 PD20

31,32

PR68 20K R0402

MAIN_PWROK 29

3

CHIPPWROK

PR69 100K R0402

PC67 0.1uF/25V,Y5V C0402

2

35

PR66 1K R0402

SHDN#

PR67 20K

PR65 10K R0402

PR75 20K R0402

PR73 20K R0402

PZ4

2

+V1.8

+V1.5S

+V1.05S

+VCC_CORE

B

1

2

BZT52C2V0S-F/2.0V SOD323 PZ5 1

2

BZT52C2V0S-F/2.0V SOD323 PZ6 1

2

BZT52C2V0S-F/2.0V SOD323 PZ7 1

B

BZT52C2V0S-F/2.0V SOD323

31,40 Isense_SYSN

PR78 1K R0402

PZ8

2

1

BZT52C13S-F/13.0V SOD323

080716VA:新料,料号申请中.

A

A

TOPSTAR TECHNOLOGY

Mayc

Swain Xu Page Name

Power Good logic/OVP

Size A3

N01

Project Name

Rev A

Date: Wednesday, July 16, 2008 Sheet 36 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

+V3.3S +V3.3AL +V5S +V5AL +V1.5S +V2.5S +V0.9S +V1.05S +VDC +V1.8

6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,39 15,17,18,19,20,23,24,25,27,29,30,31,32,33,34,35,36,39 15,16,19,20,21,25,26,27,29,35,38,39 15,20,22,25,33,34,36 8,10,11,12,20,23,24,35,36 12,38 14,34 6,7,8,9,11,12,17,20,28,35,36 15,23,25,31,33,34,35,39 10,12,14,34,36

D

D

1 2 3

PQ50 S PR136 AO4419 510K SO8_50_150 G R0402

PC126 0.01uF/25V,X7R C0402

4

PC125 0.01uF/25V,X7R C0402

1 2 3 PQ51 S AO4419 SO8_50_150 G

+V3.3AL +V5S

D

PC115 0.01uF/25V,X7R C0402

8 7 6 5

PC116 0.01uF/25V,X7R C0402

PR137 510K R0402

PR139 0 R0402

MAIN_PWR_DN#

PR141 30K R0402 29

3

3

PQ52 2N7002 SOT23

1

MAIN_ON

PQ53 2N7002 SOT23

1

PC127 0.1uF/25V,Y5V C0402

MAIN_ON

C

PR142 510K R0402 ns

2

EC

PD38 1N4148WS SOD323 1

2

C

29

+V3.3S

D

PR138 0 R0402

PR140 10K R0402

V3S1 TestP TPC60 ns

4

+V5AL

V5S1 TestP TPC60 ns

8 7 6 5

PC128 0.1uF/25V,Y5V C0402

PR143 510K R0402 ns +V1.8

+VDC

30mA

+V3.3S

50mA

+V0.9S

70mA

+V1.05S PR92 100 R0402

18mA

+VDC

21mA

PR99

10K R0402

1

PR98 510K R0402

PQ39 2N7002 SOT23

1

V1_8DISCHG B

2

2

2

PR94 510K R0402

PR100 510K R0402

1

PR93 100 R0402

1

2

2 PR91 100 R0402

1

1

PR90 100 R0402

1

PR89 100 R0402

PR88 100 R0402

1

PR87 100 R0402

2

2

2

PR86 100 R0402

1

PR85 100 R0402

1

PR84 100 R0402

2

19,29 PM_SLP_S4# B

PQ38 2N7002 SOT23 1

3

+V2.5S

1

V1_8DISCHG +V1.5S

2 PR97 100 R0402

mayc

3

Discharge by

2

Add +V2.5S

2

36mA PR96 100 R0402

3

3

PQ37 2N7002 SOT23

1 2

PQ36 2N7002 SOT23 1

2

3

3

PQ35 2N7002 SOT23

1 2

2

PQ34 2N7002 SOT23 1

2

3

PQ33 2N7002 SOT23

1 2

MAIN_PWR_DN#

PQ32 2N7002 SOT23 1

3

DISCHG

DISCHG PR95 510K R0402

A

A

TOPSTAR TECHNOLOGY Page Name

SYSTEM/DISCHARGE

Size A3

N01

Project Name

Mayc

Rev A

Date: Wednesday, July 16, 2008 Sheet 37 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

+V3.3AL +V2.5S +V5S

1

15,17,18,19,20,23,24,25,27,29,30,31,32,33,34,35,36,37,39 12,37 15,16,19,20,21,25,26,27,29,35,37,39

D

D

PD25

1N4148WS SOD323 1 ns

V25S1 TestP TPC60 ns

3

VIN

1

+V5S

ADJ/GND

PU7 VOUT Vo

2 4

+V2.5S

KIA1117-ADJ SOT223

PR104 301,1% R0402

PC79 10uF/6.3V,X5R C0805

PC80 10uF/6.3V,X5R C0805 PR106 301,1% R0402

C

PR105 1K R0402

C

B

B

TOPSTAR TECHNOLOGY Page Name

A

Size A4

Project Name

Mayc

1.5AL 2.5S

A

Rev A

N01

38 42 of Date: Wednesday, July 16, 2008 Sheet PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

+VDC 15,23,25,31,33,34,35,37 +V5S 15,16,19,20,21,25,26,27,29,35,37,38 +VCC_CORE 8,36 +V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37 +V3.3AL 15,17,18,19,20,23,24,25,27,29,30,31,32,33,34,35,36,37

mayc for L6783

0320

PR178 0 R0402

D

PD37 1N4148WS SOD323

D

1 ns

ns +VDC

+V5S

5 63 72 81 3 2 1

2

C

2

3 2

3

AO4468 PQ41 SO8_50_150

1

2

+VCC_CORE

1

5.2uH/5.5A LS2_1040 PC142 220UF/6.3V,OSCON CAP6_6x7_3

1

S

1

G

2

PL9

D

PR109 6.34K,1% R0402

PC85 10uF/25V,X5R C1210 ns

080716VA:Co_lay.

1

S

4

4

LGATE

PC84 0.1uF/25V,X7R C0603

PL12 2.2UH/14A LS2_6530 ns

PQ40 AO4468 SO8_50_150

G

PR182 30K J9 R0402 JOPEN RESISTOR_1 ns

PR160 0 R0402

PC88 47pF/50V,NPO C0402 6 FB

PC87 0.022uF/16V,X7R C0402

PQ73 MMBT3904-F

PR181 1K R0402

4

2

UGATE

D

PQ72 2N7002 SOT23

1

1

COMP/SD

PR107 20K R0402

C

PC83 1000pF/50V,X7R C0402

0.1uF/25V,Y5V C0402

PR158 0 R0402

7 PR180 4.7K R0402

IMVP_ON

8

PHASE

PR179 20K R0402 ns

+V3.3AL

PC86 4.7uF/25V,X7R C1206

PC82

+

VCORE PD28 TestP SOD323 TPC60 BZT52C3V6S-F/3.6 ns

1

PC81 4.7uF/10V,X5R C0805 3 GND

29

1

BOOT

1

VCC

5 6 7 8

5

PD26 1N5819 SOD123

PC130 0.1uF/10V,X5R C0402

PU8 SOIC8_50_150 ISL6545 PR110 2.49K,1% R0402

PR108 3.01 KOHM +/-1% R0402

PC141 0.1uF/25V,Y5V C0402 ns

+V3.3AL mayc

0324

Enable

signal

B

B

+V3.3S +V3.3AL

PR112 20K R0402

PR111 20K R0402

+VCC_CORE

IMVP_PWRGD 10,19,29 PR116 30K R0402

3 PR117 510K R0402

PC90 0.1uF/10V,X5R C0402

2

PQ42 MMBT2222A SOT23

PQ74 2N7002 SOT23

1

19 CK505_CLK_EN#

2

1 A

3

CK505_CLK_EN# 19

PR113 10K R0402

A

PC91 0.22uF/10V,X7R C0603

TOPSTAR TECHNOLOGY Page Name

+VCC CORE

Size A3

N01

Project Name

Mayc

Rev A

Date: Wednesday, July 16, 2008 Sheet 39 42 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

BATT+

31,32

PU9 PR121

PR119

PC99 0.1uF/25V,Y5V C0402

31,36 Isense_SYSN 10

CSIP

20

CSIN

DCIN

24

UGATE

17

BOOT

16

PR122 R0402

PC101 5600pF/50V,Y5V C0603

ICOMP

ISL6251HAZ

11

0A 400mA 2A

PR125 15.4K,1% R0402

2.39V_Vref PR128 10.5K,1% R0402 0.1 Vref

8

13

CSOP

21

CSON

22

CELLS

4

ICM

7

GND

12

EN

VREF ACLIM

23

ACPRN

PL7 15uH/3.6A LS2_1040

2A

PR124 50mOHM,1% R2512

8.4V PC109 BATT+ 0.1uF/25V,X7R C0603

2A

1

PQ49 AO4468 SO8_50_150

PD39 1N5819 SOD123 ns

PC107

PC108 4.7uF/25V,X7R C1206

VBATS1 TestP TPC60 ns

PC110 1uF/25V,Y5V C0805

10uF/ 25V C1210 ns

PR127

CHLIM

10

2Aphase

1

0V 0.66V 3.3V

充电电流

9

PGND

4

PR126 6.98K,1% R0402

14

VADJ

S

CHG_ON

LGATE

phase

G

3

1N4148WS/75V/150mA PR123 10K SOD323 R0402

4

D

3.3V

PHASE

VCOMP

10K

CHG_GND

Change from 10k to 6.98k 29

6

PC106 0.1uF/25V,Y5V C0402 18

PC104 4.7uF/25V,X7R C1206

PQ77 AO4468 SO8_50_150

VDDP S

R0402

0.01uF/25V,X7R

PC96 10uF/ 25V C1210 ns

31,36

070906VA：Co-lay。

0

G

PC105 C0402

PC98 0.1uF/25V,X7R C0603

0

PC102

5

SSOP24_25_150 PC103

SET_I

PR120 R0402

PC95 1000pF/50V,X7R C0402

PC97 SOD323 1N4148WS/75V/150mA ns

D

C0402

SET_I

Isense_SYSN

PC94 0.1uF/25V,Y5V C0402

VDD

19

1.5A

0 R0402

R0402 PC100 1000pF/25V,X7R

29

2

5 6 7 8

31 Isense_SYSP

1

ACSET

5 6 3 7 2 8 1

PC93 1uF/10V,X7R C0603

VDDP

3 2 1

PR118 5V_internal_LDO 4.7 R0402

15

1

CHG_GND

VDDP

1

PC92 1uF/10V,X7R C0603

设置适配器限流值为 55mV/25m ohm=2.2A. PR129 1.05K 1% R0402 PR131

PC111 1uF/10V,X7R C0603

PR130 100 R0402

2.2 R0402

SYS_I_Sense

29

Layout note: Far away from critical signal trace

PC112 3300pF/50V,X7R C0402

0 R0402 CHG_GND

CHG_GND Change solution from OZ8602 to ISL6251

TOPSTAR TECHNOLOGY Page Name

CHARGER

Size A3

N01

Project Name

Rev A

Date: Wednesday, July 16, 2008 Sheet 40 of 42 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

5

4

3

1B

2A

BATT+

PD1

1A

AD+

D

4A

+VDC

4B

Always_On Power ISL6545

PQ2

2A

AC_IN

PWRSWVCC2

DDR_PWROK

QB_PWRSWVCC2

+V3.3AL +V5AL

3A

V1_8_PWROK

7

ALWAYS_ON

11 11

PWRSWVCC2

+VDC

QB_PWRSWVCC2

6A

PM_SLP_S4#

C

PM_SLP_S3#

4A

8 8

MAIN_ON

7

20 PU7

SET_I

V2_5S_PWROK

IMVP_ON

VR_PWRGD_CK410_INV

24

13

23

Chipset PWR ISL6545 PU10

V1_05S_PWROK

23

Calistoga GMCH

C

AC_IN

Charge ISL6251

BATT+

SET_I V1_5S_PWROK

21

CHG_ON

15

B

15

IMVP_ON

IMVP_PWRGD

VCC_CORE ISL6545

22

CK410_CLK_EN#

22

Clock CK410M

Note: *A:For adapter in *B:For battery only * :For all

+VCC_CORE H_CPURST#

25

+V2.5S

11 V1_5S_PWROK 15 V1_05S_PWROK 15 V2_5S_PWROK 13 NVVDD_PWROK 19

SYS_I_Sense

+VDC 14

+V1.5S +V1.05S

+V3.3S

12

SYS_I_Sense

21

H_PWRGD

B

PLT_RST#

24

ALWAYS_ON MAIN_PWROK to IMVP_ON Delay 100mS

AS431

4A 4B

ALW_PWROK

CHG_ON

7

+V3.3S

MAIN_ON

10

MAIN_PWROK

EC_KBC PC97551

PM_PWRBTN#

+V3.3S +V5S +V1.8GDDR

DDR_PWROK

PM_RSMRST#

ICH7

+V1.8 +V0.9S 10

V0_9S_ON

RST_Circuit

10

9

9

5B

PM_RSMRST#

V1_8_ON

+V3.3AL

DDR Power TPS51116

PWRSW#

7B

11

System Power +V_S

6B 5A +VDC

1

+V5_STBY EC_RTC

ALW_PWROK

PQ1

D

2B

2

23

VR_PWRGD_CK410_INV

H_PWRGD

CPU

A

A

TOPSTAR TECHNOLOGY Page Name Size A3

Project Name

PowerOnSequence & Reset Map Rev C

N01

of Date: Wednesday, July 16, 2008 Sheet 41 42 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

G3

With Main Battery Without AC adapter

S3/S4/S5

S5

S0

T04

G3

S0

G3

With AC adapter

S3/S4/S5

S5

S0

T04

T16

T24

T15

T15 PCIRST# PLTRST#

PCIRST# T14

T14

SUS_STAT#

SUS_STAT#

T17

T23 (CPU PWRGD) H_PWRGD

S0 T16

T24

CPURST#

CPURST#

1

Power On Sequence(Adapter mode)

Power On Sequence(Battery mode) G3

2

T23

T17

(CPU PWRGD) H_PWRGD

T10

D

T10

PM_ICH_PWROK (Input to ICH)

PM_ICH_PWROK (Input to ICH)

D

Clock Gen Output

Clock Gen Output

IMVP_PWRGD

IMVP_PWRGD CK410_CLK_EN#

CK410_CLK_EN#

+VCC_CORE

+VCC_CORE

IMVP_ON(EC Output)

IMVP_ON(EC Output)

T08

T08 130ms

130ms MAIN_PWROK(Input to EC) +V3.3S,+V5S,+V2.5S,+V1.5S,+V1.05S,+V1.8, +V0.9S

MAIN_PWROK(Input to EC) +V3.3S,+V5S,+V2.5S,+V1.5S,+V1.05S,+V1.8, +V0.9S V0_9S_ON(EC Output)

V0_9S_ON(EC Output) T04

T49

V1_8_ON(EC Output)

T04

T49

V1_8_ON(EC Output)

MAIN_ON(EC Output)

MAIN_ON(EC Output)

ALWAYS_ON(EC Output) SLP_S3#(Input to EC)

SLP_S3#(Input to EC)

SLP_S4#(Input to EC)

SLP_S4#(Input to EC) PWRBTN#(EC Output)

PWRBTN#(EC Output)

ALWAYS_ON(EC Output) T03 C

PWRSW#(Input to EC)

T06

Press Power Button

(PRESS POWER BUTTON) PWRSWVCC2

Keep up +V3.3AL

RSMRST#(Input to EC)

C

T03

T06

+V3.3AL,+V5AL RSMRST#(Input to ICH&EC)

PWRSW#(Input to EC)

+V3.3AL,+V5AL, +V5_STBY,EC_RTC

Press Power Button

(PRESS POWER BUTTON)

AC_IN

+V5_STBY,EC_RTC

+VDC +VDC T01

RTCRST#

RTCRST#

T01

T02

VCCRTC

T02

VCCRTC

PLUG Adapter

PLUG Main Battery

Power Off Sequence(Adapter Mode)

Power Off Sequence(Battery Mode) S0 SUS_STAT#

S0

S5

S5

G3

S0

T18 SUS_STAT#

STP_PCI# PCIRST# PLTRST# SLP_S3#(Input to EC) SLP_S4#(Input to EC)

PCIRST# PLTRST# SLP_S3#(Input to EC)

T21 T19

SLP_S4#(Input to EC)

IMVP_ON(EC Output)

T22

IMVP_PWROK(ISL6545 Output)

T22a

MAIN_ON(EC Output)

V0_9S_ON(EC Output)

S5

G3

T21 T19

T22 MAIN_PWROK

MAIN_ON(EC Output) B

S5

IMVP_ON(EC Output)

IMVP_PWROK(ISL6545 Output) MAIN_PWROK

S0 T18

STP_PCI#

B

V1_8_ON(EC Output) V0_9S_ON(EC Output)

+V3.3S,+V5S,+V2.5S,+V1.5S,+V1.05S,+V1.8, +V0.9S

V1_8_ON(EC Output) +V3.3S,+V5S,+V2.5S,+V1.5S,+V1.05S,+V1.8, +V0.9S T22a

ALWAYS_ON(EC Output) ALWAYS_ON(EC Output)

T22c

+V3.3AL,+V5AL IacN

RSMRST#(Input to EC) IacN

ACIN Pull out Main Battery

+V3.3AL +V5AL Pull out AC_ADPTER

A

A

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