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LCFC Confidential

1

1

CG411/CG511 MB Schematics Document Intel Skylake-U22/Kabylake-U22 with DDR4 + Nvidia N16S-GTR/N16V-GMR1 GPU 2

2

2016-01-09 REV:1.0

3

3

4

4

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

Cover Page

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: A

B

C

D

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet E

1

of

60

A

B

C

D

E

LCFC confidential

DDR4 SO-DIMM x1

NV N16S-GTR/N16V-GMR1 Package: GB2B-64 Page 19~24

PCIe Port 9~12

VRAM: 256*16 DDR3L*8/*4: 4GB/2GB

Page 18

Memory Bus (Dual Channel)

PCI-Express 4x Gen3

DDR4 Memory Down

1.2V DDR4 2133MT/s

4pcs x16

Page 17

Page 25~29

1

1

HDMI Conn.

USB3.0 Left Conn

USB3.0 x1 USB2.0 x1

HDMI (DDI 1)

USB3.0 Port1 USB2.0 Port1

Page 34

DP to VGA

VGA Conn.

USB3.0 x1

DP x2 Lane (DDI 2)

3D Camera (Optional) Page 31

USB3.0 Port3

ITE IT6516BFN

Page 36

Page 41

Page 35

eDP x2 Lane

eDP Conn

USB2.0 x1

Int. Camera Conn.

USB3.0 x1

Intel MCP

USB3.0 Right Conn 1 (Optional) Page 45

USB3.0 Port2

USB2.0 Port4

USB2.0 x1

SKL-U22 15W KBL-U22 15W

Int. MIC Conn. Page 33

USB2.0 Right Conn 1 Page 45

USB2.0 Port3

USB2.0 x1

2

USB2.0 Right Conn 2

SATA Port0

BGA-1356 42mm*24mm

SATA Gen1 x1

SATA ODD Page 42

USB2.0 x1

Touch Screen (Optional)

Card Reader Realtek RTS5170

LAN Chip Page 37

PCIe Port5

PCIe Gen1 x1 USB2.0 x1

HD Audio

NGFF WLAN&BT PCIe Port6

Page 40

USB2.0 Port7

SPI

Codec 3

Conexant_CX11802_33Z Page 43

SD/MMC Conn.

Page 30

USB2.0 Port5

PCIe Gen1 x1

Realtek_RTL8111GUL Realtek_RTL8111H_CG

Page 38

Page 33

USB2.0 Port6

SATA Port1A

USB2.0 x1 RJ45 Conn.

USB Board

SATA Gen3 x1

SATA HDD Page 42

2

Page 45

USB2.0 Port2

SPI ROM (8MB) W25Q64FVSSIQ

SPK Conn. Page 43

3

Page 07

HP&Mic Combo Conn.

Page 3~16

SPI ROM (4MB) (Reserved)

Page 43

W25Q32FVSSIQ

LPC

Page 07

Sub-board( for 14") EC

USB BOARD

TPM (Reserved)

ITE IT8586E-LQFP

Z32H320TC

Page 32

Page 44

TP BOARD

Sub-board( for 15") Touch Pad Page 45

Thermal Sensor (Reserved)

Int.KBD

NCT7718W

Page 45

USB BOARD

Page 39

TP BOARD

4

4

ODD  BOARD

Issued Date

WWW.AliSaler.Com A

Title

LC Future Center Secret Data

Security Classification 2015/08/20

Block Diagram

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: B

C

D

Rev 1.0

CG411

Thursday, January 14, 2016 E

Sheet

2

of

60

A

B

Voltage Rails ( O --> Means ON

C

D

, X --> Means OFF ) SIGNAL

STATE

Power Plane

1

V20B+

+3VALW +5VALW +3VALW_PCH +1.8VALW +1.0VALW

+5VS

+1.2V

+3VS +VCCIO

+2.5V_DDR

SLP_S3# SLP_S4# SLP_S5#

+V

+VS

Clock

Full ON

HIGH

HIGH

HIGH

ON

ON

ON

ON

S3 (Suspend to RAM)

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

ON

OFF

OFF

OFF

1

+VCCSTG +VCC_GT +CPU_CORE +0.6VS

HSIO PORT

USB3.0

S0

O

S3 S3 Battery only

O

O

S5 S4 AC & Battery don't exist

X

X

X

X

X

USB2.0

X

X

X

X

X

O

O

O

O

O

O

O

S5 S4 Battery only

O

O

O

S5 S4 AC Only

X PCIE

SMBUS Control Table SOURCE

BATT

Charger

DGPU

IT8586E

Memory Down

PCH

PMIC

SODIMM

Thermal Sensor

WLAN WiMAX

Function 1

USB3.0 Conn Left

2

USB3.0 Conn Right(optional)

3

3D Camera(optional)

4

NC

5

NC

6

NC

1

USB3.0 Conn Left

2

USB2.0 Conn1 Right

3

USB2.0 Conn2 Right

4

Camera

5

Cardreader

6

Touch Panel

7

Bluetooth

8

NC

9

NC

10

NC

1

NC

2

NC

3

NC

4

NC

5

LAN

6

WLAN

7

used as SATA

8

used as SATA

9~12

BOM Structure @ 14@ 15@ 14or15@ 14or17@

DGPU

X4 PCIE 3

EC_SMB_CK1

IT8586E

EC_SMB_DA1

+3VL_EC

V

V

X

X

V

X

X

X

X

X

+3VL_EC

SATA EC_SMB_CK2

IT8586E

EC_SMB_DA2

+3VS

EC_SMB_CK3

IT8586E

EC_SMB_DA3

+3VL_EC

PCH_SMB_CLK

PCH

X

X

V

V

+3VG_AON

X

X

X

V

+3VS

V

X

X

X

V

X

0

HDD

1A

ODD

1B

used as PCIE

2

used as PCIE

+3VALW_PCH

X

X

V

V

X

X

X

V

X

For 14" part For 15" part For 14" or 15" part For 14" or 17" part

Cannonlake@ CD@ DUALMIC@ EMC@ EMC_15@ EMC_NS@ EMC_PX@ EMC_PXNS@ ES@ EXO@

For Cannonlake part

ME@ NTS@

For ME part

PX@ RANKA@ RANKB@ Realtek_SD@ SINGLEMIC@ SINGLERANK@ DUALRANK@ TS@ TPM@ UMA@

For PX part

For C cost down For Dual MIC part For EMC part

2

For EMC 15" part For EMC nu-stuff part For EMC PX part For EMC PX nu-stuff part For ES CPU For EXO GPU

For nu-touch part

For VRAM rank A part For VRAM rank B part For Realtek SD part For single MIC part 3

For single VRAN rank part For dual VRAN rank part For touch screen part For TPM part For UMA part

X

X

X

X

X

X

+3VALW_PCH

+3VS

V +3VS

EC SMBus1 address

EC SMBus2 address

EC SMBus3 address

PCH SM Bus address

Device

Address

Device

Address

Device

Address

Device

Address

Smart Battery

need to update

Thermal Sensor(NCT7718W)

1001_100xb

PMIC

need to update

DDR4 SODIMM

need to update

Charger

0001 0010 b

PCH

need to update

Wlan

Reserved

DGPU

need to update

4

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

Notes List

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: A

BTO Item Not stuff

+3VL_EC

PCH_SMB_DATA +3VALW_PCH

4

+VALW

+VCCSA

+VCCST

State

2

E

B

C

D

Rev 1.0

CG411

Thursday, January 14, 2016 E

Sheet

3

of

60

4

3

HDMI D1 HDMI D0

HDMI CLK

DP TO VGA Converter

34 34 34 34 34 34 34 34

HDMI_TX2HDMI_TX2+ HDMI_TX1HDMI_TX1+ HDMI_TX0HDMI_TX0+ HDMI_CLKHDMI_CLK+

35 35 35 35

VGA_TX0VGA_TX0+ VGA_TX1VGA_TX1+

HDMI_TX2HDMI_TX2+ HDMI_TX1HDMI_TX1+ HDMI_TX0HDMI_TX0+ HDMI_CLKHDMI_CLK+

E55 F55 E58 F58 F53 G53 F56 G56

VGA_TX0VGA_TX0+ VGA_TX1VGA_TX1+

C50 D50 C52 D52 A50 B50 D51 C51

DDI1_TXN[0] DDI1_TXP[0] DDI1_TXN[1] DDI1_TXP[1] DDI1_TXN[2] DDI1_TXP[2] DDI1_TXN[3] DDI1_TXP[3]

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

DDI2_TXN[0] DDI2_TXP[0] DDI2_TXN[1] DDI2_TXP[1] DDI2_TXN[2] DDI2_TXP[2] DDI2_TXN[3] DDI2_TXP[3]

DDI

EDP_AUXN EDP_AUXP

EDP

34 DDPB_CLK 34 DDPB_DATA

DDPB_CLK DDPB_DATA

L13 L12

DDPC_CLK DDPC_DATA

N7 N8 N11 N12

+VCCIO RC4

2

EDP_COMP

1 24.9_0402_1%

E52

+VCCIO&EDP_COMP : Trace Width: 20mil Isolation Spacing: 25mil Max length: 100mil

EDP_BKLTEN EDP_BKLTCTL EDP_VDDEN

EDP_RCOMP

CPU_EDP_AUX# CPU_EDP_AUX

CPU_EDP_TX0CPU_EDP_TX0+ CPU_EDP_TX1CPU_EDP_TX1+

33 33 33 33

confirmed with ITE, the HPD pull down resistor should follow ITE recommended resistor 4.7k~10Kohm

D

+3VS CPU_EDP_AUX# 33 CPU_EDP_AUX 33 GPP_E15

RC1601 1

@

2 10K_0402_5%

VGA_AUX# VGA_AUX

VGA_AUX# 35 VGA_AUX 35

RC37 4.7K_0402_5%

L9 L7 L6 N9 L10

HDMI_HPD DP_VGA_HPD GPP_E15

R12 R11 U13

PCH_ENBKL PCH_EDP_PWM PCH_ENVDD

HDMI_HPD RC181

1

34 @

DP_VGA_HPD EC_SCI# 44

2 0_0402_5%

CPU_EDP_HPD

CPU_EDP_HPD

35

PCH_ENBKL 33 PCH_EDP_PWM 33 PCH_ENVDD 33

33

1 OF 20

RC13 100K_0402_5%

?

C

1

C

GPP_E22/DDPD_CTRLCLK GPP_E23/DDPD_CTRLDATA

SKYLAKE-U_BGA1356 REV = 1 @

+VCCST_CPU

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3 GPP_E17/EDP_HPD

GPP_E20/DDPC_CTRLCLK GPP_E21/DDPC_CTRLDATA

E45 F45

G50 F50 E48 F48 G46 F46

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

GPP_E18/DDPB_CTRLCLK GPP_E19/DDPB_CTRLDATA

CPU_EDP_TX0CPU_EDP_TX0+ CPU_EDP_TX1CPU_EDP_TX1+

B52

EDP_DISP_UTIL

DISPLAY SIDEBANDS

C47 C46 D46 C45 A45 B45 A47 B47

2

HDMI D2

?

1

D

1

1

SKL_ULT

UC1A

2

2

5

+VCCSTG

RC1625 49.9_0402_1%

1

@

UC1D

2

RC19 1K_0402_5%

2

check PROCHOT# circuit with PWR RC20 1

44 H_PECI

2 499 +-1% 0402

1

44,55 H_PROCHOT#

PAD @ PAD @ PAD @ PAD @

2

RC143 1K_0402_5%

PAD @ PAD @

+VCCST_CPU

TC11 TC12 TC13 TC14 TC162 TC163

1 1 1 1 1 1

check H_THRMTRIP# if need to connector to EC RC155 RC156 U23E@ RC157 U23E@ RC170

1 1 1 1

2 2 2 2

CATERR# H_PECI H_PROCHOT#_R H_THRMTRIP#

D63 A54 C65 C63 A65

XDP_BPM0# XDP_BPM1# XDP_BPM2# XDP_BPM3#

C55 D55 B54 C56

GPP_E3 GPP_E7

A6 A7 BA5 AY5

PROC_OPI_RCOMP AT16 PCH_OPI_RCOMP AU16 EDRAM_OPIO_RCOMP H66 EOPIO_RCOMP H65

49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1%

SKL_ULT

CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#

+3VS

XDP_TCK RC1546

1

@

2 0_0402_5%

JTAGX

RC1551 1

2 51_0402_5%

XDP_TDO RC1547

1

@

2 0_0402_5%

PCH_JTAG_TDO

RC1543 1

2 51_0402_5%

+VCCSTG

JTAG

PROC_TCK PROC_TDI PROC_TDO PROC_TMS PROC_TRST#

CPU MISC

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_TRST# JTAGX

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

B61 D60 A61 C60 B59

XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST#

1 1 1 1 1

B56 D59 A56 C59 C61 A59

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TRST# JTAGX

1 1 1 1 1 1

TC15 TC16 TC17 TC18 TC27 TC29 TC31 TC35 TC36 TC42 TC43

PAD @ PAD @ PAD @ PAD @ PAD @

XDP_TDI

RC1548 1

@

2 0_0402_5%

PCH_JTAG_TDI

XDP_TMS

RC1549 1

@

2 0_0402_5%

PCH_JTAG_TMS

XDP_TRST#

RC1550 1

@

2 0_0402_5%

PCH_JTAG_TRST#

PAD @ PAD @ PAD @ PAD @ PAD @ PAD @

check JTAG circuit?

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP SKYLAKE-U_BGA1356 REV = 1 @

B

?

1 OF 20 ? B

check DDPC_CLK pull high or not? RPC19

8 7 6 5

1 2 3 4

DDPC_CLK DDPC_DATA DDPB_CLK DDPB_DATA

2.2K_0804_8P4R_5%

DDP*_CTRLDATA strapping sampled on the rising edge of PWROK

Port Port 1 Port 2

Strap

Enable

Disable

DDPB_CTRLDATA

Pull up to 3.3 V with 2.2Kohm

NC

DDPC_CTRLDATA

Pull up to 3.3 V with 2.2Kohm

NC

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

Deciphered Date

MCP (DDI,EDP)

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

WWW.AliSaler.Com

4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016 1

Sheet

4

of

60

5

4

3

2

1

? SKL_ULT

UC1B 17 DDRA_DQ[0..63]

D

C

DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31 DDRA_DQ32 DDRA_DQ33 DDRA_DQ34 DDRA_DQ35 DDRA_DQ36 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQ40 DDRA_DQ41 DDRA_DQ42 DDRA_DQ43 DDRA_DQ44 DDRA_DQ45 DDRA_DQ46 DDRA_DQ47 DDRA_DQ48 DDRA_DQ49 DDRA_DQ50 DDRA_DQ51 DDRA_DQ52 DDRA_DQ53 DDRA_DQ54 DDRA_DQ55 DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63

AL71 AL68 AN68 AN69 AL70 AL69 AN70 AN71 AR70 AR68 AU71 AU68 AR71 AR69 AU70 AU69 BB65 AW65 AW63 AY63 BA65 AY65 BA63 BB63 BA61 AW61 BB59 AW59 BB61 AY61 BA59 AY59 AY39 AW39 AY37 AW37 BB39 BA39 BA37 BB37 AY35 AW35 AY33 AW33 BB35 BA35 BA33 BB33 AY31 AW31 AY29 AW29 BB31 BA31 BA29 BB29 AY27 AW27 AY25 AW25 BB27 BA27 BA25 BB25

DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16]/DDR0_DQ[32] DDR0_DQ[17]/DDR0_DQ[33] DDR0_DQ[18]/DDR0_DQ[34] DDR0_DQ[19]/DDR0_DQ[35] DDR0_DQ[20]/DDR0_DQ[36] DDR0_DQ[21]/DDR0_DQ[37] DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQ[27]/DDR0_DQ[43] DDR0_DQ[28]/DDR0_DQ[44] DDR0_DQ[29]/DDR0_DQ[45] DDR0_DQ[30]/DDR0_DQ[46] DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQ[32]/DDR1_DQ[0] DDR0_DQ[33]/DDR1_DQ[1] DDR0_DQ[34]/DDR1_DQ[2] DDR0_DQ[35]/DDR1_DQ[3] DDR0_DQ[36]/DDR1_DQ[4] DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQ[61]/DDR1_DQ[45] DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQ[63]/DDR1_DQ[47]

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1] DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3] DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[3] DDR0_MA[4] DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5] DDR0_ALERT# DDR0_PAR DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR CH - A

DDR_VTT_CNTL

AU53 AT53 AU55 AT55

DDRA_CLK0# 17 DDRA_CLK0 17

BA56 BB56 AW56 AY56 AU45 AU43 AT45 AT43

DDRA_CKE0

17

DDRA_CS0#

17

DDRA_ODT0

17

DDRA_MA5 DDRA_MA9 DDRA_MA6 DDRA_MA8 DDRA_MA7 DDRA_BG0 DDRA_MA12 DDRA_MA11 DDRA_ACT#

17 17 17 17 17 17 17 17 17

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54 AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52 AM70 AM69 AT69 AT70 BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

DDRA_MA13 17 DDRA_MA15_CAS# 17 DDRA_MA14_WE# 17 DDRA_MA16_RAS# 17 DDRA_BS0# 17 DDRA_MA2 17 DDRA_BS1# 17 DDRA_MA10 17 DDRA_MA1 17 DDRA_MA0 17 DDRA_MA3 17 DDRA_MA4 17 DDRA_DQS#0 DDRA_DQS0 DDRA_DQS#1 DDRA_DQS1 DDRA_DQS#2 DDRA_DQS2 DDRA_DQS#3 DDRA_DQS3 DDRA_DQS#4 DDRA_DQS4 DDRA_DQS#5 DDRA_DQS5 DDRA_DQS#6 DDRA_DQS6 DDRA_DQS#7 DDRA_DQS7

C

DDRA_DQS#[0..7]

DDRA_DQS#[0..7]

DDRA_DQS[0..7]

AW50 AT52

DDRA_ALERT# 17 DDRA_PAR 17

AY67 AY68 BA67 AW67

D

DDR_SA_VREFCA

17

DDR_SB_VREFCA

18

DDRA_DQS[0..7]

17 17

SMVREF WIDTH:20MIL SPACING: 20MIL

DDR_VTT_CNTL

1 OF 20 SKYLAKE-U_BGA1356 REV = 1 @

?

B

B

1

+3VALW

2

RC30 100K_0402_5%

CPU_DRAMPG_CNTL

55

1

+1.2V RC3

1 2 1K_0402_5%

2

C

QC18

B

3

E

MMBT3904WH_SOT323-3

2

DDR_VTT_CNTL

1

RC29 10K_0402_5% @ A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification 2015/08/20

Deciphered Date

MCP (DDR4)

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016 1

Sheet

5

of

60

5

4

3

2

1

?

UC1C

18 DDRB_DQ[0..63] DDRB_DQ0 DDRB_DQ1 DDRB_DQ2 DDRB_DQ3 DDRB_DQ4 DDRB_DQ5 DDRB_DQ6 DDRB_DQ7 DDRB_DQ8 DDRB_DQ9 DDRB_DQ10 DDRB_DQ11 DDRB_DQ12 DDRB_DQ13 DDRB_DQ14 DDRB_DQ15 DDRB_DQ16 DDRB_DQ17 DDRB_DQ18 DDRB_DQ19 DDRB_DQ20 DDRB_DQ21 DDRB_DQ22 DDRB_DQ23 DDRB_DQ24 DDRB_DQ25 DDRB_DQ26 DDRB_DQ27 DDRB_DQ28 DDRB_DQ29 DDRB_DQ30 DDRB_DQ31 DDRB_DQ32 DDRB_DQ33 DDRB_DQ34 DDRB_DQ35 DDRB_DQ36 DDRB_DQ37 DDRB_DQ38 DDRB_DQ39 DDRB_DQ40 DDRB_DQ41 DDRB_DQ42 DDRB_DQ43 DDRB_DQ44 DDRB_DQ45 DDRB_DQ46 DDRB_DQ47 DDRB_DQ48 DDRB_DQ49 DDRB_DQ50 DDRB_DQ51 DDRB_DQ52 DDRB_DQ53 DDRB_DQ54 DDRB_DQ55 DDRB_DQ56 DDRB_DQ57 DDRB_DQ58 DDRB_DQ59 DDRB_DQ60 DDRB_DQ61 DDRB_DQ62 DDRB_DQ63

D

C

AF65 AF64 AK65 AK64 AF66 AF67 AK67 AK66 AF70 AF68 AH71 AH68 AF71 AF69 AH70 AH69 AT66 AU66 AP65 AN65 AN66 AP66 AT65 AU65 AT61 AU61 AP60 AN60 AN61 AP61 AT60 AU60 AU40 AT40 AT37 AU37 AR40 AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30 AU27 AT27 AT25 AU25 AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21

DDR1_DQ[0]/DDR0_DQ[16] DDR1_DQ[1]/DDR0_DQ[17] DDR1_DQ[2]/DDR0_DQ[18] DDR1_DQ[3]/DDR0_DQ[19] DDR1_DQ[4]/DDR0_DQ[20] DDR1_DQ[5]/DDR0_DQ[21] DDR1_DQ[6]/DDR0_DQ[22] DDR1_DQ[7]/DDR0_DQ[23] DDR1_DQ[8]/DDR0_DQ[24] DDR1_DQ[9]/DDR0_DQ[25] DDR1_DQ[10]/DDR0_DQ[26] DDR1_DQ[11]/DDR0_DQ[27] DDR1_DQ[12]/DDR0_DQ[28] DDR1_DQ[13]/DDR0_DQ[29] DDR1_DQ[14]/DDR0_DQ[30] DDR1_DQ[15]/DDR0_DQ[31] DDR1_DQ[16]/DDR0_DQ[48] DDR1_DQ[17]/DDR0_DQ[49] DDR1_DQ[18]/DDR0_DQ[50] DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQ[23]/DDR0_DQ[55] DDR1_DQ[24]/DDR0_DQ[56] DDR1_DQ[25]/DDR0_DQ[57] DDR1_DQ[26]/DDR0_DQ[58] DDR1_DQ[27]/DDR0_DQ[59] DDR1_DQ[28]/DDR0_DQ[60] DDR1_DQ[29]/DDR0_DQ[61] DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[31]/DDR0_DQ[63] DDR1_DQ[32]/DDR1_DQ[16] DDR1_DQ[33]/DDR1_DQ[17] DDR1_DQ[34]/DDR1_DQ[18] DDR1_DQ[35]/DDR1_DQ[19] DDR1_DQ[36]/DDR1_DQ[20] DDR1_DQ[37]/DDR1_DQ[21] DDR1_DQ[38]/DDR1_DQ[22] DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63] SKYLAKE-U_BGA1356 REV = 1 @

B

SKL_ULT

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1] DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3] DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_MA[3] DDR1_MA[4] DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3] DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7] DDR1_ALERT# DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

AN45 AN46 AP45 AP46

DDRB_CLK0# 18 DDRB_CLK1# 18 DDRB_CLK0 18 DDRB_CLK1 18

AN56 AP55 AN55 AP53

DDRB_CKE0 DDRB_CKE1

BB42 AY42 BA42 AW42

D

18 18

DDRB_CS0# 18 DDRB_CS1# 18 DDRB_ODT0 18 DDRB_ODT1 18

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

DDRB_MA5 DDRB_MA9 DDRB_MA6 DDRB_MA8 DDRB_MA7 DDRB_BG0 DDRB_MA12 DDRB_MA11 DDRB_ACT# DDRB_BG1

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

18 18 18 18 18 18 18 18 18 18

DDRB_MA13 18 DDRB_MA15_CAS# 18 DDRB_MA14_WE# 18 DDRB_MA16_RAS# 18 DDRB_BS0# 18 DDRB_MA2 18 DDRB_BS1# 18 DDRB_MA10 18 DDRB_MA1 18 DDRB_MA0 18 DDRB_MA3 18 DDRB_MA4 18

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21

DDRB_DQS#0 DDRB_DQS0 DDRB_DQS#1 DDRB_DQS1 DDRB_DQS#2 DDRB_DQS2 DDRB_DQS#3 DDRB_DQS3 DDRB_DQS#4 DDRB_DQS4 DDRB_DQS#5 DDRB_DQS5 DDRB_DQS#6 DDRB_DQS6 DDRB_DQS#7 DDRB_DQS7

AN43 AP43 AT13 AR18 AT18 AU18

CPU_DRAMRST#_R SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

C

DDRB_DQS#[0..7] DDRB_DQS[0..7]

DDRB_DQS#[0..7]

18

DDRB_DQS[0..7]

18

DDRB_ALERT# 18 DDRB_PAR 18 RC24 RC25 RC26

1 1 1

2 121_0402_1% 2 80.6_0402_1% 2 100_0402_1%

DDR CH - B

1 OF 20 ? B

1

+1.2V

2

RC22 470_0402_5%

RC23

17,18 CPU_DRAMRST# 1

2

1

@

2 0_0402_5%

CPU_DRAMRST#_R

CC1 0.01U_0201_25V6-K EMC_NS@

A

A

Issued Date

WWW.AliSaler.Com 5

Title

LC Future Center Secret Data

Security Classification

2015/08/20

MCP (DDR4)

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet 1

6

of

60

4

3

? +3VALW_PCH

D

SPI_CS0# SPI_CS1#

44 SPI_CS0#

RC52 RC175

RC51 RC174

1 1

1 1

@

@ @

2 15_0402_5% 2 33_0402_5%

2 0_0402_5% 2 0_0402_5%

GPP_C3/SML0CLK GPP_C4/SML0DATA GPP_C5/SML0ALERT# GPP_C6/SML1CLK GPP_C7/SML1DATA GPP_B23/SML1ALERT#/PCHHOT#

SPI_SI_R SPI - TOUCH

M2 M3 J4 V1 V2 M1

SPI_CS0#_R SPI_CS1#_R BOARD_ID4

8 BOARD_ID4

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

LPC

+3V_SPI

44 KBRST#

AW13

SERIRQ

AY11

RC60 1K_0402_5%

W3 V3 AM7

PCH_SML1_CLK PCH_SML1_DAT SML1_ALERT#

DIMM, NGFF 4 3

SML0_CLK SML0_DATA SML0_ALERT#

+3VS

RPC20 2.2K_0404_4P2R_5%

RPC24 2.2K_0404_4P2R_5%

PCH_SMB_CLK

GPU, EC, Thermal Sensor

D

6

QC2A

1

SMB_CLK_S3 18,40

GPP_A0/RCIN#

AY13 BA13 BB13 AY12 BA12 BA11

SUS_STAT#

AW9 AY9 AW11

CLK_PCI_EC_R CLK_PCI_TPM_R PM_CLKRUN#

LPC_AD0 32,44 LPC_AD1 32,44 LPC_AD2 32,44 LPC_AD3 32,44 LPC_FRAME# 32,44

PCH_SMB_DATA

QC2B

3

4

SMB_DATA_S3 18,40

2N7002KDWH_SOT363-6 1

RC173 2 RC1541 2 TPM@

1 22_0402_5% 1 22_0402_5%

CLK_PCI_EC 44 CLK_PCI_TPM 32 PM_CLKRUN# 32

+3VALW_PCH

GPP_A6/SERIRQ 1 OF 20

SMB_ALERT#

2 1 2.2K_0402_5%

?

RC1562

@

2

2

R9 W2 W1

+3VS

TC81@

GPP_A9/CLKOUT_LPC0/ESPI_CLK GPP_A10/CLKOUT_LPC1 GPP_A8/CLKRUN#

SKYLAKE-U_BGA1356 REV = 1

RC61 1K_0402_5%

Check with BIOS, SPI is Dual mode or quad mode

SPI_WP#_R

CL_CLK CL_DATA CL_RST#

1

1

32,44 SERIRQ

KBRST#

PCH_SMB_CLK PCH_SMB_DATA SMB_ALERT#

2N7002KDWH_SOT363-6

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3 GPP_A5/LFRAME#/ESPI_CS# GPP_A14/SUS_STAT#/ESPI_RESET#

C LINK

G3 G2 G1

R7 R8 R10

G

SPI_SI SPI_SI_1

44 SPI_SI

GPP_C0/SMBCLK GPP_C1/SMBDATA GPP_C2/SMBALERT#

1 2

SPI_SO_R

@

2 15_0402_5% 2 33_0402_5%

SMBUS, SMLINK

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

S

@

AV2 AW3 AV3 AW2 AU4 AU3 AU2 AU1

5

1 1

SPI_CLK_R SPI_SO_R SPI_SI_R SPI_WP#_R SPI_HOLD#_R SPI_CS0#_R SPI_CS1#_R

D

RC53 RC177

SPI_CLK_R

2

44 SPI_SO

SPI_SO SPI_SO_1

2 15_0402_5% 2 33_0402_5%

G

RC1539 1 RC1538 1

D

SPI_CLK SPI_CLK_1

3 4

SPI - FLASH

44 SPI_CLK

1

S

SKL_ULT

UC1E

2

2 1

5

RC54

1

@

2 15_0402_5%

SPI_WP#

SPI_HOLD#_R RC55

1

@

2 15_0402_5%

SPI_HOLD#

+3V_SPI

C

+3VS

+3VALW_PCH

+3VS

check CLKRUN# / SUS_STAT# signal if need to connect

C

RPC23

+3VALW_PCH

SML0_CLK SML0_DATA

RC171

1

@

2 0_0402_5%

RC172

1

@

2 0_0402_5%

PM_CLKRUN#

RC11

1

2 8.2K_0402_5%

SERIRQ

RC12

1

2 10K_0402_5%

KBRST#

RC10

1

2 10K_0402_5%

KBRST#

CC1255

4 3

1 2

2.2K_0404_4P2R_5% +3V_SPI

*

+3V_SPI

SML0_ALERT# RC180 1K_0402_5% @

1

2

RC176

1

@

2 33_0402_5%

SPI_WP#_1

SPI_HOLD#_R RC178

1

@

2 33_0402_5%

SPI_HOLD#_1

RC1564 2

@

1 2.2K_0402_5%

1000P_0201_50V7-K

This signal has a weak internal pull-down. 0 = LPC Is selected for EC. (Default) 1 = eSPI Is selected for EC. Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts. 2. This signal is in the primary wel Rising edge of RSMRST#

EMC_NS@

2

2

RC179 1K_0402_5% @ SPI_WP#_R

+3VALW_PCH

1

1

1. If support DS3, connect to +3VS and don't support EC mirror code; 2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.

+3V_SPI

+3VALW_PCH

UC3 SPI_SO

2

SPI_WP#

3

B

4 SPI_SO_R

RC1565

2

@

1 20K_0402_5%

SPI_SI_R

RC1578

2

@

1 20K_0402_5%

SPI_WP#_R

RC1580

2

@

1 20K_0402_5%

SPI_HOLD#_R

WP#

CLK

GND

DI

SPI_HOLD#

6

SPI_CLK

5

SPI_SI

1

B

+3VALW_PCH

RPC25 2.2K_0404_4P2R_5%

@

1 4.7K_0402_5%

SPI_SO_R

2

@

1 4.7K_0402_5%

SPI_SI_R

RC1581

2

@

1 4.7K_0402_5%

SPI_WP#_R

RC64

1 ES@

2 1K_0402_5%

SPI_HOLD#_R

VCC HOLD# CLK DI

8 7 6 5

W25Q32FVSSIQ_SO8 @

SPI_HOLD#_1 SPI_CLK_1 SPI_SI_1

PCH_SML1_CLK 1

2

QC10A 6

CC97 0.1u_0201_10V6K @

1 @

2N7002KDWH_SOT363-6

A

EC_SMB_CK2

20,39,44

EC_SMB_DA2

20,39,44

G

CS# DO WP# GND

D

1 2 3 4

PCH_SML1_DAT

QC10B 3

4

@

D

2

To enable Direct Connect Interface (DCI), a 150K pull up resistor will need to be added to PCHHOT# pin. This pin must be low during the rising edge of RSMRST#. (Refer to WW52_MOW)

1 2

UC6

RC1566

+3VS

W25Q64FVSSIQ_SO8

SPI_CS1# SPI_SO_1 SPI_WP#_1

RC1567

2 150K_0402_5%

2

+3V_SPI

Follow CRB, need to check the strap ?

RC1569 1

CC8 0.1u_0201_10V6K

S

1 20K_0402_5%

7

5

@

SML1_ALERT#

HOLD#

2

2

DO

8

VCC

4 3

RC1568

CS#

G

Follow CRB, need to check the strap ?

1

S

+3VALW_PCH

SPI_CS0#

2N7002KDWH_SOT363-6

Based on WW36 SKL U&Y WOM, RC64 populated, and RC61 de-populated for SKL U ES sample. In this case, customers must ensure that the SPI flash device on the platform has HOLD functionality disabled by default.

A

Issued Date

Title

LC Future Center Secret Data

Security Classification 2015/08/20

Deciphered Date

MCP (MISC,JTAG,SPI,LPC,SMB)

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

4

3

2

1

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet

7

of

60

5

4

3

2

1

+3VS +3VS

@

2 2.2K_0402_5%

GPP_B18

2 2.2K_0402_5%

AM5 PCH_CMOS_ON# AN7 AP5 GPP_B22 AN5

33 PCH_CMOS_ON# RC1637 1 OPT@

2 10K_0402_5%

FB_GC6_EN_R

RC1638 1

2 10K_0402_5%

GPU_EVENT#

@

RC1563 1

2 10K_0402_5%

RC1558 1 UMA@ 2 10K_0402_5% CC1259

1

2 0.01U_0201_10V6K

AB1 AB2 W4 AB3

40 UART_RX_DEBUG 40 UART_TX_DEBUG

Reserve for NV GPU

RC1557 1 OPT@

@

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

PXS_RST#_R RC7 RC8

22,58 PXS_PWREN 20 PXS_RST# 24,57,58 DGPU_PWROK 20 FB_GC6_EN_R

DGPU_PWROK PXS_RST#

1 OPT@ 1 @

2 1K_0402_5% 2 0_0402_5%

31 3D_FR 40 PCH_WLAN_OFF# 40 PCH_BT_OFF#

PXS_PWREN_R PXS_RST#_R DGPU_PWROK FB_GC6_EN_R

AD1 AD2 AD3 AD4

3D_FR

U7 U6

PCH_WLAN_OFF# PCH_BT_OFF#

U8 U9

C

1 10K_0402_5% 1 10K_0402_5% 1 10K_0402_5%

GPP_F10/I2C5_SDA/ISH_I2C2_SDA GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL GPP_D15/ISH_UART0_RTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5 GPP_A12/BM_BUSY#/ISH_GP6

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL

AF11 AF12 @

GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL

AH11 AH12

RC1595 2 RC1596 2 RC1597 2

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL

AH9 AH10 +3VS

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

9 BOARD_ID2 7 BOARD_ID4

BOARD_ID7 BOARD_ID8

N1 N2

BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 BOARD_ID4 BOARD_ID5

AD11 AD12

D

14or15@

U1 U2 U3 U4 AC1 AC2 AC3 AB4

GPU_EVENT#

14or17@

Board ID

Description 14"

RC1616 RC1614

Board_ID[0:1] 01

15"

RC1616 RC1613

10

17"

RC1615 RC1614

11

Reserved

0

Non-touch RC1612

Board_ID2

?

Stuff R

00

? SKL_ULT

UMA@

GPU_EVENT# 20

AY8 BA8 BB7 BA7 AY7 AW7 AP13

1 OF 20

SKYLAKE-U_BGA1356 REV = 1 @ UC1G

SINGLERANK@ SINGLEMIC@

NTS@

GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

PCH_CMOS_ON# PCH_WLAN_OFF# PCH_BT_OFF#

1 RC1606 2 10K_0402_5%

BOARD_ID6 BOARD_ID5

BOARD_ID3

RC1608 1 2 10K_0402_5%

M4 N3

1 RC123 2 10K_0402_5%

RC1561 1

BOARD_ID0 BOARD_ID1

DUALMIC@

1 RC1607 2 10K_0402_5%

+3VS

P2 P3 P4 P1

1 RC1609 2 10K_0402_5%

GPU_EVENT#

GPP_D9 GPP_D10 GPP_D11 GPP_D12

OPT@

1 RC1610 2 10K_0402_5%

2 10K_0402_5%

D

GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

1 RC1611 2 10K_0402_5%

FB_GC6_EN_R

TS@

1 RC1612 2 10K_0402_5%

RC1630 1 GC6@

2 10K_0402_5%

ISH

15@

1 RC1613 2 10K_0402_5%

@

AN8 AP7 AP8 AR7

17@

1 RC1614 2 10K_0402_5%

Reserve for GPU sequence

RC1629 1

DUALRANK@

?

LPSS

PXS_RST#_R

2 10K_0402_5%

@

SKL_ULT

UC1F

1 RC1615 2 10K_0402_5%

RC1641 1

PXS_PWREN_R

1 10K_0402_5%

1 RC1616 2 10K_0402_5%

RC1559 2 OPT@

Board_ID3

1

Touch

RC1611

0

UMA

RC1610

1

DIS

RC1609

0

SingleRankRC1607

1

DualRank

0

SingleMIC RC123

1

DualMIC

C

double check if need the pull up resisor AUDIO

43 HDA_RST_AUDIO#

HDA_SDOUT

RC44 1

2 33_0402_5%

HDA_RST#

* HDA_SDO This signal has a weak internal pull-down. 0 = Enable security measures defined in the Flash Descriptor. 1 = Disable Flash Descriptor Security(override). This strap should only be asserted high during external pull-up in manufacturing/debug environments ONLY.

AK7 AK6 AK9 AK10

BOARD_ID9

For EMI

HDA_SDIN0 PCH_BEEP

43 PCH_BEEP

AW5

GPP_A17/SD_PWR_EN#/ISH_GP7 GPP_A16/SD_1P8_SEL

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

SD_RCOMP

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

GPP_F23

BA9 BB9 AB7 AF13

CC7 10P_0201_50V8F EMC_NS@

SD_RCOMP

RC49 200_0402_1%

B

RC1606

@

510Z@

@

@

@

BOARD_ID6 BOARD_ID7 BOARD_ID8 BOARD_ID9

GPP_B14/SPKR 1 OF 20

SKYLAKE-U_BGA1356 REV = 1 @

RC1608

+3VS

2 RC1634 1 10K_0402_5%

2

D8 C8

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

2

1

H5 D7

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3 GPP_G5/SD_CD# GPP_G6/SD_CLK GPP_G7/SD_WP

Board_ID5

2 RC1639 1 10K_0402_5%

2 1K_0402_5%

AB11 AB13 AB12 W12 W11 W10 W8 W7

2 RC1640 1 10K_0402_5%

@

SDIO/SDXC

2 RC1633 1 10K_0402_5%

1

RC47

43 HDA_SDIN0

Board_ID4

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

?

@

310G@

2 RC1636 1 10K_0402_5%

2 1K_0402_5%

BA22 AY22 BB22 BA21 AY21 AW22 J5 AY20 AW20

2 RC1632 1 10K_0402_5%

@

HDA_SYNC HDA_BCLK HDA_SDOUT HDA_SDIN0

2 RC1635 1 10K_0402_5%

RC1600 1

2 33_0402_5% 2 33_0402_5%

2 RC1631 1 10K_0402_5%

+3VS

RC43 1 RC42 1

1

+3VALW_PCH

43 HDA_SYNC_AUDIO 43 HDA_BITCLK_AUDIO

@

B

+3VS RC45 1 RC46 1

43 HDA_SDOUT_AUDIO 44 ME_FLASH

@

2 33_0402_5% 2 0_0402_5%

HDA_SDOUT RC14

1

@

2 2.2K_0402_5%

PCH_BEEP

Board ID

Pin Name Strap Description

SPKR / GPP_B14

Top Swap Override

Description

Default When Sampled Value

Configuration Internal PD 0 = Disable “ Top Swap” mode. (Default) 1 = Enable “ Top Swap” mode.

*

Stuff R

00 Samsung 8Gb RC1634 RC1635 01 Hynix 8Gb

Rising edge of PCH_PWROK

10 Micron 8Gb RC1631 RC1635 11 Reserved

GSPI0_MOSINo Reboot /GPP_B18

Internal PD 0 = Disable “ No Reboot” mode. (Default) 1 = Enable “ No Reboot” mode

*

RC1634 RC1632

Board_ID[6:7] 0

0

Rising edge of PCH_PWROK

RC1631 RC1632

0

310G

RC1636

1

510Z

RC1633

Board_ID8

A

A

GSPI1_MOSIBoot BIOS /GPP_B22 Strap Bit BBS

Internal PD 0 = SPI (Default) 1 = LPC

*

0

Rising edge of PCH_PWROK

Issued Date

2015/08/20

Deciphered Date

1

Reserved

MCP (LPSS,ISH,AUDIO,SDIO)

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date:

WWW.AliSaler.Com

Reserved

Title

LC Future Center Secret Data

Security Classification

5

0 BOARD_ID9

4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016 1

Sheet

8

of

60

5

4

3

2

1

D

D

?

SKL_ULT

UC1H

SSIC / USB3

PCIE/USB3/SATA

H13 G13 B17 A17 G11 F11 D16 C16 H16 G16 D17 C17 G15 F15 B19 A19 37 37 37 37

LAN C

WLAN

40 40 40 40

PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PTX_C_DRX_N5 PCIE_PTX_C_DRX_P5

CC22 1 CC23 1

PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_C_DRX_N6 PCIE_PTX_C_DRX_P6

SATA HDD

42 42 42 42

SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0

SATA ODD

42 42 42 42

SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1

CC24 1 CC25 1

F16 E16 C19 D19

PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 2 0.1u_0201_10V6K PCIE_PTX_DRX_N6 2 0.1u_0201_10V6K PCIE_PTX_DRX_P6

G18 F18 D20 C20

SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0

F20 E20 B21 A21

SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1

G21 F21 D21 C21

PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P0

0.22U_0201_6.3V6-K 0.22U_0201_6.3V6-K

OPT@1 OPT@1

2 CC16 2 CC14

PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P0 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P0

E22 E23 B23 A23

PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P1

0.22U_0201_6.3V6-K 0.22U_0201_6.3V6-K

OPT@1 OPT@1

2 CC15 2 CC17

PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P1

F25 E25 D23 C23

RC119

DGPU

PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 2 0.1u_0201_10V6K PCIE_PTX_DRX_N5 2 0.1u_0201_10V6K PCIE_PTX_DRX_P5

1

PCIE_RCOMPN PCIE_RCOMPP

2 100_0402_1% PAD @ PAD @

PCIE_RCOMPN and PCIE_RCOMPP Trace Width: 12-15mil Differential between RCOMPP/RCOMPN

TC20 TC19

1 1

XDP_PRDY# XDP_PREQ# PIRQA#

F5 E5 D56 D61 BB11

B

PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P2

0.22U_0201_6.3V6-K 0.22U_0201_6.3V6-K

OPT@1 OPT@1

2 CC18 2 CC19

PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P3

0.22U_0201_6.3V6-K 0.22U_0201_6.3V6-K

OPT@1 OPT@1

2 CC20 2 CC21

PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P2 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P3

E28 E27 D24 C24 E30 F30 A25 B25

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

PCIE1_RXN/USB3_5_RXN PCIE1_RXP/USB3_5_RXP PCIE1_TXN/USB3_5_TXN PCIE1_TXP/USB3_5_TXP

USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP

PCIE2_RXN/USB3_6_RXN PCIE2_RXP/USB3_6_RXP PCIE2_TXN/USB3_6_TXN PCIE2_TXP/USB3_6_TXP

USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP USB3_3_TXN/SSIC_2_TXN USB3_3_TXP/SSIC_2_TXP

PCIE3_RXN PCIE3_RXP PCIE3_TXN PCIE3_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

PCIE4_RXN PCIE4_RXP PCIE4_TXN PCIE4_TXP

USB2N_1 USB2P_1

PCIE5_RXN PCIE5_RXP PCIE5_TXN PCIE5_TXP

USB2N_2 USB2P_2 USB2N_3 USB2P_3

PCIE6_RXN PCIE6_RXP PCIE6_TXN PCIE6_TXP

USB2N_4 USB2P_4

PCIE7_RXN/SATA0_RXN PCIE7_RXP/SATA0_RXP PCIE7_TXN/SATA0_TXN PCIE7_TXP/SATA0_TXP

USB2N_5 USB2P_5

USB2

USB2N_6 USB2P_6

PCIE8_RXN/SATA1A_RXN PCIE8_RXP/SATA1A_RXP PCIE8_TXN/SATA1A_TXN PCIE8_TXP/SATA1A_TXP

USB2N_7 USB2P_7 USB2N_8 USB2P_8

PCIE9_RXN PCIE9_RXP PCIE9_TXN PCIE9_TXP

USB2N_9 USB2P_9

PCIE10_RXN PCIE10_RXP PCIE10_TXN PCIE10_TXP

USB2N_10 USB2P_10 USB2_COMP USB2_ID USB2_VBUSSENSE

PCIE_RCOMPN PCIE_RCOMPP

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

PROC_PRDY# PROC_PREQ# GPP_A7/PIRQA# PCIE11_RXN/SATA1B_RXN PCIE11_RXP/SATA1B_RXP PCIE11_TXN/SATA1B_TXN PCIE11_TXP/SATA1B_TXP PCIE12_RXN/SATA2_RXN PCIE12_RXP/SATA2_RXP PCIE12_TXN/SATA2_TXN PCIE12_TXP/SATA2_TXP

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2 GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 GPP_E8/SATALED#

H8 G8 C13 D13

USB30_RX_N1 USB30_RX_P1 USB30_TX_N1 USB30_TX_P1

J6 H6 B13 A13

USB30_RX_N2 USB30_RX_P2 USB30_TX_N2 USB30_TX_P2

J10 H10 B15 A15

USB30_RX_N3 USB30_RX_P3 USB30_TX_N3 USB30_TX_P3

USB30_RX_N1 USB30_RX_P1 USB30_TX_N1 USB30_TX_P1

41 41 41 41

LEFT USB (3.0)

USB30_RX_N2 45 USB30_RX_P2 45 USB30_TX_N2 45 USB30_TX_P2 45

Right USB (3.0) (Optional)

USB30_RX_N3 31 USB30_RX_P3 31 USB30_TX_N3 31 USB30_TX_P3 31

3D Camera (Optional)

E10 F10 C15 D15 AB9 AB10

USB20_N1 USB20_P1

AD6 AD7

USB20_N2 USB20_P2

AH3 AJ3

USB20_N3 USB20_P3

AD9 AD10

USB20_N4 USB20_P4

AJ1 AJ2

USB20_N5 USB20_P5

AF6 AF7

USB20_N6 USB20_P6

AH1 AH2

USB20_N7 USB20_P7

USB20_N1 41 USB20_P1 41

LEFT USB (3.0)

USB20_N2 45 USB20_P2 45

RIGHT USB (2.0)

USB20_N3 45 USB20_P3 45

RIGHT USB (2.0)

USB20_N4 33 USB20_P4 33

Camera

USB20_N5 30 USB20_P5 30

Card reader

USB20_N6 33 USB20_P6 33

Touch panel

USB20_N7 40 USB20_P7 40

BT

C

AF8 AF9 AG1 AG2 AH7 AH8 AB6 AG3 AG4

USB2_COMP USB2_ID USB2_VBUSSENSE

A9 C9 D9 B9

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

J1 J2 J3

GPP_E4 GPP_E5

H2 H3 G4

SATA0GP ODD_DETECT# SATA2GP

H1

BOARD_ID2

RC118 2 RC1626 1 RC1627 1

1 113_0402_1% 2 0_0402_5% 2 1K_0402_5%

@

USB_OC1# USB_OC2#

USBRBIAS Width 20Mil Space 15Mil Length 500Mil

41 45 B

RC1628 1

@

2 0_0402_5%

EC_SMI# 44

1 @ PAD

BOARD_ID2

8

1 OF 20

SKYLAKE-U_BGA1356 REV = 1 @

TC202

+3VS ?

GPP_E4 +3VALW_PCH

RC1617 2

@

1 10K_0402_5%

+3VS

20 PCIE_CRX_GTX_N[0..3]

RPC2 1 2 3 4

20 PCIE_CRX_GTX_P[0..3] 20 PCIE_CTX_C_GRX_N[0..3] 20 PCIE_CTX_C_GRX_P[0..3]

RPC17 8 7 6 5

ODD_DETECT# SATA0GP SATA2GP PIRQA#

USB_OC0# USB_OC1# USB_OC3# USB_OC2#

8 7 6 5

10K_0804_8P4R_5%

1 2 3 4

10K_0804_8P4R_5%

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

MCP (PCIE,SATA,USB3,USB2)

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet 1

9

of

60

5

4

3

1

?

SKL_ULT

UC1I

2

CSI-2

A36 B36 C38 D38 C36 D36 A38 B38

D

C31 D31 C33 D33 A31 B31 A33 B33 A29 B29 C28 D28 A27 B27 C27 D27

check the Pull up resistor +3VS

RPC4 1 2 3 4

8 7 6 5

CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_COMP GPP_D4/FLASHTRIG

GPP_F21/EMMC_RCLK GPP_F22/EMMC_CLK GPP_F12/EMMC_CMD EMMC_RCOMP

WLAN_CLKREQ#

E13 B7

CSI2_COMP

RC73

1

2 100_0402_1%

EMMC_RCOMP

RC50

1

2 200_0402_1%

C

AM2 AM3 AP4 AT1

?

SKL_ULT

UC1J

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

1 OF 20

SKYLAKE-U_BGA1356 REV = 1 @

10K_0804_8P4R_5%

D

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

GPU_CLKREQ# LAN_CLKREQ#

C37 D37 C32 D32 C29 D29 B26 A26

? C

CLOCK SIGNALS

B42 A42 AT7 D41 C41 AT8 D40 C40 AT10

PCIE CLK4 LAN PCIE CLK5 WLAN

37 CLK_PCIE_LAN# 37 CLK_PCIE_LAN 37 LAN_CLKREQ# 40 CLK_PCIE_WLAN# 40 CLK_PCIE_WLAN 40 WLAN_CLKREQ#

CLK_PCIE_LAN# CLK_PCIE_LAN LAN_CLKREQ#

B40 A40 AU8

CLK_PCIE_WLAN# CLK_PCIE_WLAN WLAN_CLKREQ#

E40 E38 AU7

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 GPP_B5/SRCCLKREQ0# CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1#

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B7/SRCCLKREQ2#

GPD8/SUSCLK XTAL24_IN XTAL24_OUT

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3#

XCLK_BIASREF RTCX1 RTCX2

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4#

SRTCRST# RTCRST#

F43 E43

CLK_PCIE_XDP# CLK_PCIE_XDP

BA17

SUSCLK

E37 E35

XTAL24_IN XTAL24_OUT

E42

DIFFCLK_BIASREF

AM18 AM20

RTC_X1 RTC_X2

AN18 AM16

SRTC_RST# RTC_RST#

1 1

TC85 TC87 SUSCLK

@ @

SUSCLK

40

RC72 1

2

@

DIFFCLK_BIASREF RC1555 1 2 Cannonlake@

1K_0402_5% 60.4_0402_1%

2 2.7K_0402_1%

CC3 1U_0402_6.3V6K

VCCRTC

1 OF 20

1

2

? RC33 RC34

B

1 1

SRTC_RST# RTC_RST#

2 20K_0402_1% 2 20K_0402_1% CC6 1U_0402_6.3V6K

2

1

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5#

SKYLAKE-U_BGA1356 REV = 1 @

RC71

RC95

+VCCCLK5

1

1

20 CLK_PCIE_GPU# 20 CLK_PCIE_GPU 20 GPU_CLKREQ#

D42 C42 AR10

2

2

PCIE CLK0 DGPU

CLK_PCIE_GPU# CLK_PCIE_GPU GPU_CLKREQ#

RC1624 1

@

2 0_0402_5%

EC_RTC_RST#

44

B

JCMOS1 SHORT PADS @

RTC_X1

1 1M_0402_5%

YC2 RC32 2 XTAL24_IN

CC12 3.3P_0402_50V8-C

1

1

2

GND1

OSC2

OSC1

GND2

2

RTC_X2

1 10M_0402_5%

XTAL24_OUT

3

YC1 4

24MHZ_6PF_7V24000032

1 2 1

CC11 3.3P_0402_50V8-C

1

2

32.768KHZ_9PF_X1A0001410002 CC4 7P_0402_50V8J

2

1

CC5 7P_0402_50V8J

when single end external clock generator used, this pin should be grounded

2

need to use 38.4MHz (30ohm) for Cannonlake-u A

A

Issued Date

WWW.AliSaler.Com 5

Title

LC Future Center Secret Data

Security Classification

2015/08/20

MCP (CSI2,EMMC,CLOCK)

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet 1

10

of

60

5

4

3

2

SKL_ULT

UC1K

1

?

SYSTEM POWER MANAGEMENT

20,32,37,40,44 D

PLT_RST#

44 EC_RSMRST#

@

2 0_0402_5%

RC85 1

@

2 0_0402_5%

PLT_RST#_R SYS_RESET# PCH_RSMRST#_R

AN10 B5 AY17

PAD @ TC21 VCCST_PWRGD_R

44 SYS_PWROK 44 PCH_PWROK 44 SUSWARN# 44 SUSACK# 37,40,44

RC84 1

PCIE_WAKE#

1 RC93

CPU_PROCPWRGD 2 60.4_0402_1% VCCST_PWRGD

1

A68 B65

RC139 RC126

1 1

@ @

2 0_0402_5% 2 0_0402_5%

SYS_PWROK_R PCH_PWROK_R PCH_DPWROK_R

B6 BA20 BB20

RC86 RC79

1 1

@ @

2 0_0402_5% 2 0_0402_5%

SUSWARN#_R SUSACK#_R

AR13 AP11

@

2 0_0402_5%

WAKE# PCH_LAN_WAKE#

BB15 AM15 AW17 AT15

Reserve for DS3 RC91

1

AT11 AP15 BA16 AY16

GPP_B12/SLP_S0# GPD4/SLP_S3# GPD5/SLP_S4# GPD10/SLP_S5#

GPP_B13/PLTRST# SYS_RESET# RSMRST#

SYS_PWROK PCH_PWROK DSW_PWROK

RC96 RC97

1 1

@ @

2 0_0402_5% 2 0_0402_5%

AN15 AW15 BB17 AN16

PM_SLP_SUS#_R

RC89

1

@

2 0_0402_5%

BA15 AY15 AU13

PBTN_OUT#_R AC_PRESENT_R BATLOW#

AU11 AP16

PME# INTVRMEN

PM_SLP_S3# 13,44 PM_SLP_S4# 44 D

SLP_SUS# SLP_LAN# GPD9/SLP_WLAN# GPD6/SLP_A#

PROCPWRGD VCCST_PWRGD

PM_SLP_S3#_R PM_SLP_S4#_R

GPD3/PWRBTN# GPD1/ACPRESENT GPD0/BATLOW#

GPP_A13/SUSWARN#/SUSPWRDNACK GPP_A15/SUSACK#

PM_SLP_SUS# 44

Reserve for DS3 RC87

1

RC41

2

PBTN_OUT# 44

2 0_0402_5%

@

VCCRTC GPP_A11/PME# INTRUDER#

WAKE# GPD2/LAN_WAKE# GPD11/LANPHYPC GPD7/RSVD

@1

TC89 1 330K_0402_5%

AM10 AM11

GPP_B11/EXT_PWR_GATE# GPP_B2/VRALERT# 1 OF 20

SKYLAKE-U_BGA1356 REV = 1 @

?

+3VALW

1

2 10K_0402_5%

AC_PRESENT_R

RC75

1

2 8.2K_0402_5%

BATLOW#

RC76

2

1 1K_0402_5%

WAKE#

RC90

1

2 10K_0402_5%

PCH_LAN_WAKE#

1

RC88

44 AC_PRESENT

@

Follow CRB change to 1kohm

C

3 2 10K_0402_5%

@

+3VALW

RC137 1K_0402_5%

SYS_RESET#

RC1554 1K_0402_5% @

RC136 10K_0402_5% @

2 CC104

VCCST_PWRGD_R 3

0.01U_0201_10V6K 1

PCH_RSMRST#_R

5

1

47P_0201_25V8-J

2 CC103 EMC_NS@

PCH_DPWROK_R

2 CC101

SYS_PWROK

2 CC1260

EC_RSMRST#

6

PCH_PWROK RC138

44 EC_VCCST_PWRGD

1

@

2 0_0402_5%

2 B

0.01U_0201_10V6K 1

QC6A 2N7002KDWH_SOT363-6 @

G

1

S

D

2

2

1

CC140 1000P_0201_50V7-K EMC_NS@

S

CC46 0.01U_0201_25V6-K EMC_NS@

1

1000P_0201_50V7-K 1

QC6B 2N7002KDWH_SOT363-6 @

G

Stuff to fix Reset&PWRGD test fail issue

D

4

2 CC1254 EMC_NS@

1

1000P_0201_50V7-K 1

1

1

2

2 10K_0402_5%

+VCCSTG

2

2

+3VS

1

S

SUSWARN#_R +VCCST_CPU

RC80

C

QC8 2N7002KW_SOT323-3 @

G

+3VALW_PCH

1

D

2

44 ACIN#

RC78

AC_PRESENT_R

2 0_0402_5%

1

RC74

B

Add to fix Reset&PWRGD test fail issue RC1599 1

RPC21 1 2 3 4

PM_SLP_S3#

10K_0804_8P4R_5%

100K_0402_5%

2

100K_0402_1%

2

@

@

2 0_0402_5%

PCH_RSMRST#_R PCH_PWROK SYS_PWROK

8 7 6 5

DC4

1

2

@

RB751V-40_SOD323-2

1 RC92

PLT_RST#_R

1 RC94

PCH_DPWROK_R

PCH_DPWROK_R

RC182

1

RC81

1

@

2 0_0402_5%

@

2 0_0402_5%

EC_RSMRST#

DPWROK_EC

44

Reserve for DS3

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

MCP (SYSTEM PWR MANAGEMENT)

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet 1

11

of

60

5

4

+CPU_CORE

?

@

TC92

RSVD_AK32

AB62 P62 V62

+V_EDRAM_VR

1

@

TC94

1

@ @

TC95 TC97

1 1

@

TC99

1

VCCSTG_G20

@ @

TC100 TC101

1 1

VCCGT_VCC_SEN

2 100_0402_1%

1

1

VCORE_VCC_SEN VCORE_VSS_SEN

B63 A63 D64

CPU_SVID_ALERT#_R CPU_SVID_CLK_R CPU_SVID_DAT_R

VCORE_VCC_SEN 59 VCORE_VSS_SEN 59

G20

+VCCSTG

VCC_OPC_1P8_G61

AC63 AE63

59 VR_SVID_ALRT#

59 VR_SVID_CLK VCCEOPIO_AE62 VCCEOPIO_AG62 59 VR_SVID_DAT

AL63 AJ62

2

VCCEOPIO_SENSE VSSEOPIO_SENSE

RC133

1

2 100_0402_1%

CC42 0.1u_0201_10V6K @

RC134

1

RC1545 1

2 220_0402_1%

CPU_SVID_ALERT#_R

@

2 0_0402_5%

CPU_SVID_CLK_R

@

2 0_0402_5%

CPU_SVID_DAT_R

1, Alert# Route Between CLK and Data 1 OF 20

SKYLAKE-U_BGA1356 REV = 1 @

?

+CPU_CORE +VCC_GT

C

Backside Cap 8x10uF 0402, SIT update

2

1

2

CD@

CC1129 10U_0402_6.3V6M

2

CD@

1

CC1128 10U_0402_6.3V6M

2 @

1

CC1127 10U_0402_6.3V6M

2

1

CC1126 10U_0402_6.3V6M

2 @

1

CC1125 10U_0402_6.3V6M

2 @

1

CC1124 10U_0402_6.3V6M

2 @

1

CC1123 10U_0402_6.3V6M

2

1

CC1122 10U_0402_6.3V6M

2

1

CC1238 10U_0603_6.3V6M

2

1

CC1089 10U_0603_6.3V6M

2

1

CC1091 10U_0603_6.3V6M

2

1

CC1092 10U_0603_6.3V6M

2

1

CC1093 10U_0603_6.3V6M

2

1

CC1237 10U_0603_6.3V6M

2

CD@

1

CC1236 10U_0603_6.3V6M

2

1

CC1080 10U_0603_6.3V6M

1

CC1085 10U_0402_6.3V6M

2 @

CC1086 10U_0402_6.3V6M

13x10uF 0402, SIT update to 0603 package

1

SKL_ULT

+VCC_GT

?

CPU POWER 2 OF 4

A48 A53 A58 A62 A66 AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71 J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60 K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71 M62 N63 N64 N66 N67 N69

@

VCCOPC_SENSE VSSOPC_SENSE

AE62 AG62

1

RC98

UC1M

2 100_0402_1%

+VCCST_CPU

SVID

E32 E33

1

RC83

VCCGT_VSS_SEN

2 100_0402_1%

VCC_OPC_1P8_H63

G61

+VCCEOPIO

VIDALERT# VIDSCK VIDSOUT

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

H63 +V1.8S_EDRAM

VCC_SENSE VSS_SENSE

RC82

1

1

AK32

RSVD_K32

VCORE_VSS_SEN

RC77

RC132 100_0402_1%

K32

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

2

1

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42 VCC_J30 VCC_J33 VCC_J37 VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

1

TC90

VCORE_VCC_SEN

VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RC1544 100_0402_1%

@

+VCC_GT

2

D

1

+VCC_GT

1

A30 A34 A39 A44 AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40 AM32 AM33 AM35 AM37 AM38 G30

2

+CPU_CORE

CPU POWER 1 OF 4

2

SKL_ULT

UC1L

RC131 56_0402_5%

+CPU_CORE

3

VCCGT_VCC_SEN VCCGT_VSS_SEN

59 VCCGT_VCC_SEN 59 VCCGT_VSS_SEN

J70 J69

VCCGT_A48 VCCGT_A53 VCCGT_A58 VCCGT_A62 VCCGT_A66 VCCGT_AA63 VCCGT_AA64 VCCGT_AA66 VCCGT_AA67 VCCGT_AA69 VCCGT_AA70 VCCGT_AA71 VCCGT_AC64 VCCGT_AC65 VCCGT_AC66 VCCGT_AC67 VCCGT_AC68 VCCGT_AC69 VCCGT_AC70 VCCGT_AC71 VCCGT_J43 VCCGT_J45 VCCGT_J46 VCCGT_J48 VCCGT_J50 VCCGT_J52 VCCGT_J53 VCCGT_J55 VCCGT_J56 VCCGT_J58 VCCGT_J60 VCCGT_K48 VCCGT_K50 VCCGT_K52 VCCGT_K53 VCCGT_K55 VCCGT_K56 VCCGT_K58 VCCGT_K60 VCCGT_L62 VCCGT_L63 VCCGT_L64 VCCGT_L65 VCCGT_L66 VCCGT_L67 VCCGT_L68 VCCGT_L69 VCCGT_L70 VCCGT_L71 VCCGT_M62 VCCGT_N63 VCCGT_N64 VCCGT_N66 VCCGT_N67 VCCGT_N69 VCCGT_SENSE VSSGT_SENSE

VCCGT_N70 VCCGT_N71 VCCGT_R63 VCCGT_R64 VCCGT_R65 VCCGT_R66 VCCGT_R67 VCCGT_R68 VCCGT_R69 VCCGT_R70 VCCGT_R71 VCCGT_T62 VCCGT_U65 VCCGT_U68 VCCGT_U71 VCCGT_W63 VCCGT_W64 VCCGT_W65 VCCGT_W66 VCCGT_W67 VCCGT_W68 VCCGT_W69 VCCGT_W70 VCCGT_W71 VCCGT_Y62 VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56 VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66 VCCGTX_SENSE VSSGTX_SENSE

SKYLAKE-U_BGA1356 1 OF 20 REV = 1 @

+CPU_CORE

1

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66 AK62 AL61

TC135 @

C

VCCGTX_SENSE VSSGTX_SENSE

1 1

TC133 TC134

@ @

?

2

1

2

1U_0402_6.3V6K CC1241

2

1

1U_0402_6.3V6K CC1240

2

1

1U_0402_6.3V6K CC1119

2

1

1U_0402_6.3V6K CC1118

2

1

1U_0402_6.3V6K CC1116

2

1

1U_0402_6.3V6K CC1115

2 @

1

1U_0402_6.3V6K CC1114

2 @

1

1U_0402_6.3V6K CC1111

2

1

CC1109 1U_0201_6.3V6-M

2

1

CC1108 1U_0201_6.3V6-M

2

1

1U_0402_6.3V6K CC1105

2

1

Backside Cap 12x1uF 0201, SIT update 1U_0402_6.3V6K CC1104

2

1

1U_0402_6.3V6K CC1102

2

1

1U_0402_6.3V6K CC1101

2

1

1U_0402_6.3V6K CC1100

2

1

SIT update to 0402 package

1U_0402_6.3V6K CC1099

2

1

1U_0402_6.3V6K CC1098

1

1U_0402_6.3V6K CC1097

1U_0402_6.3V6K CC1096

1U_0402_6.3V6K CC1095

2

D

+VCC_GT

15x1uF 0201,

1

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

1

2

B

B

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification

Deciphered Date

2015/08/20

MCP (CPU PWR1)

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

WWW.AliSaler.Com

4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016 1

Sheet

12

of

60

5

4

3

2

1

+VCCIO

+VCCSTG

+VCCST_CPU

+VDDQ_CPU_CLK

VCCIO_SENSE VSSIO_SENSE

1

2 @

1

2

RC103

+VCCIO

1

RC1604 1

+VCCST_CPU

2 0_0402_5% 2 0_0402_5%

@

1

Reserved for VCCST/VCCSTG/VCCPLL power optimized

2

1

CC87 1U_0402_6.3V6K

2 0_0402_5% CC1228 10U_0402_6.3V6M

@

CC1229 1U_0201_6.3V6-M

RC1497 1

2

CC86 1U_0402_6.3V6K

120mA +1.2V

VSSSA_SENSE VCCSA_SENSE SKYLAKE-U_BGA13561 OF 20 REV = 1 @

1

2

1

2

CC1232 1U_0402_6.3V6K

CC1231 1U_0402_6.3V6K

CC1230 1U_0402_6.3V6K

CC1218 1U_0402_6.3V6K

CC1161 1U_0201_6.3V6-M

CC1160 1U_0201_6.3V6-M

10x10uF, 7x1uF, SIT update

1

2

@

AM23 AM22

VCCIO_SENSE VSSIO_SENSE

H21 H20

VCCSA_VSS_SEN VCCSA_VCC_SEN

1 1

1

2

1

2

1

2

1

2

@

1

2

@

1

2

1

2

@

1

2

1

2

CD@

1

2

1

2

1

2

CD@

1

2

CC1144 1U_0201_6.3V6-M

4.5A

CC1143 1U_0201_6.3V6-M

VCCPLL_K20 VCCPLL_K21

D

+VCCSA

CC1141 1U_0201_6.3V6-M

VCCPLL_OC

+VCCSA

CC1145 1U_0402_6.3V6K

K20 K21

+VCCPLL_CPU

@

CC1142 1U_0402_6.3V6K

AL23

VCCSTG_A22

@

2

CC1140 1U_0402_6.3V6K

+VCCSFR_OC

VCCST

2

1

CC1139 1U_0402_6.3V6K

A22

2

1

CC1253 10U_0402_6.3V6M

+VCCSTG

VDDQC

2

1

CC1252 10U_0402_6.3V6M

A18

@

2

1

CC1251 10U_0603_6.3V6M

AM40

+VCCST_CPU

@

2

1

CC1137 10U_0603_6.3V6M

@

+VDDQ_CPU_CLK

2

1

CC1136 10U_0603_6.3V6M

CD@

2

2

@

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

VCCSA_AK23 VCCSA_AK25 VCCSA_G23 VCCSA_G25 VCCSA_G27 VCCSA_G28 VCCSA_J22 VCCSA_J23 VCCSA_J27 VCCSA_K23 VCCSA_K25 VCCSA_K27 VCCSA_K28 VCCSA_K30

2

1

CC1135 10U_0402_6.3V6M

@

2

1

AK28 AK30 AL30 AL42 AM28 AM30 AM42

VCCIO_AK28 VCCIO_AK30 VCCIO_AL30 VCCIO_AL42 VCCIO_AM28 VCCIO_AM30 VCCIO_AM42

CC1134 10U_0402_6.3V6M

CD@

2

1

CC1227 1U_0201_6.3V6-M

@

2

1

CC1226 1U_0201_6.3V6-M

@

2

1

CC1225 1U_0201_6.3V6-M

2

1

CC1224 1U_0201_6.3V6-M

2

1

CC1244 10U_0402_6.3V6M

2

1

CC1243 10U_0402_6.3V6M

CD@

2

1

CC1223 10U_0603_6.3V6M

2

1

CC1222 10U_0603_6.3V6M

2

1

CC1171 10U_0402_6.3V6M

2

1

CC1169 10U_0402_6.3V6M

CD@

2

1

CC1168 10U_0603_6.3V6M

2

1

CC1258 22U_0603_6.3V6-M

1

2A , 3x22uF, 6x10uF, 4x1uF, SIT update

CC1257 22U_0603_6.3V6-M

D

CC1256 22U_0603_6.3V6-M

+1.2V

2

VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51

1

CC1159 1U_0201_6.3V6-M

CPU POWER 3 OF 4

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

1

CC1158 1U_0201_6.3V6-M

1

?

CC1133 10U_0603_6.3V6M

SKL_ULT

CC1132 10U_0603_6.3V6M

UC1N

2x10uF, 4x1uF

CC1153 10U_0402_6.3V6M

+VCCIO +1.2V

CC1152 10U_0402_6.3V6M

3.1A

CD@

TC136 @ TC137 @ VCCSA_VSS_SEN 59 VCCSA_VCC_SEN 59

? +VCCSA

+VCCSFR_OC VCCSA_VCC_SEN

RC101

1

2 100_0402_1%

VCCSA_VSS_SEN

RC102

1

2 100_0402_1%

+VCCPLL_CPU 2 0_0402_5% 1 C

2

120mA 1

RC105

+VCCST_CPU

2 0_0402_5% 1

2

1

2

C

CC84 1U_0402_6.3V6K

@

CC1249 0.1u_0201_10V6K

1

CC85 1U_0201_6.3V6-M

RC104

+1.0VALW

+VCCST_CPU

1

RC1605

@

2

0_0402_5%

Reserved for VCCST/VCCSTG/VCCPLL power optimized

S

1 2 1

QC13 2N7002KW_SOT323-3 @ 3

1

2 RC1411 47K_0402_5%

S

VCCST_EN#

2

1

D

QC16A 2N7002KDWH_SOT363-6

G

44 EC_VCCST_EN

EC_VCCST_EN

2

3

1 2 100K_0402_5%

S

RC1584 120K_0402_5%

QC16B 2N7002KDWH_SOT363-6

3

4

S

A

11,44 PM_SLP_S3#

RC1577

1

DC1

1

@

2 0_0402_5%

VCCIO_EN

5

QC12B 2N7002KDWH_SOT363-6

G

2

+VCCST_CPU switch

D

@

A

S

RB751V-40_SOD323-2

4

44 EC_VCCIO_EN

S

D

5 G

1

1

RC1575 47K_0402_5% @

2

QC14 2N7002KW_SOT323-3 @

2

2

RC125 470K_0402_5%

D

2

1

QC12A 2N7002KDWH_SOT363-6

G

RC142

+3VALW

1

D

2

2 @

D

3

VCCIO_EN#

2

RC135 470_0603_5% @

VCCST_EN#

2

1 2 47K_0402_5%

CC77 0.01U_0201_25V6-K

6 2

RC128

1

G

G

1

1

2

CC79 10U_0603_6.3V6M

1 1 VCCIO_EN#

1 100K_0402_5%

B

3

V20B+

V20B+ 2

S

RC124 470_0603_5% @

+3VALW RC1621

D

CC81 0.01U_0201_25V6-K

2 @

6

2

1

2

4

1

C1102 22U_0603_6.3V6-M

G

1 2 3 10U_0603_6.3V6M

@

2

S1 S2 S3

D

CC1250

2

1

CC72 10U_0603_6.3V6M

1

CC71 22U_0603_6.3V6-M

5

1

+VCCIO

AON7408L_DFN8-5 QC11

G

B

+1.0VALW

+VCCST_CPU

QC19 AO3402_SOT-23-3

CC80 10U_0603_6.3V6M

+1.0VALW

Issued Date

Title

LC Future Center Secret Data

Security Classification

Deciphered Date

2015/08/20

MCP (CPU PWR2)

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016 1

Sheet

13

of

60

5

4

3

2

+3VALW_PCH

+1.0VALW

RC1503

1

+1.0VALW

RC1504

1

@

2 0_0603_5%

+VCCAMPHY

2 0_0603_5%

+VCCAPLL_1P0

+VCCPGPPG

RC1622

D

1

1

2

@

0_0402_5%

D

+VCCHDA RC1585 1

+3VS

RC1586 1

+3VALW_PCH

@

2 0_0402_5%

2 0_0603_5%

VCCMPHYON_1P0_L1

1

2

CC144 1U_0402_6.3V6K

RC1620 1

+1.0VALW

2 0_0402_5%

@

+3VALW_PCH

V15

+VCCHDA

1

2

AD17 AD18 AJ17

0.118A

+3VALW

68mA

AJ19 11mA

+3VALW_PCH

AJ16

2 CD@

AF20 AF21 T19 T20

Near AF20 75mA

+3VALW_PCH

1

B

2

CC171 1U_0402_6.3V6K

1

CC159 1U_0402_6.3V6K

0.642A

+1.0VALW

AJ21 AK20

+1.0VALW +1.0VALW

N18

33mA

1

CD@

2

CC169 1U_0402_6.3V6K

2

+1.0VALW CC165 0.1u_0201_10V6K

1

CC154 1U_0402_6.3V6K

2

C1097 0.1u_0201_10V6K

1

AB17 Y18

VCCRTCPRIM_3P3 VCCRTC_AK19 VCCRTC_BB14

VCCAMPHYPLL_1P0_K15 VCCAMPHYPLL_1P0_L15

DCPRTC VCCCLK1

VCCAPLL_1P0 VCCCLK2 VCCPRIM_1P0_AB17 VCCPRIM_1P0_Y18

VCCCLK3

VCCDSW_3P3_AD17 VCCDSW_3P3_AD18 VCCDSW_3P3_AJ17

VCCCLK4

VCCHDA

VCCCLK6

VCCCLK5

VCCSPI

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

CC174 1U_0402_6.3V6K

+1.8VALW

2 @

V19 T1

+3VALW_PCH

1

2

+1.0VALW

AA1

6mA

AK17

1mA

+1.8VALW

C

1

2

2

+3VALW_PCH

1mA

AK19 BB14 BB10

1

CC143 1U_0402_6.3V6K

VCCATS_1P8 VCCMPHYGT_1P0_N15 VCCMPHYGT_1P0_N16 VCCMPHYGT_1P0_N17 VCCMPHYGT_1P0_P15 VCCMPHYGT_1P0_P16

1

1

VCCRTCEXT

A14

35mA

K19

29mA

L21

24mA

N20

33mA

L19

4mA

A10

10mA

+1.0VALW

1

0_0603_5%

1

+1.0VALW +VCCCLK4

2

+VCCCLK5

AN11 AN13

1

VCCSRAM_1P0_AF20 VCCSRAM_1P0_AF21 VCCSRAM_1P0_T19 VCCSRAM_1P0_T20

2

+1.0VALW

1

2 @

@

2 RC1587 +1.0VALW

1

2

2

1

2

CC1242 1U_0402_6.3V6K

K15 L15

VCCPRIM_1P0_T1

2 @

CC146 0.1u_0201_10V6K

Near K15

VCCPRIM_3P3_V19

VCCMPHYAON_1P0_K17 VCCMPHYAON_1P0_L1

1

Near Y15

CC149 0.1u_0201_10V6K

N15 N16 N17 P15 P16

DCPDSW_1P0

2 @

CC55 0.1u_0201_10V6K

K17 L1

VCCMPHYON_1P0_L1

20mA 4mA 6mA 8mA 6mA 161mA 61mA

2

+VCCPGPPG

CC142 1U_0402_6.3V6K

AL1

VCCPRIM_CORE_AF18 VCCPRIM_CORE_AF19 VCCPRIM_CORE_V20 VCCPRIM_CORE_V21

AK15 AG15 Y16 Y15 T16 AF16 AD15

2 @

1

CC176 1U_0402_6.3V6K

PCH Internal VRM

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF VCCPGPPG

2 @

1

CC175 1U_0402_6.3V6K

AF18 AF19 V20 V21

VCCPRIM_1P0_AB19 VCCPRIM_1P0_AB20 VCCPRIM_1P0_P18

1

CC173 1U_0402_6.3V6K

CC153 1U_0402_6.3V6K

Near AF18

22mA

+VCCAPLL_1P0

2 @

CPU POWER 4 OF 4

AB19 AB20 P18

1

C1098 22U_0603_6.3V6-M

2

@

UC1O

?

CC56 1U_0402_6.3V6K

2 @

1

CC151 1U_0402_6.3V6K

1

C1096 22U_0603_6.3V6-M

+VCCAMPHY

2

1 SKL_ULT

VCCRTC

VCCPRIM_3P3_AJ21 VCCPRIM_1P0_AK20

SKYLAKE-U_BGA1356 REV = 1 @

0_0603_5%

+VCCCLK4

VCCAPLLEBB

1

1 OF 20 ?

2 @

0_0603_5%

+VCCCLK5

Near A18

1

2 @

1

@

2 RC1588

+1.0VALW

@

2 RC1589

+1.0VALW

C1099 22U_0603_6.3V6-M

2

2

2 @

1

C1100 22U_0603_6.3V6-M

Near N15 88mA

1

CC147 1U_0201_6.3V6-M

1

CC148 47U_0805_4V6-M

2 C

2 @

1

CC57 1U_0402_6.3V6K

+1.0VALW

22U_0603_6.3V6-M

1 1.5A

CC145 1U_0402_6.3V6K

+VCCDSW_1P0

1

CC158

2.574A

+1.0VALW

CC172 1U_0402_6.3V6K

1 22mA

+1.0VALW

CC164 1U_0402_6.3V6K

Near AB19

CC156 1U_0402_6.3V6K

+1.0VALW

CC141 1U_0402_6.3V6K

0.696A

B

A

A

Issued Date

WWW.AliSaler.Com 5

Title

LC Future Center Secret Data

Security Classification

Deciphered Date

2015/08/20

MCP (PCH PWR)

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016 1

Sheet

14

of

60

5

4

SKL_ULT UC1P

3

2

SKL_ULT UC1Q

?

1

? ?

SKL_ULT

UC1R

GND 2 OF 3 GND 1 OF 3

A5 A67 A70 AA2 AA4 AA65 AA68 AB15 AB16 AB18 AB21 AB8 AD13 AD16 AD19 AD20 AD21 AD62 AD8 AE64 AE65 AE66 AE67 AE68 AE69 AF1 AF10 AF15 AF17 AF2 AF4 AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13 AH6 AH63 AH64 AH67 AJ15 AJ18 AJ20 AJ4 AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69 AK8 AL2 AL28 AL32 AL35 AL38 AL4 AL45 AL48 AL52 AL55 AL58 AL64

D

C

B

VSS_A5 VSS_A67 VSS_A70 VSS_AA2 VSS_AA4 VSS_AA65 VSS_AA68 VSS_AB15 VSS_AB16 VSS_AB18 VSS_AB21 VSS_AB8 VSS_AD13 VSS_AD16 VSS_AD19 VSS_AD20 VSS_AD21 VSS_AD62 VSS_AD8 VSS_AE64 VSS_AE65 VSS_AE66 VSS_AE67 VSS_AE68 VSS_AE69 VSS_AF1 VSS_AF10 VSS_AF15 VSS_AF17 VSS_AF2 VSS_AF4 VSS_AF63 VSS_AG16 VSS_AG17 VSS_AG18 VSS_AG19 VSS_AG20 VSS_AG21 VSS_AG71 VSS_AH13 VSS_AH6 VSS_AH63 VSS_AH64 VSS_AH67 VSS_AJ15 VSS_AJ18 VSS_AJ20 VSS_AJ4 VSS_AK11 VSS_AK16 VSS_AK18 VSS_AK21 VSS_AK22 VSS_AK27 VSS_AK63 VSS_AK68 VSS_AK69 VSS_AK8 VSS_AL2 VSS_AL28 VSS_AL32 VSS_AL35 VSS_AL38 VSS_AL4 VSS_AL45 VSS_AL48 VSS_AL52 VSS_AL55 VSS_AL58 VSS_AL64

VSS_AL65 VSS_AL66 VSS_AM13 VSS_AM21 VSS_AM25 VSS_AM27 VSS_AM43 VSS_AM45 VSS_AM46 VSS_AM55 VSS_AM60 VSS_AM61 VSS_AM68 VSS_AM71 VSS_AM8 VSS_AN20 VSS_AN23 VSS_AN28 VSS_AN30 VSS_AN32 VSS_AN33 VSS_AN35 VSS_AN37 VSS_AN38 VSS_AN40 VSS_AN42 VSS_AN58 VSS_AN63 VSS_AP10 VSS_AP18 VSS_AP20 VSS_AP23 VSS_AP28 VSS_AP32 VSS_AP35 VSS_AP38 VSS_AP42 VSS_AP58 VSS_AP63 VSS_AP68 VSS_AP70 VSS_AR11 VSS_AR15 VSS_AR16 VSS_AR20 VSS_AR23 VSS_AR28 VSS_AR35 VSS_AR42 VSS_AR43 VSS_AR45 VSS_AR46 VSS_AR48 VSS_AR5 VSS_AR50 VSS_AR52 VSS_AR53 VSS_AR55 VSS_AR58 VSS_AR63 VSS_AR8 VSS_AT2 VSS_AT20 VSS_AT23 VSS_AT28 VSS_AT35 VSS_AT4 VSS_AT42 VSS_AT56 VSS_AT58

1 OF 20 SKYLAKE-U_BGA1356 REV = 1 @

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

AT63 AT68 AT71 AU10 AU15 AU20 AU32 AU38 AV1 AV68 AV69 AV70 AV71 AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57 AW6 AW60 AW62 AW64 AW66 AW8 AY66 B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71 BA1 BA10 BA14 BA18 BA2 BA23 BA28 BA32 BA36 F68 BA45

VSS_AT63 VSS_AT68 VSS_AT71 VSS_AU10 VSS_AU15 VSS_AU20 VSS_AU32 VSS_AU38 VSS_AV1 VSS_AV68 VSS_AV69 VSS_AV70 VSS_AV71 VSS_AW10 VSS_AW12 VSS_AW14 VSS_AW16 VSS_AW18 VSS_AW21 VSS_AW23 VSS_AW26 VSS_AW28 VSS_AW30 VSS_AW32 VSS_AW34 VSS_AW36 VSS_AW38 VSS_AW41 VSS_AW43 VSS_AW45 VSS_AW47 VSS_AW49 VSS_AW51 VSS_AW53 VSS_AW55 VSS_AW57 VSS_AW6 VSS_AW60 VSS_AW62 VSS_AW64 VSS_AW66 VSS_AW8 VSS_AY66 VSS_B10 VSS_B14 VSS_B18 VSS_B22 VSS_B30 VSS_B34 VSS_B39 VSS_B44 VSS_B48 VSS_B53 VSS_B58 VSS_B62 VSS_B66 VSS_B71 VSS_BA1 VSS_BA10 VSS_BA14 VSS_BA18 VSS_BA2 VSS_BA23 VSS_BA28 VSS_BA32 VSS_BA36 VSS_F68 VSS_BA45

VSS_BA49 VSS_BA53 VSS_BA57 VSS_BA6 VSS_BA62 VSS_BA66 VSS_BA71 VSS_BB18 VSS_BB26 VSS_BB30 VSS_BB34 VSS_BB38 VSS_BB43 VSS_BB55 VSS_BB6 VSS_BB60 VSS_BB64 VSS_BB67 VSS_BB70 VSS_C1 VSS_C25 VSS_C5 VSS_D10 VSS_D11 VSS_D14 VSS_D18 VSS_D22 VSS_D25 VSS_D26 VSS_D30 VSS_D34 VSS_D39 VSS_D44 VSS_D45 VSS_D47 VSS_D48 VSS_D53 VSS_D58 VSS_D6 VSS_D62 VSS_D66 VSS_D69 VSS_E11 VSS_E15 VSS_E18 VSS_E21 VSS_E46 VSS_E50 VSS_E53 VSS_E56 VSS_E6 VSS_E65 VSS_E71 VSS_F1 VSS_F13 VSS_F2 VSS_F22 VSS_F23 VSS_F27 VSS_F28 VSS_F32 VSS_F33 VSS_F35 VSS_F37 VSS_F38 VSS_F4 VSS_F40 VSS_F42 VSS_BA41

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

GND 3 OF 3

F8 G10 G22 G43 G45 G48 G5 G52 G55 G58 G6 G60 G63 G66 H15 H18 H71 J11 J13 J25 J28 J32 J35 J38 J42 J8 K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71 L11 L16 L17

VSS_F8 VSS_G10 VSS_G22 VSS_G43 VSS_G45 VSS_G48 VSS_G5 VSS_G52 VSS_G55 VSS_G58 VSS_G6 VSS_G60 VSS_G63 VSS_G66 VSS_H15 VSS_H18 VSS_H71 VSS_J11 VSS_J13 VSS_J25 VSS_J28 VSS_J32 VSS_J35 VSS_J38 VSS_J42 VSS_J8 VSS_K16 VSS_K18 VSS_K22 VSS_K61 VSS_K63 VSS_K64 VSS_K65 VSS_K66 VSS_K67 VSS_K68 VSS_K70 VSS_K71 VSS_L11 VSS_L16 VSS_L17

VSS_L18 VSS_L2 VSS_L20 VSS_L4 VSS_L8 VSS_N10 VSS_N13 VSS_N19 VSS_N21 VSS_N6 VSS_N65 VSS_N68 VSS_P17 VSS_P19 VSS_P20 VSS_P21 VSS_R13 VSS_R6 VSS_T15 VSS_T17 VSS_T18 VSS_T2 VSS_T21 VSS_T4 VSS_U10 VSS_U63 VSS_U64 VSS_U66 VSS_U67 VSS_U69 VSS_U70 VSS_V16 VSS_V17 VSS_V18 VSS_W13 VSS_W6 VSS_W9 VSS_Y17 VSS_Y19 VSS_Y20 VSS_Y21

1 OF 20 SKYLAKE-U_BGA1356 REV = 1 @

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

D

C

?

B

1 OF 20 SKYLAKE-U_BGA1356 REV = 1 @

?

?

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

MCP (VSS)

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet 1

15

of

60

5

4

3

2

1

? SKL_ULT

UC1S

RESERVED SIGNALS-1

1 1

CPU_CFG16 CPU_CFG17

E63 F63

PAD @ TC161 PAD @ TC160

1 1

CPU_CFG18 CPU_CFG19

E66 F66

CFG_RCOMP

C

2

PAD @ TC166

1

E60

XDP_ITP_PMODE

E8 AY2 AY1

RC162 49.9_0402_1% 1

PAD @ TC186

D1 D3

1

K46 K45 AL25 AL27 PAD @ TC189 PAD @ TC191

C71 B70

1 1

F60 A52 B

PAD @ TC171 PAD @ TC172

BA70 BA68

1 1

J71 J68 PAD @ TC169 PAD @ TC170

F65 G65

1 1

F61 E61

TC173 @ PAD TC174 @ PAD

AK13 AK12

1 1

TC175 @ PAD TC176 @ PAD

D

BB2 BA3

UC1T

SKL_ULT

TP5 TP6 RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2 RSVD_B3 RSVD_A3

CFG[18] CFG[19]

RSVD_AW1 CFG_RCOMP RSVD_E1 RSVD_E2

ITP_PMODE RSVD_AY2 RSVD_AY1

RSVD_BA4 RSVD_BB4

RSVD_D1 RSVD_D3

RSVD_A4 RSVD_C4

RSVD_K46 RSVD_K45

TP4 RSVD_A69 RSVD_B69

RSVD_AL25 RSVD_AL27

RSVD_AY3 RSVD_C71 RSVD_B70

RSVD_D71 RSVD_C70

RSVD_F60 RSVD_C54 RSVD_D54

RSVD_A52 RSVD_TP_BA70 RSVD_TP_BA68

TP1 TP2

RSVD_J71 RSVD_J68

VSS_AY71 ZVM#

VSS_F65 VSS_G65

RSVD_TP_AW71 RSVD_TP_AW70

RSVD_F61 RSVD_E61

MSM# PROC_SELECT#

AU5 AT5 D5 D4 B2 C2

1 1

TC183 @ PAD TC185 @ PAD

B3 A3

1 1

TC184 @ PAD TC181 @ PAD

1

TC187 @ PAD

1

TC182 @ PAD

1 1

TC188 @ PAD TC193 @ PAD

1 1

TC190 @ PAD TC192 @ PAD

AW69 AW68 AU56 AW48 C7 Cannonlake@ 1 0_0402_5% RSVD_U12 U12 RC1582 2 1 0_0402_5% RSVD_U11 U11 RC1583 2 Cannonlake@ H11

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11 1 OF 20 SKYLAKE-U_BGA1356 REV = 1 @

AW1 E1 E2

+VCCST_CPU

?

SPARE

+1.8VALW

CFG[16] CFG[17]

SKYLAKE-U_BGA1356 REV = 1 @

Pin Name Strap Description

RSVD_BB2 RSVD_BA3

1 1

1

PAD @ TC159 PAD @ TC158

RSVD_TP_AK13 RSVD_TP_AK12

BB68 BB69

RSVD_F6 RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

F6 E3 C11 B11 A11 D12 C12 F52 RSVD_F52

RC1619 150_0402_5% @

2

1 1 1 1 1 1 1 1 1 1 1

RSVD_TP_BB68 RSVD_TP_BB69

? C

BA4 BB4 A4 C4 BB5 A69 B69 AY3

RSVD_AY3

D71 C70

need to check with Intel

2

PAD @ TC146 PAD @ TC147 PAD @ TC148 PAD @ TC153 PAD @ TC150 PAD @ TC151 PAD @ TC152 PAD @ TC157 PAD @ TC154 PAD @ TC155 PAD @ TC156

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

RC107 0_0402_5%

C54 D54

1

1 1 1

B

AY4 BB3 AY71 AR56

VSS_AY71

need to check with Intel

1

TC167 @ PAD

AW71 AW70

1 1

TC177 @ PAD TC178 @ PAD

AP56 C64

1

2

1

RC106 1K_0402_5%

PAD @ TC142 PAD @ TC143 PAD @ TC144

E68 B67 D65 D67 E70 C68 D68 C67 F71 G69 F70 G68 H70 G71 H69 G70

TC168 @ PAD PROC_SELECT# 1 2 100K_0402_5% Cannonlake@

RC108 0_0402_5% R22

+VCCST_CPU

1

1

RC1618 1K_0402_5% @

2

2

D

CPU_CFG0 CPU_CFG1 CPU_CFG2 XDP_CPU_CFG3 CPU_CFG4 CPU_CFG5 CPU_CFG6 CPU_CFG7 CPU_CFG8 CPU_CFG9 CPU_CFG10 CPU_CFG11 CPU_CFG12 CPU_CFG13 CPU_CFG14 CPU_CFG15

1 OF 20 ?

Default Value

Configuration

A

A

CFG[4]

Display Port Presence strap

— 1 = eDP Disabled — 0 = eDP Enabled

1

*

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

MCP (CFG,RESERVED)

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

WWW.AliSaler.Com

4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet 1

16

of

60

5

4

3

2

1

DDRA_DQ[0..63]

DDRA_ODT0

K3

DDRA_PAR

T3 N9

F1 H1 A2 D2 E3 A8 D8 E8 C9 H9

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10

+VREF_CA_MD

M1 E1 K1 N1 T1 B2 G8 E9 K9 M9

1

2

1

2

1

2

1

2

RD95 1

DDRA_ODT0

K3

DDRA_PAR

T3

2 10K_0402_5% TEN_UD2

N9

CPU_DRAMRST# @ 1

T7

NC

2

P1 F1 H1 A2 D2 E3 A8 D8 E8 C9 H9 F9

ODT

VPP1 VPP2

PAR

VREFCA

TEN

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

RESET_N VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10

NC

+VREF_CA_MD

M1 E1 K1 N1 T1 B2 G8 E9 K9 M9

1

2

1

2

1

2

1

2

34.8_0402_1% 34.8_0402_1%

2

34.8_0402_1%

DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3

RD54 RD55 RD56 RD57

1 1 1 1

2 2 2 2

34.8_0402_1% 34.8_0402_1% 34.8_0402_1% 34.8_0402_1%

DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7

RD58 RD59 RD60 RD61

1 1 1 1

2 2 2 2

34.8_0402_1% 34.8_0402_1% 34.8_0402_1% 34.8_0402_1%

DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11

RD62 RD63 RD64 RD67

1 1 1 1

2 2 2 2

34.8_0402_1% 34.8_0402_1% 34.8_0402_1% 34.8_0402_1%

DDRA_MA12 RD70 DDRA_MA13 RD71 DDRA_MA14_WE#RD72 DDRA_MA15_CAS#RD73

1 1 1 1

2 2 2 2

34.8_0402_1% 34.8_0402_1% 34.8_0402_1% 34.8_0402_1%

DDRA_MA16_RAS#RD74 DDRA_BG0 RD75 DDRA_BS0# RD76 DDRA_BS1# RD77

1 1 1 1

2 2 2 2

34.8_0402_1% 34.8_0402_1% 34.8_0402_1% 34.8_0402_1%

DDRA_ACT# DDRA_PAR

1 1

2 2

34.8_0402_1% 34.8_0402_1%

D

RD78 RD79

1

RD86

2 49.9_0402_1%

PAR

VREFCA

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 NC

CD@

2

M1

2

10U_0603_6.3V6M

1

CD146

2

10U_0603_6.3V6M

1

CD145

2

10U_0603_6.3V6M

1

CD144

CD143

2

1

2

CD109 22P_0402_50V8-J RF@

1

2

CD110 22P_0402_50V8-J RF@

B

CD@

(1OuF_0603_6.3V) *3 Place around the DRAMs

+2.5V_DDR

+VREF_CA_MD

1

2

1

2

1

2

CD@

1

2

1

2

+2.5V_DDR

1

2

1

2

1

2

CD157 22P_0402_50V8-J RF@

1

2

CD148 22P_0402_50V8-J RF@

T7 +0.6VS

(1uF_0402_6.3V) *8 Place 2 near each DRAM

(1OuF_0603_6.3V) *2 Place around the DRAMs

+0.6VS

ZQ

RD44 MT40A512M16HA083EA_FBGA96 240_0402_1% 2

2

1

CD158

2

1

2

Issued Date

1

2

CD@

1

2

1

2

1

2

CD@

1

2

1

2

1

2

CD@

1

2

1

2

Deciphered Date

CD168 22P_0402_50V8-J RF@

2

2

CD169 22P_0402_50V8-J RF@

A

DDR4 Memory Down

2016/08/20

Size Document Number Custom

Date: 3

1

Title

LC Future Center Secret Data 2015/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 4

2

+2.5V_DDR

B1 R9

E1 K1 N1 T1 B2 G8 E9 K9 M9

1

Security Classification

5

1

1U_0402_6.3V6K

1

1U_0402_6.3V6K

2

CD141

1

1U_0402_6.3V6K

1U_0402_6.3V6K

2

CD140

CD@

1

CD139

2

CD138

1

1U_0402_6.3V6K

1U_0402_6.3V6K

2

CD137

1U_0402_6.3V6K

1

CD136

1U_0402_6.3V6K

CD134

2 CD135

1U_0402_6.3V6K

1U_0402_6.3V6K

CD133

1U_0402_6.3V6K

CD132

1U_0402_6.3V6K

CD130

CD131

1U_0402_6.3V6K

1U_0402_6.3V6K

CD129

1U_0402_6.3V6K

CD127

CD126

A1 C1 G1 F2 J2 F8 J8 A9 D9 G9

10U_0603_6.3V6M

CD142

2

1

RD43 MT40A512M16HA083EA_FBGA96 240_0402_1% A

1

10U_0603_6.3V6M

F9

VPP1 VPP2

1

10U_0603_6.3V6M

ZQ

ODT

RESET_N

2

CD167

2

P1 F1 H1 A2 D2 E3 A8 D8 E8 C9 H9

1

CD166

1

2

1U_0402_6.3V6K

CPU_DRAMRST# @

BG0

TEN

1

+1.2V

CD165

N9

2

1U_0402_6.3V6K

2 10K_0402_5% TEN_UD4

CD@

T7

T3

1

CD@

CD164

2

K3

DDRA_PAR

2

1U_0402_6.3V6K

2

DDRA_ODT0

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10

D1 J1 L1 R1 B3 G7 B9 J9 L9 T9

1U_0402_6.3V6K

2

RD97 1

M2

1

CD163

NC

2

1

DDRA_BG0

ACT_N CS_N ALERT_N

2

10U_0603_6.3V6M

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10

1

1

L3 L7 P9

BA0 BA1

1

+1.2V VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10

1U_0402_6.3V6K

RESET_N

E1 K1 N1 T1 B2 G8 E9 K9 M9

1

DDRA_ACT# DDRA_CS0# DDRA_ALERT#

NF/UDM_N/UDBI_N NF/LDM_N/LDBI_N

2

CD147

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

+VREF_CA_MD

N2 N8

1

F9

TEN

M1

DDRA_BS0# DDRA_BS1#

1

CD162

2

F1 H1 A2 D2 E3 A8 D8 E8 C9 H9

VREFCA

E2 E7

2

1U_0402_6.3V6K

CD107

1

P1

VPP1 VPP2

PAR

DDRA_DM6 DDRA_DM7

LDQS_C LDQS_T UDQS_C UDQS_T

1

(1OuF_0603_6.3V) *5 Place around the DRAMs

CD156

N9

ODT

B1 R9

F3 G3 A7 B7

+1.2V

CD159

T3

BG0

+2.5V_DDR

DDRA_DQS#7 DDRA_DQS7 DDRA_DQS#6 DDRA_DQS6

CKE

2

10U_0603_6.3V6M

K3

DDRA_PAR

ACT_N CS_N ALERT_N

K2

CK_C CK_T

1

CD@

CD152

DDRA_ODT0

0.1u_0201_10V6K

@

2 2

1

(1uF_0402_6.3V) *16 Place 4 near each DRAM

1U_0402_6.3V6K

M2

2 0_0402_5% 2 0_0402_5%

DDRA_CKE0

WE_N/A14 CAS_N/A15 RAS_N/A16

2

1U_0402_6.3V6K

DDRA_BG0

@ @

K8 K7

DDRA_DQ59 DDRA_DQ60 DDRA_DQ62 DDRA_DQ56 DDRA_DQ63 DDRA_DQ61 DDRA_DQ58 DDRA_DQ57 DDRA_DQ54 DDRA_DQ52 DDRA_DQ51 DDRA_DQ49 DDRA_DQ50 DDRA_DQ53 DDRA_DQ55 DDRA_DQ48

1U_0402_6.3V6K

L3 L7 P9

RD89 1 RD90 1

DDRA_CLK0# DDRA_CLK0

G2 F7 H3 H7 H2 H8 J3 J7 A3 B8 C3 C7 C2 C8 D3 D7

CD155

DDRA_ACT# DDRA_CS0# DDRA_ALERT#

BA0 BA1

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10

A1 C1 G1 F2 J2 F8 J8 A9 D9 G9

L2 M8 L8

1

@ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

CD154

N2 N8

NF/UDM_N/UDBI_N NF/LDM_N/LDBI_N

+1.2V

DDRA_MA14_WE# DDRA_MA15_CAS# DDRA_MA16_RAS#

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC_N A13

0.1u_0201_10V6K

DDRA_BS0# DDRA_BS1#

LDQS_C LDQS_T UDQS_C UDQS_T

P3 P7 R3 N7 N3 P8 P2 R8 R2 R7 M3 T2 M7 T8

.047U_0201_6.3V6K

E2 E7

CPU_DRAMRST#

1 1

RD53

C

CD153

DDRA_DM4 DDRA_DM5

2 10K_0402_5% TEN_UD3

RD51 RD52

DDRA_CKE0

DDRA_ALERT#

CD116

F3 G3 A7 B7

CKE

D1 J1 L1 R1 B3 G7 B9 J9 L9 T9

DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11 DDRA_MA12 DDRA_MA13

0.1u_0201_10V6K

K2

CK_C CK_T

+1.2V VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10

CD108

DDRA_CKE0

WE_N/A14 CAS_N/A15 RAS_N/A16

1U_0402_6.3V6K

K8 K7

CD151

DDRA_CLK0# DDRA_CLK0

DDRA_DQ43 DDRA_DQ44 DDRA_DQ46 DDRA_DQ40 DDRA_DQ47 DDRA_DQ45 DDRA_DQ42 DDRA_DQ41 DDRA_DQ34 DDRA_DQ37 DDRA_DQ39 DDRA_DQ32 DDRA_DQ35 DDRA_DQ33 DDRA_DQ38 DDRA_DQ36

1U_0402_6.3V6K

L2 M8 L8

G2 F7 H3 H7 H2 H8 J3 J7 A3 B8 C3 C7 C2 C8 D3 D7

CD150

2 0_0402_5% 2 0_0402_5%

DDRA_CS0# DDRA_ODT0

T7

@ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

0.1u_0201_10V6K

DDRA_MA14_WE# DDRA_MA15_CAS# DDRA_MA16_RAS#

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC_N A13

CD149

P3 P7 R3 N7 N3 P8 P2 R8 R2 R7 M3 T2 M7 T8

.047U_0201_6.3V6K

DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11 DDRA_MA12 DDRA_MA13

CD115

RD96 1

@ @

36_0402_1% 36_0402_1%

ZQ

UD4

RD87 1 RD88 1

2 2

2 UD3

+1.2V

1 1

+1.2V

+1.2V

DDRA_DQS#5 DDRA_DQS5 DDRA_DQS#4 DDRA_DQS4

RD49 RD50

RD40 MT40A512M16HA083EA_FBGA96 240_0402_1%

2

RD39 MT40A512M16HA083EA_FBGA96 240_0402_1%

B

1 2 1 2

1 +2.5V_DDR

B1 R9

DDRA_CLK0# DDRA_CLK0

1

ZQ

BG0

2

M2

1

F9

RESET_N

DDRA_BG0

CD161

C

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

B1 R9

ACT_N CS_N ALERT_N

1U_0402_6.3V6K

2

P1

TEN

L3 L7 P9

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10

BA0 BA1

A1 C1 G1 F2 J2 F8 J8 A9 D9 G9

CD128

CD47

1

0.1u_0201_10V6K

@

VREFCA

DDRA_ACT# DDRA_CS0# DDRA_ALERT# +2.5V_DDR

NF/UDM_N/UDBI_N NF/LDM_N/LDBI_N

2

CD112 0.1u_0201_10V6K

RD48 24.9_0402_1%

10U_0603_6.3V6M

CPU_DRAMRST#

6,18 CPU_DRAMRST#

PAR

N2 N8

2

10U_0603_6.3V6M

2 10K_0402_5% TEN_UD1

RD94 1

ODT

VPP1 VPP2

DDRA_BS0# DDRA_BS1#

1

RD47 1.8K_0402_1%

1U_0402_6.3V6K

5 DDRA_PAR

BG0

E2 E7

LDQS_C LDQS_T UDQS_C UDQS_T

5 +0.6VS

+VREF_CA_MD

CD160

5 DDRA_ODT0

M2

DDRA_DM3 DDRA_DM2

CKE

D1 J1 L1 R1 B3 G7 B9 J9 L9 T9

5 5

DDRA_MA[0..13]

1U_0402_6.3V6K

DDRA_BG0

5 DDRA_BG0

ACT_N CS_N ALERT_N

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10

2 0_0402_5% 2 0_0402_5%

CD111 0.022U_0201_6.3V6-K

1U_0402_6.3V6K

L3 L7 P9

BA0 BA1

@ @

F3 G3 A7 B7

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10

2

1

+1.2V

CK_C CK_T

DDRA_DQS[0..7]

RD45 1.8K_0402_1%

2 RD46 1 2.7_0402_1%

5 DDR_SA_VREFCA

CD125

DDRA_ACT# DDRA_CS0# DDRA_ALERT#

NF/UDM_N/UDBI_N NF/LDM_N/LDBI_N

RD66 1 RD69 1

DDRA_DQS#2 DDRA_DQS2 DDRA_DQS#3 DDRA_DQS3

1 CD119 0.1u_0201_10V6K

5

DDRA_DQS#[0..7]

DDRA_DQS[0..7] DDRA_MA[0..13]

CD124

N2 N8

A1 C1 G1 F2 J2 F8 J8 A9 D9 G9

K2

WE_N/A14 CAS_N/A15 RAS_N/A16

+1.2V

DDRA_DQ18 DDRA_DQ19 DDRA_DQ16 DDRA_DQ21 DDRA_DQ22 DDRA_DQ17 DDRA_DQ23 DDRA_DQ20 DDRA_DQ30 DDRA_DQ28 DDRA_DQ26 DDRA_DQ25 DDRA_DQ31 DDRA_DQ29 DDRA_DQ27 DDRA_DQ24

0.1u_0201_10V6K

DDRA_BS0# DDRA_BS1#

+1.2V

K8 K7

DDRA_CKE0

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

G2 F7 H3 H7 H2 H8 J3 J7 A3 B8 C3 C7 C2 C8 D3 D7

.047U_0201_6.3V6K

E2 E7

LDQS_C LDQS_T UDQS_C UDQS_T

DDRA_CLK0# DDRA_CLK0

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC_N A13

DDRA_DQ[0..63]

DDRA_DQS#[0..7]

@

CD122

5 DDRA_ACT# 5 DDRA_CS0# 5 DDRA_ALERT#

DDRA_DM1 DDRA_DM0

CKE

CD48

5 DDRA_BS0# 5 DDRA_BS1#

F3 G3 A7 B7

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10

L2 M8 L8

0.1u_0201_10V6K

2 0_0402_5% 2 0_0402_5%

DDRA_DQS#0 DDRA_DQS0 DDRA_DQS#1 DDRA_DQS1

CK_C CK_T

1U_0402_6.3V6K

@ @

K2

1U_0402_6.3V6K

RD65 1 RD68 1

K8 K7

DDRA_CKE0

D1 J1 L1 R1 B3 G7 B9 J9 L9 T9

CD123

+1.2V

DDRA_CLK0# DDRA_CLK0

P3 P7 R3 N7 N3 P8 P2 R8 R2 R7 M3 T2 M7 T8

DDRA_MA14_WE# DDRA_MA15_CAS# DDRA_MA16_RAS#

+1.2V

CD121

5 DDRA_CKE0

WE_N/A14 CAS_N/A15 RAS_N/A16

DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11 DDRA_MA12 DDRA_MA13

0.1u_0201_10V6K

5 DDRA_CLK0# 5 DDRA_CLK0

L2 M8 L8

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DDRA_DQ2 DDRA_DQ3 DDRA_DQ7 DDRA_DQ1 DDRA_DQ4 DDRA_DQ0 DDRA_DQ6 DDRA_DQ5 DDRA_DQ11 DDRA_DQ8 DDRA_DQ14 DDRA_DQ13 DDRA_DQ15 DDRA_DQ12 DDRA_DQ10 DDRA_DQ9

.047U_0201_6.3V6K

DDRA_MA14_WE# DDRA_MA15_CAS# DDRA_MA16_RAS#

5 DDRA_MA14_WE# 5 DDRA_MA15_CAS# 5 DDRA_MA16_RAS#

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC_N A13

G2 F7 H3 H7 H2 H8 J3 J7 A3 B8 C3 C7 C2 C8 D3 D7

CD120

D

P3 P7 R3 N7 N3 P8 P2 R8 R2 R7 M3 T2 M7 T8

UD2

CD113

DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11 DDRA_MA12 DDRA_MA13

@

CD114

UD1

Re v 1.0

CG411

Thursday, January 14, 2016 1

Sheet

17

of

60

5

4

3

2

1

+1.2V DDRB_DQ[0..63]

DDRB_DQ[0..63]

DDRB_DQS#[0..7] +1.2V

+1.2V

+1.2V

+1.2V

DDRB_DQS[0..7]

DDRB_DQS[0..7]

6

+1.2V

+1.2V

+1.2V

RD91 240_0402_1% @

+1.2V

JDDR1B

6

2

JDDR1A

6

DDRB_DQS#[0..7]

1

DDR4 SO-DIMM

DDRB_DQ10 D

DDRB_DQ14 DDRB_DQ0 DDRB_DQ6

DDRB_DQ7 DDRB_DQ3 DDRB_DQ18 DDRB_DQ16 DDRB_DQS#2 DDRB_DQS2 DDRB_DQ22 DDRB_DQ23 DDRB_DQ27 DDRB_DQ28 +1.2V

DDRB_DQ30

1

1

DDRB_DQ25

2

RD93 240_0402_1%

2

RD92 240_0402_1%

DDRB_DQS#8 DDRB_DQS8

C

6 DDRB_CKE0 6 DDRB_BG1 6 DDRB_BG0 6 DDRB_MA12 6 DDRB_MA9 6 DDRB_MA8 6 DDRB_MA6

DDRB_CKE0 DDRB_BG1 DDRB_BG0 DDRB_MA12 DDRB_MA9 DDRB_MA8 DDRB_MA6

DDRB_DQ8

DDRB_CLK0 DDRB_CLK0#

6 DDRB_CLK0 6 DDRB_CLK0#

DDRB_PAR

6 DDRB_PAR

DDRB_DQ11 DDRB_DQ15

DDRB_BS1#

6 DDRB_BS1#

DDRB_DQ5 DDRB_DQ4

6 DDRB_CS0# 6 DDRB_MA14_WE#

DDRB_DQS#0 DDRB_DQS0

6 DDRB_ODT0 6 DDRB_CS1#

145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231 233 235 237 239 241 243 245 247 249 251 253 255 257 259

DDRB_CS0# DDRB_MA14_WE# DDRB_ODT0 DDRB_CS1# DDRB_ODT1

6 DDRB_ODT1

DDRB_DQ1

131 133 135 137 139 141 143

DDRB_DQ2 DDRB_DQ32 DDRB_DQ20 DDRB_DQ33 DDRB_DQ21 DDRB_DQS#4 DDRB_DQS4 DDRB_DQ17

DDRB_DQ39

DDRB_DQ19

DDRB_DQ38

DDRB_DQ24

DDRB_DQ41

DDRB_DQ29

DDRB_DQ40

DDRB_DQS#3 DDRB_DQS3 DDRB_DQ47 DDRB_DQ26 DDRB_DQ43 DDRB_DQ31 DDRB_DQ53 DDRB_DQ48 DDRB_DQS#6 DDRB_DQS6 DDRB_DQ54 DDRB_DQ50 CPU_DRAMRST# DDRB_CKE1 DDRB_ACT# DDRB_ALERT# DDRB_MA11 DDRB_MA7 DDRB_MA5 DDRB_MA4

CPU_DRAMRST# DDRB_CKE1

6

1

DDRB_ACT# 6 DDRB_ALERT# 6 DDRB_MA11 6 DDRB_MA7 6

2

DDRB_DQ60

6,17

DDRB_DQ57 CD3 0.1u_0201_10V6K @ DDRB_DQ59 DDRB_DQ58

DDRB_MA5 6 DDRB_MA4 6 +3VS

RD1

ARGOS_D4AS0-26001-1P60 ME@

CD4 2.2U_0402_6.3V6M

+2.5V_DDR

RD2

SMB_CLK_S3 +VDD_SPD

7,40 SMB_CLK_S3 1 2 @ 0_0603_5% 1 1

2

2

261

CD5 0.1u_0201_10V6K

A3 A1 VDD_9 CK0_t CK0_c VDD_11 Parity

A2 EVENT_n VDD_10 CK1_t CK1_c VDD_12 A0

BA1 A10/AP VDD_13 VDD_14 CS0_n BA0 WE_n/A14 RAS_n/A16 VDD_15 VDD_16 ODT0 CAS_n/A15 CS1_n A13 VDD_17 VDD_18 ODT1 C0/CS2_n/NC VDD_19 VREFCA C1/CS3_n/NC SA2 VSS_53 VSS_54 DQ37 DQ36 VSS_55 VSS_56 DQ33 DQ32 VSS_57 VSS_58 DQS4_c DM4_n/DBl4_n/NC DQS4_t VSS_59 VSS_60 DQ39 DQ38 VSS_61 VSS_62 DQ35 DQ34 VSS_63 VSS_64 DQ45 DQ44 VSS_65 VSS_66 DQ41 DQ40 VSS_67 VSS_68 DQS5_c DM5_n/DBl5_n/NC DQS5_t VSS_69 VSS_70 DQ46 DQ47 VSS_71 VSS_72 DQ42 DQ43 VSS_73 VSS_74 DQ52 DQ53 VSS_75 VSS_76 DQ49 DQ48 VSS_77 VSS_78 DQS6_c DM6_n/DBl6_n/NC DQS6_t VSS_79 VSS_80 DQ54 DQ55 VSS_81 VSS_82 DQ50 DQ51 VSS_83 VSS_84 DQ60 DQ61 VSS_85 VSS_86 DQ57 DQ56 VSS_87 VSS_88 DQS7_c DM7_n/DBl7_n/NC DQS7_t VSS_89 VSS_90 DQ62 DQ63 VSS_91 VSS_92 DQ58 DQ59 VSS_93 VSS_94 SCL SDA VDDSPD SA0 VPP_1 Vtt VPP_2 SA1 GND_1

GND_2

132 134 136 138 140 142 144

DDRB_MA2 DDRB_EVENT#

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260

DDRB_MA10

DDRB_MA2 6

DDRB_CLK1 DDRB_CLK1#

DDRB_CLK1 6 DDRB_CLK1# 6

DDRB_MA0

DDRB_MA0 6 D

DDRB_MA10 6

DDRB_BS0# DDRB_MA16_RAS#

DDRB_BS0# 6 DDRB_MA16_RAS#

DDRB_MA15_CAS# DDRB_MA13

DDRB_MA15_CAS# DDRB_MA13 6

6 6

+VREF_CA_DIMM DDRB_SA2 DDRB_DQ36

1

DDRB_DQ37

2 DDRB_DQ34

@

1

2 CD2

DDRB_DQS#1 DDRB_DQS1

DDRB_MA3 DDRB_MA1

6 DDRB_MA3 6 DDRB_MA1

DDRB_DQ9

2.2U_0402_6.3V6M

DDRB_DQ13

VSS_1 VSS_2 DQ5 DQ4 VSS_3 VSS_4 DQ1 DQ0 VSS_5 VSS_6 DQS0_C DM0_n/DBIO_n/NC DQS0_t VSS_7 VSS_8 DQ6 DQ7 VSS_9 VSS_10 DQ2 DQ3 VSS_11 VSS_12 DQ12 DQ13 VSS_13 VSS_14 DQ8 DQ9 VSS_15 VSS_16 DQS1_c DM1_n/DBl1_n/NC DQS1_t VSS_17 VSS_18 DQ15 DQ14 VSS_19 VSS_20 DQ10 DQ11 VSS_21 VSS_22 DQ21 DQ20 VSS_23 VSS_24 DQ17 DQ16 VSS_25 VSS_26 DQS2_c DM2_n/DBl2_n/NC DQS2_t VSS_27 VSS_28 DQ22 DQ23 VSS_29 VSS_30 DQ18 DQ19 VSS_31 VSS_32 DQ28 DQ29 VSS_33 VSS_34 DQ24 DQ25 VSS_35 VSS_36 DQS3_c DM3_n/DBl3_n/NC DQS3_t VSS_37 VSS_38 DQ30 DQ31 VSS_39 VSS_40 DQ26 DQ27 VSS_41 VSS_42 CB5/NC CB4/NC VSS_43 VSS_44 CB1/NC CB0/NC VSS_45 VSS_46 DQS8_c DM8_n/DBI8_n/NC DQS8_t VSS_47 VSS_48 CB6/NC CB2/NC VSS_49 VSS_50 CB7/NC CB3/NC VSS_51 VSS_52 RESET_n CKE0 CKE1 VDD_1 VDD_2 BG1 ACT_n BG0 ALERT_n VDD_3 VDD_4 A12 A11 A9 A7 VDD_5 VDD_6 A8 A5 A6 A4 VDD_7 VDD_8

0.1u_0201_10V6K

DDRB_DQ12

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130

CD1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129

DDRB_DQ35 DDRB_DQ45 DDRB_DQ44 DDRB_DQS#5 DDRB_DQS5 DDRB_DQ46 DDRB_DQ42 DDRB_DQ52 DDRB_DQ49

DDRB_DQ55 C

DDRB_DQ51 DDRB_DQ56 DDRB_DQ61 DDRB_DQS#7 DDRB_DQS7 DDRB_DQ62 DDRB_DQ63 SMB_DATA_S3 DDRB_SA0

SMB_DATA_S3 7,40 +0.6VS

DDRB_SA1

262

ARGOS_D4AS0-26001-1P60 ME@

1 2 @ 0_0603_5%

+VPP

+1.2V

1

Note: VREF trace width:20 mils at least Spacing:20mils to other signal/planes Place near DIMM scoket

+0.6VS

Layout Note: Place near DIMM

2

CD@

2

1U_0402_6.3V6K

2

1

CD12

CD@

2

1U_0402_6.3V6K

2

1

CD11

2

10U_0603_6.3V6M

2

1

CD10

2

10U_0603_6.3V6M

CD14 0.1u_0201_10V6K

CD9

CD6

RD5 1K_0402_1%

10U_0603_6.3V6M

2

1

1

CD13 0.022U_0201_6.3V6-K

1

B

2

1

2

1

CD8

1

1

10U_0603_6.3V6M

+VREF_CA_DIMM

1 2 2_0402_5%

1

CD7

RD4

1

1U_0402_6.3V6K

@

B

5 DDR_SB_VREFCA

+2.5V_DDR

CD118

RD3 1K_0402_1%

1U_0402_6.3V6K

1 2

2

CD117 0.1u_0201_10V6K

RD6 24.9_0402_1%

2

+1.2V

+3VS

+

2

220U_6.3V_M

1U_0402_6.3V6K

2

1

CD35

CD@

1

CD34

2

1U_0402_6.3V6K

1

CD33

2

1U_0402_6.3V6K

2

1

CD32

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

CD31

CD@

1

CD30

2

1U_0402_6.3V6K

1

CD29

2

1U_0402_6.3V6K

1

CD28

2

1U_0402_6.3V6K

1

CD27

2

10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

CD26

CD@

1

CD25

2

10U_0603_6.3V6M

1

CD24

2

10U_0603_6.3V6M

1

CD23

2

10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

CD22

10U_0603_6.3V6M

2

1

CD21

CD@

+3VS

1

CD20

CD19

2

10U_0603_6.3V6M

@

1

+3VS

For EMC

WWW.AliSaler.Com 5

33P_0402_50V8J

RF@

2

A

Near JDDRL1

Issued Date

Title

LC Future Center Secret Data

Security Classification

SPD Address = 2H

1

CD37

2

33P_0402_50V8J

RF@

1

CD36

0.1u_0201_10V6K

EMC_NS@

1

2 CD18

EMC_NS@

2

0.1u_0201_10V6K

EMC_NS@

2

1

CD17

CD15

RD12 0_0402_5% @

2

RD11 0_0402_5% @

2

2

RD10 0_0402_5% @

1

1

1

2

1

4.7U_0402_6.3V6M

EMC_NS@

1

DDRB_SA2

CD16

DDRB_SA1

A

4.7U_0402_6.3V6M

DDRB_SA0

RD9 0_0402_5% @

2

RD8 0_0402_5% @

2

2

RD7 0_0402_5% @

1

1

1

+1.2V

2015/08/20

DDR4 SO-DIMM

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet 1

18

of

60

5

4

3

2

1

N15x GPIO GPIO

I/O

ACTIVE

GPIO0

OUT

-

GPIO1

OUT

N/A

Performance Mode P0 TDP at Tj = 102 C* (DDR3)

Function Description

(4)

Mem (1,5)

NVCLK /MCLK

(W)

(W)

(MHz)

GPU

D

FB Enable for GC6 2.0 Products

OUT

N/A

GPIO3

OUT

N/A

GPIO4

OUT

N/A

GPIO5

OUT

N/A

GPU power sequencing---3V3_MAIN_EN

GPIO6

IN

-

GPU wake signal for GC6 2.0

GPIO7

OUT

N/A

GPIO8

I/O

-

System side PCIe reset Monitor

GPIO9

I/O

N/A

2.2K Pull-up

GPIO10

OUT

N/A

GPIO11

OUT

-

GPIO12

IN

GPIO13

OUT

-

GPIO14

IN

N/A

GPIO15

IN

N/A

2GB DDR3

AC Power Detect Input

IN

N/A

GPIO19

IN

N/A

TBD

Physical Strapping pin ROM_SCLK

Phase Shedding

N/A

GPIO20

(W)

(A)

(A)

(W)

I/O and PLLVDD (1.05V)

(mA)

(mA)

(W)

(W)

Other (3.3V) (mA)

(W)

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

(10K pull High)

N/A

GPIO18

(W)

PCI Express (1.05V) (6)

GPU Core VDD PWM control signal

N/A IN

(A)

FBVDDQ

(GPU+Mem) (1.35V)

N15x Multi-level Straps

C

GPIO17

(V)

(1.35V)

D

N14X 128bit

GPIO2

GPIO16

FBVDD

NVVDD

Power Rail

Logical Strapping Bit3

Logical Strapping Bit2

Logical Strapping Bit1

Logical Strapping Bit0

+3VGS

SOR3_EXPOSED

SOR2_EXPOSED

SOR1_EXPOSED

SOR0_EXPOSED

ROM_SI

+3VGS

RAM_CFG[3]

RAM_CFG[2]

RAM_CFG[1]

RAM_CFG[0]

ROM_SO

+3VGS

DEVID_SEL

PCIE_CFG

SMB_ALT_ADDR

VGA_DEVICE

STRAP0

+3VGS

STRAP1

+3VGS

STRAP2

+3VGS

STRAP3

+3VGS

STRAP4

+3VGS

C

Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)

Reserved(keep pull-up and pull-down footprint and not stuff by default)

SMBUS_ALT_ADDR

GPIO21

OUT

GPU PCIe self-reset control

0

0x9E (Default)

OVERT

OUT

Active Low Thermal Catastrophic Over Temperature

1

0x9C (Multi-GPU usage)

N15V-GM Power Sequence N15x Binary Straps

B

+3VG_AON

Other Power rail

+VGA_CORE

+3VG_AON

Physical Strapping pin ROM_SCLK

tNVVDD >0

+1.35VGS

Tpower-off 0

+1.05VS_VGA tPEX_VDD >0

1.all GPU power rails should be turned off within 10ms 2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

1. all power rail ramp up time should be larger than 40us

Power Rail

B

Strap Mapping

+3VGS

SMB_ALT_ADDR

ROM_SI

+3VGS

SUB_VENDOR

ROM_SO

+3VGS

VGA_DEVICE

STRAP0

+3VGS

RAM_CFG[0]

STRAP1

+3VGS

RAM_CFG[1]

STRAP2

+3VGS

RAM_CFG[2]

STRAP3

+3VGS

RAM_CFG[3]

STRAP4

+3VGS

PCIE_MAX_SPEED

N15S-GT Power Sequence +3VG_AON +VGA_CORE A

A

tNVVDD >0

+1.05VS_VGA +1.35VGS tPEX_VDD >0

Issued Date

1. all power rail ramp up time should be larger than 40us

Title

LC Future Center Secret Data

Security Classification

2015/08/20

Deciphered Date

VGA Notes List

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size C

Date: 5

4

3

2

Document Number

Rev 1.0

CG411 Thursday, January 14, 2016 1

Sheet

19

of

60

5

4

3

2

1

+3VG_AON 9 PCIE_CRX_GTX_N[0..3] 2

9 PCIE_CRX_GTX_P[0..3]

RV41 10K_0402_5% @

9 PCIE_CTX_C_GRX_N[0..3] 9 PCIE_CTX_C_GRX_P[0..3]

1

+3VG_AON

2

1 UV1A

2 OPT@

1 0_0402_5%

PU AT EC SIDE, +3VS AND 4.7K

+3VG_AON RV12 1

+3VGARST 1 UV2 PLT_RST#

1 2

8 PXS_RST#

3

A

CV10 CV13 CV8 CV9 CV6 CV7 CV4 CV5

1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2

0.22U_0201_6.3V6-K 0.22U_0201_6.3V6-K 0.22U_0201_6.3V6-K 0.22U_0201_6.3V6-K 0.22U_0201_6.3V6-K 0.22U_0201_6.3V6-K 0.22U_0201_6.3V6-K 0.22U_0201_6.3V6-K

PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0 PCIE_CRX_C_GTX_P1 PCIE_CRX_C_GTX_N1 PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2 PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3

CV11 0.1u_0201_10V6K OPT@

5

VCC

B SYS_PEX_RST_MON#

4

74LVC1G08SE-7_SOT353-5 OPT@ RV14

2 OPT@

1 10K_0402_5%

RV16

1

2 0_0402_5%

@

2 RV37 10K_0402_5% @

B

1 2 RV32 @ 200_0402_1%

DV6 GPU_PEX_RST_HOLD#

2

SYS_PEX_RST_MON#

3

RV35 PLT_RST_VGA#

1

PEX_TSTCLK_OUT PEX_TSTCLK_OUT#

AE8 AD8 AC6 AF22 AE22

Differential signal

1

1

RV180 2.2K_0402_5% GC6@

CLK_PCIE_GPU CLK_PCIE_GPU# CLK_REQ_GPU#

1 OPT@ 2 2.49K_0402_1%

PLT_RST_VGA# PEX_TERMP

AC7 AF25

1 NGC6@ 2

1 RV6

1

@

2

2 0_0402_5%

RV49 2 GC6@

1

RB751V-40_SOD323-2 2 1 DV1 @

58

VGA_AC_DET

1 0_0402_5%

44

PSI_VGA 58

+3VG_AON

+3VG_AON

GPU_PEX_RST_HOLD# 1

RV13 10K_0402_5% @

AG3 AF4 AF3

3

GPU_EVENT#

1

AE3 AE4

PLT_RST_VGA#

I2CA_SCL I2CA_SDA I2CB_SCL I2CB_SDA I2CC_SCL I2CC_SDA I2CS_SCL I2CS_SDA

1 GC6@

2 0_0402_5%

B7 A7

VGA_CRT_CLK VGA_CRT_DATA

C9 C8

I2CB_SCL I2CB_SDA

A9 B9

I2CC_SCL I2CC_SDA

D9 D8

VGA_SMB_CK2 VGA_SMB_DA2

RV174

1 2 @ 1K_0402_5%

1

2

I2C,if not use, can be soft grounded and delete pull up resistor ---colin

3

OVERT#

1

2

Internal Thermal Sensor

L6 M6 N6

+PLLVDD +3VG_AON

45mA

RV24 1

@

2 0_0402_5%

PEX_TSTCLK PEX_TSTCLK_N PEX_RST_N PEX_TERMP

XTAL_IN XTAL_OUT XTAL_SSIN XTAL_OUTBUFF

45mA

C11 XTAL_IN B10 XTAL_OUT A10 XTALSSIN C10 XTALOUT

1 OPT@ 1 OPT@

+3VG_AON

+SP_PLLVDD

PEX_REFCLK PEX_REFCLK_N PEX_CLKREQ_N

2 RV34 10K_0402_5% 2 RV36 10K_0402_5%

VGA_CRT_DATA RV17 1

@

2 2.2K_0402_5%

3VGS_PWR_EN

RV18 2 OPT@

1 10K_0402_5%

VGA_CRT_CLK

RV19 1

@

2 2.2K_0402_5%

OVERT#

RV20 1 OPT@

2 10K_0402_5%

I2CB_SCL

RV22 1

@

2 2.2K_0402_5%

VGA_ALERT#

RV23 1 OPT@

2 10K_0402_5%

I2CB_SDA

RV25 1

@

2 2.2K_0402_5%

VGA_AC_DET_R

RV26 1 OPT@

2 100K_0402_5%

I2CC_SCL

RV28 1

@

2 2.2K_0402_5%

PSI_VGA

RV29 1 OPT@

2 10K_0402_5%

I2CC_SDA

RV30 1

@

2 2.2K_0402_5%

GPU_PEX_RST_HOLD# RV31 1 OPT@

2 10K_0402_5%

XTALOUT

RV33 1

@

2 10K_0402_5%

1

CV19 10P_0201_25V8G OPT@

+3VG_AON 1

1

180ohms

OSC2

27MHZ_10PF_7V27000050 OPT@

2

XTAL_OUT 1

2

CV20 10P_0201_25V8G OPT@

Under GPU

2

OPT@

OPT@

30ohms

OPT@

(ESR=0.05) 1 2 @ 0_0603_5%

1

2

Bead LV1

+1.05VGS

Bead LV2

+1.05VGS

22U_0603_6.3V6-M

CV21

2

2

S

A

RV46 10K_0402_5% @ 1

D

CLK_REQ_GPU#

3

1 OPT@ 2 0_0402_5%

2

1

Near GPU

CV22

OPT@

1

1

0.1u_0201_10V6K

2 2

A

RV48

2

1 2 @ 0_0603_5%

+PLLVDD RV44 10K_0402_5% @

G

2

CV18

4 3

(ESR=0.2)

22U_0603_6.3V6-M

GND1

GND2

1

4.7U_0402_6.3V6M

OSC1

1

CV17

2

RV40 10K_0402_5% @

CV15

2

1

OPT@

1

CV16

150mA

0.1u_0201_10V6K

10M_0402_5%

OPT@

2

0.1u_0201_10V6K

1 OPT@ YV1

XTAL_IN

QV5 2N7002KW_SOT323-3 @

B

0_0402_5%

+3VG_AON

1

WRST# 44

QV23 2N7002KW_SOT323-3 @

1

CV221 0.01U_0201_10V6K @

CV218 0.1u_0201_10V6K @

60mA CORE_PLLVDD SP_PLLVDD

RV38

10 GPU_CLKREQ#

8

W5 AE2 AF2

Under GPU(below 150mils)

2

GPU_EVENT#

QV4 2N7002KW_SOT323-3 @

+SP_PLLVDD

CV23 0.1u_0201_10V6K @

CV12 0.1u_0201_10V6K @

2

GPU_EVENT#_R

N15S-GT-S-A2_FCBGA595 @

BAT54AW_SOT323-3 GC6@ RV39

NVVDD_PWM_VID

8

C

VID_PLLVDD 10 CLK_PCIE_GPU 10 CLK_PCIE_GPU#

NVVDD_PWM_VID VGA_AC_DET_R PSI_VGA_R

RV15 NC102 NC103 NC104

+3VG_AON

2

+3VGS

NC100 NC101

RV47 10K_0402_5% @

SYS_PEX_RST_MON# VGA_ALERT#

FB_GC6_EN_R

QV6 2N7002KW_SOT323-3 @

D

Y

PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N NC89 NC90 NC91 NC92 NC93 NC94 NC95 NC96 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 NC29 NC30 NC31 NC32

22,58

S

GND

AC9 AB9 AB10 AC10 AD11 AC11 AC12 AB12 AB13 AC13 AD14 AC14 AC15 AB15 AB16 AC16 AD17 AC17 AC18 AB18 AB19 AC19 AD20 AC20 AC21 AB21 AD23 AE23 AF24 AE24 AG24 AG25

3VGS_PWR_EN

G

11,32,37,40,44

PLT_RST#

2

2 @ 0_0402_5%

OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@

OVERT#

3VGS_PWR_EN GPU_EVENT#_R

FB_GC6_EN_R

1

D

2 1 @ 0_0402_5%

RV10 C

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3

NC97 NC98 NC99

A6 AB6

3

S

+3VS

OVERT NC33

D

FB_GC6_EN

G

RV9

7,39,44

24

2

D

EC_SMB_DA2

FB_GC6_EN

2

S

1

FB_GC6_EN

2

G

VGA_SMB_DA2

QV1A 2N7002KDWH_SOT363-6 @ 6

C6 B2 D6 C7 F9 A3 A4 B6 E9 F8 C5 E7 D7 B4 B3 C3 D5 D4 C2 F7 E6 C4

1

2

1 0_0402_5%

GPIO

2 OPT@

RV7

7,39,44

DACs

D

EC_SMB_CK2

CLK

S

4

I2C

5

VGA_SMB_CK2

PCI EXPRESS

2

2

QV1B 2N7002KDWH_SOT363-6 @ 3

1

1

RV5 2.2K_0402_5% @

G

RV3 2.2K_0402_5% @

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21

CV24 0.1u_0201_10V6K @

D

+3VG_AON

PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N NC81 NC82 NC83 NC84 NC85 NC86 NC87 NC88 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16

S

+3VG_AON

AG6 AG7 AF7 AE7 AE9 AF9 AG9 AG10 AF10 AE10 AE12 AF12 AG12 AG13 AF13 AE13 AE15 AF15 AG15 AG16 AF16 AE16 AE18 AF18 AG18 AG19 AF19 AE19 AE21 AF21 AG21 AG22

2

G

Part 1 of 6 PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3

D

2

RV45 10K_0402_5% @

Issued Date

Title

LC Future Center Secret Data

Security Classification

Deciphered Date

2015/08/20

N16X_PCIE/ DAC/ GPIO

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

WWW.AliSaler.Com

4

3

2

Re v 1.0

CG411

Thursday, January 14, 2016 1

Sheet

20

of

60

5

4

3

2

1

D

D

UV1C

NC

V3 V4 U3 U4 T4 T5 R4 R5 N1 M1 M2 M3 K2 K3 K1 J1 M4 M5 L3 L4 K4 K5 J4

J5 N4 N5 P3 P4

B

J2 J3 H3 H4

NC133 NC134 NC135 NC136 NC137 NC138 NC139 NC140

PGOOD NC71 NC72

THERMDP THERMDN

NC42 NC43 NC44 NC45 NC46

RV50 2

1 10K_0402_5%

@

D10 E10 F10 +3VG_AON

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 NC73

MULTI_STRAP_REF0_GND MULTI_STRAP_REF1_GNDMLS_REF1 MULTI_STRAP_REF2_GND

NC34 NC35 NC36 NC37 NC38 NC39 NC40 NC41

D11

D1 D2 E4 E3 D3 C1

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

F6 F4 F5

MULTI_STRAP_REF0_GND

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

29 29 29 29 29

C

RV181 10K_0402_5% @ 2

C

BUFRST_N

V5 V6 G1 G2 G3 G4 G5 G6 G7 V1 V2 W1 W2 W3 W4

VDD_SENSE

1

NC125 NC126 NC127 NC128 NC129 NC130 NC131 NC132

F11 AD10 AD7

RV51 40.2K_0402_1% OPT@

F12 2

NC115 NC116 NC117 NC118 NC119 NC120 NC121 NC122 NC123 NC124

GENERAL

T2 T3 T1 R1 R2 R3 N2 N3

NC50 NC51 NC52 FERMI_RSVD1 FERMI_RSVD2 NC56 NC57 NC58 NC59 NC60 NC61 NC62 NC63 NC64 NC65 NC66 NC67 NC68

LVDS/TMDS

AB5 AB4 AB3 AB2 AD3 AD2 AE1 AD1 AD4 AD5

NC105 NC106 NC107 NC108 NC109 NC110 NC111 NC112 NC113 NC114

1

Part 3 of 6 AC3 AC4 Y4 Y3 AA3 AA2 AB1 AA1 AA4 AA5

E12

F2

VCCSENSE_VGA

VCCSENSE_VGA

58

trace width: 16mils differential voltage sensing. differential signal routing.

NC47 NC48

GND_SENSE

NC49 NC141 NC142

F1

VSSSENSE_VGA

AD9 AE5 AE6 AF6 AD6 AG4

TESTMODE @ @ @ @

D12 B12 A12 C12

@ 1 ROM_SI ROM_SO ROM_SCLK

VSSSENSE_VGA 58

TEST

NC143 NC144 NC145 NC146

TESTMODE JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N

NC147 NC148

SERIAL ROM_CS_N ROM_SI ROM_SO ROM_SCLK

RV52 1 OPT@ 1 1 1 1

TV1 TV2 TV3 TV4

2 10K_0402_5% B

RV53 1 OPT@

2 10K_0402_5%

TV5 ROM_SI 29 ROM_SO 29 ROM_SCLK 29

N15S-GT-S-A2_FCBGA595 @

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

Deciphered Date

N16X_LVDS/ HDMI/ THERM

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size C

Date: 5

4

3

2

Document Number

Rev 1.0

CG411 Thursday, January 14, 2016 1

Sheet

21

of

60

5

4

3

2

1

PEX_IOVVDD/Q

M7 N7 T6 P6

NC154 NC155 NC156 NC157

FB_CAL_TERM

RF_NS@ CV215

33P_0402_50V8J

OPT@ CV39

10U_0603_6.3V6M

OPT@ CV37

4.7U_0402_6.3V6M

OPT@

1U_0402_6.3V6K

CV33

2

For RF

1.0uF

1

4.7uF

1

10uF

1

22uF

1

G10 G12

+3VG_AON

G8 G9

2

Near balls (Under GPU)

OPT@ CV49

OPT@

1

4.7U_0402_6.3V6M

2

CV48

1

Near 1U_0402_6.3V6K

2

OPT@

1

CV47

AA22 AB23 AC24 AD25 AE26 AE27

+3VG_AON

Under 0.1u_0201_10V6K

OPT@

D

+1.05VGS

1

2

Near GPU RV54 1

2 40.2_0402_1%

C24

RV56 1 OPT@

2 42.2_0402_1%

B25

RV57 1 OPT@

2 51.1_0402_1%

2

2

1

2

OPT@

1

OPT@

1

CV53

RV55 1 OPT@

1

2

@

2 0_0402_5%

4.7U_0402_6.3V6M

D22

1U_0402_6.3V6K

+1.35VGS

OPT@

+VDD33

CV52

FB_CAL_GND

1

1

CV51

FB_CAL_VDDQ

2

2

0.1u_0201_10V6K

NC150 NC151 NC152 NC153

3V3_MAIN_1 3V3_MAIN_2

2

1

OPT@

W7 AA6 W6 Y6

NC149

3V3_AON_1 3V3_AON_2

1

CV50

V7

FBVDDQ_AON_1 FBVDDQ_AON_2 FBVDDQ_AON_3 FBVDDQ_AON_4

PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 PEX_IOVDD_6

AA10 AA12 AA13 AA16 AA18 AA19 AA20 AA21 AB22 AC23 AD24 AE25 AF26 AF27

Q'ty

+1.05VGS

0.1u_0201_10V6K

H24 H26 J21 K21

PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14

MLCC

Under GPU Near GPU (below 150mils)

CV43

2

FBVDDQ_01 FBVDDQ_02 FBVDDQ_03 FBVDDQ_04 FBVDDQ_05 FBVDDQ_06 FBVDDQ_07 FBVDDQ_08 FBVDDQ_09 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27

POWER

OPT@ CV32

2

1

2000mA Part 4 of 6

B26 C25 E23 E26 F14 F21 G13 G14 G15 G16 G18 G19 G20 G21 L22 L24 L26 M21 N21 R21 T21 V21 W21

0.1u_0201_10V6K

OPT@ CV31

1

0.1u_0201_10V6K

CD@ 2

3.5A

1U_0402_6.3V6K

2

1

CV30

OPT@

1

1U_0402_6.3V6K

2

CV29

OPT@

1

4.7U_0402_6.3V6M

2

CV28

OPT@

1

4.7U_0402_6.3V6M

1

CV27

OPT@

2

Under GPU(below 150mils)

10U_0603_6.3V6M

2

CV26

CD@ CV25

D

1

22U_0603_6.3V6-M

Near GPU

22U_0603_6.3V6-M

UV1D +1.35VGS

Place near balls

2

OPT@ CV57

1

1

2

+PEX_PLLVDD

2

OPT@ CV60

OPT@

1

1

2

4.7U_0402_6.3V6M

2

CV59

N15S-GT-S-A2_FCBGA595 @

1

1U_0402_6.3V6K

@ OPT@

AA14 AA15

CV58

PEX_PLLVDD_1 PEX_PLLVDD_2

FB_CAL_x_PD_VDDQ

40.2Ohm

FB_CAL_x_PU_GND

42.2Ohm

FB_CAL_xTERM_GND

51.1Ohm

C

120ohm (ESR=0.18) Bead

120mA

NC76 NC77 NC78 NC79 NC80

DDR3

+3VG_AON

4.7U_0402_6.3V6M

OPT@

OPT@ CV56

2

0.1u_0201_10V6K

J7 K7 K6 H6 J6

AB8

1

4.7U_0402_6.3V6M

PEX_SVDD_3V3

AA8 AA9

CV55

PEX_PLL_HVDD_1 PEX_PLL_HVDD_2

0.1u_0201_10V6K

Under GPU(below 150mils) NC158 NC159 NC160 NC161

+3VGS

CALIBRATION PIN

C

T7 R7 U6 R6

Decouling

2 1 LV3 HCB1608KF-121T30_0603 1

RV62

+1.05VGS

2 0_0603_5%

@

Near balls

+3.3VS TO +3VG_AON +1.35VGS

+3VS

+3VG_AON

D

S

2

FBVDDQ_PWR_EN#

PXS_PWREN#

D

2

QV15 2N7002KW_SOT323-3 @

D

2

QV13 2N7002KW_SOT323-3 @

G

24,57 FBVDDQ_PWR_EN

D

2

S

QV18 2N7002KW_SOT323-3 @

G

S

S

2

3

S

3

1

CV64 0.1u_0201_10V6K OPT@

B

2

2

2

CV63 10U_0603_6.3V6M OPT@

2

2

RV69 47K_0402_5% @

3

3

2

RV64 470_0603_5% @

1

G

1 QV12 2N7002KW_SOT323-3 OPT@

1

2

CV62 0.01U_0201_10V6K @

1 2 RV65 10K_0402_5%

D

G

1

1

1

OPT@

1

RV67 470_0603_5% @

1 1

1 2

CV61 0.1u_0201_10V6K @

2

RV66 100K_0402_5% OPT@

OPT@ G

RV63 47K_0402_5% OPT@

8,58 PXS_PWREN

1

QV11

1

3

PXS_PWREN#

1

LP2301ALT1G_SOT23-3

+5VALW

B

+5VALW

+1.05VGS +5VALW +3VGS 1

+3VG_AON

1 2 NGC6@ 0_0603_5%

1

D

S

QV16

2

LP2301ALT1G_SOT23-3

+5VALW

RV59 470_0603_5% @

RV60 47K_0402_5% @

2

RV171

1

+3.3VS TO +3VGS

3

1 GC6@

1

1.05VGS_EN#

3

1

2

23,57,58

DGPU_PWR_EN#

5

D

2

QV9 2N7002KW_SOT323-3 @

G

3 2

CV75 0.1u_0201_10V6K GC6@

S A

S

D

2

QV20 2N7002KW_SOT323-3 @

G

S

WWW.AliSaler.Com

EN_VGA

3

CV74 10U_0603_6.3V6M GC6@

2

RV72 470_0603_5% @

1

1 2

CV73 0.01U_0201_10V6K GC6@

1

Issued Date

Title

LC Future Center Secret Data

Security Classification

S

2

RV74 100K_0402_5% GC6@

1 QV19 2N7002KW_SOT323-3 GC6@

G

2

1 2 RV73 4.7K_0402_5%

D

2

20,58 3VGS_PWR_EN

2

3

1

GC6@

1

1

2

CV72 0.1u_0201_10V6K @

1

G

DGPU_PWR_EN#

QV10 2N7002KW_SOT323-3 @

G

RV71 47K_0402_5% GC6@

A

D

2

2015/08/20

Deciphered Date

N16X_Power

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size C

Date: 4

3

2

Document Number

Rev 1.0

CG411 Thursday, January 14, 2016 1

Sheet

22

of

60

5

4

3

2

1

D

D

UV1E

GND_113 GND_114

UV1F

+VGA_CORE

K11 K13 K15 K17 L10 L12 L14 L16 L18 L2 L23 L25 L5 M11 M13 M15 M17 N10 N12 N14 N16 N18 P11 P13 P15 P17 P2 P23 P26 P5 R10 R12 R14 R16 R18 T11 T13 T15 T17 U10 U12 U14 U16 U18 U2 U23 U26 U5 V11 V13 V15 V17 Y2 Y23 Y26 Y5

+VGA_CORE Part 6 of 6

2

1

2

@ CV88

2

1

2

4.7U_0402_6.3V6M

@ CV87

2

1

4.7U_0402_6.3V6M

@ CV86

2

1

4.7U_0402_6.3V6M

OPT@ CV85

2

1

4.7U_0402_6.3V6M

OPT@ CV84

2

1

4.7U_0402_6.3V6M

OPT@ CV83

2

1

4.7U_0402_6.3V6M

OPT@ CV82

2

1

4.7U_0402_6.3V6M

OPT@ CV81

OPT@

1

4.7U_0402_6.3V6M

2

4.7U_0402_6.3V6M

CV80 RF_NS@

OPT@

OPT@

CD@

1

33P_0402_50V8J

1

4.7U_0402_6.3V6M

CV79 OPT@

2

CV213

2

1

1U_0402_6.3V6K

1

4.7U_0402_6.3V6M

CV78 OPT@

2

CV92

2

1

1U_0402_6.3V6K

1

4.7U_0402_6.3V6M

CV77 OPT@

2

CV91

2

1

1U_0402_6.3V6K

1

CV90

OPT@ CV76 OPT@

2

1U_0402_6.3V6K

CV89

1

4.7U_0402_6.3V6M

Under GPU

VDD_001 VDD_002 VDD_003 VDD_004 VDD_005 VDD_006 VDD_007 VDD_008 VDD_009 VDD_010 VDD_011 VDD_012 VDD_013 VDD_014 VDD_015 VDD_016 VDD_017 VDD_018 VDD_019 VDD_020

VDD_041 VDD_040 VDD_039 VDD_038 VDD_037 VDD_036 VDD_035 VDD_034 VDD_033 VDD_032 VDD_031 VDD_030 VDD_029 VDD_028 VDD_027 VDD_026 VDD_025 VDD_024 VDD_023 VDD_022 VDD_021

POWER

K10 K12 K14 K16 K18 L11 L13 L15 L17 M10 M12 M14 M16 M18 N11 N13 N15 N17 P10 P12

+VGA_CORE

V18 V16 V14 V12 V10 U17 U15 U13 U11 T18 T16 T14 T12 T10 R17 R15 R13 R11 P18 P16 P14

For RF C

1

2

@ CV102

2

1

2

4.7U_0402_6.3V6M

@ CV101

2

1

4.7U_0402_6.3V6M

@ CV100

2

1

4.7U_0402_6.3V6M

@ CV99

2

1

4.7U_0402_6.3V6M

@ CV98

2

1

4.7U_0402_6.3V6M

CD@ CV97

CD@

1

4.7U_0402_6.3V6M

2

4.7U_0402_6.3V6M

CV96 RF_NS@

1

33P_0402_50V8J

OPT@

4.7U_0402_6.3V6M

OPT@ CV94

CV95 CD@

2

CV214

2

2

1

CV105

1

4.7U_0402_6.3V6M

2

1

22U_0603_6.3V6-M

2

OPT@

1

CV104

2

1

22U_0603_6.3V6-M

OPT@ CV93

AA7 AB7

1

4.7U_0402_6.3V6M

N15S-GT-S-A2_FCBGA595 @

OPT@

GND_057 GND_058 GND_059 GND_060 GND_061 GND_062 GND_063 GND_064 GND_065 GND_066 GND_067 GND_068 GND_069 GND_070 GND_071 GND_072 GND_073 GND_074 GND_075 GND_076 GND_077 GND_078 GND_079 GND_080 GND_081 GND_082 GND_083 GND_084 GND_085 GND_086 GND_087 GND_088 GND_089 GND_090 GND_091 GND_092 GND_093 GND_094 GND_095 GND_096 GND_097 GND_098 GND_099 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112

CV103

Part 5 of 6

22U_0603_6.3V6-M

C

GND_001 GND_002 GND_003 GND_004 GND_005 GND_006 GND_007 GND_008 GND_009 GND_010 GND_011 GND_012 GND_013 GND_014 GND_015 GND_016 GND_017 GND_018 GND_019 GND_020 GND_021 GND_022 GND_023 GND_024 GND_025 GND_026 GND_027 GND_028 GND_029 GND_030 GND_031 GND_032 GND_033 GND_034 GND_035 GND_036 GND_037 GND_038 GND_039 GND_040 GND_041 GND_042 GND_043 GND_044 GND_045 GND_046 GND_047 GND_048 GND_049 GND_050 GND_051 GND_052 GND_053 GND_054 GND_055 GND_056

GND

A2 A26 AB11 AB14 AB17 AB20 AB24 AC2 AC22 AC26 AC5 AC8 AD12 AD13 AD15 AD16 AD18 AD19 AD21 AD22 AE11 AE14 AE17 AE20 AF1 AF11 AF14 AF17 AF20 AF23 AF5 AF8 AG2 AG26 B1 B11 B14 B17 B20 B23 B27 B5 B8 E11 E14 E17 E2 E20 E22 E25 E5 E8 H2 H23 H25 H5

For RF

Near GPU

N15S-GT-S-A2_FCBGA595 @

B

B

+VGA_CORE 1

+5VALW 2

RV173 470_0603_5% @

1

1

2

RV172 47K_0402_5% @

D

2

QV22 2N7002KW_SOT323-3 @

1

G

2

QV21 2N7002KW_SOT323-3 @

G

3

EN_VGA

3

22,57,58

D S

S

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

Deciphered Date

N16X_+VGA CORE, GND

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size C

Date: 5

4

3

2

Document Number

Rev 1.0

CG411 Thursday, January 14, 2016 1

Sheet

23

of

60

5

25,26,27,28

4

3

2

1

FBA_D[0..63]

FBA_D[0..63]

25,26,27,28 FBA_DQM[7..0] 25,26,27,28 FBA_DQS[7..0] 25,26,27,28 FBA_DQS#[7..0] 25,26,27,28

FBA_CMD[30..0]

UV1B D

D

Part 2 of 6

200mA

Place close to BGA

Place close to BGA

Place close to ball

OPT@

1

2

0.1u_0201_10V6K

2

CV113

OPT@

1

1U_0402_6.3V6K

2

CV112

CV111

1

22U_0603_6.3V6-M

OPT@

+FB_PLLAVDD

F16 P22

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FB_PLLAVDD_1 FB_PLLAVDD_2

D23 +FB_PLLAVDD

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_CLK1 FBA_CLK1_N

FB_VREF

Place close to ball

B

OPT@ FB_GC6_EN

RV119 1 RV120 1

1

2 CV115 H22 0.1u_0201_10V6K FB_CLAMP F3 2 0_0402_5% @ OPT@ 2 10K_0402_5%

FBA_CLK0 FBA_CLK0_N

FBA_WCK01 FBA_WCK01_N FBA_WCK23 FBA_WCK23_N FBA_WCK45 FBA_WCK45_N FBA_WCK67 FBA_WCK67_N

FB_DLLAVDD FB_CLAMP

RV79 1 OPT@ RV80 1 OPT@

2 100_0402_5% 2 100_0402_5%

CV106

FBA_CMD7

RV81 1 OPT@ RV82 1 OPT@

2 100_0402_5% 2 100_0402_5%

@

RV83 1 OPT@ RV84 1 OPT@

2 100_0402_5% 2 100_0402_5%

RV85 1 OPT@ RV86 1 OPT@

2 100_0402_5% 2 100_0402_5%

FBA_CMD8 FBA_CMD9 FBA_CMD10

RV87 1 OPT@ RV88 1 OPT@

2 100_0402_5% 2 100_0402_5%

FBA_RAS#

RV89 1 OPT@ RV90 1 OPT@

2 100_0402_5% 2 100_0402_5%

FBA_CMD12

RV91 1 OPT@ RV92 1 OPT@

2 100_0402_5% 2 100_0402_5%

RV93 1 OPT@ RV94 1 OPT@

2 100_0402_5% 2 100_0402_5%

+1.35VGS FBA_CMD13

F22 RV121 J22 RV122

2 2

@ @

D19 D14 C17 C22 P24 W24 AA25 U25

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

F19 C14 A16 A22 P25 W22 AB27 T27

FBA_DQS#0 FBA_DQS#1 FBA_DQS#2 FBA_DQS#3 FBA_DQS#4 FBA_DQS#5 FBA_DQS#6 FBA_DQS#7

1 60.4_0402_1% 1 60.4_0402_1% FBA_CMD14

RV95 1 OPT@ RV96 1 OPT@

2 100_0402_5% 2 100_0402_5%

FBA_CAS#

RV97 1 OPT@ RV98 1 OPT@

2 100_0402_5% 2 100_0402_5%

FBA_CMD21 FBA_CMD22

E19 C15 B16 B22 R25 W23 AB26 T26

FBA_DQS0 FBA_DQS1 FBA_DQS2 FBA_DQS3 FBA_DQS4 FBA_DQS5 FBA_DQS6 FBA_DQS7 FBA_CLK0 FBA_CLK0#

N22 M22

FBA_CLK1 FBA_CLK1#

2 100_0402_5% 2 100_0402_5%

RV101 1 OPT@ RV102 1 OPT@

2 100_0402_5% 2 100_0402_5%

FBA_CMD23

RV103 1 OPT@ RV104 1 OPT@

2 100_0402_5% 2 100_0402_5%

FBA_CMD24

RV105 1 OPT@ RV106 1 OPT@

2 100_0402_5% 2 100_0402_5%

FBA_CMD25

RV107 1 OPT@ RV108 1 OPT@

2 100_0402_5% 2 100_0402_5%

FBA_CMD26

RV109 1 OPT@ RV110 1 OPT@

2 100_0402_5% 2 100_0402_5%

FBA_CMD27

RV111 1 OPT@ RV112 1 OPT@

2 100_0402_5% 2 100_0402_5%

RV113 1 OPT@ RV114 1 OPT@

2 100_0402_5% 2 100_0402_5%

FBA_CMD28 D24 D25

RV99 1 OPT@ RV100 1 OPT@

FBA_CLK0 25,27 FBA_CLK0# 25,27

FBA_CMD29

FBA_CLK1 26,28 FBA_CLK1# 26,28

RV115 1 OPT@ RV116 1 OPT@

2 100_0402_5% 2 100_0402_5%

FBA_CMD30

RV117 1 OPT@ RV118 1 OPT@

2 100_0402_5% 2 100_0402_5%

D18 C18 D17 D16 T24 U24 V24 V25

1

2

@ 1

2

@ 1

2

0.1u_0201_10V6K

FBA_CMD6

2

0.1u_0201_10V6K

FBA_CAS# 25,26,27,28 FBA_ODT_H 26,28 FBA_CS1#_H 28 FBA_CS0#_H 26 FBA_CKE_H 26,28 FBA_RST# 25,26,27,28

2 100_0402_5% 2 100_0402_5%

1

CV107

25,26,27,28

RV77 1 OPT@ RV78 1 OPT@

@

CV108

FBA_RAS#

2 100_0402_5% 2 100_0402_5%

0.1u_0201_10V6K

FBA_CMD5

RV75 1 OPT@ RV76 1 OPT@

0.1u_0201_10V6K

OPT@

CMD mapping mod Mode E FBA_CMD4

CV109

2 LV4 1 HCB1608KF-300T60_2P

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

+1.35VGS

FBA_ODT_L 25,27 FBA_CS1#_L 27 FBA_CS0#_L 25 FBA_CKE_L 25,27

@ 1

2

@ 1

2

Rank1

Rank0 Address

0..31

FBx_CMD0

ODT_L

32..63

0..31

32..63

ODT_L

FBx_CMD1

CS1#_L

FBx_CMD2

CS0#_L

FBx_CMD3

CKE_L

FBx_CMD4

A9

A9

A11

A11

FBx_CMD5

A6

A6

A7

A7

FBx_CMD6

A3

A3

BA1

BA1

FBx_CMD7

A0

A0

A12

A12

FBx_CMD8

A8

A8

A8

A8

FBx_CMD9

A12

A12

A0

A0

FBx_CMD10

A1

A1

A2

A2

FBx_CMD11

RAS#

RAS#

RAS#

RAS#

FBx_CMD12

A13

A13

A14

A14

FBx_CMD13

BA1

BA1

A3

A3

FBx_CMD14

A14

A14

A13

A13

FBx_CMD15

CAS#

CAS#

CAS#

CAS#

FBx_CMD16

CKE_L

ODT_H

C

ODT_H

FBx_CMD17

CS1#_H

FBx_CMD18

CS0#_H

FBx_CMD19 0.1u_0201_10V6K

+FB_PLLAVDD

FBA_CMD34 FBA_CMD35

FBA_ODT_L FBA_CS1#_L FBA_CS0#_L FBA_CKE_L FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_RAS# FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CAS# FBA_ODT_H FBA_CS1#_H FBA_CS0#_H FBA_CKE_H FBA_RST# FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30

C27 C26 E24 F24 D27 D26 F25 F26 F23 G22 G23 G24 F27 G25 G27 G26 M24 M23 K24 K23 M27 M26 M25 K26 K22 J23 J25 J24 K27 K25 J27 J26 B19

CV110

+1.05VGS

FBA_CMD00 FBA_CMD01 FBA_CMD02 FBA_CMD03 FBA_CMD04 FBA_CMD05 FBA_CMD06 FBA_CMD07 FBA_CMD08 FBA_CMD09 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31 FBA_CMD32

0.1u_0201_10V6K

30ohms (ESR=0.01) Bead

FBA_D00 FBA_D01 FBA_D02 FBA_D03 FBA_D04 FBA_D05 FBA_D06 FBA_D07 FBA_D08 FBA_D09 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

CV114

C

E18 F18 E16 F17 D20 D21 F20 E21 E15 D15 F15 F13 C13 B13 E13 D13 B15 C16 A13 A15 B18 A18 A19 C19 B24 C23 A25 A24 A21 B21 C20 C21 R22 R24 T22 R23 N25 N26 N23 N24 V23 V22 T23 U22 Y24 AA24 Y22 AA23 AD27 AB25 AD26 AC25 AA27 AA26 W26 Y25 R26 T25 N27 R27 V26 V27 W27 W25

MEMORY INTERFACE A

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

CKE_H

CKE_H

FBx_CMD20

RST

RST

RST

RST

FBx_CMD21

A7

A7

A6

A6

FBx_CMD22

A4

A4

A5

A5

FBx_CMD23

A11

A11

A9

A9

FBx_CMD24

A2

A2

A1

A1

FBx_CMD25

A10

A10

WE#

WE#

FBx_CMD26

A5

A5

A4

A4

FBx_CMD27

BA2

BA2

FBx_CMD28

WE#

WE#

A10

A10

FBx_CMD29

BA0

BA0

BA0

BA0

BA2

BA2

FBx_CMD30

B

N15S-GT-S-A2_FCBGA595 @

DV4 GC6@ FB_GC6_EN

20 FB_GC6_EN

1 @ 2 RV123 0_0402_5%

GC6_EN 2 1

FBVDDQ_PWR_EN

8,57,58

1 2 @ 10K_0402_5%

BAV70W-7-F_SOT323-3 RV126

DGPU_PWROK

1 2 NGC6@ 0_0402_5%

22,57

RV125 200K_0402_5% GC6@ 2

+3VGS

RV124

1

3

A

A

Issued Date

WWW.AliSaler.Com 5

Title

LC Future Center Secret Data

Security Classification

2015/08/20

Deciphered Date

N16X_MEM Interface

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size C

Date: 4

3

2

Document Number

Rev 1.0

CG411 Thursday, January 14, 2016 1

Sheet

24

of

60

5

4

3

2

1

at least 16 mils width(optimal) 20 mils spacing to other signals /planes

FBA_D[0..63]

24,26,27,28

+1.35VGS FBA_CMD[30..0]

24,26,27,28

D

1

D

2

RANKA@ RV128 1.33K_0402_1%

UV6

+FBA_VREFCA0

+FBA_VREFCA0 +FBA_VREFDQ0

27

1

+FBA_VREFCA0

2

FBA_CMD7 FBA_CMD10 FBA_CMD24 FBA_CMD6 FBA_CMD22 FBA_CMD26 FBA_CMD5 FBA_CMD21 FBA_CMD8 FBA_CMD4 FBA_CMD25 FBA_CMD23 FBA_CMD9 FBA_CMD12 FBA_CMD14

CV116 0.01U_0201_10V6K RANKA@

2

RANKA@ RV127 1.33K_0402_1%

1

1

+1.35VGS

M8 H1 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

+FBA_VREFDQ0

+FBA_VREFDQ0

FBA_CMD29 FBA_CMD13 FBA_CMD27

27

1

2

CV216 0.01U_0201_10V6K RANKA@

FBA_CLK0 FBA_CLK0# FBA_CKE_L

24,27 FBA_CLK0 24,27 FBA_CLK0# 24,27 FBA_CKE_L

2

RANKA@ RV168 1.33K_0402_1%

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3

FBA_D5 FBA_D1 FBA_D7 FBA_D0 FBA_D4 FBA_D3 FBA_D6 FBA_D2

+FBA_VREFCA0 +FBA_VREFDQ0 FBA_CMD7 FBA_CMD10 FBA_CMD24 FBA_CMD6 FBA_CMD22 FBA_CMD26 FBA_CMD5 FBA_CMD21 FBA_CMD8 FBA_CMD4 FBA_CMD25 FBA_CMD23 FBA_CMD9 FBA_CMD12 FBA_CMD14

Group0

FBA_D31 FBA_D25 FBA_D30 FBA_D24 FBA_D29 FBA_D27 FBA_D28 FBA_D26

Group3

M8 H1 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

VREFCA VREFDQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

FBA_D11 FBA_D13 FBA_D8 FBA_D15 FBA_D10 FBA_D14 FBA_D9 FBA_D12

E3 F7 F2 F8 H3 H8 G2 H7

FBA_D17 FBA_D22 FBA_D16 FBA_D23 FBA_D19 FBA_D21 FBA_D18 FBA_D20

D7 C3 C8 C2 A7 A2 B8 A3

+1.35VGS

1

2

RANKA@ RV167 1.33K_0402_1%

VREFCA VREFDQ

M2 N8 M3

J7 K7 K9

BA0 BA1 BA2

CK CK CKE

FBA_DQM[7..0]

24,26,27,28

FBA_DQS[7..0]

24,26,27,28

FBA_DQS#[7..0]

24,26,27,28

UV5

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

Group1

FBA_CMD29 FBA_CMD13 FBA_CMD27

FBA_CLK0 FBA_CLK0# FBA_CKE_L

M2 N8 M3

J7 K7 K9

BA0 BA1 BA2

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

CK CK CKE

Rank1

Rank0 Address

0..31

FBx_CMD0

ODT_L

32..63

B2 D9 G7 K2 K8 N1 N9 R1 R9

0..31

32..63

ODT_L

FBx_CMD1 Group2

+1.35VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

CMD mapping mod Mode E

CS1#_L

FBx_CMD2

CS0#_L

FBx_CMD3

CKE_L

FBx_CMD4

A9

A9

A11

A11

FBx_CMD5

A6

A6

A7

A7

FBx_CMD6

A3

A3

BA1

BA1

FBx_CMD7

A0

A0

A12

A12

FBx_CMD8

A8

A8

A8

A8

FBx_CMD9

A12

A12

A0

A0

FBx_CMD10

A1

A1

A2

A2

FBx_CMD11

RAS#

RAS#

RAS#

RAS#

FBx_CMD12

A13

A13

A14

A14

FBx_CMD13

BA1

BA1

A3

A3

FBx_CMD14

A14

A14

A13

A13

FBx_CMD15

CAS#

CAS#

CAS#

CAS#

CKE_L

C

C

NC1 NC2 NC3 NC4 NC5

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

B1 B9 D1 D8 E2 E8 F9 G1 G9

CKE_H

CKE_H

FBx_CMD20

RST

RST

RST

RST

FBx_CMD21

A7

A7

A6

A6

FBx_CMD22

A4

A4

A5

A5

FBx_CMD23

A11

A11

A9

A9

FBx_CMD24

A2

A2

A1

A1

FBx_CMD25

A10

A10

WE#

WE#

FBx_CMD26

A5

A5

A4

A4

FBx_CMD27

BA2

BA2

FBx_CMD28

WE#

WE#

A10

A10

FBx_CMD29

BA0

BA0

BA0

BA0

BA2

BA2

FBx_CMD30

B

+1.35VGS

1

2

1

2

1

2

RF_NS@

For RF

CV139

2

CS0#_H

FBx_CMD19

RANKA@

CD@

RANKA@

1

CV131

2

0.1u_0201_10V6K

2

1

CS1#_H

FBx_CMD18

UV5 SIDE

CV130

1

0.1u_0201_10V6K

2

RANKA@

RF_NS@

For RF

1

+1.35VGS

CV129

2

ZQ

ODT_H

FBx_CMD17

96-BALL SDRAM DDR3 K4W4G1646B-HC11_FBGA96 @

33P_0402_50V8J

RANKA@

1

1U_0402_6.3V6K

CV122

RANKA@

CD@ 2

1U_0402_6.3V6K

2

1

CV121

2

1

1U_0402_6.3V6K

RANKA@

1

CV120

2

J1 L1 J9 L9 M7

RV132 243_0402_1% RANKA@

RESET

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

ODT_H

1

2

33P_0402_50V8J

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.35VGS

1U_0402_6.3V6K

RANKA@

1

L8

96-BALL SDRAM DDR3 K4W4G1646B-HC11_FBGA96 @

CV119

2

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

UV6 SIDE

0.1u_0201_10V6K

RANKA@ CV117

1

0.1u_0201_10V6K

+1.35VGS

CV118

2

RV134 10K_0402_5% RANKA@ 2

RV133 10K_0402_5% RANKA@

B

NC1 NC2 NC3 NC4 NC5

T2

DQSL DQSU

FBx_CMD16

1U_0402_6.3V6K

2 1

1

FBA_CKE_L

ZQ

FBA_RST#

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12

A1 A8 C1 C9 D2 E9 F1 H2 H9

CV134

RV131 10K_0402_5% RANKA@

FBA_ODT_L

L8 2 RV130 243_0402_1% RANKA@ J1 L1 J9 L9 M7

RESET

DML DMU

RANKA@

1

1

T2

DQSL DQSU

1U_0402_6.3V6K

FBA_RST#

FBA_RST#

E7 D3

FBA_DQS#1 G3 FBA_DQS#2 B7

CV127

24,26,27,28

DQSL DQSU

FBA_DQM1 FBA_DQM2

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

CV133

FBA_CLK0#

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12

F3 C7

ODT CS RAS CAS WE

RANKA@

2

FBA_DQS#0 G3 FBA_DQS#3 B7

DML DMU

FBA_DQS1 FBA_DQS2

K1 L2 J3 K3 L3

1U_0402_6.3V6K

E7 D3

DQSL DQSU

FBA_ODT_L FBA_CS0#_L FBA_RAS# FBA_CAS# FBA_CMD28

A1 A8 C1 C9 D2 E9 F1 H2 H9

CV132

FBA_DQM0 FBA_DQM3

RV129 162_0402_1% RANKA@

F3 C7

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

1U_0402_6.3V6K

1

FBA_CLK0

ODT CS RAS CAS WE

1

FBA_DQS0 FBA_DQS3

K1 L2 J3 K3 L3

2

FBA_ODT_L FBA_CS0#_L FBA_RAS# FBA_CAS# FBA_CMD28

24,27 FBA_ODT_L 24 FBA_CS0#_L 24,26,27,28 FBA_RAS# 24,26,27,28 FBA_CAS#

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

Deciphered Date

N16X_DDR3_Rank0_[31:0]

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size C

Date: 5

4

3

2

Document Number

Rev 1.0

CG411 Thursday, January 14, 2016 1

Sheet

25

of

60

5

4

3

2

1

at least 16 mils width(optimal) 20 mils spacing to other signals /planes

1

+1.35VGS

D

FBA_D[0..63]

RANKA@ RV135 1.33K_0402_1% 28

+FBA_VREFCA1 +FBA_VREFDQ1

1

+FBA_VREFCA1

1

2

CV141 0.01U_0201_10V6K RANKA@

2 1

+1.35VGS

2

RANKA@ RV169 1.33K_0402_1%

FBA_CMD7 FBA_CMD10 FBA_CMD24 FBA_CMD6 FBA_CMD22 FBA_CMD26 FBA_CMD5 FBA_CMD21 FBA_CMD8 FBA_CMD4 FBA_CMD25 FBA_CMD23 FBA_CMD9 FBA_CMD12 FBA_CMD14

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

FBA_CMD29 FBA_CMD13 FBA_CMD27

M2 N8 M3

28

1

+FBA_VREFDQ1

1

FBA_CLK1 FBA_CLK1# FBA_CKE_H

24,28 FBA_CLK1 24,28 FBA_CLK1# 24,28 FBA_CKE_H

2

2

CV217 0.01U_0201_10V6K RANKA@

C

24,28 24 24,25,27,28 24,25,27,28

FBA_ODT_H FBA_CS0#_H FBA_RAS# FBA_CAS# FBA_CMD28

FBA_ODT_H FBA_CS0#_H FBA_RAS# FBA_CAS#

J7 K7 K9 K1 L2 J3 K3 L3

FBA_CLK1 1

FBA_DQS4 FBA_DQS7 RV137 162_0402_1%

2

VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

E3 F7 F2 F8 H3 H8 G2 H7

FBA_D34 FBA_D38 FBA_D35 FBA_D39 FBA_D32 FBA_D36 FBA_D33 FBA_D37

+FBA_VREFCA1 +FBA_VREFDQ1

M8 H1

FBA_CMD7 FBA_CMD10 FBA_CMD24 FBA_CMD6 FBA_CMD22 FBA_CMD26 FBA_CMD5 FBA_CMD21 FBA_CMD8 FBA_CMD4 FBA_CMD25 FBA_CMD23 FBA_CMD9 FBA_CMD12 FBA_CMD14

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

B2 D9 G7 K2 K8 N1 N9 R1 R9

FBA_CMD29 FBA_CMD13 FBA_CMD27

M2 N8 M3

A1 A8 C1 C9 D2 E9 F1 H2 H9

FBA_ODT_H FBA_CS0#_H FBA_RAS# FBA_CAS# FBA_CMD28

D7 C3 C8 C2 A7 A2 B8 A3

FBA_D59 FBA_D62 FBA_D58 FBA_D63 FBA_D57 FBA_D60 FBA_D56 FBA_D61

Group4

Group7

VREFCA VREFDQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

FBA_D44 FBA_D43 FBA_D45 FBA_D40 FBA_D47 FBA_D42 FBA_D46 FBA_D41

E3 F7 F2 F8 H3 H8 G2 H7

FBA_DQM4 FBA_DQM7

RANKA@

F3 C7 E7 D3

BA0 BA1 BA2

CK CK CKE ODT CS RAS CAS WE DQSL DQSU DML DMU

FBA_CLK1# FBA_DQS#4 G3 FBA_DQS#7 B7

24,25,27,28

FBA_RST#

FBA_RST#

T2 L8

FBA_CKE_H 1

J1 L1 J9 L9 M7

RV140 243_0402_1% RANKA@ 2

1

1

FBA_ODT_H

2

2

RV138 RV139 10K_0402_5% 10K_0402_5% RANKA@ RANKA@

DQSL DQSU

RESET ZQ NC1 NC2 NC3 NC4 NC5

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

FBA_CLK1 J7 FBA_CLK1# K7 FBA_CKE_H K9

FBA_DQS5 FBA_DQS6 FBA_DQM5 FBA_DQM6

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

K1 L2 J3 K3 L3 F3 C7 E7 D3

FBA_DQS#5 G3 FBA_DQS#6 B7

FBA_RST#

T2 L8

B1 B9 D1 D8 E2 E8 F9 G1 G9

J1 L1 J9 L9 M7

RV141 243_0402_1% RANKA@

BA0 BA1 BA2

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

CK CK CKE ODT CS RAS CAS WE

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

DQSL DQSU DML DMU

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12

DQSL DQSU

RESET ZQ NC1 NC2 NC3 NC4 NC5

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

FBA_CMD[30..0]

24,25,27,28

FBA_DQM[7..0]

24,25,27,28

FBA_DQS[7..0]

24,25,27,28

FBA_DQS#[7..0]

24,25,27,28

Rank0 Group6

Address

0..31

FBx_CMD0

ODT_L

Rank1

32..63

0..31 CS1#_L

FBx_CMD1

B2 D9 G7 K2 K8 N1 N9 R1 R9 A1 A8 C1 C9 D2 E9 F1 H2 H9

FBx_CMD2

CS0#_L

FBx_CMD3

CKE_L

FBx_CMD4

A9

A9

A11

A11

FBx_CMD5

A6

A6

A7

A7

FBx_CMD6

A3

A3

BA1

BA1

FBx_CMD7

A0

A0

A12

A12

FBx_CMD8

A8

A8

A8

A8

FBx_CMD9

A12

A12

A0

A0

FBx_CMD10

A1

A1

A2

A2

FBx_CMD11

RAS#

RAS#

RAS#

RAS#

FBx_CMD12

A13

A13

A14

A14

FBx_CMD13

BA1

BA1

A3

A3

FBx_CMD14

A14

A14

A13

A13

FBx_CMD15

CAS#

CAS#

CAS#

CAS#

CKE_L

C

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

ODT_H

ODT_H

FBx_CMD16

CS1#_H

FBx_CMD17 CS0#_H

FBx_CMD18

CKE_H

CKE_H

FBx_CMD19 B1 B9 D1 D8 E2 E8 F9 G1 G9

96-BALL SDRAM DDR3 K4W4G1646B-HC11_FBGA96 @

FBx_CMD20

RST

RST

RST

RST

FBx_CMD21

A7

A7

A6

A6

FBx_CMD22

A4

A4

A5

A5

FBx_CMD23

A11

A11

A9

A9

FBx_CMD24

A2

A2

A1

A1

FBx_CMD25

A10

A10

WE#

WE#

FBx_CMD26

A5

A5

A4

A4

FBx_CMD27

BA2

BA2

FBx_CMD28

WE#

WE#

A10

A10

FBx_CMD29

BA0

BA0

BA0

BA0

BA2

BA2

RF_NS@

1

2

33P_0402_50V8J

CV164

CD@ 2

1U_0402_6.3V6K

2

For RF 1

CV159

RANKA@

1

1U_0402_6.3V6K

2

CV158

RANKA@

1

1U_0402_6.3V6K

2

CV157

RANKA@

RANKA@

1

1U_0402_6.3V6K

CV156

2

0.1u_0201_10V6K

2

1

B

+1.35VGS

UV7 SIDE

CV155

RANKA@

RF_NS@

1

0.1u_0201_10V6K

2

CV154

2

1

+1.35VGS

33P_0402_50V8J

1

CV152

RANKA@

For RF 1U_0402_6.3V6K

2

CV147

RANKA@

1

1U_0402_6.3V6K

2

CV146

RANKA@

1

1U_0402_6.3V6K

CV145

CD@ 2

1U_0402_6.3V6K

2

1

CV144

RANKA@

RANKA@

1

0.1u_0201_10V6K

CV143

2

0.1u_0201_10V6K

CV142

1

+1.35VGS

UV8 SIDE

32..63

ODT_L

FBx_CMD30

+1.35VGS

D

CMD mapping mod Mode E

+1.35VGS

96-BALL SDRAM DDR3 K4W4G1646B-HC11_FBGA96 @

B

Group5

FBA_D52 FBA_D50 FBA_D55 FBA_D51 FBA_D53 FBA_D48 FBA_D54 FBA_D49

D7 C3 C8 C2 A7 A2 B8 A3

+1.35VGS

+FBA_VREFDQ1

RANKA@ RV170 1.33K_0402_1%

M8 H1

1

RANKA@ RV136 1.33K_0402_1%

UV7

2

2

UV8 +FBA_VREFCA1

24,25,27,28

A

A

Issued Date

WWW.AliSaler.Com 5

Title

LC Future Center Secret Data

Security Classification

2015/08/20

Deciphered Date

N16X_DDR3_Rank0_[64:32]

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size C

Date: 4

3

2

Document Number

Rev 1.0

CG411 Thursday, January 14, 2016 1

Sheet

26

of

60

5

4

3

2

1

FBA_D[0..63]

D

UV9 +FBA_VREFCA0 +FBA_VREFDQ0

25 +FBA_VREFCA0 25 +FBA_VREFDQ0

at least 16 mils width(optimal) 20 mils spacing to other signals /planes

FBA_CMD9 FBA_CMD24 FBA_CMD10 FBA_CMD13 FBA_CMD26 FBA_CMD22 FBA_CMD21 FBA_CMD5 FBA_CMD8 FBA_CMD23 FBA_CMD28 FBA_CMD4 FBA_CMD7 FBA_CMD14 FBA_CMD12

M8 H1 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

FBA_D1 FBA_D5 FBA_D0 FBA_D7 FBA_D2 FBA_D6 FBA_D3 FBA_D4

D7 C3 C8 C2 A7 A2 B8 A3

FBA_D25 FBA_D31 FBA_D24 FBA_D30 FBA_D26 FBA_D28 FBA_D27 FBA_D29

+FBA_VREFCA0 +FBA_VREFDQ0

M8 H1

FBA_CMD9 FBA_CMD24 FBA_CMD10 FBA_CMD13 FBA_CMD26 FBA_CMD22 FBA_CMD21 FBA_CMD5 FBA_CMD8 FBA_CMD23 FBA_CMD28 FBA_CMD4 FBA_CMD7 FBA_CMD14 FBA_CMD12

Group0

Group3

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

24,25 FBA_ODT_L 24 FBA_CS1#_L 24,25,26,28 FBA_RAS# 24,25,26,28 FBA_CAS#

J7 K7 K9

FBA_ODT_L FBA_CS1#_L FBA_RAS# FBA_CAS# FBA_CMD25

K1 L2 J3 K3 L3

FBA_DQS0 FBA_DQS3 FBA_DQM0 FBA_DQM3

F3 C7 E7 D3

FBA_DQS#0 G3 FBA_DQS#3 B7

24,25,26,28

FBA_RST#

FBA_RST# 1

T2

L8 2 RV142 243_0402_1% RANKB@ J1 L1 J9 L9 M7

CK CK CKE ODT CS RAS CAS WE DQSL DQSU DML DMU DQSL DQSU

RESET ZQ NC1 NC2 NC3 NC4 NC5

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

B2 D9 G7 K2 K8 N1 N9 R1 R9

FBA_CMD29 FBA_CMD6 FBA_CMD30

FBA_CLK0 FBA_CLK0# FBA_CKE_L

J7 K7 K9

A1 A8 C1 C9 D2 E9 F1 H2 H9

FBA_ODT_L FBA_CS1#_L FBA_RAS# FBA_CAS# FBA_CMD25

K1 L2 J3 K3 L3

M2 N8 M3

FBA_DQS1 FBA_DQS2

F3 C7

FBA_DQM1 FBA_DQM2

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

E7 D3

FBA_DQS#1 G3 FBA_DQS#2 B7

FBA_RST#

T2 L8

1

C

FBA_CLK0 FBA_CLK0# FBA_CKE_L

BA0 BA1 BA2

B1 B9 D1 D8 E2 E8 F9 G1 G9

J1 L1 J9 L9 M7

RV143 243_0402_1% RANKB@

96-BALL SDRAM DDR3 K4W4G1646B-HC11_FBGA96 @

B

24,25,26,28

FBA_DQM[7..0]

24,25,26,28

FBA_DQS[7..0]

24,25,26,28

FBA_DQS#[7..0]

24,25,26,28

VREFCA VREFDQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

E3 F7 F2 F8 H3 H8 G2 H7

FBA_D13 FBA_D11 FBA_D15 FBA_D8 FBA_D12 FBA_D9 FBA_D14 FBA_D10

Group1

D7 C3 C8 C2 A7 A2 B8 A3

FBA_D22 FBA_D17 FBA_D23 FBA_D16 FBA_D20 FBA_D18 FBA_D21 FBA_D19

Group2

CMD mapping mod Mode E

BA0 BA1 BA2

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

CK CK CKE ODT CS RAS CAS WE

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

DQSL DQSU DML DMU

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12

DQSL DQSU

RESET ZQ NC1 NC2 NC3 NC4 NC5

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

Rank1

Rank0

B2 D9 G7 K2 K8 N1 N9 R1 R9

Address

0..31

FBx_CMD0

ODT_L

32..63

FBx_CMD1 FBx_CMD2

A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

CS1#_L CS0#_L

FBx_CMD3

CKE_L

FBx_CMD4

A9

A9

A11

A11

FBx_CMD5

A6

A6

A7

A7

FBx_CMD6

A3

A3

BA1

BA1

FBx_CMD7

A0

A0

A12

A12

FBx_CMD8

A8

A8

A8

A8

FBx_CMD9

A12

A12

A0

A0

FBx_CMD10

A1

A1

A2

A2

FBx_CMD11

RAS#

RAS#

RAS#

RAS#

FBx_CMD12

A13

A13

A14

A14

FBx_CMD13

BA1

BA1

A3

A3

FBx_CMD14

A14

A14

A13

A13

FBx_CMD15

CAS#

CAS#

CAS#

CAS#

CKE_L

ODT_H

FBx_CMD16

B1 B9 D1 D8 E2 E8 F9 G1 G9

CS1#_H

FBx_CMD18

CS0#_H

FBx_CMD19

CKE_H RST

RST

RST

RST

FBx_CMD21

A7

A7

A6

A6

FBx_CMD22

A4

A4

A5

A5

FBx_CMD23

A11

A11

A9

A9

FBx_CMD24

A2

A2

A1

A1

FBx_CMD25

A10

A10

WE#

WE#

FBx_CMD26

A5

A5

A4

A4

FBx_CMD27

BA2

BA2

FBx_CMD28

WE#

WE#

A10

A10

FBx_CMD29

BA0

BA0

BA0

BA0

BA2

BA2

2

RF_NS@

1

2

33P_0402_50V8J

1

CV188

RANKB@

For RF 1U_0402_6.3V6K

2

CV183

RANKB@

1

1U_0402_6.3V6K

CV182

CD@ 2

1U_0402_6.3V6K

2

1

CV181

RANKB@

RANKB@

1

B

+1.35VGS

1U_0402_6.3V6K

CV180

2

0.1u_0201_10V6K

2

1

CKE_H

FBx_CMD20

UV3 SIDE

CV179

RANKB@

1

0.1u_0201_10V6K

2

CV178

RF_NS@

1

+1.35VGS

33P_0402_50V8J

2

CV176

RANKB@

1

1U_0402_6.3V6K

2

CV171

RANKB@

1

1U_0402_6.3V6K

CV170

CD@ 2

1U_0402_6.3V6K

2

1

CV169

RANKB@

1

1U_0402_6.3V6K

2

CV168

RANKB@

RANKB@

1

0.1u_0201_10V6K

CV167

2

0.1u_0201_10V6K

CV166

1

+1.35VGS

For RF

C

ODT_H

FBx_CMD17

96-BALL SDRAM DDR3 K4W4G1646B-HC11_FBGA96 @

UV4 SIDE

32..63

0..31 ODT_L

FBx_CMD30

+1.35VGS

D

+1.35VGS

2

24,25 FBA_CLK0 24,25 FBA_CLK0# 24,25 FBA_CKE_L

M2 N8 M3

FBA_CMD[30..0]

UV10 E3 F7 F2 F8 H3 H8 G2 H7

+1.35VGS FBA_CMD29 FBA_CMD6 FBA_CMD30

24,25,26,28

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

Deciphered Date

N16X_DDR3_Rank1_[31:0]

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size C

Date: 5

4

3

2

Document Number

Rev 1.0

CG411 Thursday, January 14, 2016 1

Sheet

27

of

60

5

4

3

2

1

FBA_D[0..63]

24,25,26,27

FBA_CMD[30..0]

24,25,26,27

FBA_DQM[7..0]

24,25,26,27

FBA_DQS[7..0]

24,25,26,27

FBA_DQS#[7..0]

24,25,26,27

D

D

at least 16 mils width(optimal) 20 mils spacing to other signals /planes

FBA_CMD9 FBA_CMD24 FBA_CMD10 FBA_CMD13 FBA_CMD26 FBA_CMD22 FBA_CMD21 FBA_CMD5 FBA_CMD8 FBA_CMD23 FBA_CMD28 FBA_CMD4 FBA_CMD7 FBA_CMD14 FBA_CMD12

M8 H1 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

UV12

VREFCA VREFDQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3

FBA_D38 FBA_D34 FBA_D39 FBA_D35 FBA_D37 FBA_D33 FBA_D36 FBA_D32 FBA_D62 FBA_D59 FBA_D63 FBA_D58 FBA_D61 FBA_D56 FBA_D60 FBA_D57

+FBA_VREFCA1 +FBA_VREFDQ1 FBA_CMD9 FBA_CMD24 FBA_CMD10 FBA_CMD13 FBA_CMD26 FBA_CMD22 FBA_CMD21 FBA_CMD5 FBA_CMD8 FBA_CMD23 FBA_CMD28 FBA_CMD4 FBA_CMD7 FBA_CMD14 FBA_CMD12

Group4

Group7

M8 H1 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

VREFCA VREFDQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

FBA_D43 FBA_D44 FBA_D40 FBA_D45 FBA_D41 FBA_D46 FBA_D42 FBA_D47

E3 F7 F2 F8 H3 H8 G2 H7

FBA_D50 FBA_D52 FBA_D51 FBA_D55 FBA_D49 FBA_D54 FBA_D48 FBA_D53

D7 C3 C8 C2 A7 A2 B8 A3

+1.35VGS

C

FBA_CLK1 FBA_CLK1# FBA_CKE_H

J7 K7 K9

FBA_ODT_H FBA_CS1#_H FBA_RAS# FBA_CAS# FBA_CMD25

FBA_ODT_H FBA_CS1#_H FBA_RAS# FBA_CAS#

FBA_DQS4 FBA_DQS7 FBA_DQM4 FBA_DQM7

K1 L2 J3 K3 L3 F3 C7 E7 D3

FBA_DQS#4 G3 FBA_DQS#7 B7

24,25,26,27

FBA_RST#

FBA_RST#

T2 L8

1

J1 L1 J9 L9 M7

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

CK CK CKE ODT CS RAS CAS WE

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

DQSL DQSU DML DMU

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12

DQSL DQSU

RESET ZQ NC1 NC2 NC3 NC4 NC5

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

2

RV144 243_0402_1% RANKB@

BA0 BA1 BA2

FBA_CMD29 FBA_CMD6 FBA_CMD30

B2 D9 G7 K2 K8 N1 N9 R1 R9

FBA_ODT_H FBA_CS1#_H FBA_RAS# FBA_CAS# FBA_CMD25

A1 A8 C1 C9 D2 E9 F1 H2 H9

FBA_DQS5 FBA_DQS6 FBA_DQM5 FBA_DQM6

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

K1 L2 J3 K3 L3 F3 C7 E7 D3

FBA_DQS#5 G3 FBA_DQS#6 B7

FBA_RST#

T2 L8

B1 B9 D1 D8 E2 E8 F9 G1 G9

RV145 243_0402_1% RANKB@

96-BALL SDRAM DDR3 K4W4G1646B-HC11_FBGA96 @

B

M2 N8 M3

FBA_CLK1 J7 FBA_CLK1# K7 FBA_CKE_H K9

1

24,26 24 24,25,26,27 24,25,26,27

M2 N8 M3

Group6

CMD mapping mod Mode E

J1 L1 J9 L9 M7

BA0 BA1 BA2

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

CK CK CKE ODT CS RAS CAS WE

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

DQSL DQSU DML DMU

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12

DQSL DQSU

RESET ZQ NC1 NC2 NC3 NC4 NC5

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

Rank1

Rank0

+1.35VGS

2

24,26 FBA_CLK1 24,26 FBA_CLK1# 24,26 FBA_CKE_H

FBA_CMD29 FBA_CMD6 FBA_CMD30

Group5

B2 D9 G7 K2 K8 N1 N9 R1 R9

Address

0..31

FBx_CMD0

ODT_L

32..63

A1 A8 C1 C9 D2 E9 F1 H2 H9

CS1#_L CS0#_L CKE_L

FBx_CMD3

CKE_L

FBx_CMD4

A9

A9

A11

A11

FBx_CMD5

A6

A6

A7

A7

FBx_CMD6

A3

A3

BA1

BA1

FBx_CMD7

A0

A0

A12

A12

FBx_CMD8

A8

A8

A8

A8

FBx_CMD9

A12

A12

A0

A0

FBx_CMD10

A1

A1

A2

A2

FBx_CMD11

RAS#

RAS#

RAS#

RAS#

FBx_CMD12

A13

A13

A14

A14

FBx_CMD13

BA1

BA1

A3

A3

FBx_CMD14

A14

A14

A13

A13

FBx_CMD15

CAS#

CAS#

CAS#

CAS#

C

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

ODT_H

FBx_CMD16

CS1#_H CS0#_H

FBx_CMD18

CKE_H

FBx_CMD19

96-BALL SDRAM DDR3 K4W4G1646B-HC11_FBGA96 @

RST

RST

RST

RST

FBx_CMD21

A7

A7

A6

A6

FBx_CMD22

A4

A4

A5

A5

FBx_CMD23

A11

A11

A9

A9

FBx_CMD24

A2

A2

A1

A1

FBx_CMD25

A10

A10

WE#

WE#

FBx_CMD26

A5

A5

A4

A4

FBx_CMD27

BA2

BA2

FBx_CMD28

WE#

WE#

A10

A10

FBx_CMD29

BA0

BA0

BA0

BA0

BA2

BA2

+1.35VGS RF_NS@ CV212

CD@ 2

1U_0402_6.3V6K

2

1

CV207

RANKB@

1

1U_0402_6.3V6K

2

CV206

RANKB@

1

1U_0402_6.3V6K

2

CV205

RANKB@

RANKB@

1

B

For RF 1U_0402_6.3V6K

CV204

2

0.1u_0201_10V6K

2

1

CKE_H

FBx_CMD20

UV5 SIDE

CV203

RANKB@

1

0.1u_0201_10V6K

2

CV202

RF_NS@

1

33P_0402_50V8J

2

CV200

RANKB@

1

1U_0402_6.3V6K

CV195

CD@ 2

1U_0402_6.3V6K

2

1

CV194

RANKB@

1

1U_0402_6.3V6K

2

CV193

RANKB@

1

+1.35VGS

For RF 1U_0402_6.3V6K

2

CV192

RANKB@

RANKB@

1

0.1u_0201_10V6K

CV191

2

0.1u_0201_10V6K

CV190

1

+1.35VGS

UV6 SIDE

ODT_H

FBx_CMD17

B1 B9 D1 D8 E2 E8 F9 G1 G9

FBx_CMD30

+1.35VGS

32..63

ODT_L

FBx_CMD1 FBx_CMD2

0..31

1

2

33P_0402_50V8J

UV11 +FBA_VREFCA1 +FBA_VREFDQ1

26 +FBA_VREFCA1 26 +FBA_VREFDQ1

A

A

Issued Date

WWW.AliSaler.Com 5

Title

LC Future Center Secret Data

Security Classification

2015/08/20

Deciphered Date

N16X_DDR3_Rank1_[64:32]

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size C

Date: 4

3

2

Document Number

Rev 1.0

CG411 Thursday, January 14, 2016 1

Sheet

28

of

60

5

4

3

+3VG_AON

2

2

RV150 45.3K_0402_1% @

+3VGS

1

Logical Strapping Bit3

Logical Strapping Bit2

Logical Strapping Bit1

Logical Strapping Bit0

SOR3_EXPOSED

SOR2_EXPOSED

SOR1_EXPOSED

SOR0_EXPOSED

ROM_SI

+3VGS

RAM_CFG[3]

RAM_CFG[2]

RAM_CFG[1]

RAM_CFG[0]

ROM_SO

+3VGS

DEVID_SEL

PCIE_CFG

SMB_ALT_ADDR

VGA_DEVICE

STRAP0

+3VGS

STRAP1

+3VGS

STRAP2

+3VGS

STRAP3

+3VGS

STRAP4

+3VGS

RV155 45.3K_0402_1% @

Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)

Reserved(keep pull-up and pull-down footprint and not stuff by default)

DEVID_SEL

Pull-up to +3VGS

Pull-down to Gnd

4.99K

1000

0000

10K

1001

0001

15K

1010

0010

20K

1011

0011

24.9K

1100

0100

30.1K

1101

0101

34.8K

1110

0110

45.3K

1111

0111

Resistor Values

D

0

(Default)

1

RV154 4.99K_0402_1% @ 1

1

RV153 15K_0402_1% @

Power Rail

2

2

2

2 RV152 4.99K_0402_1% @ 1

1

RV151 45.3K_0402_1% @

Physical Strapping pin ROM_SCLK

1

RV149 4.99K_0402_1% @ 1

1

RV148 24.9K_0402_1% @

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

2

21 21 21 21 21

RV147 4.99K_0402_1% @ 1

1

RV146 49.9K_0402_1% OPT@

2

2

2

D

2

+3VGS

1

PCIE_CFG 0

(Default)

1

C

C

RV158 4.99K_0402_1% @

0

0x9E (Default)

1

0x9C (Multi-GPU usage)

1

RV157 4.99K_0402_1% @ 1

1

RV156 4.99K_0402_1% @

2

2

X76

2

SMBUS_ALT_ADDR

VGA_DEVICE

B

GPU

Configuration

FB Memory (DDR3L) Samsung 900MHz

Single-Rank

Hynix 900MHz Micron 900MHz

N16S-GTR N16V-GMR1

Samsung 900MHz Dual-Rank

Hynix 900MHz Micron 900MHz

2 RV160 4.99K_0402_1% OPT@

3D Device (Class Code 302h)

1

VGA Device (Default)

RV161 4.99K_0402_1% OPT@

1

1

RV159 20K_0402_1% @

0

1

2

2

ROM_SI ROM_SO ROM_SCLK

21 ROM_SI 21 ROM_SO 21 ROM_SCLK

ROM_SI

ROM_SO

K4W4G1646E-BC1A

0x1

256M x 16

PD 10K

H5TC4G63CFR-N0C

0x2

256M x 16

PD 15K

MT41J256M16LY-091G:N

0x6

256M x 16

PD 34.8K

K4W4G1646E-BC1A

0xF

256M x 16

PU 45.3K

H5TC4G63CFR-N0C

0xE

256M x 16

PU 34.8K

MT41J256M16LY-091G:N

0xA

256M x 16

PU 15K

ROM_SCLK

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

VRAM

X76 P/N X7610212201

4

X7610212001

8

X7610212202

4

X7610212101

8

X7610212203

4

N/A

8

Samsung

Hynix PD 4.99K

PD 4.99K

PU 49.9K

Un-stuff

Un-stuff

Un-stuff

Un-stuff

VRAM Q'ty

Micron

B

VRAM P/N SA000063F20

SA00007DU10

SA00007QJ00

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

Deciphered Date

N16X_MISC

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size C

Date: 5

4

3

2

Document Number

Rev 1.0

CG411 Thursday, January 14, 2016 1

Sheet

29

of

60

5

4

3

2

1

UW1 RW2 1 RW9 1 RW10 1

USB20_N5 USB20_P5

9 USB20_N5 9 USB20_P5

@ @

2 6.2K_0402_1% 2 0_0402_5% 2 0_0402_5%

+3VS D

CW2 4.7U_0402_6.3V6M LW1 USB20_N5

1

1

2

2

RREF USB20_N5_R USB20_P5_R CARD_3V3 SDREG

1

1

2

2

USB20_N5_R

SD_WP

CW3 0.1u_0201_10V6K CW4 1U_0402_6.3V6K

SD_D1_R SD_D0_R

1

2 USB20_P5

FOR EMI

C

SD_D0_R

4

4

3

3

1 2 3 4 5 6 7 8 9 10 11 12 25

@

V18 XD_D7 SP14 SP13 SP12 SP11 SP10 GPIO0 SP9 SP8 SP7 SP6

24 23 22 21 20 19 18 17 16 15 14 13

1U_0402_6.3V6K 2

VDD18

1

CW1

SD_D2_R SD_D3_R SD_CMD_R

D

SD_CLK_R SD_CD#

GND

USB20_P5_R

EXC24CH900U_4P EMC_NS@

RW3 1

RREF DM DP 3V3_IN CARD_3V3 SDREG XD_CD# SP1 SP2 SP3 SP4 SP5

RTS5170-GRT_QFN24_4X4

SD_D0

2 0_0402_5% CW5 1

2 5.6P_0402_50V8-D

C

SD / MMC

EMC@ CARD_3V3 @

SD_D1

2 0_0402_5% CW6 1

JREAD1

2 5.6P_0402_50V8-D

4

EMC@ SD_D2_R

RW5 1

@

SD_D2

2 0_0402_5% CW7 1

2 5.6P_0402_50V8-D EMC@

SD_D3_R

RW6 1

@

CW8 1

CW9

2

SD_D0 SD_D1 SD_D2 SD_D3

1 CW17

2

Close to Connector

SD_D3

2 0_0402_5%

1

0.1u_0201_10V6K

RW4 1

4.7U_0402_6.3V6M

SD_D1_R

SD_CD# SD_WP

11 10

SD_CMD SD_CLK

2 5

2 5.6P_0402_50V8-D 3 6

EMC@ SD_CMD_R

RW7 1

@

CW11 1

VDD DAT0 DAT1 DAT2 CD/DAT3 C/D W/P CMD CLK VSS1 VSS2

GND_1 GND_2

12 13

DEREN_404232501111RHF_NR ME@

SD_CMD

2 0_0402_5%

B

7 8 9 1

2 5.6P_0402_50V8-D

B

EMC@ SD_CLK

2 0_0402_5% 2 5.6P_0402_50V8-D

Close to Connector

EMC@

1

AZ5123-01F.R7GR_DFN1006P2X2

CARD_3V3

DW1

1

CW12 1

2

RW8 1

2

SD_CLK_R

EMC_NS@

FOR ESD

A

A

Title

LC Future Center Secret Data

Security Classification Issued Date

2015/08/20

Cardreader

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

WWW.AliSaler.Com

4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet 1

30

of

60

5

4

+5VS @

1

2 0_0603_5%

1

2.285W, 0.457A

ENB

OCB

3D@ 2 0_0603_5% @

3

1

SY6288D20AAC_SOT23-5

1

33 CMOS_ON#

R282 1

2

2

C1112

R273 100K_0402_5% @

1

2

RF_NS@

GND 4

1 2

1

2

47P_0402_50V8J

OUT

C1114

IN

RF_NS@

5

D

3D@

2200P_0402_50V7K

U15

C1113

2

+5VS_CMOS

4.7U_0603_10V6-K

C1111 1U_0402_10V6K 3D@

2

+5VS_CMOS_R R271 1

D

3

3D Camera DB Connector

For RF

+5VS_CMOS J3D

C

+3VS

Prevent damage CPU from LAN surge 8 3D_FR USB30_TX_P3 USB30_TX_N3

9 USB30_TX_P3 9 USB30_TX_N3

R293 1 3D@ R294 1 3D@

2 0_0402_5% 2 0_0402_5%

USB30_TX_P3_R USB30_TX_N3_R

3D@ 3D@

C1115 1 C1116 1

2 0.1u_0201_10V6K 2 0.1u_0201_10V6K

USB30_TX_C_P3 USB30_TX_C_N3

USB30_RX_P3 USB30_RX_N3

9 USB30_RX_P3 9 USB30_RX_N3

R274 1 3D@ R275 1 3D@

2 0_0402_5% 2 0_0402_5%

USB30_TX_R_P3 USB30_TX_R_N3

R276 1 3D@ R277 1 3D@

2 0_0402_5% 2 0_0402_5%

USB30_RX_R_P3 USB30_RX_R_N3

33,43 DMIC_CLK 33,43 DMIC_DATA

B

L18 USB30_TX_C_P3

1

USB30_TX_C_N3

4

1

2

4

3

L19 1

USB30_RX_N3

4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

C

GND1 GND2

21 22 B

EMC_NS@ 2

USB30_TX_R_P3

3

USB30_TX_R_N3

I-PEX_20374-020E-31 ME@

08/29: Double confirm if can change to 18pin

EXC24CH900U_4P

USB30_RX_P3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

EMC_NS@

1

2

4

3

2

USB30_RX_R_P3

3

USB30_RX_R_N3

EXC24CH900U_4P

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

3D Camera

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet 1

31

of

60

5

4

3

+3VS RTPM1 1 TPM@

2

1

+3VS_TPM

D

1

2

CTPM4 0.1u_0201_10V6K TPM@

2 0_0603_5% 1

1A 1 CTPM1 10U_0603_6.3V6M TPM@

2

2

D

CTPM3 0.1u_0201_10V6K TPM@

TPM +3VS_TPM UTPM1 C

RTPM12

1 TPM@ 2 0_0402_5%

Reserve for Nationz TPM

1 2 3 7 6 9 4 11 18

+3VALW RTPM11

1 TPM@ 2 0_0603_5%

NC_1 NC_2 NC_3 PP

VDD3 VDD1 LPCPD# SERIRQ LAD0 LAD1 LFRAME# LAD2 LAD3

NC_4 NC_7 GND_1 GND_2 GND_3 NC_5 NC_6 NC_8 NC_9 NC_10

GND_4 LCLK VDD2 CLK_RUN# LRESET#

24 10 28 27 26 23 22 20 17 25 21 19 15 16

RTPM2 1 TPM@ 2 SERIRQ_TPM RTPM5 LPC_AD0_TPM RTPM6 LPC_AD1_TPM RTPM7 LPC_FRAME#_TPM RTPM8 LPC_AD2_TPM RTPM9 LPC_AD3_TPM RTPM10

C

Reserve for Nationz TPM

4.7K_0402_5% 1 TPM@ 2 0_0402_5% 1 TPM@ 2 0_0402_5% 1 TPM@ 2 0_0402_5% 1 TPM@ 2 0_0402_5% 1 TPM@ 2 0_0402_5% 1 TPM@ 2 0_0402_5%

SERIRQ 7,44 LPC_AD0 7,44 LPC_AD1 7,44 LPC_FRAME# 7,44 LPC_AD2 7,44 LPC_AD3 7,44 +3VS_TPM CLK_PCI_TPM

TPM_CLKRUN#

7

2 RTPM13 1 @ 0_0402_5%

PLT_RST# 11,20,37,40,44 1

Add for Nuvoton TPM

5 8 12 13 14

TPM@

PM_CLKRUN#

7

Reserve for Nuvoton TPM RTPM4 0_0402_5% TPM@

2

Z32H320TC-LPC-T28-LT1_TSSOP28

B

B

Nationz TPM

Nuvoton TPM

RTPM2

Stuff

NC

RTPM12

Stuff

NC

RTPM11

NC

Stuff

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

TPM

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

WWW.AliSaler.Com

4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet 1

32

of

60

4

3

2

1

LCD POWER CIRCUIT

CMOS Camera

+3VS

Need  short

+3VS +LCDVDD

+LCDVDD_CON

J1

1

C121

U5 EN PIN VIH MIN 1.5V

RF_NS@

2

LP2301ALT1G_SOT23-3 Q7 C5 0.1u_0201_10V6K @ CMOS_ON#

For RF

PCH_ENVDD

C9 0.01U_0201_25V6-K EMC_NS@

1 R1 100K_0402_5%

CD@

2

1

C14

2

1

2

R13 100K_0402_1%

R15 100K_0402_1%

@

@

INVT_PWM

DISPOFF#

2

1

2

2

4 CPU_EDP_TX0+ 4 CPU_EDP_TX04 CPU_EDP_TX1+ 4 CPU_EDP_TX14 CPU_EDP_AUX 4 CPU_EDP_AUX#

1 4 PCH_EDP_PWM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

INVT_PWM

CPU_EDP_TX0+ CPU_EDP_TX0-

C19 C16

1 1

2 0.1u_0201_10V6K 2 0.1u_0201_10V6K

EDP_TX0+ EDP_TX0-

CPU_EDP_TX1+ CPU_EDP_TX1-

C17 C18

1 1

2 0.1u_0201_10V6K 2 0.1u_0201_10V6K

EDP_TX1+ EDP_TX1-

CPU_EDP_AUX C20 CPU_EDP_AUX# C21

1 1

2 0.1u_0201_10V6K 2 0.1u_0201_10V6K

EDP_AUX EDP_AUX#

1

DISPOFF# INVT_PWM R20 100K_0402_5%

+3VS

2

R21

1 EMC_NS@ C22 680P_0402_50V7K

1 2 @ 0_0402_5%

4 CPU_EDP_HPD +LCDVDD_CON

W=60mils

+3VS

2

31,43 DMIC_DATA 31,43 DMIC_CLK

9 USB20_P4 9 USB20_N4

B

Touch Screen +5VS

2

JEDP1

R18 1K_0402_5% @

2 0_0402_5%

1

C

+LEDVDD

EMI Request

@

EMC_NS@

1

470P_0201_50V7-K

0_0805_5%

@

2

2

1

@

2A 80 mil EMC@

1

@

DMIC_CLK

EMC@

1 +LEDVDD

R17

ENBKL 44

R9 100K_0402_1%

EDP_AUX EDP_AUX#

C15

2A 80 mil

EMI request

R8 100K_0402_1%

C13

0_0402_5%

+3VS

31

+3VS

1

2

C4 10U_0603_6.3V6M @

470P_0201_50V7-K

2

CMOS_ON#

EMC_NS@

@

R16 100K_0402_5%

R19

D

1

C3 0.1u_0201_10V6K CD@

C12

1

CMOS_ON#

0.1U_0201_25V6-K

ENBKL

2

100P_0201_25V8J

R297

V20B+

DISPOFF#

2 0_0402_5%

@

C

2

2

1

C10 0.1u_0201_10V6K @

C11

0_0402_5%

4.7U_0805_25V6-K

1

R14

2 0_0402_5%

@

2

1

2

1

4 PCH_ENBKL

1

R12

1

2

@

1 44 BKOFF#

2

1

2

1

2

44 EC_CMOS_ON#

R296

R10 4.7K_0402_5% @

1 2 @ 0_0402_5%

1

2

2 +3VS

R11

1

W=40mils

2 R3 1 @ 0_0603_5%

@

For EMI Close to R5

8 PCH_CMOS_ON#

PCH_ENBKL

1

2 @ R5 1 100K_0402_5%

1

4 PCH_ENVDD

3

@

2

+3VS_CMOS

1

G

2

1

C6

SY6288C20AAC_SOT23-5

@

33P_0402_50V8J

OCB

1

D

EN

0_0805_5%

3

2

2

S

2

D

2

1

JUMP_43X39

W=40 mils

C123

4

W=60mils

2

0.1u_0201_10V6K

PCH_ENVDD

C1 0.1u_0201_10V6K

@

C122

OUT GND

1

R263

4.7U_0402_6.3V6M

IN

1

1

2

U5

5

+3VS_CMOS_R

@

0.01U_0201_10V6K

5

R182 1 R183 1 +3VS_CMOS

2 0_0402_5% USB20_P4_R 2 0_0402_5% USB20_N4_R

1

C24 .047U_0201_6.3V6K EMC_NS@

W=40mils

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 G1 G2

B

DRAPH_FC5AF301-3181H ME@

2

+5VS_TS

R26

1 TS@

EMI request

2 0_0402_5% C25 0.1u_0201_10V6K TS@

JTS1

1

2

R28

44 EC_TS_ON

R23 R24

9 USB20_N6 9 USB20_P6

2 TS@ 1 TS@ 1 TS@

TS_RS

1 0_0402_5%

USB20_N6_CONN USB20_P6_CONN

2 0_0402_5% 2 0_0402_5%

1 2 3 4 5 6

1 2 3 4 5 6

GND1 GND2

7 8

For EMI

CVILU_CI1806M2HR0-NH ME@

L12 USB20_N4

1

USB20_P4

4

Touch Screen

EMC_NS@

1

2

4

3

2

USB20_N4_R

3

USB20_P4_R

EXC24CH900U_4P USB20_P6_CONN

USB20_N6

4

1

2

4

3

2

USB20_P6_CONN

3

USB20_N6_CONN

2

A

D2

1

A

EXC24CH900U_4P EMC_NS@

2

2

D1 AZC199-02S.R7G_SOT23-3 EMC_NS@

For EMI

AZ5725-01F.R7GR_DFN1006P2X2 EMC_NS@

For EMI

1

1

1

USB20_P6

3

USB20_N6_CONN +5VS_TS

L15

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

eDP/CMOS/Touch screen

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet 1

33

of

60

5

4

1

HDMI_CLK+_C

4

1

2

4

3

HDMI_CLK-_CON

2

1

3

HDMI_CLK+_CON

2

HDMI_TX0-_CON

HDMI_TX0+_C

4

1

2

4

3

3

HDMI_TX0+_CON

2

HDMI_TX1-_CON

D

5

1

+3VS EMC_NS@ 1 2 C28 3.3P_0402_50V8-C EMC_NS@ 1 2 C29 3.3P_0402_50V8-C

EMC@

L3 HDMI_TX0-_C

1

C26

EXC24CH900U_4P D

2

EMC_NS@ 2 3.3P_0402_50V8-C EMC_NS@ 1 2 C27 3.3P_0402_50V8-C

EMC@

L2 HDMI_CLK-_C

3

G

EXC24CH900U_4P

HDMI_DET

D3 1 1

10 9

HDMI_DET

HDMIDAT_R

2 2

9 8

HDMIDAT_R

HDMICLK_R

4 4

7 7

HDMICLK_R

+5VS_HDMI

5 5

6 6

+5VS_HDMI

Q1B EMC@

1

3

4 DDPB_CLK

EXC24CH900U_4P

4

EMC_NS@ 2 3.3P_0402_50V8-C EMC_NS@ 1 2 C33 3.3P_0402_50V8-C

4

HDMI_TX2-_CON

2

2

1

C32 HDMI_TX2+_CON

3

3

1

4 DDPB_DATA

3 3

HDMIDAT_R

6 D

HDMI_TX2+_C

1

2N7002KDWH_SOT363-6

S

1

HDMICLK_R

Q1A

EMC@

L5 HDMI_TX2-_C

3

G

4

HDMI_TX1+_CON

3

4

D

4

2

S

HDMI_TX1+_C

1

EMC_NS@ 2 C30 3.3P_0402_50V8-C EMC_NS@ 1 2 C31 3.3P_0402_50V8-C 1

2

L4 HDMI_TX1-_C

8

2N7002KDWH_SOT363-6 AZ1045-04F_DFN2510P10E-10-9 EMC_NS@

EXC24CH900U_4P

For EMC For EMC

C

C

+5VS

2 470_0402_5% +5VS

2

+3VS D4

2 470_0402_5%

HDMI_TX2-_C

R37

1

2 470_0402_5%

HDMI_TX2+_C

R38

1

2 470_0402_5%

@

R35 1M_0402_5%

Q12

3

1

1

2N7002KW_SOT323-3

Q13

2 G

@

3

Q22

1

C34 0.1u_0201_10V6K

2 R39 2.2K_0402_5%

R40 2.2K_0402_5%

S

JHDMI1 HDMI_DET

1

1

1

R41 20K_0402_5%

2N7002KW_SOT323-3 3

R42

2

0.5A_6V_1206L050YRHF

LP2301ALT1G_SOT23-3

BAT54S-7-F_SOT23-3

46 SUSP

D

D

S

4 HDMI_HPD +3VS

D4

1

2

2 470_0402_5%

1

2

1

R34

1

R33

HDMI_TX1+_C

2

HDMI_TX1-_C

2

2 470_0402_5% 2

1

1

R32

G

HDMI_TX0+_C

F1

1 3 RB491D_SOT23-3 @

2

2 470_0402_5%

1

2 470_0402_5%

1

1

1

R31

S

R30

HDMI_TX0-_C

+5VS_HDMI

G

HDMI_CLK+_C

+5VS_HDMI_F D5

D

1

2

R29

3

HDMI_CLK-_C

2

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

HDMIDAT_R HDMICLK_R

100K_0402_5%

HDMI_CLK-

4 HDMI_CLKB

4 HDMI_CLK+ 4 HDMI_TX04 HDMI_TX0+ 4 HDMI_TX14 HDMI_TX1+ 4 HDMI_TX24 HDMI_TX2+

1 0.1u_0201_10V6K

HDMI_CLK-_C R43 2

2 2

1 0.1u_0201_10V6K 1 0.1u_0201_10V6K

HDMI_CLK+_C R44 2 HDMI_TX0-_C R45 2

C38 C39

2 2

1 0.1u_0201_10V6K 1 0.1u_0201_10V6K

HDMI_TX1+ HDMI_TX2-

C40 C41

2 2

HDMI_TX2+

C42

2

C35

HDMI_CLK+ HDMI_TX0-

C36 C37

HDMI_TX0+ HDMI_TX1-

2

1 0_0402_5%

HDMI_CLK-_CON

@ @

1 0_0402_5% 1 0_0402_5%

HDMI_CLK+_CON HDMI_TX0-_CON

HDMI_TX0+_C R46 2 HDMI_TX1-_C R47 2

@ @

1 0_0402_5% 1 0_0402_5%

HDMI_TX0+_CON HDMI_TX1-_CON

1 0.1u_0201_10V6K 1 0.1u_0201_10V6K

HDMI_TX1+_C R48 2 HDMI_TX2-_C R49 2

@ @

1 0_0402_5% 1 0_0402_5%

HDMI_TX1+_CON HDMI_TX2-_CON

1 0.1u_0201_10V6K

HDMI_TX2+_C R50 2

@

1 0_0402_5%

HDMI_TX2+_CON

@

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND1 CK_shield GND2 CK+ GND3 D0GND4 D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

20 21 22 23

B

SINGA_2HE3Y37-000111F ME@

Close to JHDMI1

A

HDMI_CLK+_CON

D6 1 1

10 9

HDMI_CLK+_CON

HDMI_TX1-_CON

D7 1 1

HDMI_CLK-_CON HDMI_TX0+_CON

2 2

9 8

HDMI_CLK-_CON

HDMI_TX1+_CON

4 4

7 7

HDMI_TX0+_CON

HDMI_TX2-_CON

HDMI_TX0-_CON

5 5

6 6

HDMI_TX0-_CON

HDMI_TX2+_CON

10 9

HDMI_TX1-_CON

2 2

9 8

HDMI_TX1+_CON

4 4

7 7

HDMI_TX2-_CON

5 5

6 6

HDMI_TX2+_CON

3 3

3 3

8

8

AZ1045-04F_DFN2510P10E-10-9 EMC_NS@

For EMC

AZ1045-04F_DFN2510P10E-10-9 EMC_NS@

A

Issued Date

WWW.AliSaler.Com 5

Title

LC Future Center Secret Data

Security Classification

2015/08/20

HDMI_CONN

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet 1

34

of

60

5

4

3

2

1

+IVDDO +3VS

LVG2 RVG16 1

+RX_AVCC

+DP_3V3

@

1

2 0_0402_5%

@

2 0_0603_5% 1 1 2

CVG15 0.1u_0201_10V6K

2

CVG3 CVG2

1 1

2 2

0.1u_0201_10V6K 0.1u_0201_10V6K

DRX0P DRX0N

18 19

CVG4 CVG5

1 1

2 2

0.1u_0201_10V6K 0.1u_0201_10V6K

DRX1P DRX1N

20 21

23

9 16 30 31 IVDD1 IVDD2 IVDD3 IVDD4

HPD

IVDDO

26

IVDD33

DP_VGA_HPD

25

D

4 DP_VGA_HPD

4 VGA_TX1+ 4 VGA_TX1-

+IVDDO +RX_IVDD

2

UVG1

4 VGA_TX0+ 4 VGA_TX0-

+DP_3V3

8 32

D

+DP_3V3

OVDD1 OVDD2

CVG8 10U_0603_6.3V6M

1

CVG10 10U_0603_6.3V6M

+IVDDO

RX0P RX0N

NC

27

1

TVG1

+RX_IVDD

RVG19 1

@

2 0_0603_5%

@

1

RX1P RX1N

CVG16 0.1u_0201_10V6K

2

4 VGA_AUX 4 VGA_AUX#

CVG6 CVG7

1 1

2 2

0.1u_0201_10V6K 0.1u_0201_10V6K

15 14

AUXP AUXN

ISPSCL ISPSDA RXAUXP RXAUXN

VGADDCCLK VGADDCSDA VSYNC HSYNC

10 11 13 12 1 2

CRT_DDC_CLK CRT_DDC_DAT VGA_VS VGA_HS

36 36 +IVDDO

VGA_VS 36 VGA_HS 36

LVG4

+DAC_VDDC

+DAC_VDDC

1

2 0_0402_5%

@

+RX_AVCC C

17 22

AVCC ASPVCC

IT6516BFN

VDDAC

IORP @ @

TVG3 TVG4

1 1

29 28

PCSDA PCSCL

IOGP IOBP

RSET TVG2

1

24

CVG17 0.1u_0201_10V6K

7

CRT_R

6

CRT_G

5

CRT_B

3

RVG3 1

CRT_R

1

1

2

2

C

CVG11 4.7U_0402_6.3V6M

36

CRT_G 36 CRT_B 36

2 200_0402_1%

RVG3 closed to pin3 URDBG

GND

@

4

CRT_R

33

IT6516BFN-BX-0061_QFN32_4X4 B

B

CRT_G

2

2

RVG25 75_0402_1%

1 RVG26 75_0402_1%

RVG27 75_0402_1%

2

1

1

CRT_B

CLOSE TO UVG1

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

DP to VGA (IT6516BFN)

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet 1

35

of

60

4

3

2

+CRT_VCC_CON

1

2 1

CRT Connector +CRT_VCC_CON

RPVG3 2.2K_0404_4P2R_5%

+CRT_VCC

RVG4 1

2 22_0402_5%

CRT_DDC_DAT_R

CRT_DDC_CLK

RVG5 1

2 22_0402_5%

CRT_DDC_CLK_R

RVG39 1

@ 2 1

1

+CRT_VCC_CON

2 @

3

35 CRT_DDC_CLK

RB491D_SOT23-3 1

1

2

2

0.5A_6V_1206L050YRHF

W=40mils

CVG44 68P_0201_50V8-J @

1

D

CVG34 0.1u_0201_10V6K CD@

2

DVG2 AZ5725-01F.R7GR_DFN1006P2X2 EMC_NS@

2

2

CVG43 100P_0201_25V8J @

2 0_0603_5%

FVG1

1

CRT_DDC_DAT

@

DVG1

3 4 35 CRT_DDC_DAT D

+5VS_HDMI

+5VS

1

5

JCRT1

35 CRT_R

2 EMC@ LVG6 1 BLM15BA220SN1D_2P

35 CRT_G

2 EMC@ LVG7 1 BLM15BA220SN1D_2P

35 CRT_B

2 EMC@ LVG8 1 BLM15BA220SN1D_2P

6 11 1 7 12 2 8 13 3 9 14 4 10 15 5

CRT_R_CON CRT_DDC_DAT_R CRT_G_CON HSYNC_CON CRT_B_CON VSYNC_CON

EMC@

EMC@

2

EMC@

1

2

CVG40 15P_0402_50V8J

EMC@

2

1

CVG39 15P_0402_50V8J

EMC@

2

1

CVG38 15P_0402_50V8J

2

1

CVG37 15P_0402_50V8J

1

CVG36 15P_0402_50V8J

2

CVG35 15P_0402_50V8J

1

CRT_DDC_CLK_R

CVG41 100P_0201_25V8J @

EMC@

1

For EMC

G G

16 17

SUYIN_070546HR015M25KZR ME@

2

C

C

VGA_HS

35 VGA_HS

RVG32 1

@

HSYNC_CON

2 0_0402_5%

1

2

VGA_VS

35 VGA_VS

RVG33 1

@

CVG42 10P_0201_50V8F

VSYNC_CON

2 0_0402_5% 1

2

CVG45 10P_0201_50V8F

B

A

B

CRT_B_CON

DVG3 1 1

10 9

CRT_B_CON

VSYNC_CON

DVG4 1 1

10 9

VSYNC_CON

CRT_G_CON

2 2

9 8

CRT_G_CON

HSYNC_CON

2 2

9 8

HSYNC_CON

CRT_R_CON

4 4

7 7

CRT_R_CON

CRT_DDC_CLK_R

4 4

7 7

CRT_DDC_CLK_R

5 5

6 6

CRT_DDC_DAT_R

5 5

6 6

CRT_DDC_DAT_R

3 3

3 3

8

8

AZ1045-04F_DFN2510P10E-10-9 EMC_NS@

For EMC

AZ1045-04F_DFN2510P10E-10-9 EMC_NS@

A

Issued Date

WWW.AliSaler.Com 5

Title

LC Future Center Secret Data

Security Classification

2015/08/20

CRT_CONN

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet 1

36

of

60

5

4

3

2

1

+3VALW  TO  +3VALW_LAN +3VALW

Need  short 1

JL1

1

+3VALW_LAN  rising  t i me ( 10 %~90 %):  0.5ms＜ s pec＜ 10 0m s

+3VALW_LAN

+LAN_VDDREG RL1

width : 40 mils

2 @

2

+3VALW_LAN

1

1

2

2 @

@

2 @

1

2 @

CL6

1

2

CL7

1

2

Close to Pin11 Close to Pin32 Close to Pin11

1

0.1u_0201_10V6K

CL9

CL5

0.1u_0201_10V6K

1 CL8

1

0.01U_0201_10V6K

1 @

2

0.1u_0201_10V6K

1 2 44 LAN_PWR_ON#

D

1 2 @ 47K_0402_5%

RL3

3

G

RL2 100K_0402_5% @

S

Q14

CL4

4.7U_0402_6.3V6M

LP2301ALT1G_SOT23-3

4.7U_0402_6.3V6M

+3VALW

2 0_0603_5%

JUMP_43X79

D

@

2

CL1 4.7U_0402_6.3V6M @

1

2

D

CL2 0.1u_0201_10V6K CD@

Close to Pin32 +3VALW_LAN

+3VS

2

+3VALW_LAN

UL1

2 G

1

1 RL7 1 RL6 1

11,40,44 PCIE_WAKE# 40,44 LAN_WAKE#

@ @

2 0_0402_5% 2 0_0402_5%

+3VS 1

LAN_PWR_ON#

2

RL9 1K_0402_1%

2

@

11,20,32,40,44 PLT_RST# 9 PCIE_PRX_DTX_N5 9 PCIE_PRX_DTX_P5

LAN_PWR_ON#

0_0402_5%

1

LAN_CLKREQ#

10

PCIE_WAKE#_R 33 32 31 30 29 28 27 TL3 @ 1 @ LAN_DISABLE# 26 2 RL121 25 0_0402_5% TL4 @ 1 +LAN_REGOUT 24 +LAN_VDDREG 23 +LAN_VDD10 22 PCIE_WAKE#_R 21 20 ISOLATE# PLT_RST# 19 2 0.1u_0201_10V6K PCIE_PRX_C_DTX_N5 18 CL10 1 2 0.1u_0201_10V6K PCIE_PRX_C_DTX_P5 17 CL11 1 RL8

RL10 1

@

2N7002KW_SOT323-3

C

ISOLATE#

3

D

LAN_CLKREQ#_R

QL1

S

manual change the Codec PN to RTL8111GUL-CG

RL5 10K_0402_5% @

1

2

@ RL4 10K_0402_5%

1 2 2.49K_0402_1%

+3VALW_LAN RSET +LAN_VDD10 LAN_XTALO LAN_XTALI

RL18 1

GND AVDD33_2 RSET AVDD10 CKXTAL2 CKXTAL1 LED0 LED1/GPIO LED2 REGOUT VDDREG DVDD10 LANWAKEB ISOLATEB PERSTB HSON HSOP

REFCLK_N REFCLK_P HSIN HSIP CLKREQB AVDD33_1 MDIN3 MDIP3 AVDD10_2 MDIN2 MDIP2 MDIN1 MDIP1 AVDD10_1 MDIN0 MDIP0

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

CLK_PCIE_LAN# CLK_PCIE_LAN PCIE_PTX_C_DRX_N5 PCIE_PTX_C_DRX_P5 LAN_CLKREQ#_R +3VALW_LAN LAN_MDI3LAN_MDI3+ +LAN_VDD10 LAN_MDI2LAN_MDI2+ LAN_MDI1LAN_MDI1+ +LAN_VDD10 LAN_MDI0LAN_MDI0+

@

2 0_0402_5% C

CLK_PCIE_LAN# 10 CLK_PCIE_LAN 10 PCIE_PTX_C_DRX_N5 9 PCIE_PTX_C_DRX_P5 9 LAN_MDI3- 38 LAN_MDI3+ 38 LAN_MDI2LAN_MDI2+ LAN_MDI1LAN_MDI1+

38 38 38 38

LAN_MDI0- 38 LAN_MDI0+ 38

CL10 close to Pin18 CL11 close to Pin17

2

RL11 15K_0402_5% @

RTL8111GUL-CG QFN 32P 8111GUL@

B

B

LAN_XTALI LAN_XTALO_R 1 2 RL21 1K_0402_5%

For  RTL8111GUL(SWR  mode,  reserved) For RTL8111H (LDO mode)

LAN_XTALO

+LAN_VDD10

YL1 1 2 1

CL12 12P_0402_50V8-J

2

LL1

OSC1

GND2

GND1

OSC2

1 2 8111GUL@ 2.2UH_NLC252018T-2R2J-N_5%

4 +LAN_REGOUT 3

25MHZ_10PF_7V25000014

RL20

1

2 0_0805_5%

8111H@ 1

1

CL13 15P_0402_50V8J

CL15 4.7U_0402_6.3V6M

2

1

2

1 CL16 0.1u_0201_10V6K

2

1

CL17 0.1u_0201_10V6K 2 CD@

2

1 CL18 0.1u_0201_10V6K

2

1 CL19 0.1u_0201_10V6K

2

1 CL20 0.1u_0201_10V6K

Close to Pin3, 8, 22, 30

2

1 CL21 1U_0402_6.3V6K

2

CL22 0.1u_0201_10V6K

Close  to  Pin22(Reserved)

Layout Note: LL1 must be within  200mil  to  Pin24, CL15,CL16 must  be  within 200mil  to  LL1 +LAN_REGOUT: Width =60mil A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

LAN_RTL8111H_CG

2016/08/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom

Date: 5

4

3

2

Rev 1.0

CG411

Thursday, January 14, 2016

Sheet 1

37

of

60

5

4

3

2

1

DL1/DL2 1'S PN:SC300003M00 TL1

2 3

LAN_MDI3+

4

LAN_MDI3-

5 11 12

LINE1OUT

LINE2IN

LINE2OUT

GND1

GND2

LINE3IN

LINE3OUT

LINE4IN

LINE4OUT

GND3

GND5

10

LAN_MDI2+

9

LAN_MDI2-

37 LAN_MDI0-

37 LAN_MDI1+ LAN_MDI3+

6

LAN_MDI3-

22 21

8 7

LAN_MDI0-

37 LAN_MDI1-

LAN_MDI1+

20

LAN_MDI1-

19 18

13

37 LAN_MDI2+ 37 LAN_MDI2-

GND4

LAN_MDI2+

17

LAN_MDI2-

16 15

AZ3133-08F.R7G_DFN3020P10E10 EMC_NS@ 37 LAN_MDI3+

C

1

DL2 LAN_MDI1-

1

LAN_MDI1+

2 3

LAN_MDI0-

4

LAN_MDI0+

5 11 12

LINE1IN

LINE1OUT

LINE2IN

LINE2OUT

GND1 LINE3IN LINE4IN

GND2 LINE3OUT LINE4OUT

GND3

GND5

10

LAN_MDI1-

9

LAN_MDI1+

2

8

37 LAN_MDI3-

LAN_MDI3+

14

LAN_MDI3-

13

CL24 0.01U_0201_25V6-K EMC@

TD1+

MX1-

TD1-

MCT2

TCT2

MX2+

TD2+

MX2-

TD2-

MCT3

TCT3

MX3+

TD3+

MX3-

TD3-

MCT4

TCT4

MX4+

TD4+

MX4-

TD4-

2

LAN_MDO0+

3

LAN_MDO0-

4

MCT

5

LAN_MDO1+

6

LAN_MDO1-

7

MCT

D

8

LAN_MDO2+

9

LAN_MDO2-

10

MCT

11

LAN_MDO3+

12

LAN_MDO3-

EMC@ RL17 20_0603_5%

1

LAN_MDI2-

LINE1IN

MX1+

MCT

1

1

23

1

2

DL1 LAN_MDI2+

LAN_MDI0+

TCT1

DL3 PDT5061_DO-214AA EMC@

EMC

2

37 LAN_MDI0+

MCT1

1

D

2

24

CL32 0.022U_0603_50V7K EMC@

1

1

2

2

CL25 1000P_1206_2KV7-K EMC@

EMC C

BOTH_GST5009 LF

EMC

7

LAN_MDI0-

6

LAN_MDI0+

CHASSIS1_GND

13

GND4 AZ3133-08F.R7G_DFN3020P10E10 EMC_NS@ JRJ1

ME@

GND_4

Place Close to TL1

GND_3

EMC B

LAN_MDO0+

1

LAN_MDO0-

2

LAN_MDO1+

3

LAN_MDO2+

4

LAN_MDO2-

5

RL14 1

@

2 0_0603_5%

LAN_MDO1-

6

RL15 1

@

2 0_0603_5%

LAN_MDO3+

7

RL16 1

@

2 0_0603_5%

LAN_MDO3-

8

EMC

GND_2 PR1+ GND_1

12 11 10 9

B

PR1PR2+

CHASSIS1_GND

PR3+ PR3PR2PR4+ PR4SANTA_130460-3

CHASSIS1_GND

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification

2015/08/20

Deciphered Date

LAN_Transformer

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size B

Date: 5

WWW.AliSaler.Com

4

3

2

Document Number

Rev 1.0

CG411 Thursday, January 14, 2016

Sheet 1

38

of

60

@

2 0_0402_5%

REMOTE1+

R176 1

@

2 0_0402_5%

REMOTE2+

REMOTE-_R

2

R177 1

REMOTE-_R

R178 1

@ @

2 0_0402_5% 2 0_0402_5%

C45 100P_0201_25V8J @

REMOTE2REMOTE1-

1 2 B

2

E

3

1

REMOTE1-

C46 100P_0201_25V8J @

C

Q15 MMBT3904WH_SOT323-3 @

Near CPU core

1 2

E

REMOTE2-

+3VALW

REMOTE-_R

3

2 1 @ 10K_0402_5%

4

1

SDA

D-

ALERT#

T_CRIT#

2 1

1 2 EC_SMB_DA2

EC_SMB_CK2 7,20,44

R184 0_0402_5% OPT@

EC_SMB_DA2 7,20,44

6 5

GND

2

EC_SMB_CK2

2

8 7

2

@

SCL

D+

R288 100K_0402_1%_NCP15WF104F03RC

R185 0_0402_5% @

1

C47 0.1u_0201_10V6K @ 2 R51 +3VS

2

NTC_V2

1

1

REMOTE+_R

R25 13.7K_0402_1%

R287 100K_0402_1%_NCP15WF104F03RC OPT@

+3VS

VDD

D

Near CPU

2

NTC_V1

SMSC thermal sensor placed near DIMM U1

Q16 MMBT3904WH_SOT323-3 @

B

2

R36 13.7K_0402_1%

1

C

+3VALW

REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: Trace width/space:10/10 mil Trace length: