• Author / Uploaded
• Claudiu Petrache

• Categories
• Protocolos de capa física
• Redes sociales y digitales
• Tecnología digital
• Hardware de la computadora
• Electrónica

Citation preview

A

B

C

D

E

COMPAL CONFIDENTIAL MODEL NAME : HAL00 PCB NO : LA-2791 COMPAL P/N : 45135631L01

1

1

Travis (UMA) Schematics Document

2

2

uFCPGA Mobile Yonah Intel Calistoga + ICH7M

2006-01-20 REV : 1.0 (DELL: A00) 3

3

4

4

DELL CONFIDENTIAL/PROPRIETARY MB PCB Part Number DAA0000040L

Compal Electronics, Inc.

Description PCB ZJX LA-2791 REV0 M/B UMA

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

BOM NO. 45135631L01 PCB P/N: DA800002L1L

A

B

C

D

Title

Cover Sheet Size

Document Number

Date:

Tuesday, February 07, 2006

Rev 0.6

LA-2791 Sheet E

1

of

63

A

B

C

D

E

Compal confidential

Block Diagram

Model : HAL00 FAN 1

Pentium-M Yonah-2M uFCPGA CPU

Thermal GUARDIAN II EMC4000

FAN1_VOUT page 18

+3.3V_SUS

+VCC_CORE

page 20

RGB

page 19

+3.3V_RUN

page6

H_D#(0..63)

INTEL Calistoga

+1.5V_RUN

LVDS

+1.8V_SUS

DVI

+1.05V_VCCP page 7

page 7,8,9

System Bus

LVDS CONN on M/B Board

1

FSB 533/667 MHz

CRT CONN +5V_RUN

Clock Generator SLG84450VTR

478pin

H_A#(3..31)

RGB

CPU ITP Port

+1.05V_VCCP (1.05V)

page 18

DVI Bridge SI1362 page

DVO

Memory BUS (DDR2) +1.8V_SUS

DDRII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

533 / 667MHz

page 16,17 +0.9V_DDR_VTT

1466pin BGA

+1.8V_SUS

+1.05V_VCCP (1.05V)

19

+3.3V_RUN

TV

+2.5V_RUN

HUB USB[3]

page 10,11,12,13,14,15

Smart Card OZ77C6

SLOT

USB Ports X2

USB4 on right side of connector, USB6 on left side

+3.3V_RUN page 31

DMI

2

PCI BUS

USB[5,6]

+3.3V_RUN 33MHz

+5V_SUS 48MHz

DOCKING PORT PAGE 36

DOCKING BUFFER +5VRUN PAGE 35

CardBus OZ601 TQFP +3VRUN

USB[7] +3.3V_RUN/ +1.5V_RUN 100MHz

+3.3V_RUN +3.3V_SUS +1.5V_RUN

PCI Express BUS

+3.3V_RUN +1.5VRUN page 34

Mini Card 1 WWAN

+3.3V_RUN +1.5VRUN page 34

GIGA Enthernet BCM5752

+3VRUN 33MHz

VCORE (IMVP-6)

page 47

CHARGER 4

SMSC SIO ECE5018 +3VALW

BATT SELECT

3V/5V/15V

page 51

page 38

Power Sequence

S-HDD

HUB USB[2]

D Moudle

+5VHDD

HUB USB[3]

+5VMOD page 25

page 25

page 46

+3.3V_RUN +VDDA

page 26

RJ11

IO/B

SPI +RTC_CELL

+3.3V_ALW page 39

AMP & INT. Speaker

COM page 43

3

Azalia Codec STAC9200

MEC5004

+3.3V_RUN page 33

INT MIC +5V_SUS

+5V_SUS page 27

page 37

Power On/Off SW & LED page 45

M DC Cable

HUB USB[1]

Bluetooth

page 44

BATT IN

page 50

USB[2]

LPC BUS

page 42

DC IN

page 49

SATA

SPI

+3.3V_SUS page 33

HUB USB[4]

1.5V/1.05V

page 48

USB0 on the top of connector, USB2 on the bottom

ATA100

USB[1]

IO/B

1.8V/0.9V

IO/B

Azalia I/F

page 28,29

RJ45

page 32

USB Ports X2

+3VLAN

HUB USB[2]

Int.KBD & Stick page

FIR

HeadPhone & MIC Jack +3.3V_RUNpage 27

ST M25P80

+3.3V_ALW page 39 40 4

+3.3V_RUN page 37

Stick

DC/DC Interface

Touch Pad +5V_RUN

page 41

DELL CONFIDENTIAL/PROPRIETARY

page 33

Compal Electronics, Inc. Title

Block Diagram Size

Document Number

Date:

Tuesday, February 07, 2006

Rev 0.6

LA-2791 A

B

2

+1.05V_VCCP

3

USB[0]

SIDE

+5V_SUS

page 21,22,23,24

Mini Card2 WLAN

USB[3,4]

INTEL ICH7-M 652pin BGA

IDSEL:AD17 (PIRQC,D#,GNT#1,REQ#1)

page 30

HUB USB[1]

REAR

+1.5V_RUN 100MHz

C

D

Sheet E

2

of

63

5

4

3

2

PCI TABLE

Ceramic Capacitors :

PCI DEVICE

0.1U_0402_6.3VXX Tolerance Temperature Characteristics Rated Voltage

D

1

CARD BUS

IDSEL

REQ#/GNT#

PIRQ

AD17

1

C

D

Package Size Value PM TABLE +5V_RUN +3.3V_SRC

Tantalum or Polymer Capacitors :

power plane

+3.3V_RUN

+15V_SUS

+3.3V_RUN_R

+5V_ALW

+5V_SUS

+1.8V_RUN

+3.3V_ALW

+3.3V_SUS

+0.9V_DDR_VTT

+1.8V_SUS

+1.5V_RUN

10U_D2_10VX_R45

+VCC_CORE

State

+1.05V_VCCP

Low ESR Mark : 45 m ohm

C

Tolerance

S0

ON

ON

ON

Rated Voltage

S1

ON

ON

ON

Package Size

S3

ON

ON

OFF

Value

S5 S4/AC

ON

OFF

OFF

S5 S4/AC don't exist

OFF

OFF

OFF

USB

Capacitor Spec Guide:

C

+2.5V_RUN

TABLE

Temperature Characteristics: B

Symbol

3

4

5

6

7

Z5P

Y5U

Y5V

Y5P

X5R

X7R

A

B

C

D

E

F

G

X6S

BJ

CH

CJ

CK

SH

SJ

0

1

Z5U

Z5V

8

9

NPO

COG

CODE

H

I

J

K

UJ

UK

SL

X5S

Tolerance: Symbol A CODE

A

2

K +-10%

B

C

D

+-0.05PF +-0.1PF +-0.25PF +-0.5PF N

M +-20%

+-30%

P

Q

F

G

+-1PF

+-2%

+-3%

V

X

Z

H

+100,-0% +30,-10% +20,-10% +40,-20% +80,-20%

DESTINATION

USB HUB

DESTINATION

0

Mini 2(WLAN)

1

PC Card Bay

1

USB Hub (5018)

2

Mini 1(WWAN)

2

D Moudle

3

Smart Card --> BIO

3,4

SIDE

4

Blue tooth

5,6

REAR

7

Docking

USB PORT#

J +-5%

B

A

NOTE1: @XX :

DELL CONFIDENTIAL/PROPRIETARY

Depop component

Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Index and Config. Size

Document Number

Date:

Tuesday, February 07, 2006

Rev 0.6

LA-2791 Sheet 1

3

of

63

5

4

3

2

1

D

D

ADAPTER RUN_ON

+PWR_SRC

FDS4435

+INV_PWR_SRC

BATTERY

ALWON

MAX8734 C

ISL6260

ISL6227

MAX88550 C

+5V_SATA

+VDDA

+5V_RUN

+15V_SUS

+3.3V_RUN

SI4800

+3VLAN

+3.3V_SUS

+1.8V_SUS +0.9V_DDR_VTT

RUN_ON

SI3456

SI4800

+3.3V_RUN_R

RUN_ON

SUSPWROK_5V

RUNPWROK

RUNPWROK

+VCC_CORE +1.5V_RUN +1.05V_VCCP

RUN_ON

SI4800

ENAB_3VLAN

PL8

RUN_ON

793475

(Option)

SI3456

+3.3V_SRC AUDIO_AVDD_ON

RUN_ON MODC_EN#

HDDC_EN#

SI3456

RUNPWROK

SUS_ON

SUS_ON

+3.3V_ALW

+5V_SUS

B

+5V_ALW

ALWON

B

SI3456

+1.8V_RUN

SI3456 L47

EMC4000

MOD (+5VRUN) A

A

DELL CONFIDENTIAL/PROPRIETARY

+2.5V_RUN

Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Power Rail Size

Document Number

Date:

Tuesday, February 07, 2006

Rev 0.6

LA-2791 Sheet 1

4

of

63

5

4

3

2

1

+3.3V_SUS 2.2K

D

ICH7-M

C22

ICH_SMBCLK

B22

ICH_SMBDATA

+3.3V_RUN

2.2K

2N7002 2N7002 30

C7

+3.3V_ALW

10K

10K

C8

32

5752M LOM

WWAN

5

2.2K

CLK_SCLK

16

+3.3V_SUS

32

6

2.2K

SMBUS Address [TBD]

CLK_SDATA

30

SMBUS Address [D2]

WLAN

SMBUS Address [C8]

197

DIMM0

SMBUS Address [TBD]

195

CLK_SMB

SMBUS Address [A0]

8

DAT_SMB

17

D

CLK GEN.

+3.3V_ALW

GUARDIAN

7

197

SMBUS Address [2F]

195

+3.3V_ALW

DIMM1

SMBUS Address [A2] C

8.2K 10

DOCK_SMB_CLK

9

DOCK_SMB_DAT

39

+3.3V_ALW

SIO

40

+3.3V_ALW 4.7K

Macallan IV

C

8.2K

112

SBAT_SMBCLK

111

SBAT_SMBDAT

100

4.7K

3 4

100

+3.3V_ALW

DOCKING

SMBUS Address [C4, 72, 70, 48]

2'nd BATTERY

SMBUS Address [16]

6

INV

5

Inverter SMBUS Address [58]

B

B

+3.3V_ALW 8.2K 8

PBAT_SMBCLK

7

PBAT_SMBDAT

8.2K 100

3 4

BATTERY CONN

SMBUS Address [16]

10

CHARGER

SMBUS Address [12]

+3.3V_ALW 100

9

A

A

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

SMBUS TOPOLOGY Size

Document Number

Date:

Tuesday, February 07, 2006

Rev 0.6

LA-2791 Sheet 1

5

of

63

5

4

3

+3.3V_RUN

D 3

S

D

ICH_SMBDATA

23,28,34 ICH_SMBDATA

S

2N7002 1

3

1

2

C402 10U_0805_10V4Z~D 2

1 C384 0.1U_0402_16V4Z~D 2

1 C58 0.1U_0402_16V4Z~D 2

1 C64 0.1U_0402_16V4Z~D 2

CLK_SDATA

1

L32 BLM21PG600SN1D_0805~D

2 G

1

1

2

C308 10U_0805_10V4Z~D 2

C330 0.1U_0402_16V4Z~D

0

266

PCI MHz

100

33.3

0

0

1

133

100

33.3

0

1

0

200

100

33.3

0

1

1

166

100

33.3

1

0

0

333

100

33.3

1

1

0

1

1

0

1

1

1

100 400

2

2

+CK_VDD_48 1

Place crystal within 500 mils of CK410

33.3

100

R274 1_0603_5%~D 1 2 +CK_VDD_REF 1

2

+CK_VDD_48

R273 2.2_0603_5%~D CLK_XTAL_IN

C333 27P_0402_50V8J~D 2 1

R32 470_0402_5%~D 1 2

CLK_ICH_48M

23 CLK_ICH_48M

CLK_SMC_48M CLK_PCI_5004

39 CLK_PCI_5004

CLK_PCI_LOM

28 CLK_PCI_LOM

0

CLK_PCI_PCM

30 CLK_PCI_PCM

0

CLK_DOCKPCI_33M

36 CLK_DOCKPCI_33M

1

2 R1619 2 R1438 2 R331 2 R302 2 R294

CLK_PCI_5018

38 CLK_PCI_5018

0

2 R298 1 R1589

VDDSRC VDDSRC VDDSRC VDDSRC

30 36

VDDPCI VDDPCI

12

VDDCPU

18

VDDREF

40 20

CLK_XTAL_OUT

1 12.1_0402_1%~D 2 12.1_0402_1%~D

10 DREFCLK 10 DREFCLK#

1 12.1_0402_1%~D 1 12.1_0402_1%~D 1 33_0402_5%~D 1 33_0402_5%~D 1 33_0402_5%~D

CLK_PCI_ICH CLK_ENABLE#

21 CLK_PCI_ICH 49 CLK_ENABLE#

1 R362

X2

41

USB_48MHz/FSLA

FSB

45

FSLB/TEST_MODE

FSC

23

REF0/FSLC/TEST_SEL

FCTSEL1

34

PCICLK4/FCTSEL1

PCI_LOM

33

PCI_PCM DOCKPCI_33M

2 CLKIREF 475_0402_1%~D

FSC

8

2

1

1

2

R330 0_0402_5%~D

CPU_BSEL2

FSB

MCH_CLKSEL2 10 8

1

2

2

FCTSEL1

PIN47

PIN48

96/100M_T

96/100M_C

MCH_BCLK

10

MCH_BCLK#

CPUT0

14

CPU_BCLK

CPUC0

13

0

DOT96T DOT96C

1 27M_out 27M SSout

SRCT0

SRCC0

1 R321 CPU_BCLK# 1 R337

CLK_CPU_BCLK 2 33_0402_5%~D CLK_CPU_BCLK# 2 33_0402_5%~D CLK_CPU_ITP 2 33_0402_5%~D CLK_CPU_ITP# 2 33_0402_5%~D

6

CPU_ITP

5

CPU_ITP#

SRCT9

3

SRCC9

2

1 R368 1 R376

PCIE_SATA

PCICLK2

SRCC8

69

PCIE_SATA#

27

PCICLK1

CLKREQ8#

71

SRCT7

66

SRCC7

67

22

REF1

43

DOTT_96MHz/27MHz

44

DOTC_96MHz/27MHz(SS)

37

ITP_EN/PCICLK_F0

39

Vtt_PwrGd#/PD

CLKREQ7#

38

SRCT6

63

PCIE_ICH

SRCC6

64

PCIE_ICH#

CLKREQ6#

62

SRCT5

60

SRCC5

61

IREF CLKREQ5#

29

SRCT4

58

SRCC4

59

SMBCLK CLKREQ4#

57

SRCT3

55 56

SMBDAT

1 R366 1 R375 1 R1761

@ 1 R397 MCH_3GPLL# 1 R402 MCH_3GPLL

SRCC3 CLKREQ3#

28

21

GNDREF

SRCT2

52

PCIE_MINI2

31

GNDPCI

SRCC2

53

PCIE_MINI2#

35

GNDPCI

CLKREQ2#

26

42

GND48

SRCT1

50

68

GNDSRC

SRCC1

51

CLKREQ1#

46

LCD100/96/SRC0_T

47

LCD100/96/SRC0_C

48

THRM_PAD THRM_PAD THRM_PAD THRM_PAD

4

CLK_CPU_ITP# 7

CLK_PCIE_SATA 22 CLK_PCIE_SATA# 22 SATA_CLKREQ# 23 +3.3V_RUN

B

CLK_PCIE_MINI2 34 CLK_PCIE_MINI2# 34

R1395 1 PCIE_MINI1 1 R1638 PCIE_MINI1# 1 R1639

MINI2CLK_REQ# 34 2 10K_0402_5%~D +3.3V_RUN CLK_PCIE_MINI1 2 CLK_PCIE_MINI1 34 33_0402_5%~D CLK_PCIE_MINI1# 2 CLK_PCIE_MINI1# 34 33_0402_5%~D

1 DOT96_SSC R1640 1 R524 DOT96_SSC# 1 R525

2 10K_0402_5%~D 2 33_0402_5%~D 2 33_0402_5%~D

MINI1CLK_REQ# 34 +3.3V_RUN DREF_SSCLK 10

A

DREF_SSCLK# 10

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

CLK_CPU_ITP 7

CLK_PCIE_MINI2 2 33_0402_5%~D CLK_PCIE_MINI2# 2 33_0402_5%~D

1 R1393 1 R1394

SLG84450VTR_QFN72~D

Solder Thermal Pad to GND. Add min. 4 vias.

CLK_CPU_BCLK# 7

CLK_3GPLLREQ# 10 2 10K_0402_5%~D +3.3V_RUN CLK_PCIE_LOM 2 CLK_PCIE_LOM 28 33_0402_5%~D CLK_PCIE_LOM# 2 CLK_PCIE_LOM# 28 33_0402_5%~D LOM_CLKREQ# 28 2 +3.3V_RUN 10K_0402_5%~D

1 R1762

GNDCPU

3

2

D

C

CLK_CPU_BCLK 7

CLK_PCIE_ICH 2 CLK_PCIE_ICH 23 33_0402_5%~D CLK_PCIE_ICH# 2 CLK_PCIE_ICH# 23 33_0402_5%~D 2 +3.3V_RUN 10K_0402_5%~D CLK_MCH_3GPLL 2 CLK_MCH_3GPLL 10 33_0402_5%~D CLK_MCH_3GPLL# 2 CLK_MCH_3GPLL# 10 33_0402_5%~D

R299 1 1 R1435 PCIE_LOM# 1 R1436

GNDSRC

1 49.9_0402_1%~D 1 49.9_0402_1%~D 1 49.9_0402_1%~D 1 49.9_0402_1%~D 1 49.9_0402_1%~D 1 49.9_0402_1%~D 2 49.9_0402_1%~D 2 49.9_0402_1%~D 2 49.9_0402_1%~D 2 49.9_0402_1%~D 2 49.9_0402_1%~D 2 49.9_0402_1%~D 2 49.9_0402_1%~D 2 49.9_0402_1%~D 2 49.9_0402_1%~D 2 49.9_0402_1%~D 2 49.9_0402_1%~D 2 49.9_0402_1%~D 2 49.9_0402_1%~D 2 49.9_0402_1%~D 2 49.9_0402_1%~D 2 49.9_0402_1%~D

CLK_MCH_BCLK# 10

2 10K_0402_5%~D

PCIE_LOM

4

CLK_MCH_BCLK 10

CLK_PCIE_SATA 2 33_0402_5%~D CLK_PCIE_SATA# 2 33_0402_5%~D

1 R394 1 R400 R292 1

15

73 74 75 76

@ R278 10K_0402_5%~D

CLK_MCH_BCLK 2 33_0402_5%~D CLK_MCH_BCLK# 2 33_0402_5%~D

CPUT_ITP/SRCT10

23

H_STP_CPU# 23

1 R348 1 R359

CPUC_ITP/SRCC10

2

PIN44

11

H_STP_PCI#

2

A

FSA

*

1

1

R271 10K_0402_5%~D

PIN43

CPUT1 CPUC1

32

17

R291 10K_0402_5%~D

H_STP_CPU#

72

CLK_SDATA

1

+3.3V_RUN

H_STP_PCI#

24

70

16

FCTSEL1

25

CPU_STOP#

SRCT8

CLK_SCLK

R354 0_0402_5%~D

CPU_BSEL1

PCI_SRC_STOP#

PCICLK3

9

MCH_CLKSEL1 10

7 8

CLKREQ9#

R531 8.2K_0402_5%~D

VDDA GNDA

X1

19

CLKREF 2 2 12.1_0402_1%~D 12.1_0402_1%~D DOT96 2 33_0402_5%~D DOT96# 2 33_0402_5%~D R316 R1582 1 2 +3.3V_RUN 33_0402_5%~D 10K_0402_5%~D PCI_ICH 2 1

B

Place near CK410+

VDD48

FSA

CLK_ICH_14M 1 CLK_SIO_14M R266 1 R250 DREFCLK 1 R345 DREFCLK# 1 R356

23 CLK_ICH_14M 38 CLK_SIO_14M

+CK_VDD_A

U16

1 49 54 65

Reserve

CPU_BSEL2(FSC) CPU_BSEL1(FSB)

166

2

C329 X2 27P_0402_50V8J~D 14.31818MHz_20P_1BX14318CC1A~D 2 1

31 CLK_SMC_48M

133

2

1

NOTE: Place Decoupling as close as physically possilble to the VDD pins

Table : ICS954305AK

CPU_BSEL

2

33.3

100

R401 2.2_0603_5%~D 1 2

+CK_VDD_REF 1

C52 0.047U_0402_16V4Z~D

CLKSEL0

0

SRC MHz

1

1

CLKSEL1

0

C

FSA

1

Place near each pin W>40 mil

2

CLKSEL2

CPU MHz

*

FSB

+CK_VDD_A C68 4.7U_0603_6.3V4Z~D

FSC

C70 0.1U_0402_16V4Z~D

1 C344 0.1U_0402_16V4Z~D 2

16,17

C51 0.047U_0402_16V4Z~D

Q38 2N7002W-7-F_SOT323~D

CLK_SCLK

C50 4.7U_0603_6.3V4Z~D

S

CLK_SCLK C61 0.047U_0402_16V4Z~D

3

2

2

2 G 1 D

ICH_SMBCLK

C389 0.1U_0402_16V4Z~D

16,17

+3.3V_RUN

23,28,34 ICH_SMBCLK

1

+CK_VDD_MAIN2 CLK_SDATA

2 R369 2 R377 CLK_MCH_BCLK 2 R349 CLK_MCH_BCLK# 2 R360 CLK_CPU_BCLK 2 R322 CLK_CPU_BCLK# 2 R338 CLK_MCH_3GPLL 1 R392 CLK_MCH_3GPLL# 1 R403 CLK_PCIE_SATA 1 R381 CLK_PCIE_SATA# 1 R385 CLK_PCIE_ICH 1 R365 CLK_PCIE_ICH# 1 R374 CLK_PCIE_LOM 1 R393 CLK_PCIE_LOM# 1 R399 DREFCLK 1 R344 DREFCLK# 1 R355 DREF_SSCLK 1 R522 DREF_SSCLK# 1 R523 CLK_PCIE_MINI2 1 R544 CLK_PCIE_MINI2# 1 R545 CLK_PCIE_MINI1 1 R1641 CLK_PCIE_MINI1# 1 R1642 CLK_CPU_ITP#

1

2

Q36 2N7002W-7-F_SOT323~D

D

2 L40 BLM21PG600SN1D_0805~D

1

C326 0.1U_0402_16V4Z~D

1

CLK_CPU_ITP +CK_VDD_MAIN

1

R275 2.2K_0402_5%~D 2 1

1 G 2

R270 2.2K_0402_5%~D 2 1

+3.3V_RUN

2

+CK_VDD_MAIN

Title

Clock Generator Size

Document Number

Date:

Tuesday, February 07, 2006

Rev 0.6

LA-2791 Sheet 1

6

of

63

5

10 10

H_ADSTB#0 H_ADSTB#1

REQ0# REQ1# REQ2# REQ3# REQ4#

H_ADSTB#0 H_ADSTB#1

L2 V4

ADSTB0# ADSTB1#

DINV0# DINV1# DINV2# DINV3#

J26 M26 V23 AC20

DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3#

H23 M24 W24 AD23 G22 N25 Y25 AE24

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

A20M# FERR# IGNNE# INIT# LINT0 LINT1

A6 A5 C4 B3 C6 B4

H_A20M# H_FERR# H_IGNNE# H_INIT# H_INTR H_NMI

STPCLK# SMI#

D5 A3

H_STPCLK# H_SMI#

YONAH

ADDR GROUP

DATA GROUP

C

6 CLK_CPU_BCLK 6 CLK_CPU_BCLK#

CLK_CPU_BCLK A22 CLK_CPU_BCLK# A21

H_ADS# H_BNR# H_BPRI# H_BR0# H_DEFER# H_DRD Y# H_HIT# H_HITM# H_IERR# H_LOCK# H_RESET#

10 10

+1.05V_VCCP

R422 56_0402_5%~D 1

2

H_ADS# H_BNR# 10 H_BPRI# 10 H_BR0# 10 H_DEFER# 10 H_DRDY# 10 H_HIT# 10 H_HITM# 10 H_LOCK# 10 H_RESET#

10

H_RS#[0..2]

H_RS#0 H_RS#1 H_RS#2 H_TRDY#

23,39 ITP_DBRESET# 10 H_DBSY# 22 H_DPSLP# 22,49 H_DPRSTP# 10 H_DPWR#

ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3

AD4 AD3 AD1 AC4

BPM0# BPM1# BPM2# BPM3#

ITP_DBRESET# H_DBSY# H_DPSLP# H_DPRSTP# H_DPWR# ITP_BPM#4 ITP_BPM#5

C20 E1 B5 E5 D24 AC2 AC1 D21

DBR# DBSY# DPSLP# DPRSTP# DPWR# PRDY# PREQ# PROCHOT#

D6 D7 AC5 AA6 AB3 C26 D25 AB5 AB6

PWRGOOD SLP# TCK TDI TDO TEST1 TEST2 TMS TRST#

A24 A25 C7

THERMDA DIODE THERMDC THERMTRIP#

22 H_PWRGOOD 10,22 H_CPUSLP# R1387 @ 1K_0603_1%~D 2 1 2 1 R1378 51_0603_1%~D

H_CPUSLP# ITP_TCK ITP_TDI ITP_TDO TEST1 TEST2 ITP_TMS ITP_TRST# H_THERMDA H_THERMDC

18 H_THERMDA 18 H_THERMDC 18 H_THERMTRIP#

CONTROL

RS0# RS1# RS2# TRDY#

38 CPU_PROCHOT#

Pop R1378 required by Intel for B0 Yonah. Backward compatible for A0 and A1 Yonah

ADS# BNR# BPRI# BR0# DEFER# DRDY# HIT# HITM# IERR# LOCK# RESET#

HOST CLK

F3 F4 G3 G2

10 H_TRDY#

B

H1 E2 G5 F1 H5 F21 G6 E4 D20 H4 B1

BCLK0 BCLK1

MISC

THERMAL

1

2 @

JITP

2 @

ITP_DBRESET# ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4

R424 22.6_0402_1%~D H_RESET# 1 2 R434 22.6_0402_1%~D ITP_TDO 1 2

6 6

CLK_CPU_ITP CLK_CPU_ITP#

ITP_BPM#5 ITP_TCK CLK_CPU_ITP CLK_CPU_ITP# ITP_TCK ITP_TRST# ITP_TMS ITP_TDI

28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

+3.3V_SUS R367 150_0402_1%~D ITP_DBRESET# 1 2

VTT1 VTT0 VTAP DBR# DBA# BPM0# GND5 BPM1# GND4 BPM2# GND3 BPM3# GND2 BPM4# GND1 BPM5# RESET# FBO GND0 BCLKP BCLKN TDO NC2 TCK NC1 TRST# TMS TDI

D

+1.05V_VCCP R415 51_0402_5%~D ITP_TDO 1 2 R416 51_0402_5%~D H_RESET# 1 2 R33 54.9_0402_1%~D ITP_BPM#5 1 2

+1.05V_VCCP

@ MOLEX_52435-2891_28P~D

R387 39.2_0402_1%~D ITP_TMS 1 2 R417 150_0402_5%~D ITP_TDI 1 2 This shall place near CPU R391 680_0402_5%~D ITP_TRST# 1 2 R436 27.4_0402_1%~D ITP_TCK 1 2

C

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

LEGACY CPU

1

29

K3 H2 K2 J3 L5

E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26

29

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

+1.05V_VCCP H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#

30

10 H_REQ#[0..4]

A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31#

30

D

J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1

1

H_D#[0..63] 10

JCPUA H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

2

C72 0.01U_0402_16V7K~D

H_A#[3..31]

3

C71 0.01U_0402_16V7K~D

10

4

10 10 10 10 B

H_DSTBN#[0..3] 10

H_DSTBP#[0..3] 10

H_A20M# H_FERR# H_IGNNE# H_INIT# H_INTR H_NMI

22 22 22 22 22 22

H_STPCLK# 22 H_SMI# 22

H_THERMTRIP# TYCO_1-1674770-2_Yonah~D

H_THERMDA, H_THERMDC routing together. Trace width / Spacing = 10 / 10 mil A

+1.05V_VCCP

R398 56_0402_5%~D 1 2 H_THERMTRIP#

A

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Yonah in mFCPGA479 Size

Document Number

Date:

Tuesday, February 07, 2006

Rev 0.6

LA-2791 Sheet 1

7

of

63

5

4

3

2

1

Length match within 25 mils +VCC_CORE JCPUB VCCSENSE VSSSENSE

VCCSENSE VSSSENSE

+1.5V_RUN +1.05V_VCCP

D

+VCC_CORE R140 1K_0402_1%~D 2

R555 100_0402_1%~D VCCSENSE 2

1

1

V_CPU_GTLREF

R556 100_0402_1%~D VSSSENSE 1 2

R_B

2

1

2

49

H_PSI#

49 49 49 49 49 49 49

VID0 VID1 VID2 VID3 VID4 VID5 VID6

H_PSI#

2

R147 2K_0402_1%~D

1

C87 10U_0805_4VAM~D

R_A

C88 0.01U_0402_16V7K~D

1

+1.05V_VCCP

Layout close CPU PIN AD26 0.5 inch (max)

Layout close CPU

VID0 VID1 VID2 VID3 VID4 VID5 VID6

10 6 6

C

CPU_BSEL0 CPU_BSEL1 CPU_BSEL2

R129 27.4_0402_1%~D 1

R124 54.9_0402_1%~D 1

R465 27.4_0402_1%~D 1

R457 54.9_0402_1%~D 1

2

2

2

2

+VCC_CORE

Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal.

CPU_BSEL

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0

133

0

0

1

166

0

1

1

VCCSENSE VSSSENSE

B26

VCCA

K6 J6 M6 N6 T6 R6 K21 J21 M21 N21 T21 R21 V21 W21 V6 G21

VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP

AE6

PSI#

AD6 AF5 AE5 AF4 AE3 AF2 AE2

VID0 VID1 VID2 VID3 VID4 VID5 VID6

AD26

V_CPU_GTLREF

B22 B23 C21

BSEL0 BSEL1 BSEL2

COMP0 COMP1 COMP2 COMP3

R26 U26 U1 V1

COMP0 COMP1 COMP2 COMP3

E7 AB20 AA20 AF20 AE20 AB18 AB17 AA18 AA17 AD18 AD17 AC18 AC17 AF18 AF17

YONAH

GTLREF

CPU_BSEL0 CPU_BSEL1 CPU_BSEL2

D2 F6 D3 C1 AF1 D22 C23 C24 AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 T22 B25

B

JCPUC

AF7 AE7

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

POWER, GROUNG, RESERVED SIGNALS AND NC

49 49

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AB26 AA25 AD25 AE26 AB23 AC24 AF24 AE23 AA22 AD22 AC21 AF21 AB19 AA19 AD19 AC19 AF19 AE19 AB16 AA16 AD16 AC16 AF16 AE16 AB13 AA14 AD13 AC14 AF13 AE14 AB11 AA11 AD11 AC11 AF11 AE11 AB8 AA8 AD8 AC8 AF8 AE8 AA5 AD5 AC6 AF6 AB4 AC3 AF3 AE4 AB1 AA2 AD2 AE1 B6 C5 F5 E6 H6 J5 M5 L6 P6 R5 V5 U6 Y6 A4 D4 E3 H3 G4 K4 L3 P3 N4 T4 U3 Y3 W4 D1 C2 F2 G1

AE18 AE17 AB15 AA15 AD15 AC15 AF15 AE15 AB14 AA13 AD14 AC13 AF14 AE13 AB12 AA12 AD12 AC12 AF12 AE12 AB10 AB9 AA10 AA9 AD10 AD9 AC10 AC9 AF10 AF9 AE10 AE9 AB7 AA7 AD7 AC7 B20 A20 F20 E20 B18 B17 A18 A17 D18 D17 C18 C17 F18 F17 E18 E17 B15 A15 D15 C15 F15 E15 B14 A13 D14 C13 F14 E13 B12 A12 D12 C12 F12 E12 B10 B9 A10 A9 D10 D9 C10 C9 F10 F9 E10 E9 B7 A7 F7

TYCO_1-1674770-2_Yonah~D

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

YONAH

POWER, GROUND

K1 J2 M2 N1 T1 R2 V2 W1 A26 D26 C25 F25 B24 A23 D23 E24 B21 C22 F22 E21 B19 A19 D19 C19 F19 E19 B16 A16 D16 C16 F16 E16 B13 A14 D13 C14 F13 E14 B11 A11 D11 C11 F11 E11 B8 A8 D8 C8 F8 E8 G26 K26 J25 M25 N26 T26 R25 V25 W26 H24 G23 K23 L24 P24 N23 T23 U24 Y24 W23 H21 J22 M22 L21 P21 R22 V22 U21 Y21

D

C

B

TYCO_1-1674770-2_Yonah~D

A

A

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Yonah in mFCPGA479 Size

Document Number

Date:

Tuesday, February 07, 2006

Rev 0.6

LA-2791 Sheet 1

8

of

63

5

4

3

2

1

+VCC_CORE

Place these inside 1 socket cavity on L8 (North side Secondary) 2

1 C100 10U_0805_4VAM~D 2

1 C429 10U_0805_4VAM~D

2

1 C98 10U_0805_4VAM~D

2

1 C430 10U_0805_4VAM~D

2

C99 10U_0805_4VAM~D

1

1

2

C472 10U_0805_4VAM~D 2

1 C473 10U_0805_4VAM~D

1 C119 10U_0805_4VAM~D

2

2

1 C142 10U_0805_4VAM~D

2

C141 10U_0805_4VAM~D

D

D

+VCC_CORE

Place these inside 1 socket cavity on L8 (Sorth side Secondary) 2

1 C428 10U_0805_4VAM~D 2

1 C138 10U_0805_4VAM~D

2

1 C447 10U_0805_4VAM~D

2

1 C470 10U_0805_4VAM~D

2

C469 10U_0805_4VAM~D

1

1

2

C467 10U_0805_4VAM~D 2

1 C471 10U_0805_4VAM~D

1 C97 10U_0805_4VAM~D

2

2

1 C102 10U_0805_4VAM~D

2

C433 10U_0805_4VAM~D

+VCC_CORE

Place these inside 1 socket cavity on L8 (North side Primary) 2

1 C468 10U_0805_4VAM~D 2

1 C140 10U_0805_4VAM~D

2

1 C139 10U_0805_4VAM~D

2

1 C446 10U_0805_4VAM~D

2

1 C466 10U_0805_4VAM~D

2

C137 10U_0805_4VAM~D

+VCC_CORE

C

Place these inside 1 socket cavity on L8 (Sorth side Primary) 2

1 C448 10U_0805_4VAM~D 2

1 C432 10U_0805_4VAM~D

2

1 C426 10U_0805_4VAM~D

2

1 C427 10U_0805_4VAM~D

2

22uF 0805 X5R -> 85 degree C

1 C431 10U_0805_4VAM~D

2

10uF 0805 X5R -> 85 degree C

C120 10U_0805_4VAM~D C

High Frequence Decoupling

Near VCORE regulator.

2

1 + 2

1 + 2

C365 330U_D_2.5VM_R6M~D

+

@ C618 330U_D_2.5VM_R6M~D

2

1

C497 330U_D_2.5VM_R6M~D

+

@ C354 330U_D_2.5VM_R6M~D

1

The caps need change to ESR=6m ohms C496 330U_D_2.5VM_R6M~D

South Side Secondary

C352 330U_D_2.5VM_R6M~D

+VCC_CORE

1 + 2

1

North Side Secondary

ESR 1980uF

+ 2

B

B

7mOhm PS CAP

7mOhm PS CAP

7mOhm PS CAP

7mOhm PS CAP

7mOhm PS CAP

7mOhm PS CAP

@ C372 330U_D2E_2.5VM_R9~D

+1.05V_VCCP

A

1 1

+ 2

2

1 C415 0.1U_0402_10V7K~D

2

1 C439 0.1U_0402_10V7K~D

2

1 C451 0.1U_0402_10V7K~D

2

1 C416 0.1U_0402_10V7K~D

2

1 C462 0.1U_0402_10V7K~D

2

C414 0.1U_0402_10V7K~D

Place these inside socket cavity on L8 (North side Secondary)

CRB was 270uF

A

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

CPU Bypass Size

Document Number

Date:

Tuesday, February 07, 2006

Rev 0.6

LA-2791 Sheet 1

9

of

63

5

4

3

2

1

Description at page12 Note : CFG3:17 has internal pullup, CFG18:19 has internal pulldown

B7 E8 E7 J9 H8 C3 D4 D3 B3 C7 C6 F6 A7 E3

HRS0# HRS1# HRS2#

B4 E6 D6

H_DRD Y# H_DEFER# H_HITM# H_HIT# H_LOCK# H_BR0# H_BNR# H_BPRI# H_DBSY# H_CPUSLP#

221_0402_1%~D R85

H_RESET# H_ADS# H_TRDY# H_DPWR# H_DRDY# H_DEFER# H_HITM# H_HIT# H_LOCK# H_BR0# H_BNR# H_BPRI# H_DBSY# H_CPUSLP#

7 7 7 7 7 7 7 7 7 7 7 7 7 7,22

16 16 17 17

M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3

16 16 17 17

M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3

DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#

16 16 17 17

+1.8V_SUS

R142 1 1 R141

H_VREF

1

2

M_ODT0 M_ODT1 M_ODT2 M_ODT3

DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3

DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3

AE37 AF41 AG37 AH41

DMITXN0 DMITXN1 DMITXN2 DMITXN3

DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3

AC37 AE41 AF37 AG41

DMITXP0 DMITXP1 DMITXP2 DMITXP3

M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3

AY35 AR1 AW7 AW40

SM_CK0 SM_CK1 SM_CK2 SM_CK3

M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3

AW35 AT1 AY7 AY40

SM_CK0# SM_CK1# SM_CK2# SM_CK3#

DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB

AU20 AT20 BA29 AY29

SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3

DDR_CS0_DIMMA# AW13 DDR_CS1_DIMMA# AW12 DDR_CS2_DIMMB# AY21 DDR_CS3_DIMMB# AW21

SM_CS0# SM_CS1# SM_CS2# SM_CS3#

M_OCDOCMP0 M_OCDOCMP1

AL20 AF10

SM_OCDCOMP0 SM_OCDCOMP1

M_ODT0 M_ODT1 M_ODT2 M_ODT3

BA13 BA12 AY20 AU21

SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3

2 80.6_0402_1%~D 2 80.6_0402_1%~D

SMRCOMPN SMRCOMPP

AV9 AT9

V_DDR_MCH_REF

23 PM_BMBUSY# PM_EXTTS#0 16 PM_EXTTS#0 PM_EXTTS#1 23 PM_EXTTS#1 18 THERMTRIP_MCH# ICH_PWRGD 23,42 ICH_PWRGD PLTRST_R# 2 1 21,23,28,34,52 PLTRST# 100_0402_1%~D R441 21 MCH_ICH_SYNC#

CFG

DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3

AC35 AE39 AF35 AG39

SM_RCOMPN SM_RCOMPP

AK1 AK41

SM_VREF0 SM_VREF1

G28 F25 H26 G6 AH33 AH34

PM_BMBUSY# PM_EXTTS0# PM_EXTTS1# PM_THERMTRIP# PWROK RSTIN#

K28

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 G_CLKP G_CLKN

CLK

0.1U_0402_16V4Z~D C48

23 23 23 23

+1.05V_VCCP

H_DSTBP#[0..3] 7

7 7 7 7

DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3

DMI_MRX_ITX_P0 DMI_MRX_ITX_P1 DMI_MRX_ITX_P2 DMI_MRX_ITX_P3

NC

0.1U_0402_16V4Z~D C65

2 1

100_0402_1%~D R86

2 1 2

221_0402_1%~D R64 100_0402_1%~D R65

2 CLK_MCH_BCLK# 6 CLK_MCH_BCLK 6 H_DSTBN#[0..3] 7

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_RESET# H_ADS# H_TRDY#

16 16 17 17

7 7

23 23 23 23

DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3

RESERVED

HCPURST# HADS# HTRDY# HDPWR# HDRDY# HDEFER# HHITM# HHIT# HLOCK# HBREQ0# HBNR# HBPRI# HDBSY# HCPUSLP#

16 16 17 17

DMI_MRX_ITX_P0 DMI_MRX_ITX_P1 DMI_MRX_ITX_P2 DMI_MRX_ITX_P3

AE35 AF39 AG35 AH39

ICH_SYNC#

CALISTOGA A0_FCBGA1466~D

AG33 AF33

CLK_MCH_3GPLL 6 CLK_MCH_3GPLL# 6

D_REF_CLKN D_REF_CLKP

A27 A26

D_REF_SSCLKN D_REF_SSCLKP

C40 D41

DREF_SSCLK# 6 DREF_SSCLK 6

CLK_REQ#

H32

CLK_3GPLLREQ# 6

DREFCLK# DREFCLK

NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18

A3 A39 A4 A40 AW1 AW41 AY1 BA1 BA2 BA3 BA39 BA40 BA41 C1 AY41 B2 B41 C41 D1

RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVED5 RESERVED6 RESERVED7 RESERVED8 RESERVED9 RESERVED10 RESERVED11 RESERVED12 RESERVED13

T32 R32 F3 F7 AG11 AF11 H7 J19 A41 A34 D28 D27 A35

Layout Note: Route as short as possible

H_RS#0 H_RS#1 H_RS#2

PM_EXTTS#0 16,17,48 V_DDR_MCH_REF H_RS#[0..2]

CPU_BSEL0 CPU_BSEL0 8 MCH_CLKSEL1 MCH_CLKSEL1 6 MCH_CLKSEL2 MCH_CLKSEL2 6 CFG3 PAD~D T34 CFG4 PAD~D T35 CFG5 CFG5 12 CFG6 CFG6 12 CFG7 CFG7 12 CFG8 PAD~D T41 CFG9 CFG9 12 CFG10 PAD~D T42 CFG11 CFG11 12 CFG12 CFG12 12 CFG13 CFG13 12 CFG14 PAD~D T43 CFG15 PAD~D T44 CFG16 CFG16 12 CFG17 PAD~D T45 CFG18 CFG18 12 CFG19 CFG19 12 CFG20 CFG20 12

K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26

6 6

7

CALISTOGA A0_FCBGA1466~D

V_DDR_MCH_REF

B

R336 10K_0402_5%~D 2 1 @

PM_EXTTS#1

1

M_OCDOCMP0 M_OCDOCMP1

R253 10K_0402_5%~D 2 1

2

@

A

THERMTRIP_MCH# 1

R335 75_0402_5%~D 2 +1.05V_VCCP

A

Stuff R435 & R437 for A1 Calistoga

Layout Note: H_XRCOMP & H_YRCOMP trace width and spacing is 10/20

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

C

+3.3V_RUN_R

@ R437 40.2_0402_1%~D 2 1

J7 W8 U3 AB10

2

23 23 23 23

DMI_MRX_ITX_N0 DMI_MRX_ITX_N1 DMI_MRX_ITX_N2 DMI_MRX_ITX_N3

@ R435 40.2_0402_1%~D 2 1

HDINV#0 HDINV#1 HDINV#2 HDINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

1

0.1U_0402_16V4Z~D

HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3

K4 T7 Y5 AC4 K3 T6 AA5 AC5

H_ADSTB#0 H_ADSTB#1

1

AG1 AG2

H_ADSTB#0 H_ADSTB#1

2

HCLKN HCLKP

H_REQ#[0..4] 7

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_SWNG0

100_0402_1%~D R326

B9 C13

2

+1.05V_VCCP

1

HVREF0 HVREF1 HXRCOMP HXSCOMP HYRCOMP HYSCOMP HXSWING HYSWING

HADSTB#0 HADSTB#1

1

C425 0.1U_0402_16V4Z~D

24.9_0402_1%~D R90

24.9_0402_1%~D R57 2 1

1 2

J13 K13 E1 E2 Y1 U1 E4 W1

D8 G8 B8 F8 A8

H_SWNG1

C363

1 2

54.9_0402_1%~D R52

1 2

54.9_0402_1%~D R80

H_VREF H_XRCOMP H_XSCOMP H_YRCOMP H_YSCOMP H_SWNG0 H_SWNG1

HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4

D

DMI_MRX_ITX_N0 DMI_MRX_ITX_N1 DMI_MRX_ITX_N2 DMI_MRX_ITX_N3

PM

B

HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#

U40B 23 23 23 23

DDR MUXING

+1.05V_VCCP

HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14

1

C

F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8

7

DMI

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_A#[3..31]

200_0402_1%~D

U40A

R325

H_D#[0..63]

2

7

HOST

D

1

+1.05V_VCCP

3

2

Title

Calistoga(1 of 6) Size

Document Number

Date:

Tuesday, February 07, 2006

Rev 0.6

LA-2791 Sheet 1

10

of

63

5

4

D

3

2

1

D

D E

16 DDR_A_DQS[0..7]

AU12 AV14 BA20

SA_BS0 SA_BS1 SA_BS2

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4

SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

C

16 DDR_A_DQS#[0..7]

16 DDR_A_MA[0..13]

16 DDR_A_CAS# 16 DDR_A_RAS# 16 DDR_A_WE#

B

T2022 T2024

PAD~D PAD~D

DDR_A_DQS#0 AK32 DDR_A_DQS#1 AU33 DDR_A_DQS#2 AN27 DDR_A_DQS#3 AM21 DDR_A_DQS#4 AM12 DDR_A_DQS#5 AL8 DDR_A_DQS#6 AN3 DDR_A_DQS#7 AH5

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13

AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12

DDR_A_CAS# AY13 DDR_A_RAS# AW14 DDR_A_WE# AY14 SA_RCVENIN# AK23 SA_RCVENOUT# AK24

SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_CAS# SA_RAS# SA_WE# SA_RCVENIN# SA_RCVENOUT#

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

U40E AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_D[0..63] 16 17 DDR_B_BS0 17 DDR_B_BS1 17 DDR_B_BS2 17 DDR_B_DM[0..7]

17 DDR_B_DQS[0..7]

17 DDR_B_DQS#[0..7]

17 DDR_B_MA[0..13]

17 DDR_B_CAS# 17 DDR_B_RAS# 17 DDR_B_WE# T2023 T2025

PAD~D PAD~D

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

AT24 AV23 AY28

SB_BS0 SB_BS1 SB_BS2

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4

SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5

SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13

AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13

DDR_B_CAS# DDR_B_RAS# DDR_B_WE# SB_RCVENIN# SB_RCVENOUT#

AR24 AU23 AR27 AK16 AK18

SB_CAS# SB_RAS# SB_WE# SB_RCVENIN# SB_RCVENOUT#

CALISTOGA A0_FCBGA1466~D

DDR SYS MEMORY B

16 DDR_A_DM[0..7]

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR SYS MEMORY A

U40D 16 DDR_A_BS0 16 DDR_A_BS1 16 DDR_A_BS2

AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

DDR_B_D[0..63] 17

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

C

B

CALISTOGA A0_FCBGA1466~D

A

A

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Calistogo(2 of 6) Size

Document Number

Date:

Tuesday, February 07, 2006

Rev 0.6

LA-2791 Sheet 1

11

of

63

5

4

3

2

1

LOW = Moby Dick C

+1.5VRUN_PCIE

U40C

19 LCD_A019 LCD_A119 LCD_A2-

C37 B35 A37 F30 D29 F28

19 LCD_B019 LCD_B119 LCD_B2-

G30 D30 F29

19 19 19 19

LCD_ACLK+ LCD_ACLKLCD_BCLK+ LCD_BCLKBIA_PWM_R PANEL_BKEN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA

19 PANEL_BKEN 19 LDDC_CLK 19 LDDC_DATA ENVDD

1 R314 2

TVIREF 4.99K_0402_1%~D

TV_CVBS TV_Y TV_C

LB_DATA0 LB_DATA1 LB_DATA2 LB_DATA#0 LB_DATA#1 LB_DATA#2

A32 A33 E26 E27

LA_CLK LA_CLK# LB_CLK LB_CLK#

D32 J30 H30 H29 G26 G25 F32 B38 C35 C33 C32

LBKLT_CTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL

A16 C18 A19

TVDAC_A TVDAC_B TVDAC_C

J20

TV_IREF

B16 B18 B19

TV_IRTNA TV_IRTNB TV_IRTNC

J29 K30

TV_DCONSEL1 TV_DCONSEL0

TV

36 36 36

R23 2 1 150_0402_1%~D

C

for Alviso N.C for Calistoga to GND

R24 2 1 150_0402_1%~D

LVREF

L_IBG

2 1 R251 1.5K_0402_1%~D

R25 2 1 150_0402_1%~D

19

LA_DATA#0 LA_DATA#1 LA_DATA#2

LVDS

19 LCD_B0+ 19 LCD_B1+ 19 LCD_B2+

EXP_RXN0 EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8 EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15

Close to U40.J20

20 VGA_VSYNC 20 VGA_HSYNC 20,36 VGA_BLU 20,36

VGA_GRN

20,36

VGA_RED

2

Close to U40.J22 B

1

C26 C25

DDCCLK DDCDATA

H23 G23 E23 D23 C22 B22 A21 B21

VSYNC HSYNC BLUE BLUE# GREEN GREEN# RED RED#

J22

CRT_IREF

CRT

G_CLK_DDC2 G_DAT_DDC2

R150 255_0402_1%~D

Strap Pin Table

F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38

SDVOB_INT- 52

CFG5 CFG6 CFG7 CFG9

EXP_RXP0 EXP_RXP1 EXP_RXP2 EXP_RXP3 EXP_RXP4 EXP_RXP5 EXP_RXP6 EXP_RXP7 EXP_RXP8 EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15

D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38

EXP_TXN0 EXP_TXN1 EXP_TXN2 EXP_TXN3 EXP_TXN4 EXP_TXN5 EXP_TXN6 EXP_TXN7 EXP_TXN8 EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15

F36 DVO_RED#_C C1346 1 C1347 1 G40 DVO_GREEN#_C H36 DVO_BLUE#_C C1348 1 J40 DVO_CLK#_C C1349 1 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40

2 2 2 2

EXP_TXP0 EXP_TXP1 EXP_TXP2 EXP_TXP3 EXP_TXP4 EXP_TXP5 EXP_TXP6 EXP_TXP7 EXP_TXP8 EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15

D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40

DVO_RED_C C1350 1 DVO_GREEN_CC1360 1 DVO_BLUE_C C1372 1 DVO_CLK_C C1359 1

2 2 2 2

SDVOB_INT+ 52

Low

= DMI x 2

High = DMI x 4

D

*

LOW = Moby Dick HIGH = Calistoga Low

*

= DT/Transportable CPU

High = Mobile CPU

*

Low = Reverse Lane High = Normal Operation

*

CFG11

10

CFG5

10

CFG6

10

CFG7

10

CFG9

10

CFG11

10

CFG12

10

CFG13

10

CFG16

R307

1

2

@ 2.2K_0402_5%~D

R67

1

2 @ 2.2K_0402_5%~D

R281

1

2

@ 2.2K_0402_5%~D

R282

1

2

@ 2.2K_0402_5%~D

R357

1

2 @

2.2K_0402_5%~D

R288

1

2 @

2.2K_0402_5%~D

R323

1

2 @

2.2K_0402_5%~D

R346

1

2

@ 2.2K_0402_5%~D

CFG[3:17] have internal pullup

CFG[13:12]

CFG16 (FSB Dynamic ODT) 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D

SDVOB_RED- 52 SDVOB_GREEN- 52 SDVOB_BLUE- 52 SDVOB_CLK- 52

(VCC Select) CFG19 (DMI Lane Reversal)

SDVO_CTRLDATA 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D

SDVOB_RED+ 52 CFG20 SDVOB_GREEN+ 52 SDVOB_BLUE+ 52 SDVOB_CLK+ 52 (PCIE/SDVO select)

= = = =

Low

Reserved XOR Mode Enabled All Z Mode Enabled Normal Operation * (Default)

+3.3V_RUN_R

= Disabled

High = Enabled Low

*

= 1.05V (Default)

10 10

CFG18 CFG19

10

CFG20

R308 R306 R310

1 1

2 2

1

2

@ 1K_0402_5%~D @1K_0402_5%~D @1K_0402_5%~D C

* CFG[18:20] have internal pulldown

High = 1.5V Low = Normal * Operation (Default): Lane number in Order High = Reverse Lane Low

= No SDVO Device Present (Default)* High = SDVO Device Present Low = Only PCIE or SDVO is operational. (Default)

*

High = PCIE/SDVO are operating simu.

B

+3.3V_RUN_R VGA_RED

CALISTOGA A0_FCBGA1466~D

CFG18

00 01 10 11

VGA_GRN VGA_BLU

1 R261 1 R260 1 R295

2 150_0402_1%~D 2 150_0402_1%~D 2 150_0402_1%~D

1

LA_DATA0 LA_DATA1 LA_DATA2

PEGCOMP

D

S

G_CLK_DDC2

R232 2.2K_0402_5%~D

B37 B34 A36

D40 D38

2

19 LCD_A0+ 19 LCD_A1+ 19 LCD_A2+

EXP_COMPI EXP_COMPO

R229 2.2K_0402_5%~D 2 1

SDVOCTRL_DATA SDVOCTRL_CLK

PCI-EXPRESS GRAPHICS

D

SDVO_CTRLDATA SDVO_CTRLCLK

H27 H28

52 SDVO_CTRLDATA 52 SDVO_CTRLCLK

R1493 24.9_0402_1%~D 1 2

3

1

G

2

CLK_DDC2

CLK_DDC2 20,36

Q31 BSS138W-7-F_SOT323~D

+3.3V_RUN_R G

2

+3.3V_RUN_R +3.3V_RUN_R G_DAT_DDC2

3

4

19,39 BIA_PWM

IN1

O 3

G

IN2

1

DAT_DDC2

DAT_DDC2 20,36

Q27 BSS138W-7-F_SOT323~D

5 P

1 R279

LCTLB_DATA 2 10K_0402_5%~D

D

LCTLA_CLK 2 10K_0402_5%~D

S

1 R283

1

BIA_PWM_R

2 U8 74AHC1G08GW_SOT353-5~D

A

A

1 R300

PANEL_BKEN 2 100K_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Calistoga(3 of 6) Size

Document Number

Date:

Tuesday, February 07, 2006

Rev 0.6

LA-2791 Sheet 1

12

of

63

4

3

U40H

VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2

A28 B28 C28

VCCD_TVDAC VCCDQ_TVDAC

D21 H19

VCCHV0 VCCHV1 VCCHV2

A23 B23 B25

C599 10U_0805_4VAM~D

C22 0.1U_0402_16V4Z~D

2

C35, C305, C306 replace by 0 ohm 0805 resistor

1

2

1

1

2

2

+1.5VRUN_HPLL

Should be placed in cavity

1

2 +1.5V_RUN +1.5VRUN_3GPLL R267 L34 0.5_0805_1%~D BLM18PG181SN1_0603~D 1 2+3GPLL_R 2 1

1

2

1

2

1

1 C94 22U_0805_6.3VAM~D

2

1

2

1

1

2

2

B

+1.5V_RUN

1 C419 22U_0805_6.3VAM~D

2

+1.5VRUN_DPLLB

L28 10U_MLZ2012E100PTAIN_60mA_25%_0805~D 2 1 +1.5V_RUN

40mA Max.

L38 2 1 BLM18AG121SN1D_0603~D

45mA Max.

+1.5VRUN_DPLLA

2

+1.5V_RUN

+1.5VRUN_MPLL L39 2 1 +1.5V_RUN BLM18AG121SN1D_0603~D

45mA Max.

+1.5V_RUN_TVDAC

0.1U_0402_16V4Z~D C297

close pin B30/C30/A30

+1.5V_RUN L11 BLM18PG181SN1_0603~D 2 1

C304 0.022U_0402_16V7K~D

+1.5VRUN_QTVDAC

2

1

+

2

40mA Max.

L33 10U_MLZ2012E100PTAIN_60mA_25%_0805~D 2 1 +1.5V_RUN

1

2

1 +

2

C335 470U_D2_2.5VM~D

2

1

+3.3V_RUN_R

2

3

1 2 R12 10_0402_5%~D

A

D8 MMBD4148_SOT23~D

DELL CONFIDENTIAL/PROPRIETARY

TV DAC Voltge Follower Circuit - 700mV

Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

2

0.1U_0402_16V4Z~D

2

1

+1.5V_RUN

D14 MMBD4148_SOT23~D

CRT DAC Voltge Follower Circuit - 700mV

1

C24 0.1U_0402_16V4Z~D

2

1

2

C37 0.022U_0402_16V7K~D

1

2

1

C324 0.1U_0402_16V4Z~D

+3.3V_RUN_R

1

C314 4.7U_0603_6.3V4Z~D

AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14

1 3

2

2

C

2

+2.5V_RUN

C299 0.1U_0402_16V4Z~D

10U_0805_4VAM~D

10U_0805_4VAM~D C59

220U_V_4VM_R45~D C53

+1.5V_RUN_TVDAC +1.5VRUN_QTVDAC

+1.5V_RUN

1 2 R320 10_0402_5%~D

1

2 3

+2.5V_RUN

+1.05V_VCCP

1

3

VSSA_TVBG

1

2

C35 22n_0805_25V

close pin A38

1

+1.5V_RUN

CALISTOGA A0_FCBGA1466~D

A

1 2

+3VRUN_ATV 1

+1.5V_RUN

+3VRUN_ATVBG +3VRUN_TVDACC

C23 0.1U_0402_16V4Z~D

AH1 AH2

2

R92 0_0603_5%~D

22n_0805_25V

VCCD_HMPLL0 VCCD_HMPLL1

+3VRUN_TVDACC

2

1

1

Route VSSA_TVBG GND from GMCH to decoupling cap ground lead and then connect to the GND plane.

+3VRUN_TVDACB

2

1

C36

+3VRUN_TVDACA

Route VSSACRTDAC gnd from GMCH to decoupling cap ground lead and then connect to the gnd plane.

VSSA_TVBG

2

4.7U_0603_6.3V4Z~D

VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1

E19 F19 C20 D20 E20 F20

1

D

@ C598

AF2 H20 G20

1

3

C298 0.1U_0402_16V4Z~D

+1.5VRUN_MPLL +3VRUN_ATVBG

VCCA_MPLL VCCA_TVBG VSSA_TVBG

CRTDAC: Route caps within 250mil of Alviso. Route FB within 3" of Calistoga

2

C306 22n_0805_25V

+2.5V_RUN

2

2

1 +2.5V_RUN

C305 22n_0805_25V

A38 B39

2

1

+3VRUN_TVDACB

BLM18PG181SN1_0603~D 2 +2.5V_RUN

C318 0.01U_0402_16V7K~D

VCCA_LVDS VSSA_LVDS

1

C364 0.1U_0402_16V4Z~D

+1.5VRUN_DPLLA +1.5VRUN_DPLLB +1.5VRUN_HPLL

Route +2.5VRUN from GMCH pinG41 to decoupling cap (C345)

34 PCIE_IRX_WANTX_N1 34 PCIE_IRX_WANTX_P1 34 PCIE_ITX_WANRX_N1_C

1

AA4

ICH_PWRGD

AC22

DPRSLPVR

TP0 / BATLOW#

C21

ICH_BATLOW#

PWRBTN#

C23

SIO_PWRBTN#

LAN_RST#

C19

PLTRST#

RSMRST#

Y4

2 SIO_SLP_S5# 39 ICH_PWRGD 10,42 DPRSLPVR

49

R280 10K_0402_5%~D 1 2

1 R1799

2 0_0402_5%~D

PM_EXTTS#1 10

SIO_PWRBTN# 39 PLTRST#

SUSPWROK 1 2 R296 10K_0402_5%~D

C380 @ 4.7P_0402_50V8C~D

SIO_SLP_S3# 39

SIO_SLP_S5#

E20 A20 F19 E19 R4 E22 R3 D20 AD21 AD20 AE20

2

10,21,28,34,52

SUSPWROK

+3.3V_SUS

18,42

SIO_EXT_SCI#

SIO_EXT_SCI# 39

USB_IDE# SATA_DET#

USB_IDE# 25

R784 100K_0402_5%~D C

SATA_DET# 25

GPIO24 T39 PAD~D SATA_CLKREQ# 6 WWAN_RADIO_DIS#

WWAN_RADIO_DIS# 34

34 34 34 34

PCIE_ITX_WANRX_P1_C PCIE_IRX_WLANTX_N2 PCIE_IRX_WLANTX_P2 PCIE_ITX_WLANRX_N2_C

34 PCIE_ITX_WLANRX_P2_C 28 PCIE_IRX_LOMTX_N3 28 PCIE_IRX_LOMTX_P3 28 PCIE_ITX_LOMRX_N3_C 28 PCIE_ITX_LOMRX_P3_C

U45D

C1

1

2 0.1U_0402_16V4Z~D

C2

1

2 0.1U_0402_16V4Z~D

C602 1

2 0.1U_0402_16V4Z~D

C603 1

2 0.1U_0402_16V4Z~D

C281 1

2 0.1U_0402_16V4Z~D

C282 1

2 0.1U_0402_16V4Z~D

PCIE_IRX_WANTX_N1 PCIE_IRX_WANTX_P1 PCIE_ITX_WANRX_N1 PCIE_ITX_WANRX_P1

F26 F25 E28 E27

PERn1 PERp1 PETn1 PETp1

PCIE_IRX_WLANTX_N2 PCIE_IRX_WLANTX_P2 PCIE_ITX_WLANRX_N2 PCIE_ITX_WLANRX_P2

H26 H25 G28 G27

PERn2 PERp2 PETn2 PETp2

PCIE_IRX_LOMTX_N3 PCIE_IRX_LOMTX_P3 PCIE_ITX_LOMRX_N3 PCIE_ITX_LOMRX_P3

B

ICHO_ECI_SPI_DATA ICHI_ECO_SPI_DATA

39 ICHO_ECI_SPI_DATA 39 ICHI_ECO_SPI_DATA

2 1

R389 10K_0402_5%~D

2 1

+3.3V_SUS

R1786 47_0402_5%~D 1 2 R1787 47_0402_5%~D 1 2

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

PERn3 PERp3 PETn3 PETp3

M26 M25 L28 L27

PERn4 PERp4 PETn4 PETp4

P26 P25 N28 N27

PERn5 PERp5 PETn5 PETp5

T25 T24 R28 R27

PERn6 PERp6 PETn6 PETp6

R2 P6 P1

SPI_CLK SPI_CS# SPI_ARB

P5 P2

SPI_MOSI SPI_MISO

D3 C4 D5 D4 E5 C3 A2 B3

OC0# OC1# OC2# OC3# OC4# OC5# / GPIO29 OC6# / GPIO30 OC7# / GPIO31

A

SPI

39 ICH_EC_SPI_CLK 39 SPI_CS#

R388 10K_0402_5%~D

2 1 ICH_EC_SPI_CLK SPI_CS#

+3.3V_SUS R384 10K_0402_5%~D

+3.3V_SUS

K26 K25 J28 J27

PCI-EXPRESS

GIGA LAN --->

PWROK

1

ICH7M A0_BGA652~D

close to ICH7-M MiniWLAN (Mini Card 2)--->

B24 D23 F22

GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15 GPIO24 GPIO25 SATACLKREQ#/GPIO35 GPIO38 GPIO39

CLK_ICH_14M 6 CLK_ICH_48M 6 T36 PAD~D

ICH_SUSCLK

C20

SLP_S3# SLP_S4# SLP_S5#

GPIO16 / DPRSLPVR

DPRSLPVR

CLK_ICH_14M CLK_ICH_48M

AC1 B2

SIO_SLP_S3#

GPIO11 / SMBALERT#

LCD_TST

CLKRUN#

30,38,39 CLKRUN#

R269 8.2K_0402_5%~D ICH_BATLOW# 1 2 R318 680_0402_5%~D 1 2

AC20 AF21

SUSCLK

D

R379 10_0402_5%~D @

USB

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

V26 V25 U28 U27

DMI_MTX_IRX_N0 DMI_MTX_IRX_P0 DMI_MRX_ITX_N0 DMI_MRX_ITX_P0

DMI1RXN DMI1RXP DMI1TXN DMI1TXP

Y26 Y25 W28 W27

DMI_MTX_IRX_N1 DMI_MTX_IRX_P1 DMI_MRX_ITX_N1 DMI_MRX_ITX_P1

DMI2RXN DMI2RXP DMI2TXN DMI2TXP

AB26 AB25 AA28 AA27

DMI_MTX_IRX_N2 DMI_MTX_IRX_P2 DMI_MRX_ITX_N2 DMI_MRX_ITX_P2

DMI3RXN DMI3RXP DMI3TXN DMI3TXP

AD25 AD24 AC28 AC27

DMI_MTX_IRX_N3 DMI_MTX_IRX_P3 DMI_MRX_ITX_N3 DMI_MRX_ITX_P3

DMI_CLKN DMI_CLKP

AE28 AE27

10 10 10 10

DMI_MTX_IRX_N1 DMI_MTX_IRX_P1 DMI_MRX_ITX_N1 DMI_MRX_ITX_P1

10 10 10 10

DMI_MTX_IRX_N2 DMI_MTX_IRX_P2 DMI_MRX_ITX_N2 DMI_MRX_ITX_P2

10 10 10 10

DMI_MTX_IRX_N3 DMI_MTX_IRX_P3 DMI_MRX_ITX_N3 DMI_MRX_ITX_P3

10 10 10 10

CLK_PCIE_ICH# CLK_PCIE_ICH

C25 D25

DMI_IRCOMP

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P

F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3

USBP0USBP0+ USBP1USBP1+ USBP2USBP2+ USBP3USBP3+ USBP4USBP4+ USBP5USBP5+ USBP6USBP6+ USBP7USBP7+

USBRBIAS# USBRBIAS

D2 D1

USBRBIAS

DMI_ZCOMP DMI_IRCOMP

DMI_MTX_IRX_N0 DMI_MTX_IRX_P0 DMI_MRX_ITX_N0 DMI_MRX_ITX_P0

USB_OC3# USB_OC0# USB_OC1# USB_OC2# USB_OC7# USB_OC5# USB_OC6#

CLK_PCIE_ICH# 6 CLK_PCIE_ICH 6 R427 24.9_0402_1%~D 1 2 USBP0USBP0+ USBP1USBP1+ USBP2USBP2+ USBP3USBP3+ USBP4USBP4+ USBP5USBP5+ USBP6USBP6+ USBP7USBP7+

USB_OC4#

1 R1622 1 R1623 1 R1624 1 R1625 1 R1626 1 R1627 1 R1628 1 R1629

USB_OC2#

25

USB_OC3#

32

2 10K_0402_5%~D 2 10K_0402_5%~D 2 10K_0402_5%~D 2 10K_0402_5%~D 2 10K_0402_5%~D 2 10K_0402_5%~D 2 10K_0402_5%~D 2 10K_0402_5%~D

B

Within 500 mils USB_OC4# USB_OC6# USB_OC5#

+1.5V_RUN 34 34 38 38 25 25 32 32 32 32 32 32 32 32 36 36

+3.3V_SUS

32 32 32