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Flip-Flop Applications • Applications of Flip-Flops: – Counters • Asynchronous Counter • Synchronous Counter

– Register

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Counters • A counter is a sequential machine that produces a specified count sequence. • The count changes whenever the input clock is asserted. • There is a great variety of counter based on its construction: – – – – –

Clock: Synchronous or Asynchronous Clock Trigger: Positive edged or Negative edged Counts: Binary, Decade, Gray …… Count Direction: Up, Down, or Up/Down Flip-flops: JK or T or D

Counters • A counter is a register that goes through a predetermined sequence of states upon the application of clock pulses. – Asynchronous counters – Synchronous counters • Async. counters (or ripple counters) – the clock signal (CLK) is only used to clock the first FF. – Each FF (except the first FF) is clocked by the preceding FF.

• Sync. counters, – the clock signal (CLK) is applied to all FF, which means that all FF shares the same clock signal, – thus the output will change at the same time. 3

Uses of Counters • The most typical uses of counters are: – To count the number of times that a certain event takes place – The occurrence of event to be counted is represented by the input signal to the counter – To control a fixed sequence of actions in a digital system – To generate timing signals – To generate clocks of different frequencies

Two Classes of Counters • Counters are classified into two categories: – Asynchronous Counters (Ripple counters) – Synchronous Counters • Asynchronous: The events do not have a fixed time relationship with each other and do not occur at the same time. • Synchronous: The events have a fixed time relationship with each other and do occur at the same time. • Counters are classified according to the way they are clocked: – In asynchronous counters, the first flip-flop is clocked by the external clock pulse and then each successive flip-flop is by clocked the output of the preceding flip-flop. – In synchronous counters, the clock input is connected to all of the flip-flop so that they are clocked simultaneously.

Asynchronous Counters • In asynchronous counter each flip-flop derives its own clock from other flip-flops and is therefore independent of the input clock. • Consequently, the output of each flip-flop may change at different time, hence the term asynchronous. • For the asynchronous counter, the output of the first flip-flop becomes the clock input for the second flip-flop, and the output of the second flip-flop becomes the clock input for the third flip-flop etc. • For the first flip-flop, the output changes whenever there is a negative transition in the clock input.

Asynchronous Counters • This means that the output of the first flip-flop produces a series of square waves that is half the frequency of the clock input. • Since the output of the first flip-flop becomes the clock of the second flip-flop, the output of the second flip-flop is half the frequency of its clock, • i.e. the output of the first flip-flop that in turn is half the frequency of the clock input. • This behavior, in essence is captured by the binary bit pattern in the counting sequence.

Asynchronous counters • Modulus (MOD) – the number of states it counts in a complete cycle before it goes back to the initial state. • Thus, the number of flip-flops used depends on the MOD of the counter (ie; MOD-4 use 2 FF (2bit), MOD-8 use 3 FF (3-bit), etc..) • Example: MOD-4 ripple/asynchronous upcounter.

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Asynchronous Counters (continue) • The asynchronous counter that counts 4 number starts from 00011011 and back to 00 is called MOD-4 ripple (asynchronous) up-counter. Next state table and state diagram Present State Q1Q0 00 01 10 11

Next State Q1Q0 01 10 11 00

00 11

01 10

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Asynchronous Counters (continue) • MOD-4 Asynchronous up-counter Q0 (LSB) 1 CLK

J

Q

1

CLK

K

Q1 (MSB)

J

Q CLK

Q

K

Q

CLK Q1 0

0

1

1

0

0

1

1

0

Q0 0

1

0

1

0

1

0

1

0

Binary 0  1  0

 2  3  0  1  10

2  3

Asynchronous Counters (continue) • The external clock is connected to the clock input of the first flip-flop (FF0) only. • So, FF0 changes state at the falling edge of each clock pulse, but FF1 changes only when triggered by the falling edge of the Q output of FF0. • Because of the inherent propagation delay through a flip-flop, the transition of the input clock pulse and a transition of the Q output of FF0 can never occur at exactly the same time. • Therefore, the flip-flops cannot be triggered simultaneously, producing an asynchronous operation. • The 2-bit ripple counter circuit above has four different states, each one corresponding to a count value.

Asynchronous Counters (continue) • A counter with n flip-flops can have 2 to the power n states. • The number of states in a counter is known as its mod (modulo) number. • Thus a 2-bit counter is a mod-4 counter. • A mod-n counter may also be described as a divide-by-n counter. • This is because the most significant flip-flop (the furthest flip-flop from the original clock pulse) produces one pulse for every n pulses at the clock input of the least significant flip-flop (the one triggers by the clock pulse). • Thus, the above counter is an example of a divide-by-4 counter.

Asynchronous Counters (continue) • MOD-8 Asynchronous up-counter C

1

J

Q CLK

K

Q

B

1

J

Q

A

1

J

CLK

K

CLK

Q

K

CLK A

0

B

0

C

0

Q

13

Q

Asynchronous Counters (continue) • Next state table and state diagram Present State ABC

Next State

000 001 010 011 100 101 110 111

001 010 011 100 101 110 111 000

0

ABC 7

1

6

2 5

3 4

14

Four bit up counter

15

Asynchronous 3 Bit Down Counter

Asynchronous Counters (continue) • So far, we have design the counters with MOD number equal to 2N, where N is the number of bit (N = 1,2,3,4….) (also correspond to number of FF) • Thus, the counters are limited on for counting MOD-2, MOD4, MOD-8, MOD-16 etc..

• The question is how to design a MOD-5, MOD-6, MOD-7, MOD-9 which is not a MOD-2N (MOD  2N) ? • MOD-6 counters will count from 010 (0002) to 510(1012) and after that will recount back to 010 (0002) continuously. 17

Asynchronous Decade counter

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Asynchronous Decade counter

Mod-12 Asynchronous counter

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Asynchronous Counters (continue) • Circuit diagram for MOD-6 ripple up-counter (MOD  2 N) C

1 CLK

J Q

B

1

J Q 1

A

J Q

CLK

CLK

CLK

K Q

K Q

K Q

CLR

CLR

CLR

Detect the output at ABC=110 to activate CLR. NAND gate is used to detect outputs that generates ‘0’! 21

• Disadvantages of Asynchronous Counters: – Propagation delay is severe for larger MOD of counters, especially at the MSB. – Existence of „glitch‟ is inevitable for MOD  2N counters.

– Difficult to design random counters (i.e.: to design circuit that counts numbers in these sequence 56723156723156….)

• Solution, use SYNCHRONOUS COUNTERS.

Synchronous Counters • For synchronous counters, all the flip-flops are using the same clock signal. • Thus, the output would change synchronously.

• Procedure to design synchronous counter as follows: STEP 1: Obtain the State Diagram. STEP 2: Obtain the Excitation Table using state transition table for any particular FF (JK or D). Determine # of FF used. STEP 3: Obtain and simplify the function of each FF input using K-Map. STEP 4: Draw the circuit.

Synchronous Counters • Design a MOD-4 synchronous up-counter, using JK FF. STEP 1: Obtain the State transition Diagram 0 3

00 1

2

Binary

11

01 10

STEP 2: Obtain the Excitation table, two JK FF are used. OUTPUT TRANSITION QN QN+1

Excitation table

Present State A B 0 0 0 1 1 0 1 1

0 0 1 1

   

Next State A B 0 1 1 0 1 1 0 0

0 1 0 1

FF INPUT J K

0 1 X X

X X 1 0

Flip-Flop inputs JA K A JB KB 0 X 1 X 1 X X 1 X 0 1 X X 1 X 1

STEP 3: Obtain the simplified function using K-Map B

A

0 0 0 1 X

B

1 1 X

A

JA = B

0 0 1 1 1

1 X 1

KA = B

B

B A

0 0 X 1 0

1 X X

A

JB = 1

0 0 X 1 X

1 1 1

KB = 1

STEP 4: Draw the circuit diagram

B (LSB) 1

A (MSB)

JB Q

JA Q

CLK

CLK

KB Q

KA Q

Synchronous counters • Design a MOD-4 synchronous down-counter, using JK FF?

STEP 1: Obtain the State transition Diagram 0 1

00 3

01

11

Binary

2

10

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Synchronous counters – Obtain the Excitation table. Two JK FF are used. OUTPUT TRANSITION QN QN+1

0 0 1 1

   

FF INPUT J K

0 1 0 1

0 1 X X

X X 1 0

Present St. A B

Next St.

A B

JA KA

JB KB

0 0 0 1 1 0

11 00 01

1x 0x x1

1x x1 1x

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Synchronous counters – Obtain the simplified function using K-Map B

A

0 0 1 1 x

B

1 0 x

A

JA =A’

B

A

0 0 1 1 1

0 0 X 1 1

1 X 0

KA =B’

B

1 X X

A

JB =1

0 0 X 1 X 30

1 1 1

KB =1

Synchronous counters – Draw the circuit diagram JA

Q A

CLK

KA Q JB

Q B

CLK

KB Q 31

3-Bit Synchronous Binary Counter • The J and K inputs of FF0 are connected to HIGH.

3-Bit Synchronous Binary Counter • FF1 has its J and K inputs connected to the output of FF0, and the J and K inputs of FF2 are connected to the output of an AND gate that is fed by the outputs of FF0 and FF1. • After 3rd clock pulse, both outputs of FF0 and FF1 are HIGH. • Positive edge of the 4th clock pulse will cause FF2 to change its state due to the AND gate. • Advantage of sync. counters is that there is no cumulative time delay because all flip-flops are triggered in parallel. • Maximum operating frequency for this counter will be significantly higher than for the corresponding ripple counter.

SYNCHRONOUS COUNTERS All flip-flops are clocked simultaneously • Mod-16 Synchronous Up-Counter

fmax 

1



ff

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SYNCHRONOUS COUNTER DESIGN • Mod-6 Up-Counter Using D-flip-flops – Design table

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MOD-6 UP-COUNTER – K-maps

– Final design

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Synchronous Up/Down Counters

Counter Design Procedure 1. Describe a general sequential circuit in terms of its basic parts and its input and outputs. 2. Develop a state diagram for a given sequence. 3. Develop a next-state table for a specific counter sequence. 4. Create a FF transition table. 5. Use K-map to derive the logic equations. 6. Implement a counter to produce a specified sequence of states.

Registers • Sample data using clock • Hold data between clock cycles • Computation (and delay) occurs between registers data in

D Q

D Q

clock

stable

may change

data in clock data out (Q)

stable

stable

stable

data out

Timing Methodologies (cont‟d) • Definition of terms – setup time: minimum time before the clocking event by which the input must be stable (Tsu) – hold time: minimum time after the clocking event until which the input must remain stable (Th) Tsu

Th

data

input

clock

there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized

D Q

clock stable changing data clock

D Q

Example - Circuit with Feedback • Output is a function of arbitrarily many past inputs

Example - Circuit without Feedback • Output is a function of the input sampled at three different points in time.

Shift Register  Shift registers are constructed using several flip-flop, connected in such a way to STORE and TRANSFER digital data.  Basically, D flip-flop is used. The input data (either „0‟ or „1‟) is applied to the D terminal and the data will be stored at Q during positive/negative-edge transition of the clock pulse. Negative edge transition of CLK

1

D Q

Q

1

Shift Register • One D FF is used to store 1-bit of data.

• Thus, the number of flip-flops used is the same with the number of bit stored. • Shift register mean that the data in each FF can be transferred/ move to other FF upon edge triggering of the clock signal. • Four types of data movement in shift register are:  Parallel in / parallel out (PIPO)  Serial in / parallel out (SIPO)  Serial in / serial out (SISO)  Parallel in / serial out (PISO)

Shift Register

 Serial Data Vs. Parallel Data movement Serial

Parallel

•Movement of N-bit data require N number of CLK pulses. Thus, the operation is slow. • Only one FF is required to be connected at the output terminal, thus only one wire is required.

• Require only one CLK pulse to transfer all N-bit of data. Thus, operation is faster than serial. •Required N number of connection to the output terminal, which is proportional to the number of bit. Thus, too many connection is required.

Parallel in / parallel out (PIPO)  Flip-flop configuration for PIPO register. D3

D2

D1

D0

D Q3

D Q2

D Q1

D Q0

CP

CP

CP

CP

CLK Q3

Q2

Q1

Q0

 PIPO data movement. CLK D3

1

0

1

1

D2

0

1

0

1

1 0

D1

1

1

1

0

1

D0

0

0

0

1

0

Q3

0

1

0

Q2

0

0

1

Q1

0

1

1

Q0

0

0

0

Parallel in / parallel out

Serial in / parallel out (SIPO)

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Serial in / Serial out (SISO)  Flip-flop connection for SISO. 1st CLK DIN

CLK

2nd CLK

3rd CLK

4th CLK

D Q0

D Q1

D Q2

D Q3

CP

CP

CP

CP

FF0

FF1

FF2

FF3

Parallel in / serial out (PISO)  Flip-flop connection for PISO. SHIFT/LOAD D0

CLK

D1

D2

D3

Serial data out

D Q0

D Q1

D Q2

D Q3

CP

CP

CP

CP

FF0

FF1

FF2

FF3

 PISO data movement. CLK D0

0

0

1

1

D1

0

1

0

1

1 0

D2

1

1

1

0

1

D3

1

0

0

1

1

SHIFT/ LOAD

Q3

0

1

1

0

0

1

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Shift Register Counters  A shift register counter is a shift register whose output being fed back (connected back) to the serial input.  This shift register would count the state in a unique sequence!  Two types of shift register counter:  The ring counter  The Johnson counter

Ring Counter Q3

Q2

Q1

Q0

Ring Counter (continue)

0 0

0

1

1 0

0

0

0 1

0

0

0 0

1

0

Ring Counter (continue)

Ring counters are used to construct “One-Hot” counters It can be constructed for any desired MOD number A MOD-N ring counter uses N flip-flops connected in the arrangement as shown in fig. a) In general ring-counter will require more flip-flops than a binary counter for the same MOD number

Johnson Counter Or Twisted-ring counter

Johnson counter constructed exactly like a normal ring counter except that the inverted output of the last flip-flop is fed back to first flip-flop

Johnson Counter (Continue)

A0

1

1

1

B 0

0

1

1

0

0

0

1

C

Johnson Counter (Continue)

Applications of shift registers

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Sequential Circuits Design steps

Topics Discussed • • • •

Characteristic equation for RS, D, JK & T FF. Design/excitation table for RS, D, JK & T FF. 3-bit synchronous counter design using T FF. Design of synchronous counter with the count sequence 0,3,2,4,1,5,7, and repeat using RS FF/T FF. • Design of synchronous counter that goes through the sequence 2,6,1,7,5, and repeat using D FF. • A FF has 3 inputs S, R, & T. no more than one of these inputs may be 1 at any time. S & R inputs behave as SR FF. T input behave as T FF. – Show a state graph for this FF – Write an equation for output Q+ in terms of S, R, T & Q

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