• Author / Uploaded
• Marcelinho Lambrese

Citation preview

4

3

2

1 REVISIONS DESCRIPTION

REV EA EB A B C

PROTOTYPE RELEASE MADE FROM 75832010W

CHANGE METER AND LIGHT DRIVERS PRODUCTION RELEASE CHANGE U11 IS: 32725300W WAS: 32724400W Q10,Q18,Q19 IS:48119291W WAS:48117891W

BY/DATE

CHK/DATE

RHC/25MAR09 RHC/03JUN09 GDW/01JUN10 RHC/09MAY11 RHC/29AUG11

--BJB\28APR10 BJB/12MAY11 BJB/30AUG11

D

D

SHEET 1 - INDEX SHEET 2 - POWER SUPPLY,POWER DOWN DETECTOR, 3.3V, 5V, 1.2V FPGA SHEET 3 - FPGA DIP SWITCH, LED, POWER BYPASS SHEET 4 - POWER DISTRIBUTION SHEET 5 - FPGA, TEST POINTS SHEET 6 - COM BOARD INTERFACE, TAG PORT SHEET 7 - EEPROM, TELL-TALE, DOORS SHEET 8 - CANDLE, HARD METERS, HANDLE, SPARE I/O SHEET 9 - SWITCH INPUT, SWITCH LAMPS, JACKPOT, W2G SHEET 10 - USB HUB SHEET 11 - NETPLEX INTERFACE

C

C

B

B

A

A CONFIDENTAL. DO NOT USE OR REPRODUCE WITHOUT AUTHORITY OF IGT COPYRIGHT IGT. ALL RIGHTS RESERVED. DRAWN

G WRIGHT CHECKED

B. BOUTTE APPROVED

G WRIGHT

INTERNATIONAL GAME TECHNOLOGY R

TITLE

PCB,WIDE SCRN DIST AND CNTRL,V4,SCH

DATE

23APR10 DATE

28APR10 DATE

28MAY10

9295 PROTOTYPE DRIVE RENO NV 89521

DWG_SIZE

C

DWG_NO

REV_LTR

758 320 11W NONE

4

3

2

1

C

SCALE

SHT

1

OF

11

4

3

2

1

POWER SUPPLY IN +12V

CR2 +24V

3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

BAT54

C16 0.01uF 25V

+12V

+5V +5V

SHIELDED

L11 1

SINE_IN_RAW

5

1

PEG3

RT8 1

L13 1 2 2.5A

2

5 R81 100K 1%

J11 1 2 3 4 5 6 7 8 9 10

BUFFER_SIN_IN

5

2X12 MFJ R293

1 2 3 4 5 6 7 8 9 10

VIN

1.1A

TO BRAIN BOX POWER SUPPLY +12V GND +12V (9.42A) +24V (3.6A) GND AC_SIN_IN GND +12V +24V GND

C186 0.1uF 16V X7R

C112 0.001UF 50V

U36

C3 10uF 25V

4

BOOST

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

SW

EN

FB

6

L9 3.9uH 1.44A

1

3

2

R21 2 2.5A

C183 0.1uF 16V

D

0 C252 22uF 6.3V

CR5 MBRM140

C253 22uF 6.3V

R72 5.23K 1%

2 C182 0.1uF 16V X7R

GND LM2734

2

D

+12VDC +12VDC +12VDC +12VDC +12VDC +12VDC +24VDC +24VDC +24VDC +24VDC +24VDC AC_SIN_IN 12VGND 12VGND 12VGND 12VGND 12VGND 12VGND 24VGND 24VGND 24VGND 24VGND 24VGND 24VGND

1

J32

R87 100K 1%

C111 0.001UF 50V

DS6 GREEN

1 2

DP56 40A 5V 400W Peak

5.0 V 750 MA MAX

1 R114 1K

R1 1K 1%

GND1

2X5 MINIMATE

0

A_GND

+5V

3.3V +3_3V

U12 IN

OUT

3

R22

0

GND1 GND2

1

+12V

C1 10UF 25V

+24V

M1 1 PCB STANDOFF NC

1 2 3 4 5 6 7 8

M2 1 PCB STANDOFF NC 3 AMPS ON EACH

M3

J12 1 2 3 4 5 6 7 8

GND GND +24VDC +12VDC +12VDC +24VDC GND GND

C39 0.1UF 16V

LM2937

2 4

C

2 C36 22UF 16V

DS7 GREEN

C38 0.1UF 16V

3.3V

C

150 MA MAX

1 R113 1K GND

POWER SUPPLY To Light Bars

2X4 SKT RECEPTACLE

1 PCB STANDOFF NC M4 1 PCB STANDOFF NC

3.3V

+5V

R112 1K

1.2V U1 1

R38

VIN

VOUT

+1_2V

5 0

C2 22UF 6.3V

C117 0.1UF 16V

3

EN

GND 2

NC

R144 1K NOSTUFF

4

ADP1710 C66 0.001UF 50V NOSTUFF

B

C90 22UF 6.3V

2 DS5 GREEN

C118 0.1UF 16V

1

1.2V FPGA 100 MA MAX

R145 2K NOSTUFF

R68

2.2K

B

3 1

Q1 MMBT3904 2

+12V

+12V OPTIONAL 3.3V

10VDC

R43 75K

R88 75K NOSTUFF

3.3V

R69 2.2K LMV331

3 1 2.5VDC

+

R199 10.2K NOSTUFF R413

5 4 2

U26 NOSTUFF

POWER_FAIL_EM

R222 15K

5

R80 100K NOSTUFF

1.05K NOSTUFF

33mv

1.2V R70 NOSTUFF

2.2K

3.3V C187 0.1uF 16V NOSTUFF

C24 0.001uF 50V NOSTUFF

C180 0.1uF 16V NOSTUFF

A

A CONFIDENTAL. DO NOT USE OR REPRODUCE WITHOUT AUTHORITY OF IGT COPYRIGHT IGT. ALL RIGHTS RESERVED. DRAWN

INTERNATIONAL GAME TECHNOLOGY R

TITLE

PCB,WIDE SCRN DIST AND CNTRL,V4,SCH

DATE

G WRIGHT CHECKED

B BOUTTE APPROVED

G WRIGHT

23APR10 DATE

28APR10 DATE

28MAY10

9295 PROTOTYPE DRIVE RENO NV 89521

DWG_SIZE

C

DWG_NO

REV_LTR

758 320 11W NONE

4

3

2

1

C

SCALE

SHT

2

OF

11

4

3

2

1

D

D

LED_[0:4]

LED_0

LED_1

LED_2

LED_3

LED_4

R290 681

R289 681

R288 681

R287 681

R286 681 3.3V

2

2 DS3 YELLOW

1

TAG CLOCK

DS22 YELLOW 1

2

2

SEL GROUP 0

2 DS1 ORANGE

DS21 YELLOW 1

TELL TALE SEL

1

DS2 ORANGE 1

EEPROM 0 SEL

3.3V

EEPROM 1 SEL

C4 10uF 25V

U18 119 136 86 95 40 61 14 23

C LED_0 LED_1 LED_2 LED_3 LED_4

112 111 113 110 142 123 80 97 53 35 33

1.2V

VCCO_00 VCCO_01 VCCO_10 VCCO_11 VCCO_20 VCCAUX_0 VCCO_21 VCCAUX_1 VCCO_30 VCCAUX_2 VCCO_31 VCCAUX_3 VREF_0A IO_L01N_0 IO_L02N_2 IO_L01P_0 IO_0 VREF_0B VREF_1A VREF_1B VREF_2 VREF_3 IP_L13P_3

22 52 VCCINT_0 94 VCCINT_1 122 VCCINT_2 VCCINT_3

36 66 108 133

C51 0.01UF 25V

C189 0.1uF 16V

C32 0.01UF 25V

C33 0.01UF 25V

C52 0.01UF 25V

C34 0.01UF 25V

C190 0.1uF 16V

C35 0.01UF 25V

C

3.3V GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13

9 17 26 34 56 65 81 89 100 106 118 128 137

C5 10uF 25V

C196 0.1uF 16V

C191 0.1uF 16V

C192 0.1uF 16V

C193 0.1uF 16V

C194 0.1uF 16V

C20 0.01UF 25V

C21 0.01UF 25V

C22 0.01UF 25V

C23 0.01UF 25V

C25 0.01UF 25V

XC3S50AN C6 10uF 25V

C18 0.01UF 25V

C197 0.1uF 16V

C10 0.01UF 25V

C19 0.01UF 25V

C200 0.1uF 16V

C198 0.1uF 16V

C17 0.01UF 25V

C199 0.1uF 16V

B

B

A

A CONFIDENTAL. DO NOT USE OR REPRODUCE WITHOUT AUTHORITY OF IGT COPYRIGHT IGT. ALL RIGHTS RESERVED. DRAWN

INTERNATIONAL GAME TECHNOLOGY R

TITLE

PCB,WIDE SCRN DIST AND CNTRL,V4,SCH

DATE

G WRIGHT CHECKED

B BOUTTE APPROVED

G WRIGHT

23APR10 DATE

28APR10 DATE

28MAY10

9295 PROTOTYPE DRIVE RENO NV 89521

DWG_SIZE

C

DWG_NO

REV_LTR

758 320 11W NONE

4

3

2

1

C

SCALE

SHT

3

OF

11

4

3

+12V

2

1

+24V

J41 1 2 3 4 5 6 7 8

D MAIN DOOR POWER

1 2 3 4 5 6 7 8

+12VDC +24VDC

D

5VCOMM J4

DP20 18.6A 13V

5V COMM IGND 12V COMM IGND IGND

DP1 26V 9.5A

2X4 VERTICAL MFJ

1 2 3 4 5

1 2 3 4 5

L15 1

2 2.5A

L16 1

2 2.5A

C204 0.1uF 16V

12VCOMM C119 0.1UF 16V

1X5 SL IGND

C114 10UF 25V

1 2

C86 0.1UF 16V

+24V C203 0.1uF 16V

IGND

DP55 40A 5V

C113 10UF 25V

DP19 18.6A 13V

IGND

IGND

J6 1 2 1 2

IGND

J42 1 2 3 4 5 6 7 8

TOP BOX POWER

1 2 3 4 5 6 7 8

DP8 26V 9.5A NOSTUFF

+12VDC IGND

IGND

+24VDC

2X4 VERTICAL MFJ

CABINET FAN SOURCE

1X2 VERTICAL MICROFIT

12VCOMM 5VCOMM J46

UPTI - BOARD

J22 1 1 2 2 3 3 4 4

FAN CAB POWER

+12VDC +24VDC

1 1 2 2 3 3 4 4

5VCOMM 12VCOMM

1X4 VERTICAL HEADER

2X2 MFJ VERTICAL

C

J47 1 1 2 3 2 4 3 4

5VCOMM IGND

12VCOMM

J48 1 1 2 2 3 3 4 4 J23 1 1 2 2 3 3 4 4

CAB. I/O POWER

5VCOMM 12VCOMM

+24VDC

12VCOMM

J50 1 1 2 2 3 3 4 4

1 2 3 4 5 6

J49 1 1 2 3 2 4 3 4

5VCOMM

12VCOMM

24V_A 24V_A +12V 24V_AGND 24V_AGND GND

1 2 3 4 5 6

2X3 VERTICAL MFJ

1X4 VERTICAL HEADER

5VCOMM

C

AUDIO SUPPLY J55

IGND

IGND

2X2 MFJ VERTICAL

+24V

1X4 VERTICAL HEADER

1X4 VERTICAL HEADER

+12VDC

+12V

A_GND

IGND

1X4 VERTICAL HEADER J20 1 1 2 2 3 3 4 4

BILL VAL POWER

IGND +12VDC +24VDC

2X2 MFJ VERTICAL

SERVICE LAMPS

12VCOMM J52 SW_12VC J21 1 1 2 2 3 3 4 4

DOOR POWER

B

1

+12VDC +24V

DP68 24V NOSTUFF

+24VDC

2X2 MFJ VERTICAL

2 IGND

R37 2.2K

+12V

12VCOMM

1 2 3 4 5 6

1 2 3 4 5 6

1X6 VERTICAL SL

B

5VCOMM IGND

R8 2.2K

R27 2.2K

R9 2.2K

R73 1K

J24 1 1 2 2 3 3 4 4

PRINTER POWER

+12VDC +24VDC DS9 GREEN

+24VDC

+12VDC

DS10 GREEN

12VCOMM

DS12 GREEN

DS11 GREEN

5VCOMM

2X2 MFJ VERTICAL

J56 1 1 2 2 3 3 4 4

BELLY DOOR POWER

IGND +12VDC +24VDC +12VDC

2X2 MFJ VERTICAL

+24VDC

J58 1 2 1 3 2 4 3 4

SPARE POWER

2X2 MFJ VERTICAL J5

A

SPARE POWER

1 1 2 2 3 3 4 4

+12VDC

A

+24VDC +12VDC

2X2 MFJ VERTICAL

+24VDC

J57 1 1 2 3 2 4 3 4

SPARE POWER

CONFIDENTAL. DO NOT USE OR REPRODUCE WITHOUT AUTHORITY OF IGT COPYRIGHT IGT. ALL RIGHTS RESERVED.

2X2 MFJ VERTICAL

DRAWN

INTERNATIONAL GAME TECHNOLOGY R

TITLE

PCB,WIDE SCRN DIST AND CNTRL,V4,SCH

DATE

G WRIGHT CHECKED

B BOUTTE APPROVED

G WRIGHT

23APR10 DATE

28APR10 DATE

28MAY10

9295 PROTOTYPE DRIVE RENO NV 89521

DWG_SIZE

C

DWG_NO

REV_LTR

758 320 11W NONE

4

3

2

1

C

SCALE

SHT

4

OF

11

4

3

2

1

FPGA AND RESET

3.3V

3.3V C213 0.1uF 16V

R53 681

2

OSCILLATOR BY-PASS

R249

C210 0.1uF

4 VDD

3 OUT Y1

EN 1

GND 2

49.9

CLK30MHZ TAG_CLOCK

GCLK10

125 GCLK6 127 GCLK7

130

SPI TRISTATE

10 5

D

SPI TRISTATE

1

D TP50

R339 4.7K

16V

SWTB_[0:15]

7

9

SWTB_0 SWTB_1 SWTB_2 SWTB_3 SWTB_4 SWTB_5 SWTB_6 SWTB_7 SWTB_8 SWTB_9 SWTB_10 SWTB_11 SWTB_12 SWTB_13 SWTB_14 SWTB_15

3 4 5 6 7 8 10 11 12 13 15 16 18 19 20 21

IO_L02_3 IO_L01P_3 IO_L02N_3 IO_L01N_3 IO_L03P_3 IO_L03N_3 IO_L04P_3 IO_L04N_3 IO_L05P_3 IO_L05N_3 IO_L06P_3 IO_L06N_3 IO_L07P_3 IO_L08P_3 IO_L07N_3 IO_L08N_3

TAG_[0:5] TAG_0 TAG_1 TAG_2 TAG_3 TAG_4 TAG_5

TAG_CS[0] TAG_CS[1] TAG_CS[2] TAG_CLOCK TAG_DATA_FROM_DISTBD TAG_DATA_TO DISTBD

R202

24 25 27 28 29 30

49.9

C

48 HARD METERS

IO_L09P_3 IO_L09N_3 IO_L10P_3 IO_L11P_3 IO_L10N_3 IO_L11N_3 IO_L05N_2

SSI_CHNL_1_[0:2]

8,9

SSI_CHNL_1_0 SSI_CHNL_1_1 SSI_CHNL_1_2

HARD_METER_CE

9

3.3V

MASTER SPI MODE

TAG_SE_[0:5]

6

4.7K

124 GCLK4 126 GCLK5

RP1

3.3V

3.3V

DS32 ORANGE

U18

1 2 3 4 6 7 8 9

C26 0.001uF 50V

134 135 IO_L10P_0 IO_L10N_0 138IO_L11P_0 139 IO_L11N_0

IO_L08P_1 IO_L08N_1 IO_L09P_1 IO_L09N_1 IO_L10P_1 IO_L11P_1 IO_L12P_0 IO_L02P_1 IO_L01P_1 IO_L02N_1 IO_L01N_1 IO_1 IO_L05P_1 IO_L05N_1 IO_L06P_1

96 98 99 101 102 103

R28 R29 R30 R31

49.9 49.9 49.9 49.9

R32

49.9

TAG_SE_0 TAG_SE_1 TAG_SE_2 TAG_SE_3 TAG_SE_4 TAG_SE_5

141

79 87 88 90

NOSTUFF

M0

R318

0

STUFF

M1

R315

0

STUFF

M2

R444 10K

R441 10K

R449 10K

PLACE AS CLOSE TO FPGA PART AS POSSIBLE J13

R162

8

SPAREIN1 MTR_DIS_NOT SPAREIN2

R314

0

NOSTUFF

VS0

R316

0

STUFF

VS1

R317

0

NOSTUFF

VS2

TMS TDI TDO TCK

1 2 3 4 5 6 7 8

0 NOSTUFF

3.3V GND

2X4 HEADER NOSTUFF

8 9 8 U18

R203 R219

49.9 49.9

TTFPGA_1 TTFPGA_2

7 7

S2 3.3V

91 92 93 104 105 120

TELL_TALE_RESET COMM_ENABLE_NOT

121

BELL_DRIVE

38 37 M0 39 M1 M2

3.3V

R10 4.7K

7 6

1

1

2

2

7

3

3

6

4

4

5

8

3.3V IO_RESET_1 IO_RESET_2

TMS 1 TDI 2 TD0 107 TCK 109

45 44 VS0 43 VS1 VS2

3.3V

3.3V

73

9 8 R341 4.7K

8

R340 4.7K

DONE

CSO_B PROG_B DIN CSI_B 67 INIT_B CCLK

R321 332

3.3V

3.3V

R117 1K NOSTUFF

144 3.3V

IO_L05N_0

R440 10K

3.3V

R7 4.7K IO_L07P_1 IO_L06N_1 IO_L07N_1 IO_L10N_1 IO_L11N_1 IO_L05P_0

0

TELL_TALE_CS EEP1_CS EEP2_CS TAG_SPI_CLOCK TAG_SPI_RETURN_DATA TAG_SPI_DATA

CANDLE_DETECT

75 76 77 78

R313

41 71 62 72

3.3V

R343 4.7K STUFF

FPGA CONFIG

R155 4.7K STUFF

C

49.9 STUFF

R247

3.3V

XC3S50AN

3.3V 3.3V

9

114 115 IO_L04P_0 116 IO_L03P_0 117 IO_L04N_0 IO_L03N_0 49

IO_L06N_2

IO_L08N_0 IO_L08P_0 IO_L09N_0 IO_L12N_0

131 129 132 143

IO_L11N_2 64 IO_L12N_2 68 IP_0 140

NETPLEX_RST

R76 4.7K

4

R243 49.9 STUFF

TEST0 TEST1 TEST2 TEST3

TP17

R253 49.9 STUFF

TP18

TP26

DIPSW_0 DIPSW_1

R223 1K NOSTUFF

R82 10K

R83 10K

R84 10K

1 2 CS 3 SO WP

R252 49.9 STUFF R116 1K STUFF

3.3V

R118 1K STUFF

U56

8

SSI_CHNL_0_0 SSI_CHNL_0_1 SSI_CHNL_0_2

B_LAMP_CE

69 70

VCC

9

IO_L13P_2 IO_L14P_2

GND

SSI_CHNL_0_[0:2]

7 HOLD 6 SCK 5 SI

J31

R323

0 STUFF

EXT_IN_[0:1]

9

EXT_IN_0 EXT_IN_1

31 32 46 47

3.3V

R107

42 RDWR_B

4.7K

B

IO_L12P_3 IO_L12N_3 IO_L05P_2 IO_L06P_2

IO_L03P_1 IO_L04P_1 IO_L03N_1 IO_L04N_1 IO_L09P_2 IO_L10P_2 IO_L09N_2 IO_L10N_2 IO_L07P_2 IO_L07N_2 IO_L08P_2 IO_L08N_2

74 SUSPEND 63 AWAKE

82 83 84 85 57 58 59 60

CANDLE_1 CANDLE_2 CANDLE_3 CANDLE_4

50 51 54 55

DIPSW_2 POWER_FAIL_EM DIPSW_3 SIN_IN

R54 681

8 8 8 8

HNDLREL SPAREOUT1 SPAREOUT2

R52 120

8 8 8

PLACE AS CLOSE TO FLASH PART AS POSSIBLE

2 DS23 YELLOW

2 DS8 ORANGE

1

2

DONE 3

1

SET PROGRAM

R61 1 2

Q4 IRLM2402

120 HIGH WHEN CONFIGURED

XC3S50AN R322 332 3 R402

SETPROG

1

Q2 C27 0.001uF 50V

IRLM2402

120 R342 4.7K

BUFFER_SIN_IN

4

2

6 8 3.3V 10 HANDLESW R154 10K

12

1

8

DIPSW_1

2

2

7

3

3

6

4

4

A

R39 100K

3

5

NOSTUFF

C30 0.001uF 50V

C216 0.1uF 16V

C29 0.001uF 50V

C215 0.1uF 16V

C28 0.001uF 50V

4A

5Y

5A

6Y

6A

Q3 1

C214 0.1uF 16V

5

1 R64 10.5K

DP77 24V

9

2

11 13 MASTER_RESET 6 0 = MASTER RESET

HNDLSW

8

CR4 BAT54

A RESET 26 MS

CONFIDENTAL. DO NOT USE OR REPRODUCE WITHOUT AUTHORITY OF IGT COPYRIGHT IGT. ALL RIGHTS RESERVED.

3.3V R403

C217 0.1uF 16V

4Y

2 33K

3

1 R163 47K

C31 0.001uF 50V

3A

SINE_IN_RAW

1

3.3V

1

DIPSW_3

3.3V

2A

3Y

74LVC14AD

DIPSW_0

DIPSW_2

R89 1A

2Y

R156 10K S1

3.3V

1Y

7 GND

2

VCC 14

FLASH BY-PASS U13

3.3V

C212 0.1uF 16V

3.3V

DIPSW_[0:3]

R115 10K

B

3.3V

2

R111 10K

120

3 2

C102 0.22UF 10V

DRAWN

IRLM2402

G WRIGHT

R344 4.7K

INTERNATIONAL GAME TECHNOLOGY R

CHECKED APPROVED

PCB,WIDE SCRN DIST AND CNTRL,V4,SCH

G WRIGHT

23APR10 DATE

28APR10 DATE

28MAY10

9295 PROTOTYPE DRIVE RENO NV 89521

TITLE

DATE

B BOUTTE

DWG_SIZE

C

DWG_NO

REV_LTR

758 320 11W

3

2

1

C

SCALE

NONE

4

3.3v GND

2X4 HEADER STUFF

3.3V JACKPOT RESET, W2G

TMS TDI TDO TCK

1 2 3 4 5 6 7 8

AT25F2096 STUFF

4

BUTTON LAMPS

SHT

5

OF

11

4

3

2

1

12VCOMM 5VCOMM COMM_BUSS_[0:23] J30

---->

R397

100 R396

R393

PCI_COMM_9 PCI_COMM_10 PCI_COMM_11

0

PCI_COMM_12 PCI_COMM_13 PCI_COMM_14

100 R392

R391

100

100

R386

1 23 24

PCI_COMM_6 PCI_COMM_7 PCI_COMM_8

PCI_COMM_15 PCI_COMM_16 PCI_COMM_17 R387

100

R378

100

2 22

A0 A1 A2 A3 A4 A5 A6 A7 T/R OE

R477 332

R367

R351 10K

R350 10K

R349 10K

R348 10K

TTLDCD-7 TTLRXD-8 TTLCTS-8 TTLDCD-8 PCI_COMM_13 PCI_COMM_21 PCI_COMM_20 PCI_COMM_19

0

SPIPORTSI+ SPIPORTSCK+ SPIPORTSISPIPORTSCK-

PCI_COMM_13 PCI_COMM_21 PCI_COMM_20 PCI_COMM_19

COMM_BUSS_0 COMM_BUSS_2 COMM_BUSS_4 COMM_BUSS_6 COMM_BUSS_8 COMM_BUSS_10 COMM_BUSS_12 COMM_BUSS_14

74LVX4245

---->







PCI_COMM_5 ----> PCI_COMM_4 ----> PCI_COMM_6 ----> PCI_COMM_11 ----> PCI_COMM_10 ----> PCI_COMM_12 ----> PCI_COMM_17 ---->

1 23 24

R518 4.7K 0603

R362

B

10K

3.3V

2

TAG_1

R183 R184 R185 R186

3.3V +5V

TAG_2 U20

TTLRXD-5