8255 Interface

8255 PPI (Programmable Peripheral Interface) (Parallel Port Interface) 8 Data RD WR RESET CS A1 A0 8 Port A Port B {

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8255 PPI (Programmable Peripheral Interface) (Parallel Port Interface) 8

Data RD WR RESET CS A1 A0

8 Port A Port B

{

8 4

CH

Port C

CL

4

Addressing the 8255 A1 A0 = 00 = 01 = 10 = 11

PORT2A PORT2B PORT2C STAT2

Port A ; IN, OUT 8 bits at a time Port B ; IN, OUT 8 bits at a time Port C ; IN, OUT 8 bits at a time Control Register; Write ONLY!

= = = =

From IO.EQU 0224h ;Port A 0225h ;Port B 0226h ;Port C 0227h ;8255-5

externally available externally available externally available # 2A / Status Register

Interfacing the 8255 8088

20 Address Only A19 A18 Address/Data A17 AD7 A16 AD6 A15 AD5 A14 + AD4 A13 AD3 A11 AD1 A10 AD0 A9 A8

Address and Data lines are multiplexed in the 8088

Address and Data Buses 8088

20 ALE

Address Latch

20-bit address bus

8 Data Transceiver

ALE is Address Latch Enable

8-bit data bus

Addressing the 8255 IO/M 8-bit data bus 20-bit address bus

A15 -A2 A1 A0

8

Data

Port A

RD WR RESET Logic Circuit

CS A1 A0

Port B

{

Port C

8 4

CH CL

4

Logic Circuit • Inputs to the Logic Circuit – address lines A15 - A2 (the I/0 address space is 216 addresses, and A1 and A0 are used for the chip’s address lines) – the 8088’s IO/M line HIGH denotes an IO instruction (IN, OUT) LOW denotes a memory access instruction (i.e., MOV) • Output of the logic circuit – a single low value from the 15 inputs (a NAND or OR gate) to activate the Chip Select • The connections for A15-A2 fix the chip’s address in I/O space

8088 pins The 8088 is a 16-bit microprocessor: Internal registers and buses are 16 bits wide 8 address/data lines 12 addresslines IO/M RD and WR

Minimum mode • In minimum mode, the 8088 is the only microprocessor in the circuit. It can assume that it has control of memory, address, and data buses • In maximum mode, the 8088 is configured for multiple microprocessors. The function of pins is changed to provide processor-to-processor communication

8255 PPI (Programmable Peripheral Interface) (Parallel Port Interface) 8

Data RD WR RESET CS A1 A0

8 Port A Port B

{

8 4

CH

Port C

CL

4

Reset • A single reset line is connected to all chips in the system (8088, 8255, 8253, etc.) • Reset puts the chip in a known state • Pushing the reset button on your computer generally activates a 555 timer circuit that outputs a high pulse for a short period of time • On Reset, the 8088 goes to fixed addresses (ROM chips) where boot sequence instructions are stored.

A/D • Step 1: • Step 2:

• Step 3: • Step 4: • Step 5:

Call SetupAD Mov al, channel# Mov dx, WRTCH1 Out dx, al Mov dx, STBAD1 Out dx, al ; or IN dx, al Mov CX, delaycount L1: Loop L1 Mov dx, RDCH1 IN al, dx

A/D #2 • After an A/D value is read, many algorithms will need to compare the analog voltage to some target analog voltage • For the computers in Anderson 307, the conversion is 18 mv per 1-bit change. • If Vtarget is the target voltage in volts, it must be converted to a target count Multiply Vtarget * 1000 ; target in millivolts Divide target by 18 ; equivalent count • Careful use of word-wide vs. byte-wide multiply and divide is essential • For critical applications may need to investigate remainder to round count to nearest integer.

D/A • A voltage proportional to the count appears on the D/A output Mov dx, DAC# Mov al, dacount Out dx,al • At times the program must make a voltage-to-count conversion (previous slide).

Homework for Thursday, October 28 • Write a commented 8088 assembly language procedure that will output a “clipped” signal that follows an input signal. • The procedure should operate continuously until a key is pressed • Assume that the input signal is in the range 0 - 5 volts the A/D has been calibrated at 20 mv per 1-bit change the D/A has been calibrated at 25 mv per 1-bit change the level to clip the output at is stored in variable, CLIPLEVEL, and is given in units of tenths of volts (0.1 v) • That is, if CLIPLEVEL = 10, then the output signal should be in the range 0 - 1 volt.