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VERILOG HDL Gate Level Modeling

What is Verilog ? • Verilog is a Hardware Description Language (HDL). – Design and document electronic systems. – Supports different levels of abstraction. • Structural or Gate Level • Register Transfer Level (RTL) • Behavioral

– Higher Level of abstraction improves productivity – Technology independent specification. – Syntax is similar to C

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History of Verilog • Gateway Design Automation. – Proprietary language developed in 1985 – Developed to SIMULATE only • Product was VERILOG-XL

– Synthesis capabilities were added latter on – Became very popular

• Cadence Design Automation – Acquired it in 1989.

• Open Verilog International (OVI) – Cadence makes it public in 1990

• IEEE Verilog standard 1364 in 1995 ECE301 VLSI System Design

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Verilog Basic • Verilog – case sensitive language • temp, Temp, TEMP are different names

– keywords are lower case – Comments are specified as • // This is a single line comment • /* This is how a multiple-line comment is specified in Verilog….. */ – Multiple line comments can’t be nested

– Semicolon(;) are line terminators – Notice the similarity to ‘C’ ECE301 VLSI System Design

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Four Valued Logic • • • •

Verilog’s bit can take 4 values Logic high (1) Logic low (0) High Impedance (z) – high impedance state of tristate.

• Unknown (x) – Model conflict or un-initialized state – is only a debugging aid

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Structural Model • Specify the structure of design – gate primitives – connecting wires //Example of 2:1 mux module mux (y, a, b, sel ); output y ; input a, b, sel ; wire y1, y2, sel_n ; not A1 (sel_n, sel); and A2 (y1, a, sel_n); and A3 (y2,b, sel); or A4 (y,y1,y2); endmodule

Single Line Comment Component Interface

Gate & Connections

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Module • Basic unit used to specify a hardware entity. • Nesting of modules is not allowed. • Defines interface module_name module mux (y, a, b, sel ); output y ; Interface list input a, b, sel ; a wire y1, y2, sel_n ; MUX b not A1 (sel_n, sel); and A2 (y1, a, sel_n); and A3 (y2,b, sel); sel or A4 (y,y1,y2); Denotes end of module description endmodule ECE301 VLSI System Design

y

7

Identifiers • Name given to objects for referencing – example mux, y, a, b, sel

• Identifier naming rules – can be 1023 characters long – cannot be a VERILOG reserved keyword • module, endmodule, input etc.

– First character must be a alphabet or underscore – Can contain alphanumeric, underscore (_), or $. – Names must be sensible and improve readability. • ASH is also a legal module name

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Port Declaration • Used to specify the port direction. – input Input port – output Output port – inout Bi-directional port module mux ( y, a, b, sel ); output y ; Port input a, b, sel ; Declawire y1, y2, sel_n ; ration not A1 (sel_n, sel); and A2 (y1, a, sel_n); and A3 (y2,b, sel); or A4 (y,y1,y2); endmodule

Interface list

a b

ECE301 VLSI System Design

MUX

y

sel

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Port Connection Rules • net and reg are data types in Verilog – will explain them input port reg or net

output port

MODULE reg or net

net

net

net net

ECE301 VLSI System Design

inout port

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Data types • Net : is not a keyword but represents a class – wire, wand, wor, tri, triand, trior, trireg

• Used for connection. – Values should be continuously driven module mux (y, a, b, sel ); output y ; input a, b, sel ; wire y1, y2, sel_n ; not A1 (sel_n, sel); and A2 (y1, a, sel_n); and A3 (y2,b, sel); or A4 (y,y1,y2); endmodule

•wire is the default data type •wire and tri are exactly identical •separate names indicate purpose. •Net value is ‘x’ for multiple drivers •Net value is ‘z’ without any drivers

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Data types …contd • reg represent data storage element – need not be continuously driven

• Retain value until driven again • Default value is ‘x’ • Don’t confuse them with Hardware – need not infer a register, latch or flip-flop !!!

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Logic Gate Primitives • Verilog has predefined primitives for logic gates • Pins of primitive gates are expandable module mux (y, a, b, sel ); output y ; input a, b, sel ; wire y1, y2, sel_n ; not A1 (sel_n, sel); and A2 (y1, a, sel_n); and A3 (y2,b, sel); or A4 (y,y1,y2); endmodule

Supported Gates are AND : and (out, in1, in2,……inN) ; OR : or (out, in1, in2,……inN); XOR : xor (out, in1, in2,……inN); NAND : nand (out, in1, in2,……inN); NOR : nor (out, in1, in2,……inN); XNOR : xnor (out, in1, in2,……inN); BUFFER : buf (out1, …., outN, in); Inverter : not (out1,….. , outN, in);

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Instance • Instantiation is the process of calling a module – 4 gates are instantiated in our mux example

• The referred module are called instances – 2 instance of AND and 1 instance each of OR & NOT module mux (y, a, b, sel ); output y ; input a, b, sel ; wire y1, y2, sel_n ; not A1 (sel_n, sel); and A2 (y1, a, sel_n); and A3 (y2,b, sel); or A4 (y,y1,y2); endmodule

• instance_name – A1, A2, A3 & A4

• Positional Instantiation – not (out, in) – not (sel_n, sel)

sel

in

ECE301 VLSI System Design

out

sel_n

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Question • Design a 4-to-1 mux using 2-to-1 mux • Write the verilog code for the same – Hint : instantiate the 2-to-1 mux from our example a b c d

mux4_1 sel1 sel0 -> y 0 0 -> a 0 1 -> b 1 0 -> c 1 1 -> d

sel0

y

sel1

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Answer module mux4_1 (y, a, b, c, d, sel0, sel1 );

Named Instantiation is RECOMMENDED

output y ;

Predefined Primitives can use only positional instantiation

input a, b, c, d, sel ; wire y1, y2 ; mux M1 (.y(y1), .a(a), .b(b), .sel(sel0));

mux M1 (y1, a, b, sel0);

mux M2 (.y(y2), .a(c), .b(d), .sel(sel0));

mux M2 (y2, c, d, sel0);

mux M3 (.y(y), .a(y1), .b(y2), .sel(sel1));

mux M3 (y, y1, y2, sel1);

endmodule

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Vector • Also known as BUS in hardware – Group of signals

module mux4_1 (y, in, sel );

Syntax [MSB:LSB]

output y ; input [3:0] in ; input [1:0] sel

2-bit wide bus

wire y1, y2 ;

Bit Select of a bus

wire [1:0] sel; wire [3:0] in mux M1 (.y(y1), .a(in[0]), .b(in[1]), .sel(sel[0]) ); mux M2 (.y(y2), .a(in[2]), .b(in[3]), .sel(sel[0]) ); mux M3 (.y(y), .a(y1), .b(y2), .sel(sel[1]) ); endmodule ECE301 VLSI System Design

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Unconnected Ports • Unused input port – Always connect to either ‘1’ or ‘0’ – Value such that functionality is not effected

• Unused output port – Leave it floating

Example module parity_gen(even_pty, odd_pty, datain) ; parity_gen P1 (parity, ,datain) ; parity_gen P1 (.datain(datain), .even_pty(parity)); ECE301 VLSI System Design

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Assignment 1 •

Write Verilog Gate or Structural code for – 16 to 1 mux • using mux4_1

– 3 line to 8 line decoder – BCD-to-7 segment decoder – Half Adder – Full Adder • using logic gates • using the above defined Half Adder http://www.angelfire.com/electronic/AnandVenkat/verilog.html ECE301 VLSI System Design

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Tristate Gate Primitive • Tristate Gate Primitives – – – –

bufif1(out,in,ctl); : Tristate buffer with active high enable bufif0 (out,in,ctl); : Tristate buffer with active low enable notif1(out,in,ctl); : Tristate inverter with active high enable notif0 (out,in,ctl); : Tristate inverter with active low enable

• Example module guess_me ( y, a, b, sel ) ; input a, b, sel ; output y ; bufif0 B2 (y,a,sel) ; bufif1 B1 (y,b,sel) ; endmodule

What logic function does this module perform ?

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Advanced Nets • wor and trior models wired OR connection – supports multiple drivers to be active at the same time – the net value is ‘1’ if any driver value is ‘1’

• wand and triand models wired AND connection – supports multiple drivers to be active at the same time – the net value is ‘0’ if any driver value is ‘0’ a b

&

wor

|

b

wand

y c

c d

&

|

d

y = ( a ? b ) ? ( c ? d)

y = ( a ? b ) ? ( c ? d)

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Example Code a

a b

&

wor

|

b

wand

y c

c

&

d

d

module and_or (y, a, b, c, d );

|

module or_and (y, a, b, c, d );

output y ;

output y ;

input a, b, c, d ;

input a, b, c, d ;

wor

wand

y;

y;

and A1 (y, a, b);

or A1 (y, a, b);

and A2 (y, c, d);

or A2 (y, c, d);

endmodule

endmodule ECE301 VLSI System Design

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Advanced Nets • supply1 models power supply connection – the value of these net is always ‘1’ – synthesizer treats this net as logic 1.

• supply0 models power ground connection – the value of these net is always ‘0’ – synthesizer treats this net as logic 0.

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Advanced Nets • tri0 models resistive pulldown – similar to tri expect that the net value is ‘0’ if no drivers

• tri1 models resistive pullup – the net value is ‘1’ if no drivers

• No synthesis support module or (y, a, b); output y ; input a, b ; tri0 y ; supply1 vdd; bufif1 B1 (y, vdd, a); bufif1 B2 (y, vdd, b); endmodule

module nor (y, a, b); output y ; input a, b ; tri1 y ; supply0 gnd; bufif1 B1 (y, gnd, a); bufif1 B2 (y, gnd, b); endmodule

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Advanced Nets • trireg model net with capacitance – the net holds (remembers) the last driven value if no drivers – models bus-keeper circuit trireg – No synthesis support out

in sel in sel

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MOS Gate Primitive • Transistor level primitves (Non-Synthesizable) – Model MOS transistor as switches – nmos(out,in,ctl); – pmos(out,in,ctl); in

in

ctl nmos

ctl out

pmos

Active high enable switch

out

Active low enable switch

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MOS example • CMOS NOT GATE module not_mos ( out, in ) ; input in ; output out ; in supply1 vdd ; supply0 gnd ; nmos N1 (out,gnd,in) ; pmos P1 (out,vdd,in) ; endmodule

ECE301 VLSI System Design

Vdd

out

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Assignment 2 •

Write Verilog code using MOS primitives for – 2 input CMOS AND gate – 2 input CMOS XOR gate – 3 input CMOS OR gate – 3 input CMOS gate with boolean expression • Y=A.B+C

– CMOS Tristate inverter with active high enable

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CMOS Gate Primitive • CMOS switch model – cmos(out, in, nctl, pctl) ; – Preferred over nmos or pmos switch. Why ? sel_n

• Example module cmos_mux ( y, a, b, sel ) ; input a, b, sel ; output y ; wire sel_n; not_mos (sel_n, sel) ; cmos C1 (y,a,sel_n, sel) ; cmos C2 (y,b,sel, sel_n) ; endmodule

a sel

y

b sel_n

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Transmission Gate Primitive • Transmission gate (Bi-directional) – Buffer : tran ( inout, inout ) ; – Tristate Buffer with active high enable : tranif1(inout,inout,ctl) – Tristate Buffer with active low enable : tranif0(inout,inout,ctl) module guess_me ( y, d, en ) ; input d, en ; output y ; wire y1, y2; not_mos N1 (y, y1) ; not_mos N2 (y2, y); tranif1 C1 (y1, d, en) ; tranif0 C2 (y1,y2, en) ; endmodule

What logic function does this module perform ?

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Misc Gate Primitive • Pullup – pullup(out) – Net out is high if no drivers are active – Else the net has the driven value

• Pulldown – pulldown(out) – Net out is LOW if no drivers are active – Else the net has the driven value

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Assignment 3 • Design and Write a Verilog structural code using transistor primitives for : – Design AND and OR gate using 1 tristate buffer and pullup/pulldown primitive – Design a rising edge D FF using transmission gate – Design a falling edge D FF with asynchronous active low reset using cmos gates – Design a falling edge J-K Flip Flop with active high reset using the cmos D FF defined above – Design a falling edge J-K Flip Flop with active high preset using the JK FF defined above

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