• Author / Uploaded
• Robert Betz

Citation preview

ELEC3250 Notes - Power Electronics1 R.E. Betz School of Electrical Engineering and Computer Science University of Newcastle, Australia. email: [email protected] c

2012 April, 2012

1

First created: July 20, 2005 Revised on 2012-04-30 00:27:06 +1000 (Mon, 30 Apr 2012) by R.E. Betz SVN Version: 513

ii

Preface The notes in this document are for a course in the School of Electrical Engineering and Computer Science at the University of Newcastle, Australia. This course covers a number of topics that can be broadly grouped under the title of “power electronics”. The first section of the course will look at switch mode power supplies in their various forms. The main structures for switch mode power supplies will be considered. Again practical issues will be emphasised. Design of the magnetics for switching supplies will be considered, as well as some control issues. The control issues are only briefly considered due to the lack of background of some students doing the course. The second part of the course considers high powered converter and inverter topologies. There will be an emphasis on the grid connection of converter technologies. An introduction to matrix converters is presented. Issues such as commutation, modulation strategies, and devices are covered. There are several appendices covering some useful topics which may be useful in the context of the remainder of these notes. It should be noted that these notes are constantly being added to, altered, correctly, clarifications added – in other words they are a work in progress. The latest version can be downloaded from anonymous ftp at: ftp://vcs2.newcastle.edu.au/Elec3250_Power_Electronics/elec3250_notes. pdf.

Robert E. Betz – Newcastle, Australia, April, 2012.

iv

Revision History April-May 2012 (REB) Made corrections and added new material on Space Vectors. April-May 2011 (REB) Added new chapter on grid interfacing and renewables. March 11 2011 (REB) Did some minor conversions of the file to allow operation in Subversion. Have also fixed up some minor typos that were found last year. July 30 2010 (REB) Made a few wording error corrections in the first chapter. Minor typos really. July 29 2010 (REB) Typo corrections from last year were made. Added a small section on the linear interpretation of switching poles as a DC-DC transformer. July 23 2009 (REB) Have added a number of sections. A whole section on matrix converters added. A new introductory chapter on Switching Basics added, several Appendices added – space vectors, Syncrel inductances, imaginary power. July 25, 2008 (REB) Started adding a section on matrix converters. Still incomplete. July 24, 2008 (REB) Have converted the original Latex notes to Lyx. Complete compilation achieved. August 1, 2005 (REB) The initial distribution version for the students. Some additions have been made for snubbing circuits, but at this stage these additions are incomplete. There have also been some changes made to the Appendix on second order circuits. July 20, 2005 (REB) The initial version of these notes was constructed from the notes that were developed for Elec3230. The main difference with the current set of notes is that they no longer include the section on digital switching and printed circuit boards. This initial version basically was the Elec3230 notes with the digital switching cut out. As the notes develop new sections will be added with respect to high power power electronics.

vi

Contents List of Figures

xv

List of Tables

xxiii

Nomenclature

xxv

I

Switched Mode Power Supplies

1 Switching Basics 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Why Use Switching? . . . . . . . . . . . . . . . . . . . . 1.3 Taxonomy of Power Electronic Systems . . . . . . . . . 1.3.1 Naturally Commutated Systems . . . . . . . . . 1.3.2 Forced Commutated Systems . . . . . . . . . . . 1.3.2.1 Linearising the Non-linear System . . . 1.3.2.2 Basics of PWM and Frequency Spectra 1.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . .

1 . . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

2 Fundamental Topologies 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Taxonomy of Switch Mode Converters . . . . . . . . . . . . . . . 2.3.1 Step-down or Buck Converters . . . . . . . . . . . . . . . 2.3.2 Step-up or Boost Converters . . . . . . . . . . . . . . . . 2.3.3 Buck–Boost Converters . . . . . . . . . . . . . . . . . . . 2.3.4 Cúk Converters . . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 Full Bridge Converters . . . . . . . . . . . . . . . . . . . . 2.4 Basic Analysis of Switch Mode Converters . . . . . . . . . . . . . 2.4.1 Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 Basic PWM Generator . . . . . . . . . . . . . . . . . . . . 2.4.3 Simplified Analysis of the Buck Converter . . . . . . . . . 2.4.3.1 Continuous Conduction Mode . . . . . . . . . . 2.4.3.2 Boundary between Continuous and Discontinuous Conduction . . . . . . . . . . . . . . . . . . 2.4.3.2.1 Discontinuous Current with Constant Vd . . . . . . . . . . . . . . . . . . . . .

1-1 1-1 1-2 1-4 1-4 1-6 1-8 1-10 1-18 2-1 2-1 2-1 2-2 2-2 2-4 2-5 2-7 2-9 2-11 2-11 2-11 2-14 2-14 2-16 2-18

viii

CONTENTS 2.4.3.2.2

Discontinuous Current with Constant Vo . . . . . . . . . . . . . . . . . . . . . 2-19 2.4.3.3 Output Ripple . . . . . . . . . . . . . . . . . . . 2-23 2.4.3.4 Simulation . . . . . . . . . . . . . . . . . . . . . 2-25 2.4.4 Simplified Analysis of the Boost Converter . . . . . . . . 2-28 2.4.4.1 Continuous Conduction Mode . . . . . . . . . . 2-28 2.4.4.2 Boundary between Continuous and Discontinuous Conduction . . . . . . . . . . . . . . . . . . 2-28 2.4.4.2.1 Discontinuous Current with Constant Vd .2-31 2.4.4.3 Simulation . . . . . . . . . . . . . . . . . . . . . 2-33 2.4.5 A Brief Look at the Buck-Boost Converter . . . . . . . . 2-36 2.4.6 A Brief Analysis of the Cúk Converter . . . . . . . . . . . 2-36 2.4.7 Full Bridge dc-dc Converter . . . . . . . . . . . . . . . . . 2-38 2.4.7.1 Bipolar Switching . . . . . . . . . . . . . . . . . 2-39 2.4.7.2 Unipolar Switching . . . . . . . . . . . . . . . . 2-42 2.4.8 Comparison of Basic Converter Topologies . . . . . . . . . 2-44 2.4.8.1 Switch Utilisation . . . . . . . . . . . . . . . . . 2-44 2.4.8.1.1 Buck Converter . . . . . . . . . . . . . 2-45 2.4.8.1.2 Boost Converter . . . . . . . . . . . . . 2-45 2.4.8.1.3 Buck-Boost Converter . . . . . . . . . . 2-46 2.4.8.1.4 Full Bridge Converter . . . . . . . . . . 2-47 2.4.9 Synchronous Rectifiers . . . . . . . . . . . . . . . . . . . . 2-49 2.4.10 Switching Losses and Snubber Circuits . . . . . . . . . . . 2-50 2.4.10.1 Diode Snubbers . . . . . . . . . . . . . . . . . . 2-51 2.4.10.2 Snubbers for Thyristors . . . . . . . . . . . . . . 2-58 2.4.10.3 Snubbers and Transistors . . . . . . . . . . . . . 2-58 2.4.11 Resonant and Soft-Switching Converters . . . . . . . . . . 2-65 2.4.11.1 Why One Should Not Use Resonant Converters 2-67 2.4.11.2 Why One Should Use Quasi-Resonant Converters 2-67 2.4.12 Example: ZVS Converter Design and Analysis . . . . . . 2-68 3 Switch Mode Power Supplies 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Isolated Converter Topologies . . . . . . . . . . . . . . . . . . . . 3.2.1 The Forward Converter . . . . . . . . . . . . . . . . . . . 3.2.1.1 Other Forward Converter Topologies . . . . . . . 3.2.1.1.1 Two Switch Converter . . . . . . . . . . 3.2.1.1.2 Push-Pull Converter . . . . . . . . . . . 3.2.2 The Flyback Converter . . . . . . . . . . . . . . . . . . . 3.2.3 Utilisation of Magnetics . . . . . . . . . . . . . . . . . . . 3.3 Introduction to Control Techniques for Switching Power Supplies 3.3.1 Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Protection Issues . . . . . . . . . . . . . . . . . . . . . . . 3.3.2.1 Soft Start . . . . . . . . . . . . . . . . . . . . . . 3.3.2.2 Voltage Protection . . . . . . . . . . . . . . . . . 3.3.2.3 Current Limiting . . . . . . . . . . . . . . . . . . 3.3.3 Control Architecture of a Switch Mode Power Supply System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.1 Voltage Mode Control . . . . . . . . . . . . . . . 3.3.3.2 Voltage Feed-forward PWM Control . . . . . . .

3-1 3-1 3-1 3-1 3-7 3-7 3-7 3-12 3-18 3-22 3-25 3-27 3-27 3-28 3-28 3-30 3-30 3-33

CONTENTS

ix 3.3.3.3

Current Mode Control . . . . . . . . . . . . . . . 3-33 3.3.3.3.1 Slope Compensation . . . . . . . . . . . 3-37

4 Introduction to Practical Design of Switch Mode Power plies 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Component Selection . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Resistors . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1.1 Values . . . . . . . . . . . . . . . . . . . . . 4.2.1.2 Resistor Types . . . . . . . . . . . . . . . . 4.2.1.3 Tolerance . . . . . . . . . . . . . . . . . . . 4.2.1.4 Selecting Values . . . . . . . . . . . . . . . 4.2.1.5 Maximum Voltage . . . . . . . . . . . . . . 4.2.1.6 Temperature Coefficient . . . . . . . . . . . 4.2.1.7 Power Rating . . . . . . . . . . . . . . . . . 4.2.1.8 Shunts . . . . . . . . . . . . . . . . . . . . 4.2.1.9 PCB Track Resistors . . . . . . . . . . . . 4.2.2 Capacitors . . . . . . . . . . . . . . . . . . . . . . . 4.2.2.1 Types of Capacitors . . . . . . . . . . . . . 4.2.2.2 Standard Values . . . . . . . . . . . . . . . 4.2.2.3 Tolerance . . . . . . . . . . . . . . . . . . . 4.2.2.4 ESR and Power Dissipation . . . . . . . . . 4.2.2.5 Aging . . . . . . . . . . . . . . . . . . . . . 4.2.2.6 dv/dt Rating . . . . . . . . . . . . . . . . . 4.2.2.7 Series Connection of Capacitors . . . . . . 4.2.3 Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3.1 Schottky Diodes . . . . . . . . . . . . . . . 4.2.3.2 PN diodes . . . . . . . . . . . . . . . . . . 4.2.4 The BJT . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 The MOSFET . . . . . . . . . . . . . . . . . . . . . 4.2.5.1 Bi-directional Conduction . . . . . . . . . . 4.2.5.2 Power Losses . . . . . . . . . . . . . . . . . 4.2.5.3 MOSFET Gate Resistors . . . . . . . . . . 4.2.5.4 Maximum Gate Voltage . . . . . . . . . . . 4.2.6 Operational Amplifiers . . . . . . . . . . . . . . . . . 4.2.6.1 Offsets . . . . . . . . . . . . . . . . . . . . 4.2.6.1.1 Input Offset Voltage . . . . . . . . 4.2.6.1.2 Input Offset Current . . . . . . . . 4.2.6.1.3 Input Bias Current . . . . . . . . 4.2.6.2 Limits on Resistor Values . . . . . . . . . . 4.2.6.3 Gain-Bandwidth Product . . . . . . . . . . 4.2.6.4 Phase Shift . . . . . . . . . . . . . . . . . . 4.2.6.5 Slew Rate Limits . . . . . . . . . . . . . . . 4.2.7 Comparators . . . . . . . . . . . . . . . . . . . . . . 4.2.7.1 Hysteresis . . . . . . . . . . . . . . . . . . . 4.2.7.2 Comparator Interfacing . . . . . . . . . . . 4.3 Introduction to Magnetics Design . . . . . . . . . . . . . . . 4.3.1 Review of the Fundamentals . . . . . . . . . . . . . 4.3.1.1 Ampere’s Law . . . . . . . . . . . . . . . . 4.3.1.2 Faraday’s Law . . . . . . . . . . . . . . . .

Sup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1 4-1 4-1 4-2 4-2 4-2 4-3 4-3 4-3 4-4 4-4 4-5 4-6 4-6 4-7 4-7 4-8 4-8 4-8 4-9 4-9 4-9 4-9 4-10 4-12 4-12 4-13 4-13 4-14 4-14 4-14 4-15 4-15 4-16 4-16 4-17 4-19 4-20 4-20 4-20 4-21 4-22 4-22 4-23 4-23 4-24

x

CONTENTS 4.3.1.3 4.3.1.4 4.3.1.5

4.3.2 4.3.3

4.3.4 4.3.5

4.3.6

Inductance . . . . . . . . . . . . . . . . . . . . . A Note on Units . . . . . . . . . . . . . . . . . . The Three R’s . . . . . . . . . . . . . . . . . . . 4.3.1.5.1 Reactance . . . . . . . . . . . . . . . . 4.3.1.5.2 Remanence . . . . . . . . . . . . . . . . 4.3.1.5.3 Reluctance . . . . . . . . . . . . . . . . The Ideal Transformer . . . . . . . . . . . . . . . . . . . . Real Transformers . . . . . . . . . . . . . . . . . . . . . . 4.3.3.1 Core Materials . . . . . . . . . . . . . . . . . . . 4.3.3.2 Saturation . . . . . . . . . . . . . . . . . . . . . 4.3.3.3 Other Core Limitations . . . . . . . . . . . . . . 4.3.3.3.1 Curie Temperature . . . . . . . . . . . 4.3.3.3.2 Core Losses . . . . . . . . . . . . . . . . Optimal Design Issues . . . . . . . . . . . . . . . . . . . . Design of an Inductor . . . . . . . . . . . . . . . . . . . . 4.3.5.1 Key Magnetic Parameters . . . . . . . . . . . . . 4.3.5.1.1 Initial Permeability . . . . . . . . . . . 4.3.5.1.2 Effective Permeability . . . . . . . . . . 4.3.5.1.3 Amplitude Permeability . . . . . . . . . 4.3.5.1.4 Incremental Permeability . . . . . . . . 4.3.5.1.5 Effective Core Dimensions . . . . . . . 4.3.5.1.6 Inductance Factor . . . . . . . . . . . . 4.3.5.2 Details of Inductor Design . . . . . . . . . . . . 4.3.5.3 Issues in Forward Converter Transformer Design 4.3.5.3.1 Turns Ratio = 1:1 . . . . . . . . . . . . 4.3.5.3.2 Turns Ratio = 2:1 . . . . . . . . . . . . 4.3.5.3.3 Turns Ratio = 3:1 . . . . . . . . . . . . 4.3.5.3.4 Turns Ratio = 4:1 . . . . . . . . . . . . Design of Manufacturable Magnetics . . . . . . . . . . . . 4.3.6.1 Wire Gauge . . . . . . . . . . . . . . . . . . . . 4.3.6.2 Wire Gauge Ratio . . . . . . . . . . . . . . . . . 4.3.6.3 Toroidal Core Winding Limits . . . . . . . . . . 4.3.6.4 Tape versus Wire Insulation . . . . . . . . . . . 4.3.6.5 Layering of Windings . . . . . . . . . . . . . . . 4.3.6.6 Number of Windings . . . . . . . . . . . . . . . 4.3.6.7 Potting . . . . . . . . . . . . . . . . . . . . . . . 4.3.6.8 Safety Requirements . . . . . . . . . . . . . . . .

4-24 4-26 4-26 4-26 4-26 4-27 4-27 4-29 4-30 4-32 4-32 4-32 4-32 4-33 4-35 4-38 4-38 4-38 4-38 4-38 4-39 4-39 4-40 4-46 4-47 4-47 4-47 4-47 4-48 4-48 4-48 4-48 4-49 4-49 4-50 4-50 4-50

II Line Commutated Converters and High Power Inverters 4-53 5 Introduction to High Power Converter Technology 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Applications of Power Converter Technology 5.2 Review of Power Semiconductor Devices . . . . . . . 5.2.1 Diodes . . . . . . . . . . . . . . . . . . . . . . 5.2.1.1 Series Diodes . . . . . . . . . . . . . 5.2.2 Thyristors . . . . . . . . . . . . . . . . . . . . 5.2.2.1 Turn-on Transient . . . . . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

5-1 5-1 5-1 5-3 5-3 5-8 5-8 5-11

CONTENTS

xi . . . . . . . . . . . . . .

5-13 5-13 5-15 5-17 5-17 5-21 5-22 5-24 5-25 5-26 5-26 5-26 5-26 5-27

6 Line Frequency Uncontrolled Rectifiers 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Some Mathematical Preliminaries . . . . . . . . . . . . . . . . . . 6.2.1 Fourier Analysis of Repetitive Waveforms . . . . . . . . . 6.2.1.1 Measures of Waveform Distortion . . . . . . . . 6.2.1.2 Power and Power Factor . . . . . . . . . . . . . 6.3 The Half Wave Rectifier Circuit . . . . . . . . . . . . . . . . . . . 6.3.1 Pure Resistive Load . . . . . . . . . . . . . . . . . . . . . 6.3.2 Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Inductive Load with Back EMF . . . . . . . . . . . . . . . 6.4 The Concept of Current Commutation . . . . . . . . . . . . . . . 6.5 Practical Uncontrolled Single Phase Rectifiers . . . . . . . . . . . 6.5.1 Unity Power Factor Single Phase Rectifier . . . . . . . . . 6.5.2 Effect of Current Harmonics on Line Voltages . . . . . . . 6.5.3 Voltage Doubler Single Phase Rectifiers . . . . . . . . . . 6.5.4 The Effect of Single Phase Rectifiers on Three Phase, Four Wire Systems . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Three Phase, Full Bridge Rectifiers . . . . . . . . . . . . . . . . .

6-1 6-1 6-1 6-2 6-3 6-5 6-11 6-11 6-11 6-13 6-15 6-19 6-25 6-30 6-31

5.2.3

5.2.4

5.2.5

5.2.2.2 Turn-off Transient . . . . . . . . . . . . Gate Turn-off Thyristors . . . . . . . . . . . . . . 5.2.3.1 Snubbers and GTO Thyristors . . . . . 5.2.3.2 GTO Turn-on . . . . . . . . . . . . . . 5.2.3.3 GTO Turn-off . . . . . . . . . . . . . . Insulated Gate Bipolar Transistors (IGBTs) . . . 5.2.4.1 IGBT Operation . . . . . . . . . . . . . 5.2.4.2 IGBT Turn-on . . . . . . . . . . . . . . 5.2.4.3 IGBT Turn-off . . . . . . . . . . . . . . Other Devices and Developments . . . . . . . . . 5.2.5.1 Power Junction Field Effect Transistors 5.2.5.2 Field Controlled Thyristor . . . . . . . 5.2.5.3 MOS-Controlled Thyristors . . . . . . . 5.2.5.4 New Semiconductor Materials . . . . .

. . . . . . . . . . . . . .

. . . . . . . . . . . . . .

. . . . . . . . . . . . . .

. . . . . . . . . . . . . .

6-32 6-34

7 Introduction to Other Power Electronic Devices and Applications 7-1 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 Inverters and Applications . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2.1 Pulse Width Modulation . . . . . . . . . . . . . . . . . . . 7-4 7.2.1.1 Space Vectors and PWM . . . . . . . . . . . . . 7-8 7.2.2 Dead-time Issues . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.2.3 Some Inverter Applications . . . . . . . . . . . . . . . . . 7-15 7.2.3.1 Variable Speed Drives . . . . . . . . . . . . . . . 7-15 7.2.3.2 Grid Connected Applications . . . . . . . . . . . 7-17 7.3 Multilevel Converters and Applications . . . . . . . . . . . . . . 7-20 7.4 Basic Introduction to Matrix Converters . . . . . . . . . . . . . 7-20 7.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 7.4.2 Switching Rules . . . . . . . . . . . . . . . . . . . . . . . . 7-21 7.4.3 Switching – Some More Detail . . . . . . . . . . . . . . . 7-22 7.4.3.1 Alesina/Venturini Modulation Algorithm . . . . 7-22

xii

CONTENTS

7.4.4

7.4.5

7.4.3.2 Space Vector Modulation Techniques Implementation Issues . . . . . . . . . . . . . . 7.4.4.1 Bidirectional Switches . . . . . . . . . 7.4.4.2 Current Commutation . . . . . . . . . 7.4.4.3 Input Filters . . . . . . . . . . . . . . 7.4.4.4 Over-voltage Protection . . . . . . . . Comments . . . . . . . . . . . . . . . . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

7-28 7-37 7-37 7-40 7-44 7-44 7-46

8 Grid Connected Converters and Renewable Energy Systems 8-1 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1.1 Wind Power . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.1.2 Photovoltaics . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.1.3 Outline and Scope of this Chapter . . . . . . . . . . . . . 8-2 8.2 Photovoltaic Inverters . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.1 Review of Power Electronic Configurations for Grid Connected Converters . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.1.1 How do photovoltaic devices work? . . . . . . . 8-5 8.2.1.2 Equivalent Circuit of a Solar Cell . . . . . . . . 8-8 8.2.1.3 Traditional PV Inverter Topologies . . . . . . . 8-14 8.2.2 New PV Inverter Topologies . . . . . . . . . . . . . . . . . 8-26 8.2.2.1 H5 Inverter (SMA) . . . . . . . . . . . . . . . . 8-26 8.2.2.2 HEIRC Inverter (Sunways) . . . . . . . . . . . . 8-32 8.2.2.3 Full Bridge with DC Bypass (Ingeteam) . . . . . 8-33 8.2.2.4 Neutral Point Clamped (NPC) Half-Bridge Inverter . . . . . . . . . . . . . . . . . . . . . . . . 8-35 8.2.2.5 Some Other Topologies and Issues . . . . . . . . 8-37 8.2.3 Grid Requirements for PV Systems . . . . . . . . . . . . . 8-41 8.2.3.1 Discussion of the International Standards . . . . 8-42 8.2.3.2 Anti-islanding Standards . . . . . . . . . . . . . 8-49 8.2.3.3 Australian Standards . . . . . . . . . . . . . . . 8-51 8.2.4 Grid Synchronization and Related Control for PV Systems 8-53 8.2.4.1 Brief review of PLLs . . . . . . . . . . . . . . . . 8-54 8.2.4.2 Brief Review of Synchronisation Techniques for Power Systems . . . . . . . . . . . . . . . . . . . 8-60 8.2.5 Islanding Detection Techniques . . . . . . . . . . . . . . . 8-73 8.3 Wind Turbine Converter Systems . . . . . . . . . . . . . . . . . . 8-73 8.3.1 Grid Requirements for Wind Turbine Systems . . . . . . . 8-73 8.3.2 Grid Synchronization for Three Phase Systems . . . . . . 8-73 8.3.3 Brief Overview of Wind Turbine Converter Control . . . . 8-76

III

Appendices

8-77

A Review of Second Order Circuits A-1 A.1 Series RLC Circuits . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1.1 Quality Factor . . . . . . . . . . . . . . . . . . . . . . . . A-4 A.1.2 Time Domain Response . . . . . . . . . . . . . . . . . . . A-5 A.1.2.1 Forced Response of Series RLC Circuit with Initial Inductor Current . . . . . . . . . . . . . . . A-7 A.2 Parallel RLC Circuits . . . . . . . . . . . . . . . . . . . . . . . . A-8

CONTENTS

xiii

A.2.1 Quality Factor . . . . . . . . . . . . . . . . . . . . . . . . A-10 B Introduction to Space Vectors B-1 B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B.2 The Sinusoidal Assumption . . . . . . . . . . . . . . . . . . . . . B-1 B.2.1 Winding Interaction with Spatial Flux Density DistributionB-2 B.2.2 Winding Interaction with Temporal Flux Density VariationB-6 B.3 dq Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8 B.3.1 Stationary Frame Transformations . . . . . . . . . . . . . B-9 B.3.1.1 MMF transformations . . . . . . . . . . . . . . . B-9 B.3.1.2 Current Transformations . . . . . . . . . . . . . B-11 B.3.1.3 Voltage Transformations . . . . . . . . . . . . . B-12 B.3.1.4 Impedance Transformations . . . . . . . . . . . . B-13 B.3.1.5 Flux Linkage Transformations . . . . . . . . . . B-14 B.3.2 Rotating Frame Transformations . . . . . . . . . . . . . . B-14 B.3.3 Example – SYNCREL Linear dq Model . . . . . . . . . . B-17 B.4 Space Vector Model . . . . . . . . . . . . . . . . . . . . . . . . . B-21 B.4.1 Current Space Vectors . . . . . . . . . . . . . . . . . . . . B-22 B.4.1.1 Stationary Frame Current Vectors . . . . . . . . B-22 B.4.1.2 Rotating Frame Current Vectors . . . . . . . . . B-24 B.4.2 Flux Linkage Space Vector . . . . . . . . . . . . . . . . . B-25 B.4.3 Voltage Space Vector . . . . . . . . . . . . . . . . . . . . . B-27 B.4.4 Example – SYNCREL Space Vector Model . . . . . . . . B-27 B.4.5 Space Vector Power Expression . . . . . . . . . . . . . . . B-28 B.4.6 Space Vector Expression for SYNCREL Torque . . . . . . B-29 B.4.7 Relationship Between Space Vectors and dq Models . . . B-32 C Calculation of Inductances for chine C.1 Calculation of Inductances . . C.1.1 Self Inductances . . . C.1.2 Mutual Inductances . C.1.3 Summary . . . . . . .

a Synchronous Reluctance MaC-1 . . . . . . . . . . . . . . . . . . . . C-1 . . . . . . . . . . . . . . . . . . . . C-3 . . . . . . . . . . . . . . . . . . . . C-11 . . . . . . . . . . . . . . . . . . . . C-14

D Introduction to Instantaneous Imaginary Power D-1 D.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 D.1.1 Single Phase Reactive Power . . . . . . . . . . . . . . . . D-1 D.1.2 Three Phase Instantaneous Imaginary Power . . . . . . . D-3 E Introductory Exercise using Saber Simulator E.1 Introduction . . . . . . . . . . . . . . . . . . . E.2 Circuit Schematic Capture . . . . . . . . . . . E.3 Executing the Transient Analysis . . . . . . . E.4 Plotting and Processing Results . . . . . . . . E.4.1 Manipulating Results . . . . . . . . . E.4.2 Fourier Analysis . . . . . . . . . . . . E.5 A Practice Exercise . . . . . . . . . . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

E-1 E-1 E-2 E-6 E-7 E-9 E-11 E-13

xiv

CONTENTS F PV F.1 F.2 F.3

Related Information SunnyBoy Transformerless PV Inverter . . . . . . . . . . . . . . . Tianwei PV Array Datasheet . . . . . . . . . . . . . . . . . . . . Australian Standards for PV Inverter Connections . . . . . . . . F.3.1 AS4777.2-2005: Grid connection of energy systems via inverters Part 2: Inverter Requirements . . . . . . . . . . F.3.2 AS4777.3-2005 Grid connection of energy systems via inverters Part 3: Grid protection requirements . . . . . . .

G Python Listing for Two Phase PLL Bibliography

F-1 F-2 F-4 F-6 F-6 F-17 G-1

G-21

List of Figures 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14

Conceptual diagram of a traditional linear DC linear power supply. 1-3 Simple half wave rectifier circuit with LR load. . . . . . . . . . . 1-4 Plots for a half wave rectifier with an LR load – L = 200mH and R = 50Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Forced commutated switching pole. . . . . . . . . . . . . . . . . . 1-7 Output of the switching pole. . . . . . . . . . . . . . . . . . . . . 1-7 Example buck converter with waveforms. . . . . . . . . . . . . . 1-9 Conceptual diagram of a H-bridge. . . . . . . . . . . . . . . . . . 1-10 Conceptual diagram showing how to generate double edge naturally sampled PWM. . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Close-up of naturally sampled PWM process. . . . . . . . . . . . 1-13 Equivalence between a switching pole and a variable turns ratio DC-DC transformer. . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Saberr circuit used to simulate double edged naturally sampled PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 Saberr simulation output for double edged naturally sampled PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Component waveforms for double edged naturally sampled PWM. 1-17 Spectrum when the triangular modulation waveforms are 180◦ out of phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

Block diagram of the structure of a typical DC-DC converter. . . 2-2 A basic buck or step-down converter. . . . . . . . . . . . . . . . . 2-4 A basic boost or step-up converter. . . . . . . . . . . . . . . . . . 2-5 Two switch buck–boost converter. . . . . . . . . . . . . . . . . . . 2-6 Single switch Buck–boost converter circuit. . . . . . . . . . . . . 2-7 The Cúk converter. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Cúk converter with the switch open. . . . . . . . . . . . . . . . . 2-8 Cúk converter with the switch closed. . . . . . . . . . . . . . . . 2-9 Full bridge converter. . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Definition of the terms related to duty cycle. . . . . . . . . . . . 2-12 Waveforms in a sawtooth based PWM modulator. . . . . . . . . 2-13 Simple PWM generator circuit. . . . . . . . . . . . . . . . . . . . 2-14 Currents and circuit configurations for a buck converter. . . . . . 2-15 Current waveform at the point of discontinuous current in the inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.15 Current waveform for a buck converter with discontinuous current.2-18

xvi

LIST OF FIGURES 2.16 Voltage ratio of the buck converter for continuous and discontins Vd uous operation modes and constant Vd . NB. ILBmax = T8L . . . 2.17 Characteristics of the buck converter with constant Vo . NB. s Vo ILBmax = T2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.18 Output voltage ripple for a buck converter. . . . . . . . . . . . . 2.19 Circuit used in simulation of the buck converter. . . . . . . . . . 2.20 Waveforms for a buck converter with D = 0.5, RL = 100, and continuous inductor current. . . . . . . . . . . . . . . . . . . . . . 2.21 Initial startup waveforms for a buck converter with D = 0.5, RL = 40kΩ, and discontinuous inductor current. . . . . . . . . . 2.22 Currents and circuit configurations for a boost converter. . . . . 2.23 Voltage ratio of a boost converter versus duty cycle. . . . . . . . 2.24 Current waveform on the edge of continuous current. . . . . . . . 2.25 Plot of the normalised continuous current boundary for the boost converter (Vo constant). . . . . . . . . . . . . . . . . . . . . . . . 2.26 Current waveforms for the boost converter with discontinuous current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.27 Duty cycle versus normalised output current for the boost converter with constant Vo . . . . . . . . . . . . . . . . . . . . . . . . 2.28 Boost converter simulated using Saberr . . . . . . . . . . . . . . . 2.29 Simulated waveforms for a boost converter with D = 0.5 and continuous current. . . . . . . . . . . . . . . . . . . . . . . . . . . 2.30 Output of a boost converter in continuous current mode with several different duty cycles. . . . . . . . . . . . . . . . . . . . . . 2.31 Steady state currents and voltages in a Cúk converter. . . . . . . 2.32 Waveforms for a full bridge converter with a bipolar switching strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.33 Waveforms for a full bridge converter with a unipolar switching strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.34 The input current into a buck-boost converter with a large input inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.35 Plot of switch utilisation for the common converter types. . . . . 2.36 (a) Conventional non-synchronous rectifier based boost converter. (b) Synchronous rectifier based boost converter. . . . . . . . . . . 2.37 (a) Step-down converter circuit with a RC snubber; (b) The diode reverse recovery current [2]. . . . . . . . . . . . . . . . . . . . . . 2.38 Equivalent circuit of the snubber used to protect diodes. (a) Full equivalent circuit; (b) simplified circuit with Rs = 0. . . . . . . . 2.39 Waveforms for the simplified (Rs = 0) snubber circuit. . . . . . . 2.40 Plot of the normalised capacitor voltage versus Cbase /Cs . . . . . 2.41 Turn-off snubber circuit for a transistor step-down converter. . . 2.42 Stray inductances that are important in a transistor switching circuit during turn-on [2]. . . . . . . . . . . . . . . . . . . . . . . 2.43 Current and voltage trajectories during turn-on and turn-off for a step-down transistor converter. . . . . . . . . . . . . . . . . . . 2.44 Equivalent circuit for the turn-off RCD snubber and approximate waveforms for different values of capacitance [2]. . . . . . . . . . 2.45 Switching trajectories for different turn-off capacitor values. . . . 2.46 Typical turn-on snubber for a transistor step-down converter. . . 2.47 Over-voltage snubber for a transistor step-down converter. . . . .

2-20 2-22 2-24 2-26 2-27 2-27 2-29 2-29 2-30 2-31 2-32 2-34 2-35 2-35 2-36 2-37 2-41 2-43 2-47 2-48 2-50 2-52 2-54 2-55 2-56 2-59 2-60 2-61 2-62 2-63 2-63 2-64

LIST OF FIGURES 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 2.56 2.57 2.58 2.59 2.60

3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 3.25 3.26 3.27

xvii

Undeland snubber for a step-down converter circuit. . . . . . . . 2-65 A zero current switching (ZCS) resonant buck converter. . . . . . 2-66 A zero voltage switching (ZVS) resonant buck converter. . . . . . 2-67 A quasi-resonant forward converter. . . . . . . . . . . . . . . . . 2-68 Zero Voltage Switching quasi resonant buck converter for example.2-69 Waveforms in the ZVS circuit (scanned from [2]) . . . . . . . . . 2-70 Voltage across the freewheeling diode in the ZVS circuit. . . . . . 2-72 Final design of the resonant buck ZVS circuit. . . . . . . . . . . . 2-77 ZVS circuit without output filter but with an ideal current source load at 6 Amps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78 ZVS circuit with output filter and ideal current source load at 6 Amps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79 Saber circuit used for the 6 Amp full simulation. . . . . . . . . . 2-80 ZVS circuit with output filter and resistive load at 6 Amps. . . . 2-80 ZVS circuit with filter circuit and resistive load, output current 20 Amp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81 Basic circuit of the forward converter. . . . . . . . . . . . . . . . A practical forward converter. . . . . . . . . . . . . . . . . . . . . Equivalent circuit for a practical forward converter. . . . . . . . . Current waveforms for a practical forward converter. . . . . . . . Circuit diagram of a two switch forward converter. . . . . . . . . Push-pull forward converter. . . . . . . . . . . . . . . . . . . . . . Currents flowing in the push-pull forward converter with SW1 closed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Currents flowing in the push-pull forward converter with SW1 and SW2 open. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flux imbalance in the push-pull circuit. . . . . . . . . . . . . . . Connection between the Buck-Boost and Flyback converter. . . . Flyback converter with the switch closed. . . . . . . . . . . . . . Flyback converter with the switch open. . . . . . . . . . . . . . . The voltage, current and flux in the ideal Flyback Converter. . . Typical BH loop for a magnetic material. . . . . . . . . . . . . . Core excitation waveforms. (a) forward converter. (b) full bridge converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram of a typical switch mode power supply. . . . . . . Feedback circuit using a small forward converter. . . . . . . . . . Example of a simple bootstrap power circuit for a PWM generator chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap circuitry modified for increased hysteresis range. . . . Block diagram of the Unitroder high speed PWM generator. . . Operation of a constant current limit. . . . . . . . . . . . . . . . Operation of a fold-back current limit. . . . . . . . . . . . . . . . Conceptual diagram of a control system for a switch mode power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linearised model of a switch mode power supply. . . . . . . . . . Block diagram of a nested loop control system for a switch mode power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Waveforms for tolerance band current control. . . . . . . . . . . . Waveforms for constant “off” time control. . . . . . . . . . . . . .

3-2 3-3 3-3 3-5 3-7 3-8 3-9 3-10 3-12 3-13 3-14 3-15 3-16 3-18 3-19 3-23 3-24 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-32 3-34 3-35

xviii

LIST OF FIGURES 3.28 Waveforms for constant frequency with turn-on at clock time control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.29 Open loop instability of current mode control. (a) stability with duty cycle < 0.5; (b) instability with duty cycle > 0.5; (c) stability with duty cycle > 0.5 and slope compensation. . . . . . . . . 3.30 Geometrical relationship of the current waveform slopes when there is a current perturbation. . . . . . . . . . . . . . . . . . . . 3.31 Inductor current response of current mode converter. . . . . . . . 3.32 Optimal slope compensation to eliminate RLC type oscillations. . 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16

3-36

3-38 3-39 3-40 3-40 4-5 4-10 4-10 4-11 4-15 4-17 4-18 4-19 4-21 4-22 4-24 4-26 4-28 4-30 4-36

4.23

Equivalent circuit model of a current shunt . . . . . . . . . . . . Method of voltage sharing for series capacitors. . . . . . . . . . . Reverse recovery in a converter secondary circuit. . . . . . . . . . Reverse recovery in a boost converter circuit. . . . . . . . . . . . Operational amplifier circuit for discussion of offsets. . . . . . . . Conventional inverting Op Amp circuit with a gain of 1000. . . . Inverting Op Amp circuit with alternative feedback network. . . Gain-bandwidth product of an Op Amp. . . . . . . . . . . . . . . Comparator with hysteresis. . . . . . . . . . . . . . . . . . . . . . Interfacing a comparator to an NPN transistor. . . . . . . . . . . A loop of wire enclosing an area of time varying flux density. . . A BH loop for a magnetic material. . . . . . . . . . . . . . . . . Circuit symbol for a transformer. . . . . . . . . . . . . . . . . . . Simplified model of a real transformer. . . . . . . . . . . . . . . . Ferrite choice (from [9]). . . . . . . . . . . . . . . . . . . . . . . . Initial permeability with respect to frequency for 2P iron powder Ferroxcube material (from [8]). . . . . . . . . . . . . . . . . . . . Incremental permeability as a function of magnetic field strength for 2P iron powder Ferroxcube material (from [8]). . . . . . . . . Core type selection table (from [8]). . . . . . . . . . . . . . . . . Core data for toroidal cores using powdered iron (from [8]). . . . Typical BH characteristic for 2P magnetic material (from [8]). . Losses in 2P material with respect to flux density and frequency (from [8]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Winding interleaving for high-dielectric isolation and good primary to secondary coupling. . . . . . . . . . . . . . . . . . . . . . A transformer design to satisfy safety requirements. . . . . . . .

5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12

The current-voltage characteristic of a diode. . . . . . . . Conceptual structure of a conventional diode. . . . . . . . Conceptual structure of a power diode. . . . . . . . . . . . Typical reverse recovery characteristic for a diode. . . . . Series connection of diodes to support higher voltage. . . Conceptual diagram of a thyristor. . . . . . . . . . . . . . Transistor model of the thyristor. . . . . . . . . . . . . . . Typical characteristic of a thyristor. . . . . . . . . . . . . Typical turn-on waveforms for a thyristor. . . . . . . . . . Typical thyristor turn-off waveforms. . . . . . . . . . . . . An example of a dc chopper circuit using a GTO thyristor Turn on waveforms for a GTO thyristor. . . . . . . . . . .

5-4 5-5 5-5 5-7 5-8 5-9 5-10 5-11 5-12 5-14 5-16 5-18

4.17 4.18 4.19 4.20 4.21 4.22

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

4-36 4-37 4-40 4-42 4-44 4-44 4-50 4-51

LIST OF FIGURES 5.13 5.14 5.15 5.16

5.17 5.18

5.19 5.20 5.21 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19

6.20 6.21 6.22

Turn-off waveforms for a GTO thyristor. . . . . . . . . . . . . . . GTO thyristor circuit with additional “crowbar” SCR . . . . . . A schematic diagram of the basic structure of the IGBT. . . . . . The IGBT voltage and current transfer characteristics and circuit symbol: (a) output characteristic; (b) transfer characteristic; (c) and (d) n-channel IGBT circuit symbols. . . . . . . . . . . . . . . Current flows in the IGBT. . . . . . . . . . . . . . . . . . . . . . Equivalent circuits for the IGBT: (a) approximate equivalent circuit for normal operating conditions; (b) more complete equivalent circuit showing the parasitic thyristor. . . . . . . . . . . . . . Typical turn-on waveforms for an IGBT. . . . . . . . . . . . . . . Turn-off waveforms for an IGBT. . . . . . . . . . . . . . . . . . . Schematic and circuit symbol for the P-MCT. . . . . . . . . . . .

xix 5-19 5-21 5-22

5-23 5-28

5-29 5-30 5-31 5-31

Line current waveform distortion. . . . . . . . . . . . . . . . . . . 6-3 Phasor relationship for complex power. . . . . . . . . . . . . . . . 6-6 Diagram of the normalised single phase power components with a 30◦ phase angle – the power is normalised by dividing by Vrms Irms . 6-7 Half wave rectifier with a resistive load. . . . . . . . . . . . . . . 6-11 Half wave rectifier with an LR load. . . . . . . . . . . . . . . . . 6-12 Plots for a half wave rectifier with an LR load – L = 200mH and R = 50Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Half wave rectifier circuit with an inductor and back emf. . . . . 6-14 Plots for a half wave rectifier with an inductor and back emf as a load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Test circuit used for current commutation discussion. . . . . . . . 6-15 Circuit configurations during current commutation of the circuit in Figure 6.9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 Plots of the currents in the test circuit of Figure 6.9 – vs = 50 sin ωt, Ls = 5mH, Id = 1 Amp. . . . . . . . . . . . . . . . . . . 6-18 A practical single phase rectifier. . . . . . . . . . . . . . . . . . . 6-19 Equivalent circuit of the single phase rectifier when the diodes are conducting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 Waveforms for the practical single phase rectifier circuit of Figure 6.12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 Input current and output voltage harmonics in a single phase rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Real and imaginary components of the harmonic phasors for the harmonics single phase rectifier harmonics plotted in Figure 6.14. 6-23 Single phase rectifier with input and dc link filters. . . . . . . . . 6-26 Circuit for the a single phase rectifier with current wave shaping boost converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 Waveforms for a single phase rectifier with active current waveshaping – (a) the input current and voltage; (b) the boost converter input voltage and inductor current. . . . . . . . . . . . . . 6-28 Block diagram of the control system for a single phase rectifier with active current wave-shaping. . . . . . . . . . . . . . . . . . . 6-30 Single phase rectifier showing the point of common coupling. . . 6-31 Single phase rectifier voltage doubler. . . . . . . . . . . . . . . . . 6-32

xx

LIST OF FIGURES 6.23 Single phase rectifiers loads in a three phase, four wire distribution system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 6.24 Basic three phase, six pulse, full wave rectifier circuit. . . . . . . 6-35 6.25 Waveforms of a three phase rectifier with a constant current source load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10

7.25 7.26

Definition of rectifier and inverter modes of operation [2]. . . . . Generic power processing block [2]. . . . . . . . . . . . . . . . . . Block diagram of a generic AC drive system. . . . . . . . . . . . Specific implementation of an inverter. . . . . . . . . . . . . . . . Single leg of inverter and the PWM waveforms. . . . . . . . . . . Switch positions and the resultant voltage space vectors. . . . . . Switching waveforms for double edge pulse width modulation. . . Switching time determination. . . . . . . . . . . . . . . . . . . . . Voltage limit hexagon. . . . . . . . . . . . . . . . . . . . . . . . . Inverter showing the initial and final current flow after a leg is fired. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of dead-time induced switching error in an inverter. . . Generic non-battery based photo-voltaic supply system. . . . . . Some grid connected FACTS units offered by Siemens. . . . . . . Conceptual diagram of a matrix converter. . . . . . . . . . . . . . Reconfigured conceptual diagram of the matrix converter. . . . . General form of switching pattern [16]. . . . . . . . . . . . . . . . (a) Direction of the output line-to-neutral voltage vectors for the active switch configurations. (b) Directions of the input line current vectors generated by the active switch configurations. . . . . Derivation of the voltage components for a desired voltage space vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double sided switching sequences for a matrix converter over one control cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diode bridge bidirectional switch cell. . . . . . . . . . . . . . . . Common emitter and common collector back-to-back bidirectional switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short and open circuit situations that can occur during commutation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two phase switching matrix example. . . . . . . . . . . . . . . . Four step commutation process between bidirectional switch cells in Figure 7.23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Matrix converter input filters and damping resistors. . . . . . . . Matrix converter with over-voltage diode clamp protection. . . .

8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9

Block diagram of a generic PV system [21] . . . . . . . . . . . . . 8-6 Band gap diagram of a solar cell (pn junction). . . . . . . . . . . 8-7 Optical generation of carriers in a pn junction. . . . . . . . . . . 8-9 Equivalent circuit of an ideal solar cell. . . . . . . . . . . . . . . . 8-11 Equivalent circuit of a non-ideal solar cell. . . . . . . . . . . . . . 8-11 Circuit symbols for a solar cell and a series array of solar cells. . 8-12 Maximum power diagram for a solar cell. . . . . . . . . . . . . . 8-13 Relative merits of different inverter topologies for PV systems [24].8-15 Single-phase multi-string converter [25]. . . . . . . . . . . . . . . 8-17

7.11 7.12 7.13 7.14 7.15 7.16 7.17

7.18 7.19 7.20 7.21 7.22 7.23 7.24

7-2 7-2 7-3 7-4 7-5 7-9 7-9 7-11 7-13 7-15 7-16 7-18 7-19 7-20 7-21 7-24

7-31 7-33 7-38 7-38 7-39 7-41 7-42 7-43 7-45 7-45

LIST OF FIGURES 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 8.25 8.26 8.27 8.28 8.29 8.30 8.31 8.32 8.33 8.34 8.35 8.36 8.37 8.38 8.39 8.40 8.41

8.42 8.43 8.44 8.45

Detailed view of a single single phase output module [25]. . . . . Multi-string converter with a three phase output stage [25]. . . . A transformerless bridge converter interface for a PV system. . Equivalent circuit for the H-bridge PV converter with S1 and S4 turned on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equivalent circuit for the H-bridge PV converter with S2 and S3 turned on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equivalent circuit for the H-bridge PV converter with S1 and S3 turned on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hybrid Switching H-bridge converter. . . . . . . . . . . . . . . . Hybrid Switching H-bridge converter equivalent circuit for the two positions of the low frequency switches. . . . . . . . . . . . . H5 H-bridge converter. . . . . . . . . . . . . . . . . . . . . . . . . H5 H-bridge equivalent circuit for Vg > 0. . . . . . . . . . . . . . H5 H-bridge equivalent circuit for Vg < 0. . . . . . . . . . . . . . The HERIC PV inverter topology (Sunways) . . . . . . . . . . . The full bridge DC bypass PV inverter (Ingeteam). . . . . . . . . Basic NPC single phase leg. . . . . . . . . . . . . . . . . . . . . . NPC with Vg > 0 and i > 0. . . . . . . . . . . . . . . . . . . . . . NPC with Vg < 0 and i < 0. . . . . . . . . . . . . . . . . . . . . . Basic structure of a single phase PV interface with a high frequency isolated boost converter. . . . . . . . . . . . . . . . . . . Basic structure of a single phase PV interface with a low frequency transformer and non-isolated boost converter. . . . . . . . Test set up for testing the compliance of a distributed resource with the IEEE 1547 standard in anti-islanding. . . . . . . . . . . VDE 0126-1-1 anti-islanding standard test circuit. . . . . . . . . Lightning impulse test waveform. . . . . . . . . . . . . . . . . . . Classic PLL block diagram. . . . . . . . . . . . . . . . . . . . . . Block diagram of a PLL control system when in lock. . . . . . . . Root locus and Bode plot for a 1st order classic PLL. . . . . . . Root locus and Bode plot for the 2nd order PLL. . . . . . . . . . Open loop Bode plots for a 2nd order PLL with zero added. . . . Closed loop magnitude response of a 2nd order PLL with zero added. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic in-quadrature PLL. . . . . . . . . . . . . . . . . . . . . . . Xcos simulation model of the basic in-quadrature PLL. . . . . . . Xcos simulation result – input waveform and feedback sine waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xcos simulation result – the error between the input waveform and the sine feedback waveform. . . . . . . . . . . . . . . . . . . Xcos simulation result – the output of the PI controller which indicates the difference between the input frequency and the loop centre frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . In-quadrature PLL implemented with a Park transformation. . . The three phase quadrature PLL using a Park Transformation. . Space vector representation of the convergence process of a Park Transformation based quadrature PLL. . . . . . . . . . . . . . . . Space vector representation when the Park Transformation quadrature based PLL is locked. . . . . . . . . . . . . . . . . . . . . . .

xxi 8-18 8-19 8-20 8-21 8-21 8-24 8-26 8-27 8-28 8-29 8-31 8-33 8-34 8-37 8-38 8-39 8-40 8-41 8-50 8-51 8-53 8-54 8-56 8-58 8-59 8-60 8-61 8-62 8-64 8-65 8-65

8-66 8-67 8-68 8-69 8-70

xxii

LIST OF FIGURES 8.46 Two phase PLL implemented in Python showing the estimated waveform versus the actual waveform. . . . . . . . . . . . . . . . 8.47 Two phase PLL implemented in Python showing the estimate frequency error from the centre frequency of the PLL. . . . . . . 8.48 Two phase PLL implemented in Python showing the estimated waveform versus the actual waveform when there is a 30% 5th input harmonic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.49 Two phase PLL implemented in Python showing the estimate frequency error from the centre frequency of the PLL when there is a 30% 5th input harmonic. . . . . . . . . . . . . . . . . . . . . 8.50 Two phase PLL implemented in Python showing the estimate frequency error from the centre frequency of the PLL when there is a 30% 5th input harmonic and filter. . . . . . . . . . . . . . . .

8-73

A.1 A.2 A.3 A.4

Series RLC circuit . . . . . . . . . . . . . . . . . . . Series RLC circuit pole positions. . . . . . . . . . . . Time response of a series RLC circuit with Q = 6.3. Parallel RLC circuit. . . . . . . . . . . . . . . . . . .

. . . .

. . . .

. . . .

A-2 A-3 A-7 A-9

B.1 B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.9

MMF calculation integration path. . . . . . . . . . . . . . . . Dimensions of a single coil. . . . . . . . . . . . . . . . . . . . Three phase to two phase transformation. . . . . . . . . . . . Two phase stationary to two phase rotating transformations. Conceptual diagram of a three phase SYNCREL. . . . . . . . Ideal dq equations. . . . . . . . . . . . . . . . . . . . . . . . . Resolving the current space vector onto the abc axes. . . . . . Relationship between the dq-axes and current space vectors. . Space vector rotating frame transformations. . . . . . . . . .

. . . . . . . . .

. . . . . . . . .

B-3 B-6 B-9 B-16 B-18 B-20 B-23 B-24 B-25

C.1 C.2 C.3 C.4

Two pole three phase Syncrel – conceptual Developed diagram of a Syncrel. . . . . . d axis developed diagram for Syncrel . . . ‘a’ phase inductance plot. . . . . . . . . .

. . . .

. . . .

C-2 C-5 C-6 C-11

diagram . . . . . . . . . . . . . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

8-71 8-72

8-74

8-75

D.1 Phasor relationship for complex power. . . . . . . . . . . . . . . . D-2 D.2 Space vector diagram. . . . . . . . . . . . . . . . . . . . . . . . . D-6 E.1 E.2 E.3 E.4 E.5 E.6 E.7 E.8 E.9 E.10 E.11

Simple single phase, half wave rectifier, with an LR load. . . . . . E-2 Initial screen upon invoking SaberSketch. . . . . . . . . . . . . . E-3 An example of a parts gallery screen. . . . . . . . . . . . . . . . . E-4 The wire attributes window. . . . . . . . . . . . . . . . . . . . . . E-7 An example of SaberSketch with the Saber guide toolbar activated.E-8 An example dc/transient simulation set-up window. . . . . . . . E-9 The input-output table of the dc/transient analysis window. . . . E-10 The initial SaberScope window. . . . . . . . . . . . . . . . . . . . E-11 A signal plotted in SaberScope. . . . . . . . . . . . . . . . . . . . E-12 An example of a waveform calculation in SaberScope. . . . . . . E-13 Fourier analysis dialogues in Saber. . . . . . . . . . . . . . . . . . E-14

List of Tables 1.1

Switch configurations and output voltages for a generic H-bridge. 1-11

4.1 4.2 4.3 4.4

Resistor application selection guide Capacitor application guide . . . . Core materials and their uses. . . . Inductor specifications. . . . . . . .

6.1 6.2

Fourier coefficient formulae with symmetry. . . . . . . . . . . . . 6-3 Current harmonic amplitudes. . . . . . . . . . . . . . . . . . . . . 6-25

7.1

Switching combinations and associated phase and line-to-line voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching combinations and associated phase and phase-to-neutral voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM firing times for various sectors . . . . . . . . . . . . . . . . . Voltage limit γ’s . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching values used in SVM. . . . . . . . . . . . . . . . . . . . Selection of switching configurations for combinations of output voltage and input current vectors. . . . . . . . . . . . . . . . . .

7.2 7.3 7.4 7.5 7.6

8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

EN50160 European standards for public distribution grid voltage harmonics limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison of US and European Standards on disconnection times for PV inverters under abnormal voltage variations. . . . . Comparison of European and US standard for disconnection with respect to frequency deviations. . . . . . . . . . . . . . . . . . . . European and US reconnection conditions for PV inverter systems after a trip [21]. . . . . . . . . . . . . . . . . . . . . . . . . . European and US DC current injection limitations . . . . . . . . IEC and IEEE standards for injected current harmonics . . . . . IEC61000-3-2 current harmonic limits. . . . . . . . . . . . . . . . Australian Standard voltage and frequency limits. . . . . . . . .

4-3 4-7 4-31 4-35

7-6 7-7 7-12 7-14 7-30 7-32

8-45 8-45 8-46 8-47 8-47 8-48 8-48 8-52

B.1 Summary of Stationary Frame Transformations . . . . . . . . . . B-14 B.2 Summary of Rotating Frame Transformations . . . . . . . . . . . B-17 E.1 Number magnitude specifiers in Saber . . . . . . . . . . . . . . . E-6

xxiv

LIST OF TABLES

Nomenclature ton T .

D

Duty cycle =

gop

Optical generation rate (EHP/cm3 /sec)

I0

Diode reverse saturation current.

isw

Current through a semiconductor switch.

itr

Current through a pass transistor in a linear power supply.

k

Boltzmann’s constant (1.38 × 10−23 J/K ).

Ln

Mean diffusion length of electrons in p materials.

Lp

Mean diffusion distance of holes in n materials.

q

Charge of an electron (1.6 × 10−19 C).

T

Switching period.

ton

On-time of a switch. On means that the switch is closed.

TK

Temperature in Kelvin.

Vd

DC input voltage to a linear or switching power supply.

vsw

Voltage across a semiconductor switch.

vtr

Voltage across a pass transistor in a linear power supply.

BJTs

Bipolar Junction Transistors

EHP

Electron-hole-pairs.

GTO

Gate Turn Off Thyristor.

◦

IBGT Insulated Gate Bipolar Junction Transistor. MOSFET Metal Oxide Semiconductor Fiedl Effect Transistor. PWM Pulse Width Modulation. SCR

Silicon Controlled Rectifier or Thyristor.

SMPS Switch Mode Power Supplies.

xxvi

Nomenclature

Part I

Switched Mode Power Supplies

Chapter 1

Switching Basics 1.1

Introduction

Power electronics is an enabling technology for a carbon constrained world. Power electronic systems allow the very efficient conversion of electrical energy to forms which can be more easily utilised. For example, photovoltaic collectors naturally generate DC output voltages, the level of the voltage being dependent on the number of series cells. In order to utilise photovoltaics in the power system as it currently exists, the DC voltage needs to be converted to AC voltage of the correct magnitude. Without the use of power electronics this conversion is very difficult to achieve at reasonable cost. Power electronics is essential to power all electric and hybrid electric vehicles, allow efficient air-conditioning, drive new technology lighting systems, allow interfacing of wind turbines to the grid and so on. Another major use of power electronics is in variable speed drives. AC electrical machines are normally constant speed systems, with the shaft rotational speed being related to the AC supply frequency and the number of pole pairs in the machine. In order to change the speed of an AC machine one needs a variable frequency, variable voltage supply. Prior to the advent of power electronics, this was achieved by the use of electrical machine based frequency converters. This was a very expensive solution, which meant the variable speed AC systems were almost never used. If one wanted a variable speed electrical machine one used the DC machine, where the shaft speed can be controlled by the magnitude of the DC armature voltage. Power electronics, coupled with microprocessors has allowed the development of completely static (i.e. no rotating parts) power electronic variable frequency, variable voltage supplies for AC electrical machines (know as inverters). Inverters can be built using current technology up to the several megawatts. The variable speed AC machine drive market is now worth tens of billions of dollars per year on a global basis. Power electronics is also embedded in many consumers products as well – most home electronic systems, for example, are powered by a switch mode power supply (computers, LCD and plasma TVs, video recorders etc). The reason for the switch mode power supply’s ubiquitous use is related to their light weight, efficiency, and multi-voltage capabilities. The remainder of this chapter will examine the basic switch building blocks

1-2

Switching Basics for power electronic systems. These will be examined in a very generic way initially, and then some specific implementations will be considered throughout the remainder of the course.

1.2

Why Use Switching?

One question that needs to be answered before looking at how switching is implemented is: “Why bother using switching in electronic circuits?” Clearly the answer depends on what one is trying to achieve. One can use switching to implement a classic switch function – i.e. connect one part of a circuit to another part. One can use a mechanical or a semiconductor based switch for this. Usually once a switch of this type is closed or opened it tends to remain this way for a long period of time. Whilst this is a valid use of switching, it is not the focus of the switching discussed in this course. The switching that will be discussed here is relatively high frequency switching that occurs continuously whilst the circuit is operating. This means that the electronic circuit’s operation is in a constant transient state. Switching is used in power electronic systems because the power conversion is very efficient. This is due to the fact that if a device is switched then ideally the voltage across the device is zero. Therefore the power dissipated in the switching element is: p = vsw isw = 0 × isw = 0 (1.1)

Power dissipated in the switch is zero.

where vsw is the voltage across the switch, and isw is the current through the switch. Obviously the power dissipated in the switch is zero regardless of isw . Similarly one can have voltage across a device, and due to external circuit conditions the current through the device can be zero, and again the power dissipated in the switch will be zero. Remark 1.1 The previous paragraph is simply a statement as to why switches are in general used in electrical systems. The trick to using switching electronic elements in power electronic systems is that by using high frequency switching (which can only be obtained electronically), together with specific external circuit conditions, one can obtain a linearly controllable output from the system without dissipating any power. Remark 1.2 Switches used in real systems do have resistance and offset voltages across them. Therefore the switches do dissipate power when they switch is closed, but the power dissipated is often very low compared to the amount of energy being controlled by the switching circuit. Remark 1.3 Another advantage of power conversion using switching is that the size and weight of the power conversion device is far less than power conversion techniques that do not use switching. This is largely due to the fact that inductors and capacitors are frequency dependent devices, and the switching frequency in power electronics systems are high which means that these components can be made smaller.

1.2 Why Use Switching?

1-3

vtr = (Vd ¡ vout ) itr

Vd

vref

vout

Control

Cout

RL

Figure 1.1: Conceptual diagram of a traditional linear DC linear power supply.

traditional linear DC power supply

The benefits of switching can clearly be seen if one considers the traditional linear DC power supply. These power supplies take a DC input voltage and convert it to a lower DC voltage. This are implemented by using a circuit of the general configuration shown in Figure (1.1). As can be seen from this figure, there is a substantial voltage across the pass transistor, and therefore the power dissipated in the transistor is: ptr = vtr itr = (Vd − vout )itr

(1.2)

where vtr is the voltage across the pass transistor, itr is the current through the pass transistor, and Vd is the DC input voltage to the power supply. The pass transistor is essentially behaving as an electronically controlled resistor, its value being dynamically changed by the control circuit to maintain the output voltage at the desired output voltage. Remark 1.4 As can be seen from (1.2) if Vd − vout is a large value and there is a reasonable current flow, itr through the device, the power dissipated can be very large. Therefore the efficiency of these power supplies is usually very low. The pass transistor requires a large heat sink under these conditions, making the supply bulky.

Remark 1.5 The key point to note in Figure 1.1 is that the NPN transistor is operating in its linear region of operation. This is similar to Class A amplifiers that one may be familiar with from linear electronics. As with the Class A amplifier, operation in the linear region means that a lot of power is being dissipated in the transistor.

1-4

Switching Basics

+

v diode

-

+

+

vL

-

iL

L

vs

+ R

v out

-

-

Figure 1.2: Simple half wave rectifier circuit with LR load.

1.3

Taxonomy of Power Electronic Systems

Power electronic systems fall into two broad categories, depending on how the switches in the system are switch off: • naturally commutated systems; • and forced commutated systems. We shall briefly consider these, in a very generic sense, below. Both these switching strategies will be further developed later in the course.

1.3.1

Naturally Commutated Systems

Naturally commutated power electronic devices are very common – a diode rectifier consists of naturally commutated devices called diodes (which the readers should be very familiar with). Natural commutation means that the power device is turned off by a “natural” process derived from the external circuit conditions. For example consider a simple half wave rectifier circuit with an LR load as shown in Figure 1.2. In this circuit the diode will switch (or turn) on when the voltage vd across the diode becomes positive, and it will naturally turn off when the current attempts to reverse through the diode – this is the point of natural commutation or transition from the conduction mode of the diode to the turned off state. Note that this point of turn-off is determined by the external circuit conditions (i.e. the input voltage waveform and the specific values of the load resistor and inductor). Figure 1.3 on page 1-5 shows the waveforms for this particular circuit, and one can see that when the current through the load attempts to reverse the diode turns off and the diode voltage becomes that of the supply waveform.

Remark 1.6 One can see that with this circuit the turn-on time of the diode is determined by the properties of a diode – i.e. turns on immediately it becomes

1.3 Taxonomy of Power Electronic Systems

t1

t2

1-5

t3

0.8 0.6

(A)

iL 0.4 0.2 0.0 -0.2

Due to simulation numerics

60.0

vs

v out

vL

40.0

(V)

20.0

Area A 0.0

Area B

-20.0 -40.0

v diode

-60.0 0.0

0.005

0.01

0.015

0.02 t(s)

0.025

0.03

0.035

0.04

Figure 1.3: Plots for a half wave rectifier with an LR load – L = 200mH and R = 50Ω. forward biased. The turn-off time is determined by the load and supply properties only, and the fact that a diode cannot conduct current in the reverse direction. We shall see that the turn-on time of some naturally commutated circuits can be controlled. A variant of the basic diode rectifier circuit can be obtained by replacing the diode with a thyristor or Silicon Controlled Rectifier (SCR). These devices are similar to a diode in that it turns off, or commutates, when the current attempts to reverse through the device. However it is different from the diode because it does not turn on immediately it becomes forward biased, but must have a firing pulse put into it via a third “gate” terminal, assuming that it is already forward biased. There are a variety of systems that fall under the category of naturally commutated – single and three phase rectifiers, and thyristor rectifiers or converters. Remark 1.7 One of the main problem application areas with naturally commutated devices is DC. Because these devices require a reverse of current and voltage across them to turn off, DC systems are a problem. It is possible to turn off naturally commutated devices in DC systems, but it requires complex auxiliary circuitry. Summary 1.1 Naturally commutated switching devices are characterised by the property that they turn off or commutate from the conducting mode to the nonconducting mode due to external circuit conditions. There is not an explicit

1-6

Switching Basics input under the designers control that results in the device turning off. The turn on time may or may not be a controlled time.

1.3.2

Forced Commutated Systems

Power electronic systems are categorised as forced commutated if the turn on and turn off times are determined by an externally generated firing pulse, the timing of which is completely controlled by the system designer. From a hardware perspective, the devices used for such systems are bipolar junction transistors (BJTs), MOSFETs, Insulated Gate Bipolar Junction Transistors (IBGTs), Gate Turn-off thyristors (GTOs) etc. Remark 1.8 Forced commutated systems are more flexible than naturally commutated systems because they can more easily handle DC input voltages. Naturally commutated systems have problems with DC inputs because without special provision the circuit conditions cannot reverse the current flow through the switching device to facilitate a natural commutation. Switch mode power supplies (SMPS), which are the subject of this section of the course, almost exclusively use forced commutation. An alternative name to indicate this that is often used in the SMPS literature is “hard switched”. This refers to the fact that the device can be switched off regardless of the current and voltage conditions across the switching element. Remark 1.9 It should be noted that not all SMPS are forced commutated. There is a strategy for switching, what would normally be forced commutated switching devices, called soft switching, or resonant mode switching. This switching strategy has many aspects similar to natural commutation, where extra circuitry is used to force conditions that allow zero voltage or zero current through the switching device at the time of switching. However, even under this condition, the device switching gate has to be activated to turn off the device – it does not do it naturally. The fundamental element of a forced commutated system is the switching pole, which is shown conceptually in Figure 1.4 on page 1-7. As can be seen from this figure, the switch is modeled as a single pole double throw switch. The connection of the switch is controlled by the S/W ctrl input to the switch. The output voltage is either v or 0 volts depending on the switch connection.

By its very nature, the switching pole is a non-linear element – the output can only take one of two different values. Assuming that the control circuit is switching the output from v to 0 at a particular frequency then the output of the circuit appears as shown in Figure 1.5 on page 1-7. The non-linearity of the output of the circuit is clearly evident.

From a control perspective non-linear behaviour is undesirable. In most electronic circuits it is desired that the output of the circuit is related to the input of the circuit in a linear fashion – e.g. in amplifier or attenuator applications. Therefore the output of Figure 1.5 needs to be modified in some way so that the switching system behaves linearly.

1.3 Taxonomy of Power Electronic Systems

1-7

v

vout

S/W ctrl Figure 1.4: Forced commutated switching pole.

vout

Vd

ton

t

T

Figure 1.5: Output of the switching pole.

1-8

Switching Basics Remark 1.10 The upshot of the linearisation of the converter system is that it allows the use of conventional and familiar linear control theory on the converter systems. Remark 1.11 Another consequence of the quest for linearisation of switching systems is that the control rates and switching frequencies have to be high. This allows the overall control for these systems to be organised as a nested hierarchy of control loops, with the inner most loops having the highest bandwidth. The inner control loops, as far as the slower outer control loops are concerned, appear to be algebraic in nature. This approach allows a “decoupled” control design approach to be used, and greatly simplifies the design. Remark 1.12 There is a move in the control of power electronic systems to embrace the non-linearity of the system by the use of non-linear control strategies such as Model Predictive Control (MPC). It should be noted that the application of such control methodologies to power electronic systems has only been made possible because of the availability of low cost powerful microprocessor systems. 1.3.2.1

Linearising the Non-linear System

To linearise the basic switching pole one needs firstly to define what the input/output relationship is. An examination of Figure 1.5 shows that the switching waveform average value over the period T is controlled by the time that the voltage is at Vd and at 0 volts. A way of capturing this is to define the duty cycle of the waveform: ton (1.3) D= T where 0 ≤ D ≤ 1 and ton is the on-time of the switch which means that the switch is closed so that the output is connected to the input voltage. The average voltage output of the waveform is: Z 1 ton vave = Vd dt (1.4) T 0 Z 1 DT = Vd dt (1.5) T 0 = DVd (1.6)

...what is required is a filter on the output of the switching pole.

As can be seen from (1.6) the relationship between the average output voltage and the input voltage is linear with respect to the duty cycle – i.e. vave ∝ Vd when the constant of proportionality is D the duty cycle.1 One could also consider that the relationship is vave ∝ D, where the constant of proportionality is the input voltage magnitude, and D is regarded at the input to a linear system. However, if the waveform of Figure 1.5 is fed into a resistive load the current would look like the output voltage waveform. What is usually required in real world applications is a DC current through the load that is related to the average output voltage vave . Most readers will see that what is required is a filter on the output of the switching pole. The filter will only respond to the low frequency components in 1 The switching pole, in an average sense, behaves like an electronically controlled attenuator.

1.3 Taxonomy of Power Electronic Systems

1-9

iL IL t

vL

vout

L

vout

Vd

iL

t

RL

Cout

S/W ctrl Filter Figure 1.6: Example buck converter with waveforms. the output waveform of Figure 1.5, the lowest frequency being DC. Therefore if the filter has a lower enough role off frequency the AC components in the waveform will be attenuated, and the DC component will be predominant. Figure 1.6 shows the previous switching pole with the output filter added. The waveforms for the inductor current and the output voltage are also shown. As can be seen, the inductor current waveform and the output voltage waveforms are smoothed compared to the square wave voltage and current waveforms at the switch. This particular circuit is a basic switched mode power supply circuit known as a buck converter. We shall examine this circuit in much more detail in Chapter 2 on page 2-1.

Remark 1.13 The amount of ripple on the current and voltage waveforms depends on the values of the filtering components in Figure 1.6. For example, if the inductor is made larger then the peak-to-peak ripple on iL can be decreased, and similarly if Cout is made larger then the ripple on the output voltage can be made smaller. The other parameter that affects the magnitude of both ripples is the frequency of switching (i.e. fs = 1/T ). The higher the frequency, then for given values of L and Cout , the smaller the ripple on iL and vout respectively. Remark 1.14 The observations and remarks in Remark 1.13 above are another way of saying that the frequency characteristics of the output filter are the determining factor for minimising the ripple on the output for a given switching frequency. Remark 1.15 If it is desired to have vout as a variable quantity – i.e. the output can move to different reference outputs vref , then the dynamics associated with the output filter are very important. If the ripple is to be kept low, then the switching frequency should be very high, this allowing the filtering components to be kept small to achieve a low output ripple. The small filter components will allow rapid transient output voltage changes with set-point changes.

1-10

Switching Basics

vout

S=W1

S=W2

Load

Vd

vsw1

S=W1 ctrl

vsw2

S=W2 ctrl

Figure 1.7: Conceptual diagram of a H-bridge. 1.3.2.2

...frequency characteristics of Pulse Width Modulation

Basics of PWM and Frequency Spectra

From the previous section one can deduce that the linearisation of the nonlinear switching waveforms from the switching pole is related to the relationship between the frequency characteristics of the switching pole output waveforms and the frequency characteristics of the output filter. Given this relationship, we shall introduce some basic theory on the frequency characteristics of Pulse Width Modulation (PWM), which is the main technique used to generate the output waveforms for most forced commutated power electronic systems. In order to introduce PWM we shall consider a basic building block for many power electronic systems – the H-bridge. A basic schematic of this building block can be seen in Figure 1.7. One can see that the name of the topology is derived from the shape of the circuit when drawn.

The outputs of this circuit can be easily tabulated by considering that a ‘1’ is when the switch is connected to the top terminal in Figure 1.7, and a ‘0’ is when a switch is connected to the bottom terminal. The possible switch configurations and the vout voltages are shown in Table 1.1. As can be seen this particular circuit is capable of producing three different output voltages.

The simplest way of switching the H-bridge is to use the ‘10’ and ‘01’ switching strategies to produce a ±Vd output voltage waveform. The average voltage is then determined by the length of time that waveforms spend on each of the voltages. For example, if the time spent at Vd is equal to the time spent at −Vd then the average output voltage is obviously 0 volts.

1.3 Taxonomy of Power Electronic Systems S/W1 0 0 1 1

S/W2 0 1 0 1

1-11

vout 0 −Vd Vd 0

Table 1.1: Switch configurations and output voltages for a generic H-bridge.

Remark 1.16 The H-bridge circuit is a very versatile power electronic circuit. With the addition of one more parallel switching pole it becomes an inverter module capable of three phase output waveforms. As presented in Figure 1.7 on page 1-10 it is capable of positive and negative output voltages by simply changing the effective duty cycle of the output waveforms. As noted later in the course in Section 2.4.7 on page 2-38 one can develop more sophisticated switching strategies to produce less ripple in the output (when the output is filtered) without an increase in the switching frequency of the devices. I will not preempt this material here, but instead present a more general consideration of PWM switching strategies, their harmonic implications, and implementation approaches. We shall consider a form of PWM called double edge naturally sampled PWM[1]2 . A conceptual diagram of how this PWM is implemented is shown in Figure 1.8. Consider the top part of the diagram. As can be seen the basic idea is that the sinusoidal reference waveform is compared to a triangular modulating waveform of the same amplitude using a comparator. The output of the comparator is a digital waveform. If one takes the average of this digital waveform it is 1/2 and the peak-to-peak value is 1 (since it is digital). Therefore the waveform has a DC component in it of 1/2. The widths of the pulses in this waveform vary, and over each interval corresponding to one period of the triangular carrier the average output is a scaled value of the reference waveform with the 1/2 DC offset added to it. A similar argument can be made for the waveform at the bottom part of the diagram. The difference here is that the reference waveform is an inverted version of the reference for the top half of the circuit, therefore the this comparator is trying to PWM the output to produce a voltage that is the opposite of the top half of the circuit. These two offset waveforms are then subtracted, which removes the DC component from the output, and doubles the average output voltage compared to the DC offset waveforms. This also means that the output waveform is now bipolar.

Let us consider a little theory associated with this. Consider Figure 1.9 which shows a close up of the modulation process. This is a simplified situation in that the reference waveform Vref is considered to be a DC level. Nevertheless one can see the basic idea by analysing this situation. 2 Note that there are a variety of forms of PWM, and this is but one. It does happen to have some nice properties with respect to the spectrum though.

...double edge naturally sampled PWM

1-12

Switching Basics

vref

t + -

t

+

PWM output §

vref

t + -

t

Figure 1.8: Conceptual diagram showing how to generate double edge naturally sampled PWM. Carrying out some simple geometry on these waveforms we can write:   4Vtri Vref = Vtri − (ton − t0 ) (1.7) T   T Vref ∴ ton = 1− + t0 (1.8) 4 Vtri Similarly one can also write:  Vref t1 ∴ toff

= −Vtri +

4Vtri T

 (toff − t1 )

T = t0 + 2  T Vref = + 3 + t0 4 Vtri

(1.9) (1.10) (1.11)

It is simple to see that: δt = toff − ton

T = 2



Vref 1+ Vtri

 (1.12)

and therefore the average voltage over one cycle of the triangular modulating waveform is: 1 vave = [δt · Vd ] (1.13) T   Vref Vd 1+ (1.14) = 2 Vtri

1.3 Taxonomy of Power Electronic Systems

m=

1-13

m = ¡ 4VTtri

4Vtri T

Vtri Vref

t

¡Vtri

Vd

t t0 ton

t1

to®

T

Figure 1.9: Close-up of naturally sampled PWM process.

1-14

Switching Basics

vL

vL

L

L

vout

vout

Vd

Vd iL

vsw

1

iL

D

v sw Cout

RL

Cout

RL

S/W ctrl Vref

1 2Vtri

+

§ + 1 2

Figure 1.10: Equivalence between a switching pole and a variable turns ratio DC-DC transformer. If we let Vtri = 1 and normalise to Vd then we can write the average voltage as:

vave 1 1 = + Vref Vd 2 2

(1.15)

Remark 1.17 One can see from (1.15) that there is a DC offset in the output waveform that is unrelated to Vref . Remark 1.18 Equation (1.14) can be broken into two components; the DC offset Vdc = V2d ; and the component related to the reference signal 2VVdtri Vref = kpole Vref , where kpole = 2VVdtri can be considered to be the gain of the switching pole. Now equate (1.6) and (1.14): DVd

=

∴D

=

Vd Vd + Vref 2 2Vtri 1 1 + Vref 2 2Vtri

(1.16) (1.17)

Figure 1.10 shows the equivalence between the switching pole and a variable turns ratio transformer. The switching pole, in an average sense behaves as a DCDC transformer with an infinite turns ratio. When analysing the performance of the system from a control perspective, the ripple in the currents and voltages can be ignored because of the averaging effect of the filter, and the switching pole can be consider to be a linear transformation with a ratio of D. If a similar analysis is carried out for the negative reference waveform and the 180◦ phase shifted triangular waveform then one one will get a similar expression: vave 1 1 = − Vref (1.18) Vd 2 2 and therefore if these two expressions are subtracted then the difference waveform will eliminate the DC component, and the average difference waveform will be Vref . A simulation of the PWM scheme of Figure 1.8 was set up in the Saberr . This simulation also allows the Fourier components of the waveform to be easily

1.3 Taxonomy of Power Electronic Systems

1-15

rel_oper_gte in1

conv_d2var diff

out

d2var

in2

combined_output

c_sin ZeroPhaseDelay amplitude:2 offset:−1 frequency:10000 amplitude:0.9 frequency:50

delay:0 rel_oper_gte in1 k:−1

conv_d2var out

in2

d2var

c_saw3 amplitude:2 offset:−1 frequency:10000 delay:0

Figure 1.11: Saberr circuit used to simulate double edged naturally sampled PWM. obtained. The Saberr circuit appears in Figure 1.11. As can be seen this circuit essentially mirrors the conceptual diagram of Figure 1.8.

Figure 1.12 shows the output of the modulator along with its spectrum. In this simulation the triangular waveform has a frequency of 10kHz, and the reference waveform is a 50Hz sine wave with an amplitude of 0.9. Several observations can be made from this figure: • Fundamental component of the output is at 50Hz and its amplitude is 0.9. • The first appreciable harmonics in the PWM output waveform are sidebands of the 10kHz triangular wave frequency. • There are no harmonics at the switching frequency of 10kHz.

Let us examine the PWM generated in a little more detail. The absence of the harmonics at the triangular wave frequency (which is the effective switching frequency if a H-bridge converter is being driven) is a direct consequence of the 0◦ phase shift in the triangular wave for the bottom modulation stream in Figure 1.8 on page 1-12. This results in a 0◦ phase difference between the 10kHz harmonic produced in either leg in the H-bridge. Therefore when the harmonic components are implicitly subtracted by the H-bridge one is subtracting two waveforms that are in phase, and the net result is zero. Figure 1.13 shows the component waveforms for the simulation that produced the results of Figure 1.12. One can see that the “ZeroPhaseLegSwWaveform” and “DelayedPhaseLegSwWaveform” have a DC offset – this is evident from the time domain waveforms and the spectrum where the DC component can be seen in the spectrum of both signals as 0.5. The other interesting observation is that the spectrum of the “ZeroPhaseLegSwWaveform” and “DelayedPhaseLegSwWaveform” both have the 10kHz

1-16

Switching Basics Graph0 Mag(−) : f(Hz)

combined_output

1.0

0.8

Mag(−)

0.6

0.4

0.2

0.0 0.0

1.0k

2.0k

3.0k

4.0k

5.0k

6.0k

7.0k

8.0k

9.0k

10.0k

11.0k

12.0k

13.0k

14.0k

15.0k

f(Hz)

(−) : t(s)

combined_output

1.0

Reference

(−)

0.5

0.0

−0.5

−1.0

20.0m

21.0m

22.0m

23.0m

24.0m

25.0m

26.0m

27.0m

28.0m

29.0m

30.0m t(s)

31.0m

32.0m

33.0m

34.0m

35.0m

36.0m

37.0m

38.0m

39.0m

40.0m

Figure 1.12: Saberr simulation output for double edged naturally sampled PWM. switching harmonic, but in the “combined_output” waveform this component is missing. As mentioned previously this is due to the 180◦ phase shift in the triangular modulating waveforms and the leg reference waveforms.

Given the above cancellation, it is informative to consider the case where the triangular modulation waveforms are 180◦ out of phase, as compared to in phase. Figure 1.14 shows the spectrum in this case, and as expected the 10kHz switching frequency in each of the leg switching waveforms is no longer cancelled and appears in the combined output waveform. The real and imaginary components of the Fourier components were taken. As can be seen the real 10kHz components in the leg switching waveforms are opposite in magnitude indicating that when they are subtracted they will add together to give a resultant in the output waveform. The imaginary component is only present in the fundamental as it is a sine wave and hence at 90◦ to the assumed cosine waveforms for the Fourier series in Saberr .

Remark 1.19 The main point to note from the above harmonic analysis is that when triangular PWM is used the phase angle between the triangular carrier waveforms can have important implications on the harmonic content of the output waveforms. The PWM sampling strategy presented above is called naturally sampled because the switching occurs at the “natural” cross-over points of the triangular

1.3 Taxonomy of Power Electronic Systems

1-17

Graph0 (−) : t(s)

Reference

1.0

(−)

0.5

0.0

−0.5

−1.0

(−) : t(s)

ZeroPhaseLegSwWaveform

1.0

(−)

0.5

0.0

−0.5

(−) : t(s)

DelayedPhaseLegSwWaveform

1.0

(−)

0.5

0.0

−0.5

19.5m

20.0m

20.5m

21.0m

21.5m

22.0m t(s)

22.5m

23.0m

23.5m

24.0m

24.5m Mag(−) : f(Hz)

ZeroPhaseLegSwWaveform

Mag(−)

0.6

0.4

0.2

0.0

Mag(−) : f(Hz)

DelayedPhaseLegSwWaveform

Mag(−)

0.6

0.4

0.2

0.0

Mag(−) : f(Hz)

combined_output

1.0

Mag(−)

0.8 0.6 0.4 0.2 0.0 −2.0k

0.0

2.0k

4.0k

6.0k

8.0k

10.0k

12.0k

f(Hz)

Figure 1.13: Component waveforms for double edged naturally sampled PWM.

Graph0 Mag(−) : f(Hz)

Mag(−)

0.6

Leg1

0.4

0.2

0.0

(−) : f(Hz)

0.6

Real_Leg1

(−)

0.4 0.2 0.0 −0.2 −0.4

(−) : f(Hz)

Imag_Leg1

0.2

(−)

0.0 −0.2 −0.4 −0.6

Mag(−) : f(Hz)

0.5

Leg2

Mag(−)

0.4 0.3 0.2 0.1 0.0

(−) : f(Hz)

0.6

Real_Leg2

(−)

0.4 0.2 0.0 −0.2

(−) : f(Hz)

Imag_Leg2

0.6

(−)

0.4 0.2 0.0 −0.2

Mag(−) : f(Hz)

combined_output

1.0

Mag(−)

0.8 0.6 0.4 0.2 0.0 0.0

1.0k

2.0k

3.0k

4.0k

5.0k

6.0k

7.0k

8.0k

9.0k

10.0k

11.0k

12.0k

13.0k

14.0k

15.0k

f(Hz)

Figure 1.14: Spectrum when the triangular modulation waveforms are 180◦ out of phase.

1-18

regular sampled double edge PWM

Switching Basics waveform and the reference waveform. This form of modulation is particularly suitable to analogue implementation, and indeed many early analogue modulators used this strategy or variants of it. However, this particular technique is difficult to implement digitally because the times for switching at the crossover points can only be calculate by solving a transcendental equation, which is time consuming in a microprocessor system. To make the strategy amenable to digital implementation, a regular sampled double edge PWM strategy can be employed. This is achieved by sampling the reference waveform at the peak of the triangular waveform and then holding this sample constant until the next peak of the triangular waveform. It is this constant sampled value that it compared to the triangular wave to determine the switching time. The use of this constant sample means that the cross point of the triangular waveform is easy to compute digitally. Sampling at the peak of the triangular waveform prevents multiple switching due to the reference step changing at in inappropriate time.

1.4

Summary

This chapter has outlined the following: 1. Why use switching? – it allows very efficient control of electrical energy. 2. The basic taxonomy of power electronic converter systems into naturally commutated systems and forced commutated systems. The fundamental differences in the operational principles of these two different approaches are presented, and the semiconductor devices that are associated with them are briefly discussed. 3. The fundamental operational element of forced commutated systems, the switching pole, was introduced. 4. Discussion of the use of filtering on the output of forced commutated power electronic systems to hide the inherent non-linearity of the system is introduced. 5. Finally some of the basic concepts of PWM and its frequency spectra are presented.

Chapter 2

Fundamental Topologies 2.1

Introduction

This course part will not attempt to cover every issue related to the design and operation of switch mode power supplies – there is more than enough work in this area to fill a whole course by itself. Instead, the material shall seek to emphasise the main types of switch mode converter structures, their fundamental operational principles, the various areas where the different structures are useful, and finally aspects of the design and control of the switch mode converters. Before looking at the different structures for switch mode converters, we should firstly define what we mean by switch mode converters. Definition 2.1 Switch Mode Converters (SMCs) are converters which accept a DC input and generate a DC output. Switched mode converters are usually only operating at powers up to 10’s of kilowatts. The switched mode converter usually finds application as a power supply regulator in such items as computers, television sets, stereo systems etc., in fact almost all modern electronic consumer devices use some form of switch mode converter. One of the other areas of application of switch mode converters are aerospace systems, where weight is a very important consideration. The switch mode inverter, on the other hand accepts a DC input and generates an AC output. These are treated in their own section of this course, since these devices tend to find application in the high power industrial systems area, and are most often used for the control of electrical machines (although they are not exclusively used for this).

2.2

References

References to switch mode power supplies are often contained in texts on electronics and power electronics. There are some specialised book written on the design of switching power supplies. Tutorial references that readers may find useful are [2, 3, 4, 5]. One can find a lot of material in the IEEE Transactions on Industrial Electronics, and the IEEE Transactions on Power Electronics. This information

2-2

Fundamental Topologies tends to be of a more detailed nature on specific design issues with converters, or new converter topologies.

2.3

Taxonomy of Switch Mode Converters

There are literally hundreds of different circuit configurations for switch mode converters. However, one can classify most of the them into two basic categories: buck converters

• Step-down or buck converters.

boost converters

• Step-up or boost converters. Many of the other topologies that are in the literature are combinations of these two basic topologies. The basic layout of a SMC system is shown in Figure 2.1 below. The input to the converter is usually the mains. Since this is AC the first step is to convert this to DC via a rectifier. Notice that one can also feed DC, from a battery, directly in at the output point of the rectifier. The unregulated DC is usually filtered with a capacitor, before feeding the DC-DC converter electronics. The output of this stage then feeds the load.

Battery

AC line voltage Uncontrolled Filter DC-DC capacitor converter (1 or 3 diode rectifier DC DC DC phase) (unregulated) (unregulated) (regulated)

Load

Desired output voltage

Figure 2.1: Block diagram of the structure of a typical DC-DC converter.

In the following diagrams the switches are assumed to be unidirectional. The direction of current flow is indicated by the arrow on the switch.

2.3.1 output voltage is always less than input voltage

Step-down or Buck Converters

The step-down or buck converter is distinguished by the fact that the output voltage is always less than the input voltage. This means, that regardless of the switching strategy, it is impossible to get the output at a higher voltage than the input. The distinguishing circuit feature of the buck converter is that one cannot get any current to flow in the circuit when the power device is turned on, if the output voltage is greater than or equal to the input voltage. Figure 2.2 shows a basic circuit for a buck converter. Before analysing the circuit, let us look at it heuristically to determine its basic operation. When

2.3 Taxonomy of Switch Mode Converters

2-3

the switch SW closes, current will flow to the resistive load via the inductor L. The capacitor C will charge up during this process. Note that there is a transient involved in the inductor current building up and the voltage being established on the capacitor. When the switch is opened the current through the inductor cannot stop instantly (if it does then the voltage across the inductor will become very large and the circuit will most probably be destroyed). The diode in the circuit will become forward biased, allowing the current in the inductor to continue flowing in the same direction (towards the load). During this phase of operation the energy that was stored in the field of the inductor during the switch on time is being transferred to the load. If the switch remains open for a long time the inductor current gradually decreases to zero, and at the same time the current drawn from the capacitor increases. If the switch is closed before the inductor current decreases to zero, then the current begins to increase again. Remark 2.1 Note that the maximum current that can flow through the inductor if the switch is left closed is Vd /RL . Remark 2.2 If the inductor current goes to zero then the converter is said to be operating in discontinuous mode. If it does not go to zero, then the converter is operating in continuous current mode. Generally speaking, it is desirable to operate the converter in one mode or the other, without a change of mode. Changes in mode can result in difficulties in controlling the output voltage of the converter. A change of mode can occur depending on load changes. Remark 2.3 If the filter were not present in Figure 2.2 then the output voltage would exactly mirror the input voltage – i.e. if the switch is opened an closed then the output would be a square wave voltage. The filter has to be designed so that the cutoff frequency is significantly below the switching frequency. If this is the case then the filter will reject most of the AC components present at the vod , so that the output voltage will essentially be a DC value equal to the average value of the voltage vod . Remark 2.4 One of the distinguishing features of this type of circuit is that when the switch is closed the input is connected to the output, but when the switch is open the input is disconnected from the output. Another distinguishing feature of the buck converter is that the inductor is not placed across the input voltage when the switch is closed. The inductor has a voltage imposed across it that is usually somewhat lower than the input voltage. This means that the inductor does not store all the energy being supplied by the input.

Remark 2.5 If multiple output voltages are required then the buck converter as depicted here is not the topology to use. Other converters, such as the forward converter, that are related to the buck converter can be used. Remark 2.6 Since the switch is at the input to the converter, then the input current is discontinuous. Therefore the input filter to this circuit is more complicated compared to other converter types.

buck converter distinguishing features

2-4

Fundamental Topologies

Energy storage inductor

id

Low pass filter iL

SW

L Vd

vod

+

vL

-

io

C

RL Load

Vo

Figure 2.2: A basic buck or step-down converter. Practical issue 2.1 Driving the gate of a buck converter can be a problem. If we assume that the switching element is a n-channel MOSFET (as it would be for many designs), then the gate voltage often has to be 5V, and in some cases 10V above the supply voltage. This complicates the gate drive, since one has to fabricate the higher voltage using a transformer based gate drive circuit.

2.3.2 output voltage that is always greater than the input voltage

Step-up or Boost Converters

As the name implies, the boost or step-up converter has an output voltage that is always greater than the input voltage. The boost converter also has the added advantage that the output can isolated from the input (using transformer isolation). Figure 2.3 shows a conceptual diagram of a non-isolated boost converter. The basic operation mechanism is that when the switch is closed the load is isolated from the input by the diode, and current builds up in the inductor. This current build is effectively storing energy in the field of the inductor. When the switch is opened, the current in the inductor wishes to continue to flow in the same direction and with the same magnitude. Therefore the diode will turn on and the current will immediately flow into the filter capacitor and any connected load.

Remark 2.7 If the voltage on the capacitor is larger than the supply voltage, the inductor will produce what ever voltage is required so that Vd + vL = Vo . This is required in order for the current to continue to flow in the inductor. One can see that because the polarity of vL shown in Figure 2.3 always has to reverse for this situation, then the output voltage must always be greater than the input voltage (except under initial start-up conditions).

boost converter distinguishing features

Remark 2.8 The main feature of the boost converter is that current can flow through the switch regardless of the relationship between the input and output voltages. This usually occurs because the input to the circuit is disconnected from the output when the switch is closed. It is this feature that one must look for when one is trying to ascertain what category a particular topology falls into.

2.3 Taxonomy of Switch Mode Converters

2-5

Energy storage

iL

+ Vd

io

L vL

SW

+ C

Vo

Figure 2.3: A basic boost or step-up converter. When the switch is opened, the input is connected to the output because the diode switches on. Another distinguishing feature is that when the switch is closed the input voltage is placed across the inductor (so that it stores all the energy being supplied by the input), and when the switch is opened the inductor is placed in series with the load. and this stored energy is transferred to the load. Remark 2.9 In a boost converter the inductor fulfills an energy storage function, whereas in the buck converter the inductor forms a filtering function. Therefore, one can view the boost converter as not having a filter capacitor. This distinction is not very clear for the non-isolated converter, but when we look at isolated converters in the next chapter we shall see that there is a clear distinction. Remark 2.10 There is a maximum power that is practical to build for converters that rely on the energy storage principle. This is especially true for low input voltages. As we shall see in the next chapter a related converter is the flyback converter, which operates using the same principle, and hence suffers from the same power limitations. In order to cater for high power output with an energy storage converter, one needs to have a very small energy storage inductor (since E = 12 Li2 , and therefore the current contributes most significantly to the stored energy). It turns out that for powers much above 50W when the input voltage is low, the inductance becomes very small and is comparable with the parasitics of the circuit. Therefore, the circuit becomes very difficult to manufacture.

2.3.3

Buck–Boost Converters

The buck–boost converter seeks to combine the properties of the previous two converters. This converter type allows the output to be less than or greater than the input voltage. Furthermore, this type of converter also allows a negative polarity output to be generated. The most obvious way of generating a buck–boost converter is to cascade the buck and the boost converter. In practice, however, this is not usually done, since one can obtain the same performance from the system using a single switch

2-6

Fundamental Topologies arrangement. In this case one must really consider the circuit configuration to be a new one, and not a combination of the previous two.1 In order to understand the operation of this circuit let us firstly look at a two switch implementation. Figure 2.4 shows the conceptual circuit for this. In this circuit both switches are either closed at the same time, or they are open at the same time. If both the switches are closed, then the circuit takes on the classic boost converter configuration. If the output voltage is higher than the input voltage, current can still flow through the inductor. When both the switches are opened, then the inductor is positioned in the circuit as in the classic buck converter, and the current built up during the switch closed stage circulates via the diodes through the output capacitor. Remark 2.11 The key to the circuit of Figure 2.4 is that the switches effectively change the circuit configuration, from a boost circuit during the energy storage phase, to a buck circuit when energy is transferred to the load.

iL

SW1

+ Vd

L vL

io

SW2

C

Vo

RL

Figure 2.4: Two switch buck–boost converter. Figure 2.5 shows a simplified circuit for a buck-boost converter circuit using only one switch. The crucial change in this circuit is the swap of the inductor and the switch and the reversal of the diode as compared to the boost converter of Figure 2.3. The swapping of the inductor and the switch and reversing the diode means that the full input voltage is applied across the inductor when the switch is closed (as in the boost converter). This means that the inductor is essentially a energy storage element, as in the boost converter. However, when the switch is opened the input is no longer connected to the supply (as is the situation in the buck converter), and therefore the constraint that the output must be larger than the input is removed. The resultant voltage across the capacitor is simply related to the amount of energy stored in the inductor, and the current required by the load resistor. If one wishes to increase the output voltage then the switch is closed for a longer period of time, and it the voltage is to be decreased then the switch is closed for a shorter period of time. Remark 2.12 One can see from the above explanation that the operation of this circuit has characteristics of both the buck and the boost converter. Reiterating, the energy storage in the inductor is from the boost converter (when the switch 1 One must consider the buck-boost converter to be a configuration in its own right, since it is very difficult to see the separate buck or boost converters in the single switch circuits.

2.3 Taxonomy of Switch Mode Converters

id

2-7

SW +

Vd

vL L

iL

C

Vo

RL

io Figure 2.5: Single switch Buck–boost converter circuit. is closed), and the disconnection of the input from the output when the switch is open is the same as the buck converter. One can therefore identify a buck–boost topology by looking for the fact that the inductor is placed across the supply and disconnected from the load during the energy storage phase when the switch is closed, and the inductor is disconnected from the supply and placed in the output circuit when the switch is opened. Remark 2.13 One should note that the voltages one can obtain from the buck– boost converter are related to the relationship between the load, the capacitor, and the inductor . Remark 2.14 The limitations on the performance of the buck-boost converter are very similar to those of the buck and the boost. In addition the presence of two diodes in the circulating current path can lead to inefficiency (even when Schottky diodes are used).

2.3.4

Cúk Converters

This converters peculiar name arises from its inventor (pronounced Ch-ooo-k). It was arrived at by essentially forming a dual of the buck–boost converter. Similarly to the buck–boost converter it is capable of producing voltages that are larger and smaller than the input voltage, and the output voltage is negative relative to the same reference as the input voltage. One fundamental difference is that the primary storage element is a capacitor, as opposed to the inductor in the buck–boost converter. Figure 2.6 shows a basic Cúk converter. This circuit is slightly more difficult to understand. Therefore we shall consider two situations: one when the switch is closed, and the other when the switch is open. Consider Figure 2.7, which shows the situation when the switch is open. For the sake of the discussion it shall be assumed that the current in the inductors

2-8

Fundamental Topologies

iL

+ Vd

L1 vL 1

iL

vC 1 + -

1

-

2

L2 vL

-

C1

+

2

SW

Vo

C

RL

io

Figure 2.6: The Cúk converter. is continuous. In this case the capacitor is charged by the current iL1 flowing from the input. The current iL2 flowing on the load side of the circuit continues to deliver energy to the load. Note that both iL1 and iL2 would be decreasing under this circuit condition. Remark 2.15 The input current, iL1 , would be decreasing because the capacitor voltage is greater than the input voltage. This can be deduced from the fact that: vc1 = Vd + Vo

(2.1)

Remark 2.16 Equation (2.1) results from the fact that the average voltage across the inductors in the circuit must be zero under steady state conditions – the total volt-seconds change across an inductor must be zero over a complete switching cycle under steady state conditions.

iL

1

+ Vd

L1 vL

1

iL

vC 1 + -

-

2

-

L2 vL

2

+ C

Vo

RL

io

Diode is short circuit Figure 2.7: Cúk converter with the switch open.

Let us consider the situation when the switch is closed. The circuit under this condition is shown in Figure 2.8. Clearly the diode is reverse biased under this condition, and the input inductor, L1 is storing energy with the input voltage

2.3 Taxonomy of Switch Mode Converters

iL

1

+ Vd

L1 vL

1

i L2

vC 1 + -

-

C1

2-9

-

L2 vL

2

+ C2

Vo

RL

io

Switch is closed circuit Figure 2.8: Cúk converter with the switch closed. appearing across it. The current, iL2 is also flowing through the switch. This current to will be increasing with the capacitor voltage driving it. Therefore, the energy that has been stored in the capacitor is being transferred to the load. Remark 2.17 The important point to note about the operation of the Cúk converter is that the capacitor C1 is the element that is actually transferring the energy to the output (and not the inductor as in the other converters that we have looked at). The inductors in the circuit are essentially performing a filtering function on the input currents. Remark 2.18 Examination of Figures 2.7 and 2.8 indicate that the switch simply transfers the capacitor from the input where it receives energy from the supply, to across the load where it supplies energy to the load. Remark 2.19 The capacitor in the Cúk converter has to be able to handle high ripple currents.

2.3.5

Full Bridge Converters

This is the most complex of the converters, in terms of the number of semiconductor components, that we shall look at. It is also the most versatile, in that it can find application in everything from SMCs to dc-to-ac drives. We shall only be considering the former of these two applications. Figure 2.9 shows a conceptual diagram of the full bridge converter circuit. Notice that it has a total of eight semiconductors, with four of them being unidirectional switches. The application of a full bridge circuit depends on the control applied to the bridge. One of the most important properties of the full bridge is that it operates in all four quadrants of the io vo plane. This means that the converter can produce positive and negative output voltage and positive and negative current. The previous converters could only operate in one quadrant (positive or negative voltage, and only positive current). This fact also means that the full

2-10

Fundamental Topologies Leg A

Leg B DC machine load

SWA+

DA+

SWB +

DB +

La i0

Vd

v 0 = v AN - v BN

v AN SWA-

Ra ea

DA-

SWB-

DB- v BN

+ -

N

Figure 2.9: Full bridge converter. bridge converter can accept a dc input and produce an ac output (this mode of operation is known as inversion, and will not be discussed further at this stage). One can see from Figure 2.9 that the switches have diodes in parallel with them. This acknowledges the fact that the switches shown in the diagram are considered to be constructed of a technology that only conducts current in one direction. It also means that if a switch is closed and the current is in the reverse direction then the current will flow through the diode and not through the switch. There are two main switching strategies that can be adopted using the full bridge inverter: • Bipolar switching. • Unipolar switching. Bipolar switching is the name given to the switching strategy when the A+ and B− are switched together, and the B+ and A− are switched together. Therefore the voltage applied to the load is ±Vd . There are no other voltages that can be applied. One can deduce that it the switching is such that 50% of the time the A+, B− is in force, and the remainder of the time the B+, A− state in in force, then the average voltage across the load is zero. By varying the switching around this the voltage can be varied from zero to Vd (when only A+, B− are in force) to −Vd (when only B+, A− are in force). Remark 2.20 The full bridge converter can only produce output voltages that are in the range of −Vd ≤ vo ≤ Vd . Unipolar switching, on the other hand, exploits another degree of freedom available in the full bridge to gain a lower current ripple in the output. One can

2.4 Basic Analysis of Switch Mode Converters

2-11

also switch two devices in different legs but on the same rail. For example, one could switch the A+, B+ devices. This effectively places zero volts on the load, and allows the current to freewheel through one of the switches and the diode paralleling the other device. The mode of operation clearly changes the rate of change the current as compared to the bipolar switching mode.

2.4

Basic Analysis of Switch Mode Converters

In this section we shall do some basic analysis of the converters mentioned in the previous section. Before carrying out this analysis we shall firstly define the concept of duty cycle, also known as mark-space ratio. We shall also introduce the concept behind the development of the switching waveforms. This work has already been presented in a general way in Section 1.3.2.2 on page 1-10, so some of what is below is a refresher of this presentation with an emphasis on this particular application of PWM.

2.4.1

Duty Cycle

Consider Figure 2.10, which shows a switching waveform. The duty cycle of this waveform is defined as: ton (2.2) D= Ts Considering the waveform in Figure 2.10 we can work out the average voltage produced: vave =

1 Ts

1 = Ts

Z

Ts

vo dt 0

(Z

ton

Z

Ts

Vd dt + 0

) 0dt

ton

ton Vd Ts = DVd =

(2.3)

From (2.3) one can see that the average voltage is directly proportional to the duty cycle of the switching.

2.4.2

Basic PWM Generator

In the previous section we defined the concept of a duty cycle. The next question that arises is: “how does one generate the switched output in a manner that a desired average output voltage is produced?”. The simplest technique, that actually arose from the days of complete analogue PWM generators is to use a sawtooth or triangular waveform. This concept is shown schematically in Figure 2.11. One can see from Figure 2.11 that the slope of the sawtooth is: m=

vst Ts

2-12

Fundamental Topologies

SW

Vd

R

v0

v0

ON

OFF

Vd

V0

0

t t off

t on Ts

Figure 2.10: Definition of the terms related to duty cycle.

2.4 Basic Analysis of Switch Mode Converters

2-13

Therefore one can say that: Vcontrol m Vcontrol = Ts vst

ton =

(2.4) (2.5)

One can see from (2.5) that: D=

Vcontrol vst

and hence: vave = DVd =

Vcontrol Vd vst

(2.6)

(2.7)

or vave ∝ Vcontrol where the constant of proportionally is Vd /vst . Sawtooth waveform

v st Vcontrol

ON

OFF

ton

toff

Vd

Ts

Figure 2.11: Waveforms in a sawtooth based PWM modulator. Remark 2.21 Note that if Vd = vst then the constant of proportionality is one. Therefore the average output voltage is the same as the control voltage. In most PWM generators this is not the situation. The circuitry required to perform the PWM generation using the waveforms of Figure 2.11 is very simple. Figure 2.12 shows a conceptual diagram of the required circuit.

Remark 2.22 The PWM generator circuit shown in Figure 2.12 is usually implemented using analogue circuitry. This can be done at a very low cost. It can also be implemented in a digital system.

2-14

Fundamental Topologies

Vdesired

+ Amplifier

V0

v control

+

-

Comparator

Switch control

-

Sawtooth waveform Figure 2.12: Simple PWM generator circuit.

2.4.3

Simplified Analysis of the Buck Converter

In this section we shall carry out a simplified analysis of the characteristics of the buck converter. The assumptions used are detailed later. However, one observation that can be made about the circuit is that the inductor/capacitor combination in Figure 2.2 effectively form a low pass filter. This filter filters out the harmonics in the switching waveform, which is of the form of Figure 2.10. For the filtering action to be effective, the -3db roll-off of the LC circuit has to be substantially lower than the switching frequency of the inverter (i.e. fs = 1/Ts ). This means that the effect of the switching on the output current is largely eliminated, and the switching current is essentially dc. This fact forms the basis of one of the assumptions made later. As mentioned Section 2.3.1 the buck converter can operate in continuous conduction mode or discontinuous mode. This term refers to the current in the inductor. In continuous mode, the current in the inductor never goes to zero, whereas in discontinuous mode the current will go to zero at some point in the switching time Ts . Let us now consider each of these modes separately. 2.4.3.1

Continuous Conduction Mode

We shall assume that the circuit is in steady state for the development of the expressions. If the circuit is in steady state then we immediately know that the sum of the volt-seconds applied across the inductor when the switch is closed plus the volt-seconds when the switch is open must equal zero.2 The waveforms and circuit configurations for the buck converter are shown in Figure 2.13. Note 2.1 The following analysis assumes that the capacitor voltage essentially remains constant over a complete PWM cycle. This in turn implies that the value of the capacitor is large enough that it can absorb the charge supplied from the inductor current without significant voltage rise. 2 This

R is true because λ = vdt, and the flux in the inductor must not increase over a complete period for the circuit to be in steady state.

2.4 Basic Analysis of Switch Mode Converters

2-15

Remark 2.23 A consequence of the previous note is that over a complete cycle of the PWM the average current supplied by the inductor must be equal to the average current supplied to the load. If this were not the case then the capacitor voltage would continually rise or fall over time as the circuit operated, thereby violating the steady state assumption. Notation 2.1 The capitalised currents and voltages in Figure 2.13 and the following analysis refer to the average values of the currents, and not the instantaneous values.

vL Vd -Vo

0

A t B

-V0 iL

Ts

IL

Io

0

t t on

t off

iL

iL

io

Vd

+

L vL

-

C

io

Vo

Vd

+

L vL

-

C

Vo

Figure 2.13: Currents and circuit configurations for a buck converter.

Remark 2.24 As stated above the average inductor voltage over the complete PWM interval has to be zero for steady state operation. Therefore, by inspection of the inductor voltage plot in Figure 2.13 we can say that the volt-seconds applied must be zero.3 Therefore: (Vd − Vo )ton = Vo (Ts − ton )

(2.8)

This expression can be rearranged to give: Vo ton = = D (duty cycle) Vd Ts

linear voltage gain (2.9)

3 Note the dc output voltage assumption appears in Figure 2.13 as the constant voltages over each of the switching intervals.

2-16

Fundamental Topologies Remark 2.25 Keeping in mind the assumptions in the above analysis, this (2.9) means that the output voltage varies linearly with the duty cycle, given a fixed input voltage. Remark 2.26 One could also obtain the relationship of (2.9) by averaging the vo voltage shown in Figure 2.10, realising that this voltage waveform is the form of the input waveform. The output is then obtained since the average input voltage has to be the same as the average output voltage for steady state to exist in the circuit (else the current through the inductor would be increasing or decreasing over a number of cycles.) By using conservation of energy one can also calculate the ratio of the input and output currents. Assuming that the circuit is essentially lossless, then we can say: Pd = Po (2.10) This can be clearly expanded as:

or

Vd Id = Vo Io

(2.11)

Vd 1 Io = = Id Vo D

(2.12)

Remark 2.27 As can be seen from (2.12) the buck converter acts the same as an electronic transformer when in continuous current mode. Remark 2.28 Even though the current iL is fairly smooth, the input current id is jumping from some peak value to zero every time the switch is opened. Depending on the source for the converter, the input may have to be filtered to smooth out these current fluctuations. 2.4.3.2

Boundary between Continuous and Discontinuous Conduction

In this section we shall establish the condition for the converter to move from continuous to discontinuous conduction. Discontinuous conduction occurs when the current iL goes to zero at or before the end of the control period. Consider the current waveform shown in Figure 2.14. One can formally work out that the average value of such a waveform is 12 iLpeak , which is also obvious using geometric arguments based on the fact that the waveform is made up of triangles. Therefore one can derive the following expression for the minimum average current that must be flowing in the circuit to sustain continuous conduction: ILB =

current required for continuous inductor current

1 DTs 1 iLpeak = [(Vd − Vo )ton ] = (Vd − Vo ) = IoB 2 2L 2L

(2.13)

where ILB , is the minimum average inductor current, and IoB , the minimum output current value (remember the two are the same given the steady state assumption). Equation (2.13) can be further manipulated using the expression (2.9) to eliminate V0 , and assuming that Vd is constant, giving:

2.4 Basic Analysis of Switch Mode Converters

ILB = IoB =

2-17

Ts Vd (D − D2 ) 2L

(2.14)

On can differentiate (2.14) to find the duty cycle for the maximum ILB for given Vd , Ts , D, and L: dILB Ts Vd = (1 − 2D) (2.15) dD 2L Clearly from (2.15), the maximum value occurs at D = that value is: Ts Vd ILBmax = 8L

iL

1 2

Therefore using (2.14) (2.16)

Current is zero here

peak

v L = (Vd -Vo )

iL

0

t I LB = I oB

-Vo t off

t on Ts Figure 2.14: inductor.

Current waveform at the point of discontinuous current in the

Remark 2.29 Equation (2.14) defines the value of the average current required in the inductor to just allow continuous conduction. Therefore, the maximum value for this average current, which is the value defined in (2.16) occurs when the duty cycle is 1/2. This means that the onset of discontinuous current operation occurs first if the duty cycle is around this value (which implies that the output voltage is 12 Vd ). Remark 2.30 The previous remark implies that one can design the converter so that the minimum load current is larger than ILBmax in order to ensure continuous conduction (assuming that continuous conduction is the desired operation mode). Note that one of the main design parameters is the inductance value itself. Another point to note is that the input voltage is a parameter in (2.16), so if this voltage varies over a range then this must be taken into consideration. Finally, the load of the system will define the load current required, and via the other considerations mentioned above it will define the parameters of the converter.

2-18

Fundamental Topologies Remark 2.31 There are two main cases to investigate in relation to discontinuous current – the constant Vd case and the constant Vo case. Let us now consider each of these. 2.4.3.2.1 Discontinuous Current with Constant Vd . In many applications the input voltage remains constant, and only the output voltage is varied. We are interested in what the voltage gain of the inverter is under the condition of discontinuous current. Note that we found that with continuous current the voltage gain of the converter was D, and hence it operated linearly. However, as we shall see if the converter operates in discontinuous mode then the voltage gain of the converter becomes non-linear. The following discussion is with reference to Figure 2.15.

iL

Current is zero here

peak

v L = (Vd -Vo )

I L = Io

iL

0

t

-Vo D1Ts

DTs

D2Ts

Ts Figure 2.15: Current waveform for a buck converter with discontinuous current. voltage conversion ratio

In order to calculate the voltage conversion ratio, we firstly start by using the volt-seconds condition – i.e. the total volt-seconds over a control interval must be zero for steady state operation: (Vd − Vo )DTs + (−Vo ∆1 Ts ) = 0

(2.17)

which leads to the following relationship for the voltage ratio: D Vo = Vd D + ∆1

(2.18)

The next relationship to establish is the value of the average current in the inductor under this condition depicted in Figure 2.15. We shall use a technique similar to that used for (2.13). We must firstly get an expression for the peak inductor current. It can be seen from Figure 2.15 that iLpeak can be written as: iLpeak =

Vo ∆1 Ts L

2.4 Basic Analysis of Switch Mode Converters

2-19

We are now in a position to calculate the average inductor current over a period. This is most easily carried out by calculating the area under the iL current in Figure 2.15 for a complete control cycle and dividing by Ts . Therefore we can write: Io =

1 2 iLpeak (DTs

+ ∆1 Ts )

Ts

1 iL (D + ∆1 ) 2 peak 1 Vo ∆1 Ts (D + ∆1 ) = 2 L

=

(2.19) (2.20) (2.21)

Substituting for Vo using (2.18) one can manipulate (2.21) to give: Io =

1 Ts Vd D∆1 2 L

(2.22)

average inductor current discontinuous mode

Clearly this can also be expressed in terms of the minimum load current that results in discontinuous conduction using (2.16) to give: Io = 4ILBmax D∆1

(2.23)

We can now find an expression for ∆1 in (2.18) by rearranging (2.23) to give: ∆1 =

Io 4ILBmax D

(2.24)

Substituting (2.24) into (2.18) and rearranging we get the final expression for the voltage ratio: Vo D2   = (2.25) Io Vd D2 + 1 4

ILBmax

Remark 2.32 The most notable feature of (2.25) is that the voltage ratio is now non-linear. In other words there is a non-linear gain through the converter. Clearly this complicates the design of the control. Furthermore, the onset of nonlinearity with the onset of discontinuous current would make the control even more difficult if the converter moved from continuous current to discontinuous current operation.

voltage ratio is now non-linear

Figure 2.16 is a plot of (2.25) in the discontinuous region, and (2.9) in the continuous region. Remark 2.33 As noted in the previous remark, the voltage ratio to duty cycle relationship for discontinuous operation can be seen, from Figure 2.16, to be very non-linear .

2.4.3.2.2 Discontinuous Current with Constant Vo . In many applications the output voltage should be kept constant whilst the input voltage varies. An example of this type of application is a traditional switch mode power supply (SMPS), where the power supply should keep a constant voltage output despite variations of the mains supply voltage.

constant output

voltage

2-20

Fundamental Topologies

1

D =10 .

Boundary for onset of discontinuous current

D = 0.9 D = 0.8

0.8

D = 0.7

Vo 0.6 Vd

0.4

D = 0.6

DISCONTINUOUS CURRENT REGION

D = 0.5

CONTINUOUS CURRENT REGION

D = 0.4 D = 0.3 D = 0.2

0.2

D = 01 .

0

0

0.2

0.4

0.6

0.8

1 Io I LB

1.2

1.4

1.6

D = 0.0 1.8 2

max

Figure 2.16: Voltage ratio of the buck converter for continuous and discontins Vd uous operation modes and constant Vd . NB. ILBmax = T8L

2.4 Basic Analysis of Switch Mode Converters

2-21

If one uses (2.14) and the linear voltage ratio (2.9), one can calculate the value of the current at the edge of continuous current conduction in the inductor. Substituting for Vd in (2.14) one gets: Ts Vo (1 − D) 2L

ILB =

(2.26)

which clearly has a maximum at D = 0, giving: ILBmax =

Ts Vo 2L

(2.27)

Remark 2.34 Note that (2.27) is the expression for ILBmax in terms of Vo whereas the expression (2.14) is in terms of Vd . In (2.27) the assumption is that Vo is constant (held there by the control of D), and Vd is totally variable. Remark 2.35 Operation at D = 0 for a constant finite Vo is a mathematical artifact, since this would imply that Vd = ∞ (given that D = Vo /Vd in continuous current mode). Using (2.26) and (2.27) we can write: ILB = (1 − D)ILBmax

(2.28)

Using (2.18), (2.21), and (2.27) one can write the following expression (note that both (2.18) and (2.21) are valid regardless of the constraint on Vd or Vo ). Now from (2.18) we have: DVd (2.29) Vo = D + ∆1 Substituting into (2.21) one can write: Ts Vd D∆1 2L

Io =

(2.30)

Using (2.27) we can write: ILBmax Ts = 2L Vo

(2.31)

Substituting this into (2.30) we get: Io =

ILBmax Vd D∆1 Vo

(2.32)

which can be manipulated to give: ∆1 =

Io ILBmax

Vo DVd

(2.33)

which can be substituted back into (2.18) and manipulated to give: Vo D= Vd

Io ILBmax 1 − VVdo

! 12 (2.34)

2-22

Fundamental Topologies

1 Vd Vo Vd

0.8

Vo

CONTINUOUS CURRENT REGION

0.6 D 0.4

Vd Vo Vd

DISCONTINUOUS CURRENT REGION

Vo Vd Vo

0.2 Vd Vo

= 125 . = 15 . = 2.0 = 3.0 = 4.0

= 5.0

0 0

0.2

0.4

0.6 Io I LB

0.8

1

1.2

max

Figure 2.17: Characteristics of the buck converter with constant Vo . NB. s Vo ILBmax = T2L .

2.4 Basic Analysis of Switch Mode Converters

2-23

Remark 2.36 As can be seen from (2.34) the relationship between D and Vo /Vd is again highly non-linear. As in the constant Vd case, the control for constant Vo would be much simpler if operation is maintained in the continuous current mode.

Remark 2.37 The ILBmax in Figure 2.17 is different from that in Figure 2.16. Figure 2.17 shows the inter-relationship between the duty cycle, load current and inverse voltage ratio for the buck converter. The non-linearity in the discontinuous current region of operation is very evident from the figure. Remark 2.38 Figures 2.16 and 2.17 are actually equivalent. For example, at = 1. The corresponding D = 0.5 in Figure 2.16 VVdo = 0.5 and ILB Io max(D=0.5)

point in Figure 2.17 is

Vd Vo

= 2 (i.e.

Vo Vd

= 0.5), D = 0.5 and

Io ILBmax(D=0)

= 0.5.

The latter can be seen from (2.27) and (2.16) as follows. From (2.16): Ts Vd Ts Vo Vo = (using Vd = ) 8L D8L D Ts Vo (for D = 0.5) = 4L 1 = ILBmax(D=0) 2

ILBmax(D=0.5) =

(2.35) (2.36) (2.37)

Correspondence can be found for all the other points. 2.4.3.3

Output Ripple

In the analysis thus-far we have assumed that the capacitor is large enough that the voltage at the output does not change substantially. This was an approximation that made the analysis simpler, but in reality is not true. In many applications that ripple at the output is important – for example, in power supply applications many circuits cannot tolerate significant ripple. In order to get a feel for the voltage ripple we shall assume that the current is continuous. A further simplification is that the impedance of the capacitor is very much lower than the load resistance, and therefore we can assume that the ac component of the current ripple all flows into the capacitor, and the average current over a switching interval flows into the resistor. The following analysis is with reference to Figure 2.18.

Remark 2.39 One can immediately see from Figure 2.18 that we are assuming that the ripple is small enough to be insignificant compared to the voltage across the inductor – hence the inductor voltages are drawn as piecewise constant. Remark 2.40 One could also carry out a complete circuit analysis for the buck converter and get very precise voltage ripple waveforms. The equations for this are straight forward, but just a little messy.

voltage ripple

2-24

Fundamental Topologies

vL Ts Vd - vo

0

t -vo

iL

DI L 2

DQ

I L = Io

0

Ts 2

t

vo

Vo

DVo

0

t Figure 2.18: Output voltage ripple for a buck converter.

2.4 Basic Analysis of Switch Mode Converters

2-25

The output voltage ripple expression can be developed using a capacitor charge approach:   ∆Q 1 1 ∆IL Ts ∆Vo = = (2.38) C C 2 2 2 The next step is to get an expression for ∆IL . From the definition of the voltage across an inductor we can say the following: ∆IL =

vL ∆t L

(2.39)

Considering the off time, we can carry out the following calculations. If ∆t = toff , and we can write toff = Ts − ton , and ton = DTs (from (2.2)) then we get ∆t = toff = (1 − D)Ts . Using this expression, and the fact that vL = Vo we can write: Vo (1 − D)Ts (2.40) ∆IL = L Substituting this expression into (2.38) we can write the following expression for the voltage ripple: Ts Vo (1 − D)Ts 8C L ∆Vo 1 Ts2 (1 − D) ∴ = Vo 8 LC ∆Vo =

(2.41) (2.42)

This expression can be further manipulated into a form that highlights the filtering requirements of the LC combination. Realising that: fc =

1 √ 2π LC

(2.43)

then (2.42) can be written as: ∆Vo π2 (1 − D) = Vo 2



fc fs

2 (2.44)

where fs = 1/Ts . Remark 2.41 Equation (2.44) emphasises that fact that making the filter pole of the LC filter circuit much smaller than the frequency of the PWM results in a lower output voltage ripple. Remark 2.42 Note that (2.44) indicates that the ripple is independent of the average inductor current (in continuous conduction mode). Therefore, keeping in mind the assumptions made in the analysis, the load on the inverter does not influence the amount of ripple. The most relevant of these assumptions in relation to this issue is that the capacitor impedance is much lower than that of the load. 2.4.3.4

Simulation

One can set up a computer simulation of the buck converter circuit. The particular simulator used for this exercise is the Saberr by Analogy. The circuit set up in the simulator is shown in Figure 2.19. The switching device is modeled

2-26

Fundamental Topologies by a switch which has a very high off resistance, and a very low on resistance. The diodes in the circuit are essentially ideal, in that they have a zero turn on voltage. prbit_l4

prbit_l4

BIT STREAM

BIT STREAM

sw1_l4

switch_output_voltage

v_o

100

10

pwld

sw1_l4

v_dc

pwld

50e-3

100e-6

40000

Figure 2.19: Circuit used in simulation of the buck converter. If the load is set at 100Ω, the switching duty cycle to 0.5, and the switching frequency to 100kHz, then the plot of Figure 2.20 results. Note that this low value of load resistance ensures that the current is continuous in the inductor. The plots shows the initial startup transient (that was missing from the steady state analysis that we have carried out above). Once the transient has died away then the output voltage settles to the 5 Volt level that is predicted from the theory. The inductor current settles to the load current, which is Io = 5/100 = 0.05 Amp. Notice that the capacitor current is essentially zero. If one magnifies the graph it can be seen that the capacitor is absorbing the ac currents resulting from the high frequency switching.

Remark 2.43 One can also simulate the performance of the buck converter if there is discontinuous current flow in the inductor. However, the simulation time required for the system to go into steady state is very long due to a problem with the initial transient. This phenomena can be seen in Figure 2.21 which shows the currents for a 50% duty cycle and a load resistance of 40kΩ. Notice that we get an initial LC transient which leaves the capacitor with a charge of approximately 9 Volts (i.e. about twice the applied average voltage of 5 Volt). Once this voltage has appeared on the capacitor it can only dissipate via the load resistor. Therefore the time for the voltage to decay to the steady state value is of the order of 4 to 5 seconds. Remark 2.44 The slow transient that is evident in Figure 2.21 would not occur in a practical discontinuous mode buck converter. It occurs in the example case because the converter control is open loop. In a practical converter the duty cycle is varied depending on the error between the output voltage and the desired output voltage, so as to force the output voltage to the desired.

2.4 Basic Analysis of Switch Mode Converters

2-27

(A) : t(s)

(A)

0.2

Capacitor cur

0.0

-0.2

(A) : t(s)

0.4

Inductor cur

(A)

0.2

0.0

-0.2

(V) : t(s)

10.0

v_o

8.0

(V)

6.0 4.0 2.0 0.0 0.0

0.025

0.05

0.075

0.1

0.125

0.15

0.175

0.2

0.225

t(s)

Figure 2.20: Waveforms for a buck converter with D = 0.5, RL = 100, and continuous inductor current. (A) : t(s)

(A)

0.2

Capacitor cur

0.0 (0.11243, 167.57u)

-0.2

(A) : t(s)

(A)

0.2

Inductor cur

0.0 (0.11243, 70.099u) -0.2

(V) : t(s)

10.0

v_o

8.0

(V)

(0.11243, 8.8035) 6.0 4.0 2.0 0.0 0.0

0.025

0.05

0.075

0.1

0.125

0.15

0.175

0.2

0.225

t(s)

Figure 2.21: Initial startup waveforms for a buck converter with D = 0.5, RL = 40kΩ, and discontinuous inductor current.

2-28

Fundamental Topologies

2.4.4

Simplified Analysis of the Boost Converter

In a manner similar to the analysis of the buck converter we shall also analyse the basic properties of the boost converter. The converter analyzed is that shown in Figure 2.3. As with the buck converter there are two cases to consider – the continuous inductor current case, and the discontinuous inductor current case. 2.4.4.1

Continuous Conduction Mode

The following discussion is in relation to Figure 2.22. Using the same approach as with the buck converter, we can say that in steady state that the time integral of the voltage across the inductor over a complete switching period is zero. Therefore, by inspection of Figure 2.22 we can write: Vd ton + (Vd − Vo )toff = 0 boost converter voltage ratio

(2.45)

Rearranging this gives the voltage ratio of the converter: Ts 1 Vo = = Vd toff 1−D

(2.46)

Assuming a lossless circuit we can say that Pd = Po , and hence: Vd Id = Vo Io boost current ratio

(2.47)

which can be rearranged to give the current ratio of the converter: Io = (1 − D) Id

(2.48)

Remark 2.45 Equation (2.46) indicates that the voltage ratio goes to infinity if D = 1. This arises from the fact that the steady state assumption means via (2.45) that the output voltage becomes increasingly large as D → 1. Remark 2.46 Equation (2.46) indicates that the voltage ratio is not linear for a boost converter. A plot of the voltage ratio is shown in Figure 2.23. Note the very large increase in the voltage ratio as D → 1. In reality this increase does not occur. The analysis that lead to (2.46) involved ideal components. However, if one includes resistance in the inductors and capacitors, and accounts for the very poor switch utilisation under large duty cycles, then as D → 1, then Vo /Vd → 0, and not ∞.

2.4.4.2

inductor current continuous current boundary

Boundary between Continuous and Discontinuous Conduction

The following discussion is with reference to Figure 2.24. This figure shows the current waveform at the edge of continuous conduction. Following an analysis technique similar to that for the buck converter, we can write that the average value of the inductor current at this boundary is:

2.4 Basic Analysis of Switch Mode Converters

2-29

vL Vd

A

0

t B

Vd -Vo iL

Ts

IL

0

t t on

t off

iL

iL

io

+

Vd

L vL

-

C

io

+

Vd

Vo

L vL

-

C

Vo

Figure 2.22: Currents and circuit configurations for a boost converter. 100 90 80 70 60 Vo 50 Vd

40 30 20 10 0

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

D (Duty Cycle)

Figure 2.23: Voltage ratio of a boost converter versus duty cycle.

1

2-30

Fundamental Topologies 1 iL 2 peak 1 Vd = ton 2 L Ts Vo D(1 − D) = 2L

ILB =

output current continuous current boundary

(2.49) (2.50) (2.51)

Equation (2.51) can be further manipulated by realising that the inductor current and the input current in this converter are the same (i.e. id = iL ). Therefore using (2.48) we can say that Io = (1 − D)IL , and hence: IoB =

iL

Ts Vo D(1 − D)2 2L

(2.52)

peak

Current is zero here v L = Vd

iL I LB t

0

Vd -Vo t off

t on Ts

Figure 2.24: Current waveform on the edge of continuous current.

maximum inductor continuous current boundary maximum output continuous current boundary

If we consider that the output voltage of the boost converter is kept constant, then one can differentiate (2.51) and equate to zero to get the value of D = 0.5 for the maximum value of inductor current at the edge of continuous conduction. This value of current is: Ts Vo ILBmax = (2.53) 8L Similarly, one can differentiate (2.52) and equate to zero to get the maximum value of IoB at D = 1/3. The value of IoB is: IoBmax =

2 Ts Vo Ts Vo = 0.074 27 L L

(2.54)

Both ILB and IoB can be expresses as follows in terms of their maximum values: ILB = 4D(1 − D)ILBmax 27 IoB = D(1 − D)2 IoBmax 4

(2.55) (2.56)

2.4 Basic Analysis of Switch Mode Converters

2-31

If we normalise (2.51) and (2.52) using (2.53) we can get the plot shown in Figure 2.25. I LB

1

max

0.9 I LB

0.8 0.7 I oB

0.6

max

= 0.59I LB

max

I I LB

0.5 max

0.4

I oB

0.3 0.2 0.1 0 0

0.1

0.2

0.3 1 3

0.4

0.5

0.6

0.7

0.8

0.9

1

D

Figure 2.25: Plot of the normalised continuous current boundary for the boost converter (Vo constant).

Remark 2.47 Figure 2.25 can be interpreted in the following way. If the current in the inductor is less than ILB then the converter will begin to operate with discontinuous inductor current. This translates to the output current being less than IoB , since the inductor current is not the output current for this type of converter. Notice that the largest value of the continuous output current boundary occurs at D = 0.33, which does not correspond to the point where the largest value of the continuous inductor current boundary occurs. This is due to the fact that the inductor current does not linearly relate to the output current. Remark 2.48 Figure indicates that for continuous current flow in the inductor, either keep the inductor current above ILB , or the output current above IoB . If the output is above IoB , then IL is above ILB , and vice-versa. 2.4.4.2.1 Discontinuous Current with Constant Vd . We shall assume that Vd and D remain constant as the output load varies. Under normal operating conditions there would be a controller that would vary D so as to maintain

2-32

Fundamental Topologies Vo constant despite load variations. However, the above assumptions allow an easier understanding of the discontinuous current condition. The following discussion is with reference to Figure 2.26 which shows the current under the discontinuous current condition.

iL

Current is zero here

peak

v L = Vd

IL

iL

0

t

Vd -Vo D1Ts

DTs

D2Ts

Ts Figure 2.26: current.

discontinuous voltage ratio

discontinuous current ratio

Current waveforms for the boost converter with discontinuous

The integral of the voltage over one control interval must be equal to zero for the circuit to be in steady state. Therefore we can write the following equation: Vd DTs + (Vd − Vo )∆1 Ts = 0 Vo ∆1 + D ∴ = Vd ∆1

(2.57) (2.58)

Again using the fact that the converter is assumed to be lossless, then we can say Pd = Po , and hence the current ratio under discontinuous operation is: ∆1 Io = Id ∆1 + D

(2.59)

If we consider Figure 2.26, and using the fact that the current waveform can be broken down into a number of triangles, we can calculate the average input current. The peak current is: iLpeak = discontinuous average input current

Vd DTs L

(2.60)

and hence the average input current can be deduced to be: Id =

Vd DTs (D + ∆1 ) 2L

(2.61)

2.4 Basic Analysis of Switch Mode Converters discontinuous average output current

2-33

Using (2.59) one can write the average output current expression as:   Ts Vd Io = D∆1 2L

(2.62)

We can use (2.58), (2.62) and (2.54) to get an expression for the duty cycle in terms of the voltage ratio and the output current. From (2.54) we can write: 27 Ts = IoBmax L 2Vo

(2.63)

and from (2.58) one can write: ∆1 =

Vo Vd

D −1

(2.64)

Substituting both of these into (2.62) and manipulating one can get the expression: s   4 Vo Vo Io (2.65) D= −1 27 Vd Vd IoBmax Using (2.65) we can develop a plot of D versus Io /IoBmax for various Vo /Vd . The normal operating mode would be that Vo is constant, and Vd is varying. The development of this plot is slightly complicated due to the fact that the Io /IoBmax for discontinuous current is a function of the duty cycle. Using (2.56) and (2.65) it is possible to get the following expression for the limit on the duty cycle for discontinuous conduction, for a given value of Vd /Vo : h i rh i 2−

Dlim =

1

1 1 x (1− x )

2−

±

2

1

1 1 x (1− x )

2

−4

(2.66)

where x = VVdo . The negative of the two solutions gives a value of D in the valid range of 0 → 1. This sets the limit on the D values, and therefore a limit on the Io /IoBmax range via (2.56). The characteristics of the boost converter with a constant Vo are shown in Figure 2.27. Remark 2.49 One can see from Figure 2.27 that the duty cycle has a highly non-linear relationship to the output current in the discontinuous region of operation. Once outside this region the duty cycle is constant for a particular voltage ratio output.

2.4.4.3

Simulation

To complete this section on the boost converter we shall construct a simulation of the circuit shown in Figure 2.28. The circuit simulated has the switch output switch closed, therefore the load resistance is approximately 100Ω. The voltage output of the circuit, inductor current, load current, and energy stored in the output capacitor and with a 50% duty cycle is shown in Figure 2.29. Notice that the output voltage is 2Vd , as one would predict from (2.46). After the initial startup transient the energy in the capacitor settles

discontinuous duty cycle

2-34

Fundamental Topologies

1

Vd Vo

0.9

Vd

0.8

Vo

0.7

= 0.1

= 0.25

CONTINUOUS CURRENT REGION Vd

0.6

Vo

D 0.5

= 0.5

DISCONTINUOUS CURRENT REGION

0.4

Vd

0.3

Vo

0.2

Vd Vo

0.1

= 0.75

= 0.9

0 0

0.2

0.4

0.6 Io I oB

0.8

1

1.2

max

Figure 2.27: Duty cycle versus normalised output current for the boost converter with constant Vo .

2.4 Basic Analysis of Switch Mode Converters

2-35

to a dc value, indicating that the circuit is now in steady state. The inductor current is essentially constant, which means that the current being pulled from the supply is very close to constant. The effect of applying several different duty cycles when there is continuous conduction is shown in Figure 2.30. Again the simulation output conforms almost exactly to the predicted values of the output using (2.46). prbit_l4 BIT STREAM

prbit_l4 BIT STREAM pwld

100

v_dc

sw1_l4

50e-3 10

sw1_l4

v_o

40000

100e-6

Figure 2.28: Boost converter simulated using Saberr .

(J) : t(s) 0.04

(J)

Cap energy 0.02

0.0

(A) : t(s)

(A)

0.4

I_o

0.2

0.0

(A) : t(s)

0.8 Inductor cur

(A)

0.6 0.4 0.2 0.0

(V) : t(s)

(V)

40.0

v_o

20.0

0.0 0.0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0.2

0.22

t(s)

Figure 2.29: Simulated waveforms for a boost converter with D = 0.5 and continuous current.

2-36

Fundamental Topologies

(V) : t(s) 60.0

v_o;D=0.5

v_o;D=0.8 50.0 v_o;D=0.2

(V)

40.0

30.0

20.0

10.0

0.0 0.0

0.025

0.05

0.075

0.1

0.125

0.15

0.175

0.2

0.225

t(s)

Figure 2.30: Output of a boost converter in continuous current mode with several different duty cycles.

2.4.5

buck-boost ratio

voltage

buck-boost current ratio

A Brief Look at the Buck-Boost Converter

We shall not carry out a complete analysis of the buck-boost converter. We can consider the buck-boost converter can be considered to be a cascade of a buck converter and a boost converter. Therefore, assuming that both converters are operated with the same duty cycle, that the current conduction is continuous, then the output voltage ratio is simply the cascade of the two expressions already derived for the buck and boost converters: Vo D = Vd 1−D

(2.67)

As with the previous converters, if we use the lossless converter assumption we can get the current ratio for the buck-boost converter as: Io 1−D = ID D

(2.68)

Equation (2.67) can easily be shown to hold for the single switch version of the converter as in Figure 2.5. The situation with discontinuous current is more complex, and cannot be considered to be a cascade of the individual converters under this condition.

2.4.6

A Brief Analysis of the Cúk Converter

The following analysis is with reference to Figures 2.6, 2.31, 2.7 and 2.8. It is assumed in the following analysis that the voltage on the capacitor VC1 is constant. This implies that the capacitor is fairly large.

2.4 Basic Analysis of Switch Mode Converters

2-37

vL

1

Vd

ON

0

t OFF

Vd -VC = -Vo 1

vL

2

VC -Vo 1

ON

0

t

OFF -Vo

iL

1

IL

1

0

t

iL

2

IL

2

0

t (1 - D )Ts (= t on )

DTs (= t off )

Figure 2.31: Steady state currents and voltages in a Cúk converter.

2-38

Fundamental Topologies

Under the constant VC1 and steady state operation assumptions, the integral of the voltages across the inductors must be zero. Therefore we can write: Vd DTs + (Vd − VC1 )(1 − D)Ts = 0 ∴ VC1

1 = Vd (for L1 ) 1−D

(2.69) (2.70)

and (VC1 − Vo )DTs + (−Vo )(1 − D)Ts = 0 1 ∴ VC1 = Vo (for L2 ) D Cúk voltage ratio

(2.72)

Using (2.70) and (2.72) we can write: Vo D = Vd 1−D

Cúk current ratio

(2.71)

(2.73)

As with the previous converter analysis, if we assume that the converter is lossless, then we can develop the current ratio: Io 1−D = Id D

(2.74)

Remark 2.50 Equations (2.73) and (2.74) are the same as those for the buckboost converter. One can calculate the current and voltage ratios using an alternate technique based on the charge transferred by the capacitor. This technique is illuminating in that it emphasises the fact that it is the capacitor that is storing the energy that is being transferred from the source to the load. It shall be assumed that the inductors, L1 and L2 , are large enough that the ripple in the currents can be ignored – i.e. iL1 = IL1 and iL2 − IL2 . If the circuit is in steady state then the total charge delivered to the capacitor over a complete control interval is zero. This can be expressed mathematically as follows: IL1 (1 − D)Ts − IL2 DTs = 0 IL Io 1−D ∴ 2 = = IL1 Id D

(2.75) (2.76)

Using the lossless argument once again (Po = Pd ), then one gets: Vo D = Vd 1−D

2.4.7

(2.77)

Full Bridge dc-dc Converter

We shall now consider the calculation of the output voltage ratio and currents for the full bridge dc-dc converter. As was previously noted, this converter is capable of producing both ac and dc outputs, but in this analysis we shall only consider dc output. The following discussion is with respect to Figure 2.9.

2.4 Basic Analysis of Switch Mode Converters

2-39

Assuming that the switches are switched in such a way that the current is continuous in the load, then the output voltage is only a function of the switch states. Let us consider Leg A in Figure 2.9. If switch SWA+ is closed and if io is positive then the current will flow through SWA+ . If io is negative then the current will flow through DA+ . In either case, the Leg A load connection is connected to the positive rail of the dc supply. Therefore: vAN = Vd (for SWA+ on and SWA− off)

(2.78)

Remark 2.51 The assumption stated above essentially means that one of the switches in a leg is switched on at a particular instant of time. As we shall see later, if both switches are open in a leg, then the output voltage is no longer a function of the switch states, but depends on the direction of the load current from the leg. The alternative switching position for Leg A is SWA+ off and SWA− on. In this case a positive current flows through DA− and a negative current through SWA− . Hence in both cases the Leg A load connection is connected to the negative of the supply, which is also the reference point for the voltage measurements. Therefore: vAN = 0 (for SWA− on and SWA+ off) (2.79) Remark 2.52 Expressions (2.78) and (2.79) indicate that the output voltage is dependent only on the status of the switches, and not on the direction of the current. Given Remark 2.52 then the output voltage of Leg A averaged over a complete switching cycle Ts , depends only on the input voltage Vd and the duty ratio of SWA+ . Therefore the average Leg A voltage is: VAN =

Vd ton + 0 · toff = Vd · duty cycle of SWA+ Ts

(2.80)

Similar arguments apply to Leg B. Therefore VBN is: VBN = Vd · duty cycle of SWB+

(2.81)

independent of io . Given VAN and VBN , then we can calculate the output voltage for the converter as follows: Vo = VAN − VBN (2.82) Equation (2.82) is a general expression for the output voltage. It was mentioned in Section 2.3.5 that there are two main strategies for arranging the switching in full bridge converters. We shall now investigate these strategies in detail. 2.4.7.1

Bipolar Switching

This is a switching strategy where the top switch in one leg is closed and the bottom switch in the other leg is closed. Therefore the switches are grouped as diagonal pairs in Figure 2.9.

2-40

Fundamental Topologies In a manner similar to that shown in Section 2.4.2, the PWM for bipolar switching is implemented conceptually by comparing a reference voltage with a triangular waveform. We can work out the output voltage of the converter with this type of switching with the aid of Figure 2.32. In the bipolar converter the basic algorithm is that when the control voltage is greater than vtri then SWA+ and SWB− are turned on. If the control voltage is less than vtri then SWA− and SWB+ are turned on. The logic behind this switching algorithm, is that the triangular switching waveform can be considered to be a scaled version of the integral of the leg waveform with respect to the voltage reference point. Therefore, for a particular leg voltage one has to simply find the scaling factor for the control voltage or the triangular wave. From Figure 2.32A we can see that: vtri = Vˆtri

1 Ts 4


t

(2.83)

At the switching time t1 one can see that vtri = vcontrol . Substituting this into the above expression we can write: t1 =

Leg A duty cycle

Leg B duty cycle

vcontrol Ts Vˆtri 4

(2.84)

Again referring to Figure 2.32A we can see that the total on time for Leg A of the inverter is: 1 (2.85) ton = 2t1 + Ts 2 We can now use (2.2) to give the duty cycle for the SWA+ and SWB− switch pair:   ton 1 vcontrol D1 = = 1+ (2.86) Ts 2 Vˆtri The duty cycle for the SWB+ − SWA− leg (i.e. leg B) is therefore: D2 = (1 − D1 )

(2.87)

Vo = D1 Vd − D2 Vd = (2D1 − 1)Vd

(2.88)

Using (2.82) we can write:

full bridge bipolar output voltage

which becomes, substituting (2.86) : Vo =

Vd vcontrol = kvcontrol ˆ Vtri

(2.89)

Remark 2.53 Equation 2.89 indicates that the output voltage is linear with respect to the control voltage. This makes the control of the converter fairly simple. Remark 2.54 From Figure 2.32 it can be seen that the voltage across the load is bipolar in nature, hence the name of this switching strategy. It should also be noted that the fact that the voltage is going from positive to negative will result in higher ripple in the output current, as compared to any strategy that keeps the voltage unipolar.

2.4 Basic Analysis of Switch Mode Converters

2-41

v tri

V$tri

v control

A

t Ts / 2

t1

t1

Ts

v AN Vd

10

01

01

10

10

B

t

v BN Vd

10

01

10

01

10

C

t

vo = v AN - v BN Vd Vo

10

D

01

10

01

10

t

-Vd

I o + ve io

E

Io SWA + D ASWB - D

B+

DA +

SWA +

DB -

SWB -

t

SWA-

I o - ve

SWB +

io

F

t

-I o SWA + SWA-

DA +

SWA +

SWB - SWB +

DB -

SWB -

DADB +

Figure 2.32: strategy.

Waveforms for a full bridge converter with a bipolar switching

2-42

Fundamental Topologies Remark 2.55 From (2.88) it can be seen that as the duty cycle D1 is varied from 0 to 1 the output voltage varies from −Vd to Vd . This variation is independent of the direction of the current, although different switching components are responsible for the conduction of the current depending on the current direction. This can be seen from Figure 2.32E and F, where the various conduction devices are shown. 2.4.7.2

Unipolar Switching

An alternative switching strategy to the bipolar strategy is the unipolar strategy. This switching strategy takes into account another degree of freedom as compared to the bipolar strategy. The basic idea of this switching strategy is to keep the voltage across the load unipolar if the desired voltage is unipolar. This is achieved by the voltage switching from Vd to 0. Examination of Figure 2.9 indicates that there are two basic strategies for obtaining unipolar operation. For example, assuming that the current direction is positive, then one can have switch SWB− switched on, and then open and close SWA+ depending on the average voltage that one desires. This would result in the voltage across the load going from Vd with SWA+ closed, and 0 with SWA+ open (and hence SWA− closed). The other strategy is to switch leg B. For example, assuming the same current direction, one could open SWB− (and hence close SWB+ ), the current then circulating through via SWA+ and DB+ . Both of the above switching strategies are employed in the switching algorithm drawn in Figure 2.33. One could use a switching scheme similar to that of the bipolar case, where one has a unipolar control voltage. In this case only one of the two switching patterns could be easily incorporated. This would result in a larger output voltage for unipolar switching as compared to bipolar switching. Both of the switching strategies could be used however, if one has the bipolar control voltage shown in Figure 2.33. The switching times are determined as follows: SWA+ closed if: vcontrol > vtri (2.90) and SWB+ closed if: − vcontrol > vtri i.e. vtri < −vcontrol

(2.91) (2.92)

This switching strategy allows both the positive and negative parts of the triangular waveform to be utilised. The net result of switching using this strategy is shown in Figure 2.33C. As compared to the bipolar strategy, or a unipolar strategy where only one of the switching options are used, the switching frequency has effectively been doubled without actually changing the switching frequency of the switches themselves. Remark 2.56 The effective doubling of the switching frequency means that the ripple in the current using the unipolar strategy is less than the ripple using the bipolar strategy. Examination of the waveforms in Figure 2.32B and C and Figure 2.33B and C indicate that the duty cycles are the same for the unipolar case and the bipolar

2.4 Basic Analysis of Switch Mode Converters

2-43

v tri V$tri

v control

A

t t1

t1

-v control

t1

t1

t1

Ts

v AN Vd

10

00

10

11

00

10

10

11

B

t

v BN Vd

10

00

11

10

10

00

10

11

C

t

vo = v AN - v BN Vd Vo

10

2t 1

00

2t 1

10

11

10

00

D

10

11 t

-Vd

I o + ve DA + SWA + SWB D B-

E

io

Io

t

SWA + SWB -

SWADA-

DB -

SWB -

I o - ve

SWADB -

F

-I o

io

t SWA + SWB -

DA + DB DA-

DA +

SWB -

DB -

Figure 2.33: strategy.

Waveforms for a full bridge converter with a unipolar switching

2-44

full bridge duty cycle

Fundamental Topologies case (the VAN and VBN waveforms are the same in both cases). Rewriting these for convenience:   1 vcontrol +1 (2.93) D1 = 2 Vˆtri and D2 = 1 − D1

full bridge unipolar output voltage

(2.94)

Clearly then in this case the output voltage is exactly the same as that of the bipolar case – i.e.: Vd Vo = (2D1 − 1)Vd = vcontrol (2.95) Vˆtri Remark 2.57 Because of the effectively higher switching frequency of the unipolar strategy, it is the preferred method of switching for these types of converters.

2.4.8

Comparison of Basic Converter Topologies

In this section we shall attempt to compare the basic converter topologies introduced in this chapter. This comparison is somewhat limited, as there are a great many topologies that fall into these general categories of those introduced, that in particular applications have advantages over others. Nevertheless this somewhat theoretical comparison is beneficial in that it highlights some of the fundamental structural differences between the converters, and in addition introduces some of the metrics used for carrying out comparisons. One of the first points to notice about most of the converter structures that we have looked at is that they produce unipolar output voltages. There is one exception to this – the full bridge converter. In addition to the unipolar operation, all except the full bridge converter can only handle current in one direction; into the load. Therefore the buck, boost, buck-boost and Cúk converters are said to operate in one quadrant of the io vo operation plane. The full bridge converter on the other hand can operate on all four quadrants of the io vo plane. 2.4.8.1

Switch Utilisation

One of the important metrics of power electronic devices is the switch utilisation. This refers to how well a particular converter topology uses the voltage and current ratings of the semiconductor switches used. If a switch is poorly utilised then a larger semiconductor switch must be used for a given power output for the converter. This corresponds to more expensive switches. In order to calculate the switch utilisation for the previous converters we firstly need a few assumptions: 1. The average current is at its rated value of Io . The ripple in the current can be ignored. 2. The output voltage is ripple free and is at a constant rated value of Vo . 3. The input voltage is allowed to vary and the duty cycle is varied by a control algorithm to keep the output voltage at its fixed rated value.

2.4 Basic Analysis of Switch Mode Converters

switch utilisation definition

2-45

Given these assumptions the peak switch voltage VT and current IT are calculated. The switch peak power rating is then calculated as PT = VT IT . The switch utilisation is then calculated as: Us =

Po PT

(2.96)

where Po = Vo Io . Remark 2.58 The low ripple assumption used in the following analysis implicitly allows one to remove the particular value of inductance used in the circuit from the switch utilisation expressions – i.e. the expressions are circuit value independent. It also serves to simplify the analysis whilst still capturing the essential character of the expressions. Let us now consider the switch utilisation of the generic converter types that we have considered in this chapter. 2.4.8.1.1

Buck Converter The peak voltage across the switch is: VT = Vd

(2.97)

This can be written in terms of the output voltage using (2.9) allowing the peak switch voltage to be written as: VT =

Vo D

(2.98)

Examination of Figure 2.2 reveals that the peak current through the switch must be the same as the average load current, since when the switch is closed the two currents have to be the same (via the no inductor current ripple assumption). Therefore: IT = Io (2.99) Using these two expressions for VT and IT we can write the expression for the switch rating power: V o Io PT = VT IT = (2.100) D Therefore: Po V o Io Us = (2.101) = Vo Io
= D PT D 2.4.8.1.2 Boost Converter A similar analysis for the boost converter can also be carried out. Again the basic equations for the voltage ratio, (2.46), and the current ratio, (2.48) can be used. The key to getting the switch utilisation in this case is to realise that the average input current id and the inductor current iL are the same. Since we are assuming that the inductor is large enough that there can be little ripple in the inductor current, then the switch current must also equal the inductor current. The same assumption also means that we can replace the instantaneous currents with their average values (since they will be the same). Therefore id = Id and iL = IL . We can therefore write: IT = Id

(2.102)

buck converter switch utilisation

2-46

Fundamental Topologies Using (2.48) we can relate the Id and Io , therefore we have: Io (2.103) 1−D From Figure 2.3 one can see that the peak voltage across the transistor is the output voltage – i.e.: VT = Vo (2.104) IT = Id =

allowing the switch peak power to be written as: PT = VT IT = boost converter switch utilisation

Vo Io 1−D

(2.105)

and the switch utilisation as: Us =

Po Vo Io  =1−D = Vo Io PT

(2.106)

1−D

2.4.8.1.3 Buck-Boost Converter The determination of the switch utilisation for the buck-boost converter is a little more complicated than the previous cases. This complication occurs due to the fact that the average current ID is not the peak current value flowing through the switch device (as was the case in most of the above). This occurs due to the fact that the switch disconnects the input from the output. The waveform for the input current (which is also the switch current in this case) is shown in Figure 2.34. Note that the constant value of the current from 0 to DTs is due to the large inductance assumption. It can be seen that that average input current is: iD DTs ID = = iD D (2.107) Ts and therefore the peak current through the switch is: ID D Using (2.68) and (2.108) we can write:   1 IT = iD = Io 1−D iD =

(2.108)

(2.109)

The maximum voltage across the switch (from Figure 2.5) can be seen to be: VT = Vd + Vo

(2.110)

and using (2.67) we can write: 1−D Vo Vo + Vo = D D Using (2.109) and (2.111) we can now write the peak switch power: VT =

PT = VT IT = buck-boost utilisation

switch

1 V o Io D(1 − D)

and hence the switch utilisation factor is: Po Us = = D(1 − D) = D − D2 PT

(2.111)

(2.112)

(2.113)

The Cúk converter has the same switch utilisation as the buck-boost converter.

2.4 Basic Analysis of Switch Mode Converters

2-47

Input current

iD ID

t (1 - D )Ts

DTs

Figure 2.34: The input current into a buck-boost converter with a large input inductance. 2.4.8.1.4 Full Bridge Converter When we consider the switch utilisation for the full bridge converter we shall look at SWA+ and then divide the result by four, because there are four switches in this converter. In other words we require fours times the amount of semiconductor material in this converter, and hence we consider then the peak power is divide across these four devices. Remark 2.59 The division of the single switch utilisation is a technique for saying that the converter is using more silicon than other converters. However, it should be noted that each individual switch has to satisfy the peak power prior to being divided by four. From Figure 2.9 it is obvious that the peak voltage across a switch is: VT = Vd

(2.114)

Similarly it is clear that the peak current is the load current: IT = Io

(2.115)

PT = VT IT = Vd Io

(2.116)

Therefore the peak switch power is:

We need to get the output power. Since we have expressed the peak switch power in terms of Vd we need to get the output power in terms of this as well. This can be achieved by using (2.89) in conjunction with (2.86) which allows us to write: vcontrol = Vˆtri (2D1 − 1) (2.117)

2-48

Fundamental Topologies and hence: Vo = Vd (2D1 − 1)

(2.118)

and therefore the output power is: Po = Vo Io = Vd (2D1 − 1)Io

(2.119)

Therefore the switch utilisation for SWA+ is: USWA+ = full bridge switch utilisation

Po = (2D1 − 1) PT

(2.120)

In order to get the final value we divide then single switch value by four: Us = 0.5D1 − 0.25

(2.121)

The best way to get an overall comparison of the switch utilisation for the various converters is to plot the switch utilisation versus duty cycle for them. This plot is shown in Figure 2.35. Remark 2.60 One can see from Figure 2.35 that the buck-boost converter, the Cúk and the full bridge converter do not have good switch utilisation as compared to the buck or the boost converter. Therefore, where possible it is better to use these converters, since a lower cost switch can be used for a given application.

1 0.9 Boost

Buck

0.8 0.7 0.6 Po PT 0.5

0.4

Buck-boost and Cuk Full bridge

0.3 0.2 0.1 0

0

0.1

0.2

0.3

0.4

0.5 D

0.6

0.7

0.8

0.9

Figure 2.35: Plot of switch utilisation for the common converter types.

1

2.4 Basic Analysis of Switch Mode Converters Remark 2.61 If both higher and lower voltages than the supply are required then one has to use either the buck-boost or the Cúk converters. A significant advantage of the Cúk converter is that the front end of the converter looks like that of the conventional boost converter. Therefore it shares the property of this inverter that the input current is reasonable constant, and hence the filtering of the input is significantly simplified as compared to the buck-boost converter where the input (and output) currents are highly discontinuous. Similarly the output current of this converter can also be kept almost constant. A disadvantage of the Cúk converter is that the capacitor has to have a high ripple current capacity. Remark 2.62 The full bridge converter should only be used if four quadrant operation is required.

2.4.9

Synchronous Rectifiers

In a switching power supply is being used in very low voltage applications the drop of voltage across the rectifier diodes can be significant. This voltage drop obviously results in less efficiency from the converter. In some of the more demanding applications efficiency takes precedence over other considerations. One halfway solution to the efficiency problem is to use of Schottky diodes for the rectifier. These devices have an “on” voltage of approximately 0.2 volt, as compared to the 0.6–0.7 volt of the conventional diode. However, in the very demanding applications this drop is still too much. The solution employed is the use of the so-called synchronous rectifier. This uses a MOSFET instead of the diode. The reader should be aware that a MOSFET has a conventional diode intrinsically built into its structure. This is not the diode that is being used in the synchronous rectifier. The synchronous rectifier uses the fact that a MOSFET is a symmetric structure, and consequently conducts current from the Drain to the Source and vice-versa. This means that when the internal diode is reverse biased the MOSFET is not turned on (thereby operating as a reverse biased diode). But when the diode is forward biased the MOSFET is turned “on”. This effectively shorts out the internal diode since the “on” voltage of a MOSFET is significantly lower than the “on” voltage of the internal diode. This is due to the fact that the MOSFET essentially functions as a resistance when turned “on” hard, and the “on” state resistance of many modern MOSFETs is very very low – of the order of 10−3 mΩ. This principle is shown in Figure 2.36 which shows a conventional boost converter circuit with and without a diode rectifier. One feature in Figure 2.36 is the parallel Schottky diode with the MOSFET. This diode is required to carry the current when the bottom MOSFET turns “off”, and the rectifier MOSFET is “off”. This gap is required so that shoot through from the load cannot occur (and from the supply for the buck converter). The body diode of the MOSFET should not be allowed to carry this current because of the very high reverse recovery time.

Remark 2.63 One other advantage of using synchronous rectifiers is that one can make sure that there is continuous conduction under all load conditions. This occurs because the current can flow in either direction through the inductor with a series MOSFET as opposed to a diode.

2-49

2-50

Fundamental Topologies

+V

+V

(a)

Synchronous rectifier

(b)

Figure 2.36: (a) Conventional non-synchronous rectifier based boost converter. (b) Synchronous rectifier based boost converter.

2.4.10

Switching Losses and Snubber Circuits

It has been shown that the losses in power electronic switches due to the switching process itself and be between two and four times the static losses when the switch is conducting [4] depending on the switching frequency. Clearly these losses will increase in proportion to frequency. The switching losses are switching device and topology dependent. Switching losses occur primarily because as a device switches on or off there may be both substantial voltage and current across the device. Consequently there is a spike of power dissipation during this interval. Specifically the purpose of snubber circuits are [2]: 1. Limit voltages applied across semiconductor devices during turn-off and/or turn-on transients. 2. Limit the rate of rise of current through devices (di/dt) during turn-on. 3. Limit the rate of rise of voltage across devices during turn-off or re-applied forward blocking voltages. 4. Shape the switching trajectory so that the device remains in the safe operating area (SOA)4 under all switching circumstances. transistor switches

Topologies, which use transistor switching devices, and have a transformer pri4 The SOA is the area in the VI plane for devices operation where the manufacturer will guarantee that the device will not be damaged. The device must remain within this area under static and dynamic conditions.

2.4 Basic Analysis of Switch Mode Converters

2-51

mary in series with the switching device tend to have their switching losses concentrated in the turn-off switching cycle (as compared to the turn-on switching cycle). This is because the leakage inductance of the transformer limits the rate of rise of current upon switching device turn-on, and therefore there is little current flowing the device whilst the voltage is at a substantial level across the device. Remark 2.64 Any topology where there is an inductor in series with the power device will have a lower turn-on loss because of the slow rise of current at turnon. Remark 2.65 The non-isolated buck converter, at first sight, would appear to fall into the low turn-on loss category of converters. However, in the case of this converter there is a free wheeling diode at the junction point of the inductor and the switching device which completely changes the situation. In fact the stored charge in the free wheeling diode exacerbates the situation by providing a short circuit to ground upon switching device turn-on. This results in a very high current spike with a very rapid rise time. Therefore in this case there are significant turn-on losses. During turn-off the transistor is protected by the same types of snubber circuits as other topologies. If the switching device is a MOSFET the switching losses tend to be concentrated at turn-on. This is due to the devices own self capacitance Co , which is in parallel with the device. At turn-on one gets a large spike of current due to this capacitance being charged, often to the level of twice the supply voltage. The turn-off losses of the MOSFET tend not be be very high because of the very rapid turn-off of this type of device. Remark 2.66 Snubbers are often required with MOSFETs, not because of the turn-off losses as with transistors, but because of inductive spikes across the drain-source due to parasitic inductance. The fact that MOSFETs can turn-off very quickly exacerbates this inductive spike issue. Not only do active switching elements need snubbers, but so do naturally commutated elements such as diodes and thyristors. As a starting point to this analysis we shall consider diode snubbing. 2.4.10.1

Diode Snubbers

This section is still in development and is far from complete at the moment. Currently it only introduces the various applications of snubbers but does not include comprehensive analysis. The simplest situation to analyse is the diode in a buck converter situation [2]. Consider the diagram in Figure 2.37. A snubber circuit is required across the diode because of the large voltage that can occur across it as a result of the reverse recovery current and the parasitic inductance. In Figure 2.37 the Lσ is the leakage inductance in the diode recovery path. The highly inductive load is being modeled as an ideal current source, Io . When the switch T is opened the current flowing in the load is allowed to flow up

MOSFET switches

2-52

Fundamental Topologies

Io

iLs

Ls

Rs Vd

iDf

Df

vD +

Cs

T

(a) diDf V =- d dt Ls iDf

t0 Io

0

t

tSW

I rr

(b)

ts

Figure 2.37: (a) Step-down converter circuit with a RC snubber; (b) The diode reverse recovery current [2].

2.4 Basic Analysis of Switch Mode Converters through the diode Df , therefore preventing the large voltage spike that would otherwise result from the highly inductive load. This is shown in Figure 2.37(a), where IDf = Io . When the switch T is closed again at time tSW then the current iDf remains initially at Io and starts to decrease. It remains at this level because of the inevitable parasitic inductance of the circuit associated with the diode. The voltage Vd is applied across the leakage inductance, hence the linear decrease of the current. At time t0 the current through the diode (and the Lσ inductor) becomes zero. After this time the current flowing through the diode begins to flow in the reverse direction of normal forward bias current flow. This will continue until the stored charge in the diode is exhausted, and at time ts the diode “snaps off”. At ts the current through Lσ is Irr and if nothing is done, the voltage produced by di/dt through Lσ in order to keep Irr flowing would be enormous. Hence the requirement of a snubber circuit Rs Cs . In order to analyse the snubber circuit consider the equivalent circuit of Figure 2.38. This shows the full equivalent circuit for the snubber section of the circuit, as well as a simplified circuit when the resistor is zero. We shall use the later initially to carry out the analysis, even though this circuit is not used in practice. Nevertheless the basic principles of operation are shown by using this circuit. Not that the following analysis is based on this presented in [2]. The circuit in Figure 2.38(b) is a simple LC circuit, and therefore can be solved using the standard differential equation. It can be shown that the solution to this circuit is: Vd − VCs 0 sin ω0 (t − t0 ) (2.122) iL (t) = IL0 cos ω0 (t − t0 ) + Z0 vCs (t) = Vd − (Vd − VCs 0 ) cos ω0 (t − t0 ) + Z0 IL0 sin ω0 (t − t0 )(2.123) where: ω0 Z0

1 2πf0 = √ Lσ CS r Lσ Ω = Cs =

In this particular case, we shall assume that the t = 0 time is at the point where the diode snaps off. Therefore the initial conditions for the inductor current and the capacitor voltage are iL0 = Irr and vCs = 0. Figure 2.39 shows the waveforms that are generated for the simplified circuit of Figure 2.38(b). Note that the capacitor voltage is the negative of the diode voltage. Let us define a base capacitance value: 2  Irr (2.124) Cbase = Lσ Vd 2 2 (this is derived from the expression 12 Lσ Irr = 12 Cs vC , and saying that the s capacitor voltage is the input voltage). h i2 into (2.123) and manipulating we can write: Substituting Lσ = Cbase IVrrd " # r Cbase vCs = Vd 1 − cos ω0 t + sin ω0 t (2.125) Cs

2-53

2-54

Fundamental Topologies

Ls

iC

I rr

(a) Vd

Diode Snap-off

K

Rs

A Cs

vCs

Cs

vCs

Rs = 0

Ls iLs

(b) Vd

Figure 2.38: Equivalent circuit of the snubber used to protect diodes. (a) Full equivalent circuit; (b) simplified circuit with Rs = 0.

2.4 Basic Analysis of Switch Mode Converters

2-55

vCs

vCsmax

Irr

L¾ didtL = Vd

Vd

t

Figure 2.39: Waveforms for the simplified (Rs = 0) snubber circuit.

Taking the derivative of this expression we and equating the result to zero (the find the extremum) we can write: r sin ω0 t = −

Cbase cos ω0 t Cs

(2.126)

or r tan ω0 t = −

Cbase Cs

(2.127)

where ω0 t is the “optimal” value for θ. Note that due to the properties of the tan function, we can also write: r tan(ω0 t ± π) = −

Cbase Cs

(2.128)

We shall make us of the following trigonometric identities: sin x

=

√

cos x

=

√

tan x 1 + tan2 x 1 1 + tan2 x

(2.129) (2.130)

where x denotes the optimal value for the phase in the expressions (note that x can equal ω0 t or ω0 t ± π). Due to the ambiguity of the x value, then the above two expressions can be positive or negative depending on whether x = ω0 t or

2-56

Fundamental Topologies

3.0

Normalised v_Cs

2.8 2.6 2.4 2.2 2.00.0

0.5

1.0

1.5 C_base/C_s

2.0

2.5

3.0

Figure 2.40: Plot of the normalised capacitor voltage versus Cbase /Cs . x = ω0 t ± π. Using these expressions we can write from(2.125): # " r 1 Cbase tan x √ vCsmax = Vd 1 ± √ ± Cs 1 + tan2 x 1 + tan2 x q   r Cbase − 1 Cbase Cs  q = Vd 1 − q + Cbase C C s 1 + Cs 1 + Cbase s   1 + CCbase s  = Vd 1 ± q Cbase 1 + Cs " # r Cbase = Vd 1 ± 1 + Cs

(2.131)

(2.132)

(2.133)

(2.134)

The negative solution does not make sense – the maximum voltage would be less than the input voltage. Therefore chose the positive solution, which gives: # " r Cbase vCsmax = Vd 1 + 1 + (2.135) Cs Remark 2.67 One can see from (2.135) that if Cs < Cbase that vCsmax increases, and for small values very large values of voltage would occur. The maximum capacitor voltage is impressed across the diode, and therefore has to be kept under control. Figure 2.40 shows a plot of this normalised capacitor voltage versus the Cbase /Cs value. As can be seen, if Cbase /Cs > 1 then the capacitor voltages

2.4 Basic Analysis of Switch Mode Converters

2-57

become quite large. However, one can also see that the Cs has to be fairly large to reduce the voltage to any significant margin. The above analysis was only approximate in that we neglected the Rs resistance in the circuit to get an approximate feel for the effect of the capacitance. However, in reality there is a resistor there, and it is required in order to prevent large currents from flowing into the switching transistor when the switch is turned back on. The differential equation for the circuit under this condition is: dvCf d2 vDf + Rs C s + vDf = −Vd (2.136) Lσ Cs dt2 dt where vDf is the diode voltage after t = 0 which is the instant that the diode snaps off. The initial conditions at this point are the initial inductor current of Irr and the initial capacitor voltage is zero (as was the case for the previous analysis). These conditions then lead to the boundary condition for the differential equation of vDf (0+) = −Irr Rs and: Irr Rs Vd Irr R22 dvDf (0+) =− − − dt Cs Lσ Lσ Using standard solution techniques one can show that the solution is: r Lσ Irr −αt e cos(ωα t − φ − γ) vDf (t) = −Vd − Cs cos φ

(2.137)

(2.138)

where: s ωα

=

α

=

φ

=

γ

=

1−

α2 ω02

Rs 2ωα Vd − Irr2Rs tan ωα Lσ Irr ω  α tan−1 α

!

−1

As in the previous case the maximum value can be found by taking the derivative, and then setting to zero and solving for the time. If this is done then the time at which the maximum voltage occurs can be found to be: tm =

φ+γ− ωα

π 2

(2.139)

If this is substituted into (2.138) then the normalised maximum reverse voltage across the diode is: s   2   Vmax Cbase Rs Rs =1+ 1+ + − 0.75 e−αtm (2.140)  Vd Cs Rbase Rbase  where Rbase =

Vd Irr

and Cbase is as defined previously.

2-58

Fundamental Topologies 2.4.10.2

Snubbers for Thyristors

RC snubbers, similar to those used for diodes, are also required for thyristor circuits. For example, when thyristors are being used in the controlled rectifier applications, when only thyristor is turned off by another being turned on, then there is a reverse recovery current that flows through the thyristor that is being turned off. This current will snap-off very rapidly when the reverse recovery is complete. The inductance of the circuit that this reverse recovery current is flowing through will result in a large voltage occurring across that device that is commutating off (i.e. undergoing the reverse recovery). If nothing is done about this the device may suffer failure due to over-voltage. Details of design to be presented later. In the meantime information can be found in [2].

2.4.10.3

Snubbers and Transistors

This section is incomplete – the analysis has not been completed. Refer to [2] for more details.

turn-off snubber

Snubbers are required for transistor switches in order to improve their switching trajectory. Transistors (regardless of whether they are BJTs, MOSFETs etc) experience stresses during turn-on and turn-off. These stresses are due to either higher than normal current through the device while there is substantial current across of the device (this usually occurs at turn-on due to diode reverse recovery), or higher than normal voltage across the device while there is substantial current flowing in the device (this usually occurs are turn-off due to stray inductances). Both of these situations can be managed by judicious use of snubber. A typical turn-off snubber circuit for a transistor switch in a step-down converter is shown in Figure 2.41. It is fairly obvious how this circuit works – when the transistor turns off the voltage across the capacitor cannot change instantly. Therefore as the current through the transistor falls it is transferred to the capacitor via the snubber diode. Whilst the voltage across the capacitor is less than the supply voltage the freewheeling diode around the current source remains off. Therefore this circuit keeps the voltage across the transistor near zero as the current through the device falls. Therefore the power dissipation in the transistor during the switching transient is low. Note 2.2 Note that most snubbers are essentially transferring energy from the silicon switching device to a passive component (e.g. a resistor). Therefore they may not improve the efficiency of a circuit, but the power dissipation may be easier to handle in a passive device as opposed to a transistor where critical function temperatures are of vital importance with respect to lifetime. Remark 2.68 Note that the turn-off snubber also helps prevent over-voltages on the transistor due to stray inductances. When diode Df turns on an equivalent LC circuit is formed with the leakage inductances in the circuit and the snubber capacitor. Normally a high voltage could be induced in the leakage inductance as the current changes when the freewheeling diode turns on, but with

2.4 Basic Analysis of Switch Mode Converters

2-59

the snubber capacitor there an LC circuit is formed that limits the voltage rise across the device.

I0

I Df

Vd

DS

RS

iC S

Figure 2.41: Turn-off snubber circuit for a transistor step-down converter. When the transistor switches back on, the diode DS in Figure 2.41 will be reverse bias. Hence the capacitor CS will discharge through the resistor RS . Providing the capacitor is largely discharged before the transistor is next turned off the circuit will function as described above. Remark 2.69 The discharge current through Rs resistor is added to the turnon current through the transistor. The turn-on current through the transistor can be quite large under some circumstances due to the stored charge in the freewheeling diode. This is the main reason for a turn-on snubber discussed later. Let us look in more detail at the reasons for the turn-on and turn-off snubbers. Figure 2.42 shows the various stray inductances in a transistor circuit that can influence the switching of the circuit. The L1 to L5 inductors are effectively in the switching path during turn-on and turn-off, and the affect the switching trajectories of the device (i.e. the v versus i relationship during the switching of the transistor).

Figure 2.43 shows a conceptual diagram of the turn-on and turn-off switching trajectories under the influence of the stray inductances. At t0 the transistor is on, and at t+ 0 the turn-off of the device begins. As the process proceeds the current through the device begins to fall and the voltage across the device begins to rise. The trajectory moves towards the point on the graph that is denoted

2-60

Fundamental Topologies L1

L2 Io

L5

Vd

L3

L4

Figure 2.42: Stray inductances that are important in a transistor switching circuit during turn-on [2]. with t1 . As the switching trajectory moves towards this point there is clearly power being dissipated in the device as there is simultaneously substantial current and voltage through and across the device. The over-voltage at t1 is due to the inductances in the circuit – i.e. Lσ = L1 + L2 + · · · + L5 and the didtC of the switch current as the device turns off. Note 2.3 The over-voltage at t1 would result in considerable extra power dissipation in the switching device, since there can often still be considerable current flowing in the device at the time of this over-voltage.

The device finally turns off at point t3 when it supports the full supply voltage and has zero current flowing through it. When the device turns back on, it follows the trajectory from t3 to t4 and up to t5 and finally t6. . The bump above the rated current at t5 is due to the reverse recovery of the freewheeling diode that has been taking the load current whilst the transistor has been turned off. As with the turn-off situation clearly one has considerable voltage across the device simultaneously with a more than rated current through the device at this point, which indicates that there will be considerable power dissipation due to this. In addition to this, the reverse recovery current could, in some cases, cause damage to the device over time. This is especially true if the switching device is a minority carrier based switch such as a bipolar junction transistor (BJT). These devices suffer from secondary break down due to a negative temperature coefficient resulting in hot spots in the device under circumstances similar to those just describe. Remark 2.70 During the turn-on phase the current being handled by the transistor is Io + irr where irr is the reverse recovery current of the diode. When the diode snaps off, it is only the irr component of this current that is undergoing a rapid rate of change, and consequently only the energy stored in 12 Lσ i2rr has to be handled by any snubbering circuitry.

2.4 Basic Analysis of Switch Mode Converters

Idealised switching loci

t5

iC

2-61

t6 t0

Turn-off t1

Turn-on

t4

0

C L¾ idt

t3

vCE

L¾ didtC

iC Vd

Io

Io

vCE t0 t1

t3

t4 L¾ = L1 + L2 + ¢ ¢ ¢

t5 t6

Figure 2.43: Current and voltage trajectories during turn-on and turn-off for a step-down transistor converter.

2-62

Fundamental Topologies Model of transistor switch during turn-o®

tfi iC

tfi iC

tfi iC

Io

Io

iDf

iDf

iDf

iCS

Vd

Vd

iC

CS

Vd

Vd

vCS

CS small

CS = CS1

CS big

iCS = Io ¡ iC

Figure 2.44: Equivalent circuit for the turn-off RCD snubber and approximate waveforms for different values of capacitance [2]. If one now considers the operation of the turn-off snubber with different values of capacitor Cs we get the plots in Figure 2.44. One can see that if the capacitor is small then the voltage across it does not stay low during the turn-off, and there can still be substantial current and voltage across the switch. The CS = CS1 is characterised by the fact that the capacitor charge time is exactly the fall time of the current. For the large value of capacitor the charge time is far longer than the fall time of the current. Consequently for the whole of the turn-off period the voltage across the switch has a very low value. Remark 2.71 Clearly, from a switch power dissipation perspective, the large value of CS is superior. However, the down side of this approach is that the energy stored in CS has to be dissipated in the RS resistor on the next turn-on of the switch. Therefore it is best, for efficiency reasons to choose a sensible compromise based on a balance between switch losses and RS losses. An optimum value can be found to minimise the total losses in the circuit [2].

Figure 2.45 shows the switching trajectories for the different values of capacitor shown in Figure 2.44. This simply confirms the comments in Remark 2.71.

turn-on snubber

A typical turn-on snubber is shown in Figure 2.46. As mentioned in a previous remark, the function of turn-on snubbers is to alleviate the large currents that can flow at turn-on due to reverse recovery currents from diodes that are conducting at the time of turn-on. As can be seen from Figure 2.46 the turn-on snubber works by using the inductance of the series inductance LS to limit the rate of rise of current during the turn-on phase. Therefore, since the diode Df will be a short circuit due to

2.4 Basic Analysis of Switch Mode Converters

2-63

iC SOA

Io CS = 0

CS small CS = CS1

CS large vCE

Vd

Figure 2.45: Switching trajectories for different turn-off capacitor values.

Df

I0

DLS

Vd LS

RLS

Figure 2.46: Typical turn-on snubber for a transistor step-down converter.

2-64

over-voltage ber

Fundamental Topologies

snub-

reverse recovery during for a period of time during the turn-on the LS inductor will be supporting approximately Vd volts across it, and hence the voltage across the transistor will almost be zero. The price paid for the turn-on snubber is that the energy stored in the LS inductor must be dissipated. In order to do this additional components RLS and DLS are included to provide a path for the current to flow when the transistor is turned off. When the current flows through this path there will be a slight over-voltage impressed across the transistor. The resistor RLS is chosen so that the current in the inductor will be dissipated in a reasonable time after turn-off – i.e. before the next turn-on. In addition it also has to be chosen so that the voltage rise on the transistor is not too great during turn-off as the inductor current flows through it. The final type of snubber we shall consider is the over-voltage snubber. This type of snubber is specifically designed to prevent over-voltage on the transistor due to the stray inductances in the circuit. It does not prevent voltages from appearing across the device during turn-off, and does not add any current at the turn-on of the device. The over-voltage snubber and the turn-off snubber should not be used at the same time. The basic structure for the over-voltage snubber is shown in Figure 2.47.

Ls

I0

Df

Rov

Vd Dov C ov

Figure 2.47: Over-voltage snubber for a transistor step-down converter.

In this circuit the voltage across the capacitor is at Vd when the switch is closed (diode Dov is reverse biased). When the transistor is switched off then diode Df turns on and the stray inductance Lσ causes diode Dov to turn on forming a resonant circuit with Cov . This allows the energy to flow into Cov pushing its voltage above Vd . The amount the voltage goes above Vd depends on the relative values of Lσ and Cov . The over-voltage across the capacitor then dissipates through the resistor back to the supply during the transistor off time.

2.4 Basic Analysis of Switch Mode Converters

Cov

2-65

Df

Io

Cd Vd

CS

T

RS

LS

Figure 2.48: Undeland snubber for a step-down converter circuit. Remark 2.72 As noted previously turn-off snubbers can perform the function of over-voltage protection. The question then arises why bother with the overvoltage snubber? The main reason is that there is more freedom to address the over-voltage problem without running into difficulties with the discharge time and subsequent resistance dissipation of the turn-off snubber. Also, in some other circuit configurations that employ turn-on snubbers, the over-voltage cadi pacitor serves to capture the energy from the dt limiting turn-on inductor. A snubber that attempts to combine aspects of all the previous snubbers, but with reduced component count is the Undeland Snubber. This combines characteristics of the turn-on, turn-off and over-voltage snubbers. Figure 2.48 shows an Undeland snubber for a step-down converter circuit.

2.4.11

Resonant and Soft-Switching Converters

This section of the notes will be undergoing a major revision during course presentation in 2005. The material below is still correct as far as it goes, but it is only a very brief and not particularly erudite presentation of some aspects of resonant converters. These notes will not look at resonant converters in any detail. These types of converters are not in the mainstream of converter technology at this time, and in fact some people in the switch mode power supply area think that they

2-66

Fundamental Topologies are a fad [5]. Nevertheless one should know what they are and what are their limitations. By the way I think that over time resonant converter technologies will certainly have increased application in specialist areas. Currently they are being used in areas where weight and losses are of particular importance (e.g. aerospace). A resonant converter is a converter that intentionally has a resonant LC tank circuit as a fundamental part of its operation. This tank circuit is excited by the switching of the converter, so that the resonance is maintained during operation. There are a variety of different topologies to achieve this operation. The reason for having this resonance is that if the switching of the main power devices occurs at the time when the voltage across, or the current through the device is zero. This means that the power dissipated in the device ideally is zero. Consequently it is possible to increase the switching frequency of the converter, without incurring excessive losses in the switching devices. In order to have some idea of the configurations of a resonant converters consider Figures 2.49 and 2.50. Figure 2.49 shows a resonant buck converter that is designed to switch when the current through the switch reaches zero. Figure 2.50 is a resonant buck converter which switches when the voltage is zero across the switch. We shall not look at the details of the operation of these (for details look in [2, 4]), but one can see that both circuits have the extra LC components represented by Cr and Lr . These are the components that represent the resonant circuit that is used to assist the switching of the power devices. SW

Lr

Lf

Io Vd

+ -

Cr

D

Cf

RL

Figure 2.49: A zero current switching (ZCS) resonant buck converter.

Remark 2.73 We shall see that the concepts used in resonant converters are actually very old. These ideas were originally used in forced commutated silicon controlled rectifier (SCR) circuits from as far back as the 1960s. Before considering the pros and cons of resonant converters we need to distinguish between them and the so-called soft switching converters (a name often used in the literature to mean a resonant converter). Soft switched converters are also known as quasi-resonant converters. A resonant converter is one in which the power waveforms (current and voltage) are sinusoidal, and switching occurs when the voltage and/or current go through zero. Therefore the switching losses (ideally) should be zero. The quasi-resonant converter on the other hand is intermediate between the resonant converter and the conventional PWM converter. The circuit of these converters is so arranged that it creates a tank circuit for a portion of the switching period so that the switch transitions are nearly lossless.

2.4 Basic Analysis of Switch Mode Converters

2-67

Cr Dr

SW

Lr

Lf

Io Vd

+ D -

Cf

RL

Figure 2.50: A zero voltage switching (ZVS) resonant buck converter. 2.4.11.1

Why One Should Not Use Resonant Converters

Resonant converters have several problems in practice. The first major one is that the switching frequency is a function of the load. This causes problems in the design of the EMI filters. A more serious problem is that it is common to use the parasitic capacitances as one of the elements in the resonant tank circuit. This makes is virtually impossible to build units that behave the same on the production line. The obvious solution to the problem is to parallel the parasitics with a capacitor that swamps its effects. However, this has the effect of lowering the oscillation frequency of the tank circuit, which is the whole objective of having the resonant converter in the first place. In addition to the above problems, resonant converters still have problems with large line voltage changes, short-circuited or unloaded outputs, and component tolerances in general. They also operate mainly at higher peak transistor currents for the same output power compared to conventional PWM inverters, and in some configurations at larger voltage stresses. 2.4.11.2

Why One Should Use Quasi-Resonant Converters

Before discussing the benefits of using these converters it may be beneficial to review the operation of a quasi-resonant converter. Consider Figure 2.51, which is a conceptual diagram of a quasi-resonant forward converter. Notice that the main difference between this converter and that of Figure 3.1 is the addition of the capacitor across the switch. The presence of the capacitor across the switch forms an LC circuit together with the magnetising inductance of the transformer. When the switch is opened, the voltage across the capacitor is zero. The current through the magnetising inductance will continue flowing into the capacitor, and a resonant ring begins. This ring will continue until the voltage on the capacitor falls back to the supply voltage. At this point the voltage on the magnetising inductance will be positive at the dot end of the primary. This will cause the diode rectifier in the secondary to turn on, and the remainder of the energy stored in the magnetising

switching frequency is a function of the load parasitic capacitances

2-68

Fundamental Topologies

D1

L +

N1

N2

D2

vL

iL

C

RL

Vo

Vd

SW

C SW

Vd

t Switch voltage

Figure 2.51: A quasi-resonant forward converter.

zero voltage switching

inductance is transferred to the load. One can see that the quasi resonant converter essentially forms a zero voltage switching (ZVS) device, since the voltage across the capacitor cannot change instantaneously when the switch is opened. One must be sure to choose the LC components so that the LC ring is complete before the start of the next control interval. However, this is not too limiting, and there is usually a reasonable range of components that can be chosen. Another possible problem is the presence of a charged capacitor across the switching device when it is turned on. However, a few calculations for practical situations show that the energy dissipated in a MOSFET switch due to this is very small. The major advantage of the quasi-resonant converter is the fact that it essentially works the same as the standard hard switched PWM converters, and the switching rate is determined by the PWM controller chip. Therefore the design of the filtering and EMI circuits is greatly simplified compared to frequency wild converters such as many of the pure resonant designs.

2.4.12

Example: ZVS Converter Design and Analysis

This example comes from a previous assignment in this course. Figure 2.52 is a diagram of a Zero Voltage Switching (ZVS) quasi resonant buck converter. The key equations for LC series circuits are as follows [2]. The equation for the current through the inductor is: iL (t) = IL0 cos ω0 (t − t0 ) +

Vd − Vc0 sin ω0 (t − t0 ) Z0

(2.141)

and the equation for the voltage across the switch capacitor is: vCr (t) = Vd − (Vd − VC0 ) cos ω0 (t − t0 ) + IL0 Z0 sin ω0 (t − t0 )

(2.142)

2.4 Basic Analysis of Switch Mode Converters

2-69

iLr vC r Cr Dsw

isw

Lr

Lo

iL

io » I o

+ Vin

-

Df

C bulk

Co

RLoad

vo

Figure 2.52: Zero Voltage Switching quasi resonant buck converter for example. where: 1 ω0 = √ Lr Cr r Lr Z0 = Cr iL (t0 ) = IL0 (the initial inductor current)

(2.145)

vCr (t0 ) = VC0 (the initial capacitor voltage)

(2.146)

t ≥ t0

(2.143) (2.144)

(2.147)

a. Explain how the circuit of Figure 2.52 works. Use the above equations above appropriately to augment your explanation. Provide sketches of the current through the Lr inductor, and the voltage across the capacitor vCr as the circuit moves through its very states of operation. b. Carry out a design of the circuit assuming 24V input, a 5 Volt output, 30→100 Watt output power range, 100mV output ripple, and continuous output current conduction. Make the resonant frequency 100kHz. c. Simulate the design to show that it works as designed. Solution Answer to Part (a) The fundamental assumption made in the following discussion is that the output can be modeled over one switching period as a constant current sink. Usually this assumption, for most realistic values of the output filter inductor, is reasonable. The following discussion is taken almost directly from Mohan[2]. This book gives a very clear explanation of the operation and behaviour of this circuit. The following explanation is with respect to Figure 2.53 from Mohan[2]. This diagram has been scanned from the text book, and therefore the quality is a little compromised. There are five main areas of operation is this figure. Each of these areas shall be discussed in turn.

2-70

Fundamental Topologies

Figure 2.53: Waveforms in the ZVS circuit (scanned from [2]) . Interval t0 → t1 The assumed starting point of the switching cycle is that the switch is opened at t0 (it has been closed up until this time), and that vCr = 0 and the current through the Lr inductor is the load current Io . The fact that vCr = 0 when the switch is opened means that this is a zero voltage switch operation. Since this current is constant then there will be no voltage across the inductor. Consequently the freewheeling diode will have a voltage across it of Vd Volts and hence will be off. This in turn implies that all the current will be flowing through the capacitor. Therefore as time progresses from t0 the capacitor will be linearly charging in the polarity shown in Figure 2.53. The equivalent circuit at this time is shown in the Figure. Therefore the expression for the voltage on the capacitor is: Z t Io vc = dt t ≤ t1 (2.148) C r t0 Interval t1 → t2 The next interval can be divided into several sub-intervals.

2.4 Basic Analysis of Switch Mode Converters

2-71

We shall discuss these in detail with the appropriate supporting equations. At time t1 the voltage across Cr becomes equal to Vd Volts, and therefore the voltage across the diode is 0 Volts. As t becomes greater that t1 then the voltage across the diode will attempt to go forward bias, and hence the free wheel diode will turn on and the load current will begin to transfer to it. The Lr current will also continue to flow in the Cr Lr part of the circuit. Since the right hand side of Lr is now connected to ground, the Cr Lr circuit now becomes a resonant circuit, where the initial condition in the circuit for the inductor current is Io . The inductor current for t1 ≤ t ≤ t2 is can be found by using the appropriate initial conditions in (2.141). In this case at t1 we have IL0 = I0 and Vc0 = Vd hence (2.141) can be written as: iL (t) = I0 cos ω0 (t − t1 )

t1 ≤ t ≤ t2

(2.149)

Similarly, for the capacitor voltage. We already know that the initial condition on the Cr capacitor at the beginning of the t1 time is Vd . Therefore we can write the expression for the voltage on the capacitor from (2.142) as: vc (t) = Vd + IL0 Z0 sin ω0 (t − t1 ) t1 ≤ t ≤ t2 (2.150) As can be seen from (2.150), the capacitor voltage is essentially that of a resonant circuit with a Vd voltage offset. Therefore the peak capacitor voltage is Vd + Z0 IL0 , and this occurs when the inductor current is zero. This is also the time when all of the load current is flowing through the freewheeling diode. At t = t01 the resonant current in the circuit will attempt to reverse in direction. There is no current in the inductor, and therefore no energy to keep the current flowing in the same direction. The voltage on the capacitor is in such a polarity to begin to make the current flow in the negative direction through the inductor. Consequently, as per (2.150) the voltage across the capacitor begins to decrease. The resonant pulse continues to t001 , at which point the voltage on the capacitor has reached the initial value at the start of the resonant cycle, and therefore in an offset sense is starting to reverse the voltage across it. This continues until time t2 when the voltage across the capacitor attempts to go negative. This is prevented by the diode Dr across the switch, which turns on. The situation at t2 is that freewheeling diode is still on, diode Dr has just turned on, the Lr inductor has a negative current flowing through it, and the freewheeling diode has both the load current and the negative Lr current flowing through it. Interval t2 → t3 During this interval the current through the Lr inductor, which is initially negative at t2 , will start to increase linearly. One can see from the equivalent circuit in Figure 2.53 that the rate of change of current through the Lr inductor is: Vd diL = dt Lr

(2.151)

2-72

Fundamental Topologies

vio

vio V0 Vd t0 t1

t2

Ts =

t3

t4

1 fs

Figure 2.54: Voltage across the freewheeling diode in the ZVS circuit. This linear increase in the Lr current will continue whilst ever the switch diode and the freewheeling diode are on. Immediately after t2 (between t2 and t02 ) the switch should be closed, and this will allow the current to flow through the switch when it attempts to reverse direction through the Lr inductor. If this is not done, then there will be a different resonant cycle through the Cr Lr components. This is undesirable, as one can end up with a non-zero voltage across the Cr capacitor, and there would be a non-zero voltage switch on of the switch in the next complete cycle. Interval t3 → t4 The switch is closed , therefore vCr is clamped at zero. The freewheeling diode is on and the Lr current at Io and freewheeling diode is off. At this point the whole sequence can now repeat if the switch is opened. Remark 2.74 The average output voltage for this circuit is controlled by controlling the period t3 → t4 . The period t0 → t3 is determined by the load current and the resonant circuit parameters, and is therefore not under the control of the circuit controller. Therefore if one wishes to have a lower average output voltage then t3 to t4 has to be made very short. Figure 2.54 shows the voltage waveform across the freewheeling diode. If the circuit is in steady state then the average voltage on the diode side of the Lf filter inductor has to be equal to the average output voltage. n Remark 2.75 It should be noted that the circuit has to be designed so that Z0 I0 > Vd . If it isn’t the resonant ring will not have sufficient amplitude to cause the voltage across the switch to become zero at time t2 . Therefore there would be a non-zero voltage switching if this occurs. This means that it is important to understand the minimum output current in order to make sure that zero voltage switching occurs under all load conditions. n Answer to Part (b) The first part of the design is to work out the resonant circuit components. There are two factors that must be taken into account when designing these components:

2.4 Basic Analysis of Switch Mode Converters

2-73

• The resonant frequency required – in this case 100kHz. • The minimum current that will be pulled through the converter. This value will determine the Z0 I0min value. This must be larger than all values of Vd in order to ensure ZVS under all circumstances. These two constraints can be used to determine the two circuit parameters. The specifications say that the minimum power the circuit has to supply is Po = 30 Watts at a voltage of 5 Volts. Therefore Iomin = 6Amps. We only have to cope with a constant input voltage of 24 Volts. The key equations are: 1 √ 2π Lr Cr 1 ∴ Lr C r = 4π 2 fr2 fr =

(2.152) (2.153)

In relation to the minimum power requirement we have: Z0 Iomin ≥ Vd r Now Z0 = ∴ Lr ≥ Cr

(2.154) Lr Cr 

(2.155) Vd

2

(2.156) Iomin 2  P Vd 30 Now Iomin = oVmin = = 6Amps. Therefore = 16. We shall choose 5 Iomin o this value to be 20, so that it is well above the minimum value. Using (2.156) we can write Lr = 20Cr . Using this expression in (2.153) we can after a little manipulation write: s s 1 1 = = 0.3559µF (2.157) Cr = 80π 2 fr2 80π 2 (100e3 )2 Therefore using Lr = 20Cr we have that Lr = 7.112µH. As a check these values give: Z0 Iomin = 26.83

(2.158)

which is clearly greater than the 24 Volt supply. In order to have continuous conduction the output filter inductor must be able to supply the energy for the whole of the period whilst the switch is open. As noted previously, the time that the switch is open in this circuit is not a controllable quantity, but is dependent on the circuit parameters and the output current. The precise answer to this question could be quite complex due to the fact that the output current varies the time that the switch is open in the circuit. In order to make the design robust to variations in design parameters and variations in circuit operational conditions that occur in real life, I will take a conservative approach to the design of the filter inductor. This conservative approach manifests itself in the calculation of the time that the switch is open. When the switch is open, ignoring the ramp slope

2-74

Fundamental Topologies shown in Figure 2.54 and assuming the output voltage is constant, we can write the following expression under steady state conditions for the voltage across the filter inductor: −Vo topen + (Vd − Vo )tclosed = 0

(2.159)

where topen is the effective time that the switch is open, and tclosed is the effective time that the switch is closed. The word effective relates to the fact that the actual time that the switch is open and closed is not related to the true time that these switches are open and closed for this converter. This is due to the fact that the voltage appearing across the output filter inductor does not correspond to the actual points where the switch is switched. Clearly equation (2.159) implies that for the system to be in steady state:   Vo topen (2.160) tclosed = Vd − Vo Remark 2.76 Note that this expression contains an implicit assumption because the slope on the diode voltage waveform when the switch is first opened is being ignored. The expression in its full form becomes a function of the resonant capacitor and the load current since these determine the time for the slope. n In addition we require that the average current over the total switching cycle is is equal to the Iomin = 6Amp current. Since the current waveform in the filter inductor (Lo ) is a triangular waveform, this implies that the average over half the period also equals the same value. The next question to resolve is the value of the topen time. This is where the worst case analysis comes in. One could calculate from the resonant waveform and the current value what the precise time is for the capacitor voltage to go to zero at t2 . The time from t2 → t3 could then be calculated. This together with the linear charge time of t0 → t1 gives the total effective open time for the switch. A more conservative approach is to assume the maximum possible effective open time for the resonant frequency chosen. For the resonant part of the cycle this is the time to the negative peak of the resonant capacitor voltage plus the linear charge time of the capacitor and the linear current increase time from t2 → t3 . If the circuit is continuous for this time it will be continuous under all contingencies for ZVS for this circuit design. We shall now calculate topen . The linear charge time t0 → t1 is given by: δt0→1 =

Cr Iomin

Vd =

0.3559e−6 × 24 = 1.4236e−6 secs 6

(2.161)

Three quarters of the resonant period is 7.5µsecs – this is the time to when the resonant capacitor voltage has reached its maximum negative value in the worst case. As mentioned above we are assuming that this is the time when the total voltage across the capacitor is zero. The final time to calculate is the time it takes the current in the Lr to again reach Iomin from zero. This time is: Lr Iomin Vd 7.112e−6 × 6 = = 1.778e−6 secs 24

δt2→3 =

(2.162) (2.163)

2.4 Basic Analysis of Switch Mode Converters

2-75

Therefore the total effective time that the switch is open is, adding to the times calculated above, equal to topen = 10.7016µsecs. The actual physical maximum switch open time is: tphy open = 1.4236e−6 + 7.5e−6 = 8.9236µsecs

(2.164)

where tphy open is the actual true physical time that the switch is open. Note again that this is NOT the effective open time. These times give the time axis in calculation of the average current under the inductor ripple current. Assuming that this current is on the verge of discontinuity, then it is a triangle that starts at zero, goes to a maximum value and then back to zero at the end of the switching interval. Remark 2.77 This is an interesting situation. In the analysis for the converter we make the assumption that the current through the output filter inductor is more or less continuous and constant at the average current value. Indeed we sometimes model it as a current source. However in the situation of being the verge of discontinuity and the Lr inductor current reaching zero at the negative maximum voltage of the Cr capacitor, both the current in Lo and Lr are zero. Therefore the effective inductor for the current build-up is Lr + Lo . A situation completely violates the assumptions we made to establish the operation of the circuit. The waveforms applied to the output side of the circuit do not appear as shown in Figure 2.54. n Keeping in mind the limitations of the analysis from the previous remark, we still need to make some sort of an estimate for the Lo filter inductor value. During the topen time we shall assume that the current is freewheeling through the diode. If the output side of the circuit is on the verge of discontinuity, then this current will approximately reach zero during this period. If the iLo current is assumed to be triangular in shape then the average current is iave = 12 ipeak . Therefore, since iave = Iomin = 6A then ipeak = 2Iomin = 12A. So this is the value of current that has to decrease to zero during topen when the voltage applied to the inductor is −Vo .   Vo ipeak = topen (2.165) Lo and the average current for a triangular waveform such as this is 12 ipeak . Since the average current has  to be Iomin = 6Amps the ipeak = 2Iomin and using Vo Vd −Vo

the fact that tclosed = Vo Vd

=

5 24

topen from equation (2.160) and realising that

= 0.2083 allows us to write5 : 

 Vo topen 2Iomin   Vo 5 = = × 8.92e−6 = 3.71µH 2Iomin 2×6

Lo =

(2.166) (2.167)

The final section to the design is capacitor design for the output. The specification says that the ripple has to be less than 100mV. The equation developed 5 See

remark below with respect to the meaning of the following value of inductance.

2-76

Fundamental Topologies in the notes for working out ripple can be used for this situation. This equation uses the concept of duty cycle. As can be seen from Figure 2.54 the effective waveform across the output is similar to that of a conventional hard-switched converter. Therefore the same relationships hold with respect to duty cycle. One of the main results we found previously when considering hard-switched converters is that the output voltage is a function only of the duty cycle in steady state, regardless of the load current. A similar property applies in this case. Notwithstanding the approximations with respect to the wave-shapes in5 ) = 13.518µsecs. volved, the switching period is Ts = topen +tclosed = topen (1+ 24−5 5 The switch closed time is tclosed = 24−5 topen = 2.8162µsecs. Therefore the switching frequency is fs = 73975Hz under steady state conditions for all load currents. Using the traditional definition of the duty cycle we can write: Deff =

2.8162 tclosed = = 0.2083 topen + tclosed 2.8162 + 10.7016

(2.168)

Remark 2.78 We have to use the effect duty cycle, because the switch is actually closed after 8.9µsecs, but voltage is not applied at the output until the iL = Io – i.e. the resonant inductor (Lr ) current has reached the load output current. Consequently duty cycle cannot be defined by the true on and off times of the switch as in other converters. n The expression for the ripple form the notes is: Co =

1 − 0.2083 1 − Deff =  ∆v 8 × 739752 × 3.71e−6 × 8fs2 Lo Voo

0.1 5

= 244µF

(2.169)

Remark 2.79 The values for the filter inductor and capacitor are very much the worst case values. In fact the inductor has been chosen so that the ripple current is the maximum possible value before the current becomes discontinuous. As can be seen from the value it is smaller than the value of the inductance in the resonant circuit. One of the key approximations made in the above analysis was that the current through the Lo inductor could be considered constant over a switching cycle. Clearly if the ripple current is of the order of the average current itself then the Lo inductor cannot be considered to be a virtual current sink. If this assumption is not correct then all of the previous calculations will be thrown out by a significant amount. Therefore a value of Lo should be chosen that is much larger than the minimum value chosen, and also much larger than the resonant inductor value as well so that it sees this inductor as a current sink. We shall choose a value for the filter inductor of Lo = 300µH. This value is somewhat arbitrary but is two orders of magnitude above that previous calculated, and, more importantly is significantly larger than the resonant inductor. It is not a ridiculously large value that would make it difficult or expensive to manufacture. n If we use the value of Lo = 300µH then we can recalculate the value of the filter inductor. Substituting this value of Lo into (2.169) we get: Co = 3µF

(2.170)

2.4 Basic Analysis of Switch Mode Converters

2-77

iLr vC r C r = 0.3559mF

Dsw

isw

Lr = 7.112mH

Lo = 300mH

iL

io » I o C o = 3m F

+ Vin

-

Df

C bulk

RLoad

vo

Figure 2.55: Final design of the resonant buck ZVS circuit. This completes the design calculations for the power supply under minimum current conditions. The completed design is show in Figure 2.55 with the circuit parameters shown. If the circuit is operating at maximum power the operational frequency of the converter will change. This is due to the fact that in the t2 → t3 time will be longer. You may recall from (2.151) that the rate of increase of the iL current is only related to the input voltage and the value of Lr . Since the negative current starting point when the switch is re-closed is a large value, then clearly this time will be much larger. This means that the effective topen time of the switch will be much longer, and consequently the tclosed time will need to be longer to compensate for this increase in time. Remark 2.80 The point made in the previous paragraph is a negative for the ZVS resonant converter. It appears to be much more susceptible to load effects with respect to the switching frequency as compared to the ZCS form of the converter. n The worst case rise time of the current is: δt2→3 =

Lr 7.112e−6 δiL = × 40 = 11.85µsecs Vd 24

(2.171)

Therefore the total worst case time for there to be no voltage applied to the output inductor is: topen = 10.7016e−6 + 11.85e−6 = 22.5516µsecs

(2.172)

Remark 2.81 This value is likely to be quite inaccurate because it was derived using worst case assumptions – we used you may recall the three quarters point in the resonant cycle for the worst case resonant time. In the high current case this will be more in error because of the large amplitude of the resonant pulse. n The effective duty cycle has to be such as to produce the correct average output voltage. As in the previous analysis we have: tclosed =

5 topen = 5.93µsecs 24 − 5

(2.173)

2-78

Fundamental Topologies ZVS Resonant Buck − Ideal current sink load at 6 Amp

M

period: 12.8u

Switch sig

(A) : t(s)

7.5

Lr inductor current

5.0 (A)

2.5 0.0 −2.5 −5.0 −7.5

(V) : t(s)

60.0

locmax: (0.0016679, 50.81)

Cr cap voltage

50.0

(V)

40.0 30.0 20.0 10.0 0.0 −10.0

(V) : t(s)

40.0

Diode voltage

30.0

(V)

20.0

10.0

Ave: 5.0797

0.0

−10.0

1.66m

1.67m

1.68m

t(s)

1.69m

1.7m

1.71m

Figure 2.56: ZVS circuit without output filter but with an ideal current source load at 6 Amps. Therefore the effective duty cycle becomes in this case: Deff =

tclosed 5.93 = 0.2083 = topen + tclosed 22.5516 + 5.93

(2.174)

as was found previously. The new switching frequency is: fs =

1 1 = = 35110 Hz −6 topen + tclosed 22.5516e + 5.93e−6

(2.175)

Remark 2.82 One can see that the frequency of operation has dropped significantly. This will therefore affect the output filter components dramatically if the same ripple is to be obtained. n Answer to Part (c) In this section we consider the simulation results. The first set of results in Figure 2.56 are for the light load case where the load is modeled as an ideal current sink of 6 Amps. As can be seen the frequency of operation and the waveform amplitude are as predicted in the design. If we include the load filter in the circuit, but still with an ideal current sink as the load, then we can the results shown in Figure 2.57. As can be seen the results are largely the same as those in Figure 2.56.

2.4 Basic Analysis of Switch Mode Converters

2-79

VS resonant buck − I_o = 6Amp, LoCo filter, Current Source Load.

M n_15 period: 12.8u

(A) : t(s)

7.5

Lr inductor curret

5.0 (A)

2.5 0.0 −2.5 −5.0 −7.5

(V) : t(s)

70.0 X_Max: (0.008055, 50.79)

60.0

Cr voltage

50.0

(V)

40.0 30.0 20.0 10.0 0.0 −10.0

(V) : t(s)

Vo

5.1 5.075

PK2PK: 0.0838

5.05

(V)

5.025 5.0 4.975 4.95 4.925 4.9

8.035m

8.04m

8.045m

8.05m t(s)

8.055m

8.06m

8.065m

Figure 2.57: ZVS circuit with output filter and ideal current source load at 6 Amps. Finally if we include a resistor in circuit. The Saber model appears in Figure 2.58, and the results of the simulation with a 6 Amp output current appear in Figure 2.59. As can be seen the results are very similar to the ideal cases. The ripple current is within specification. If we increase the output current to the full load value of 20 Amps then we have to make a change in the frequency and the timing in the circuit. The result of the simulation of this circuit appears in Figure 2.60. As can be seen the frequency of operation at 45872Hz is different from that calculated, mainly due to the different time for the resonant pulse. This was noted as a point of inaccuracy above. The rise time of the inductor current is virtually exactly as calculated. The waveforms have again the correct form as discussed earlier. Remark 2.83 In order to get a more accurate design one would need to precisely calculate the resonant pulse width for the Cr capacitor voltage. n Remark 2.84 One very interesting observation from the results in Figure 2.60 is that the output ripple has not increased as we had predicted. The reason for this is subtle. When we calculated the ripple we were assuming a normal buck converter operating in continuous current mode. However, in the ZVS resonant converter case during the period of t2 → t3 the Lr inductor current is building up, and therefore not all the current being supplied to the the load is having to be supplied from the Lo inductor. Therefore it does not use as much stored energy, and hence it is able to keep more continuous current flow. Therefore the ripple specification is satisfied without having to change the output filter capacitor. n

2-80

Fundamental Topologies

period:12.8u bits:[(tx=0,bit=_1),(tx=1n,bit=_1),(tx=1.1n,bit=_0),(tx=8.5u,bit=_0),(tx=8.5001u,bit=_1)] prbit_l4 BIT STREAM

ref:l1

sw1_l4

ref:l2

7.112u

pwld

300u

pwld ref:pwld2

ref:c3

0.3559u

pwld

v_dc 24

ref:c2 0.8333

3u

gnd

Figure 2.58: Saber circuit used for the 6 Amp full simulation.

ZVS resonant waveforms, with output filter and resistor − 6 Amp output

M n_15 period: 12.8u

(V) : t(s)

V_o

5.05

5.025 PK2PK: 0.06894

(V)

5.0

4.975

4.95

4.925

(V) : t(s)

60.0

Cr voltage

50.0

Maximum: 50.82

(V)

40.0 30.0 20.0 10.0 0.0

(A) : t(s)

−10.0

7.5

Lr current

5.0 (A)

2.5 0.0 −2.5 −5.0 −7.5

4.305m

4.31m

4.315m

4.32m

4.325m

t(s)

4.33m

4.335m

4.34m

4.345m

4.35m

Figure 2.59: ZVS circuit with output filter and resistive load at 6 Amps.

2.4 Basic Analysis of Switch Mode Converters

2-81

ZVS resonant buck − Io=20Amp, Output filter and R load

M n_15

(A)

period: 21.8u

(A) : t(s)

20.1 20.0 19.9 19.8 19.7

Lo current

(V) : t(s)

(V)

40.0

Diode voltage

Delta X: 4.224u Delta X: 17.276u

20.0

0.0

−20.0

(V) : t(s)

5.02

Vo ripple

(V)

5.0

PK2PK: 0.062998

4.98 4.96 4.94 4.92

(V) : t(s)

150.0

Cr voltage

X_Max: (0.0063686, 112.83)

(V)

100.0

50.0 Delta X: 5.9446u 0.0

(A) : t(s)

(A)

40.0

Lr current

20.0

Delta X: 11.85u

0.0 −20.0

6.33m

6.34m

6.35m

t(s)

6.36m

6.37m

6.38m

Figure 2.60: ZVS circuit with filter circuit and resistive load, output current 20 Amp.

2-82

Fundamental Topologies

Chapter 3

Switch Mode Power Supplies 3.1

Introduction

In the previous chapter we looked at some fundamental topologies for switch mode converters. In this chapter we shall build on this basic information by considering some topologies that are used for commonly available switch mode power supplies (SMPSs). Towards the end of the chapter we shall consider some aspects of the control of these power supplies.

3.2

Isolated Converter Topologies

The converters presented in the previous chapter were all non-isolated converters. However, in practice isolated converters are very common. This is due to the fact that these converters do offer electrical isolation, but more importantly that allow the simple production of a number of voltages that are all electrically isolated. In this section the isolated converters will be related back to the basic topologies of the previous chapter. We do not look at all possible isolated topologies, since there are far too many to do this. Instead we concentrate on the basic types, from which all the others have common features. The fundamental principles of operation are emphasised.

3.2.1

The Forward Converter

Figure 3.1 shows the basic idealised circuit for the forward converter. The forward converter is derived from the buck converter shown in Figure 2.2. The connection between the two converters is not obvious at a first glance. One may recall that the main distinguishing feature of the buck converter is that when the switch is closed the input is connected to the output. In the case of the forward converter this is not literally true due to the isolation of the transformer. However, when the switch is closed the secondary side of the transformer is reflected to the primary, so in effect this connection exists. When the switch in the buck converter is opened then the input is disconnected from the output. In the forward converter this occurs due to the fact that the voltage across the transformer reverses (because of the trapped flux in

simple production of a number of voltages

3-2

Switch Mode Power Supplies the transformer), and the diode D1 is reversed biased and disconnects the load from the transformer secondary. Remark 3.1 The above-mentioned trapped flux in the magnetising inductance of the transformer is a new problem that does not exist in the conventional buck converter. If one were to operate the forward converter as described in the paragraph above then the switch would be destroyed by the very high voltages created as the flux in the magnetising flux attempts to maintain the current through the open switch.

D1

L +

N1

N2

D2

vL

iL

C

RL

Vo

Vd

SW

Figure 3.1: Basic circuit of the forward converter. practical converter

forward

Figure 3.2 shows a practical forward converter circuit. In this circuit we introduce a third winding to transfer the energy trapped in the magnetising inductance back to the supply. This winding plays no part when the switch is turned on, but when the switch is turned off and the voltage across the magnetising inductance reverses then, due to the turn direction of the third winding, diode D3 turns on and current flows back into the supply. This limits the rate at which the flux collapses in the magnetising inductance, and therefore the voltage induced by this collapse is controlled. The operation of the circuit can be better understood by referring to the equivalent circuit in Figure 3.3. This circuit is based on using the concept of the ideal transformer that does not require any mmf to operate.1 Ignoring the leakage inductances, the flux is stored in the Lm inductance. When the switch is closed current builds up in this inductance, and at the same time current, i1 flows into the transformer. The voltage v1 appears across the magnetising inductance, and this is reflected via the transformer voltage ratio to 1 The transformer has a magnetic structure with infinite permeability and consequently the coupling between the windings is one. This also implies that the primary winding has infinite inductance.

3.2 Isolated Converter Topologies

3-3

D1

L

N3

vL

+

N1

N2

iL

-

D2

RL

C

Vo

Vd D3

SW

Figure 3.2: A practical forward converter.

Ideal transformer i3 Ll1

i2

i1

Ll 2

L

D1

N3

Lm

im v 1 N 1

+ N2

D2

vL

iL

-

C

RL

Vd D3 v sw

SW

Figure 3.3: Equivalent circuit for a practical forward converter.

Vo

3-4

influence of leakage inductance

Switch Mode Power Supplies winding 2 (the secondary). Similarly the current i1 is reflected as i2 in winding 2 via the transformer current ratio. This current then feeds the load via the output LC filter. When the switch is opened then the current im flowing in the magnetising inductance cannot stop instantaneously. As can be seen from the equivalent circuit the current can flow in a loop via the ideal transformer. The dot relationship between the primary and ternary winding means that the voltage Vd appears across the ternary winding. This voltage is reflected to the primary winding voltage as v1 = −Vd . This implies that vsw = 2Vd . Therefore, the presence of the third winding keeps the voltage across the switch to a reasonable and controllable value, and essentially returns the energy trapped in the magnetic field of the magnetising inductance to the supply. The above discussion omitted the influence of the leakage inductance. Unfortunately the presence of leakage disrupts the ideal operation. If we again consider Figure 3.3, we can see that the leakage inductance carries im + i1 , and therefore it would store the energy 21 Ll1 (im + i1 )2 . As with the magnetising current this stored energy will attempt to maintain the current in the same direction. Therefore when the switch is opened a large voltage can be produced across this inductance, which would also result in a high vsw voltage. Even for fairly small values, the voltage produced could result in the destruction of the switch. Remark 3.2 In order to minimise the leakage inductance the primary and ternary winding are often bifilar wound – i.e. they are both wound on the same arm of the transformer. The secondary may not be wound like this as large voltage isolation between the primary and secondary is often very important. Remark 3.3 In order to catch any voltage spikes associated with the leakages one may need some “snubbers” across the switch. Remark 3.4 The wire used for the ternary winding can be much smaller gauge than the secondary winding as it only has to carry the magnetising current of the transformer. Now let us consider the operation of this forward converter in a little more detail. Assuming for the moment that we are dealing with the ideal forward converter as depicted in Figure 3.1, and assuming that the transformer is ideal. If the switch is turned on, then there will be current flowing through the transformer primary, and hence the secondary. Since the voltage ratio of a transformer is: v2 N2 = v1 N1

(3.1)

then we can deduce that: vL =

N2 Vd − Vo N1

for 0 < t < ton

(3.2)

which is a positive value, causing iL to increase in value. When the switch is turned off then the diode D1 is reverse biased, effectively disconnecting the transformer from the remainder of the secondary side

3.2 Isolated Converter Topologies

3-5

circuit. The trapped energy in the filter inductor causes the diode D2 to turn on, allowing current to circulate. In this case the inductor voltage is: vL = −Vo

for ton < t < Ts

(3.3)

which is negative, resulting in a decreasing current in the filter inductor. If one integrates the inductor voltage over one complete period and equate to zero one gets: N2 Vo = D (3.4) Vd N1 Remark 3.5 One can see from (3.4) that the voltage ratio is the same, in principle, as that for the buck converter. However, whilst a buck converter can only produce voltages less than the input voltage, the forward converter can produce voltages that are greater than the input voltage with an appropriate turns ratio for the transformer. As we have previously noted, in a practical forward converter one must account for the energy trapped in the magnetising inductance. Let us now consider how this requirement alters the operational range of the converter output voltages. The following discussion is with reference to Figures 3.3 and 3.4. v1 Vd

t N1 -

N3

tm

Vd

t off

t on Ts isw

i1

im

t iL

i1 = im

t

Figure 3.4: Current waveforms for a practical forward converter.

forward converter voltage ratio

3-6

Switch Mode Power Supplies When the switch is closed then: v1 = Vd

for 0 < t < ton

(3.5)

and the current through the magnetising inductance, im , increases at a linear rate (as can be seen in Figure 3.4). When the switch is opened at time ton , the imton must instantaneously keep flowing. This is achieved via the primary coil of the ideal transformer. Note 3.1 The capacity for the magnetising current to flow through the primary of the ideal transformer is due to a property of transformers. The circuitry connected to the secondary winding of the transformer is reflected (via a turns ratio relationship) to the primary. Therefore, the current is actually flowing in the secondary circuit, but reflects in such a way as to create the illusion that it is flowing in the primary. From this point of view Figure 3.3 is a little deceptive. When the switch is opened, as previously mentioned, the voltage induced in winding 2 is such that the diode D1 is reversed biased, thereby disconnecting the secondary circuit. At the same time, diode D3 turns on due to the voltage induced in winding 3. Therefore this winding effectively becomes the secondary under this condition. Under this condition the currents flowing in the circuits are: i1 = −im , i2 = 0 and i3 becomes (from the normal current ratio for an ideal transformer): N1 im (3.6) i3 = N3 During the time tm , when the i3 current flows, the voltage across the transformer primary is: N1 for ton < t < ton + tm (3.7) v1 = − Vd N3 since Vd is the voltage across winding 3. When the transformer demagnetises, then im = 0 and v1 = 0. The time can be obtained by realising that the time integral of the voltage across the magnetising inductance must be zero over a complete time period (for steady state operation). Considering Figure 3.4 one can see that: Vd DTs −

Forward converter maximum duty cycle

N1 V d tm = 0 N3 tm N3 ∴ = D Ts N1

(3.8) (3.9)

If the transformer has to be totally demagnetised before the start of the next control interval, then the maximum value of tm /Ts = 1 − D. Therefore the maximum duty cycle, using (3.9) is: N3 Dmax N1 1 = 3 1+ N N1

(1 − Dmax ) =

(3.10)

∴ Dmax

(3.11)

Remark 3.6 Equation (3.11) indicates that the maximum duty cycle is 0.5 if N1 = N3 (a common choice in many designs).

3.2 Isolated Converter Topologies 3.2.1.1

3-7

Other Forward Converter Topologies

We shall not go into detail into the other forward converter topologies, but shall simply show the basic design and highlight a few pertinent properties. Only a subset of the available of forward converter topologies will be presented. 3.2.1.1.1 Two Switch Converter This topology is shown in Figure 3.5. In this converter each of the switches are turned on and off simultaneously. Consequently each switch only has to stand a maximum voltage of Vd . One of the other nice features of the circuit is that the magnetising and leakage currents can flow via the diodes to the supply, thereby eliminating the ternary winding on the transformer, and negating the requirement for snubbing across the switches. A Dmax = 0.5 limitation applies to this converter.

SW1

Vd

N1

N2

Vo

SW2

Figure 3.5: Circuit diagram of a two switch forward converter.

3.2.1.1.2 Push-Pull Converter This topology is shown in Figure 3.6. The salient feature of this topology is the centre tap transformer used. One of the main limitations of the previous forward converters was that the duty cycle was limited to a maximum value of 0.5. This limitation occurred due to the need to demagnetise the transformer prior to the start of the next switching cycle. The push-pull form of the forward converter effectively allows one to get a full duty cycle range, at the cost of a more elaborate transformer and two switching devices. We shall spend a little more time investigating this circuit because a few important concepts can be gleaned from this that are of use in Power Electronics and circuits in general. One can see from Figure 3.6 that only one half of the transformer is active at any one time, since only one of the switches is turned on at any one time. For example, if SW1 is closed then current will flow from the supply via the

3-8

Switch Mode Power Supplies D1

Vd

N1

N2

N1

N2

L

C

RL

Vo

D2

SW1

SW2

Figure 3.6: Push-pull forward converter.

top half of the primary through SW1 . This will result in a voltage developing across the top half of the secondary winding consistent with the dot convention of the windings. The resultant current flows via diode D1 to the load. If SW2 is closed (then SW1 is open) a similar pattern occurs. In this case the current flows from the source via the bottom half of the primary through SW2 . The dot convention with this half of the primary in relation to the secondary means that diode D2 is forward biased (and D1 is reverse biased). Therefore again current flows to the load. The diode arrangement on the secondary is a conventional full wave rectifier circuit. As with the previous cases one ends up with magnetic energy trapped in the magnetising inductance of the primary. In this particular case the other half of the primary winding that is not conducting current when the corresponding switch is closed corresponds to the ternary winding shown in Figure 3.2. The two halves of the primary essentially form an autotransformer. If we operate the circuit so that there is a period of operation when both of the switches are off, then a question that immediately arises is “what happens to the trapped magnetic energy in the core of the transformer?”. This turns out to not be an easy answer in the sense that the solution takes a deal of insight into how transformers work. We shall consider the operation of the circuit if both switches are in the off state using two approaches – the first is the conventional equivalent circuit approach, and the second is based on realising that the total mmf in the circuit cannot change instantaneously. Consider the situation where switch SW1 has been closed and then it has been opened. Switch SW2 is left open. When SW1 was closed then the top half of the secondary transformer would be positive, and consequently the diode D1 is forward biased. We shall assume that the filter inductor L is large enough that the current iL is constant. Hence the current iL flows through D1 . When SW1 is opened then there is flux in the core of the transformer. This flux must be maintained by a current. This current is often called the magnetising current, and it is assumed to flow through a “fictitious” circuit element called

3.2 Isolated Converter Topologies

3-9

the magnetising inductance. This element is usually placed in the primary side of a transformer. From Figure 3.7 one can see that the current flowing through SW1 is composed of two components – the load current (with the appropriate turns ratio) and the magnetising current. Normally the magnetising current is small compared to the load component. We are assuming that the transformer is ideal – i.e. it does not require any mmf to magnetise it. The magnetising current is flowing through the magnetising inductance to produce the flux that is present in any “real” transformer. When SW1 is opened then we have the situation shown in Figure 3.8. On the primary side of the transformer there are two main effects to consider. The current shown in Figure 3.7 flowing through the leakage inductance of the primary (Ll ) wishes to continue flowing. Therefore a voltage is developed across the leakage in an effort to achieve this. This voltage appears in conjunction with the supply voltage across SW1 – this is voltage vLl +Vd in Figure 3.8. A snubber is often required across the transistors to cope with this voltage spike. Ideal transformer

Vd

N2

Ll

N2 N1

SW1

i L + im

N1

im

iL

Lm Vd

D1

N2

L iL

Vd

N1

N2 N 1

N1

N2 N2 V N1 d

C

RL

Vo

D2

Diode is open circuit.

Figure 3.7: Currents flowing in the push-pull forward converter with SW1 closed.

The second salient point on the primary side of the circuit is that the current flowing through the magnetising inductance cannot be changed instantaneously. Therefore a voltage would normally develop across the magnetising inductance in an effort to maintain this current. This voltage has a polarity with the positive on non-dotted terminal of the top half of the transformer. However, this is coupled by the ideal transformer to the secondary. This would produce a positive voltage on the non-dotted terminals of the secondary. Consequently the diode D2 would become forward biased. Diode D1 also remains forward biased as well, meaning that the (constant) iL current splits between D1 and D2 . This then provides a path for the magnetising current to flow. If this circuit was a normal push-pull inverter circuit then the diode across SW2 would turn

3-10

Switch Mode Power Supplies Ideal transformer

Vd

Ll

+

D1

im

vL

iL

l

im

Lm

N1

N2

2

-

N1 N2

L

im

iL

C

RL

Vo

iL

+ SW1

v L +Vd

N1

N2 i L

2

+

N1 N2

im

l

D2

Both diodes short circuit

Figure 3.8: Currents flowing in the push-pull forward converter with SW1 and SW2 open. on and clamp the voltage across the top half of the winding to Vd . However, the presence of the full wave rectifier circuit on the secondary side of the circuit changes this “normal” scenario. One point that is not obvious in Figure 3.8 is why does the current iL split between the two secondary windings? When D2 becomes forward biased why doesn’t D1 become reverse biased? The answer to these questions is that the constant load inductor current prevents this from happening. If D1 attempts to turn off, then the load current would immediately be diverted into the lower half of the secondary. This would mean that a voltage would be induced in this part of the winding (since a rate of change of flux in the core would result) such that diode D2 would turn off, and D1 would turn on. Therefore the stable situation is that shown in Figure 3.8. Note that due to the dots on the secondary, the iL /2 current in each half of the windings would produce fluxes that cancel each other. Therefore the only component of flux producing current is the magnetising component reflected into the secondary which circulates around the loop comprising the two diodes and the transformer secondaries. Another way of reasoning this is to realise that when SW1 is opened the reflected iL current must become zero. Consequently the effective iL current through the secondary of the transformer must also be zero (else we cannot have zero reflected iL on the primary side). Given that iL is held constant by the filter inductor, the only way that this can be achieved is if there is net zero flux produced by the secondary winding due to iL . This is achieved by D1 and D2 both being on, since this results in flux cancellation in the secondary winding. There is an alternative way of reasoning the splitting of the inductor current between the two secondary windings. This technique is simple, and can be applied to very complex coupled winding situations. For the moment consider the transformer to be ideal – i.e. the magnetising inductance is infinite. With SW1 closed all the current flowing in the primary is reflected into the secondary. In terms of mmf, an ideal transformer does not require any mmf to set up the

3.2 Isolated Converter Topologies

3-11

flux in the core. Therefore we have: N1 i1 + N2 iL = 0

(3.12)

i.e. no net mmf in the transformer. When SW1 opens the net mmf in the core cannot change since the transformer is ideal – i.e. it has to remain zero. The current in the load inductor is constant, therefore this current must split between the two secondary windings so that the flux produced by one is cancelled by that produced by the other, thereby keeping mmf in the core zero – i.e. when the switch is opened i1 = 0, therefore the second term in the mmf expression must also be zero. This occurs if the other term is 12 N2 iL + (− 12 N2 iL ), which implies the above-mentioned splitting of the currents. The overall result of D1 and D2 being on simultaneously is that the secondary windings are short circuited. This value is mirrored to the primary, and its voltage will be zero (if D1 and D2 are ideal). It can be shown that the voltage ratio [2] for this converter is: N2 Vo =2 D Vd N1

(3.13)

where 0 < D < 0.5. Therefore, even though the range of the duty cycle is limited to 0.5, the output voltage can achieve values as if the duty cycle has a range from 0 to 1. Remark 3.7 One potential problem with the push-pull converter is that the switches are subject to maximum voltages of 2Vd . For low voltage applications this is of little consequence, but for mains line applications with 240VAC this means that the devices will be subject to minimum voltages of 700V. Therefore, 1000V MOSFETs are required to ensure that there is sufficient over voltage capacity. Remark 3.8 One of the potential problems with the push-pull circuit is that small differences in the timing of the duty cycles of the two switches can lead to offsets in the flux of the transformer. These timing differences can occur because of differences between the turn-on times of the transistors, or differences in the speeds of the firing circuits. Consider Figure 3.9 which shows a typical BH curve for a ferro-magnetic material. As the ideal push-pull circuit operates it normally moves from B1 to B2 via the hysteresis loop shown. If the “on” transistor is driving the flux density to B2 , and its on-time is a little less than the other transistor, then the flux density may not quite get to B2 , but instead only gets to B2a . Therefore, when the other device turns on it will drive the flux density to a value a little higher than B1 , B1a . This process will continue, and the maximum flux density B1a will creep up higher on the BH characteristic. If the process continues then the core will saturate at the higher flux densities and the magnetising inductance of the core will become very small and excessive currents will flow through the transistor that is on when this occurs. This often results in transistor failure. Current mode control is often used to fix this problem. MOSFET transistors also help, as they have a positive temperature coefficient, and as they heat up more of the voltage is dropped across the device, thereby robbing volt seconds from the magnetising inductance. The resistance of the primary also helps via a similar mechanism.

push-pull ratio

voltage

3-12

Switch Mode Power Supplies

B

Loop with flux imbalance Normal operation loop

B1a B1

H

B 2a B2

B1 = B 2

Figure 3.9: Flux imbalance in the push-pull circuit.

Practical issue 3.1 One very nice feature of the push-pull converter is that both of the transistors are referenced to the same ground rail. This simplifies the drive circuits for transistors as compared to other topologies where one has transistors floating at different voltage levels.

3.2.2

The Flyback Converter

The Flyback converter is an isolated converter that is derived from the buckboost converter described in Section 2.3.3 of the previous chapter. Figure 3.10 diagrammatically shows this connection. Recall from Section 2.3.3 that the important properties of the buck-boost were that when the switch is closed it performs similarly to a boost converter, with the input disconnected from the output and the current flowing through an inductor storing energy. When the switch is opened then the energy stored in the inductor is then transferred to the secondary winding, and in the process of doing this the energy storage inductor effectively becomes the filter inductor in the load section of the circuit. This inductor connects the input to the output when the switch is open. If we compare the buck-boost shown in Figure 3.10 with the Flyback converter, then we can see that the magnetising inductance of the transformer carries out the same function as the storage inductor in the traditional circuit. During the phase when the switch is closed current flows through the magnetising inductance. During the time the output circuit is disconnected from the input because the diode is reversed biased. When the switch is opened, the current through the magnetising inductance wishes to keep flowing in the same direction. It therefore produces a positive voltage on the non-dot end of the primary, resulting in a corresponding positive voltage on the non-dot end of the secondary. Consequently the diode in the secondary becomes forward biased,

3.2 Isolated Converter Topologies

3-13

and the magnetising current in the primary is reflected (via the turns ratio) in the secondary. This current flows into the output capacitor. In effect the magnetising inductance in the primary has been reflected into the secondary, and it performs the same function as the filter inductor in the classical buck converter circuit.

Vo N1 Vd

N2

Vo

Vd

SW

Flyback Converter

Buck-Boost Converter

Figure 3.10: Connection between the Buck-Boost and Flyback converter. Now let us consider the operation of the Flyback converter in more detail. Again we shall assume steady state operation, and the output voltage is considered constant. We shall look in some detail at the variation of the flux in the core, since it is the flux that stores the energy that is transferred to the load. One can calculate the flux in an inductor by using Faraday’s Law: N dφ dt Z 1 t ∴ φ(t) = vL (τ )dτ + φ(0) N 0 vL =

(3.14) (3.15)

In the case when the switch is closed, as shown in Figure 3.11, there is a constant voltage of Vd applied across the magnetising inductance, Lm . The secondary side of the circuit may as well not be there, since the diode in the secondary effectively disconnects the load from the primary. The load current Io is supported by the capacitor. It is therefore important that the capacitor be large enough to support the current and voltage appropriately during the switch “on” period. Equation (3.15) can therefore be written as: φ(t) = φ(0) +

Vd t N1

for 0 < t < ton

(3.16)

and clearly the peak flux in the magnetising inductance at the end of the “on” period is: Vd φˆ = φ(0) + ton (3.17) N1 At the end of the time ton the switch is opened. Because the current flowing in the magnetising inductance cannot change instantaneously, or alternatively

flyback peak flux

3-14

Switch Mode Power Supplies

Diode reverse biased iD = 0

im Lm

v1 N 1

N2

Io

RL

C

Vo

Vd

N2 N1

v1 =

N2 N1

Vd

SW

Figure 3.11: Flyback converter with the switch closed.

the total mmf in the transformer cannot change instantaneously, then a voltage is induced on the secondary (the polarity determined by the dot convention), in such a manner as to turn on the diode in the secondary. The circuit configuration then changes to that shown in Figure 3.12. As can be seen from the figure a voltage of Vo is produced across the sec1 ondary so that the diode turns on. The voltage N N2 Vo is produced across the primary, with a polarity that will cause the magnetising current to decrease. Another way to look at this is to realise that the secondary circuit is reflected to the primary by the transformer, and therefore the magnetising current can flow in this reflected circuit. During the “off” stage of operation, the flux in the transformer core will decrease from the peak value calculated in (3.17). Therefore the time evolution of the flux during this time is again given by applying Faraday’s Law:

φ(t) = φˆ −

N1 N2 V o

(t − ton ) N1 Vo ∴ φ(t) = φˆ − (t − ton ) for ton < t < Ts N2

flyback flux at Ts

(3.18) (3.19)

From (3.19) one can deduce, using (3.19) and (3.17), that the flux at the end of the control interval:

3.2 Isolated Converter Topologies

3-15

Diode forward biased iD

N1

im Lm

N 2 Vo

Io

C

RL

Vo

Vd

v1 =

N1 N2

Vo

SW open Figure 3.12: Flyback converter with the switch open. Vo φ(Ts ) = φˆ − (Ts − ton ) N2 Vd Vo = φ(0) + ton − (Ts − ton ) N1 N2

(3.20) (3.21)

We are again assuming that the system is in steady state, therefore the flux at the beginning and end of a control interval must be the same. This means that: φ(Ts ) = φ(0)

(3.22)

which, using (3.21) allows us the write: φ(0) +

Vd Vo ton − (Ts − ton ) = φ(0) N1 N2 Vo Vd ton = (Ts − ton ) ∴ N1 N2

Rearranging this, and using (2.2) we can write:   Vo N2 D = Vd N1 1 − D

(3.23) (3.24) flyback voltage ratio (3.25)

Remark 3.9 The voltage ratio in (3.25) is identical to the voltage ratio calculated for the buck-boost converter, as shown in (2.67). The currents flowing in the circuit under the switch “on” and “off” conditions are shown in Figure 3.13

3-16

Switch Mode Power Supplies

v1 Vd

0 -

N1 N2

t

Vo t off

t on f

Ts

f(0)

t iD

N1 N2

im Io

t Figure 3.13: The voltage, current and flux in the ideal Flyback Converter.

3.2 Isolated Converter Topologies

3-17

Let us calculate the currents flowing in the Flyback converter. This analysis basically follows the same procedure as the calculation of the magnetising flux. Assume that the current at the beginning of a control interval has an initial value of im (0). Therefore during the ton period the magnetising and switch current is: Vd t for 0 < t < ton (3.26) im (t) = im (0) + Lm As with the flux, the peak magnetising current at the end of the “on” period is: ˆim = im (0) + Vd ton Lm

peak magnetising and switch current

(3.27)

Remark 3.10 Note that ˆim is also the peak current flowing through the switch. During the “off” period the switch current is obviously zero. During this time the voltage across the magnetising inductance is of a polarity so that the current decreases. The current during this period is: im (t) = ˆim −

N1 N2 Vo

Lm

(t − ton )

(3.28)

The current in the diode during this period is simply a scaled version of the inductor current (by the transformer turns ratio). i.e.: " # N1 N1 N1 ˆ N2 Vo iD (t) = im (t) = im − (t − ton ) (3.29) N2 N2 Lm Using the equations that we have derived it is now possible to get the peak magnetising current in terms of the load current and voltage and the duty cycle. This is an important equation for this type of converter, since the peak magnetising current needs to be known so that saturation of the core can be avoided, and the switches can be sized. The first step is to work out the average expression for the diode current, which is also equal to the average load current (in steady state). Taking the average of (3.29) and rearranging we can get the expression for the peak current in terms of the average load current and the output voltage:   N1 V o N2 Io 1 ˆim = N2 + (1 − D)Ts (3.30) N1 (1 − D) 2 Lm The peak voltage across the switch can be seen to be the supply voltage plus the voltage produced by the transformer: vsw = Vd +

N1 Vo N2

(3.31)

which can be written, using (3.25), as: vsw =

Vd (1 − D)

(3.32)

flyback diode current

peak switch current

3-18

Switch Mode Power Supplies

3.2.3

Utilisation of Magnetics

One important factor in the performance of converters is the utilisation of the magnetic material. Converters such as the boost and flyback converter are storing energy in the magnetic field and then transferring this stored energy to the load when the switching device is turned off. A converter such as the forward converter is transferring energy via direct transformer action – the stored energy is a nuisance in that it has to be transferred somewhere when the power device is turned off. Despite this two different modes of operation, both these converter types are only magnetising the core in one direction. The full bridge converter, on the other hand, is really a variant of the forward converter, but it is different in that the core is magnetised on both directions during normal operation. This bidirectional magnetisation has implications on the utilisation of the core material. One of the main motivations for the use of SMPSs is their low weight and volume. Therefore it is essential that the magnetic material is well utilised to achieve these objectives. Consider Figure 3.14 which shows a typical BH curve for a magnetic material. The flux density Bm is the maximum flux density that can be achieved when the material is saturated. The flux density Br1 is the remnant flux density when the core is not being subject to an mmf. B Original magnetic material (no air gap) Bm

Br 1 Br 2

H Magnetic material with air gap

Figure 3.14: Typical BH loop for a magnetic material. Figure 3.15 shows the excitation waveforms for a forward converter with a feedback winding such that N1 = N3 (Figure 3.15(a)), and a full bridge converter (Figure 3.15(b)) with the same primary turns. The voltage v1 is the voltage across the primary winding. We shall assume that both converters are operating with D = 0.5. ∆Bmax is the excursion of the flux density from the average value of the flux density. Note 3.2 It should be noted that the use of a full bridge converter in this mode is entirely artificial. Under a duty cycle of 0.5 the average output voltage of this converter is zero. The output could be used to drive a transformer connected

3.2 Isolated Converter Topologies

3-19

to a rectifier to get a different output voltage. If a modulation strategy using zero voltage application is used then control of the DC output voltage could be obtained. The reason for the artificial D = 0.5 restriction is that this will force the flux in the core (under appropriate start up conditions) to be bidirectional. Remark 3.11 A better converter to use for this example is the push-pull converter. This converter can perform all the functions of the full bridge if a DC output is required, only involves two switches, and can be made to operate with symmetric bidirectional flux in the core of the transformer (with modified firing of the switches using a combination of current control and zero voltage application).

v1

v1

Vd

Vd

0

t t on

0

t t on

t off

-Vd

t off

-Vd

DB

DB

(DB )max

0

(DB )max

t Ts (=

0

t

1 ) fs Ts (=

(a)

1 ) fs

(b)

Figure 3.15: Core excitation waveforms. (a) forward converter. (b) full bridge converter. Let us consider the expression for the maximum deviation of the flux density away from the average value. We know from Faraday’s Law, (3.14), and the relationship φ = BAc , where Ac , the area of the core, that flux density can be written as: Z ton 1 B= v1 dτ + B(0) (3.33) N1 Ac 0

3-20

Switch Mode Power Supplies We are interested in the total change in B from whatever initial condition there is. We shall call this ∆B. This allows us to ignore the initial condition B(0) in the following evaluation.2 Assuming that D = 0.5 (which implies that ton = Ts /2), and v = Vd then we can write: Z T2s 1 Vd dτ ∆B = N1 Ac 0 Vd Vd Ts = = 2N1 Ac 2N1 Ac fs

(3.34) (3.35)

This value corresponds to the peak value of the flux in Figure 3.15(a). To evaluate the average value we calculate the area under the ∆B curve and divide by the time (since in Figure 3.15(a) the ∆B waveform is triangular). Therefore using (3.35) the expression for ∆Bave is:   ∆Bave = =

Vd 2N1 Ac fs

Ts 2

Ts Vd 4N1 Ac fs

for D = 0.5

(3.36) (3.37)

We can now find ∆Bmax , the maximum deviation of the flux from the average flux, by subtracting (3.37) from (3.35) to give: ∆Bmax = Maximum flux excursion.

Vd 4N1 Ac fs

for D = 0.5

(3.38)

which is valid for both converters. A little earlier we mentioned that we had ignored the initial value of the flux density, but in the footnote we noted that this would be important. Referring to Figure 3.14, one can see that when there is no excitation of the core that the remnant flux density is Br . Therefore this point on the BH characteristic is the starting point for any unidirectional flux excursion – i.e it is the initial condition B(0) in (3.33). Therefore, using the definitions in Figure 3.14 the forward converter flux excursion ∆Bmax becomes: ∆Bmax =

1 (Bm − Br ) 2

(3.39)

i.e. the flux excursion is limited by the remnant flux density in the core. Because the flux is starting off with the Br offset, then the flux cannot undergo large flux excursions. In the case of the full bridge converter, the flux undergoes symmetric flux density excursions about the zero flux density point in Figure 3.14.3 Therefore ∆Bmax is limited only by the saturation flux of the core – i.e.: ∆Bmax = Bm 2 Note

(3.40)

the the initial condition is very important when it comes to evaluating the magnetic utilisation, as we shall see. 3 This is achieved because of the switch drive circuits are designed to produce these flux excursions. Note that it is not intrinsic in the design of these converters that this would happen.

3.2 Isolated Converter Topologies

3-21

What are the implications of these differences in the maximum flux density that can be achieved with these converters? These can be gleaned by considering (3.38) in the light of the above comments. Rearranging (3.38) we get: Ac =

Vd 4N1 (∆B)max fs

(3.41)

We can see from this expression that if ∆Bmax is large then Ac can be smaller. Therefore, given the same applied voltages, duty cycle and switching frequency, and for the same number of turns on the primary, the full bridge converter will have a significantly smaller core for the magnetics as compared to the forward converter. Remark 3.12 Equation (3.41) assumes that fs is the same and N1 is the same under the condition of smaller core cross-sectional area. However, as can be seen from (4.23) in the following chapter, reproduced here for convenience: L=

µN12 Ac lc

(3.42)

where lc is the magnetic path length of the core, the inductance of the core is much less. This should also be obvious from the definition of inductance: L=

λ N1 BAc = i i

(3.43)

If Ac is smaller, then for the same current i the B will be the same (via Amperes Law), and therefore λ will be smaller. Therefore implicit in (3.41) is the fact that the current is allowed to increase when we have the smaller core area, since the same voltage is applied by the converter across the winding for the same time, but the inductance is less. Remark 3.13 As can be gleaned from Remark 3.12 there is a trade-off for the reduced size magnetics under the condition specified – for the same power output we have a larger magnetising current, therefore higher losses, and larger switching devices. Remark 3.14 The fact that one does not have to demagnetise the core in the push-pull converter means, without considering the maximum flux density issue, one can produce more power from the same magnetic core. The effective maximum duty cycle is 1, whereas for the forward converter it is 0.5 (depending on the relative turns ratio of the ternary winding). Remark 3.15 In general a bidirectional flux density change type of converter uses the magnetic material more effectively than a unidirectional flux density converter. Remark 3.16 One can see from (3.39) that the maximum excursion of the flux in the forward converter is limited by the remnant flux in the core. Therefore one way to utilise the magnetics better in these types of converters is to reduce the remanence. This can be achieved by putting an air gap in the core. This to a large degree linearises the core operation, and also dramatically lowers the remnant flux density. This effect is shown diagrammatically by the dashed BH characteristic in Figure 3.14.

3-22

Switch Mode Power Supplies Under the condition of identical duty cycle, identical turns in the primary winding and identical core area (i.e. the magnetising inductance of both cores is the same), then flux in the cores is: Forward converter: Bmax = Bave + ∆Bmax + Br

(3.44)

(2∆Bmax )Ts 2Ts = 2∆Bmax + Br

Bave = ∴ Bmax

(3.45) (3.46)

For the push-pull converter, assuming appropriate control (i.e. current control), then: Bave = 0

(3.47)

∴ Bmax = 0 + ∆Bmax = ∆Bmax

(3.48)

Therefore the push-pull converter has less than half the peak flux density in the core. This would means that the core losses in this converter would be lower than those of the forward converter (see below on core losses). The other issue that can limit the utilisation of magnetic cores in switching power supplies are core losses. The general expression for the core loss per unit volume or weight is of the form: b

Core Loss density = kfsa [(∆B)max ]

(3.49)

where the k, a, and b are determined from the particular material. One can see from this expression that the core losses are a complex function of frequency of switching and the maximum flux density excursion. If, for example, the switching frequency is increased, then the maximum flux density becomes less, with everything else the same. Therefore, depending on the specific values of a and b, the overall losses will be smaller. Also the total core volume will be smaller, since the maximum flux density is less. On the other hand, the switching losses in the active devices will increase with increased frequency. One can see that the optimisation of the core losses must be carried out for each specific device.

3.3

Introduction to Control Techniques for Switching Power Supplies

Now that we have looked in detail at several idealised converter topologies suitable for switching power supplies, we shall now look at overall topological and control issues. Due to the varying background of the students doing this subject we shall not delve deeply into the control issues, but instead, an overview of the concepts involved will be presented. There are many references on issues related to the control of switching supplies, both in books and in several of the IEEE Transactions, namely Power Electronics, Industrial Electronics, and Industry Applications. Some of the books on these issues are [2, 5, 4]. Before looking at the control issues, we shall consider some broader topological and practical issues of switching supplies. Consider Figure 3.16 which is a block diagram of a typical switching power supply (from [2]).

3.3 Introduction to Control Techniques for Switching Power Supplies

3-23

Isolation barrier DC-DC power convertion Rectifier and filter

Mains Supply AC

EMI filter

HF Power Transformer

Switches

Rectifier and filter Vo

DC

HF Signal Transformer PWM Controller

Base and gate drive circuitry Small Mains Transformer

Error Amplifier DC

Rectifier and filter Feedback circuitry

Vo -ref

Figure 3.16: Block diagram of a typical switch mode power supply.

As can be seen from Figure 3.16 we have looked at the detail of the dc-dc conversion section of the power supply in the first part of this chapter. The lower half of the diagram is related to sensing of the feedback signals and the control circuitry. The important point to note here is that the feedback signals have to be isolated from the input if we are to have an isolated power supply. This complicates the design of the supply considerably. The circuit of Figure 3.16 is a conceptual diagram of one way of designing the isolated feedback. In this configuration the control circuitry and PWM generation is on the output side of the isolation. The other alternative is to have this circuity on the supply side of the isolation, and only the output voltage is feedback in an isolated fashion. The relative merits of the control circuitry on the supply side and the output side are not clear cut. Having the control circuitry on the output side (as in Figure 3.16) has the advantage that one is transmitting pulsed signals (basically firing pulses) across the isolation. This would also allow one to use an optocoupler instead of a signal transformer. On the negative side the base drive circuitry is a little more complicated. If the PWM and control circuitry is on the supply side then the base drive circuitry is usually a little simpler compared to the output side circuitry. On the negative side, getting the output voltage and/or current in an isolated fashion can be difficult. One technique is to use a voltage-to-frequency converter on the output side, and a frequency-to-voltage converter on the supply side. Some power supplies attempt to use opto-couplers in a linear mode of operation. However, opto-couplers are an inherently non-linear device, and this is difficult to do. To complicate the issue even further they are subject to temperature

feedback isolation

3-24

Switch Mode Power Supplies variations. One rather nice and simple technique of getting isolated feedback variables with the control on the supply side is the circuit shown in Figure 3.17 which was proposed in [5]. This circuit uses a small forward converter to transfer the analogue voltage value of the output voltage across the isolation barrier. The BJT is connected to the output of the main power converter, and is turned off and on by the pulsating voltage here. This then operates a low power forward converter that transfers the main converter output voltage via the transformer to main converter primary reference. The small transformer would have a turns ratio so that the output voltage is higher than the main converter output voltage. By doing this any voltage drop across the rectifying Schottky diode is insignificant. One crucial aspect of the performance of this circuit is that the duty cycle of the main converter (which is used to control the small feedback forward converter) does not affect the output voltage. This is achieved because the output circuit is a peak detector, and the precise duty cycle does not affect the peak detected. The peak is related to the output voltage of the main converter. The forward feedback converter output voltage is then resistive divided to give a voltage that is appropriate for the error amplifier. It is claimed that this circuit is capable of giving an accuracy of 2% and has a bandwidth that is controlled by the RC time constant of the capacitor/resistive divider network at the output of the feedback circuit.

Isolation barrier

Main converter output Vo

P

S

R1

S

R2

v feedback

P

P

S Feedback circuitry Forward converter

Figure 3.17: Feedback circuit using a small forward converter.

3.3 Introduction to Control Techniques for Switching Power Supplies

3.3.1

3-25

Start-Up

Another interesting practical aspect of a SMPS is how to start it up. The dilemma takes the form of a chicken or egg argument – one needs power to start the switching, and one needs switching to get power. The solution to this problem could take the form of that shown in Figure 3.16, where we have a separate power transformer for the control logic. Power is therefore immediately available for the PWM and feedback circuitry when the main power is applied. However, in many situations this would be considered to be an expensive solution. Another much lower cost solution is to use a control logic power winding, a resistor and a capacitor [5]. This is suitable for converters where the control logic is referenced to the primary. A circuit for this is shown in Figure 3.18. Initially the transformer section of the circuit is inoperative. When power is applied to the power supply the unregulated DC supply comes on-line. Consequently the electrolytic capacitor in Figure 3.18 will charge up. The zener diode is to limit the voltage to a value safe for the PWM generator IC. The PWM generator now has enough voltage to operate. Unfortunately many PWM generator ICs only have a small hysteresis band of operation around the nominal voltage of operation. For example, the UC3825 PWM generator IC by Unitroder Semiconductor Products (now owned by Texas Instrumentsr ) operates with voltages from 9 Volts to a maximum of 30 Volts. There is a 400mV hysteresis around the 9 Volt minimum voltage. Therefore, once the circuit starts operating (at 9 Volts) then it will continue to operate until the voltage falls to (9 - 0.4) Volts. This implies that the capacitor voltage in Figure 3.18 cannot fall by the 0.4 Volt hysteresis value during the time that the main power circuit starts to supply power to the PWM generator. If the voltage does fall by this amount then the PWM generator will stop working, and the resistive charging process will cause the cycle to repeat. The circuit will therefore operate in a type of limit cycle. In order to make the onset of limit cycle behaviour less likely during startup of the power supply, one needs to create a larger hysteresis in the operating supply of the PWM IC. The PWM IC is designed limited to a certain hysteresis, so the increased range must be obtained by circuitry external to the chip. Figure 3.19 shows one way of achieving this [5]. This circuit effectively allows the capacitor to charge up to a higher voltage before the PWM IC is allowed to operate. The capacitor charges up as described for Figure 3.18. When the voltage on the capacitor reaches a value equal to the value of the breakdown voltage of zener Z2 plus the threshold voltage of the MOSFET, then the MOSFET will turn on. This then allows the PNP transistor to turn on and voltage is applied to the PWM IC, which begins to operate. The resistor RG feeds back voltage to the gate of the MOSFET so that it will remain on, even if the voltage across zener Z2 drops below its threshold voltage. The feedback will remain active while the voltage on the gate of the MOSFET remains above the threshold voltage. As a specific example of the operation of this circuit, consider zener Z2 to be 12 Volt and the gate threshold of the MOSFET to be 2 Volt. Therefore when the voltage on the capacitor reaches approximately 14 Volt, zener both Z2 and the MOSFET will be on. Consequently the PNP will turn on, and the 14 Volt on the capacitor will appear on the Vcc pin of the PWM IC. The capacitor

improved power start-up circuit

3-26

Switch Mode Power Supplies

Initial charging resistor

Unregulated DC supply

Vcc

+

PWM Generator Chip

Power winding when running Figure 3.18: Example of a simple bootstrap power circuit for a PWM generator chip.

3.3 Introduction to Control Techniques for Switching Power Supplies

Initial charging resistor

Unregulated DC supply Hysteresis circuit

Vcc

+

Z1

Power winding when running

RB

Z2

RG

RG

1

PWM Generator Chip

2

Figure 3.19: Bootstrap circuitry modified for increased hysteresis range. will then begin to discharge. The PWM IC will continue to operate until the capacitor voltage falls below its minimum operating voltage, which in the case of a UC3825 is 9 Volt. Therefore, the circuit has created a voltage hysteresis for 14 − 9 = 5 Volt. Remark 3.17 The increased hysteresis created by the circuit shown on Figure 3.19 means that the capacitor can be a smaller size and still be able to keep the PWM IC running long enough to allow the auxiliary winding to start to supply the power to the PWM IC. Remark 3.18 The charging resistor shown in Figures 3.18 and 3.19 is constantly connected on the circuit. Therefore, even when the switch mode supply is running, it will still dissipate power. However, this resistor can be made quite large so that the power dissipated can be made small – the charging time of the capacitor is not that important (within reason). The resistor is no longer really supplying the current in the turn on phase, as it was with the previous circuit. Alternatively one can use auxiliary circuitry to switch the resistor out, thereby allowing a smaller resistor to be used.

3.3.2

Protection Issues

3.3.2.1

Soft Start

Soft starting refers to generating voltage output very slowly when power is first applied. This is required because when power is first applied the control

3-27

3-28

Switch Mode Power Supplies circuitry will apply the maximum duty cycle to the power stage. This can result in excessive current flow in the components which can be potentially destructive. In order to prevent this a special mode of operation is required so that the duty cycle ramps up from a very small value to the value required by the control circuitry. Soft starting is also used to recover a SMPS from fault conditions. Soft starting is handled internally in most PWM ICs, therefore it does not require any specific action by a designer. 3.3.2.2

Voltage Protection

Most SMPS integrated control circuits have a pin which can be connected to an external circuit. This circuit will generate a voltage into the pin of the IC when the input voltage rises above a certain value. Most ICs also contain circuitry that detects under voltage conditions. Internally the shutdown circuitry usually stops the internal latch from functioning and sets the outputs into a non-driving state. A block diagram of the Unitroder 1825 switch mode PWM generator chip is shown in Figure 3.20. Notice that the “Output Inhibit” is activated for low voltage to the chip itself, as well as from the Ilim/SD input (i.e. pin 9). The later is activated by external circuitry to detect over voltage/under voltage to the power circuit. BLOCK DIAGRAM

U DG-92030-2

3/97

Figure 3.20: Block diagram of the Unitroder high speed PWM generator.

3.3.2.3

Current Limiting

Current limiting is included in most PWM control ICs to protect the power supply under short circuit conditions. There are two types of current limiting: • Constant current limiting.

3.3 Introduction to Control Techniques for Switching Power Supplies

3-29

• Fold-back current limiting. Constant current limiting, as the name implies, is a form of current limit where the current can only go to a particular value and then it will not increase any more, regardless of the load. Therefore, even under short circuit conditions the current will not increase appreciably above this limit value. This concept is shown in a V0 I0 diagram in Figure 3.21. One point to note about this diagram is that the voltage at the output of the converter can be appreciable under this condition, depending on the impedance of the load.

constant limit

current

fold-back limit

current

Remark 3.19 The constant current limit may not be satisfactory in many applications, since the limit current may, over time, result in the thermal rating of the inductor or transformer windings being exceeded. Therefore, if such a limit is to be used, then one must ensure that the windings and power devices can support the limit current indefinitely.

Vo

Load lines Vo, rated

RL = R1

Vo1 RL = R2

Vo2

I o, rated

I limit

Io

Figure 3.21: Operation of a constant current limit.

A slightly different limit is the fold-back current limit. This limit is motivated by the desire of reducing the currents flowing in abnormal short circuit or near short circuit conditions. The operation of this current limit philosophy is shown in Figure 3.22. In this case when the current reaches a limit value of Io, limit then the current limit drops with the output voltage. Therefore under short circuit conditions the current is reduced to a much lower value than in the previous case. The power that is being supplied to the external circuit under this condition is not nearly as high as in the constant current limit situation. Remark 3.20 The fold-back current limit does not solve the overheating problem mentioned in the previous remark. If the circuit is operating at Io, limit then the problem is the same as in the constant current limit case.

3-30

Switch Mode Power Supplies

Vo

Load lines Vo, rated

RL = R1 RL = R2 Vo1 Vo2 I o, foldback

I o,rated

I o,limit

Io

Figure 3.22: Operation of a fold-back current limit. Most PWM ICs implement a two stage current limit. The current through the switch is fed through a sense resistor, and the fed into the current limit pin of the PWM IC. If the voltage on this pin reaches a certain value the switch turn on pulse is turned off until the next control cycle. Therefore the current limiting is carried out on a switching interval basis. If the voltage goes higher and reaches a second limit, then the controller stops switching and restarts in soft start mode. The power supply can then oscillate in this mode until the short or the fault is rectified. Current limiting is actually a little more complicated than has been made out so far. Consider the situation when one has a converter with a transformer and multiple output windings. If the current sensing is set up on the primary, then the current limit has to be set for the current pulled under full load from all the windings. However, if all the secondaries, except one, are unloaded, then if there is a short on this winding the full current of the inverter can go through this winding before there is a trip. This situation could result in the destruction of this winding, or destruction of the rectifier components on this winding. There is no easy way out of this problem. Probably the most economical solution is to sense the current limit of each winding individually, and then take the output of these limit circuits and “OR” them together. This forms the trip signal to the PWM chip.

3.3.3

Control Architecture of a Switch Mode Power Supply System

3.3.3.1

Voltage Mode Control

Figure 3.23 shows a conceptual diagram of a SMPS system from a control perspective (as opposed to an implementation perspective). The compensating

3.3 Introduction to Control Techniques for Switching Power Supplies

3-31

amplifier is shown with generic feedback components Z1 and Z2 . These components can contain reactive circuit elements, which allow a variety of different transfer functions to be set up in the feedback loop. Compensating amplifier Zf

Vd

Zi

+

vc

PWM Controller

d

Power stage and output filter

vo

Vo,ref

Figure 3.23: Conceptual diagram of a control system for a switch mode power supply. In general the main objective of the control system of Figure 3.23 is to control the output voltage to be a specific value under varying load conditions. In order to design the feedback compensation, one needs to obtain a model of the system suitable for control analysis. This is achieved by using an approach called state space averaging. This allows one to obtain a state space model of the system, accounting for the switching in the circuit in an average sense [2]. We shall not look at the detail of the process. The net result of this modeling process is that one can obtain a small signal linearised model of the converter and its control of the form shown in Figure 3.24. This figure shows each of the converter components as a transfer function. In this form one can apply standard classical control system design techniques to the system. Whilst switching power supplies seem to be very simple circuits, their operation from a control viewpoint is more complex than one might initially expect. Consider, for example, the flyback and boost converter. Because these two converters store energy in the magnetic field of an inductor before transferring it to the load they exhibit an effect caused by having a right half plane zero in their transfer function. Such systems are known as non-minimum phase systems. For the non-control literate reader, a right half plane pole corresponds to a response that tends to go in the wrong direction to correct a disturbance. Consider the following example of a right half plane zero effect. If we have a flyback converter, and there is a sudden decrease in the output voltage due to an increased output load on the converter. The natural reaction of the control system is to increase the duty cycle, D, so that more energy is transferred to the load to restore the voltage. However, due to the above-mentioned energy storage operation principle of this converter, the initial increase in the duty cycle can result in a further decrease in the output voltage. This is due to the

non-minimum phase

3-32

Switch Mode Power Supplies v~ (s ) T1 (s ) ? ~o vc (s ) ~ d (s ) Tm (s ) ? ~ vc (s ) v~o,ref (s )+

-

S

v~err (s ) Compensating

v~c (s )

error amplifier

PWM controller

v~ (s ) Tp (s ) ? ~o d (s ) ~ d (s )

v~o (s )

Power stage and output filter

Figure 3.24: Linearised model of a switch mode power supply. fact that increasing D instantaneously delays the next delivery of energy from the magnetic field to the load, as compared to what would have happened if there had been no change in D. One can see that if the feedback is very high bandwidth then this will result in a further increase in D, and the process will repeat. We effectively have positive feedback. Of course the process will stop when we get to the limit of the duty cycle (this is a non-linear effect that is not accounted for in our linear explanation). The presence of a right half plane zero in these converters limits the control bandwidth of these types of converters. Figure 3.23 shows a basic diagram for a switch mode control system. Many real systems actually use a hierarchical control system consisting of two nested control loops. The inner most of the control loops is a current control loop, and the outer control loop is the traditional voltage control loop. The advantages of using the current control loop will be discussed in detail in a following section. Suffice to say that the disturbance rejection properties of the controller are improved using this structure. A block diagram of this hierarchical control system appears in Figure 3.25. Notice that the voltage vc appears as a current reference to the section of the circuit that controls the current. Switching signal H (s ) G(s )

vo,ref

+

S -

vo,err

Voltage loop feedback compensator

vc

Comparator and latch

Power stages and output filters

vo

iL

iL

vo

Figure 3.25: Block diagram of a nested loop control system for a switch mode power supply.

3.3 Introduction to Control Techniques for Switching Power Supplies 3.3.3.2

Voltage Feed-forward PWM Control

All of the diagrams for control of the SMPSs thus-far have relied totally on feedback control. However, in the case of input voltage fluctuations one can feedforward the change of input voltage to the controller so that it can be accounted for before it would affect the output. This is usually achieve in practice by feeding the input voltage into the PWM IC. This chip usually accounts for the supply variation by altering the amplitude of the triangular waveform that is used internally to generate the PWM. One can see from (2.7) that if vst is increased (corresponding to an increase in the peak of the triangular waveform) then the duty cycle decreases. Therefore if this value is controlled by the input voltage then it is possible to get near perfect input disturbance rejection. 3.3.3.3

3-33

Current Mode Control

Current mode control is a term used in the SMPSs literature to refer to a nested loop control system, such as that depicted in Figure 3.25, where the inner loop controls the inductor current, and the outer loop controls the output capacitor voltage. There are a number of very good reasons for complicating the control structure of the addition of the current control loop: • Switch current limiting. It was mentioned in Section 3.2.1.1.2 that one of the problems with the push-pull converter was that small differences in the switching times of the switching devices could cause eventual saturation of the transformer. Employing current mode control the peak switching currents in the two switches of such converters can be balanced so that this phenomena does not occur. Note that the current mode control in this situation would be from each of the two switches. • Simplified converter dynamics. Current control effectively removes the pole introduced by the output inductor. This simplifies the dynamics of the converter system, effectively allowing the bandwidth of the control loop to be increased (because of the increased gain and phase margin achieved). This is especially useful in converters that have a right half plane zero in their response. • Simplified paralleling of converters. The presence of the current control loop allows the possibility of paralleling of several SMPSs, with each power supply contributing the same amount of current to the load. This is achieved by feeding each of the supplies with the same control voltage. • Automatic voltage feed-forward. The desirable properties of voltage feedforward are implicitly achieved when current mode control. If the input voltage increases, the current will reach the current limit sooner. Therefore the duty cycle will decrease with out the delay of waiting for the voltage to vary at the output. In a current mode controlled SMPS, as depicted in Figure 3.25, the control voltage vc , which is derived from the error between the desired output voltage and the actual output voltage, represents a desired inductor output current, or a switch current. This is achieved in a number of different ways [2]:

input disturbance rejection

3-34

Switch Mode Power Supplies a. Tolerance band control. b. Constant “off” time control. c. Constant frequency control with turn-on at clock time.

tolerance band control

Let us look at how each of these schemes works in a little more detail. In tolerance band control the inductor current is kept within a band, and the control voltage is effectively controlling the average value of the current. The width of the band is a design parameter, and by choosing it the designer is also influencing the switching frequency of the converter (which is also related to other parameters of the converter). Tolerance band control is essentially a classical hysteresis or bang bang type of control strategy. The operation of tolerance band control is depicted in Figure 3.26. The ∆iL value is one of the design parameters for the controller. If ∆iL is very small then, for the same converter parameters, the frequency of switching will be much larger. The other important point to note is that the switching frequency is related to the voltage appearing across the inductor (which changes the slope of the currents). Therefore if the input voltage increases, then so will the switching frequency. This is not a desirable property – it makes the losses of the switch difficult to predict.

vc

iL

Di L / 2

Di L / 2

IL

t t on

Switch turns on

t off

Switch Switch turns turns off on

Figure 3.26: Waveforms for tolerance band current control. Another problem with the tolerance band controller is that it only really works properly in continuous mode operation. If the current becomes discontinuous, then the desired average inductor current can become negative. If the current is discontinuous then the lower switch on limit would have to be zero – the circuit has to be designed to handle this. If the controller is not specially designed, the controller will respond to driving the inductor current to zero, and it will then stay there. There is also a problem of very high switching frequencies at low current values, this corresponding to a very small hysteresis band.

3.3 Introduction to Control Techniques for Switching Power Supplies Constant “off” time control controls the peak current in the inductor. In this strategy the control voltage specifies the maximum or peak current. When this peak current is reached the switch is opened for a fixed period of time. It is then closed again and the process repeats. This situation is depicted in Figure 3.27. This control strategy also suffers from the problem that the switching frequency is dependent on the input voltage and the converter parameters.

3-35

constant “off ” time control

vc

iL

I$L

t t on

Switch turns on

t on t off Switch turns off Switch turns on

t off

Constant t off

Figure 3.27: Waveforms for constant “off” time control. The constant-frequency with turn-on at clock time control is the control strategy most commonly used. This is due to the fact that the switching frequency is user definable in the strategy. One is effectively trading off the ripple control achievable with tolerance band control for the constant switching frequency. This allows one to control more accurately the losses in the switching devices, and makes the design of the output filter much simpler. Figure 3.28 shows the waveforms that occur with this control. The switch is closed at a time determined by a clock signal. The switch remains on until the current limit is reached, and then it turns off until the beginning of the next control period. The process then repeats. The fact that the switch only turns on at the beginning of a clock pulse means that the frequency is fixed by the clock period (which of course is user definable). There is a problem with straight current mode control that we have not mentioned in the discussion thus-far. If the converter duty cycle exceeds 50% the converter output will possibly oscillate at a subharmonic of the switching frequency – specifically at half the switching frequency. This occurs because the current control loop works by turning off a switch when the current reaches

constant frequency with turn-on clock time control

subharmonics

3-36

Switch Mode Power Supplies

vc

iL

I$L

t t on

t on t off

Ts

Clock

t off

Ts

Clock

Clock

Constant period between clock pulses Figure 3.28: Waveforms for constant frequency with turn-on at clock time control.

3.3 Introduction to Control Techniques for Switching Power Supplies a particular value. It is possible if the duty cycle is larger than 50% that the current will not return to the value at the beginning of the control interval. Therefore in the next control interval the current will reach the desired value sooner (since it is starting off with an offset). Therefore the switch will turn off sooner than it otherwise would, and consequently the “off” time will be longer. Therefore at the end of this interval the current may be lower than the desired value. This would result in the control deciding to turn the switch on longer, since we are now starting from a negative offset compared with the correct value if this phenomena were not occurring. One can see that the period of the oscillation caused by this jitter in the duty cycle results in a frequency that is half the switching frequency. In addition to the subharmonic oscillation problem, one also has a form of open loop instability with current mode control [6]. The following discussion is with reference to Figures 3.29(a), (b) and (c). Consider Figure 3.29(a) shows the effect of a perturbation of the inductor current (dashed line) away from the nominal current (the solid line). Notice that the perturbation dies away in this case. The effective duty cycle changes due to the way that current mode control works. Figure 3.29(b) shows a similar situation, but in this case the duty cycle is larger than 0.5. One can see that instead of the error between the nominal inductor current and the perturbed version getting less, it actually increases with each successive control interval. Therefore, there is effectively positive feedback in this case.

3.3.3.3.1 Slope Compensation Many of the problems with current mode control can be overcome by using the technique called slope compensation. This technique involves adding a sawtooth waveform to the current feedback waveform, or alternatively subtracting a sawtooth from the voltage error signal fed to the current mode controller comparator. Figure 3.29 shows the effect of slope compensation. In this case the sawtooth waveform is subtracted from the error voltage, Ve coming from the voltage error amplifier. This effectively forms a new reference for the current control section of the loop. In this case, even though the duty cycle is larger than 0.5 the perturbed current returns to the nominal current (as was the case for D < 0.5). The added ramp has a constant value, and therefore the sensitivity of the feedback to variations in the current measurement becomes less. To understand how this works one can look at the extreme case when the current in the load is very low and the ramp is added to the current measurement. In this situation the control voltage from the error amplifier is being compared to the slope compensation voltage, and hence the circuit is essentially operating in the normal triangular wave comparison mode of voltage control. Therefore, the addition of the slope compensation brings in some features of voltage control into the current mode loop, and under the situation of low currents it effectively behaves as voltage control (and therefore would have the dynamics of voltage control). Let us consider this situation in a little more detail. One can see from Figure 3.30 that the current perturbation error at the beginning of a control interval, ∆i0 , is related to the current perturbation error at the end of the next

3-37

open loop instability

3-38

Switch Mode Power Supplies

iL

Ve

m2 m1 Di 0

Di L

t (a) Duty cycle < 0.5

D

Ve

m1

m2

Di 0

Di L

t (b) Duty cycle > 0.5

D

Compensated voltage reference Ve

-m

m1

m2

Di 0

t D

(c) Duty cycle > 0.5, slope compensation

Figure 3.29: Open loop instability of current mode control. (a) stability with duty cycle < 0.5; (b) instability with duty cycle > 0.5; (c) stability with duty cycle > 0.5 and slope compensation.

3.3 Introduction to Control Techniques for Switching Power Supplies control interval, ∆i1 , as follows:  ∆i1 = −∆i0

m2 m1

 (3.50)

Remark 3.21 Equation (3.50) shows that if |m2 | > |m1 | then |∆i1 | > |∆i0 | – i.e. the error has increased after one control interval. This situation would continue. This situation correlates to D > 0.5, since for the circuit to be in steady state, i at the beginning of the interval, must be equal to the value at the end. This implies that |m2 | > |m1 |. Therefore the two conditions are synonymous.

m2 m1

Di 0

Di1

t

x=

Di 0 m1

x=

-Di1 m2

Figure 3.30: Geometrical relationship of the current waveform slopes when there is a current perturbation. As mentioned above the compensation can be carried out by adding the slope compensation waveform to the current, or subtracting from the voltage. The techniques can be shown to be equivalent. Therefore, assuming that we are adding to the current we can modify (3.50) by adding the slope compensation to give:   m2 + m ∆i1 = −∆i0 (3.51) m1 + m If the duty cycle is near 100% then the slope m1 ≈ 0. Furthermore, we wish that ∆i1 < ∆i0 for the error to be decreasing over successive control intervals. Using these facts we can write the following:   m2 + m −∆i0 < ∆i0 (3.52) m1 + m   m2 + m ∴− − m2 (3.54) 2

3-39

3-40

Switch Mode Power Supplies Remark 3.22 Equation 3.54 shows that the slope of the ramp that must be added to the current or subtracted from the voltage error must be greater than half the magnitude of the down slope of the inductor current. If one considers (3.51), and consider it to be a discrete iterative expression, then the inductor current behaves as though it is an underdamped RLC circuit. This is shown in Figure 3.31. This RLC response can be damped out (akin to critical damping) by choosing m = −m2 . The effect of this is shown graphically in Figure 3.32.

Din = -Di(n -1)

Fm GH m

2 1

I + m JK +m

t

1T

2T

3T

4T

5T

Figure 3.31: Inductor current response of current mode converter.

Ve

-m = m 2

m2

Dio

m1

t

Figure 3.32: Optimal slope compensation to eliminate RLC type oscillations.

Chapter 4

Introduction to Practical Design of Switch Mode Power Supplies 4.1

Introduction

In this chapter we shall briefly look at the most important aspects of the physical component design of a switch mode power supply (SMPS). The approach taken is a very practical one, with some theory where appropriate. The design of a switch mode power supply, like most electronics design, is complicated because of the large number of design trade-offs that are available. This fact means that this presentation is far from exhaustive, nevertheless the salient issues in making design choices will be emphasised. The design of SMPSs is complicated even further by the fact that virtually all SMPS’s use magnetics in their design. Consequently much of this chapter will be concerned with the design of these magnetics. The first section of this chapter will consider issues related to the selection of the electronic components of a SMPS. The second section of the chapter will look in some detail at the design of SMPS magnetics. Much of the material in this chapter is closely based on [5].

4.2

Component Selection

The information on the selection of components for SMPSs is usually material that ends up in vendor’s application notes (if one is lucky), or in the mind of a designer. This information therefore is often very inaccessible to a new designer, and is often attained by many disappointing design exercises. In this section we shall attempt to highlight some of these hard-to-find selection criteria for a variety of components: resistors, capacitors, Schottky diodes, rectifier diodes, BJTs, MOSFETs, op amps, and comparators.

4-2

Introduction to Practical Design of Switch Mode Power Supplies

4.2.1

Resistors

The resistor is probably the most ubiquitous of all electronic components. Consequently most electronic designers don’t pay a lot of attention to details other than its value and power rating. 4.2.1.1

Values

There is a practical maximum value for a resistor that is used on a PCB. This practical limit occurs for several reasons: • Large resistor values are not commonly available (although they can be obtained for specialised applications). • If a very large value of resistor is used, then the resistance across the PCB between the resistor legs may be comparable or less than the resistor value. Therefore the resistor is ineffective. • Using large resistor values makes the circuit very susceptible to electrical noise. A large value of resistance means that very small capacitively coupled currents can result in large coupled voltages. Remark 4.1 Don’t use large values of resistance in your designs if at all possible. Even values of 220kΩ can cause significant noise pickup problems, especially in switching applications which are inherently noisy in any case. 4.2.1.2 carbon composite

metal film

wire wound

Resistor Types

Obviously choosing the correct resistor for the job is necessary in electronics design. There are several resistor choices, depending on the application. The oldest style of common resistor is the carbon composite resistor. One can usually tell these resistors by the large size for their power rating. One may still find these resistors in a hobbyist store, but for professional circuit design they are no longer used, as there are much smaller, lower cost, and more reliable resistors available.Another interesting point about carbon resistors is that the preferred values made were far fewer than the more modern resistors (only 12 per decade). The most commonly used resistor today is the metal film resistor. These are available in a wide range of values, and low to moderate power ratings (several watts).As noted in the previous paragraph, there are a lot more preferred values in these resistors (48 to 96 values per decade, depending on tolerance). For higher power rating applications there are several choices. The wire wound resistor is the one that most people would be familiar with (a heating radiator element is an extreme form of this type of resistor). They are generally available in power ratings from 1W to approximately 1kW (and sometimes larger values for special applications such as regeneration banks in large inverter systems). One problem with wire wound resistors is that they have high inductance, which makes a conventional wire wound resistor unsuitable for high frequency applications. Fortunately, it is possible to wind the resistor with equal turns in two different winding directions so that the inductance can almost be eliminated (the flux produced from each winding direction cancels). Variable

4.2 Component Selection

shunt

4-3

resistance wire wound resistors are called Rheostats. These are most commonly used in laboratories for experiments, rather than in commercial products. Another common type of resistor used for current sensing applications is the current shunt. This resistor type usually has a very low, but precisely known value. One can detect the voltage across the resistor, and then use Ohm’s Law to deduce the current through the shunt. The shunt itself is made of metals that have a very low temperature coefficient. A low cost shunt can be created using a PCB track itself. This should only be considered where cost is the primary consideration, since the accuracy of such a shunt is not very good. It should be noted that shunts provide a non-isolated measurement of current. In many applications this is all right, but in other applications where isolation is important then additional measures must be used to gain isolation of the measurement. Table 4.1 summarises these comments.

Type

Suggested Applications

Carbon composite Metal film Wire wound (inductive) and rheostat Wire wound (non-inductive) Shunt PCB track

Not commonly used anymore General purpose – replace carbon Used for high power load resistors Used in high frequency applications Used for measuring large currents Used for low cost measurement of currents

Table 4.1: Resistor application selection guide

4.2.1.3

Tolerance

One important attribute of a resistor is its accuracy. Many years ago the “garden variety” resistor had a tolerance of 5%, and the exotic resistors had a tolerance of 1%. These days the default tolerance of resistors is 1%, and at slightly higher price one can have resistors with 0.1% tolerance. 4.2.1.4

Selecting Values

In many designs the specific value of a resistor does not matter (although in some it does as well). If this is the case then only the ratio between resistors is important. Therefore, in order to minimise the number of components that need to be ordered it is better to try an choose the same values of resistor where possible. For example, if sections of the circuit rely on resistor ratios, then choose one resistor out of the two to be say, 10kΩ. One can then choose the other to satisfy the ratio requirement. 4.2.1.5

Maximum Voltage

Voltage ratings are not a parameter that immediately comes to mind when thinking of resistors. However, in the case of surface mount resistors, the spacing between the ends of the resistor means that voltage rating must be considered. In SMPS circuits one can be dealing with voltages anywhere from 10s of volts

4-4

Introduction to Practical Design of Switch Mode Power Supplies to 100s of volts, and at the top end of this range resistor voltage rating can be important. 4.2.1.6

Temperature Coefficient

Most modern metal film resistors have a very small temperature coefficient of the order of 50–250ppm/◦ C. Wire wound resistors however, depending on the material they are made from, can exhibit substantial changes of resistance with temperature. This is especially a problem with these resistors, since by definition they will undergo large temperature changes. Shunt resistors, as mentioned in Section 4.2.1.2, are purpose designed to exhibit very low temperature coefficients. They also usually have a very low value so that power dissipation is low in the resistor, and hence temperature rise is kept to a minimum. 4.2.1.7

half power operation

Power Rating

All resistors have a maximum power rating. However, a resistor should not be operated at its maximum power rating, since it is severely stressing the component. This severe stress usually results in a high failure rate of components. In order to ensure high reliability of resistors it is recommended that a resistor, at worst, is operated at half its nameplate power rating. It is probably better to be even more conservative than this and operate the resistor at approximately 1/3rd of its power rating. Practical issue 4.1 Select resistor power ratings so that they are operating at approximately 1/3rd of the device specified power rating.

pulsed power The above comments are implicitly for continuous power dissipation. However, one can modify them in relation to pulses of power, especially for wire wound resistors. Manufacturers of these resistances will sometimes give a table of pulsed powers for pulses of less than 100msec. Practical issue 4.2 Power ratings for non-wire wound resistors should be strictly adhered to. It is alright to have power pulses up to the maximum rating of the resistor for short durations (say less than 100msec) providing the repetition rate is not too high. Rheostat A Rheostat is a variable power resistor, as opposed to a Potentiometer which is a variable signal level resistor. Rheostats usually consist of a wire wound resistor that has a sliding contact. The power rating for the device is for the whole resistor. Therefore if the sliding contact is halfway along the resistor, so that only half the resistor is being used, then the power rating is half the nameplate value (so that the maximum temperature of each of the wire turns is the same as for the full resistor). One must be particularly careful with using these resistors on a voltage source, as it is easy to move the slide around so that the maximum power rating of the active section of the Rheostat will be exceeded. One can put a current meter in the circuit to make sure that the current rating of the device is not exceeded as adjustments are made, or alternatively another resistor can be put in series with the Rheostat to prevent overload.

4.2 Component Selection 4.2.1.8

4-5

Shunts

Whilst a shunt is a resistor, it is not used for the normal application of the resistor, which is to somehow limit current flow. With a shunt one wishes to impede the current flow as little as possible. A shunt is generally constructed of a near zero coefficient metal such as manganin, attached to heavy duty terminal blocks made of brass. Shunts come in a variety of sizes, ranging from very low current shunts, up to shunts that can handle thousands of amps. Typically a shunt is designed to produce either 50mV or 100mV at its rated current. Shunts are generally used if one wishes to measure low frequency or DC currents. In AC applications, current transformers are often used instead since they offer isolation. Remark 4.2 It should be noted that the use of shunts in high power Power Electronic applications is not very common these days. For example, it is not common for shunts to be used to measure the currents in inverter systems. Instead Hall Effect transducers are used, since they have good frequency response and offer isolation. Consider a 100A shunt with a 100mV output. This means that the resistance of the shunt is 100mV / 100A = 1mΩ. In addition to the resistance of the shunt there is a parasitic inductance. For a 1in shunt, this inductance is of the order of 10–20nH. If we assume 20nH, then we have an AC model for the shunt as shown in Figure 4.1. Obviously the impedance of this circuit is Rshunt +jωLshunt which is frequency dependent. Clearly there is a zero in the impedance frequency response, and hence above a certain frequency the voltage across the shunt will increase due to the effect of the inductance.

Rshunt

Lshunt

Figure 4.1: Equivalent circuit model of a current shunt inductance effects We found above that the value of resistance for a shunt is usually low. Therefore, even though the parasitic Lshunt is low, the frequency at which the zero occurs can also be relatively low. If we use the specific values from the previous paragraph, then we have that the zero in the impedance occurs when ωLshunt /Rshunt = 1 which gives f = 1mΩ/(2π × 20nH) = 8kHz. In many real applications for shunts the currents will contain frequencies above 8kHz, and hence one would be getting erroneous current readings. Remark 4.3 One way to raise the frequency at which the impedance zero occurs with the shunt is to raise the resistance of the shunt. However, in high current applications this is not feasible. An alternative strategy is to lower the inductance of the shunt by making it from stacked layers of metal, instead of a single piece. There are practical limits on how far this can be taken. A control person would immediately think of another solution to the shunt frequency response problem – try and arrange a pole-zero cancellation so that

4-6

Introduction to Practical Design of Switch Mode Power Supplies infinite frequency response can be obtained. The obvious way to do this is to place a capacitor in parallel with the shunt – i.e. in parallel with the equivalent circuit of Figure 4.1. The impedance function with the capacitor can be easily sown to be: Rshunt + jωLshunt (4.1) Zeq = (1 − ω 2 Ccomp Lshunt ) + jωCcomp Rshunt where Ccomp , the compensating capacitor value. If we make the assumption in (4.1) that ω 2 Ccomp Lshunt  1 then: Zeq ≈

Lshunt Rshunt (1 + jω R ) shunt

1 + jωCcomp Rshunt

(4.2)

Clearly for pole zero cancellation we require: Ccomp Rshunt =

Lshunt Rshunt

(4.3)

which means that: Ccomp =

Lshunt 2 Rshunt

(4.4)

Substituting in the values for the 1mΩ shunt one gets: Ccomp =

20nH = 20, 000µF (1mΩ)2

(4.5)

Clearly this is not a practical value of capacitance. Fortunately there is a way to achieve the same effect in the op amp amplifier circuit that is required to amplify the current shunt voltage signals. The value of capacitance used in this circuit are much more reasonable values (usually in the nF range) [5]. 4.2.1.9

PCB Track Resistors

If one is looking for a budget priced version of the shunt one can use the resistance of a PCB track. This type of shunt will have poor accuracy because it relies on the accuracy of the track width and thickness, and the temperature coefficient for copper is very poor (0.4%/◦ C). However, this type of current sense can be used for over-current protection. Practical issue 4.3 The resistance of a trace is approximately given by the formula [5]: length R = 0.5mΩ (1 oz. copper) (4.6) width at room temperature. Two-ounce copper has half this value.

4.2.2

Capacitors

Just as there are different types of resistors, there are different types of capacitors. In any design it is usually not possible to use just one type of capacitor – the correct capacitor technology must be used for the application.

4.2 Component Selection 4.2.2.1

Types of Capacitors

Capacitor types are defined by their construction technology. The main types of capacitors in common use are: Electrolytic This is one of the most common types of capacitors used for large capacitance. There are a variety of choices available, with the most common being the aluminum electrolytics. These capacitors can have very large values – well into the millifarad range, and many hundreds of volts. Note that these capacitors are physically very large. There are also tantalum electrolytic capacitors, which are available in solid and wet varieties. These capacitors tend to have maximum sizes that are smaller than those attainable in the aluminum electrolytic variety, but they have better high frequency performance. A distinguishing feature of all electrolytic capacitors is that they have a polarity. Ceramic These are the flat, disc like capacitors that home hobbyists would be familiar with. They are used for timing and bypass purposes. They are available in values from a few picofarads to 1µF. New in this range of capacitors are the multilayer ceramic (MLC) variety, which have very low effective series resistance and larger maximum values (several hundred microfarads) as compared to the older ceramics. Plastic These capacitors can withstand very high dv/dt across them, particularly the polypropylene variety. They are used in circuits such as quasiresonant SMPSs. Another variety, Polystyrene, are more specialised, and are used where very low leakage is required, such as in sample-hold applications.

Type

Suggested Applications

Aluminum Electrolytic Tantalum Electrolytic Ceramic Multilayer ceramic Plastic

Used when large capacitance needed. Low frequencies. Bulky. Use for moderate capacitances. Medium frequencies. Less bulk. Timing and bypass applications. High frequency bypass, low leakage applications. Use for high dv/dt applications. Low leakage current applications.

Table 4.2: Capacitor application guide The information in the above description is summarised in the Table 4.2. 4.2.2.2

Standard Values

Capacitors do not have the same range of values as modern resistors do – in fact the preferred values are basically the same as those available in the old carbon resistor ranges: 1.0, 1.2 1.5, 1.8, 2.2, 2.7, 3.3, 4.7, 5.6, 6.8, 8.2. Note that 5.6 and 8.2 are not always available. One can get away with this crudely spaced set of values because the tolerances for capacitors are generally not all that accurate anyway. Also, in many applications, it is the value of a capacitor in relation to a resistor that is the

4-7

4-8

Introduction to Practical Design of Switch Mode Power Supplies important quantity. Therefore, one can adjust the resistor to get the desired result. Practical issue 4.4 Just as large resistor values should be avoided, one should also avoid the use of capacitor values less than approximately 22pF. The reason for this is that capacitance exists between any parallel plates, and consequently parasitic capacitances on a PCB can swamp out the designed low values of capacitance. 4.2.2.3

Tolerance

The tolerances on capacitors are usually very poor – typically ±20%. Electrolytic capacitors can have even worse tolerances than this. The other variable to consider is the temperature range that the capacitor will operate over. The capacitance value can vary substantially with temperature, e.g. some types of capacitors can loose 80% of their capacitance at -40◦ C. 4.2.2.4

ESR and Power Dissipation

The equivalent series resistance (ESR) of a capacitor is a very important variable, since it determines the performance of the capacitor in many applications, and is also closely related to the power dissipation in the capacitor. Most manufacturers quote the ESR at 100 or 120Hz. The reason for this is that they imagine that the capacitor is being used in power supply smoothing applications. These values of ESR are useless in determining the ESR at say 100kHz (which is necessary in power electronics applications). Therefore, if you are using a capacitor in a power electronic application with high frequency currents, make sure that you have a relevant value of ESR. Remark 4.4 The ESR resistive can have a very important effect on the voltage ripple from a capacitor. For example, if one is pulling 1 Amp of ripple current at 100kHz from a capacitor, and the ESR is 100mΩ, then there is 100mV of ripple introduced by the voltage drop across this internal resistance. Therefore, if one requires 50mV of ripple maximum, then one would need at least two capacitors in parallel, and we have not even taken into account the amount of capacitance required to supply the charge to the load. The situation in relation to the ESR could be even worse if the capacitor has to operate over a wide temperature range. 4.2.2.5

Aging

Aging of capacitors, especially in relation to electrolytics, can be very important. Electrolytic capacitors may have a life time figure associated with a certain temperature of operation. Values could be 1000 hours, 2000 hours, or even better 5000 hours. When a capacitor approaches its design age the capacitance decreases, and the capacitor will be out of specification. In the worst circumstances the capacitor may fail. Fortunately, for every 10◦ C drop in temperature, a capacitors life doubles. For example, is a capacitor is rated at 2000 hours at 85◦ C, then if it is operated at an average temperature of 25◦ C, then it will last 2000 × 26 = 128, 000 hours, or 16 years.

4.2 Component Selection Remark 4.5 The use of the average temperature the capacitor is subjected in the above calculation is important. 4.2.2.6

dv/dt Rating

There are two forms of dv/dt rating for capacitors depending on the application and the technology of the capacitor. Electrolytic capacitors, for example, usually have a rating on the amount of rms ripple current that they can tolerate. This rating is related to the average i2 R lose in the ESR resistor, and the thermal properties of the capacitor package. Metallised plastic capacitors used in resonant and quasi-resonant converters have a dv/dt rating. In these applications these capacitors can sometimes be subject to very rapid rates of change of voltage across them. This in turn leads to very large current flows via the expression i = C(dv/dt). These large peak currents can cause instantaneous heating in the capacitor, which can result in the destruction of the capacitor if the rating is exceeded. Remark 4.6 Depending on the application the ripple current or the dv/dt rating may be important. Ripple current tends to be the appropriate measure when the capacitor is being used in an application where the voltage across the capacitor is relatively constant. dv/dt is relevant with the voltage across the capacitor undergoes large and rapid transients. 4.2.2.7

Series Connection of Capacitors

Sometimes capacitors are series connected in order to get the required voltage rating. However, if precautions are not taken one will find that one of the capacitors will be supporting more of the voltage than the other. This is due to the fact that the capacitance of so-called identical capacitors are not the same. Since the same current flows into each capacitor, then one will inevitably have a higher voltage than the other. The way to force better sharing of the voltage across the capacitors is to parallel resistors with the capacitors, as shown in Figure 4.2. This arrangement will keep the capacitor voltages equal at DC, but depending on the values of the resistors and capacitors, there may be some degree of imbalance in a situation where there is a large ripple.

4.2.3

Diodes

There are two main types of diodes used in SMPS circuits – normal rectifier diodes, and Schottky diodes. We shall see in Section 5.2.1 that there are special PN junction diodes required for very high powered applications, but we shall not be considering these here. 4.2.3.1

Schottky Diodes

Schottky diodes are constructed using a metal-semiconductor junction, as compared to a normal diode which has a semiconductor-semiconductor PN junction. The special property of the Schottky diode is that it does not have the charge storage problems that normal PN diodes have. Consequently these diodes will

4-9

4-10

Introduction to Practical Design of Switch Mode Power Supplies

+

+

Figure 4.2: Method of voltage sharing for series capacitors. turn off almost instantly when a reverse voltage is applied to them. The other advantage if the Schottky diode, as compared to the PN diode, is that the forward voltage drop is much lower – approximately 0.2V for the Schottky, and 0.6V for the PN diode. There are a few caveats associated with Schottky diodes – they can only operate at fairly low voltages, up to about 100V; the higher voltage Schottky diodes tend to have a forward voltage that is approaching a PN diode; the internal space charge capacitance of a high voltage Schottky diode can be high, thus resulting in reverse current when the capacitance is charging as the diode is reverse biased. 4.2.3.2

reverse recovery

PN diodes

These are the conventional diodes. They are available in many different types, from “slow” rectifier diodes, to ultrafast signal diodes. The latter are more akin to the diodes used in SMPS circuits. The ultrafast refers to the reverse recovery characteristics of the diode. The fast diodes have the ability to get the stored minority charge out of the diode very rapidly when the device is reverse biased. Whilst the stored charge is disappearing the diode is able to conduct current in the reverse direction. This phenomenon is known as reverse recovery. v

v -

+

i Forward current

-

+

i Reverse recovery current

Figure 4.3: Reverse recovery in a converter secondary circuit.

4.2 Component Selection

4-11

Forward current

+

Reverse recovery current Figure 4.4: Reverse recovery in a boost converter circuit. Reverse recovery can have a variety of effects from poor converter efficiency, to destruction of power devices. These two situations are illustrated in Figures 4.3 and 4.4. In Figure 4.3 one can see that when the voltage across the diode reverses, the diode will conduct current for a short period of time. This current could potentially be very large since the impedance opposing it would be small, and the voltage driving it large (a combination of the output filter capacitor voltage in series with the voltage appearing across the secondary of the transformer winding, which would now aid the reverse current flow). Clearly this situation is not good for converter efficiency, and the rapid rate of change of the reverse flowing current through the diode would result in a lot of EMI being produced. Figure 4.4 is a basic schematic of the boost converter circuit. When the MOSFET turns on energy is stored in the inductor, and the diode is reverse biased. When the MOSFET turns off the current has to continue flowing, and the diode immediately becomes forward biased. The current then flows through the the load and its filters. The reverse recovery problem occurs in the next event. The MOSFET again turns on to store more energy in the inductor. However, because the inductor has been forward biased it has stored minority carriers in it. When it becomes reverse biased, these minority carriers result in the diode conducting reverse current as well as it did when forward biased. The only limitation to the current flow is the impedance of the circuit, which is very low in this case. Consequently, in some circumstances the MOSFET may receive too much current and destroy itself. Even if this does not happen there will be excessive power dissipated in the device, and large amounts of EMI generated. Practical issue 4.5 Most converters will use either ultrafast diodes, or Schot-

4-12

Introduction to Practical Design of Switch Mode Power Supplies tky diodes to prevent reverse recovery problems. Remark 4.7 Synchronous rectifiers are a very low loss rectifier employing a MOSFET. Even with these devices a Schottky diode is placed in parallel with the MOSFET to take the instantaneous currents that need a path when the MOSFET is not on during the forward bias period. The body of a MOSFET has a parasitic diode around the device, but this diode is very slow. A Schottky diode in parallel with the device prevents the internal diode from being used. Remark 4.8 Ultrafast diodes themselves generate a lot of EMI. This occurs because an ultrafast diode still has reverse recovery current, the ultrafast bit being that it only last for a short period of time. However, as the diode rapidly decreases the reverse current, it generates a very rapid rate of change of current, and consequent EMI.

4.2.4

The BJT

I shall not spend much time on describing the practical issues of using Bipolar Junction Transistors (BFTs), since they are not commonly used today. For small to medium power SMPSs MOSFETs have large enough current and voltage range for most applications. For very high power applications, Insulated Gate Bipolar Junction Transistors (IGBTs) are more commonly used. We shall not look at these devices here since they will be described in detail in Section 5.2.4. Power BJT transistors were the device of choice for SMPS applications some 15 to 20 years ago. They are not used today because of the difficulty in using the devices. For example, power BJT transistors have a very low current gain (typically known as the β of the device), especially in higher voltage applications. This means that considerable current must be supplied to the base of the device if there is a large current from the collector to emitter. This may not be a problem for small converters, but it is an issue at larger powers. The consequence of this high current is a complex and expensive base drive circuit. A second problem is the voltage drop across the device. Even when a transistor is turned hard on the collector to emitter voltage is approximately 0.2 volt. Therefore the power lost in the device is approximately ic vce . A MOSFET on the other hand would have a much lower voltage drop, and therefore much lower power loss. A final problem with the BJT is turning the device off. As with the diode, the BJT is a minority carrier device. Therefore it also suffers from charge storage problems. Consequently, when the device is turned off it will continue to conduct current from the collector to the emitter until the stored charge disappears. Special base drive circuitry must be used to get rid of the stored charge as quickly as possible.

4.2.5

The MOSFET

As mentioned in Section 4.2.4, the MOSFET is by far the most common transistor used in SMPS systems. There are two main types of MOSFETs used – n-channel devices (the most common ones), and p-channel devices – useful in certain situations. The n-channel device turns on when there is a positive voltage exceeding the threshold voltage, between the source and gate of the device.

4.2 Component Selection The p-channel device is the dual of this, and turns on when the gate has a voltage that is negative compared to the source. If the source of the p-channel device is connected to the positive supply rail of a system, then the device can be turned on by simply connecting the gate to ground. Remark 4.9 One could consider the p-channel MOSFET to be a device that turns on with an active low signal, whereas the n-channel device requires an active high signal. Remark 4.10 The n-channel device is more commonly used because the resistance of these devices is less for the same size die. Consequently the cost for a given current rating is less. 4.2.5.1

Bi-directional Conduction

It should be noted that MOSFETs can conduct current in both directions – i.e. from drain to source, and source to drain. We have seen this fact used in synchronous rectifiers in Section 2.4.9. 4.2.5.2

Power Losses

There are three sources of losses in MOSFETs used in switching applications: Conduction losses These are the losses in the MOSFET resistance when it is on. The calculation of this loss is simple – P = I 2 RDSon . However, one should be aware that the MOSFET has a positive temperature coefficient, so as the device heats up its RDSon increases based on the typical expression: R(T ) = R(25◦ C) × 1.0078e(T −25) (4.7) Therefore to calculate the power, one must first work out an initial power using the 25◦ C value of RDSon , and then work out the temperature rise (using the package thermal resistance), and recalculate the power. This procedure is carried out iteratively until the power value converges to a value.1 Gate Charge Losses This is not really a loss in the MOSFET, but a lose in the gate drive circuitry driving the MOSFET. This is due to the fact that the gate of a MOSFET looks like a capacitor. Therefore in order to get the voltage of the gate to rise quickly a substantial current must momentarily flow into the gate. Many data sheets give the total charge to bring the gate voltage to a certain voltage level, Qg . If the voltage level you are using is different then a reasonable approximation is to multiply the Qg data value by the ratio of your voltage to the data sheet voltage. The power can then be calculated by using P = Qg V fs where fs is the switching frequency. Switching Losses This is a loss that is dissipated in the MOSFET itself. When a hard switching converter is turned off there is a period of time where the MOSFET is conducting a substantial current and is supporting a substantial voltage. During this period there is substantial power dissipation 1 Usually this calculation only requires one or two iterations. The thermal resistance is a poorly known parameter, and if convergence does not occur then one is probably dissipating too much power.

4-13

4-14

Introduction to Practical Design of Switch Mode Power Supplies in the device. Clearly the more times the device is switched per unit time, then the more average power will be dissipated in the device. In order to roughly calculate the losses due to switching one can assume that as the device turns off or on that the voltage rises or falls as a linear function of time. Whilst this is happening the current through the device is more or less constant. Therefore the expression for the power dissipation for one on-off event would be the average voltage times the current – i.e. P 0 = Ipk Vpk ts /2, where ts is the time for the on-off switching event. Therefore the total power dissipated over a one second interval (i.e. the total energy dissipated in the device per second) is the energy dissipated per switching event multiplied by the number of switching events per second – i.e. P = Ipk Vpk ts fs /2 Remark 4.11 By calculating the conduction and switching losses, and using the thermal resistance of the MOSFET package one can come up with an estimate of the temperature rise of the device. This estimate is a good measure of whether the device is going to run hot or cool. 4.2.5.3

MOSFET Gate Resistors

You should always put a resistor in series with the gate of a MOSFET. This is required because the gate capacitance in series with the gate lead inductance forms a high Q series LC resonant circuit. These circuits can oscillate at frequencies in the 100s of MHz range. They result in excessive heating of the MOSFET and the emission of copious EMI radiation from the circuit. The inclusion of the gate resistor provides the necessary damping to lower the Q of the resonant circuit so that any oscillations are damped out quickly. Practical issue 4.6 If you have two MOSFETs in parallel you should put an individual resistor in series with each of the gates. If a single resistor is shared between two gates then oscillations can occur between the two MOSFET gates. 4.2.5.4

Maximum Gate Voltage

Some designers decide to make the gate-source voltage very high in order to get the gate voltage past the threshold voltage of the MOSFET in the minimum time. If the gate-source voltage exceeds approximately 20 volt, then the MOSFET is likely to be damaged. To turn a device on the most important thing is to have a very low impedance gate drive so that the current can be sourced to charge up the gate capacitance.

4.2.6

Operational Amplifiers

Operational amplifiers are used extensively in SMPS control systems. We have briefly considered control aspects of SMPS in Section 3.3. This discussion however, did not consider some of the practical issues involved in using Op Amps. These practical issues are related to the non-ideal behaviour of Op Amps. Much of the following discussion is relevant to general usage of Op Amps, and is not particular to their use in SMPSs.

4.2 Component Selection 4.2.6.1

4-15

Offsets

There are two main types of offsets in Op Amps: a. Input Offset Voltage. This is effectively a voltage between the + and − terminals of the Op Amp. It is a result of manufacturing differences between the electronics of the input circuitry of the Op Amp. The offset voltage is usually a small value – i.e. mV or µV. b. Input Offset Current. The input impedance of a real Op Amp is not infinity. Therefore current will flow into the terminals. Due to manufacturing tolerances, the current in the + and − terminals can be different. The input offset current is very small in absolute terms – usually of the order of nAmp. Considering the small values for the offset voltage and current one might be tempted to say; “What is the problem?”. The problem with the offsets is due to the fact that an Op Amp has a very high open loop gain, which is usually greater than 106 . Therefore, if one has, say a 2mV offset voltage at the input, then the output would be 2 × 10−3 × 106 = 2 × 103 . Most Op Amps operate on a power supply of 12 to 15 volt. Therefore the offset voltage would result in the output of the Op Amp being saturated to the supply rail. The immediate retort to the above paragraph is that Op Amps are never operated in open loop, but have feedback around them that lowers the effect gain. However, even with feedback, the gain can still be quite high, resulting in significant output offset voltage. Similar arguments can be mounted with offset current when there are resistances in series with the inputs.

+ LM2902 -

100k 9.09k

10k

Figure 4.5: Operational amplifier circuit for discussion of offsets. 4.2.6.1.1 Input Offset Voltage The following discussion is with reference to the circuit of Figure 4.5. This shows a typical Op Amp circuit, with the noninverting input shorted to ground. If the Op Amp was ideal then the output voltage would be zero under these conditions. However, the offset voltage for a LM2902 Op Amp is approximately 2mV. This means that there is effectively

4-16

Introduction to Practical Design of Switch Mode Power Supplies 2mV between the + and − terminals. The gain of the amplifier is 10 in this case, making the output with a zero input voltage equal to ±2mV ×10 = ±0.02 volt. In many applications this may not be a problem. However, if the gain was 1000 then the output offset would be 2 volt, which is clearly unacceptable. Remark 4.12 Note that the output offset due to input offset voltage is not a direct function of the resistors used, but is related to the gain of the amplifier. 4.2.6.1.2 Input Offset Current The following discussion is also with respect to Figure 4.5. In this case we shall assume that the offset voltage is zero. Because the inputs to a real Op Amp take slightly different currents, then the voltage at each of the input pins can be slightly different due to the differing voltage drops across the resistors. For example, in the case of the LM2902, the difference between the input currents can be as much as 5nA. Therefore the voltage difference between the two terminals can be 9.09 × 103 × 5 × 10−9 = 45µV. This voltage, in turn, is amplified by the gain of the amplifier to give 450µV output voltage. As with the offset voltage case, in many applications this is not serious, but if the gain is high, or very high precision is required, then the effect of the input current offset may cause significant output voltage offset. Remark 4.13 The effects of input current offset occur simultaneously with input voltage offset, therefore the output offsets have to be added together. Remark 4.14 Input current offset will become more pronounced if larger resistance values are used. Remark 4.15 More expensive amplifiers are laser trimmed internally in order to lower the input offset current. 4.2.6.1.3 Input Bias Current The input bias current is the current that flows into the input terminals even if there is no input offset current effect. The input bias current can cause offset problems if the resistances in the input terminal leads are mismatched. In the case of Figure 4.5 we have been careful to choose the resistors so that the effective resistance through which the bias currents flow is the same. However, if there is a mismatch in the resistance values due to resistor tolerances, or alternatively due to other external circuit considerations, then there will be different voltage drops across the input circuit resistors. This results in the generation of different voltages on the input pins to the Op Amp. As a specific example, if we assume that the resistor to ground from the non-inverting terminal is 19.09kΩ, and the input bias current for the LM2902 is 90nA, then the difference in the resistance seen by the two bias currents is 10kΩ. Consequently the bias current offset voltage is V = 90nA×10kΩ = 900µV. This voltage in turn is amplified by the amplifier gain of 10, giving an output offset of 9mV. Remark 4.16 Clearly, one should try and get the resistance in series with the Op Amp inputs to be the same values to eliminate the effect of bias currents on the output.

4.2 Component Selection

4-17

Summary 4.1 Given the above discussion, we can develop and expression for the output offset: V = [Vos + Ios R + Ib ∆R]Acl (4.8) where Vos , the input offset voltage, Ios , the input offset current, Ib , the input bias current, R , the average value of the input resistors, ∆R , the difference between the values of the resistors, and Acl , the closed loop gain of the amplifier. Remark 4.17 One can see from (4.8) that in order to minimise the output offset one must: • Keep the resistor values as small as feasible to minimise the effect of the Ios current. • Make sure the input resistor values are closely matched so that ∆R ≈ 0 . • Choose an amplifier with a very small Vos . Note that a low Vos Op Amp often has a lower gain-bandwidth product. 4.2.6.2

Limits on Resistor Values

10MW 10kW +

10kW

Figure 4.6: Conventional inverting Op Amp circuit with a gain of 1000. It has been previously mentioned in Section 4.2.1.1 that it is not desirable in general to choose large values of resistors. In Op Amp circuits there is often a temptation to do this when one is endeavoring to get a high gain feedback amplifier. Let us consider the specific example circuit shown in Figure 4.6. This is a conventional inverting Op Amp circuit, and the resistors have been chosen so that the feedback gain of the circuit is 1000. The other requirement is that the input impedance of the circuit is 10kΩ. Consequently the feedback resistor is 10MΩ. This value of resistor is far too large to be practical. Besides the problem that it will pick up a lot of electrical noise, it may not even be effective since the leakage impedance across the PCB is probably lower than this value.2

4-18

Introduction to Practical Design of Switch Mode Power Supplies

R2

R4

R3 R1 vin

-

vo +

R1

Figure 4.7: Inverting Op Amp circuit with alternative feedback network.

An alternative circuit that can be used in this situation is shown in Figure 4.7. In this case the feedback voltage is lower by the inclusion of the voltage divider network comprised of R3 and R4 . This result of this network is that the output voltage has to be higher in magnitude than it otherwise would be to get the full input current (vin /R1 ) to flow through the R2 resistor. The benefit that one obtains is that there is much more freedom to choose the resistors so that one can keep reasonable values and obtain the required gain. If one calculates the gain of the Op Amp circuit of Figure 4.7 then it can be shown that it is: vo R2 R4 + R3 R4 + R2 R3 =− (4.9) vin R1 R3 Let us consider the specific example of a gain of 1000. If we assume that the input resistance of the circuit has to be 10kΩ, then this makes R1 = 10kΩ. Let us then choose R3 = 1kΩ, which will result in a significant voltage division effect through the feedback network without having the other resistor values too large. We still have two other resistor values to choose – R2 and R4 . Let us arbitrary choose R2 = 100kΩ. The denominator of (4.9) now has a value of 10MΩ, which means that the numerator must have a value of 1010 Ω to achieve the required 1000 gain. The only unknown now is R4 . Substituting the known values into the numerator expression of (4.9), and equating to 1010 , one can calculate that R4 = 98kΩ. Therefore, to summarise, the resistor values are: R1 = 10kΩ, R2 = 100kΩ, R3 = 1kΩ, and R4 = 98kΩ. We have achieved the required gain from the circuit without having to resort to any resistor values greater than 100kΩ. This would reduce the noise pick of this amplifier circuit considerably. Remark 4.18 A similar feedback resistor arrangement can be used for inverting amplifiers. However, in this case one is not constrained by the input impedance 2 If one did not have the input impedance constraint then a smaller value for the input resistor could be chosen so that the feedback resistor would be less than or equal to 1MΩ.

4.2 Component Selection

4-19

requirement, and therefore one has more freedom to choose the resistors in the conventional non-inverting feedback amplifier.

4.2.6.3

Gain-Bandwidth Product Gain (dB)

Aol Gain bandwidth product

Acl

log f

0

fol-3db

fcl-3db

funity

Figure 4.8: Gain-bandwidth product of an Op Amp. Consider Figure 4.8 which shows a typical frequency response of an amplifier. The open loop gain, Aol , of the amplifier is very high – a gain greater than 106 is normal. However, the open loop frequency response rolls off at a very low frequency, usually 1 to 2 Hz. Since Op Amps are not designed to be used in open loop this is not a concern. Eventually the open loop gain of the amplifier goes to one. The frequency at which this occurs is the gain-bandwidth product of the amplifier. This figure is a constant for the amplifier. Therefore, if one applies feedback around the amplifier, this will lower the gain to say Acl . Therefore the roll-off frequency of the amplifier will be increased. The frequency of the -3db roll-off multiplied by the gain at this point is equal to the gain-bandwidth product. Therefore Aol fol−3db = Acl fcl−3db = funity . The importance of the gain-bandwidth product is that it indicates whether one can simultaneously achieve the gain and bandwidth specifications from an Op Amp circuit design. There are many different Op Amps available, with widely varying gain-bandwidth products. In SMPS applications one can find that high gains are required to moderate bandwidths – for example a gain of 300 and an bandwidth of 20kHz. In this case one would need an amplifier with a gain-bandwidth product of 300 × 20 × 103 = 6MHz. Whilst this is a very modest gain-bandwidth product for a discrete Op Amp, it may actually be larger than that of an integrated Op Amp that is inside a PWM IC. The effect of exceeding the gain-bandwidth product of the amplifier on the performance of the SMPS system may be poor disturbance rejection, or even worse instability (due to excessive phase shift in the feedback).

4-20

Introduction to Practical Design of Switch Mode Power Supplies 4.2.6.4

Phase Shift

Phase shift is related to the frequency response of the amplifier circuit shown in Figure 4.8. It is well known from control theory that at the -3dB point of a single pole frequency response the phase shift from input to output is −45◦ . At approximately a decade above this the phase shift has converged to approximately −90◦ . In an Op Amp circuit the situation is often more complicated than this due to the effects of internal compensation within the Op Amp itself. This can result in even more phase shift due to the introduction of more poles in the higher frequency areas of the frequency response. The only way to accurately determine the phase shift characteristics of an Op Amp is to actually measure them over the frequency range of interest. It is not always true that amplifier with higher gain-bandwidth product will have less phase shift. Remark 4.19 Excessive phase shift through an error amplifier in a feedback loop can result in a degraded phase margin. The result on the performance is ringing when there are step changes in the system, or marginal stability. 4.2.6.5

Slew Rate Limits

Slew rate limits are a non-linear effect related to the current limitations on the output stages of an Op Amp. Any Op Amp has a maximum rate at which the output can change. This is different from the gain-bandwidth product where one is assuming that the high frequency signals are very small in amplitude, and therefore do not encounter slew rate limit problems. Consider the situation where an Op Amp circuit is being driven by a sine wave. The maximum rate of change of the sine wave occurs when it goes through zero. The slope of the sine wave at that point is given by its derivative, Vm ω cos ωt, evaluated when ωt = nπ, n = 0, 1, 2 · · · . One can see that the maximum slope increases with both frequency and amplitude of the sine wave. Therefore, if the amplitude is increased at a given frequency then it may be possible to exceed the slew rate limit of the amplifier. If one had an amplifier of gain 10, with a 1 V p-p input sine wave input, then the output would be 10 V p-p. If the frequency of the input is 200kHz, then the maximum rate of change of the output would be 10 × 2 × π × 200 × 103 = 12.6V/µsec. Many low power Op Amps cannot slew their output this fast. When the slew rate limit is hit, the output tends to increase as a straight line at the slew rate. The slew rate becomes important in high-bandwidth SMPSs. When there is a rapid transient at the output, the error amplifier will see a large input. If the output slew rate of this amplifier is hit, then it will effectively introduce a phase lag in the feedback. This can result in poor disturbance rejection. It could also affect phase margins.

4.2.7

Comparators

A comparator is a special type of Op Amp specialised for comparison applications. In relation to voltage and current offsets the same principles apply to the comparator.

4.2 Component Selection 4.2.7.1

4-21

Hysteresis

Almost always whenever a comparator is being used it should incorporate hysteresis in the input. This is to prevent false triggering and potential oscillation of the device.

Vref -

vin

vo

+

R1

R2 Figure 4.9: Comparator with hysteresis. Figure 4.9 shows a comparator circuit with hysteresis established by the judicious application of positive feedback. If one carries out a little analysis on this circuit then one can see:     R1 R1 v+ = vin 1 − + vo (4.10) R1 + R2 R1 + R2 where v+ , the voltage on the ‘+’ terminal of the comparator. To understand how this works, let us consider a specific example. Assume that R1 = 1kOmega and R2 = 100kΩ, which means that R1 /(R1 + R2 ) ≈ 0.01. Under this condition: v+ = 0.99vin + 0.01vo (4.11) If v+ < v− , then vo = −V , the negative supply voltage. If this is substituted into (4.11) and the expression is rearranged, then for v+ = Vref we have: Vref + 0.01V (4.12) 0.99 Therefore the input voltage, vin , has to be greater than the reference approximately by 0.01V (it is actually a little more than this). At this input the comparator would switch so that the output voltage would become +V . We can then repeat (4.12) for this case and get: vin =

Vref − 0.01V (4.13) 0.99 As we can see the input voltage has to be less than the reference voltage, again by approximately 0.01V for the comparator to reach the switching state. Therefore we have implemented classic hysteresis by the process, with the hysteresis band being approximately 0.01V around the nominal reference voltage. vin =

4-22

Introduction to Practical Design of Switch Mode Power Supplies 4.2.7.2

Comparator Interfacing

Comparators that have a single supply rail often don’t pull the output right down to the ground rail when the output should be zero. This can have a dramatic effect if the device is driving a BJT or a logic gate. For example, some comparators are only guaranteed to have a low output of approximately 0.6-0.7 V when sinking 6mA of current. Practical issue 4.7 If the comparator output does not pull to near zero at the current level the output will be operating at, then the output voltage under the low condition must be accounted for when calculating the resistors for hysteresis.

+V

+V +

10kW

Figure 4.10: Interfacing a comparator to an NPN transistor. Figure 4.10 shows a technique for interfacing a comparator to a NPN transistor. If the comparator only pulls down to say 0.7V, then the 0.7V drop across the diode will ensure that the transistor is still off. The 10kΩ resistor ensures that the base of the transistor is firmly connected to ground when the diode is turned off. For the comparator to turn the transistor on the output needs to be greater than 1.4V.

4.3

Introduction to Magnetics Design

The design of magnetics for a real application is a complex task. there are many application specific decisions that have to be made – the core material, core style, type of conductor etc. There is usually no correct answer, since the particular solution that a designer ends up with depends on the criteria used to decide the optimal solution. The following discussion is far from an exhaustive treatise on the design of magnetic for SMPSs. The presentation closely follows that in [5], and will concentrate on some of the main practical issues. A more detailed treatment of the design on magnetics for SMPSs can be found in [4].

4.3 Introduction to Magnetics Design

4.3.1

4-23

Review of the Fundamentals

Before looking a the specifics of SMPS magnetics design, it may be opportune to review the fundamental concepts and expressions that are required. 4.3.1.1

Ampere’s Law

The law that connects the magnetic field intensity and mmf produced. It also connects the magnetic field intensity and the flux produced. The normal integral equation for Ampere’s Law in a physics or electromagnetics text is: I F = H · dl (4.14) where boldfacing means that the quantity is a vector, and F , the mmf in Ampere-turns, H , the magnetic field intensity vector in Ampere-turns/metre, and dl , an incremental path length vector. The direction of the H vector is the same as the direction of the flux vector in a isotropic medium. The direction of the magnetic flux density vector, B, can be determined by other techniques, but is defined for practical purposes by the right hand rule. Let us consider the application of (4.14) to a single strand of wire. We know a-priori that the F value in this case is I, the current being carried in the wire. Since the H and dl vectors are coincident around a circular path of integration (since the H vector is in the same direction as the B vector), and the total path length is 2πr, then one can conclude that: H=

I 2πr

(4.15)

where r , the radius of the path of integration. Remark 4.20 Equation (4.15) implies that the magnetic field intensity can be defined as: mmf F NI H= = = (4.16) l l l The relationship between Ampere’s Law and the magnetic field intensity is defined by the following: B = µr µ0 H = µH (4.17) where µr , the relative permeability, and µ0 , the permeability of free space. Equation (4.17) allows Ampere’s Law to be recast into a flux density form: F =

1 µ

I B · dl

(4.18)

In certain circumstances Ampere’s Law can be used to evaluate the magnetic field intensity, and under some circumstances the magnetic flux density. Fortunately, the design of transformers is one of the applications where the geometry is constrained in such a way that Ampere’s Law can be successfully applied in a simple fashion.

4-24

Introduction to Practical Design of Switch Mode Power Supplies 4.3.1.2

Faraday’s Law

Faraday’s Law is one of the fundamental laws of electricity. It was originally determined experimentally, and later derived from the more fundamental Maxwell’s equations, and subsequently from relativity theory. Every electrical engineer should know Faraday’s Law, but we will restate it here for completeness.

B(t)

Area A

v(t)

Figure 4.11: A loop of wire enclosing an area of time varying flux density. Figure 4.11 shows a typical situation where Faraday’s Law is active. Here we have a loop of wire, and orthogonal to the surface of the loop there is a time varying flux density, B(t).3 A voltage, v(t) is generated between the ends of the wire under this circumstance. Faraday’s Law tells us the magnitude of the voltage under this condition: v(t) =

dλ dφ dB =N = NA dt dt dt

(4.19)

where λ , the flux linkage, φ , the flux, and N , the number of turns of the coil. 4.3.1.3

Inductance

We know from Ampere’s Law that a wire produces magnetic field intensity, and consequently magnetic flux density. The inductance of a coil is a number that tells us something about how well the physical configuration of the coil produces flux density. For example, if a coil has more turns on it then it would have more inductance, if a coil has a large area then its inductance is larger, and it a coil is wrapped around a high permeable core material then its inductance will be higher. In all these situations, a higher inductance indicates that the coil is better at producing flux. 3 If the magnetic flux density vector is not orthogonal to the surface area, then it is the component that is that contributes to the Faraday voltage effect.

4.3 Introduction to Magnetics Design

4-25

The fundamental definition of inductance is: L=

dλ di

(4.20)

In the case of linear magnetic materials (i.e. the flux density varies linearly with the current through the coil) this expression can simply be written as: L=

λ I

(4.21)

Remark 4.21 A verbal definition of inductance is that it is the flux linkage produced though the coil per unit current flowing through the coil. Remark 4.22 Equation (4.20) is evaluated around some point of operation. Strictly speaking this definition is called the incremental inductance, since it is operating point dependent (i.e. dependent on the values of λ and i). Equation (4.21) can be used to develop the expression for the inductance in terms of the physical parameters of a coil. From (4.21) one can write: N AB Nφ = I I NI Since B = µH = µ l µN 2 A ∴L= l L=

(4.22)

(4.23)

where l , the length of the magnetic path. Remark 4.23 One can see from (4.23) that the inductance is defined entirely in terms of the physical characteristics of the coil. Note that the inductance is related to the square of the coil turns. Remark 4.24 In the case of a high permeability material as the coil the length of the magnetic path is easy to determine in (4.23). One can develop Faraday’s Law in terms of inductance using the flux form of Faraday’s Law and (4.22). From (4.22) one can write: N AB = Li

(4.24)

where the lower case i indicates that the current is changing. Substituting this into (4.19) one can easily see that: v=

dLi di = L for L constant dt dt

(4.25)

which is the familiar voltage relationship from circuits. Remark 4.25 Note that the L constant is not correct when the core material in a ferro-magnetic material which saturates.

4-26

Introduction to Practical Design of Switch Mode Power Supplies 4.3.1.4

A Note on Units

Unfortunately the area of magnetics is permeated with inconsistent units. This situation exists for largely historical reasons. Most of the unit confusion occurs between the mks system of units, and the cgs system. Just to make things even more confusing imperial units are also sometimes thrown in as well. Wherever possible I will use mks units in these notes. 4.3.1.5

The Three R’s

In magnetic circuits three terms beginning with the letter R are often used – Reactance, Remanence and Reluctance. We shall briefly review these (most electrical engineering students should already know what they are). 4.3.1.5.1 Reactance This is a quantity similar to resistance that is used when a circuit contains reactive elements such as inductors and capacitors. The reactance can be used in a generalised form of Ohm’s Law. For an inductor the magnitude of the reactance is Zl = 2πf L where f is the frequency of the voltage across or the current through the inductor. The voltage across the inductor is related to the reactance by Vl = Zl I, where Vl and I are AC phasors. A similar situation occurs with capacitance, where the magnitude of the reactance is Zc = 2πf1 C . If both resistance and reactance are both present, the impedance magnitude is: p |Z| = R2 + Z 2 (4.26) where Z is the generic impedance of the reactive element.

B

Bm

Br

H

Figure 4.12: A BH loop for a magnetic material. 4.3.1.5.2 Remanence Figure 4.12 shows a BH loop for a ferro-magnetic material. Notice that if the H is applied so that b = Bm and then driven back to zero there is some remnant flux still in the core. The level of this flux is the remanence of the core, and varies depending on the material. If the core is air, then the remanence is zero.

4.3 Introduction to Magnetics Design

4-27

Remark 4.26 Remanence is important as it relates to core utilisation and losses. For example a core with high remanence used in a uni-fluxed SMPS will have a lower core utilisation. If use in a flux reversing type of SMPS the hysteresis losses will be high. 4.3.1.5.3 Reluctance Reluctance is often used in circuit analogies of magnetic systems. Reluctance can be used in a way that is analogous to resistance in conventional circuit theory. Just as with resistance, the reluctance of a “magnetic circuit” is related to the physical attributes of the circuit. One way of developing the magnetic circuit analogy is to consider the mmf in a similar way to voltage is considered in a conventional circuit. This makes some intuitive sense because one can consider that the mmf is the driving force that produces the flux. We can substitute (4.16) into (4.17) to give: B = µH =

µN I l

(4.27)

Multiplying both sides of (4.27) by the area of the core, A, gives: φ = BA =

µAN I l

(4.28)

This expression can be rearranged to make the mmf the subject of the expression: l F = NI = φ (4.29) µA From (4.29) we can then identify the reluctance term as: l µA

(4.30)

F = Rφ

(4.31)

R= Therefore (4.29) can be written as:

where the flux, φ, is analogous to the current in a conventional circuit. Remark 4.27 “Magnetic circuit” analogies are particularly useful in transformer applications because the magnetic paths are very well defined and their reluctances are known. Remark 4.28 Notice that the reluctance defined in (4.30) obeys the same intuition as resistance of wires. For example, if one doubles the cross-section of the core (i.e. doubling A) then the reluctance drops, just as resistance would if a wire diameter is doubled. Similarly, if the length of the core is increased then the reluctance increases. A similar effect also occurs with resistance.

4.3.2

The Ideal Transformer

It is beyond the scope of these notes to give a full treatise of transformers. Therefore we shall concentrate on the basic properties that are required to understand their design and operation in SMPS applications. We shall begin be considering the ideal transformer, since this is a useful concept to understand

4-28

Introduction to Practical Design of Switch Mode Power Supplies

Primary coil

Secondary coil

N1 turns

N 2 turns

Core Figure 4.13: Circuit symbol for a transformer. the operation of transformers. In addition, ferro-magnetic cored transformers are a reasonable approximation to the ideal transformer. Figure 4.13 shows the conventional circuit symbol for an iron cored transformer. The primary winding is the winding that is being driven by the source, and the secondary winding is usually connected to a load of some description. The dots on the ends of the coils indicate the way that the wire is wound on the core. If current is injected into the lead at the dotted end of the primary winding, then the flux produced in the core will have the same direction as that produced by the secondary winding if current is injected into its dotted terminal. From a voltage viewpoint, if a positive voltage appears on the dotted terminal of one of the windings, then a positive voltage will appear on the dotted terminal of the other winding. An ideal transformer is a transformer that has a core material of infinite permeability. This means that no mmf is required to set up a flux in the core, since the reluctance of the core is zero (regardless of its length or area). The infinite permeability has the implications that there will be no leakage flux in the transformer – i.e. all the flux produced by the primary winding will link to the secondary winding. We can calculate some of the basic properties of ideal transformers by applying Faraday’s Law using the properties mentioned in the previous paragraphs. Consider the voltage on the primary side of the transformer: v 1 = N1 A1

dB1 dt

(4.32)

dB2 dt

(4.33)

Similarly for the secondary we can write: v 2 = N2 A2

Since both windings are wound on the same transformer core, then A1 = A2 . Furthermore, since there is no leakage of flux density from the primary to the

4.3 Introduction to Magnetics Design

4-29

secondary (and vice-versa), then B1 = B2 . Consequently we can write: dB1 dB2 v1 v2 = = = dt dt N1 N2

(4.34)

Remark 4.29 Notice that the implication of (4.34) is that the volts/turn of the transformer are constant for both the primary and the secondary. Since the ideal transformer requires not mmf to establish flux in the core, we can write: N1 i1 + N2 i2 = 0 (4.35) which implies: i2 i1 =− N2 N1

(4.36)

Remark 4.30 Equation (4.36) could also be deduced using conservation of energy together with (4.34): v1 i1 + v2 i2 = 0 (4.37) Using (4.34) one can write: v2

N1 i1 + v2 i2 = 0 N2 N1 ∴ i1 = −i2 N2 i1 i2 or =− N2 N1

(4.38)

Remark 4.31 The negative sign in (4.38) indicates that the secondary current direction is opposite to the primary current direction. Remark 4.32 The implications of (4.34) and (4.38) are that if the voltage is stepped up between the primary and the secondary then the current steps down (and vice-versa).

4.3.3

Real Transformers

Real transformers do not have core materials composed of infinite permeability material. The relative permeability of iron based laminations is in the range of 1000-2000. Many of the power based core materials, which are widely used in SMPS applications, have permeabilities in the low hundreds range. The consequence of having finite permeability core materials is that not all the flux that is produced by one winding is linked to the other winding. Another consequence is that it takes mmf to produce flux in the core, since the core has reluctance to be overcome. Models of real transformers are often based on taking the ideal transformer and adding some extra elements around it to account for the non-ideal behaviour. Consider the flux required in the core to induce voltages in the secondary winding. If the secondary winding is open circuit, and if we apply a voltage to the primary, then the voltage across the primary is related to the rate of change of flux in the primary inductance. A small proportion of the primary flux does not link the secondary winding, and this is called the leakage

4-30

Introduction to Practical Design of Switch Mode Power Supplies flux. The inductance associated with this flux is called the leakage inductance. Most of the flux produced by the primary links to the secondary winding, and this is called the magnetising flux, and the inductance associated with it is called the magnetising inductance.

Ideal transformer Magnetising inductance

Lm

Ll

Leakage inductance

Figure 4.14: Simplified model of a real transformer. If the secondary winding has a circuit connected to it, then the voltage induced in the secondary by the magnetising flux will cause a current to flow in this circuit. Consequently there will be flux produced by the secondary winding. This flux will be in such a direction in the core that it will tend to cancel the magnetising flux. However, the flux in the primary is fixed by the applied voltage and its frequency (via Faraday’s Law), therefore this cancellation of flux will result in more current being drawn from the primary circuit to compensate for the cancelled flux. This is effectively the load current on the secondary being reflected back into the primary circuit. These arguments lead to the diagram of Figure 4.14. Notice that the magnetising inductance effectively shunts current away from the ideal transformer. Therefore the magnetising current is “wasted” in the sense that it does not contribute to the output current.4 Similarly, the leakage inductance will support voltage across it, and this voltage does not appear across the primary of the ideal transformer, and will therefore not be transformed to the secondary. 4.3.3.1

Core Materials

As mentioned in the previous section real core materials have finite permeability. In addition they also exhibit properties such as saturation, eddy current and hysteresis losses. These practical issues manifest themselves in different ways in different applications. Table 4.3 summarises that main types of materials available, and their relative merits and uses. 4 The magnetising current is usually large so that the magnetising current is only a few percent of the load current of the transformer.

4.3 Introduction to Magnetics Design

Material

Consideration

Air

Pro Air core magnetics cannot saturate. Con The relative permeability of air is one, so one cannot get large inductances. Furthermore, the leakage of an air core transformer would be very high. Usage Primarily find application in rf circuits. Not used in SMPS applications. Pro Ferrite magnetic materials are very widely used in both electronic and SMPS applications. They have very high permeability and therefore can be used to produce large values of inductance. These materials are usually relatively low cost. A variety of different materials are available for different frequency bands (to help control the losses).

Ferrite

Con Ferrites usually saturate hard. Poorly controlled initial permeability.

Molyperm (MPP)

Usage Ferrites are often used in power transformers and noise filters. Pro Soft saturation. Wide variety of different permeabilities, and there values are well controlled by the manufacturer. Con Higher losses than ferrites at a particular switching frequency. Usage Used for inductors and noise filters at high DC currents. Pro Lower cost than MPP cores.

Powdered iron

Con Slightly harder saturation than MPP, and lower permeability generally than MPP.

Steel laminations

Usage Same applications as MPP where cost is a more important consideration than size. Pro Very high saturation flux density, allowing the production of very high inductances. Con Comparatively expensive, heavy. Saturates hard, and has high losses, especially at high frequencies. New amphorous iron overcomes some of the deficiencies in relation to losses. Usage Low frequency transformers, power inductors.

Table 4.3: Core materials and their uses.

4-31

4-32

Introduction to Practical Design of Switch Mode Power Supplies 4.3.3.2

Saturation

Saturation is a phenomena in ferro-magnetic cores which causes the permeability of the core to change from the normal high value to a value near the permeability of air as the flux density in the core increases. Another way of stating this is that when the core saturates an increase in the current in the winding around the core results in only a very slight increase in the flux density in the core. Saturation is usually a phenomena that one is wishing to avoid, since the incremental inductance of the core decreases dramatically as the core saturates. If the core inductance is restricting current flow in the circuit, then this decrease in inductance could result in a catastrophic increase in the current. There are two types of saturation associated with cores – hard saturation, and soft saturation. Hard saturation refers to a rapid saturation – i.e. a small increase in the flux density results in a very rapid change in the permeability. Ferrites and steel laminations fall into this category. Soft saturation is where there is not a clearly defined saturation flux density, but instead the permeability changes gradually with increased flux density. MPP cores display this saturation characteristic. Remark 4.33 A core is said to be saturated if the current flow in the winding of the core has reduced its permeability to 20% of its permeability at very low currents. 4.3.3.3

Other Core Limitations

4.3.3.3.1 Curie Temperature This is the temperature where the core looses all its magnetic properties. When the core reaches that temperature the thermal agitation of the core domains is so severe that the domain alignment is destroyed, and hence the permeability of the material decreases. Once this starts then there is a form of positive feedback occurring, and the collapse of the field continues. As the field collapses the domains have less field to keep them aligned, and therefore the thermal agitation becomes even more dominant. For many of the magnetic core materials the Curie temperature is of the order of 200◦ C. This temperature is so high that the wire insulation and bobbin materials would be damaged it it were reached. Some inductors may not have a bobbin, and employ special high temperature wire insulation. In this case the Curie temperature could be an important limitation. 4.3.3.3.2 Core Losses Changing flux in any ferro-magnetic material results in losses in the material. These losses are in two different forms – Eddy current losses, and hysteresis losses. Eddy current losses are due to induced current in the core by the changing flux. These currents result in resistive losses. A general expression for Eddy current losses is [7]: ˆ 2 W/m2 p e = ke ω 2 B (4.39) where ke is a constant related to the particular type of material. The expression for hysteresis loss is [7]: ˆn ph = kh ω B

(4.40)

4.3 Introduction to Magnetics Design

4-33

where kh and n are empirical constant dependent on the type of material. Typical values of n are 1.5 < n < 2.5 for conventional lamination steel materials. Remark 4.34 Notice from (4.39) that the Eddy current loss is dependent in a squared sense on the applied frequency, whereas hysteresis loss in only linearly dependent on the frequency. Therefore it is very important to have a high resistivity for the core material in high frequency applications. The bonded type core materials such as ferrite, MPP, and iron powder to designed to achieve this. Let us assume that we have a magnetic structure, such as an inductor, that is driven by a sinusoidal voltage source. It is easy to show that the maximum flux density in the magnetic structure is: ˆ= B

V N Aω

(4.41)

where V , the amplitude of the sinusoidal voltage source, and ω , its frequency. N and A are the turns of the coil and area of the core respectively. ˆ is to be made Remark 4.35 One can immediately see from (4.41) that if B smaller, then N or A must be made bigger. Consider the situation where the power loss in the core of our magnetic structure is less than the total copper losses. Based on (4.39) and (4.40) we can see that we must increase the peak flux density experienced by the core, given that the excitation frequency is fixed, and the core dimensions are fixed. From Remark 4.35 one can deduce that this means that the number of turns wound onto the core must be decreased. This will result in a lower inductance for the core, and hence for a fixed supply voltage, a larger peak current. Therefore, even though the wire resistance would have dropped, the higher rms current into the core will result in higher copper losses.

4.3.4

Optimal Design Issues

It can be shown that minimum power loss is obtained in a combined electrical/magnetic structure if: • The core losses are equal to the copper losses. • The primary copper loss is equal to the secondary copper loss. Remark 4.36 The core losses equal to copper losses equality for minimum overall losses applies equally well to electrical machines as to inductors and transformers. Remark 4.37 Core losses equal to copper losses equality for minimum losses is analogous to the maximum power transfer theorem in circuit theory. You may recall that this theorem says that the load resistance should be equal to the source resistance for the maximum power to be transferred to the load from the source. Therefore, in this case one has the same losses in the source resistance and the load resistance.5 5 In the case of maximum power transfer one is trying to maximise the power. In electrical/magnetic systems the power is minimised.

4-34

Introduction to Practical Design of Switch Mode Power Supplies Assuming that one has a transformer type of structure, consider the following scenario. The power loss in the magnetics is less than that in the copper. Therefore, we wish to increase the power loss in the core and reduce the losses in the copper. The power losses in the core can be increased if the number of turns on the primary winding are decreased. This can be seen if we assume that the structure in being driven at a voltage source: v(t) = V sin ωt Z 1 v sin ωt dt (from Faraday’s Law) ∴ B(t) = NA V cos ωt = N Aω ˆ= V ⇒B N Aω

(4.42)

which is the same as the expression mentioned in (4.41). Remark 4.38 Equation (4.42) shows that the peak flux density in the core is increased if the number of turns in the coil are lowered. If the number of turns in the primary coil are lowered, then the length of the copper wire is lowered, and hence the wire resistance. If the turns in the primary is lowered, then the turns of the secondary are lowered to maintain the same turns ratio. If we maintain the same amount of copper under this condition, then we can increase the diameter of the wire, this again decreasing the resistance of the primary and secondary windings. These two effects mean that the overall losses of the secondary will be reduced, since maintaining the same turns ratio meaning that the secondary current would not change.6 One can mount a similar argument if the losses in the core are larger than the copper losses. In this case the turns on the primary are increased. To help keep the primary and secondary winding losses approximately the same one should allocate similar area to the primary and secondary windings. If the secondary has more turns, it must have proportionately smaller wire. If there are multiple secondaries, allocate their winding area by output power (higher getting more winding area). If one is designing an inductor, then the magnetic losses can be traded off against the copper losses by adjusting the cross-section of the core. For example, if the magnetic losses are low, then they can be increased by decreasing the core cross-section and therefore increasing the flux density. The total losses in the core are related to the losses per unit volume, and of course the volume of the core. If the cross-sectional area is decreased then the core volume drops in proportion to the decrease. The flux density increases in proportion to the decreased area. However, the total losses will increase since the losses per unit volume are related to the peak flux density squared. Example 4.1 Assume that the core cross-section of the typical transformer core has been halved. This will mean that the volume of the core has been halved. The result of the area increase, assuming that the mmf is the same and the core is 6 Note that in this discussion we are assuming that the losses in the primary due to the magnetising current can be neglected. The losses due to this component of the current actually increase with the reduction in the number of turns of the primary.

4.3 Introduction to Magnetics Design

4-35

not saturated, is that the peak flux density will double. The Eddy current losses ˆ 2 , therefore the losses per unit per unit volume in the core are proportional to B volume increase by 4. The total losses would therefore by 1/2 × 4 = 2 times those before the change in core area.

4.3.5

Design of an Inductor

In this section we shall proceed through the practical design of an inductor. The reason for this is that this is the simplest magnetic structure that is useful in a SMPS design. For example, inductors are required in the buck converter for the output filter. In the following design we shall be referring to graphs from [8, 9], which is a data manual and selection guide for products by Ferroxcube, formerly Philips. The specifications for the inductor are shown in Table 4.4.

Parameter

Specification

Inductance DC current Max power dissipation Operation frequency Average voltage

35µH 2 Amp 300mW 250kHz 10V

Table 4.4: Inductor specifications. From Table 4.4 we need to calculate a few other values that will aid in the selection of a core material. We know from the maximum power dissipation specification that: R
βt_off where the parameter βt_off is the turn off gain given by: βt_off =

α2 α1 + α2 − 1

(5.5)

Remark 5.6 From (5.4) one can see that the βt_off value should be as large as possible to keep the i0G value as small as possible. This implies that α2 → 1 and α1 should be small. Therefore the semiconductor regions in the GTO are designed to achieve this objective. 5.2.3.1

Snubbers and GTO Thyristors

Consider the circuit shown in Figure 5.11. This is a step down converter using a GTO and the switching element. There are several points that should be noted about this diagram: • The circuit symbol for the GTO (as compared to that of the thyristor). • The Ls_on inductor and associated parallel resistor and diode form a turnon snubber3 circuit. • The Cs_off capacitor,associated resistor Rs_off , and diode Ds_off , form a turn-off snubber circuit. The Lσ inductance is an unwanted parasitic inductance. turn-on snubber The turn-on snubber is required to protect the GTO from the large currents that can flow through it because of the reverse recovery of the freewheeling diode Df w , which is usually a slow device at the power levels that GTOs are used at. The presence of the series inductance Ls_on limits that rate of rise of the current through the GTO. The resistor and diode components that are in parallel with Ls_on are to dissipate the energy stored in Ls_on when the GTO is turned off. These should be designed so that the energy in the inductor is dissipated before the next turn on of the GTO. When the GTO is turned off the voltage across the device would go to Vd almost instantaneously without the presence of a turn-off snubber. If the dv/dt across the device is too large then it will turn on, as was the case for the thyristor. The purpose of the snubber is to ensure that this cannot occur, since the voltage across Cs_off cannot change instantaneously.

5-16

Introduction to High Power Converter Technology

Load current

D fw

iL

Turn-on snubber

Rs_on

Vd

Cd

+

Parasitic inductance

Ls_on D s_on

Ls

D s_off

Rs_off

GTO

+

C s_off

Turn-off snubber Figure 5.11: An example of a dc chopper circuit using a GTO thyristor

5.2 Review of Power Semiconductor Devices Remark 5.7 The use of a turn-off snubber with the GTO is absolutely essential. If the device is turned on prior to all the internal stored charge being dissipated, then there is a very poor distribution of the turn-on current, resulting in local heating and possible destruction of the device. This occurs because of the particular internal construction of the GTO. The presence of the turn-off snubber prevents the “automatic” re-turn-on of the device when the voltage rises across it too quickly. 5.2.3.2

GTO Turn-on

We shall briefly look at what is required to turn on a GTO. Consider Figure 5.12. The turn-on is instigated by a pulse of gate current. The diG /dt and the peak iG should be large so that the device turns on rapidly and the current distributed evenly in the device. The gate pulse should last of the order of 10µ seconds or so to ensure that the turn-on process is complete. After this period a small gate current should be maintained to ensure that the device does not turn off again under low anode current conditions.4 This current is often known as the “back-porch” current. The other point to note in Figure 5.12 is the effect of the series inductance Ls_on on the anode current during turn-on. Notice that diA /dt is limited by this inductance so that the current is distribute evenly across the device, and the voltage across the device is shared with the inductor during turn-on. This inductor also stops the otherwise large reverse recovery currents in the circuit due to the recovery characteristic of the freewheeling diodes. The reverse recovery actually results in the current overshoot represented by the overshoot during turn-on. 5.2.3.3

GTO Turn-off

Next we briefly consider the turn-off waveforms for the GTO. It should be noted that the effect of the snubbers cannot be ignored for the GTO, since it is essential that they are used under normal operation (as mentioned in Remark 5.7). In order to turn the GTO off then the gate current must be negative. The magnitude of this current is approximately 1/5 to 1/3 of the anode current being turned off. Therefore in high power applications this current can be substantial in magnitude. Fortunately the duration of the current is short. Figure 5.13 shows the waveforms during turn-off. The negative diG /dt should be kept large, but it should not be made too large or undesirable tail currents occur in the anode current, and there is the possibility of device destruction. Therefore the diG /dt should be kept within the specifications supplied by the device manufacturer. The diG /dt value can be controlled by the design of the inductance in the gate drive circuit and the negative voltage applied to turn-off the device. During the time interval t1 , the growing negative gate current is removing charge stored in the two regions of the device. When enough of this is removed 3 A snubber circuit is an auxiliary circuit that is designed to protect the main switching element from excessive current or voltages. 4 This unwanted turn-off condition could also damage the device due to uneven distribution of the current in the device if there is a sudden increase in anode current.

5-17 turn-off snubber

5-18

Introduction to High Power Converter Technology

iG

t w1

“Backporch” current iGT t

0 iA td

0

t

v AK

0

t

vGK

0

t

Figure 5.12: Turn on waveforms for a GTO thyristor.

5.2 Review of Power Semiconductor Devices

iG

5-19

iGT

t

0

iA

t tail

t4

io

t

0 v AK t2 t1

dv dv < dt dt

Vd max

t

0 vGK

Inductive spike due to parasitic L in the snubber circuit. t

0 t3

vGG-

Figure 5.13: Turn-off waveforms for a GTO thyristor.

5-20

Introduction to High Power Converter Technology the regenerative action is stopped, and the device starts to turn-off (i.e. the anode current begins to fall). The growing difference between the anode current and the constant load current io flows into the snubber capacitor. There is a rapid rise of the voltage across the GTO due to the parasitic inductance of the snubber circuitry (this stray inductance has to be kept to the absolute minimum to kept this voltage small). After time t2 enough carriers have been swept out of the device for the gate-cathode junction to regain its reverse blocking capability. As the gate-cathode junction recovers it reverse blocking capability, the voltage across it starts to go negative, and the negative gate current starts to decrease. The inductance in the gate circuit tries to keep the gate current constant, and this results in avalanche breakdown of the gate-cathode junction during the time t3 – i.e. the gate-cathode junction is operating as a zener diode. This breakdown serves to remove further minority charge from the device. The t3 interval should be kept below a manufacturer specified value to prevent destruction of the gate-cathode junction. After the t3 period there is a continuation of anode current flow as the final stored charge is removed from the device. This is known as the anode tail current, and flows for time ttail . During this time the voltage across the device is growing at the rate of: io dvAK ≈ (5.6) dt Cs

GTO minimum on and off times

turn-off failure under short circuit conditions

and contributes a lot to the turn-off losses in the device. Remark 5.8 A GTO should not be turned on too soon after it has been turned off because of the potential for poor current sharing in the device due to residual charge storage. The same applies for turn-off after turn-on. Remark 5.9 If the anode current becomes too large there is the possibility that the gate current may not be able to turn the device off (there is a limit to the magnitude of the gate current, determined by the semiconductor properties of the device). This is a particular problem under short circuit conditions, since this is an abnormal condition that would not be designed for. Remark 5.10 Over-current protection can be achieved by using a “crowbar” to blow the fuse in the circuit if the current becomes too large. This concept is shown in Figure 5.14. The SCR across the dc link is fired, resulting in a short circuit on the link, and consequently the fuse will blow and protect the circuit. If the GTOs are used in an inverter structure then all the devices in the inverter can be fired simultaneously to carry out the same function. It should be noted that in Figure 5.14 we have not included the turn-on snubber. It is this snubber that gives the SCR the extra time to turn-on prior to the GTO destroying itself. Remark 5.11 One problem with the crowbar protection technique is that the presence of a fuse in the dc link introduces inductance in this part of the circuit. This can result in significant over-voltages when the main GTO is turned off.

Remark 5.12 There are several variants to the classical GTO that are being championed by different manufacturers. For example, Asea-Brown-Boveri

5.2 Review of Power Semiconductor Devices

Crowbar SCR

5-21

Short circuit

Fuse

Load

Figure 5.14: GTO thyristor circuit with additional “crowbar” SCR (ABB) has the IGCT - the Integrated Gate Commutated Thyristor. This is essentially a modified GTO with tightly coupled gate drive circuitry built onto a card with the GTO power device. It is a high power device – 4.5kV and 3kA. The onboard GTO has low conduction losses and does not require a turn-off snubber. The better gating allows higher switching frequencies as compared to standard GTOs (of the order of 1000Hz). Rockwell/Allen-Bradley have a similar device called the SGCT – the Symmetrical Gate Commutated Thyristor.

5.2.4

Insulated Gate Bipolar Transistors (IGBTs)

One of the more recent devices that has become pervasive in the lower to medium power area is the IGBT – the Insulated Gate Bipolar Transistor. This device is essentially a specialise MOSFET – in fact the input is a MOSFET input. The main advantage of these devices is that they can be easily turned off by controlling the devices gate, but unlike the GTO this turn-off process does not require large currents. The basic structure of the n-channel IGBT5 is shown in Figure 5.15. One can see that the structure of the device is nearly identical to the MOSFET, the only major difference being the presence of the p+ injection layer. It is the presence of this layer that results in the injection of minority carriers into the device, and leads to the operation of the device being something like a MOSFET fed bipolar transistor. The advantages of the device are: • The result of the injection of minority carriers in the device is that it can carry much larger currents as compared to the MOSFET, since the current is carried in more than the channel of the device. • The presence of a lengthy diode junction in the device allows it to have a significantly larger forward blocking voltage as compared to the MOSFET. • The injection of carriers into the device means that the on-state losses for this device are lower than those of a comparable power MOSFET. 5 The

layer types are all reversed for a p-channel device

5-22

Introduction to High Power Converter Technology Remark 5.13 One could consider the IGBT to be a “super” MOSFET. In many IGBTs the MOSFET part of the device carries the majority (up to 90%) of the current in the device (this is to help prevent a large amount of minority carrier storage from occurring, which slows down the turn-off of the device).

Source

Gate

SiO2

SiO2 n

+

n

+

Body region

p

J1 J2

Ls J1

n

-

n+

Drain drift region Buffer layer

p+

Injecting layer Parasitic SCR Drain

Figure 5.15: A schematic diagram of the basic structure of the IGBT. The n+ layer between the p+ drain layer and the n− drift region is not essential for the operation of the device. As with the diode considered earlier, one can have punch-through and non-punch-through IGBTs. The n+ layer is required for the punch-through devices to prevent the J2 space charge region from going all the way to the p+ drain region. The presence of the n+ layer can significantly improve the operation of the IGBT. Remark 5.14 In Figure 5.15 there is a parasitic SCR shown. This is an undesirable feature of the structure, and design efforts must be made to ensure that the loop gain of the SCR is not greater than one so it does not turn on. The circuit symbol for the IGBT appears in Figure 5.16(c) and (d). Note that the symbol in (c) is very nearly the same as that for the n-channel MOSFET, except that there is an arrow on the drain connection indicating the direction of the current due to the injection of carriers here. Figure 5.16(d) shows a symbol that is emphasising the similarity of IGBT with the NPN bipolar transistor.

5.2.4.1

IGBT Operation

We shall briefly consider the salient points of IGBT operation. The following discussion is with reference to Figure 5.17.

5.2 Review of Power Semiconductor Devices

5-23

iD

Increasing vGS

v RM v DS

v DS brk

(a) » 0.7 V

iD

Drain Drain Gate

Gate

Source vGS th

vGS

Source (c)

(d)

(b)

Figure 5.16: The IGBT voltage and current transfer characteristics and circuit symbol: (a) output characteristic; (b) transfer characteristic; (c) and (d) nchannel IGBT circuit symbols.

5-24

Introduction to High Power Converter Technology Figure 5.17(a) shows the current flows in the device when it is turned on. When the gate voltage exceeds the threshold voltage an inversion layer forms beneath the gate of the IGBT. This channel shorts the n+ to the n− layer, as occurs in the MOSFET. The current flow through this channel also results in holes being injected from the p+ region into the n− region. These holes move across the n− drift region via drift and diffusion via a number of paths. These carriers reach the p body region (not necessarily where the channel is) and then are swept through to the source via recombination at the source metallisation. The junction of the n− region and the p region is called the collector region, since is operates the same as the collector region in a thick PNP transistor. The connection between the layers and parasitic transistors is shown in Figure 5.17(b). Notice that the injection layer, denoted as the p+ layer, acts as an emitter in a BJT transistor, emitting or injecting holes into the n− base region of the device. As current flow through the IGBT there are voltage drops in the device due to the bulk resistance of the semiconductor materials used. These are shown in Figure 5.17 as dashed resistors. These resistance values are important for two different reasons; (i) if the resistances are too high then the device will dissipate more power; and (ii) if the voltage drops are too high in the resistances then parasitic thyristor in the IGBT may turn on. Figure 5.18(a) and (b) shown an equivalent circuit for the IGBT. Figure 5.18(b) is more complete, showing the parasitic thyristor, and the body spreading resistance. If the body spreading resistance is too high then the current gain of the thyristor may become greater than one, and consequently the thyristor will turn on. Once this happens then the device no longer behaves as an IGBT, and power must be remove across the device to turn it off. Needless to say, much design effort has gone into ensuring that the parasitic IGBT does not turn on.

5.2.4.2

IGBT Turn-on

Typical turn-on waveforms for the IGBT are shown in Figure 5.19. These waveforms are very similar to those for a power MOSFET.6 We are assuming that the voltage to the input of the IGBT circuit is the voltage waveform vGG . The voltage across the gate-source of the IGBT is vGS . Note from Figure 5.19 that this voltage is essentially an exponential, due to the input capacitance of the IGBT, coupled with the gate resistor (which is to limit the current flowing into the gate of the IGBT to safe levels). The time period td(on) is the time required for vGS to reach a voltage where the device starts to turn on. From this point the current through the device rises as it starts to turn on harder. Eventually vDS is of the order of vGS and the current stabilises at a value determined by the external circuit. As vDS starts to fall a significant amount of current starts to flow through the Cgd capacitance. This is due to the fact that there is a changing voltage across the capacitor, and that the value of the capacitance increases considerably as the space charge region width decreases (effectively decreasing the plate separation in a parallel plate capacitor) and the stored charge in the device starts 6 Note that the waveforms for turn-on and turn-off are for the IGBT in a step down chopper circuit of the type shown in Figure 5.11, except that the main power device has been replaced by the IGBT and there are no snubbers.

5.2 Review of Power Semiconductor Devices to increase. Consequently the rise of vGS flattens out as this capacitance is charged, this being the result of the extra current being drawn through the gate resistor. Eventually vGS restarts its exponential rise again when vDS ≈ vGS , stopping when its value reaches vGG . The vDS waveform during the tf v2 time in Figure 5.19 is usually observed in IGBTs. It is due to two effects – the above-mentioned increase in Cgd as vDS falls (which also occurs in power MOSFETs), and the slower turn-on of the PNP section the IGBT (as compared to the MOSFET portion), which delays the associated conductivity modulation due to the injected carriers. 5.2.4.3

IGBT Turn-off

The waveforms for the turn-off of the IGBT are shown in Figure 5.20. The rise in the voltage vDS before iD drops is typical of all step down converter circuits. This occurs because the load is considered to be effectively a current source, and therefore it continues to supply current into the switch device until the voltage on the switch side of the load reaches the supply. At this point the diode across the load will start to turn on and take the load current. The initial part of the vGS turn-off transient, td(off) , occurs because of the time constant associated with the RG (Cgd2 +Cgs ) time constant of the MOSFET part of the IGBT.7 As the drain-source voltage vDS starts to rise, the Miller effect of Cgd2 starts to take effect. This temporary arrests the decrease of vGS during the interval trv . When vDS stabilises then this effect stops. The decrease of vGS now continues, but with a time constant of RG (Cgd1 + Cgs ), which is smaller than previously due to the change on the value of Cgd caused by the widening of the space charge region in the device. During all the phase so-far the IGBT is behaving as a MOSFET. The major difference between the IGBT turn-off and the power MOSFET turn-off is observed in the drain current waveform which has two distinct time intervals. During the tf i1 time the MOSFET is turning off. The second time interval tf i2 is due to the stored charge in the n− region of the device. Since the MOSFET is off there is no way that these carriers can be swept out of the device by a negative drain current. Consequently these carriers diminish by recombination. The punch-through IGBT attempts to minimise this effect by having a small carrier lifetime in the n+ region. This results in an electron concentration gradient from the n− region to the n+ region, thereby sweeping the electrons from the device.8 The non-punch-through IGBT attempts to minimise the tail off current by redesigning the IGBT so that the majority of the current is carried by the MOSFET. This minimises the stored charge. At the time of writing these notes IGBTs are in a rapid state of development. Currently the most advanced devices are capable of withstanding approximately 6kV, and can conduct several thousand amperes. The turn-off times for these devices are of the order of 1µsec of less. For medium power systems IGBTs are currently the device of choice. 7 R is the gate resistor that is included in the circuit to limit the gate currents to reasonable G levels. 8 It is desirable to have long carrier life times in the n− region so that the bulk resistance is kept low in this region when the device is on.

5-25

5-26

Introduction to High Power Converter Technology

5.2.5

Other Devices and Developments

Thus far we have concentrated on the devices that are the most important ones in terms of current practice. However there is also significant work going on into new devices that still have not reached the commercial stage. We shall briefly mention some of these. 5.2.5.1

Power Junction Field Effect Transistors

This device is also sometimes known as the static induction transistor (SIT). It is effectively a JFET transistor with geometry changes to allow the device to withstand high voltages and conduct high currents. The current capability is achieved by paralleling up thousands of basic JFET cells. The main problem with the power JFET is that it is a normally on device. This is not good from a start-up viewpoint, since the device can conduct until the control circuitry begins to operate. Some devices are commercially available, but they have not found widespread usage. 5.2.5.2

Field Controlled Thyristor

This device is essentially a modification of the SIT. The drain of the SIT is modified by changing it into an injecting contact. This is achieved by making it a pn junction. The drain of the device now becomes the anode, and the source of the SIT becomes the cathode. In operation the device is very similar to the JFET, the main difference being quantitative – the FCT can carry much larger currents for the same on-state voltage. The injection of the minority carriers in the device means that there is conductivity modulation and lower on-state resistance. The device also blocks for reverse voltages due to the presence of the pn junction. 5.2.5.3

MOS-Controlled Thyristors

The MOS-controlled thyristor (MCT) is a relatively new device which is available commercially. Unfortunately, despite a lot of hype at the time of its introduction, it has not achieved its potential. This has been largely due to fabrication problems with the device, which has resulted on low yields. Figure 5.21 is an equivalent circuit of the device, and its circuit symbol. From Figure 5.21 one can see that the device is turned on by the ON-FET, and turned off by the OFF-FET. The main current carrying element of the device is the thyristor. To turn the device on a negative voltage relative to the cathode of the device is applied to the gate of the ON-FET. As a result this FET turns on, supplying current to the base of the bottom transistor of the SCR. Consequently the SCR turns on. To turn off the device, a positive voltage is applied to the gate. This causes the ON-FET to turn off, and the OFF-FET to turn on. The result is that the base-emitter junction of the top transistor of the SCR is shorted, and because vBE drops to zero. volt it turns off. Consequently the regeneration process that causes the SCR latching is interrupted and the device turns off.

5.2 Review of Power Semiconductor Devices The P-MCT is given this name because the cathode is connected to P type material. One can also construct an N-MCT, where the cathode is connected to N type material. 5.2.5.4

New Semiconductor Materials

Silicon is presently the only material that is widely used for the fabrication of the power semiconductors (and integrated circuits for that matter). The reason for this is the ease with which large and very pure crystals can be grown with Silicon. However, there are other materials that have superior properties as compared to Silicon, especially in high power/high voltage applications. Gallium Arsenide (GaAs) is a well used material, especially in high frequency applications, where its very high carrier mobility allows higher frequency devices to be constructed. In addition it has a higher band-gap than Silicon, which means that it can support higher voltages than Silicon, and can be operated at higher temperatures (460C and compared to 300C for Si). Silicon Carbide is a material which is currently attracting a lot of research. It has a significantly larger band-gap than Si (2.9eV as compared to 1.12ev for Si), has excellent thermal conductivity (approximately 3 times that of Si), and can operate at temperatures of 600C, with a maximum operating temperature of 1240C. The breakdown electric field strength is approximately 10 times that of Si, meaning that it can withstand significantly higher voltages. SiC devices are probably on 3 to 5 years from commercialisation. Diamond is the ideal material for power semiconductors. It can operate at very high temperatures (similar to SiC), it can withstand fields approximately 100 times larger than Si, it has thermal conductivity 5 times larger than SiC (and therefore 15 times larger than Si), and it has electron mobility approximately twice that of Si. Unfortunately there is much research to be done before we see commercial diamond based power electronic devices (15-30 years). One can see that there are many exciting developments occurring in the area of power electronic devices. These new devices then open up new applications, that previously were not feasible.

5-27

5-28

Introduction to High Power Converter Technology

Source

Gate Channel

i

SiO2

SiO2

-

n

+

n

+

-

p

Drift region resistance

nn+

p

+ + + +

+

i

Drain

+ + + +

}

Minority carrier injection

}

Collector region

}

Minority carrier injection

Lateral body spreading resistance

(a) Source

Gate

i

SiO2

SiO2 n

+

n

p

+

nn+

p

+

i

Drain (b)

Figure 5.17: Current flows in the IGBT.

5.2 Review of Power Semiconductor Devices

Drift region resistance

Gate

5-29

Drift region resistance

Drain

Drain

Gate

Source Source

(a)

Body region spreading resistance

(b)

Figure 5.18: Equivalent circuits for the IGBT: (a) approximate equivalent circuit for normal operating conditions; (b) more complete equivalent circuit showing the parasitic thyristor.

5-30

Introduction to High Power Converter Technology

vGS / vGG

vGG

vGS

t

0 iD

td(on)

Io

t t ri

v DS Vd

v DS (on)

t t fv1

t fv 2

C gd

Rg

v DS vGG

vGS

Definitions

C gs

Figure 5.19: Typical turn-on waveforms for an IGBT.

5.2 Review of Power Semiconductor Devices

vGS / vGG

5-31

vGG

vGG vGS ,I

vGS

o

vGS(th)

t

0 iD

Io

td(off)

t fi 2

}

MOSFET current

}

BJT current

0 t rv

t

t fi1

v DS Vd

t

0

Figure 5.20: Turn-off waveforms for an IGBT.

Anode A Gate G

OFF-FET K ON-FET Cathode Figure 5.21: Schematic and circuit symbol for the P-MCT.

5-32

Introduction to High Power Converter Technology

Chapter 6

Line Frequency Uncontrolled Rectifiers 6.1

Introduction

The power input into most power electronic devices is derived from 50/60Hz ac sine wave supplies provided by the electricity authorities. This supply generally is converted into a dc supply before being used or converted into another form. The traditional and simplest way of achieving the ac–dc conversion is via an uncontrolled rectifier based on diodes. Such rectifiers only allow power to flow from the ac to the dc side. The vast majority of power electronic applications currently use such rectifiers to do the ac–dc conversion, although this situation may change in the future due to mains harmonic requirements (which are difficult to meet using conventional rectifiers). This chapter shall look at the basic operation single phase and three phase uncontrolled rectifiers. Some analysis will be carried out (based on the assumption of ideal diodes) to ascertain the harmonic performance of the various rectifiers. Before doing this there is some concepts that we will need to introduce.

6.2

Some Mathematical Preliminaries

One of the characteristics of diode rectifier circuits is that the produce nonsinusoidal currents in the ac mains. Therefore consideration of non-sinusoidal waveforms is relevant to carrying out analysis of these types of circuits. Much of the analysis is carried out assuming that the circuits are in steady state, and then calculating the Fourier components in the current (and in some cases the voltage) waveforms. We shall therefore quickly review Fourier analysis as applicable to power electronic waveforms.

6-2

Line Frequency Uncontrolled Rectifiers

6.2.1

Fourier Analysis of Repetitive Waveforms

In general, a non-sinusoidal waveform, f (t), which repeats with an angular frequency of ω, can be expressed as [13]: f (t) = F0 +

∞ X n=1

fn (t) =

∞ X 1 a0 + {an cos(nωt) + bn sin(nωt)} 2 n=1

(6.1)

where F0 = 21 a0 corresponds to the average value of the waveform (or the dc component), and the coefficients in (6.1) are: Z 1 2π f (t) cos(nωt) d(ωt) (6.2) an = π 0 Z 1 2π bn = f (t) sin(nωt) d(ωt) (6.3) π 0 Note that the F0 term is calculated if the harmonic number starts from 0 instead of 1 – i.e.: Z 2π Z 1 1 1 T F0 = a0 = f (t)d(ωt) = f (t)dt (6.4) 2 2π 0 T 0 which is the average value of f (t) as noted previously. Each component of the waveform can therefore be written as: fn (t) = an cos(nωt) + bn sin(nωt) which can be simplified using the following trigonometric identity: p A cos θ + B sin θ = A2 + B 2 cos(θ ± φ)

(6.5)

(6.6)

∓B A.

where tan φ = Since via (6.6) equation (6.5) can be written as a cos function, then we can eliminate the frequency component of the waveform and write the expression as a phasor: → − F n = Fn ejφn (6.7) where: p a2n + b2n √ Fn = 2 (−bn ) tan φn = an

(6.8) (6.9)

In many situations in power electronics the waveforms do not have a dc component. This coupled with the symmetry that is present can considerably simplify the generation of the Fourier coefficients. These are shown in Table 6.1 for several of the common symmetries. If the definition of the rms value1 of a waveform f (t) is applied to the function when expressed in terms of its Fourier components, it can be easily shown that the rms amplitude is: v u ∞ X u Fn2 F = tF02 + (6.10) n=1 1 Definition

of the rms value of a quantity is xrms =

q

1 T

RT 0

x(t)2 dt.

6.2 Some Mathematical Preliminaries Symmetry Even Odd Half-wave

Condition Required f (−t) = f (t) f (−t) = −f (t) f (t) = −f (t + 21 T )

Even quarter-wave

Even and half-wave

Odd quarter-wave

Odd and half-wave

6-3 FourierR Coefficients π an = π2 0 f (t) cos(nωt) d(ωt) bn = 0 Rπ an = 0 bn = π2 0 f (t) sin(nωt) d(ωt) an = bnR= 0 for even n π an = π2 R 0 f (t) cos(nωt) d(ωt) for odd n 2 π bn = π 0 f (t) sin(nωt) d(ωt) for odd n  R π/2 4 f (t) cos(nωt) d(ωt) for odd n π 0 an = 0 for even n bn = 0 for all n an = 0 for all n  R π/2 4 f (t) sin(nωt) d(ωt) for odd n π 0 bn = 0 for even n

Table 6.1: Fourier coefficient formulae with symmetry.

6.2.1.1

Measures of Waveform Distortion

Consider Figure 6.1 which shows the voltage and current waveforms in a situation where a power electronic device is connected to the grid supply [2]. The current waveform shows significant distortion.2 The voltage on the other hand is shown without distortion, since it usually does not display the same amount of distortion as the current. This is the case because the voltage distortion arises from the current causing a voltage drop across the line impedances.3

vs

v, i

is is1 i dis

0

wt

f1

Figure 6.1: Line current waveform distortion. Let us assume that the supply voltage can be represented as: vs (t) =

√

2Vs sin ω1 t

(6.11)

2 The distortion in this current waveform is typical of that one would expect from a diode rectifier connected to the grid. 3 The undistorted voltage assumption makes the analysis simpler in this section.

6-4

Line Frequency Uncontrolled Rectifiers The input current is represented by its Fourier components: is (t) = is1 (t) +

∞ X

isn (t)

(6.12)

n6=1

where: is1 , the fundamental line current isn , the harmonic components of the line current We can write (6.12) in an expanded form as follows: is (t) =

√

2Is1 sin(ω1 t − φ1 ) +

∞ X √

2Isn sin(ωn t − φn )

(6.13)

n6=1

where: φ1 , the phase angle of the fundamental

(6.14)

ωn = nω1

(6.15)

ωn t = nω1 t = nθ1

(6.16)

∴ φn = nφ1

(6.17)

Is , Isn , rms value of the relevant harmonic

(6.18)

The rms value of the current can be calculated using the general expression noted in footnote 1. If expression (6.12) is substituted into this, the crossproduct terms all integrate to zero due to the orthogonality property of cos and sin functions. The rms current therefore becomes: v u ∞ X u 2 2 Isn (6.19) + Is = tIs1 n6=1

total harmonic distortion

The total distortion of waveforms in general is usually measured by a parameter called the total harmonic distortion, which is abbreviated as the THD. The distorted component of the current is essentially all the components of the current except the fundamental component. Therefore using the time domain expressions for the currents we can write the distortion component as: idis (t) = is (t) − is1 (t) =

∞ X

isn (t)

(6.20)

n6=1

This current is shown schematically in Figure 6.1. Therefore, using (6.19), the rms value of the distortion section of the current can be written as: v uX q u∞ 2 2 2 Idis = Is − Is1 = t Isn (6.21) n6=1

6.2 Some Mathematical Preliminaries

6-5

The THD of the current defined as: Idis I ps1 2 Is2 − Is1 = 100 × I v s1 2 uX ∞  u Isn = 100 × t Is1

%THD = 100 ×

(6.22) (6.23) (6.24)

n6=1

6.2.1.2

Power and Power Factor

Clearly the purpose of a power electronic system is to convert electrical energy in different ways to allow energy (or power) to be effectively and efficiently used. Therefore it is relevant to briefly review the concept of power, and then to look at a generalisation of the concept of power factor to systems with non-sinusoidal waveforms. Let us begin with single phase power expressions. Consider the following time domain expressions for current and voltage flowing into some arbitrary network: v = V cos ωt

(6.25)

i = I cos(ωt + θ)

(6.26)

Using the definition of instantaneous power we can write: P = vi

(6.27)

= [V cos ωt][I cos(ωt + θ)]

(6.28)

= V I cos ωt[cos ωt cos θ − sin ωt sin θ]

(6.29)

2

= V I cos ωt cos θ − V I cos ωt sin ωt sin θ 1 Using cos2 ωt = [1 + cos 2ωt] one can write 2 V I cos θ P = [1 + cos 2ωt] − V I sin θ cos ωt sin ωt 2

(6.30) (6.31) (6.32)

Using the trig relation: cos ωt sin ωt =

1 sin 2ωt 2

we can modify the last term of (6.32) as follows: V I cos θ VI [1 + cos 2ωt] − sin 2ωt sin θ 2 2 VI VI VI = cos θ + cos θ cos 2ωt − sin θ sin 2ωt 2 2 2

P =

(6.33) (6.34)

Using cos(x + y) = cos x cos y − sin x sin y, this can be written as P =

V I cos θ 2 } | {z

Average Real power

+

VI cos(2ωt + θ) |2 {z }

Oscillatory component

(6.35)

6-6

complex power

Line Frequency Uncontrolled Rectifiers The oscillatory power component represents the power flowing into and out of the storage element of the particular circuit.4 The average real power component essentially causes an offset in this oscillation component so that there is an average value of power over a complete cycle. The other way of representing the power expression for sinusoidal steady state systems is in the form of the complex power: → − → −→ − S =V I∗

(6.36)

− where ‘∗’ represents the complex conjugate, and the → x means that x is a phasor. Let us assume that: → − V = Vrms ejα → − I = Irms ejβ

(6.37) (6.38)

where Irms and Vrms represent the current and voltage RMS values. Substituting (6.38) and (6.37) into (6.36) we can write: → − S = Vrms Irms cos θ + jVrms Irms sin θ

(6.39)

where θ = α − β.5 Equation (6.39) is broken up into two components: P = Vrms Irms cos θ

(6.40)

Q = Vrms Irms sin θ

(6.41)

One can see the vector relationship of these components in Figure 6.2. Notice that the use of the complex conjugate in the complex power expression means that the angle used is effectively the angle of the voltage phasor with respect to the current, despite the fact that the convention is that the currents phase is measured relative to the voltage.6 Imag Q = VI sin θ r I P = VI cos θ

r V θ

α β

I cos θ

Real

I sin θ

Figure 6.2: Phasor relationship for complex power. 4 As we shall see later this component consists of two different parts, one belonging to the real power and the other to the imaginary power. 5 The angle θ is the angle from the current vector to the voltage vector. → − →− → 6 It is possible to define complex power as − S = I V ∗ . In this case the angle is the current with respect to the voltage in the power expression. The meaning of the sign of the complex power changes with this definition.

6.2 Some Mathematical Preliminaries

6-7

The correspondence between (D.8) and the average real power component of (6.35) is easy to see. However, the correspondence between (D.9) and the oscillatory power part of (6.35) is not immediately obvious. Clearly Q is related the component of the voltage that is orthogonal (in a temporal sense) to the current, multiplied by that current. This correspondence is more easily seen from (6.34): P =

V I cos θ V I cos θ + cos 2ωt − {z 2 } | 2 Real power component

V I sin θ sin 2ωt } | 2 {z

(6.42)

Reactive power component

where V and I are the peak values of the voltage and current. We can see from this expression that the real power actually oscillates (with the oscillation being unipolar), and has an average value of (V I/2) cos θ. The reactive power component on the other hand does not have an offset term and its average value is zero. The amplitude of this term is equal to the Q term in the complex power expression. Therefore the reactive power component corresponds to power that is flowing into the circuit and out again per half cycle of the fundamental voltage (or current). These components are shown in Figure 6.3 for a phase angle of 30◦ . This plot is of the normalised power, the normalisation factor being Vrms Irms . Notice the reactive power component has no average dc component. 2 Real power

1.5

Total power

Normalised power

Average power

1

Reactive power

0.5

0

-0.5 0

1

2

3

4

5

6

7

q [rad]

Figure 6.3: Diagram of the normalised single phase power components with a 30◦ phase angle – the power is normalised by dividing by Vrms Irms . Remark 6.1 The presence of reactive power is generally undesirable because it contributes to the current in the circuit (and therefore the size of the conductors required) without carrying any average power to the load.

6-8

Line Frequency Uncontrolled Rectifiers Remark 6.2 With an inductive load the current lags the voltage (or the voltage leads the current). Therefore in the complex power expression the angle θ is positive, and consequently Q is positive. Therefore an inductive load absorbs reactive power, which is given the units of VARs (Volt Ampere Reactive). This is called absorbing lagging VARs. Conversely, a capacitive load results in the current leading the voltage (or the voltage lags the current). Therefore in this case the θ angle is negative, and therefore a capacitive load draws negative VARs from the supply (called leading VARs). It can also be said that the capacitor supplies positive VARs to the supply.

three phase real and reactive power

Let us now briefly consider the concept of three phase real and reactive power. We shall assume that the phase currents and voltages in a star connected system are:7  va = V cos ωt     ) vb = V cos(ωt + 2π  3   2π vc = V cos(ωt − 3 ) (6.43) ia = I cos(ωt + θ)     ib = I cos(ωt + 2π 3 + θ)    2π ic = I cos(ωt − 3 + θ) These voltages and currents can be multiplied together to give the three phase power expression: P = va ia + vb ib + vc ic 2π 2π 3V I cos θ V I cos θ + (cos 2ωt + cos(2ωt − ) + cos(2ωt + )) = 2 2 3 3 V I sin θ 2π 2π − (sin 2ωt + sin(2ωt − ) + sin(2ωt + )) (6.44) 2 3 3 Terms two and three in (D.12) are zero because the cosine and sine terms each add to be zero. Therefore the power expression becomes: P =

3V I cos θ 2

(6.45)

which is simply three times the average power in (D.10) (as one would expect). Remark 6.3 The interesting aspect about the three phase real power is that it is constant – i.e. the total real power flowing into a three phase system is constant despite the fact that the individual powers in the phase are oscillating. Let us consider the last part of (D.12). Rewriting this term one can see that:   V I sin θ V I sin θ 2π 2π sin 2ωt = sin(2ωt − ) + sin(2ωt + ) (6.46) − 2 2 3 3 which means that the reactive power in one phase is being absorbed by two other phases. Therefore the reactive power is cycling around between the three phases, and hence is not seen on the external three phase power (although there is obviously still the single phase reactive power there in each of the individual 7 The

star connection means that there are no zero sequence currents flowing.

6.2 Some Mathematical Preliminaries

6-9

phases). The reactive power of three phase systems is considered to be the reactive power of an individual phase, whereas the real power of a three phase system is three times the real power of an individual phase. Now that we have consider the concepts of real and reactive power for single and three phase systems, let use now revise the concept of power factor for sinusoidal systems. We know from (D.8) that the real power is: P = Vrms Irms cos θ

(6.47)

where θ is the angle from the current to the voltage phasor. If the current and the voltage were in phase then the power is obviously Vrms Irms . This is the maximum possible power. It is also known as the apparent power in a system where there is a phase difference between the voltage and the current. The power factor is a measure of how close the actual real power is to the apparent power – i.e.: P (6.48) PF = cos θ = Vrms Irms The next step is to generalise the power factor expression to the case where the current is not sinusoidal. We begin with the basic definition of average power: Z T1 Z T1 1 1 P = p(t) dt = vs (t)is (t) dt (6.49) T1 0 T1 0 where T1 is the period of the fundamental waveform. Remark 6.4 Mathematical preliminary: Using cos θ cos nθ = 1 2 cos(θ − nθ), where n = 2,3,. . ., one can write: Z

2π

1 2

cos(θ + nθ) +

2π

1 [cos((n + 1)θ) + cos((1 − n)θ)] dθ (6.50) 2 0 Z 2π  Z 2π 1 = cos(n + 1)θ dθ + cos(1 − n)θ dθ (6.51) 2 o 0 ( 2π  2π ) 1 sin(n + 1)θ sin(1 − n)θ (6.52) = + 2 n+1 1−n 0 0   1 sin(n + 1)2π sin0 sin(1 − n)2π sin 0 = − + − 2 n+1 n+1 1−n 1−n (6.53) Z

cos(θ) cos(nθ) dθ = 0

=0

(6.54)

Note that if n = 1, then (6.50) becomes: Z 2π Z cos(θ) cos(θ) dθ = 0

2π

cos2 θ

(6.55)

0 2π

1 [cos 2θ + cos 0] dθ 2 0 ( ) 2π 1 sin 2θ 2π = + [θ]0 2 2 0 Z

=

= 2π

power factor

(6.56) (6.57) (6.58)

generalised factor

power

6-10

Line Frequency Uncontrolled Rectifiers Remark 6.5 Remark 6.4 above shows that the product terms involving different frequencies integrate over the fundamental frequency to zero, whereas terms at the same frequency integrate to give a non-zero term. Substituting in (6.11) for vs and (6.13) for is , and noting from Remark 6.4 that the the integral of the cross-product terms are zero, we can write: P =

1 T1

Z

T1

√

2Vs sin ω1 t ·

√

2Is1 sin(ω1 t − φ1 )dt = Vs Is1 cos φ1

(6.59)

0

Remark 6.6 Equation (6.59) shows that the harmonic currents DO NOT contribute to the average (real) power drawn from the source. Therefore, one can consider that the harmonics contribute to the reactive power drawn from the source. This is the basis for the generalisation of the concept of power factor. Note 6.1 The remark immediately above is true if the voltage on the supply remains purely sinusoidal. However, the presence of the harmonics can also cause the introduction of harmonic voltages because of the voltage drop across the transmission line impedances. Usually these impedances are reactive (inductive), and consequently the induced voltage across then is 90◦ out of phase with the current. Therefore the harmonic voltage appearing across the load is zero. Therefore, even under this condition the harmonic power is zero. However, if there is substantial resistance in the line, then there can be a harmonic voltage across the load that is approximately in-phase with the harmonic current. Under this condition the harmonic real power to the load is no longer zero. We can generalise the power factor expression by realising that the apparent power is simply: S = Vs Is (6.60) where Vs and Is are the true rms values of the voltage and the current (i.e. the rms value of a non-sinusoidal current). Therefore, using the same approach as that for sinusoidal quantities we can write: PF =

P S

(6.61)

Therefore, substituting in the definitions into this expression we can write: PF =

Vs Is1 cos φ1 Is1 = cos φ1 Vs Is Is

(6.62)

Remark 6.7 From (6.62) one can see that with a non-sinusoidal current source that the sinusoidal power factor is modified by the term Is1 /Is – i.e. the fundamental current rms value divided by the total current rms value. Therefore, as the harmonics increase, the rms value of the current will increase, but the fundamental will not. Therefore the power factor will decrease. The normal power factor expression is given a new name in this context – it is called the displacement power factor (DPF): DPF = cos φ1

(6.63)

6.3 The Half Wave Rectifier Circuit

6-11

Therefore the power factor with the non-sinusoidal current is: PF =

Is1 DPF Is

(6.64)

Using (6.24) it is possible to write the power in terms of the total harmonic distortion: 1 DPF (6.65) PF = q 1 + THD2i

6.3

The Half Wave Rectifier Circuit

We shall start our study of uncontrolled rectifiers by looking at the simplest possible rectifier circuit – a single diode rectifier.

6.3.1

Pure Resistive Load

The simplest possible load for the simplest possible rectifier is a pure resistive load. The circuit and input and output current and voltages and shown in Figure 6.4. The operation of this circuit is very straight forward and does not warrant much further discussion. In addition, this circuit is not generally used because of the very high ripple in the output voltage and current. Because the output load is a pure resistance there is not output filter, and consequently the output voltage is not a very good dc voltage at all. v diode + -

i

+ vs

vd

R

-

v s , vd

i

v diode i, vd

v s , v diode

t

Figure 6.4: Half wave rectifier with a resistive load.

6.3.2

Inductive Load

The case of a half wave rectifier with a inductive-resistive load is more interesting than the previous case. With inductance in the load the current is more filtered

6-12

Line Frequency Uncontrolled Rectifiers than the previous case. The following discussion is with reference to the circuit shown in Figure 6.5. The output plots have been generated by putting the circuit of Figure 6.6, with L = 200mH and R = 50Ω, into the Saberr , and running the simulation.

+

v diode

-

vL

+

-

iL

L

+ vs

+ R

v out

-

-

Figure 6.5: Half wave rectifier with an LR load.

The first point that one notices in Figure 6.6 is that the current continues to flow even when the source voltage has gone negative. When the energy stored in the inductor reaches zero then the current stops flowing. If the resistor value is made smaller then the current will flow further into the negative half cycle. If the resistance was zero then the current would continue to flow for the whole of the negative half cycle. Let us analyse the situation in Figure 6.6. At t = 0 then the diode becomes forward biased and current begins to flow. Assuming an ideal diode then the circuit whilst the current is flowing is: di (6.66) dt At time t1 the current through the inductor reaches its peak value, since from t = 0 to t1 , vL = vs −vout is positive. Notice that after t1 vL becomes negative as the source voltage decreases, and hence the current through the inductor starts to decrease. At time t2 vs becomes negative. However, the current through the inductor continues in the same direction due to the stored energy in the inductor. Eventually at t3 the energy in the inductor is exhausted and the current drops to zero. Because the current is zero at t = 0 and t3 , we can use the inductor current equation to write: Z 1 t3 ∆i = i(t3 ) − i(0) = vL dt = 0 (6.67) L 0 vs = Ri + L

since i(0) = i(t3 ). This means that the total area under the voltage curve across the inductor is zero (which it must be for the circuit to be in steady state). The integral in (6.67) can be written as follows: Z t1 Z t3 vL dt + vL dt = 0 (6.68) 0

t1

6.3 The Half Wave Rectifier Circuit

t1

t2

6-13

t3

0.8 0.6

iL (A)

0.4 0.2 0.0 -0.2

Due to simulation numerics

60.0

vs

v out

vL

40.0 20.0

(V)

Area A 0.0

Area B

-20.0 -40.0

v diode

-60.0 0.0

0.005

0.01

0.015

0.02 t(s)

0.025

0.03

0.035

0.04

Figure 6.6: Plots for a half wave rectifier with an LR load – L = 200mH and R = 50Ω. which means that: Area A − Area B = 0

(6.69)

Remark 6.8 To get the exact times for t1 , t2 and t3 one needs to solve (6.66).

6.3.3

Inductive Load with Back EMF

Another case of interest is the inductor feeding a back emf scenario. This is shown schematically in Figure 6.7. The voltage source Ed could represent a large capacitor, for example. The result of the presence of this voltage source is that the turn-on time for the diode is change as compared to the previous case. One can see the difference in the performance of the circuit from the Saberr simulation plots shown in Figure 6.8. One can see from Figure 6.8 that the inductor current iL has much the same shape as that shown in the Figure 6.6, but the magnitude of the current in smaller. This is an obvious result, since the voltage that can increase the current through the inductor is much smaller in this case because of the Ed voltage. In addition the time for the current to build up is also smaller. The other notable difference between this case in that of Figure 6.6 is that the diode reverse voltage is substantially larger in this case.

6-14

Line Frequency Uncontrolled Rectifiers

+

v diode

-

-

vL

+

iL

L + + vs

Ed

-

Figure 6.7: Half wave rectifier circuit with an inductor and back emf.

(V)

t1

t2

t3

20.0 0.0 -20.0 -40.0 -60.0 -80.0 -100.0 0.2

v diode

(V)

(A)

iL

0.0

-0.2 60.0 40.0 20.0 0.0 -20.0 -40.0 Area A Area B -60.0 0.0 0.005 0.01

Ed

0.015

0.02 t(s)

vL

0.025

vs

0.03

0.035

0.04

Figure 6.8: Plots for a half wave rectifier with an inductor and back emf as a load.

6.4 The Concept of Current Commutation

6.4

6-15

The Concept of Current Commutation

Before looking at a practical single phase rectifier circuit we shall briefly look at the concept of current commutation in power electronic circuits. Although we shall be looking at this in terms of naturally (or self) commutated circuits, the same principles also apply to force commutated circuits. Up until this point we have not had to consider commutation issues because we have been dealing with a single diode circuit. Current commutation refers to the transfer of the current in a circuit from one power electronic device to another, as one device starts to turn off and the other turn on. In the case of a diode circuit the turn on occurs because the device becomes forward biased, and the turn off because a device becomes reverse biased. If one is dealing with an ideal circuit, then the current would transfer instantaneously from one device to another, but if there is inductance in the circuit then this does not occur instantaneously. In order to study current commutation consider the test circuit in Figure 6.9.

+

vL

D1

-

Ls is

+ vD

vs

vd

D2

1

Id

-

v s , vd is

vd

t

Waveforms with Ls = 0

Figure 6.9: Test circuit used for current commutation discussion. The following discussion is with respect to Figure 6.10. Prior to t = 0 the input voltage vs < 0, and therefore the diode D2 is conducting the output current Id . At t = 0 vs becomes positive and the diode D1 becomes forward biased and turns on. However, due to the inductance Ls the current iD1 does

6-16

Line Frequency Uncontrolled Rectifiers not instantly go to Id . The rise in the current in Ls is limited by the value of Ls and the voltage across it. Eventually the current in Ls will rise to the value if Id . During this rise the current iD2 will be falling at the same rate as the increase in iD1 , so that the current to the current source is maintained at Id . When iD1 = Id then the commutation process is complete, and the current iD2 = 0, turning off D2 . i D1

+

vL

D1

-

Ls

+ vs

is

-

D2

Id

Id

vd = 0

Id

vd = v s

i D2

(a) During commutation is = I d

+ vL = 0

D1

-

Ls

+ vs

is

D2

-

(b) After commutation

Figure 6.10: Circuit configurations during current commutation of the circuit in Figure 6.9. Let us analyse this situation as little more closely. Consider the situation when the input voltage vs initially becomes greater than zero. The voltage on the load side of the inductor is zero because D2 is on. Therefore the current across the inductor is: vL =

√

2Vs sin ωt = Ls

dis dt

0 < t < tc

(6.70)

where tc , the time when commutation is complete. We can rearrange (6.70) and integrate both sides to give: √

Z 2Vs

tc

Z sin ωt dt = Ls

0

Id

dis 0

(6.71)

6.4 The Concept of Current Commutation which becomes: Aθc =

√

2Vs (1 − cos ωtc ) = ωLs Id

6-17

(6.72)

where Aθc , the volt-second area under the inductor voltage. Rearranging this expression we can write: ωLs Id cos θc = 1 − √ 2Vs

(6.73)

where θc , ωtc , the commutation angle. Remark 6.9 Equation (6.73) confirms our previous assertion that if Ls = 0 then the commutation occurs immediately the diode D1 turns on – i.e. cos θc = 1 ⇒ θc = 0. Also note that as Ls increases the commutation angle increases (as one would intuitively expect), and as Id increases the angle increases due to the fact that it will take longer before iD1 = Id . Remark 6.10 Another interesting effect of the commutation is that the average voltage produced at the output of the circuit is lower due to commutation notches. These “notches” result in sections of vs not appearing at the output. Waveforms for the commutation of the current are shown in Figure 6.11. These waveforms are the outputs of a Saberr simulation. These plots clearly show the commutation notches in the output voltage, vd . The commutation notches appear as the voltage across the Ls inductor. The area of these commutation notches, where the horizontal axis is θ = ωt, was evaluated in the expression (6.72). The plots of Figure 6.11, however, are on the time axis. Therefore, under this condition it can be shown that the expression for the area under the inductor notch is Ls Id (the ω term is omitted). Examination of the notch integral plot of Figure 6.11 shows that the area is 0.0050081 – in other words Ls , which it should be since Id = 1. It is clear from Figure 6.11 that the commutation notches lower the output voltage. We can calculate voltage loss analytically. Firstly we can calculate the average output voltage as follows: √ Z π√ 1 2 2 Vd0 = 2Vs sin ωt d(ωt) = Vs = 0.45Vs (6.74) 2π 0 2π In the case where one has commutation notches then the average voltage can be calculated as: Z π√ 1 Vd = 2Vs sin ωt d(ωt) (6.75) 2π θc This expression can be rewritten as the average voltage with Ls = 0 minus the average voltage of the commutation notches: Z π√ Z θc √ 1 1 Vd = 2Vs sin ωt d(ωt) − 2Vs sin ωt d(ωt) (6.76) 2π 0 2π 0 area Aθc = 0.45Vs − (6.77) 2π ωLs = 0.45Vs − Id (6.78) 2π

commutation notches

6-18

Line Frequency Uncontrolled Rectifiers

(V*sec) : t(s)

(V*sec)

0.006

Notch Area

0.004 (0.020805, 0.0050081) 0.002 0.0

(V) : t(s)

20.0

Comm notches vL

(0.020007, 0.10216)

(V)

10.0 0.0 -10.0

(0.020807, -0.022068)

-20.0

(A) : t(s)

Inductor current i L , is

(A)

1.0

0.5

0.0

(V)

(V) : t(s) 60.0 40.0 20.0 0.0 -20.0 -40.0 -60.0

Output vd

vs

vD

1

Output vd 0.0

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

t(s)

Figure 6.11: Plots of the currents in the test circuit of Figure 6.9 – vs = 50 sin ωt, Ls = 5mH, Id = 1 Amp.

6.5 Practical Uncontrolled Single Phase Rectifiers

6-19

Remark 6.11 From equation (6.78) one can see that the loss of output voltage is: area Aθc ωLs ∆Vd = = Id (6.79) 2π 2π

6.5

Practical Uncontrolled Single Phase Rectifiers

We have now carried out some preliminary analysis on half wave rectifiers to develop some techniques to analyse rectifier circuits. We shall now apply these techniques to a practical single phase rectifier. These circuits are very important, as they form the front end of almost all switch mode power supplies used in domestic and computing applications. Remark 6.12 The prevalence of the single phase rectifier in computer based equipment is becoming a problem in power systems due to the harmonics that they inject into the power supply. This results in poor power factor, and can lead to heating problems in other pieces of equipment, and occasionally causing false triggering of frequency controlled equipment on the network. The circuit which is the subject of this section is shown in Figure 6.12. This is typical of a rectifier used in a linear or switch mode power supply. id

Ls

+

Rs

is Cd

vs

+

vd

Rload

-

Figure 6.12: A practical single phase rectifier. If we assume that the current id is discontinuous due to the capacitor voltage resulting in the current going to zero before the end of the half cycle of the input voltage (similarly to the waveforms for the circuit in Section 6.3.3), then we don’t have to worry about the current commutation from one diode to another. We shall generate the analytical equations for the circuit under these conditions. We shall not solve the equations, as this is a little complicated, but the solutions are obtainable. If there is current commutation in the circuit then the solutions get a little more complicated.

6-20

Line Frequency Uncontrolled Rectifiers Whilst the diodes are conducting the equivalent circuit is as shown in Figure 6.13. Applying KVL to this circuit we can write the following differential equation: did vs = Rs id + Ls + vd (6.80) dt Similarly one can also apply KCL to the circuit to give: id = Cd

dvd vd + dt Rload

(6.81)

Rearranging we can write the following matrix expressions when the diode is conducting:  did   Rs    1  − L1s − Ls id dt = (6.82) + Ls vs 1 dvd vd − Cd R1load 0 Cd dt Ls

Rs

id

+ Cd

vs

+

vd

Rload

-

Figure 6.13: Equivalent circuit of the single phase rectifier when the diodes are conducting. During the time when the diodes are off (i.e. when the energy in Ls has been expended and vs < vd ), the capacitor is discharging into the load resistor. Therefore there is an exponential decay of the output voltage. The expression for this time is (using KCL): Cd

dvd vd + =0 dt Rload dvd vd ⇒ =− dt Cd Rload

(6.83) (6.84)

Remark 6.13 Using equations (6.82) and (6.84) one can solve for the complete analytical solution for the currents and the voltages in this circuit. We shall not attempt to solve (6.82) and (6.84), but instead we shall simulate the circuit of Figure 6.12 using Saberr . The plots in Figure 6.14 are the output waveforms of this circuit. In particular notice the very “spikey” current flowing into the rectifier, and the ripples on the output voltage due to this, and the discharge time when all the diodes are off and the output is disconnected from the input.

6.5 Practical Uncontrolled Single Phase Rectifiers

40.0

6-21

(V) : t(s)

80.0

vd

60.0

(A) : t(s)

is (V)

(A)

20.0 40.0

0.0 20.0

-20.0

0.0 (V) : t(s)

60.0

vs 40.0

(V)

20.0 0.0 -20.0 -40.0 -60.0 0.0

0.025

0.05

0.075

0.1

0.125

0.15

0.175

0.2

t(s)

Figure 6.14: Waveforms for the practical single phase rectifier circuit of Figure 6.12.

6-22

Line Frequency Uncontrolled Rectifiers If one evaluates that harmonics on the current waveform the plot shown in Figure 6.15 is obtained. One can see that the output voltage has a dominant dc component (as it should) which has an amplitude of approximately 47 volts. There is also a harmonic at 100Hz corresponding to the fundamental of the ripple on the dc output voltage. The main harmonic in the current is at 50Hz, but there are also significant harmonics at 150, 250 and 350Hz as well (i.e. the 3rd, 5th and 7th harmonics). One can treat each of the harmonics in the current as a phasor (as in (6.7)). The amplitudes of the real and imaginary components of these phasors can be found using the waveform analysis tools in Saberr , and these are plotted in Figure 6.16.

Mag(A) : f(Hz) 6.0

is

Mag(A)

4.0

2.0

0.0

Mag(V) : f(Hz)

60.0

vd

Mag(V)

40.0

20.0

0.0 0.0

50.0

100.0

0.15k

0.2k

0.25k

0.3k

0.35k

0.4k

0.45k

0.5k

0.55k

0.6k

0.65k

0.7k

f(Hz)

Figure 6.15: Input current and output voltage harmonics in a single phase rectifier.

In Figure 6.16 one can see the amplitude of the fundamental real and imaginary harmonics – a1 = −0.40077 and −b1 = −4.6573.8 Therefore using the 8 In Saberr the b coefficient is called the imaginary coefficient. It is the negative of the actual b coefficient as appears in a normal Fourier series. Hence we have written the coefficient as −b1 .

6.5 Practical Uncontrolled Single Phase Rectifiers

6-23

Fourier components generated before 140msec and 180msec

Re(A) : f(Hz)

1.0

is

Re(A)

0.0

(50.0, -0.40077) -1.0

-2.0

Im(A) : f(Hz)

4.0

is

2.0

Im(A)

0.0

-2.0

-4.0 (50.0, -4.6573) -6.0 0.0

50.0

100.0

0.15k

0.2k

0.25k

0.3k

0.35k

0.4k

0.45k

0.5k

0.55k

0.6k

0.65k

0.7k

f(Hz)

Figure 6.16: Real and imaginary components of the harmonic phasors for the harmonics single phase rectifier harmonics plotted in Figure 6.14.

6-24

Line Frequency Uncontrolled Rectifiers definitions associated with (6.7) one can see that: F (1) =

q

a21 + b21 = 4.4745 Amp

φ1 = tan−1

(6.85)

−b1 = 265.08◦ = −94.92◦ a1

(6.86)

Comparison of (6.85) with the fundamental shown in Figure 6.15 indicates that the value appears to be correct. The phase in (6.86) is the phase of a cos waveform (which is the time domain representation of a phasor). The harmonics in Figure 6.15 and Figure 6.16 were taken by looking at the input current over two fundamental periods of the input voltage starting at 120msec and ending at 180msec. This was done so that the rectifier was operating in steady state, and the transients that can be seen in Figure 6.14 would not affect the harmonic analysis. This also means that the phase in (6.86) is with respect to the voltage input waveform. Consequently we can use the value in (6.86) to get the phase (and hence power factor) of the current fundamental. Realising that the time domain form of the phasor is: fn (t) = Fn cos(nω1 t + φn )

(6.87)

one can write the time domain expression for the fundamental current as: i1 (t) = I cos(ω1 t + φ1 )

(6.88) ◦

= 4.47 cos(100πt − 94.92 )

(6.89)

Using the trigonometric identity cos(x) = sin(x + 90◦ ) then we can write: i1 (t) = 4.47 sin(100πt − 4.92◦ )

(6.90)

Hence there is a phase shift of the fundamental from the input voltage of −4.92◦ . Consequently, from (6.63) we can see that the DPF is: DPF = cos φ1 = cos(−4.92◦ ) = 0.996

(6.91)

Remark 6.14 From a fundamental current view point the power factor of the system is very good. The presence of harmonics is the main contributor to poor power factor. The non-sinusoidal power factor is defined by (6.64). Therefore if we can calculate the rms value of the non-sinusoidal current then we can calculate the non-sinusoidal power factor. From Figure 6.15 one can see that the harmonics amplitudes and rms values are as shown in Table 6.2. Using (6.24) we can now calculated the THD for the input current waveform. Calculating the distorted current using (6.21) we get:

Idis

v u 13 uX 2 = 3.1076 Isn =t n6=1

(6.92)

6.5 Practical Uncontrolled Single Phase Rectifiers Harmonic 1 3 5 7 9 11 13

Amplitude 4.6775 3.6788 2.1911 0.87625 0.30301 0.29773 0.18

6-25

RMS value 3.3054 2.6013 1.5493 0.6196 0.2143 0.2105 0.1273

Table 6.2: Current harmonic amplitudes. Therefore the input current THD is: Idis Is1 3.1076 = 100 × 3.3054 = 94%

THD = 100 ×

(6.93)

Remark 6.15 The value in (6.93) shows that the harmonic distortion of the input current is quite high. We can now also calculate the non-sinusoidal power factor using (6.62): Is1 cos φ1 Is 3.3054 × 0.996 =√ 3.10762 + 3.30542 = 0.73

PF =

(6.94)

using (6.19). Remark 6.16 From (6.94) one can see that the power factor has been lowered by the presence of the harmonics. Compare this to the DPF which is 0.996. Therefore the presence of the harmonics in the input current waveform is a major contributor to the poor power factor of this circuit. Remark 6.17 Single phase full wave rectifiers such as depicted in Figure 6.12 are present in large numbers on the power supply grid (e.g. in computer power supplies). Therefore the cumulative affect of this could result in a very poor overall power factor. Techniques for improving the power factor of this rectifiers are now being used.

6.5.1

Unity Power Factor Single Phase Rectifier

The requirement for unity power factor (which implies low harmonic content) for single phase rectifiers connected to the grid has spurred research into techniques to modify the standard single phase full wave rectifier. One of the standard techniques to filter supply current waveforms is to use passive filters at the input of rectifier. These passive filters usually consisted of combinations of L or LC components. An example of a circuit with this type

6-26

Line Frequency Uncontrolled Rectifiers of filtering is shown in Figure 6.17 [2]. This particular circuit has filters at the ac input and the dc output. The input filter is a classic ‘T’ low pass filter. This filter basically filters out the higher order harmonics in the input current. The filter in the dc link needs a little explanation. Clearly it is also a low pass filter, and appears to have the classic π structure. The choice of the size of the components is important from another point of view. The capacitor Cd1 is chosen to be small so that there is considerable ripple in the vd1 voltage. This causes the current to flow in smoother fashion from the supply via the diodes. The extra ripple in vd1 is then filtered via the low pass filter formed by Ld and Cd . The Cd capacitor is much larger than Cd1 . Ld

id

Lf 1

+

Lf 2

is Cf

vs

+

C d1

+

vd1

Cd

+

Rload

vd

-

Figure 6.17: Single phase rectifier with input and dc link filters.

Remark 6.18 The passive circuits have a limited capacity to smooth the input current. The filtering achieved is capable of improving the power factor the acceptable levels. However there are some shortcomings: a. The output voltage is lowered due to the presence of the inductors. b. There is an obvious disadvantage in the cost of the filters, size, losses and dependence of the output voltage on the load current drawn. The limitations cited in Remark 6.18 have led to the investigation of active current shaping techniques to improve the power factor of the rectifiers. These techniques also have the advantage that they extend the range of operation of the rectifier – i.e. the input voltage can vary but the output voltage will stay constant. For any current shaping circuit to be of practical use it has to have the following attributes: • The current shaping circuit should be of low cost and small size. • It should enable the input power factor to be near unity. • The circuit should be simple to control. • It should allow the rectifier to provide the correct voltages under overvoltage as well as under-voltage conditions.

6.5 Practical Uncontrolled Single Phase Rectifiers

6-27

Given these specifications the obvious circuit to provide this functionality is the boost converter. This circuit is the most suitable for the following reasons: a. The circuit is capable of producing an higher voltage at the output than at the input. Therefore as the input voltage falls the output voltage can be kept constant. b. If the converter is set-up to provide an output voltage, that is say 10% higher than the nominal peak input voltage, then the circuit can cope with over-voltages of up to 10% without altering the output voltage. c. The boost converter configuration maintains a continuous current through the input inductor (if operating is continuous conduction mode). Therefore the current can be kept continuous through the diodes on the circuit. This intrinsically allows better input power factor to be achieved. Remark 6.19 Note that the buck converter is in general not suitable for this application because the input current is highly discontinuous. This is due to the fact that the switch in the circuit disconnects the output of the diodes in the rectifier from the input to the converter during normal operation. Figure 6.18 shows the basic structure of a single phase rectifier with a boost converter for current shaping. Boost converter

Ld

id

i load

iL

Ls

+

ic

Rs

is

vs

vs

Cd

+

Rload

vd (> v s )

-

Figure 6.18: Circuit for the a single phase rectifier with current wave shaping boost converter. As can be seen from Figure 6.18 the circuit is simply a conventional rectifier followed by a conventional non-isolated boost converter. The boost converter is usually controlled so that the output voltage is approximately 10% higher than the nominal rated voltage of the rectifier. This allows the circuit to work correctly if the supply is up to 10% higher than the nominal voltage. One implicitly gets a circuit that can operate with low voltages because of the boost converter. How low the voltage can go depends on the design of the boost converter and the load current and voltage required.

6-28

Line Frequency Uncontrolled Rectifiers The key to the operation of the unity power factor rectifier is the control of the boost converter. Before considering the general principles of the control we firstly need to clarify the requirements for the control. If we want unity power factor, than we need a sinusoidal input current which is in phase with the input voltage and does not have any significant harmonics. The desired waveforms are shown in Figure 6.19(a) and (b). One can see that the waveforms in the boost converter section of the circuit are sinusoidal in nature. vs

is

wt

(a) vs iL

wt

(b)

Figure 6.19: Waveforms for a single phase rectifier with active current waveshaping – (a) the input current and voltage; (b) the boost converter input voltage and inductor current. Remark 6.20 Examination of the waveforms in Figure 6.19 indicate that there will be a ripple voltage on the output filter capacitor (as there is in the conventional rectifier). The capacitor has to be designed to be large enough to keep this ripple below acceptable limits. Ignoring power losses in the boost converter we can apply some basic analysis to 6.18 with the waveforms of Figure 6.19. Define Vˆs = √ the circuit of Figure √ 2Vs , and Iˆs = 2Is – i.e. Vs and Is are the rms values of the voltage and the current. Clearly the instantaneous power flowing into the circuit is (using sin2 x = 12 (1 − cos 2x)): pin (t) = Vˆs sin ωtIˆs sin ωt = Vs Is − Vs Is cos 2ωt

(6.95)

6.5 Practical Uncontrolled Single Phase Rectifiers

6-29

which is similar to (6.35), except that this was calculated for cos waveforms with a θ phase difference between them. If we assume that the output capacitor is large then the voltage ripple across it will be minimal, and consequently the output power can be written as: pd (t) = Vd id

(6.96)

where Vd , the average output voltage = vd . The current flowing into the load and the capacitor is: id (t) = Iload + ic (t) (6.97) Assuming that the switching frequency is very high then the inductor can be negligibly small. This allows one to use the simplifying assumption that on an instantaneous basis that: pin (t) = pd (t) (6.98) and therefore we can write: Vs Is − Vs Is cos 2ωt = Vd id (t)

(6.99)

∴ id (t) = Iload + ic (t) =

Vs Is Vs Is − cos 2ωt Vd Vd

(6.100)

One can see from this expression that: Id = Iload = ic (t) = −

Vs Is Vd

Vs Is cos 2ωt = −Id cos 2ωt Vd

(6.101) (6.102)

Even though the assumption was made that the voltage across the capacitor was constant, we can use (6.102) to get an approximate value of the voltage ripple across the capacitor: Z 1 Id vd,ripple (t) ≈ ic (t) dt = − sin 2ωt (6.103) Cd 2ωCd Remark 6.21 From (6.103) it can be seen that if Cd is made large then vd,ripple can be arbitrarily small. The key to the correct functioning of this circuit is the control. Two control loops are required in order to achieve the required control – a voltage control loop so that the output voltage stays are the correct value despite load variations, and a current control loop to provide the input current wave-shaping. These two loops have to work cooperatively. We have previously encountered both voltage and current control loops, arranged in a hierarchical or nested structure, in relation to switched mode power supply control. A similar arrangement is used here, the main difference being the desired reference value for the current. Figure 6.20 shows a block diagram of the basic structure of the control for the unity power factor single phase rectifier. This block diagram is almost the same as that shown in Figure 3.25. The major difference is the inclusion of the multiplier of the error by the absolute value of the supply voltage, which results in a sinusoidal rectified inductor current reference waveform. This is

6-30

Line Frequency Uncontrolled Rectifiers then fed to the current control algorithm. The current control algorithm can be implemented in a variety of ways (see Section 3.3.3.3), but the most common technique is the “constant frequency with turn-on at clock time” controller.

vs e = Vd* -Vd ,measured

Vd*

PI Regulator

Vd,measured

´

i L*

Current mode control

Switch control signal

i L,measued

Figure 6.20: Block diagram of the control system for a single phase rectifier with active current wave-shaping. With this control strategy the net result is that the sinusoidal reference current amplitude is modulated by the output voltage error – the larger the voltage error the larger the amplitude of the sinusoidal current pulse. Some other points to note about this circuit: a. A resistor in series with the Ld inductor is often used to limit the inrush current at start-up. This resistor is usually shorted out by a SCR (large voltage drop with this though), a relay or a MOSFET once the circuit starts to operate normally. b. A small filter capacitor is usually placed across the output of the diode bridge to prevent the switching noise from entering the grid supply. c. The output filter capacitor only has to be about half the size of that in an uncontrolled rectifier, for the same ripple. Therefore the active rectifier circuit saves on weight and space. d. The energy efficiency of a typical active current controlled signal phase rectifier is 96%. An uncontrolled conventional rectifier has an efficiency of approximately 99%.

6.5.2

Effect of Current Harmonics on Line Voltages

We have seen in Section 6.5 that the single phase rectifier can produce many harmonics in the current. In the subsequent analysis of the power factor of the circuit it was assumed (for simplicity reasons) that the voltage was unaffected by the presence of these harmonics. However, in a real network this is not the case. Consider the circuit shown in Figure 6.21. Here we can see a conventional single phase rectifier connected to the grid supply via a source resistance and inductance. Note that the inductance is divided into two sections, the section between them being the so called “point of common coupling” (PCC). The PCC is the nearest point to the rectifier where other equipment can be connected

6.5 Practical Uncontrolled Single Phase Rectifiers

6-31

to the grid supply. Note that there is an additional inductance, representing the inductance of the grid supply, between the PCC and the grid supply voltage source. It is the inductance of this impedance that causes the current harmonics to affect the supply voltage seen by other devices connected to the grid supply. Point of common coupling (PCC) id

Ls2

Ls1

is

+ vs

Rs

v PCC

Cd

+

vd

Rload

-

Other equipment connected to the supply

Figure 6.21: Single phase rectifier showing the point of common coupling. The voltage across other equipment at the PCC is: dis1 (6.104) dt where vs is assumed to be an ideal sinusoidal voltage source. The current is1 contains the harmonic currents of the single phase rectifier (as well as the harmonics drawn by the other equipment). These harmonics will cause a voltage drop across the Ls1 inductance. This drop can be considerable, since the impedance of an inductor increases with increased frequency. One can break the current into a sinusoidal component and the distorted components as follows:   X dish dis1 − Ls1 (6.105) vP CC = vs − Ls1 dt dt vP CC = vs − Ls1

h6=1

Clearly the fundamental component is: vP CC1 = vs − Ls1

dis1 dt

(6.106)

and the distortion component is: vP CCdis = −Ls1

X dish dt

(6.107)

h6=1

6.5.3

Voltage Doubler Single Phase Rectifiers

The circuit shown in Figure 6.22 is sometimes used in cost conscious commercial products to produce voltage doubling without the use of a transformer. Depending on the position of the switch the rectified dc voltage is either approximately

6-32

Line Frequency Uncontrolled Rectifiers the peak of the sinusoidal input voltage, or alternatively it is twice this peak voltage.

C1

D1

Double pos

D2

vac

vd C2

Figure 6.22: Single phase rectifier voltage doubler. If the switch is closed then on a positive half cycle of the input voltage current flows via D1 , capacitor C1 , and the switch back to the supply. On the negative half cycle the current flow via the switch, capacitor C2 and diode D2 back to the supply. The result is that the two capacitors have the peak supply voltage across them, and their voltages sum. If the switch is open, then the circuit behaves as conventional bridge rectifier.

6.5.4

The Effect of Single Phase Rectifiers on Three Phase, Four Wire Systems

In large commercial buildings the primary loads are of a single phase nature, even though the building as a whole is supplied with a three phase power system. These single phase loads are usually distributed as evenly as possible between each of the three phases and the neutral of the system, as shown in Figure 6.23. If the loads on the system are linear loads then such a strategy will lead to a neutral current that is approximately zero. However, if the loads are largely single phase rectifiers, the non-linear nature of these loads can lead to substantial neutral currents. Assume that the diode rectifiers in each of the phases are identical. We can therefore write the currents in the phases as a combination of the fundamental and harmonics currents (which are the odd harmonics, since, as shown previously, the even harmonics are zero): ia = ia1 +

∞ X

iah

(6.108)

h=2k+1

=

√

2Is1 sin(ω1 t − φ1 ) +

∞ X √ h=2k+1

2Ish sin(ωh t − φh )

(6.109)

6.5 Practical Uncontrolled Single Phase Rectifiers

ia

ib

a b n

ic

c

in

Single phase rectifier loads

Figure 6.23: Single phase rectifiers loads in a three phase, four wire distribution system.

6-33

6-34

Line Frequency Uncontrolled Rectifiers In a similar manner to (6.109) one can write the other currents in the phases (assuming they are of similar form): ib =

√

∞ X √

2Is1 sin(ω1 t − φ1 − 120◦ ) +

2Ish sin(ωh t − φh − 120◦ h)

h=2k+1

(6.110) ic =

√

∞ X

2Is1 sin(ω1 t − φ1 − 240◦ ) +

√

2Ish sin(ωh t − φh − 240◦ h)

h=2k+1

(6.111) Applying Kirchhoff’s current law to Figure 6.23 we can write: in = ia + ib + ic

(6.112)

If one substitutes (6.109), (6.110) and (6.111) into (6.112) then all the nontriplen and fundamental harmonics add to be zero. The triplen harmonics on the other hand add to give: in = 3

∞ X

√

2Ish sin(ωh − φh )

(6.113)

h=3(2k−1)

which can be written in rms terms as:  In = 3 

∞ X

1/2 2  Ish

(6.114)

h=3(2k−1)

Therefore the third harmonics add together in the neutral, and the neutral current therefore becomes: In = 3Is3 (6.115) The third harmonic current in the lines can be quite significant with single phase rectifier loads, and consequently the neutral current can be large. In fact under conditions of highly non-linear loads, the neutral current can be as much as √ 3Iline . Therefore, the neutral should be a conductor that can at least carry as much as the lines.

6.6

Three Phase, Full Bridge Rectifiers

Whilst single phase rectifiers predominate in domestic and computer rectification applications, industrial rectification is carried mainly with three phase rectifiers. This is due to their lower voltage and current ripple, and their higher power carrying capabilities. These devices naturally balance the loading on each of the phases, and therefore do not require any planning action in this respect. Furthermore, no triplen harmonics can flow in these circuits since there is no neutral connection. The fundamental circuit for the conventional six pulse three phase rectifier is shown in Figure 6.24. In order to understand the operation of this device we shall firstly look at a simplified model of its operation. Assume that the load is not modeled as an

6.6 Three Phase, Full Bridge Rectifiers

6-35 id

D1

a

D3

D5

Ls

+ b

Ls

ia

+

n c

Cd

Ls

+

Rload

vd

ib

+ ic D4

D6

D2

Figure 6.24: Basic three phase, six pulse, full wave rectifier circuit. RC as in Figure 6.24, but as a constant current sink. This is an approximation to a highly inductive load. The plots of the phase currents and output voltages of this converter are shown in Figure 6.25. As can be seen from this diagram, the output voltage consists of 6 segments per input voltage period. Therefore this rectifier is often known as a six pulse rectifier.

6-36

Line Frequency Uncontrolled Rectifiers

Graph0 (A) : t(s) i(v_sin.phase_c)

(A)

5.0

0.0

-5.0 (A) : t(s) i(v_sin.phase_b)

(A)

5.0

0.0

-5.0 (A) : t(s) i(v_sin.phase_a)

(A)

5.0

0.0

-5.0 (V) : t(s) 400.0

v(v_sin.phase_a)

(V)

200.0 0.0

v(v_sin.phase_b)

-200.0 v(v_sin.phase_c) (V) : t(s)

-400.0

(V)

600.0

output_voltage

400.0 200.0 0.0 0.0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

t(s)

Figure 6.25: Waveforms of a three phase rectifier with a constant current source load.

Chapter 7

Introduction to Other Power Electronic Devices and Applications 7.1

Introduction

This chapter briefly introduces several other high power, power electronic switching devices and applications that are industrially important. The presentation here is brief and introductory in nature, and by no means comprehensive. It is intended to introduce the student to other power electronic circuits, hitherto not considered, and some of their applications. The applications chosen are, hopefully, those that are interesting to the readers. Those who wish to research into any of the circuits and applications presented are encouraged to follow up the topics in the references. The remainder of this chapter will consider the following: • Inverters and applications • Multilevel converters and applications • Matrix converters

7.2

Inverters and Applications

In the previous chapter we briefly considered rectifiers. A rectifier is the name given to a power electronic device which accepts AC voltage at its input, and “rectifies” this to DC voltage at the output. The power flow is considered to be from the AC to the DC side. The term rectifier refers to the operational function of the power electronic hardware, but not the configuration of the hardware. This distinction is demonstrated by the cycloconverter. The cycloconverter uses power electronic hardware that is virtually the same as that of a phase controlled rectifier and generates AC output voltages from AC input voltages. Power can flow bidirectionally in these devices.

7-2

Introduction to Other Power Electronic Devices and Applications

Rectifier mode P

AC

DC

CONVERTER

P Inverter mode Figure 7.1: Definition of rectifier and inverter modes of operation [2]. An inverter, is the dual of the rectifier, in that it accepts DC input and generates an AC output – i.e. power flow is from the DC to the AC side of the power electronic device. As with the rectifier, this definition does not define the hardware configuration, since it is possible to have the same hardware acting as an inverter and rectifier. The above is summarised in Figure 7.1. Consider, for example, the rectifier considered at the end of Chapter 6, i.e. Figure 6.24. In this circuit that main electronic components are diodes. Diodes can only conduct current in one direction. Therefore, if the output voltage is only allowed to be one polarity, then power cannot be transferred from the DC side to the AC side of the converter, as current cannot flow in the reverse direction through the diodes. It is this fact that defines this circuit to be a rectifier.

Input

Converter 1

Converter 2

Output

Energy Storage Element

Figure 7.2: Generic power processing block [2]. Many power electronic systems have the configuration shown in Figure 7.2. Converter 1 transforms the input to DC. There is a storage element that is able to accept the energy. Converter 2 then converters to DC to the desired output. The energy storage element is typically a capacitor or inductor. Its presence means that the instantaneous input power does not have to equal to instantaneous output power, thereby providing a degree of decoupling of the input from the output, and allowing a degree of independence in the control

7.2 Inverters and Applications

7-3

and operation of the two converters. DC link

AC

Converter 1

+

Converter 2

AC

AC Motor

Utility

Figure 7.3: Block diagram of a generic AC drive system. Figure 7.3 shows a less abstract version of Figure 7.2 for one form of an AC drive system. Notice that in this particular case to energy storage element is a capacitor. Both the input and the output is AC. Therefore, in this application there is inherently an inversion process, since one way or another power must go from the DC to AC side. In many actual implementations of Figure 7.3 Converter 1 is a rectifier, and Converter 2 is an inverter. This means that power can only flow from the utility to the motor, and not in the reverse direction since the rectifier cannot transfer power back to the utility. Depending on the details of the implementation of Converter 2, it is possible that it can act as a rectifier, and power can from the motor (which is now acting as a generator, the mode being called regeneration) back to the DC link. In this case the capacitor can accept the energy, but one must be careful to ensure that not too much energy is transferred, else the capacitor will experience over-voltage and be destroyed. If a motor is going to be regenerating for a significant percentage of time during operation, then both Converter 1 and Converter 2 need to be able to act as both a rectifier and an inverter. If this is the situation then regenerated energy can be transferred back to the utility supply, and the capacitor voltage can be controlled to remain within bounds. Remark 7.1 It is possible to further classify inverters based on the type of technology used to implement the inverter – forced commutated converters, resonant link converters. We shall not look a these differences in detail here.

Figure 7.4 shows a specific implementation of an inverter. The main difference between this and Figure 6.24 is that the diodes in the circuit are in parallel with a switch. Most modern small to medium power inverters these days use IGBTs as the switch. The arrows on the switches in Figure 7.4 indicate that this is the direction that current can flow through the switch. The presence of the parallel switches across the diodes makes a major difference to the operation of this circuit. By appropriate switching of the six switches an AC voltage (in an average sense) can be synthesized on the three phase outputs of the inverter. The presence of the diodes, of course, means that the circuit can always operate as a rectifier. In fact, this very circuit is now coming into use as the rectifier front end to large drive systems. Its ability to allow bidirectional power flow means that this rectifier allows a fully regenerative system.

7-4

Introduction to Other Power Electronic Devices and Applications Artificial ground

DC link

3 phase AC load

R

vag

Z

a DC

+

b g

c

Z vbg

n

Z vcg

R

Figure 7.4: Specific implementation of an inverter.

7.2.1

Pulse Width Modulation

Thus far we have only considered one form of the hardware for an inverter. In order for an inverter to work, there has to be a strategy for controlling the switches. In section 1.3.2.2 on page 1-10 the essential ideas behind a triangular wave PWM modulator was briefly discussed. Furthermore, in section 2.4.2 on page 2-11 we considered how to generate a Pulse Width Modulator based on sawtooth modulation waveforms to produce a desired average output voltage for a switched mode power supply. Therefore this section, is to some degree, a brief rehash of this material. The reader is referred to the sections 1.3.2.2 and 2.4.2. The essentials of this technique are shown in Figure 2.11 on page 2-13. The same technique can be used for three phase systems. If we consider just one leg of the three phase converter of Figure 7.4, then the technique outlined in sections 2.4.2 on page 2-11 and 1.3.2.2 on page 1-10 can be applied directly. When the reference waveform exceeds the triangular waveform then the top switch in the leg is turned on, and the bottom leg off. When the reference waveform is less that the triangular waveform, then the bottom transistor is turned on and the bottom transistor is turned off. The waveforms produced when the centre of the DC link is used as the reference point for the voltage are shown in Figure 7.5. Remark 7.2 Note that the fact that the load is referenced to the centre of the DC link allows true AC voltage and AC current to be applied to the load. This is similar to the situation in the three phase inverter. In the case of a three phase inverter to see how the waveforms appear is a little more complex, and not quite as obvious. As in the single leg case one needs to establish a reference point to define the voltages, and similarly the mid point of the DC link is often chosen. Therefore, if the top switch of a leg is closed (meaning that the bottom switch is open) then the voltage on the phase output terminal is 21 VDC where VDC is the total voltage across the DC

7.2 Inverters and Applications

7-5

DC link

+

Modulator

+

Z

e

Reference waveform Carrier waveform

Approximate fundamental

Figure 7.5: Single leg of inverter and the PWM waveforms.

7-6

Introduction to Other Power Electronic Devices and Applications link. Similarly if the bottom switch is closed (meaning that the top switch is open), then the voltage on the phase output terminal is − 21 VDC . Therefore, the output of a single leg has two values. Therefore with three legs we have 23 = 8 possible unique output voltage combinations, corresponding the 8 different possible switching combinations. A notation that we shall use is that the leg switching states are represented by a binary value – a ‘1’ denotes that the top switch of a leg is closed, and the bottom switch is open, and a ‘0’ denotes that the top switch is open and the bottom switch is closed. Therefore, the possible switching combinations, with the phase leg voltages with respect to the mid link ground point (denoted as “g”), and the line-to-line voltages across a three phase load (such as that in Figure 7.4) are shown in Table 7.1. Switch pattern abc 000 001 010 011 100 101 110 111

vag − 21 VDC − 21 VDC − 21 VDC − 21 VDC 1 2 VDC 1 2 VDC 1 2 VDC 1 2 VDC

vbg − 12 VDC − 12 VDC 1 2 VDC 1 2 VDC − 12 VDC − 12 VDC 1 2 VDC 1 2 VDC

vcg 1 − 2 VDC 1 2 VDC − 21 VDC 1 2 VDC − 12 VDC 1 2 VDC − 21 VDC 1 2 VDC

vab 0 0 −VDC −VDC VDC VDC 0 0

vbc 0 −VDC VDC 0 0 −VDC VDC 0

vca 0 VDC 0 VDC −VDC 0 −VDC 0

Table 7.1: Switching combinations and associated phase and line-to-line voltages. Remark 7.3 Note from Table 7.1 that the line-to-line voltages always add together to be zero (similar to line-to-line voltages in a sinusoidal three phase system). Remark 7.4 Note also from Table 7.1 that two of the switching states lead to zero line-to-line voltages. These two states correspond to all the top switches on, or all the bottom switches on. These switching combinations lead to a short circuit across the three phases. The phase voltages – i.e. van , vbn , vcn are also of interest. Let us consider switching state 001 as an example. In this case we have: vab = van − vbn = 0

(7.1)

vbc = vbn − vcn = −VDC

(7.2)

vca = vcn − van = VDC

(7.3)

One can immediately see from (7.1) that van = vbn . However, these equations are not independent, and therefore one cannot solve for the phase voltages. If one considers the three phase load to be a passive one of the form shown in Figure 7.4, then one can write, using Kirchoff’s voltage law, the following expressions: vag = ia Z + vn

(7.4)

vbg = ib Z + vn

(7.5)

vcg = ic Z + vn

(7.6)

7.2 Inverters and Applications

7-7

Adding these equations together we can write: vag + vbg + vcg = (ia + ib + ic )Z + 3vn

(7.7)

Because the load is star connected then we know that: ia + ib + ic = 0

(7.8)

vag + vbg + vcg = 3vn 1 ∴ vn = (vag + vbg + vcg ) 3

(7.9)

and hence (7.7) becomes:

(7.10)

Using (7.10) one can therefore write the following expressions for the phaseto-neutral voltages: 1 1 2 vag − vbg − vcg 3 3 3 2 1 1 = vbg − vn = vbg − vag − vcg 3 3 3 1 1 2 = vcg − vn = vcg − vag − vbg 3 3 3

van = vag − vn =

(7.11)

vbn

(7.12)

vcn

(7.13)

Using equations (7.11), (7.12) and (7.13) together with the values for the voltages vag , vbg and vcg in Table 7.1 one can write all the values for the phase voltages that can be produced by the inverter. These appear in Table 7.2. Switch pattern abc 000 001 010 011 100 101 110 111

vag − 21 VDC − 21 VDC − 21 VDC − 21 VDC 1 2 VDC 1 2 VDC 1 2 VDC 1 2 VDC

vbg − 12 VDC − 12 VDC 1 2 VDC 1 2 VDC − 12 VDC − 12 VDC 1 2 VDC 1 2 VDC

vcg 1 − 2 VDC 1 2 VDC − 12 VDC 1 2 VDC − 12 VDC 1 2 VDC − 12 VDC 1 2 VDC

van 0 − 13 VDC − 13 VDC − 23 VDC 2 3 VDC 1 3 VDC 1 3 VDC 0

vbn 0 − 31 VDC 2 3 VDC 1 3 VDC − 13 VDC − 23 VDC 1 3 VDC 0

vcn 0 2 V 3 DC − 13 VDC 1 3 VDC − 13 VDC 1 3 VDC − 23 VDC 0

Table 7.2: Switching combinations and associated phase and phase-to-neutral voltages. Remark 7.5 Adding together equations (7.11),(7.12) and (7.13) one gets: van + vbn + vcn =

2 1 1 (vag + vbg + vcg ) − (vag + vbg + vcg ) − (vag + vbg + vcg ) 3 3 3 (7.14)

∴ van + vbn + vcn = 0

(7.15)

Therefore the phase voltages always add to be zero, regardless of the applied voltages, when the three phase load is passive. It can be shown that this also applies if there are three phase sinusoidal voltage sources in the load as well.

7-8

Introduction to Other Power Electronic Devices and Applications Remark 7.6 The neutral voltage of the three phase load moves around relative to the ground at the mid point of the DC link. Consider the extreme cases of switching patterns 000 and 111. For 000, using (7.10) and substituting for the voltages from Table 7.2 one can see that vn = − 12 VDC . Similarly for the case of 111 we get vn = 12 VDC . Therefore the neutral voltage has moved around by VDC . These large voltage excursions in the neutral can cause bearing currents to flow when electrical machines are the load on the inverter. 7.2.1.1

Space Vectors and PWM

If an electrical machine is used as the load on an inverter, then space vectors can be used to represent the phase voltages. These phase voltages are appearing across the phases of the machine. Almost all AC machines are wound so that their windings are sinusoidally distributed in space. This fact allows a “space vector” concept to be used to represent currents, fluxes, mmfs, and voltages in the machine. Refer to [14, 2] for more detail. In this concept, currents, voltages, fluxes and mmfs are considered to be sinusoidally distributed in space. As an example, if one has a sinusoidally distributed winding in an AC machine, and this winding is fed with a DC current, then the mmf is sinusoidally distributed around the periphery of the AC machine. Remark 7.7 It can be shown that if we have three phase sinusoidally spatially distributed windings, fed with three phase temporal sinusoidal currents, then one ends up with a spatially sinusoidally distributed resultant mmf that moves around the machine at the electrical supply frequency. This can be represented as a single vector that is rotating with an angular velocity of ω (the electrical supply frequency). The reason for introducing the space vector concept here is because it is convenient to use this concept to represent the output voltages for an inverter. Figure 7.6 shows the space vector diagram for the various switch positions for the inverter. The length of the space vector corresponds to the maximum phaseto-neutral voltage for each phase – i.e. 32 VDC . Notice that there are six active vectors that can be spaced around a machine every 60◦ electrical. Remark 7.8 Although the space vector concept comes about because of the spatial properties of machine windings, it is often used in situations where this does not exist. For example, in Figure 7.3 we have a passive load consisting of impedances, and we can use the space vector concept to represent the voltages on this circuit. I will not, in this brief introduction, go into detail as to why this can be done, suffice to say that it is due to the very close relationship between space vectors and temporal phasors in circuits. Space vectors can be used as a basis for a different type of PWM, called Space Vector PWM (SVPWM). The basis of this PWM strategy is the realisation that three phase temporal sinusoidal voltages lead to a spatially rotating voltage vector in a three phase sinusoidally wound machine (as noted previously). However, with an inverter we do not have infinitely variable voltages that we can apply to each phase, and therefore we can switch the inverter so that at any instant of time we can, in an average sense, produce a desired voltage vector.

7.2 Inverters and Applications

7-9

C

B

A va vb vc

V dc

V 3 (010)

(110) V 2 2 V7 (111) (000) V8

3 V 4 (011)

4

A

B

C

1 (100) V 1 6

5 V 5 (001)

(101) V 6

Figure 7.6: Switch positions and the resultant voltage space vectors.

T T/2

T/2

10 0

1

1

1

1

1

1

0 A

10 0

0

1

1

1

1

0

0 B

10 0

0

0

1

1

0

0

0

t 0 t1

t2

t0

t0

t2

t1 t 0

C

Figure 7.7: Switching waveforms for double edge pulse width modulation.

7-10

Introduction to Other Power Electronic Devices and Applications

In order to develop a PWM strategy using space vectors let us define α as the duty cycle for a vector. Consider Figure 7.7 which shows the switching waveforms to generate a particular voltage vector. One can see from this diagram that the same switching pattern is generated symmetrically around the centre of the PWM period. By reading vertically one can determine the switching states for this switching sequence – they are 000, 100, 110, 111, 111, 110, 100, 000 – i.e. we are switching between vectors V8 , V1 , V2 , V7 , and then the reverse. The vector nomenclature appears in Figure 7.6. As one can imagine this would lead to an average vector somewhere in between V1 and V2 , the length of the vector being controlled by the duration of the zero vectors V7 and V8 . The duty cycle for each of the vectors is simply the total time of the vector divided by the control period time T . For example, the duty cycle for the V1 vector is: 2t1 (7.16) T Similarly one can defined the duty cycle for V2 . Using this notation, if only this vector and the zero vector was switched during an interval of T then the average voltage vector magnitude produced over the interval is α1 VDC volts. α1 =

Note 7.1 Space vectors are defined (for reasons that I shall not elaborate on here) as 23 the amplitude of the resultant vector in the machine. For a three phase machine this means that the maximum voltage vector magnitude is the same as the peak voltage that occurs across the phases. It is this correspondence of the voltage vectors with the phase voltages that is one of the main reasons for using this convention. Remark 7.9 A further comment on note 7.1 – one can resolve the space vector onto three axes 120◦ apart and get the instantaneous value of the voltage on the respective three phase axes. The same logic applies to the current vector.

One of the very convenient features of vectors is that one can take orthogonal components of them – i.e. one can not only resolve the vectors onto the 120◦ axes but one can also resolve them onto 90◦ axes. Consider the situation depicted in Figure 7.8. This shows a desired voltage vector. Note that we have not considered what limits there are on the length of the voltage vector that can be produced by this system. We do know that the limit if the voltage vector lies on one of the natural vectors that can be produced by the inverter is 32 VDC . One can consider the vector in Figure 7.8 is a normalised vector (i.e. divided by 32 VDC ), and hence αd and αq are the normalised orthogonal projections onto a set of orthogonal dq axes. If we apply vector V1 for 2t1 seconds, and V2 for 2t2 seconds then the desired normalised vector, in an average sense, is obtained. Let us now calculate the actual switching times. In order to do this let us define the normalised voltage vector lengths: α1

=

α2

=

2t1 T 2t2 T

(7.17) (7.18)

7.2 Inverters and Applications

7-11

q V2

Desired voltage vector 1

aq 2t 2 60 o

d ad

V1

2t 1 Figure 7.8: Switching time determination. where T , the switching period, and α1 and α2 are effectively the normalised voltage vectors in Figure 7.8. Using trigonometry on this Figure one can clearly write: αd

αq

= α1 + α2 cos 60◦ 1 = α1 + α2 2 √ 3 ◦ = α2 sin 60 = α2 2

(7.19) (7.20) (7.21)

Using the definitions for α1 and α2 we can write: αd

=

αq

=

∴ t2

=

2t1 1 2t1 2t1 t2 + = + T 2 T T T √   √ 3 2t2 3t2 = 2 T T αq T √ 3

(7.22) (7.23) (7.24)

Substituting into the expression for αd and making t1 the subject of the expression we can write: t1

=

∴ t1

=

1 1 αq T (αd T − t2 ) = (αd T − √ ) 2 2 3 T αq (αd − √ ) 2 3

(7.25) (7.26)

Thus t1 and t2 calculate the active vector times. One can now calculate the zero time by realising the there are four t0 periods in one switching period due

7-12

Introduction to Other Power Electronic Devices and Applications Condition for sector Sector 1 Sector 2

Firing order

√ αd > 0; αq ≥ 0; αq < 3αd √ αq > 0; αq ≥ 3 αd

V8 V1 V2 V7 V7 V2 V1 V8 V8 V3 V2 V7 V7 V2 V3 V8

Sector 5

√ αd < 0; αq ≥ 0; αq < 3 αd √ αd < 0; αq < 0; αq > 3αd √ αq < 0; αq ≥ 3 αd

Sector 6

√ αd > 0; αq < 0; αq < 3αd

Sector 3 Sector 4

V8 V3 V4 V7 V7 V4 V3 V8 V8 V5 V4 V7 V7 V4 V5 V8 V8 V5 V6 V7 V7 V6 V5 V8 V8 V1 V6 V7 V7 V6 V1 V8

t0 αq T (1 − α − √ ) d 4 3 2α T (1 − √ q ) 4 3 αq T (1 + α − √ ) d 4 3 αq T (1 + α + √ ) d 4 3 T (1 + 2α √d ) 4 3 αq T (1 − α + √ ) d 4 3

t1 αq T (α − √ ) d 2 3 α T ( √q − α ) d 2 3 αq T √ 3 αq T − √ 3 αq − T (αd + √ ) 2 3 α T (α + √q ) d 2 3

Table 7.3: PWM firing times for various sectors to the centred PWM algorithm. Therefore: 4t0

= =

∴ t0

=

T − (2t1 + 2t2 ) T αq 2αq T T − T αd + √ − √ 3 3 αq T (1 − αd − √ ) 4 3

(7.27) (7.28) (7.29)

It is possible to show, from the geometry of this situation, that for a given set of normalised orthogonal vectors αd and αq the switching times for the vectors in sector 1 of the PWM star are: t1

=

t2

=

t0

=

αq T (αd − √ ) 2 3 αq T √ 3 T αq (1 − αd − √ ) 4 3

(7.30) (7.31) (7.32)

where the various t values are defined in Figure 7.7. If a similar analysis is carried out for all the sectors then one can get a complete set of switching times as shown in Table 7.3. Another important aspect that was eluded to earlier was that there is limiting of the resultant space vectors. For example, one cannot ask for αd = 1 and αq = 1, since this would be asking for a resultant space vector that is larger than that which can be obtained given the vectors that the inverter can produce. If one applies the expressions from Table 7.3 to such a situation then this problem manifests itself by the condition [15]: 2t1 2t2 + >1 (7.33) T T or: αq αd + √ > 1 (7.34) 3 in the case of sector 1 limiting. Clearly (7.33) means that the total switching time of the active vectors exceeds the total control period. It can be shown that the limitations imposed by the available firing times result in a hexagon limit. This is shown in Figure 7.9. If a desired vector exceeds the limit hexagon, then it has to be limited to the hexagon [15].

t2 αq T √ 3 αq T (α + √ ) d 2 3 αq − T (αd + √ ) 2 3 αq T (−α + √ ) d 2 3 αq T (α − √ ) d 2 3 αq T − √ 3

7.2 Inverters and Applications

7-13

Limit hexagon Limit circle V3 (010)

V (110)2

2 V7 (111) (000) V8 5

3 V4 (011)

4

(001) V5

1 (100)V 1 6

(101) V6

Figure 7.9: Voltage limit hexagon. If the times are to be scaled so that they add to give one, then we require:   2t1 2t2 γ + =1 (7.35) T T or: γ=

1 αd +

α √q 3

(7.36)

Remark 7.10 Note that the use of the γ on both the total times means that the angle of the resultant vector is preserved. The new limited firing times for sector 1 are now: 2t1lim

=

2t1 γ

(7.37)

2t2lim

=

2t2 γ

(7.38)

The 1/γ values for all the sectors are summarised in Table 7.4.

Remark 7.11 Space vector based PWM is particular amenable to implementation in digital form. This can be contrasted with carrier wave based PWM, which was originally devised for analogue implementation. Of particular importance is that this technique does not involve the solution of any transcendental equations, and it does not involve the use of any trigonometric functions.

7-14

Introduction to Other Power Electronic Devices and Applications Sector 1

1/γ α αd + √q3 2αq √ 3

2 3 4

− αd α −(αd + √q3 )

5 6

− √3q α αd − √q3

α √q 3

2α

Table 7.4: Voltage limit γ’s Remark 7.12 Another interesting feature of space vector PWM is that the maximum amplitude of the fundamental that can be produced by the technique is larger, by approximately 15%, than that produced by carrier based sinusoidal PWM. A similar effect can be obtained in sinusoidally PWM by putting a third harmonic in the reference waveform.

7.2.2

Dead-time Issues

An important practical issue that arises with “totem pole” inverter legs is the problem of “shoot through”. This term refers to the phenomena of both the top and bottom device being momentarily on when there is a switching transition from the top to the bottom device, or vice-versa. Remark 7.13 The “shoot through” problem also exists in low power digital circuits. One may recall from your studies of logic families that CMOS and TTL both suffer from “shoot through”. In the case of digital systems the shoot through is a very short period of time, and the power levels involved are low. Consequently the problem can be tolerated. However, in high power inverter systems the devices will fail if “shoot through” occurs. Shoot through is overcome by making sure that the outgoing device is turned off before the incoming device turns on. This is achieved in practice by manipulating the device signals that turn the devices on and off.

The turn off of a power device is not instantaneous due to the phenomena of charge storage in the devices. In order to give the device time to turn off before turning on the other device in the a small delay (typically of the order of 3 to 4µsecs for todays IGBT devices) is allowed between the turning off of one device and the turning on of the other. This delay results in a different voltage being applied to the machine compared to that being demanded by the control. This is due to the fact that the dead-time delay results in a shift of the switching edges. The dead-time error problem is a little more complicated than I have outlined above. The presence of the dead-time switching delay is actually variable depending on the direction of the current through the inverter leg. The following discussion is with reference to Figures 7.10 and 7.11. Figure 7.10 shows two legs of an IGBT based inverter, with the current flowing out of leg A and into leg B. Figure 7.11 shows the effects of the current direction on the actual time of

7.2 Inverters and Applications Phase A Leg

7-15

Phase B Leg

Phase C Leg

+

Initial current Final current

ia i

DC Bus Input/Output

ib

i

ia f ib

f

}

Three Phase Input/Output

-

Figure 7.10: Inverter showing the initial and final current flow after a leg is fired. switching. As can be seen when current flows out of a leg (i.e. leg A) the actual time of switching is the desired time of switching. Therefore the dead-time of the inverter does not cause a problem. However, when current is flowing into a leg (i.e. leg B) then the switching time is delayed by the dead-time. Therefore, if one wishes to compensate for the dead-time so that correct switching always occurs, one should sense the current direction and compensate the switching time as appropriate. However, because the compensation of the switching time has to occur in the control interval before the interval it is going to be applied, then there is the possibility that the current direction may be incorrect. This situation only occurs around the times that the fundamental current is about to change direction. The result of incorrect compensation is that the cross-over of the current through zero may be considerably distorted – even more than if compensation is not being applied. This issue has not been resolved.

7.2.3

Some Inverter Applications

In this subsection we shall consider some of the applications for inverters. The presentation is by no means exhaustive, and the more common applications will be highlighted. 7.2.3.1

Variable Speed Drives

One of the most common applications of inverters are in AC variable speed drives. These drives are most commonly based on the use of induction machines. Figure 7.3 shows the generic layout of an AC drive. As mentioned in section 7.1 Converter 1 in this figure is often a uncontrolled three phase rectifier (although if the supply is single phase then one could have a single phase rectifier). Converter 2 is a conventional inverter, much as shown in Figure 7.4. At low powers and voltages the power devices in the inverter can be MOSFETs. At small to medium powers, the IGBT has become the device of choice. The range of operation of the IGBT is extending all the time in terms of the currents and voltages that can be handled. At the time of writing these notes IGBTs

7-16

Introduction to Other Power Electronic Devices and Applications

{

Top

Leg A switching

Bot

On Off On Off

Dead - time Td

{

Top

Leg A currents

Bot

{

Top

Leg B switching

Bot

ia i

Desired switching point and actual switching point

0

ia f = ia i

0

On Off On Off

Dead - time Td

{

Top

Leg B currents

Actual switching point

0 ib

i

0

Bot i = i b b f

i

Desired switching point

Figure 7.11: Example of dead-time induced switching error in an inverter.

7.2 Inverters and Applications are available with maximum voltages of 6kV, and current capabilities in the thousand of amps range. Variable speed AC drives are becoming ubiquitous devices these days. They can be found in anything from domestic air conditioners, washing machines and microwave ovens, right through to large drives in power station bag houses and rolling mills. If better power sources are found, then AC drives will become very prevalent in vehicular transportation. They are currently widespread in train transportation. The main driving factors towards the increasing use of inverters are: a. The simultaneous arrival of low cost high performance microprocessors, as well as reliable, robust and reasonable cost power electronic devices in the since the mid 1990s. b. The refinement of the control algorithms for AC machines allowing high performance from AC drives. c. A community demand for more efficient use of energy. Let us briefly consider a few of the applications mentioned above. It is not uncommon to hear in advertisements for air conditioners that they are inverter air conditioners. The inverter in these air conditioners are being used to drive the compressor in a variable speed mode. Normally an air conditioner is driven in an on-off mode, controlled by a thermostat. The reason for going to a variable speed mode is that the compressor is much more efficient in this mode. When a compressor starts for the next 30 to 60 seconds it is not really pumping any heat, but simply compressing the refrigerant. If the compressor is being started and stopped on a regular basis this non-productive time will be a significant part of the total operating time of the compressor. Under variable speed operation the thermostat simply controls the speed of the compressor, but it does not stop. Therefore the refrigerant does not have to be re-compressed, since it does not decompress whilst the compressor is running, albeit more slowly. Inverter air conditioners can be up to 30% more efficient as compared to the traditional onoff air conditioner (depending on operating cycle of the on-off air conditioner). Another domestic appliance that now has an inverter in it is the microwave oven. The inverter is used to supply variable voltage to the magnetron, and therefore get true variable power instead of pulsed on-off 100% power as in a conventional oven. This is main motivated by better cooking performance at low power levels. In actual fact the so-called inverter circuit in a microwave oven is more like a flyback switch mode power supply circuit. The switch mode supply can be operated at high frequency, and therefore allow a smaller high frequency transformer to be used. In addition, the output voltage and/or current can be controlled allowing completely variable, constant power from the magnetron. 7.2.3.2

Grid Connected Applications

As the power electronic devices improve in voltage rating, grid connected applications of inverters are becoming more common. The classic example of the use of an inverter in a grid connected application is interfacing photo-voltaics to the grid.

7-17

7-18

Introduction to Other Power Electronic Devices and Applications

Controller

AC

DC Photo-voltaic solar cells

Inverter

Utility supply

Domestic load

Figure 7.12: Generic non-battery based photo-voltaic supply system.

In a photo-voltaic interface, the solar cells are producing DC voltage which either has to be converted into AC to feed the utility grid, or converted to AC to supply domestic AC appliances. Both of these are classic inverter applications. In some situations the output of the solar cells will firstly be fed to a bank of batteries for storage. It is then the DC in the batteries that is converted to AC. In other situations, the DC from the solar cells may be fed directly into the grid without the intermediate batteries (see Figure 7.12). This is the situation that is common for non-remote properties that are connected to the main utility grid supply. The inverter is its associate controller can either deliver power to the grid, or take power from the grid, depending on the insolation falling on the solar cells. In the case of remote properties, there in many cases will not be a utility supply, and the inverter would be powering the household appliances. A more industrial application of inverters is the static var compensator (SVC). A compensator is a device that can be connected to the power system to provide voltage support for the supply, especially at the end of long transmission lines. This is achieved by the compensator being a variable capacitor. Traditionally this was achieved by using a synchronous machine, and varying the excitation to vary the apparent capacitive load represented by the machine. Later banks of switchable capacitors were used, the switching being achieved by thyristors. More recently a traditional inverter has been used. This circuit has the significant advantages over the previous techniques – injects less harmonics into the supply, very rapid bumpless changes can be achieved, can compensator for general power factor (i.e. can perform an active filter function). Figure 7.13 shows some variants of the static compensator (STATCOM) offered by the Siemens company. Some of these devices do more than simple static var compensation, and are capable of real power flow control as well as reactive power flow control. AC transmission systems that include these power electronic devices are known as Flexible AC Transmission Systems (FACTS). See the next chapter for much more details on grid connected applications related to renewable energy.

7.2 Inverters and Applications

Statcom

Unified Power Flow Controller (UPFC)

7-19

Static Synchronous Series Compensator (SSSC)

Back-to-Back Statcom

Figure 7.13: Some grid connected FACTS units offered by Siemens.

7-20

Introduction to Other Power Electronic Devices and Applications

Figure 7.14: Conceptual diagram of a matrix converter.

7.3

Multilevel Converters and Applications

This section still has to be written

7.4 7.4.1

Basic Introduction to Matrix Converters Introduction

Matrix converters are a converter type that does not have an intermediate energy storage element. It is a converter that allows direct conversion of an AC waveform of one frequency and magnitude, to a waveform of another frequency and magnitude using only semiconductor switching elements. The essential idea behind the matrix converter is that one has an array of switches that allow any input phase to be connected to any output phase. Figure 7.14 shows a conceptual diagram of a matrix converter. Note that the switches in this figure have to conduct current bidirectionally and have to be able to block current in both directions. Currently most semiconductor switches conduct current in both directions, but can only block current in one direction. Fortunately it is possible to combine these switches so that the composite switch behaves as a bidirectional bi-blocking switch. Remark 7.14 The fact that the matrix converter allows any input phase to be connected to any output phase means that there is a lot of freedom with respect to the connections that can be made with this converter. However, this also means that there are many ways that a short circuit can be created.

7.4 Basic Introduction to Matrix Converters

Figure 7.15: Reconfigured conceptual diagram of the matrix converter. It is possible to reconfigure the switch arrangement shown in Figure 7.14 on page 7-20 to that shown in Figure 7.15. This particular figure more graphically shows the “matrix” property of this converter. Remark 7.15 Note that the gaps in the wires in Figure 7.15 are actually continuous lines that run over the crossing line.

7.4.2

Switching Rules

There are 29 = 512 different combinations of the 9 possible switches. However one has to restrict the combinations for electrical reasons. Typically the input to a matrix converter is a voltage source, and the output load of the converter is an inductive load. Therefore the switching if the converter cannot short circuit the input, and at the same time cannot attempt the open circuit the output. The rules that guide these restrictions can be summed up as: • DO NOT connect two different input lines to the same output line. This is to prevent a short circuit between two or more phases. • DO NOT disconnect the output lines – inductive currents will result in very high voltages across the switches. Remark 7.16 The latter of these two rules means that output lines must be connected to an input line at all times. Remark 7.17 The fact that the output lines have to be connected to an input line under all circumstances means that the state of the matrix converter can be symbolised with only three input values. For example, ‘ACC’ means that phase ‘A’ is connected to ‘a’, phase ‘C’ is connected to ‘b’ and phase ‘C’ is connected to ‘c’. Therefore the symbols used in this notation have positional relevance. If the switching rules above are applied then the 512 possible switch states are decreased to 27 permitted switch states, which have the following properties:

7-21

7-22

Introduction to Other Power Electronic Devices and Applications a. 3 states produce forward rotating space vector voltages. These states correspond to each output phase being connected to a different input phase. Therefore a space vector is produced that rotates at the mains frequency. b. 3 states produce reverse rotating space vector voltages. This is the reverse phase sequence of the previous set of states. c. 18 states produce stationary space vector voltages of various amplitudes. This group occurs if two output phases are connected to a common input phase, and the third output phase is connected to a different input. d. 3 states produce zero space vector voltages. This corresponds to all three outputs being connected to the same input line. Remark 7.18 Most modulation techniques for matrix converters have used the states associated with points c and d above because of the difficulty of dealing with the rotating vectors with the control techniques traditionally employed.

7.4.3

Switching – Some More Detail

7.4.3.1

Alesina/Venturini Modulation Algorithm

The information in this section mostly comes from a review paper on matrix converters[16], and is reproduced here much as it is written, but with some additional explanation where appropriate. One can define the switching function for a single switch as: SKj

=

( 1, switch Skj closed 0, switch SKj open

(7.39)

where K = {A, B, C} and j = {a, b, c}. The constraint above can be expressed mathematically as: SAj + SBj + SCj = 1

(7.40)

which means that there always has to be a switched closed onto output phase j (i.e. no open circuits) and there can only be one switch closed onto output j (i.e. no short circuits). This restriction leads to the 27 valid switching states mentioned previously. Remark 7.19 Equation (7.40) has to be true if the switches are truly bidirectional in current flow when they are closed. However, as we share see it is possible to violate this condition if the switches have controlled bidirectional current flow – i.e. the switches are bidirectional, but via control the current flow direction can be selected. If the load and source voltages are referenced to the incoming supply neutral point (assuming that the supply is star connected), then the input and output vectors can be expressed as:

7.4 Basic Introduction to Matrix Converters

7-23

 vi

=

vo

=

 vA (t)  vB (t)  vC (t)   va (t)  vb (t)  vc (t)

(7.41)

(7.42)

The relationship between the load and the input voltages using these definitions can be expressed as follows:      va (t) SAa (t) SBa (t) SCa (t) vA (t)  vb (t)  =  SAb (t) SBb (t) SCb (t)   vB (t)  (7.43) vc (t) SAc (t) SBc (t) SCc (t) vC (t) vo

= Tvi

(7.44)

where T is the instantaneous transfer matrix. Similarly the relationships between the input and output currents can be defined as:   ia (t) (7.45) io =  ib (t)  ic (t)   iA (t) ii =  iB (t)  (7.46) iC (t) and: ii = T−1 io

(7.47)

where T−1 is the inverse transfer matrix. Remark 7.20 Equation (7.43) essentially says that the output voltages of the matrix converter are simply related to the value of one of the input voltages. Note that (7.40) indicates that at any point of time only one of the input voltages, vA, vB or vC can be connected to the output lines. Remark 7.21 The obvious question to ask with respect to (7.43) is what is the switching function to make the vo vector equation to the desired voref . Therefore a modulation strategy has to be defined. Figure 7.16 shows the typical form of the switching for the matrix converter switches [16]. Notice that each output phase is connected in order to one of the input phases in a repeating sequence. This means, for example, that input phase A is connected to output phase a then input phase B is connected and finally input phase C is connected, each one for a specific period of time defined by the modulation strategy.

7-24

Introduction to Other Power Electronic Devices and Applications

SCa = 1

SBa = 1

SAa = 1

tBa

tAa

tCa

SAb = 1

SBb = 1

SCb = 1

tAb

tBb

tCb

SAc = 1

SBc = 1

SCc = 1

tAc

tBc

tCc

Tseq (time sequence)

Output Phase a

Output Phase b

Output Phase c

Repeats

Figure 7.16: General form of switching pattern [16]. Let us define the duty cycle modulation function of one of the switches as: mKj (t) =

tKj Tseq

(7.48)

where can take on the following values: 0 ≤ mKj ≤ 1 K = {A, B, C},

j = {a, b, c}

(7.49)

One can now define a low frequency transfer matrix as:  mAa (t) mBa (t) mCa (t) M(t) =  mAb (t) mBb (t) mCb (t)  mAc (t) mBc (t) mCc (t) 

(7.50)

this matrix being a matrix of duty cycles. Remark 7.22 Equation (7.50) is called a low frequency matrix because if we use it to calculate the output then we are implicitly assuming that the output voltage is related to the duty cycle multiplied by the input voltage – i.e. we are considering the average output voltage over the control cycle of the converter (over Tseq ). Using (7.50) we can define the average output voltage vector as: vo = M(t)vi (t)

(7.51)

and the low frequency component of the input current is: ii = M(t)T io

(7.52)

7.4 Basic Introduction to Matrix Converters

7-25

Remark 7.23 One can see from Figure 7.16 on page 7-24 and the definition of the switch duty cycle in (7.48) that this means that the sum of the duty cycles can only be one for any particular output line, i.e. mAa (t) + mBa (t) + mCa (t) =

tAa tBa tCa + + =1 Tseq Tseq Tseq

(7.53)

If this is expressed in matrix form it becomes: M(t)1 = 1

(7.54)

where 1 is a column vector of ‘1’s. Note that this condition, together with the valid switch condition (7.40) means that there is always a connection a particular input line to an output line. Summary 7.1 Summarising so far, the key expressions which the modulation matrix must satisfy are: v0 = M(t)vi T

ii = M(t) io M(t)1 = 1

(7.55) (7.56) (7.57)

If vi is not proportional to the vector 1 then (7.55) and (7.57) provide two independent conditions on every row of the matrix M(t) while (7.56) provides one condition on every column of M(t) [17]. Two more equations can be provided from Kirchoff ’s current law and assuming that the converter is lossless: ii T vi T

=

io 1 =

io T vo

(7.58)

ii T 1

(7.59)

We have 9 unknowns in the form of the modulation functions. The input voltages and output currents are known measured variables, and the output voltage vo is a desired output voltage (if the objective is to obtain this desired output voltage). Between all of the equations above it is possible to get 9 independent equations, and therefore the system is solvable. Let us consider a three phase system. Let the sinusoidal voltages at the input be: vA

=

vB

=

vC

=

Vi cos(ωi t) 2π ) 3 4π Vi cos(ωi t + ) 3 Vi cos(ωi t +

(7.60) (7.61) (7.62)

and the assumed output sinusoidal currents: ia ib ic

= Io cos(ωo t + φo ) 2π = Io cos(ωo t + + φo ) 3 4π = Io cos(ωo t + + φo ) 3

(7.63) (7.64) (7.65)

7-26

Introduction to Other Power Electronic Devices and Applications Remark 7.24 Note that both the input voltages and the output current are measured and assumed respectively. The output current is assumed, because if the converter is driving a passive circuit then the output current is a function of the output voltages, which are what we are trying to calculate. The desired input currents are defined as follows: iA

=

iB

=

iC

=

Ii cos(ωi t + φi ) 2π Ii cos(ωi t + + φi ) 3 4π + φi ) Ii cos(ωi t + 3

(7.66) (7.67) (7.68)

and the desired output voltages: va vb vc

= Vo cos(ωo t) 2π = Vo cos(ωo t + ) 3 4π = Vo cos(ωo t + ) 3

(7.69) (7.70) (7.71)

There is an existence theorem in [17] that defines the relationship between the input voltage amplitude and the amplitude of the output voltage, and the amplitude of the output current and the input current. it states (fairly obviously) that:: Vo

≤

Ii

≤

Vi 2 Io 2

(7.72) (7.73)

These relationships are related to the fact that the input voltages and output currents are three phase 120◦ separated sine waves, and the cross-over point of the sine waves is one half the amplitude of the sine waves. Since the waves can be selected by the modulator at any time, this limits the output voltage to one half the amplitude of these waveforms. The condition in (7.58) can be written as: Vo Io cos φo Vo ∴ Vi

= Vi Ii cos φi Ii cos φi = Io cos φo

(7.74) (7.75)

Taking into consideration all these conditions the (7.55), (7.56)and (7.57) can be solved to give the modulation functions for this converter[17]:   4π 1 + 2qCS(0) 1 + 2qCS(− 2π 3 ) 1 + 2qCS(− 3 )  1  1 + 2qCS(− 4π 1 + 2qCS(0) 1 + 2qCS(− 2π M(t) = α1 3 ) 3 ) + 3  2π 4π 1 + 2qCS(− 3 ) 1 + 2qCS(− 3 ) 1 + 2qCS(0)   4π 1 + 2qCA(0) 1 + 2qCA(− 2π 3 ) 1 + 2qCA(− 3 ) 1  4π 1 + 2qCA(0) α2 1 + 2qCA(− 2π (7.76) 3 ) 1 + 2qCA(− 3 )  3  4π 1 + 2qCA(− 3 ) 1 + 2qCA(0) 1 + 2qCA(− 2π ) 3

7.4 Basic Introduction to Matrix Converters

7-27

where: CS(x)

=

cos(ωm t + x)

CA(x)

=

cos[−(ωm + 2ωi )t + x]

ωm α1 α2 q

= ωo − ωi 1 = [1 + tan(φi ) cot(φo )] 2 1 = 1 − α1 = [1 − tan(φi ) cot(φo )] 2 Vo = Vi

with the added conditions: α1

≥

0

α2

≥

0 1 2

0≤ q≤

The question that arises from the above analysis is: “How does one use the expressions in (7.76) to come up with a switching strategy. It should be remembered that the modulating functions have been derived in the sense that the converter switching is at such a high rate that the duty cycles of the switches (i.e. the m values in the matrix M) are a continuously changing set of values. In reality this is not the case, and there is a finite switching frequency. However, as discussed in Chapter 1 on page 1-1 converters only work because of the averaging action of the loads that the converter is connected under the assumption that the switching frequency is high enough that the switching harmonics produced are filtered by the load. Based on these assumptions, the switching time for each of the switches can be written as: δtKj (7.77) k = T mKj (kT ) where δtKj k denotes the switching on time for switch Kj for the interval k. Note that: Tkj

=

n X

δtKj k

(7.78)

K=1

which is simply a restatement of the condition in (7.57) saying that all the switch times for a particular output phase can only add up to be the switching period. Remark 7.25 As mentioned in the previous discussion (7.77) only gives the correct output if the switching frequency satisfies: fT =

1 ωi ωo  , T 2π 2π

Remark 7.26 The equations presented immediately above are those originally developed by Alesina and Venturini [17] and are for a system limited to an output voltage magnitude that is half the input voltage magnitude – i.e. Vo ≤ 0.5Vi .

matrix converter switching time

7-28

Introduction to Other Power Electronic Devices and Applications This is quite a restriction on these systems. Fortunately it was subsequently shown that the output voltage could be improved by adding third harmonics of the form 1 1 vo3rd = − cos(3ωo t) + √ cos(3ωi t) (7.79) 6 2 3 to the reference voltages. If this is done then it was shown in [18] that: Vo ≤ 0.87Vi

(7.80)

and this is the theoretical maximum output voltage that can be obtained from a direct AC-AC converter system regardless of the converter architecture. Remark 7.27 The solution of (7.76) is reasonably complicated, and is one reason why this technique is regarded by many as too complex. Nevertheless the technique presented in [17] is the foundation of all the subsequent work in this area. 7.4.3.2

Space Vector Modulation Techniques

Space vector modulation (SVM) is a well known modulation technique in conventional PWM inverters. It has the nice attribute that it is very amenable to digital implementation. As mentioned previously in point c and point d on page 7-22 there are a total of 18 active stationary vectors that can be produced by the converter, and 3 zero vectors, giving a total of 21 useful vectors for the SVM application. The output voltage space vector and the input current space vector are defined as[14]:

2π

vo

=

ii

= 2π

2 (va + avb + a2 vc ) 3 2 (iA + aiB + a2 iC ) 3

(7.81) (7.82)

where a = ej 3 and a2 = ej 3 . The nomenclature is as follows: ABC means that input phase A is connected to output phase a, input phase B is connected to output phase b and finally input phase C is connected to output phase c. As can be seen there is an implied positional dependency of the nomenclature, with the first position being the connection to output phase a, the second to output phase b, and the third position to output phase c. This compact notation can be used because the input and the output have to be connected at all times due to the requirement that the current flow through the converter cannot be interrupted. In order to calculate the output voltage and the input currents for a particular switch situation one has to apply the above definitions for the voltage and current space vectors to the various 21 stationary vector switch configurations. As an example of this consider the situation of the switches being ABB – i.e. input phase A is connected to output phase a, input phase B is connected to output phase b and input phase B is connected to output phase c. This means that input phase C is not connect to anything, and therefore there is no current flow in this input phase. The output voltage phasor is defined by (7.81), and with the ABB switch configuration then we can say that va = vA , vb = vB , and

improved voltage

output

7.4 Basic Introduction to Matrix Converters

7-29

vc = vB , therefore (7.81) can be written as: vo

= = =

∴ vo

=

2 (vA + avB + a2 vB ) 3 √ √ 2 3 3 [vA + (−0.5 + j )vB + (−0.5 − j )vB ] 3 2 2 2 (vA − vB ) 3 2 vAB 3

(7.83)

Similarly one can calculate the input current for this switch configuration by applying the definition of the input current space vector defined in (7.82) and realising that for the ABB switch setting that iA = ia , iB = ib + ic , and iC = 0, and that ia + ib + ic = 0: ii

= = = = = =

∴ ii

=

2 (iA + aiB ) 3 2 [ia + a(ib + ic )] 3 √ 2 3 [ia + (−0.5 + j )(−ia )] 3 2 √ 2 3 3 ( −j )ia 3 2 2 √ 2 1 3 3 √ √ ( −j )ia 2 2 3 3 √ 1 2 3 √ ( − j )ia 2 3 2 π 2 √ ia e−j 6 3

(7.84)

Similar results can be obtained for all the other switch configurations. Table 7.5 on page 7-30 shows these vectors and the output voltage and input current vector angles for them.

These space vectors can be placed on a traditional space vector hexagon. These appear in Figure 7.17. Remark 7.28 As can be seen from Figure 7.17 the hexagons are similar to those for a conventional PWM inverter. However, one point that is not clear from these diagrams is that the length of the vectors are dynamic and dependent on the various instantaneous line-to-line voltages. Similarly the current vectors are variable length and dependent on the instantaneous line currents.

Let us consider a situation where the desired voltage vector v o is in sector 1 and the angle of the current vector ii is βi as shown in Figure 7.17. As we shall see, in order to generate the average v o vector the switching vectors ±7, ±8, ±9

7-30

Introduction to Other Power Electronic Devices and Applications

Switching configuration list 01 02 03 +1 -1 +2 -2 +3 -3 +4 -4 +5 -5 +6 -6 +7 -7 +8 -8 +9 -9

Switch connections

vo

αo

ii

βi

AAA BBB CCC ABB BAA BCC CBB CAA ACC BAB ABA CBC BCB ACA CAC BBA AAB CCB BBC AAC CCA

0 0 0 2 v 3 AB − 32 vAB 2 3 vBC − 23 vBC 2 3 vCA − 32 vCA 2 3 vAB − 32 vAB 2 3 vBC − 23 vBC 2 3 vCA − 32 vCA 2 3 vAB − 32 vAB 2 3 vBC − 23 vBC 2 3 vCA − 32 vCA

0 0 0 0 0 0

0 0 0 √2 ia 3 − √23 ia √2 ia 3 − √23 ia √2 ia 3 − √23 ia √2 ib 3 − √23 ib √2 ib 3 − √23 ib √2 ib 3 − √23 ib √2 ic 3 − √23 ic √2 ic 3 − √23 ic √2 ic 3 − √23 ic

− π6 − π6

2π 3 2π 3 2π 3 2π 3 2π 3 2π 3 4π 3 4π 3 4π 3 4π 3 4π 3 4π 3

Table 7.5: Switching values used in SVM.

π 2 π 2 7π 6 7π 6 − π6 − π6 π 2 π 2 7π 6 7π 6 − π6 − π6 π 2 π 2 7π 6 7π 6

7.4 Basic Introduction to Matrix Converters

7-31

2

§4; §5; §6

3

1 vo ®o

§1; §2; §3

6

4 §7; §8; §9

5 (a)

§2; §5; §8

3

2

ii ¯i

4

§3; §6; §9

6

5

1

§1; §4; §7

(b) Figure 7.17: (a) Direction of the output line-to-neutral voltage vectors for the active switch configurations. (b) Directions of the input line current vectors generated by the active switch configurations.

7-32

Introduction to Other Power Electronic Devices and Applications

Input current sector

1 or 4 2 or 5 3 or 6

+9 +8 +7 I

1 or 4 +7 +3 +9 +2 +8 +1 II III

+1 +3 +2 IV

Output voltage sector 2 or 5 +6 +4 +9 +7 +5 +6 +8 +9 +4 +5 +7 +8 I II III IV

+3 +2 +1 I

3 or 6 +1 +6 +3 +5 +2 +4 II III

Table 7.6: Selection of switching configurations for combinations of output voltage and input current vectors. and ±1, ±2, ±3 must be used. However, for the current vector to be a angle βi then vectors ±3, ±6, ±9 and ±1, ±4, ±7 must be used. In order to achieve this simultaneously then only the vectors that are common to the two objectives can be used, which is in this case ±7, ±9, ±3, ±1. The ±8, ±2, ±6, ±4 vectors are not common between the two control objectives, and therefore cannot be used. If a similar process is carried out for all desired voltage vectors and current vector angles then the active vectors in each sector can be compiled into a table so that the vectors that can be used to control the current and the voltage can immediately be seen. This appears in Table 7.6. Remark 7.29 Note that only the positive vectors are listed in Table 7.6. This has implications on the calculated duty cycle times for the switches which allows the correct switches to be chosen under conditions where the negative vectors have to be used. Let us consider the use of this table by an example of the generation of a particular output voltage vector and a particular input current angle. Remark 7.30 The magnitude of the current is determined by the output voltage and the load that this voltage is applied across. The input current angle can be controlled by the length of time that we switch onto each of the current vectors. We are able to satisfy both of these requirements because we have four available vectors and four unknown lengths of time that these vectors are going to be switched. Note that in the case of the voltage vectors, there is also the zero vector which is used to control the magnitude of the output voltage (and by implication the input current). The following discussion is with reference to Figure 7.18, which is a detailed picture of sector 1 of Figure 7.171 . This diagram shows the desired voltage vector v o being resolved onto the vectors that are obtainable from the switching of the converter. As with all PWM type systems the v o is obtained in an average sense by switching the converter to produce a vector of average length of |v 0o | and |v 00o |. These two vectors in turn, as can be seen from Figure 7.18 result in III IV an average vector v o as required. The v Io , v II o , v o , and v o vectors correspond to the vector numbers defined in Table 7.6, and are valid for the voltage and current vectors both in sector 1. In order to calculate the switching times we must firstly calculate |v 0o | and 00 |v o |. This is carried out using relatively simple trigonometry, which is reproduced here so that the reader can see the process in detail. Let us firstly calculate 1 We

are also assuming that the current vector ii lies in sector 1 for this example.

+4 +6 +5 IV

7.4 Basic Introduction to Matrix Converters

v Io ; v II o

Sector 1 vo v 0o y

¼=3

®o

v 00o

IV v III o ; vo

±x Figure 7.18: Derivation of the voltage components for a desired voltage space vector.

7-33

7-34

Introduction to Other Power Electronic Devices and Applications |v 0o | . We can write: y

= |v o | sin αo |v | δx = √o sin αo 3 δx 2 0 ∴ |v 0 | = = 2δx = √ |v o | sin αo cos π3 3

(7.85) (7.86) (7.87)

Using the notation of [19] this is expressed in terms of α ˜ o which is the angle of the vector relative to a reference axis that bisects the sector that the vector lies in. Therefore, we can write: π αo = + α ˜o (7.88) 6 and substituting this into (7.87) and manipulating gives: 2 π |v 0o | = √ |v o | cos(α ˜o − ) 3 3

(7.89)

Similarly, for |v 00o |we can write: |v 00o | = |v o | cos αo − δx |v | = |v o | cos αo − √o sin αo 3 1 = |v o | (cos αo − √ sin αo ) 3 √ 2 3 1 = √ |v o | ( cos αo − sin αo ) 2 2 3 2 π π = √ |v o | (cos cos αo − sin sin αo ) 6 6 3 2 π ∴ |v 00o | = √ |v o | cos(αo + ) 6 3

(7.90)

Using (7.88) we can write (7.90) as: 2 π |v 00o | = √ |v o | cos(α ˜o + ) 3 3

(7.91)

Equations (7.89) and (7.91) allow us to write the space vectors for these vectors, not only for sector 1, but also for the other sectors as: v 0o

=

v 00o

=

2 √ |v o | cos(α ˜o − 3 2 √ |v o | cos(α ˜o + 3

π j[(Kv −1) π + π ] 3 3 )e 3 π j[(Kv −1) π ] 3 )e 3

(7.92) (7.93) π

π

where Kv = 1, 2, 3, · · · , 6 and − π6 < α ˜ o < π6 , and the ej[(Kv −1) 3 + 3 ] and π ej[(Kv −1) 3 ] and unit vectors in the direction of the respective space vectors. Let us define the duty cycle of a particular applied voltage space vector: mγ =

tγ T

(7.94)

7.4 Basic Introduction to Matrix Converters

7-35

where γ , I, II, III, IV . Therefore mγ is the duty cycle of one of the particular switching vectors for the matrix converter. As can be seen from Figure 7.18, v 0o and v 00o are composed by switching on 0 III the output vectors v Io and v II and v IV (for v 00o ) 2 for certain o (for v o ) and v o o periods of time over the switching period. Realising this we can write the alternate expression for these vectors as: v 0o

II = v Io mI + v II o m

(7.95)

v 00o

III IV = v III + v IV o m o m

(7.96)

Remark 7.31 Clearly substituting (7.92) and (7.93) into (7.95) and (7.96) one has two equations with four unknowns (the m duty cycles). The other two equations come from considering the angle of the current. Note that the magnitude of the current is controlled by the output voltage and the load. Now let us consider the control of the input current angle. Since we are only controlling the angle of the current, and not its magnitude, then we have to formulate an expression in terms of the desired current angle. Remark 7.32 The principle used to get the equations for the current angle is that the duty cycle equations for each for the switched current vectors has to lead to a zero orthogonal component of current to the desired angle of the current. If this is the case then the only components of current must be in the desired direction of current. The magnitude of the current (as mentioned previously) is not, and cannot be controlled. Firstly let us write the duty cycle expressions for the switching components of the current vector ii : i0i i00i

II = iIi mI + iII i m

=

III iIII i m

+

iIV i

(7.97) IV

m

(7.98)

are the current vectors for the particular sector as defined in where iI,II,III,IV i Table 7.6. The direction of the desired current vector is defined by the unit ˜ vector ej βi . Therefore the vector that is orthogonal to the desired vector is ˜ ˜ ˜ jej βi . Therefore we have to ensure that both i0i jej βi and i00i jej βi are zero, or in other words:
j β˜i j(Ki −1) π II 3 je e iIi mI + iII i m
π ˜ III IV iIII + iIV jej βi ej(Ki −1) 3 i m i m

=

0

(7.99)

=

0

(7.100)

where β˜i is measured from the reference axis that bisects the sector that the current vector lies in, and Ki = 1, 2, · · · , 6. We now have with equations (7.95), (7.96), (7.99) and (7.100) four independent equations with four unknowns – the mI,II,III,IV duty cycles. The manipulations to solve these equations are tedious and messy, and the end result 2 These

are the vectors as defined in Table 7.6.

7-36

Introduction to Other Power Electronic Devices and Applications is[20]: mI mII mIII mIV

˜ o − π3 ) cos(β˜i − π3 ) 2 cos(α (−1)(Kv +Ki +1) √ q cos ϕi 3 π ˜ o − 3 ) cos(β˜i + π3 ) 2 cos(α = (−1)(Kv +Ki ) √ q cos ϕi 3 ˜ o + π3 ) cos(β˜i − π3 ) 2 cos(α = (−1)(Kv +Ki ) √ q cos ϕi 3 π π ˜ cos( α ˜ 2 o + 3 ) cos(βi + 3 ) = (−1)(Kv +Ki +1) √ q cos ϕi 3

=

(7.101) (7.102) (7.103) (7.104)

where ϕi is the desired phase angle between the current vector and the input voltage vector (which is measured), and q ,the instantaneous voltage transfer |v | ratio, which is q = vo . Therefore ϕi = αi − βi where αi is the angle of the | i| input voltage relative to the bisecting reference on the current vector hexagon. Remark 7.33 One can see from the (−1)(Kv +Ki +1) and (−1)(Kv +Ki ) that one of the duty cycles can be positive and the other negative. A negative duty cycle means that the negative vector is chosen (e.g. -9 instead of +9 if in sector 1 for the voltage). Remark 7.34 Another constraint on the feasibility of the strategy is that the sum of the absolute values for the four duty cycles must be lower than unity – in other words the one times for the various vectors have to be less than the control period. This can be written mathematically as: I II III IV m + m + m + m ≤ 1 (7.105) If this condition is less than one, then the remainder of the time is filled by applying a zero voltage vectors. If (7.101)–(7.104) are substituted into (7.105) and some manipulations are carried out one can get the following expression: √ 3 |cos ϕi | q≤ (7.106) 2 cos β˜i cos α ˜o which is the theoretical maximum instantaneous voltage transfer ratio. Therefore at any point of calculating the duty cycles one cannot be demanding a voltage transfer ratio larger than this value. In the case of balance supply voltages and output voltages, the maximum transfer ratio occurs when (7.106) is a minimum (which implies cos β˜i and cos α ˜ o are equal to 1, which in turn implies that the power factor of the load is unity) which gives: √ 3 q≤ |cos ϕi | (7.107) 2 which has the theoretical maximum value for matrix converter of 0.866 under the condition of unity power factor.

7.4 Basic Introduction to Matrix Converters Remark 7.35 Having the ability to control the input power factor to be other than the output power factor comes at the price of decreased output voltage. One can see from the denominator of (7.106) that if cos β˜i = cos α ˜ o = 1 this√means the αo˜−β˜i = π/6 then the output power factor is unity (i.e. cos ϕo = 3/2 = 0.866). If the input power factor is also unity then cos ϕi = 1 and therefore √ 3 q ≤ 2 . This demonstrates that it is the change of the input power factor that results in the loss of the voltage transfer ratio. If other input power factors are required then the voltage transfer ratio will decrease from this value. Once the duty cycles have been calculated then the firing sequence of the devices has to be determined. Consider the situation that we have investigated as an example above – i.e. the desired output voltage vector and in the input current vector lie in sector 1. We shall assume that the active switching sequence is to achieve the desired output voltage and input current power factor is +1, -3, -7, +9. The other vectors that come into play here, depending on the output voltage magnitude, are the zero vectors. It can be verified that there in only one switching sequence characterised by one one switch commutation for each switch change, and that is 03 , −3, +9, 01 , −7, +1, 02 . If one uses this switching sequence in a double sided symmetrical switching pattern (as is done for traditional PWM inverters), then the switching pattern is simply this switching pattern reversed for the second half of the cycle. Figure 7.19 shows the switching pattern and the associated duty cycles and switches used. Note that in this diagram the switching times for the particular vectors are denoted as tζ where ζ is the vector number – i.e. 3, 9, 7 etc. As can be seen from the figure there are 12 switching over one control cycle. This switching technique is called a symmetrical SVM, and utilises all of the zero switching sequences. An alternative is to use an asymmetrical switching sequence which only uses one of the switching sequences. In this sequence the switches of one of the columns in Figure 7.15 on page 721 do not change state, and the number of switch commutations in each cycle period is reduced to 8 (SAa , SBa , SCa are always on).

7.4.4

Implementation Issues

Thus-far we have considered issues related to the modulation strategies for the matrix converter. Throughout this discussion the interested reader has probably been asked themselves the questions: “but how does one implement all of this”? There are a number of different aspects that must be addressed to answer this question. We shall probably present the most important of these. 7.4.4.1

Bidirectional Switches

The switches used in matrix converters are bidirectional as discussed in the initial introduction. Most of the common semiconductor switches available on the market are only capable of blocking current in one direction. In order to implement a matrix converter one must have a bidirectional switch. There are several ways to design bidirectional switches using technologies that can only block in one direction. Figure 7.20 shows a technique that involves the use of only one switch, but required four diodes. The function of the diodes is to direct the current only into the collector of the IGBT so that it is always presented with a positive voltage at this terminal.

7-37

7-38

Introduction to Other Power Electronic Devices and Applications

Output phase a

mAa 2

mCa 2

A

C

A

mCb 2

b

C

C

A

A

C

03

¡3 +9 t2 2T

A

C

t9 2T

A 01 t01 2T

T 2

mBa 2

B

B

A

B

B

B

mBc 2

B

B

B

¡7 +1

02

02

t02 2T

t02 2T

t7 2T

t1 2T

A

A

A

A

A

mAb 2

B

A

B

C mCb 2

A

A mAc 2

mBc 2

B

mCa 2

mAa 2

mBb 2

mBb 2

mAc 2

C

t03 2T

A

mAb 2

mAa 2

c

A

mBa 2

C

C

mAa 2

B

A

C

+1 ¡7

01

+9 ¡3

03

t01 2T

t9 2T

t03 2T

t1 2T

t7 2T

C

t2 2T

C

T 2

Figure 7.19: Double sided switching sequences for a matrix converter over one control cycle.

Figure 7.20: Diode bridge bidirectional switch cell.

7.4 Basic Introduction to Matrix Converters

7-39

Body diode

Common emitter

Common collector

Figure 7.21: Common emitter and common collector back-to-back bidirectional switches.

Remark 7.36 The diode switch cell has the advantage that only one switching device is required. This minimises the number of gate drivers required for the system. However there are two significant disadvantages of this arrangement: a. When the device is on there are three series devices – i.e. two diodes and the IGBT switch itself. Therefore the losses in the switch are higher than other strategies. b. When the switch is turned on there is no way of controlling the direction of the current through the cell – i.e. the cell operates as a normal switch. The inability to control the current direction has implications with respect to commutation strategies. The above two disadvantages are important enough that this cell is not commonly used. The common emitter and common collector switch cells are shown in Figure 7.21. This cell arrangement consists of two diodes and two switches connected in anti-parallel. The diodes are required to provide the reverse blocking capability.

Remark 7.37 There are several advantages of the common emitter /collector switching cells compared to the diode based cell: a. There are only two devices in the conduction path, therefore the switches are more efficient. b. The current direction through the device can be controlled. This occurs because the appropriate switch has to be turned on for current to conduct in the forward direction for this switch. This ability is used in the commutation algorithms as we shall see later.

common ter and collector cells

emitcommon switch

7-40

Introduction to Other Power Electronic Devices and Applications The most obvious disadvantage of these cells relative to the diode cell is that they have two active devices. The choice of the use of the common emitter version of the switch cell versus the common collector version is no immediately obvious. In the case of the common collector version, the emitters of the switching devices are connected to the incoming and outgoing lines of the converter. Therefore one needs three isolated power supplies with the common for each of the supplies connected to one of the three incoming lines, and three isolated power supplies with the common of each of them connected to the one of the three outgoing lines. Practical issue 7.1 In practice the use of only six isolated supplies for the common collector bidirectional switch is not viable because of the need to minimise stray inductance. The common emitter version of the switching cell requires on isolated power supply for each switching cell (i.e. a total of nine). The common emitters form the ground point for the supply. The common emitter cell is the one most commonly used. The above discussion has been with respect to implementing the bidirectional cells using discrete components. It is also possible to build an integrated matrix converter module, similar to the intelligent power modules used for three leg inverter systems. This has been done by EUPEC using devices connected in the common collector configuration, and is now commercially available. this type of packages has distinct advantages relative to discrete layouts in the lower stray inductances. The switching devices (IGBTs) discussed thus-far, due to the presence of parasitic internal diodes, do not have reverse blocking capability. However, devices such as the MOS turn-off thyristor (MTOs) do have reverse blocking capability, and therefore the bidirectional switch can be built using two devices in anti-parallel. 7.4.4.2

Current Commutation

Basic switching rules were outlined in Section 7.4.2 on page 7-21 which reduced the possible 512 switching combinations down to 27. These switching rules arose from electrical considerations of various switch combinations. However these same electrical considerations also have an influence on the commutation from one switch combination to another. Remark 7.38 “Reliable current commutation between switches in matrix converters in more difficult to achieve than in conventional VSIs since there are no natural freewheeling paths”[16].

commutation

To understand the issues consider Figure 7.22 which shows two different situations of two input phases and one output phase and commutation is occurring from one input phase to another. In Figure 7.22(a) both the switches have been closed onto the same output leg. Clearly this will result in a short circuit between the two input phases and consequent destruction of the switches. Figure 7.22(b) shows the alternative situation where both the switches have been opened. If the switches were carrying current at the time that were opened the input and output inductances would result in a very large voltage spike and destruction of the switch.

7.4 Basic Introduction to Matrix Converters

7-41

SW1

SW1

SW2

SW2

Load (a)

Load (b)

Figure 7.22: Short and open circuit situations that can occur during commutation.

Practical issue 7.2 Any practical commutation strategy has to avoid both the situations shown in Figure 7.22. In order to avoid the situations that are shown in Figure 7.22 a number of different commutation strategies have been devised. Two obvious ones are: • break before make approach – the outgoing switch is opened before the incoming switch is closed. This prevents the short circuit situation, but because there is an overlap period when both switches are open (to account for the charge storage turn-off delays of the semiconductor switches) then high voltages can occur due to inductive effects. Extra clamping circuitry is required to prevent these voltages from getting too high. • make before break approach – this is the dual of the previous case and results in a momentary short circuit between the phases. One needs interphase reactors to prevent the short circuit during the switching transient. These inter-phase reactors can be quite large. These two strategies, whilst they work, are not all that satisfactory for the reasons cited above. This lead to the development of the 4 stage commutation process, with the step being: a. Turn off the off-going non-conducting switch. This prevents current reversal, which could otherwise occur during the rest of the commutation process. b. Turn on the on-going conducting switch. At this point one has the offgoing conducting switch on, and the on-going conducting switch on. A short circuit is not generated because the process is utilising the fact that one can control by the choice of device in the switch cell to activate the direction of the current that can flow through the switch cell. c. Turn off the off-going conducting switch. The on-going conducting switch,

7-42

Introduction to Other Power Electronic Devices and Applications

SAa2

A

SAa1

VA

iL a

VB

SBa2 B

Load

Va

SBa1

Figure 7.23: Two phase switching matrix example. if it wasn’t already conducting the current3 , will now be forced to conduct the load current. d. Turn on the on-going non-conducting switch. This then allows natural current reversal to occur through the switch if required. In order to understand this process in more detail consider Figure 7.23 of two switching cells connected to two phases and a single output line. The state and timing diagram for the commutation process is taken directly from [16], and appears in Figure 7.24. The nomenclature iL > 0 means that the current is in the direction shown in Figure 7.23. Once can see from Figure 7.24 that the switching sequence proceeds through the four steps outlined above. Notice that there is a point where SAa1 ad SBa1 are both closed. However, a short circuit cannot develop because the SXa1 switches can only carry the iL current in the direction shown in Figure 7.23. Therefore if VA > VB then the diode in series with SBa1 will ensure that the device is turned off and no short can develop. SBa2 is already off as we have not turned it on. Similarly if VB > VA then SAa1 will be off, and SAa2 has not been turned on. Remark 7.39 One can see that the four stage commutation process exploits the fact that the switches have the extra degree of freedom at that direction of current flow through the switch is under direct control.

Remark 7.40 One variant of this technique is to only gate the conducting device. By doing this the sequence can be shortened since the initial (1100) state is not there, but instead it is (1000). Similarly the final state in the example of Figure 7.24 becomes (0010). Therefore only the top path of two transitions occurs. 3 The on-going conducting switch may not have been conducting current because the voltage across the on-going switch device may be been such that the device is effectively reverse biased.

7.4 Basic Introduction to Matrix Converters

SAa

1

0

SBa

0

1

SAa1

1

1 1 0

0

SAa2

1

0 0 0

0

SBa1

0

0 1 1

1

SBa2

0

0 0 0

1

7-43

td Timing diagram iL > 0

iL > 0

1 1 0 0

iL < 0

Steady state

1 0 0 0

1 0 1 0

0 0 1 0

0 1 0 0

0 1 0 1

0 0 0 1

Transitional states

X X ) X X

SAa1 SAa2 SBa1 SBa2

0 0 1 1

Steady state

State transition diagram

Figure 7.24: Four step commutation process between bidirectional switch cells in Figure 7.23.

7-44

Introduction to Other Power Electronic Devices and Applications Practical issue 7.3 One practical issue with the four stage and two stage commutation sequences is that they rely on accurate knowledge of the current direction in order to determine which devices to turn on. This is particular the case with the two stage process, as there is no natural current reversal in this sequence (i.e. the two anti-parallel devices in the switch are no both actively gated at the same time). One simple technique used to prevent problems is to no carry out any commutation when the absolute value of the current is below a certain value. This prevents ambiguity of current direction form upsetting the commutation. However this technique results in distortion at low currents. There are other techniques using voltage measurements across the devices that solve this problem 7.4.4.3

Input Filters

Filters are required at the input of a matrix converter in order to reduce the switching harmonics present in the input current. This filter must have the following characteristics[16]: a. have a cutoff frequency lower than the switching frequency of the converter; b. minimise it reactive power at the grid frequency; c. minimise the volume and weight for capacitors and chokes; d. minimise the filter inductance drop at rated current in order to avoid a reduction in the voltage transfer ratio. The matrix converter was originally envisaged as a pure silicon converter solution, however in reality the passive filtering components become a significant part of the design. It has turned out in some converter designs that the LC components of the filter have been comparable in size to those required for a conventional DC link based inverter. An addition issue related to the input filters is that they can cause transient over-voltages on start-up due to ringing of the filter. In order to prevent this series resistors are used during the start-up phase, and these are shorted once the converter is running. Figure 7.25 shows a matrix converter with the LC input filters. Notice the damping resistors at the input. 7.4.4.4

Over-voltage Protection

Over-voltages can occur in matrix converters for the following reasons: • input voltage transients interacting with the input filters; • interruption of over-current faults when the load has inductance. The usual solution to this problem is to connect a diode based clamping circuit to the input and output of the converter. Figure 7.26 shows this general configuration. As can be seen it is simply a rectifier circuit. Because a conventional converter already has such a circuit as an implicit part of its design, there is no need for an explicit protection circuit. There are some other “more clever” strategies that are employed that try to achieve the same result with less components.

7.4 Basic Introduction to Matrix Converters

7-45

A SAa

SAb

SAc

SBa

SBb

SBc

SCa

SCb

SCc

B

C

a

b

c

Figure 7.25: Matrix converter input filters and damping resistors.

LC filter

Matrix Converter

50Hz supply

Motor +

Diode clamp circuit

Figure 7.26: Matrix converter with over-voltage diode clamp protection.

7-46

Introduction to Other Power Electronic Devices and Applications

7.4.5

Comments

After almost three decades of research the modulation and commutation strategies and control methods for the matrix converter are reasonably mature. Two early drawbacks of the converter were the lack of a suitably packaged bidirectional switches and the large number of semiconductor switches required. Over recent years these limitations has largely been overcome with the introduction of power modules which include the complete power circuit. A remaining issue is the size of the passive filtering components in the converter – the dream of a pure silicon converter has not been realised. Research is continuing on reducing the size of the filtering components. When introduced approximately 30 years ago the matrix converter has the potential to be a superior converter, in that one had a bidirectional converter which could control harmonics at the input and output, as well as the input power factor. However, in the intervening years other converters did not stand still, and the active front end (AFE) on the conventional inverter also offers the same capabilities. This is a variant of a very mature technology. In addition the AFE inverter also has implicit ride through capability when there are supply dips due to the presence of a DC link capacitor. As it stands at the moment the matrix converter is used for niche applications. The US military are investigating its use in the electric tank, where its compact size and robust because of the absence of a DC link capacitor may be an advantage. A motor and drive manufacturer has also integrated a matrix converter into a motor frame, where again the lack of a large DC link capacitor is an advantage.

Chapter 8

Grid Connected Converters and Renewable Energy Systems 8.1

Introduction

An excellent resource for this chapter is the new book [21]. This book concentrates specifically on issues related to the use of converters to interface photovoltaics and wind turbines to the electricity grid. Although it has been written from a European perspective, nevertheless most of the material is relevant to Australia. Much of the material in this Chapter is based on content from this book. The clean production of energy is becoming increasingly important. In fact the production of low cost, environmentally friendly energy is probably the greatest challenge of our time. The consensus amongst creditable climate scientists is that man made greenhouse gases are a significant contributor to the currently measured rise in global temperature. Therefore low or zero emission production of energy is going to become increasingly important as we move into the future. Even if one is skeptical about the climate science, the sustainable use of the earth’s resources is a worthy goal in its own right. The availability of low cost energy and a system to distribute this energy is a key contributor to the lifestyle that we enjoy. It will also be a key factor in changing the lifestyles of those in the 2nd and 3rd world as they move towards the lifestyle which we enjoy. Therefore the current issues surrounding clean low cost energy are not going to go away – to the contrary they will be exacerbated. We can all see this happening with the rapid development of China and India. These factors mean that the issues that will be discussed in this Chapter are of increasing importance. This Chapter will not be attempting to consider the complex economic factors that surround the transformation of the worlds energy production systems away from fossil fuels, and towards sustainable sources. Instead it will concentrate at a much lower level on the technical issues of how to interface renewable sources to the electricity grid. Issues associated with the control of an electricity

8-2

Grid Connected Converters and Renewable Energy Systems grid with high renewable penetration will only be considered in the form of grid codes that are still under development. The remainder of this section will consider the current statistics related to the use of wind power and photovoltaics.

8.1.1

Wind Power

Wind power is a fairly mature technology for renewable generation. The nice feature about this technology is that energy can be available at all times of the day (although wind resources tend to be more available during the day time). This technology developed first because, in principle, the technology required has been known for a long time – blade design, induction generators, towers. The use of power electronics in wind power has been a more recent development as power electronics became cheaper, and the demands on the wind turbines motivated the exploration of the use of this technology. Even though wind power is a mature technology, the cost of the energy has limited its penetration in many countries. Without subsidies it was simply too expensive compared to the fossil fuel technology. This is particularly the situation in Australia. The situation is Europe has been somewhat different, where subsidies have been available for many years in countries such as Denmark. Government support for wind power technology lead to the development of a wind turbine industry in Denmark that is now selling turbines on the international market.

8.1.2

Photovoltaics

Photovoltaics is also a fairly mature technology for renewable energy. Having said that, its degree of penetration is nowhere near that of wind, although it is growing. Surprisingly, Europe has a fairly high penetration of photovoltaics even though in many parts of Europe there resource is not that good. Of the European countries, Germany has the most PV systems installed. Australia has excellent solar radiation resources, but as yet has not exploited this to the extent that the resource availability would indicate. However, this is changing as more domestic photovoltaic systems are being installed (supported by generous government subsidy schemes), and some large scale solar array projects are in the offing.

8.1.3

Outline and Scope of this Chapter

This chapter, by virtue of the fact that it is only a small part of a general course on power electronics, is limited in scope and depth. Having said that, it will attempt to at least cover, to some degree, the key issues in the use of converters to interface photovoltaics and wind turbines to the grid. It should be noted that this Chapter concentrates on the technical aspects of grid interfacing, and the politics and economic aspects of renewables is not the main focus. Note 8.1 The presentation in this chapter is limited to grid interfaced systems. The other class of systems that use renewables are microgrid systems. These are distinguished by the fact that they operate separate from a large infinite bus that

8.2 Photovoltaic Inverters is the grid system. This fact leads to a lot of interesting control issues, some of which are: • getting converters to share load on the grid; • issues related to handling the variable input energy available in wind and solar systems when there is not the large reverse of the gird there to buffer out these variations; • reliability and security of supply; • power quality issues. There are also broader issues involved in these systems as well. Because one is not constrained by the grid then, for example, consideration can be given to whether the underlying system of the microgrid is DC voltage based. n With both photovoltaic and wind turbine interfacing the same topics will be covered. Grid requirements, as legislated, will be briefly introduced and their significance highlighted. Then the specific issue of synchronizing the control strategies to the grid system will be introduced. This is very much a specific detail, but of great practical importance for the development of high performance control strategies. Basic control strategies for grid connected power electronic systems will be introduced, and some of the higher level control strategies that sit on top of the basic algorithms will be introduced (such as Maximum Power Point Tracking for Photovoltaic systems). This Chapter will hopefully give you a feeling for how power electronics is an enabling technology for the introduction of renewable energy systems.

8.2 8.2.1

Photovoltaic Inverters Review of Power Electronic Configurations for Grid Connected Converters

There are a number of possible topologies that can be used for photovoltaic converters. These topologies can be divided into two broad categories based on whether they are: • Three phase converters – generally used in high power photovoltaic applications • Single phase converters – generally used in domestic and lower power applications These two categories can then be further divided into two main types of converter topologies: • Galvanically isolated converters • Non-galvanically isolated converters Galvanic isolation is typically achieved by either using a mains frequency transformer on the mains frequency side of the converter, or alternatively using a high frequency transformer as part of a DC-DC converter in the midst of the overall

8-3

8-4

Grid Connected Converters and Renewable Energy Systems converter structure. Sometimes a boost converter is required in a photovoltaic converter system (if the voltages from the panel are no sufficient to connect to the mains), and consequently galvanic isolation is achieved as a byproduct of this. In Australia up until relatively recently most domestic scale photovoltaic converters were galvanically isolated – usually with a mains frequency transformer placed on the grid side of the output filter. This was the general practice because of the obvious safety benefits associated with isolation of the PV array from the mains supply that occurs with such an arrangement. In Europe the situation is different, with non-isolated domestic PV converters being commonplace for some 15 or more years. One obvious question to ask at this juncture is: “What are the pros and cons of galvanic versus non-galvanic isolated converters?” The obvious pro of the transformer based systems is the safety that ensues from its inclusion. However there is (literally) a price to pay for this, namely: • Higher cost for the converter. • The unit is bulky and heavy. • The converter loses about 1% to 2% in efficiency due to transformer losses. The safety issue is still there, but set against this is the fact that transformerless converters have been used safely in Europe for over 15 years, and their voltages are in many case similar to ours. So the balance of safety versus economic and efficiency gains has seen the increased use of transformerless systems in Australia [22]. In addition to the particular hardware architecture of the inverter there is a hierarchical control structure to control. A generic hardware and control structure block diagram is shown in Figure 8.1. Not all PV systems will have all of the hardware components. For example, if the PV string can produce high enough voltages then the boost converter stage may not be required, and as we have noted some converters are directly connected to the grid, and therefore there is no transformer present. The main hardware components of the PV system are fairly obvious. Of course there are the PV panels themselves. They are usually connected together in a string so that an appropriate voltage is generated from the array. What is an appropriate voltage? In many cases this will be a voltage that will give sufficient headroom in voltage to allow a DC-AC conversion to the grid without having to have a boost converter. The presence of the boost converter obviously leads to extra complexity and lowers the efficiency of the system. The boost converter, as eluded to in the previous paragraph, is required if the PV string voltage is below the voltage required for the DC-AC conversion. There may be a variety of reasons for this being the case, and depends on the application. The next component in the hardware structure is the DC-AC converter. There is a variety of structures that can be used for this component of the system, the details of which are the main subject of most of this Chapter. Whatever the DC-AC converter is, the next component is a filter. In the case of the diagram it is shown as an LCL filter as it is the most common filter used for this application. The filter is the purpose of removing the switching harmonics

8.2 Photovoltaic Inverters from the output waveforms so that grid harmonic standards are satisfied. Notice that the AC feedback measurements occur after the filter so that there are no switching harmonics to corrupt them. Remark 8.1 It should be noted that the LCL filter is a more elaborate filter. In some cases a simple inductor suffices in order to achieve the filtering required. The use of this has the added advantage that the dynamics introduced by the filter are less complex, which simplifies the control. n The control structure in Figure 8.1 is quite complex, and is one of the features of PV power electronic systems that set then apart from variable speed drives. The control in the PV case in some senses is more complex than variable speed drive control – the PV systems have a deeper hierarchical structure. The PV control is divided into a number of sub-blocks: Basic grid control This block as the name implies, provides the basic control functions to interface the inverter onto the grid. It allows synchronization of the converter output voltages to the grid voltage, controls the DC link voltages so that enough voltage is available for the current control to work. These functions have a lot of similarity to variable speed drive converter control functions. PV specific functions This block contains a number of control functions that are unique to the PV application – MPPT (Maximum Power Point Tracking) is the name given to a class of algorithms that control the current from converter so that the maximum power is obtained from the PV array under all irradiation conditions; anti-islanding protection is required to detect if the a circuit breaker has been opened on the grid isolating the section of the grid where the PV array is. The PV array should disconnect under this condition; and finally some monitoring functions of the PV array itself to check on cell performance. Ancillary functions These are high level functions that may or may not be performed depending on the sophistication of the PV system. For example active filtering of harmonics can be performed; micro-grid control functions such as control of Vars or power factor at the connection point to the grid. Note 8.2 In this chapter we shall only be considering in detail the basic converter functions in this control hierarchy. n 8.2.1.1

How do photovoltaic devices work?

In this section we will briefly consider the basic mechanism that allows a semiconductor diode to generate a voltage, conduct current, and ultimately generate power. This is provided simply as background material, and is not really essential to know with respect to the power electronics side of the system. However, as a philosophical point, engineerings should not be considering systems to be black boxes, and hopefully your natural curiosity will have you asking the question as to how this all works. You should have enough background from your basic semiconductor Physics courses to understand the basic principles of operation.

8-5

8-6

Grid Connected Converters and Renewable Energy Systems

PV Panels string

DC-DC Boost converter

+

IP V

VP V

DC-AC PWM-VSI

PWM

VDC

LCL Low Pass filter

PWM

Grid Current VDC synchronization control control Basic grid connected converter functions MPPT

Active filter functions

X’former and Grid

Ig Vg

Anti-islanding Grid/PV plant protection monitoring PV specific functions Micro-grid control

Grid support (V/F/Q)

Ancillary functions

Figure 8.1: Block diagram of a generic PV system [21] Remark 8.2 Even though I have just stated that knowing the fundamental operational principles of photovoltaics is not really necessary for this course, these principles have a profound influence on the control strategies used for photovoltaic systems. The VI relationship of a solar cell, which is irradiation dependent, is non-linear. It means that there is a optimal point of operation to get the maximum power out of a cell for a particular irradiation level. The algorithms to find this point at called Maximum Power Point Tracking (MPPT) algorithms, and they are used to determine the current set points for the power electronic controllers that interface to PV array to the grid or load. n Remark 8.3 Another influence that the basic operation of a solar cell has on the design of a power electronic system is related to the number of converters in a large system. The irradiation on large arrays of solar cells in many cases will not be uniform due to partial shading from clouds for example. Partially shaded cells become a loading on the other cells in a series string, and reduce the efficiency of the system. This can be partially catered for if the cells are connected together into smaller arrays where maximum power point tracking can be applied to each subsystem separately. n Figure 8.2 shows the band gap diagram of a pn junction (i.e. a diode band gap). As can be seen from the diagram the doping to produce the p and n materials effectively moves the Fermi level of the semiconductors. Since the p and n materials are connected together then the only stable situation is that the Fermi level is constant on both sides of the junction. This is forced by diffusion which is a consequence of the different concentrations of holes and electrons in the materials due to the doping. As a result of this diffusion process and electric field is developed in the material which drives the carriers in the opposite direction to the diffusion process. The equilibrium is reached when the

8.2 Photovoltaic Inverters

8-7 Centre of junction

Space charge region Photon

Conduction band Electron Forbidden Energy gap

Metal ohmic contacts Fermi level

n semiconductor

Metal ohmic contacts

Hole

p semiconductor Valence band

Figure 8.2: Band gap diagram of a solar cell (pn junction).

drift due to the space charge equals the diffusion current. The voltage produced by the electric field ε is the contact potential of the diode, and is typically 0.6 to 0.7 volts for Silicon. Remark 8.4 Normally the contact potential cannot be seen from the outside of the diode. If one places, for example, a voltmeter on the diodes terminals one will not see any voltage and no current will flow. The metal-semiconductor contacts of the probes on the semiconductor essentially cancel the internal electric field. This should not be a surprise, because if there was an external voltage then a current could flow and energy could be extracted. This would violate the conservation of energy, as there is no source of energy in the diode. n If photons from a radiation source can incident on the pn junction around the space charge region as shown in Figure 8.2, and if the energy of the photon is larger than the band gap (forbidden gap) energy for the particular semiconductor material (the energy of a photon is E = hf where h is Planck’s constant, and f is the frequency of the radiation), then an electron can be excited from the valence ban into the conduction band of the material. This process forms a hole in the p type material, and an free electron is generated in the p material. If this occurs in the space charge region, or near it, then the electron will be sweep by the space charge electric field towards the n material. It effective rolls down the potential gradient as shown in the figure. In this situation current can flow in an external circuit, and energy can be provided as the energy is coming from the photons striking the junction area and generating the carriers.

8-8

Grid Connected Converters and Renewable Energy Systems 8.2.1.2

Equivalent Circuit of a Solar Cell

As can be seen from the previous explanation the mechanisms within a solar cell are quite complex, and when it comes to the fine detail, it involves quantum mechanics. In order for electrical engineerings to have a simpler way of explaining the properties of a solar cell or array of solar cells, and equivalent circuit model is needed. This model can be developed from the normal equation for the current through a diode. The normal diode equation is [23]: qV

ID = I0 (e nkTK − 1)

(8.1)

where: ID

,

the diode current -positive when forward biased

I0

,

diode the reverse saturation current

q

,

the charge of and electron = 1.6 × 10−19 C

k

,

Boltzmann’s constant = 1.38 × 10−23 J/K◦

TK

,

the temperature in Kelvin

n ,

the diode ideality factor 1 → 2

V

the voltage across the diode - positive for forward bias

,

Under normal non-illuminated circumstances when the diode is reverse biased then the reverse saturation current is the only current that flows. This can be seen from (8.1) when V is negative and the expression becomes: ID =

I0 qV

e nkTK

− I0 ≈ −I0

(8.2)

Remark 8.5 The I0 current is essentially the current due to the generation of hole-electron pairs within the Lp and Ln distances of the space charge region. The Lp and Ln are the average distance a hole and electron respectively can diffuse as minority carriers before recombining. Therefore if minority carriers are generated within Lp,n distances of the space charge region then they can make it to the space charge region and be swept across the junction by the space charge electric field there. n We shall briefly go through the development of the basic equations for a solar cell, and this will lead onto the equivalent circuit for the device. This presentation is not comprehensive and the interested reader is encouraged to look at the reference (or other texts on semiconductor physics) to find out more details. The following discussion is with respect to Figure 8.3. This diagram shows a junction that is optically irradiated. The junction in Figure 8.3(a) is reverse biased and is being irradiated with energy that is greater than the band-gap of the material. Therefore electron-hole-pairs (EHP) will be generated. Figure 8.3(b) shows a section of the n material on the right side of the junction. As mentioned previously Lp is the mean diffusion distance of holes in the material before recombination. Therefore if the irradiation is generating gop holes/cm3 /sec then these carriers will be able to diffuse to the space charge

8.2 Photovoltaic Inverters

E

8-9

R W n

p

n A

(a)

V

(b)

(c)

Figure 8.3: Optical generation of carriers in a pn junction. region and then be swept to the p side of the junction by the electric field in the space charge region. The number of carriers involved in this current is ALp gop . Similarly in the p material we have ALn gop electrons generated per second within Ln of the space charge region. Therefore the total current flowing due to this optically generated current is: Iop = qAgop (Lp + Ln )

(8.3)

Remark 8.6 If there are gop excess EHP (Electron-hole-pairs) are being generated within say n material, then these excess carriers will diffuse in both directions – i.e. 50% will go in one direction, and 50% in the other if one assumes, for simplicity, a two dimensional diffusion process. However, if the n material is being uniformly illuminated then this will clearly balance out as this diffusion in each direction is occurring at all points in the material, and therefore there is no net diffusion. However, due to the boundary at the space charge region this countering of the diffusion in one direction with diffusion in the other no longer occurs. In the case of Figure 8.3(a) all of the hole carriers within Lp of the space charge region can diffuse to the space charge region without a counter group of holes from Lp to the left of the beginning of the space charge region countering the hole flow. The problem with this last statement is ‘all of the hole carriers’. We have just said that 50% go in one direction and 50% in the other. This would mean that only 50% of the holes generated within Lp of the space charge region would be contributing to the current. This is true if both diffusion directions are feasible. In the case of the holes at the extreme right edge of the n material the holes cannot diffuse to the right as there is no material to diffuse into. Therefore all of the hole have to be diffusing to the left. At the space charge region boundary holes are being swept across the region. We do not have the same end effect here that is occurring at the right ohmic contact – there is somewhere for the left diffusing holes to go. The push-back hole current flow from the right edge of the material affects the overall net hole flow from left to right in the material. If the material is in steady state then the hole flow to the space charge region if the normal 50% probability base flow plus the 50% push-back effectively from the other end of the material. Therefore all

8-10

Grid Connected Converters and Renewable Energy Systems of the carriers in the ALp volume are being swept across the space charge region boundary for the material concentrations to be in a steady state under optical excitation. n Using this expression we can augment (8.1) as follows: qV

ID = I0 (e nkTK − 1) − qAgop (Lp + Ln )

(8.4)

Remark 8.7 The gop rate is directly related to the number of photons of the correct energy hitting the Lp,n are from the junction. As can be seen from (8.4) the qAgop (Lp + Ln ) is effectively a current source whose value is related to illumination. n If the diode is short circuited then V = 0 in (8.4), and therefore there is a reverse current flowing of Iop . If the diode is open circuited then ID = 0 and therefore (8.4) can be rearranged as:   qAgop (Lp + Ln ) nkTK ln +1 (8.5) Voc = q I0 Remark 8.8 If would appear from (8.5) that Voc can increase without limit as gop is increased. However this is not the case. The reverse saturation current is due to the thermal creation of minority carriers within the Lp,n distances of the space charge region. Therefore:   Lp Lp I0 = qA pn + np (8.6) τp τn where pn is the steady state minority concentration of holes in the n material, and np is the steady state minority concentration of electrons in the p material, and τp and τn are the respective minority carrier lifetimes. Now pn and np are determined by the doping and the temperature. However the τp and τn terms become smaller as the EHPs due to optical generation increase, and therefore the n terms pτnp and τnp become larger. This clearly means that I0 becomes larger and qAg

(L +L )

op p n in (8.5) will stabilise at some value – it does not therefore the term I0 continue to increase. It turns out that this maximum value of Voc , regardless of the gop value, is V0 , the contact potential of a diode (typically about 0.6 V). This makes sense as V0 is the maximum voltage that can appear across a diode in forward bias. n

The above discussions can lead to the following equivalent circuit for an ideal solar cell. Note that this equivalent circuit comes directly from the expressions developed above. As noted previously, the gop optical EHP generation operates virtually like a current source, and its value is basically the short circuit current of the cell. Secondly the open circuit voltage of the device is limited to the contact potential, regardless of the gop value. This leads to the following ideal equivalent circuit shown in Figure 8.4. As can be seen the short circuit current is IL and the open circuit voltage is V0 . Clearly if a load is place across the cell then as it is increased more of the irradiation current will be diverted into the diode. The current through the diode is related to the output voltage by (8.1). In a real solar cell there are other effects. For example the solar cell has a series resistance (RS ) which is related to the resistance of the semiconductor

8.2 Photovoltaic Inverters

8-11

I

V

Figure 8.4: Equivalent circuit of an ideal solar cell.

I

V

Figure 8.5: Equivalent circuit of a non-ideal solar cell. materials as the current flows from the cell out of it terminals and into the load. There is also a shunt resistance (RSH ) which is related to leakage currents around the cell. We want RS to be as small as possible, and RSH to be as large as possible. Figure 8.5 shows the non-ideal model of the solar cell that includes these components. From Figure 8.5 one can write the following expressions for the current and voltage: I = IL − ID − ISH (8.7) and the current through the diode and the shunt resistor is governed by the voltage that appears across them, namely: VD = V + IRS

(8.8)

We can determine the current through the diode from (8.1), and the current through RSH is: VD ISH = (8.9) RSH Therefore the solar cell output current is:    q(V +IR )  S V + IRS −1 − I = IL − I0 e nkTK (8.10) RSH

8-12

Grid Connected Converters and Renewable Energy Systems

+ Solar cell

Solar cell series array

Figure 8.6: Circuit symbols for a solar cell and a series array of solar cells. Remark 8.9 Equation (8.10) cannot be solved in closed form, and has to be solved numerically for I. In addition the parameters in the equation cannot be directly measured, and usually have to be estimated from terminal measurements of the device under various test conditions. n Remark 8.10 The temperature of the cell also has important effects on its operation. If the temperature increases then the Voc of the cell will decrease. This in turn decreases the maximum possible output power. Therefore one wants the cell to operate at lower temperatures rather than high temperatures. n Practical issue 8.1 One thing that can be surmised from the model is that if solar cells are connected in series (as they usually are to increase the output voltage), and if one or more cells are not illuminated as much as others, then current will be forced up through RSH and RS resulting in a loss of power for the series array, and heating of the poorly illuminated solar cell. The reverse voltage from this current can result in the breakdown of the pn junction. The voltage for this is from 10 to 30 volts. Therefore one shaded cell can absorb the voltage produced by 20 or more unshaded cells. Reverse voltage diode clamps are usually place around practical solar cell arrays to prevent this from occurring.n The circuit symbols for an individual solar cell and a series array of cells are shown in Figure 8.6. The other important aspect of the operation of solar cells and arrays is how to extract the maximum power from the devices. The IV characteristics of a solar cell can be gleaned from Figure 8.3(c) by inverting the curves in the bottom right hand quadrant (this is the quadrant that the system operates in when the cell is generating power). Redrawing this section of Figure 8.3(c) we get Figure 8.7, which also shows the power diagram and the figure-of-merit power rectangle (shown in grey). The larger this rectangle the more power the cell can produce (as the area is ID V ). The theoretical ideal power would be Isc Voc . Also drawn on this diagram is the power that the cell develops at various currents and voltages for the IV characteristic drawn. One can see that the power reaches a maximum value as the voltage from the cell increases, and then it begins to fall to zero as the current from the cell decreases. For your information a data sheet for a typical PV panel appears in Appendix F.2.

8.2 Photovoltaic Inverters

8-13

V

Figure 8.7: Maximum power diagram for a solar cell. Remark 8.11 The IV characteristic shown in Figure 8.7 varies depending on the temperature and illumination of the cell and the series and shunt resistances of the cell. The load line shown on the diagram (the R1L lines) assumes a value of the effective load resistance on the cell of RL . The R1L line crosses through o the ID V curve at its maximum power value, and therefore the load would be receiving the maximum power that the cell can produce. The RLo value is the optimal load resistance for the condition drawn. The two other load lines on the diagram are for values of load resistance that are smaller than the optimal value ( R1L ) and larger than the optimal value ( R1L ). As can be seen from the 1 2 diagram in both cases (P1 and P2 ) the power produced by the solar cell will be less than the maximum value (Po ). n Remark 8.12 As mentioned in the previous remark, the ID V characteristics of the solar cell change with illumination and temperature. In order for the correct effective resistance to be place on the solar cell under varying conditions the maximum power point has to be found. This is achieve in practice by Maximum Power Point Tracking (MPPT) algorithms. Most of these algorithms work by carrying out a small perturbations in the current supplied to the load and then measuring the change in the power. If the power gradient is positive then another perturbation occurs in the same direction. If not then a perturbation in the opposite direction occurs. This approach assumes that the power electronics is operating as a programmable current source. n Summary 8.1 The main issues that arise from this section that are related to interfacing PV systems to a load or the grid are: • A solar cell can be modeled as a current source in parallel with a forward biased diode.

8-14

Grid Connected Converters and Renewable Energy Systems • The current source current value is related to the irradiation of the solar cell. • Solar cells are usually connected in series to get higher voltages (the voltage of a single cell is about 0.5 V). • If some cells in a series connected array are shaded their current source is not as large as the others. This can result in excessive power dissipation in the shaded cells, and lowers the efficiency of the array. • Shading effects mentioned in Practical Issue 8.1 can be handled by changing the power electronic architecture so that small groups of cells have their own power converter. This will allow power optimisation for the shaded cells, and prevents the effects mentioned in the previous point. Clearly there are cost implications involved in this solution. • In order to extract the maximum power from the solar array the power electronic controller has to emulate the optimal load resistance. This value changes dynamically as irradiation and temperature changes. A MPPT algorithm is required to achieve this. n 8.2.1.3

Traditional PV Inverter Topologies

In this section we shall consider in a little more detail the common topologies for PV inverters. These were briefly introduced in Section 8.2.1 when the inverter systems were broadly categorised into three phase, single phase, and galvanically isolated and non-isolated topologies. As also mentioned previously, galvanically isolated power electronic topologies have, until the last few years, been the main category of PV inverters that have been installed in Australia. This was probably due to the inherent safety of these systems, and the conservative approach Australian regulation authorities tend to take when systems are to be installed into a domestic premise. However, the non-galvanically isolated topologies have been popular in Europe for a number of years now, and over the last few years they have started to become popular in Australia. The reason for this increase in popularity can readily be seen in Figure 8.8 (which is taken from [24]). This figure compares the different inverter topologies that would be used in domestic applications on the basis of efficiency, weight, and volume. As can be seen, it is fairly clear that the non-isolated inverters win in all these categories – this is the driving motivation for their introduction in Australia. It is also clear that within the isolated category the high frequency transformer offers smaller weight and size, but it does not necessarily have better efficiency than the low frequency transformer design. The fact that there have not been major safety issues with transformerless systems in Europe appears to have allayed the fears of the regulation authorities in Australia1 . Other issues such as DC injection to the grid, that can occur with directly connected systems, can also be handled with appropriate control. Three phase systems are usually involved in PV systems with large powers, and can be used to interface a DC bus being fed from a number of PV arrays to the AC grid supply. These three phase inverter systems are fairly standard 1 It

should be noted that isolation is a requirement in the United States.

8.2 Photovoltaic Inverters

Figure 8.8: Relative merits of different inverter topologies for PV systems [24].

8-15

8-16

Grid Connected Converters and Renewable Energy Systems and are in wide use in the AC variable speed drive industry. They are treated elsewhere in these notes, and this will not be repeated here. Two structures that are used in larger power systems are the one phase multi-string converter. This type of system breaks the PV array into sections, each with a DC-DC converter that implements the MPPT algorithm. These DC-DC converters feed onto a common DC bus which in turn feeds into a single phase DC-AC converter. Usually these are arranged as three systems, with each of the DC-AC converters feeding into separate phases. Figure 8.9 shows the general configuration of this arrangement. Figure 8.10 shows a detailed view of one of the three modules. As can be seen the DC-DC converters are non-isolated, therefore they have low losses (as compared to an isolated high frequency converter based system). The grid interfacing is taken care of by the totem pole output converter. Remark 8.13 One of the best features of the topology shown in Figure 8.9 is that the MPPT and voltage control can be taken care of by the DC-DC converter controllers, and the grid interfacing control by the control unit (CU) shown. The DC bus essentially isolates these two control algorithms. This allows the controllers for these different output objectives to be designed independently. n Remark 8.14 Another advantage of the multi-DC-DC converter based topology is that each DC-DC converter can implement its own MPPT algorithm, thereby taking into consideration the particular circumstances of the solar panel array connected to the converter. This allows the possibility of different panels being in different orientations, and also accounts for differential shading across the array. n An alternative arrangement of this is to use a single three phase converter instead of the three single phase ones. This configuration is shown in Figure 8.11, and the number of switches involved is the same. The only difference between these two approaches is the control with respect to the grid interfacing – one uses three single phase controllers, and the other a three phase control algorithm. In the three phase inverter case special control strategies would have to be undertaken to account for unbalance in the grid voltages (if they exist), whereas in the single phase case there is no concept of unbalance as the control is implemented on a phase-by-phase basis. Remark 8.15 Three phase transformerless topologies tend not be be used very much. The main reason is the the DC voltage needs to be relatively high – at least 600-VDC for a 415 VAC line-to-line mains. The DC voltage is limited (in Europe) to 1000-VDC for safety reasons. It is considered that this voltage range is too narrow given that there are DC voltage changes due to temperature, and also the grid voltage can change. Single phase systems on the other hand only have to handle the line-to-neutral voltages. In addition to this reason, many manufacturers want to make up their three phase systems by using three of their single phase systems. This makes sense from the manufacturing, production and maintenance point of view. n The single phase inverters that are commonly used at the domestic level, and with smaller scale PV systems will be the focus of our attention in this section. A survey of power electronic systems for grid integration can be found

8.2 Photovoltaic Inverters

8-17

N

=

= = = =

CU

= = Converter 1

=

= = = =

CU

= = Converter 2

=

= = = =

CU

= = Converter 3

Figure 8.9: Single-phase multi-string converter [25].

8-18

Grid Connected Converters and Renewable Energy Systems DC Bus + L

DC-DC Conv 1

L

DC-DC Conv 2

Utility Grid L

DC-DC Conv 3

Figure 8.10: Detailed view of a single single phase output module [25]. in [25]. Some of the following discussion will be based on the contents of this paper together with [21]. Figure 8.12 shows the basic configuration of a modern transformerless PV bridge converter. This circuit forms the basis for most modern converters that are used in domestic situations. As can be seen from the figure the circuit is simply a basic single phase bridge converter as discussed in other parts of these notes. As we shall see, this basic circuit has some problems, that are not all that obvious, when used in the transformerless PV application. Remark 8.16 A few things to note from Figure 8.12: • The PV array is not electrically isolated from the mains supply. Therefore the PV array is floating at some voltage with respect to the ground (as noted previously). • The converter uses a very simple inductor filter. • The PV array has to have a voltage high enough so that the converter can operate directly connected to the mains without a boost converter. In Europe, where the voltages are much the same as Australia, the minimum PV array voltage is 350-VDC. • There is a capacitance between the isolated PV array and the ground with a voltage Vcg across it. If there is an AC component to this voltage a current will flow through this capacitance. • If there is substantial current flow through the Cg parasitic capacitance there is the possibility of electrical shock to a person touching the array. In addition high frequency currents through this capacitance would contribute substantially to EMI pollution, especially if arrays with this issue were widely deployed.

8.2 Photovoltaic Inverters

8-19

=

= = = =

CU

= = = = = = = = = = = = = = = = = = = =

Figure 8.11: Multi-string converter with a three phase output stage [25].

8-20

Grid Connected Converters and Renewable Energy Systems

L L L N

Figure 8.12: A transformerless bridge converter interface for a PV system. • For safety reasons the PV array and the associated power electronics has to be double insulated. n The basics of PWM for a full bridge converter (aka a H-bridge converter) were developed in Sections 1.3.2.2 and 2.4.7 and will not be repeated here, however as eluded to previously the modulation strategy adopted with this converter has profound affects on its safety and therefore usability in domestic environments. Let us initially consider bipolar switching. In this mode of switching we have the following characteristics: • The two legs are switched so that S1 = S4 = closed or S2 = S3 = closed at a high frequency and the switching is so arranged so that the output fundamental is some desired fundamental frequency. • No zero voltage state of the inverter itself is possible (although a zero average output voltage is possible). The other very interesting aspect of this modulation strategy is that the Vcg (the PV array to ground voltage) only has a small amplitude grid frequency component to it (this will be shown shortly). Therefore the current flowing through the parasitic capacitance between the array and the ground is very small due to the high impedance of this capacitance at these frequencies. The following discussion is with reference to Figures 8.13 and 8.14 which show the equivalent circuits for the PV H-bridge converter when switches S1 and S4 are turned on, and S2 and S3 are turned on. These are the two state associated with bipolar modulation switching. We are interested in what happens to the voltage across the parasitic capacitance between the PV panel and ground. Carrying out KVL around the loop shown in Figure 8.13 we can write: VP V + 2L

di − vac dt di ∴L dt

=

0

(8.11)

=

vac − VP V 2

(8.12)

8.2 Photovoltaic Inverters

8-21

L

+ i L

Figure 8.13: Equivalent circuit for the H-bridge PV converter with S1 and S4 turned on.

L

i

+

L

Figure 8.14: Equivalent circuit for the H-bridge PV converter with S2 and S3 turned on.

8-22

Grid Connected Converters and Renewable Energy Systems Clearly: di vac − VP V = (8.13) dt 2 Similarly one can do the same with Figure 8.14 allowing us to write: Vcg1 = L

VP V + 2L

di + vac dt di ∴L dt

=

0

(8.14)

=

−(VP V + vac ) 2

(8.15)

Therefore, we have the following expression for the common mode voltage under these switching conditions: Vcg2

= =

∴ Vcg2

=

di + vac dt VP V vac − − + vac 2 2 vac − VP V 2 L

(8.16) (8.17) (8.18)

We can now work out the change in the voltage across the parasitic capacitor between then two switching positions: δVcg

= =

∴ δVcg

=

Vcg1 − Vcg2 vac − Vpv vac − VP V − 2 2 0

(8.19) (8.20) (8.21)

Remark 8.17 This analysis shows that there is no change in the voltage across the parasitic capacitor when switching occurs, and therefore there will be no high frequency currents flowing through the capacitor. n If should be noted that the δVcg voltage is the difference in voltage between the two switching configurations. The question then remains as to what the actual voltage is appearing across Cg ? Since the difference in the voltages between the two switching instances is zero, then the voltage to ground is simply either Vcg1 or Vcg2 depending on the time instant. Since, for a grid connected system vac = Vˆ sin ωt then the voltage that appears across the capacitor is Vcg =

Vˆ VP V sin ωt − 2 2

(8.22)

. Remark 8.18 The overall conclusion is that the voltage appearing across the Cg capacitor is the grid voltage. Since the supply frequency is low, and the capacitor Cg has a relatively small value, then the leakage current through this capacitor is very small. Therefore the potential for enough current to flow through a person touching the outside (insulated) surface of the PV array and receiving an electric shock is virtually zero. n Summary 8.2 The PV connected H-bridge has the following properties with bipolar modulation:

8.2 Photovoltaic Inverters

8-23

• Uses the simple bipolar switching algorithm. • There are no high frequency switching components in the Vcg voltage. This means that the common mode currents through Cg are very small. • The common mode voltage is at the grid frequency. • The bipolar switching means that there is higher ripple relative to unipolar switching strategies, and this in turn means that the filtering requirements are increased. • The filter inductors are subjected to bidirectional flux transitions. This increases the losses in the inductors, and decreases efficiency. • The ripple in the current results in reactive power exchanges with the capacitor across the PV array. The current flows associated with this result in extra losses and lower efficiency for this converter. • The overall efficiency of these converters is of the order of 96.5%. • The lower efficiency of the converter because of the issues raised above means that bipolar modulated converters are not used in commercial PV inverters. n Now let us consider the PV H-bridge converter, but this time with unipolar modulation. Again we are interested in issues related to the current through the parasitic capacitance, as well as the efficiency and filtering requirements of the converter. At the outset, we already know that the filtering requirements for a unipolar modulated system, assuming the same switching frequency, will be less than that of the bipolar system (this has come from previous work in the notes on these modulation strategies). In addition to this it is easy to see that the filtering inductors in the converter will be subject to unipolar flux excursions over a switching cycle since the voltage is being switched from VP V to zero volts or from −VP V to zero volts, depending on the polarity of the output waveform. Therefore, these two properties mean that the losses in the inductors will be less for unipolar operation as compared to bipolar operation. Let us consider the Vcg voltage with this type of converter. Obviously the situation with S1 = S4 = closed is the same as in Figure 8.13. In unipolar operation the zero voltage is produced by shorting the grid supply, and this is achieved by S1 = S3 = closed. This situation in shown in Figure 8.15. Let us analysis this situation. Similar to the previous analysis we can write: L

di di − vac + L dt dt di ∴L dt

=

0

(8.23)

=

vac 2

(8.24)

We can then write the expression for the voltage across the parasitic ground capacitor: Vcg2

=

−VP V + L

∴ Vcg2

=

vac − VP V 2

di dt

(8.25) (8.26)

8-24

Grid Connected Converters and Renewable Energy Systems L i L

+

Figure 8.15: Equivalent circuit for the H-bridge PV converter with S1 and S3 turned on. We are now in a position to calculate the change in the voltage across Cg due to the change in the switch configuration. Using (8.13) we can write: δVcg

∴ δVcg

= Vcg1 − Vcg2 vac vac − VP V − + VP V = 2 2 VP V = 2

(8.27) (8.28) (8.29)

Remark 8.19 One can see from (8.29) relative to (8.29) that with unipolar modulation there is a switching component across the Cg capacitor. This switching component, with an amplitude of VP V /2 will have very fast edges, and therefore the spectral components in the waveform will have a very high frequency content. Consequently, even though Cg is a parasitic capacitor (and would have a relatively small value), a high current can flow through it. In practice currents as high as 3 to 4 Amps can flow. The exact current depends on the physical location of the panel with respect to ground. n Summary 8.3 The following can be deduced from this analysis of unipolar modulation: • The high Cg current under unipolar modulation means that there is a potential for electric shock if a person touches the outside of the array. This situation is likely to increase Cg and therefore the current. • The fact that the grid supply is disconnected from the PV array and its capacitor during the zero voltage period means that there is no reactive power exchange between the supply and the capacitor. This will improve efficiency. • The filter inductors are only subjected to unipolar flux transitions, and this will lower the losses in the inductors, thereby improving efficiency.

8.2 Photovoltaic Inverters • Unipolar modulation generates the same harmonic content as bipolar modulation, but can do so at half the switching frequency. Therefore, the filtering requirements of this modulation strategy are less than with bipolar modulation. • The efficiency of this type of converter can be up to 98%, which is the maximum efficiency that has been measured for PV inverters. • Despite the extremely good efficiency of the unipolar modulated H-bridge it is not used because of the high ground currents and consequent safety issues. n An variation to the unipolar modulation strategy is the hybrid modulation strategy [26]. In this modulation strategy one of the inverter legs is PWM’ed in the traditional sense, whilst the other leg is switched at the grid frequency (i.e. at 50Hz in Australia). Let us briefly consider this scheme. Figure 8.16 shows the H-bridge converter for a hybrid switching algorithm. The only difference between this and the previous H-bridge converter of Figure 8.12 is that there is only one inductor in the filter. From a modulation perspective Leg B (i.e. switches S3 and S4 ) are switched at the grid frequency. The switching occurs in synchronism with the voltage supply – i.e. when Vg > 0 then S4 is closed, and when Vg < 0 then S3 is closed. The equivalent circuits for these two situations are shown in Figure 8.17. Remark 8.20 One can see from Figure 8.17 that for both the cases that the equivalent circuit of the H-bridge is that of the traditional DC-DC buck converter. If Vg > 0 then S4 is closed and the PWM is carried out by S1 and S2 . If Vg < 0 then S3 is closed and again the high frequency PWM is carried out by S1 and S2 . n Remark 8.21 Since the equivalent circuits are buck converters each equivalent circuit can only operate in one quadrant. There are two equivalent circuits for the two different switch positions meaning that this circuit can only operate in two quadrants. n Remark 8.22 It is clear from the diagrams that the common mode voltage is a square wave that has moves between 0 volts (S4 closed) and -VP V volts (S3 closed). Since these switching are synchronized with the grid frequency then this square wave has the same frequency. n Remark 8.23 The first major spectral component is the switching frequency of S1,2 . Therefore this inverter does not get the 2× frequency benefit that the normal H-bridge does in unipolar modulation. Consequently it will have more stringent filtering requirements. n Remark 8.24 The inductors in the circuit are subjected to unipolar flux transitions. This makes the losses in the inductors low, and increases the efficiency of the system. n Remark 8.25 During the zero voltage intervals there is no reactive power exchange between the inductor and the PV capacitor. This increases the efficiency of the system. n

8-25

8-26

Grid Connected Converters and Renewable Energy Systems

L A B

Figure 8.16: Hybrid Switching H-bridge converter. Remark 8.26 The lower switching frequency in one of the legs also increases the efficiency of the converter by lowering the switching losses. n Summary 8.4 Summing up, one can see that there are a lot of nice properties with this converter. Of particular note is its efficiency, which is of the order of 98%. However, in the form of Figure 8.16 the converter is not used. The problem is the step changes in the common mode voltage. These steps are very fast, and this can lead to spurts of current through the parasitic capacitance at 100 times a second. n

8.2.2

New PV Inverter Topologies

The deficiencies of the transformerless H-bridge converter when used with bipolar, unipolar and hybrid modulation mode were investigated in the previous section. This section will consider some newer inverter topologies, which are based on the H-bridge, but attempt to address the efficiency issues of bipolar modulation, and the safety issues that arise with unipolar and hybrid modulation. The inverter topologies are currently being used by several manufacturers of commercial inverter systems. 8.2.2.1

H5 Inverter (SMA)

This is an inverter topology patented in 2005 by SMA Solar Technology of Germany. It consists of a classic H-bridge inverter with an extra switch in the DC link [21]. The basic circuit is shown in Figure 8.18. The name of the converter clearly comes from the fact that it is a H-bridge implemented with 5 switches. Similarly to the Hybrid converter, this converter uses a combination of switching speeds. Some of the switches are switched at mains frequency, and some are switched at high PWM frequencies. As with the hybrid H-bridge converter this has some efficiency benefits. Let us consider how this converter works. Essentially the extra switch gives an extra degree of freedom to allow a freewheeling path when zero volts is being

8.2 Photovoltaic Inverters

8-27

L i

+

L i

+

Figure 8.17: Hybrid Switching H-bridge converter equivalent circuit for the two positions of the low frequency switches.

8-28

Grid Connected Converters and Renewable Energy Systems

L A B L

Figure 8.18: H5 H-bridge converter. applied whilst at the same time isolating the grid supply from the PV array – it is this connection of the PV array to the grid supply during the zero voltage times that allows the high frequency switching to appear across the Cg parasitic capacitance. Similarly to the hybrid H-bridge, there are two cases that one needs to consider: a. Vg > 0; i > 0 b. Vg < 0; i < 0 The reason that the Vg > 0 and i > 0 are coupled together is that the PV array is delivering real power, and this is the only condition (and the vice-versa) when this will occur. The other major difference between this converter and the hybrid H-bridge we previously considered is the switching sequence. Because we want to isolate the bridge from the grid during the zero vector times we need to ensure that during these times the bottom two switches are off (i.e. S2 and S4 ) and the freewheeling path is supplied by the top switches. The isolation of the top switches from the gird is implemented by the new switch S5 . This means that S5 has to be switched every time that the zero vector is produced – i.e. it is switching at high frequency. The remainder of the switching can be worked out by realising that we need to again implement a DC-DC buck converter for both the positive Vg and negative Vg grid voltages. The following discussion can be visualised with the assistance of Figure 8.19 for the Vg > 0 case, and 8.20 for the Vg < 0. The two figures in each of these diagrams show the same respective situation for the Vg polarity. The top figure is the situation where the inverter is delivering power in the PWM cycle, and the bottom figure is the case during the PWM cycle when the inverter is in the zero voltage state. If Vg > 0 then we can form the first buck converter by closing S1 for the whole half cycle, and then PWM’ing S5 and S4 . When S5 and S4 are closed

8.2 Photovoltaic Inverters

8-29

L A

i B

L

L A

i B

These switches open

Figure 8.19: H5 H-bridge equivalent circuit for Vg > 0. power is being supplied to Vg , and when they open then the current can freewheel via S1 and S3 (and their associated diodes if required). This is the zero voltage output state of the inverter, and obviously no power is being delivered to the load. Since S2 and S4 are open then the bottom rail of the converter is not connected to the grid side. The top rail is also not connected since, as we have already said, S5 is also open during this time. Therefore whatever voltage was on Cg prior to this operation mode will remain there over this zero output voltage period (if it is small). Upon the next active switch state any sag in the Vcg voltage would be restored. A similar situation also occurs in the Vg < 0 situation (depicted in Figure 8.20). Switch S3 is closed for the whole negative half cycle, and therefore connects point B to the positive PV array rail. This allow S5 and S2 to be PWM’ed into the DC-DC equivalent buck converter. As in the previous case when S5 is off so is S2 and the freewheeling occurs around the S1 ; S3 loop ap-

8-30

Grid Connected Converters and Renewable Energy Systems plying zero volts to the grid. Because S5 is off, as well as S2 and S4 then the grid voltage is completely isolated from the PV array. Remark 8.27 One can see that in the H5 converter that the top switches, S1 and S3 are the switches that are switched at the grid frequency. Their purpose is to connect the positive terminal of the PV array to the positive terminal of the grid supply. The bottom switches and the extra S5 switch are switched at the high frequency to produce the PWM. n The other question that has not been answered at this stage about this circuit is – what is the Vcg voltage? This can be calculated by considering the equivalent circuits for the various modes of operation. Let us consider the top diagram in Figure 8.19. Carrying out KVL around the loop shown by the dashed line we can write: − VP V + L

di di + Vg + L dt dt di ∴L dt

=

0

(8.30)

=

VP V − Vg 2

(8.31)

Clearly: Vcg ∴ Vcg

di dt Vg − VP V 2

= −L

(8.32)

=

(8.33)

Conclusion 8.1 The conclusion that can be drawn from this analysis is that under the active power output condition the voltage appearing across the Cg capacitor is the value in (8.33). Examination of this expression indicates that the voltage is the grid voltage with an offset. n Conclusion 8.2 The second conclusion that can be drawn from this figure is that when the zero voltage is being produced, the isolation of the PV array from the grid means that the voltage of equation (8.33) is retained (except for whatever leakage that would occur). n The second situation is shown in the top diagram of Figure 8.20. Again using KVL around the loop shown by the dashed current direction line we can write: − VP V + L

di di − Vg + L dt dt di ∴L dt

=

0

(8.34)

=

VP V + Vg 2

(8.35)

As previously the Cg capacitor voltage is: Vcg

∴ Vcg

= Vg − L

di dt

VP V + Vg 2 Vg − VP V 2

(8.36)

= Vg −

(8.37)

=

(8.38)

8.2 Photovoltaic Inverters

8-31

L A

i B

L

L A

i B

These switches open

Figure 8.20: H5 H-bridge equivalent circuit for Vg < 0.

8-32

Grid Connected Converters and Renewable Energy Systems Remark 8.28 Equation (8.38) is the same as (8.33). Note that in this case the Vg value would be negative since this was derived for this situation. The situation for the bottom diagram is similar to that of the Vg > 0 case. The PV array is again isolated from the mains supply. n Conclusion 8.3 The overall conclusion from (8.33) and (8.38) is that Vcg =

Vg − VP V 2

(8.39)

for all switching positions. This means that there is no high frequency component, and the voltage across the parasitic capacitance is an offset version of the grid voltage. This fact means that there is little Cg leakage current and low EMI from this inverter. n Summary 8.5 The H5 inverter has all the advantages of the hybrid inverter, and at the same time eliminates the high frequency components in the Vcg voltage. It has been shown to have a European Efficiency of 97.7% and a maximum efficiency of 98%. This efficiency is the same as the maximum efficiency of all the very efficient inverter structures. This inverter is used commercially in the SunnyBoy 4000/5000 TL PV inverter. A data sheet for this inverter can be found in Appendix F section F.1. n 8.2.2.2

HEIRC Inverter (Sunways)

This is another inverter topology that is similar to the previous one. Even though it is similar, it is worth having a brief look at this topology as another variant. This is also a topology that is patented and commercialised by Sunways (in 2006). This topology differs from the previous one in that is is formed again from a H-bridge but has a bypass leg in the AC side of the bridge. Figure 8.21 shows the basic circuit. Under active power output the operation of this circuit is much the same as the operation of the H5 converter. However under zero voltage output the switches S1 , S2 ,S3 and S4 are all turned off and the current is allowed to flow around a short-circuit path produced by S+, D+ or S−, and D−. Note that these switches use unidirectional switches to effectively form a bidirectional switch. Which ever switch is chosen remains switched on for the whole half cycle of the current flow. Remark 8.29 The main points to make about this configuration [21]: • The voltage across of the filter components is unipolar (as it was with the H5 topology), and therefore the core losses in the inductors will be lower. • It has reasonable efficiency (European Efficiency of 95%) relative to other topologies that prevent reactive power exchange between CP V and the filter inductors. • The Vcg voltage only has grid frequency components in it, and therefore there is only a small ground current and the EMI is not large. • The topology has one extra switch compared to the H5 topology.

8.2 Photovoltaic Inverters

8-33 L

L

Figure 8.21: The HERIC PV inverter topology (Sunways) • The HERIC has two switches conducting at the same time, whereas the H5 has three switches conducting. n

8.2.2.3

Full Bridge with DC Bypass (Ingeteam)

This is yet another modified full bridge topology. It has a patent pending by Ingeteam in 2010. Figure 8.22 shows the circuit for this inverter. This is an interesting design in that the switches S1 and S4 are switched on for the positive half cycle of Vg , and S3 and S2 for the negative half cycle of Vg . The PWM is carried out using the S5 and S6 switches. The clamp diodes D+ and D− are there to prevent the DC link bypass switches from being subjected to more than half the DC link voltage. Due to the similarity in the operation of these converters the operation will only be briefly described. To deliver an active positive voltage switches S5 , S1 , S4 and S6 are closed – this essentially again forms the buck converter circuit. To get the zero vector then S5 and S6 are opened and S2 , S3 are turned on, and the current circulates via two paths – D3 and S1 as well as S4 and D2 . Again this is analogous to the freewheeling diode of the traditional buck converter. Remark 8.30 One nice feature of the inverter is that the switching of S3 , S2 during the zero vector production can be undertaken with no current flowing through them. Therefore there is no switching losses. n Remark 8.31 Some remarks about this topology: • As with the similar topologies the voltage across the filter is unipolar. This means that the magnetic losses will be low. • The DC bypass switches are rated at half the DC link voltage. The D+, D− diode clamps ensure that this is the case since if the voltage on the H-bridge side of the bypass switch falls below VP V /2 then the diode will turn on.

8-34

Grid Connected Converters and Renewable Energy Systems

L

L

Figure 8.22: The full bridge DC bypass PV inverter (Ingeteam). • As with all the other modified H-bridge converters there is no reactive power exchange between the filter inductors and the CP V capacitors during the zero voltage period. • The Vcg voltage only has a grid frequency component which means that the leakage current and EMI are low. • The inverter has two extra switches and two extra diodes compared to the standard H-bridge. • During the active vector there are four switches conducting. This will affect the overall efficiency. • European Efficiency is 95.1% and maximum efficiency is 96.5%. Note that this figure is a little down compared to the H5 topology for example. • Commercialised by Ingeteam in the Ingeconr Sun TL series (2.5/3.3/6 kW). Conjecture 8.1 It would seem to me that the proliferation of different topologies for these H-bridge based converters is more about circumventing the patents of other companies rather than a distinct advantage of any particular topology. It would seem that it is better to accept a slightly less efficient inverter which may be more expensive to make rather than pay a royalty to a competitor. n Up until this point the inverters that we have been looking at have been derivatives of the H-bridge. There are a lot of different versions of these, and I only covered a few of them. If one considers the PV panel integrated inverters (the inverter and panel come as an integrated set) then the inverter topologies proliferate even more. In order to ensure that these notes are not repetitive I shall not consider anymore of this genre of inverters. Instead in the next section we shall briefly consider inverters for PV applications that are derived from multi-level converter topologies. These are still single phase systems.

8.2 Photovoltaic Inverters 8.2.2.4

Neutral Point Clamped (NPC) Half-Bridge Inverter

The neutral point clamped converter is a well known converter in the multilevel converter community. The three level NPC converter (commonly used in medium voltage three phase variable speed drives) can also be used in single phase systems as well. Similarly to the H-bridge systems it enables one to produce two active voltages and a zero voltage. The basic circuit for a classic single phase NPC inverter is shown in Figure 8.23. In order to understand this circuit refer to Figures 8.24 and 8.25. Figure 8.24 is for the case where Vg > 0 and i > 0. The top drawing in this figure is for the case when there is an active voltage delivering power from the PV array to the grid. As with all the previous cases the switches are turn on so that a DC-DC buck converter circuit is formed and energy is being delivered to the load (the grid voltage in this case) as well as the filter inductor (L). The current flow is, as in previous cases, shown as the dashed line. Note that there are two switches on, S1 and S2 , and the complementary switches S3 and S4 are off (as is the normal case in a totem pole leg). The voltage being produced across the load is VAB = VP2V – the voltage appears across one of the two series capacitors in the DC link of the inverter. Remark 8.32 One can see from the figure that the current that is being delivered to the load is effectively flowing from one of the capacitors. The other capacitor is has no current flowing through it. n Remark 8.33 The other obvious difference between this inverter and the previous ones is that the output voltage is half the PV array voltage. This has the implication that the PV array voltage would have to be twice as big as in the previous converters if a boost converter is not used as part of the overall converter. However, a positive feature is that the devices themselves are subject to the only VP2V . n Remark 8.34 Under this switching state it is important point to note is that the voltage supported across S3 and S4 is VP V . A question that arises is whether this voltage is equally supported by these two devices? If the voltage at the top of S4 goes above zero volts (relative to ground) then the diode D− will become forward biased clamping this voltage. This means that the voltage across S4 has been clamped at VP2V . Therefore the voltage across S3 is also effectively clamped at the same voltage. n Remark 8.35 The voltage sharing described in the previous remark works very well despite the variations in components for several reasons: • When the switches are off the reverse currents are essentially thermal current sources (essentially reverse leakage currents through diodes). Therefore if one of the series elements tends to have an effective impedance that is lower than the other, then it will be supporting less voltage and therefore will dissipate less power. The other device on the other hand will tend to dissipate more power, and therefore the reverse current will tend to increase. This will make it effective impedance lower, and therefore an equilibrium will be achieved. Therefore there is a tendency for nature voltage sharing.

8-35

8-36

Grid Connected Converters and Renewable Energy Systems • The diode D− will contribute to the leakage current of S4 in addition to the leakage current from S3 . This will tend to make the voltage across S4 rise, and the diode D− will start to turn on. This will then clamp the voltage across both devices. These same ideas are the basis for voltage sharing of series devices in this type of clamped converters. n The bottom drawing in Figure 8.24 is when the zero voltage is being produced. One can see from this figure that this is achieved by simply turning S1 off. The filter inductor forces D+ to turn on, and the voltage VAB becomes 0 as a short circuit is developed across the output terminals of the converter. Therefore when Vg > 0 and i > 0 the S1 switch is PWM’ed to produce the desired output voltage and S2 remains on for the whole of the grid voltage half cycle. Note 8.3 It should be noted implicit in this explanation (and the previous ones for the H-bridges for that matter) is that the output current and voltage are inphase – i.e. the converter is only producing real output power and no reactive power. This is the usual case, but there could be circumstances where the PV inverters may form part of a more integrated grid control system and they could produce or absorb reactive power as well as real power. This converter can operate at non-unity power factors. For example, if Vg > 0 and i < 0 then for positive output voltage the same switches are closed (S1 and S2 – the current is actually flowing through the parallel diodes) but when zero volts is produced then S1 opens and S3 closes. The current will then flow via S3 and D− forming the short circuit across the load terminals. Similarly if Vg < 0 and i > 0 the positive voltage situation is the same, again with the parallel diodes around the switches S3 and S4 conducting. To get the zero voltage then S4 is opened and S2 is closed forming a current via S2 D+.n Figure 8.25 shows the other situation for the inverter switching. A quick perusal of the figure shows that the situation is a virtually identical to the previous case in terms of the general principle of the operation. Therefore the detailed description will not be repeated. Summary 8.6 Summing up we can say the following about this topology: • The PWM frequency is applied to switches S1 and S4 and the switches S2 and S3 are switched at the grid frequency. • The converter is able to handle non-unity output power factors. • The voltage across the filter is unipolar giving low core losses. • Able to achieve high efficiency (98%) since there is no reactive power exchange during the zero voltage state. • The voltage rating of the switches is VP V /2, which is half the voltage rating of the H-bridge topologies for the same VP V . • Due to the fact that the peak output voltage VAB = VP2V then the VP V voltage will have to be twice that of the H-bridge for the same grid voltage. This means that there is no saving in switch voltage rating with NPC.

8.2 Photovoltaic Inverters

8-37

L

Figure 8.23: Basic NPC single phase leg. • Because the centre point of the capacitors is held at zero volts then Vcg = − VP2V (the voltage across the bottom capacitor). Therefore there is theoretically no ground current or ground current induced EMI. • The switching losses between the switches are uneven due to the fact that S1 and S4 are PWM’ed and S2 and S3 are switched at grid frequency. • The ground wire from the load to the capacitor centre point has to be very low inductance to prevent transient common mode voltages from being generated. The NPC topology has been commercialised in the transformerless TripleLynx PV inverter sold by Danfoss Solar. These are rated at 10, 12.5 and 15 kW. They are reported to have a European Efficiency of 97% and a maximum efficiency of 98%. 8.2.2.5

Some Other Topologies and Issues

Thus far several topologies have been introduced and considered in various amounts of detail. In this section several other issues will be covered, some of which are relevant to all the topologies presented, as well as a brief discussion of three phase topologies. Up until now we have considered H-bridge converters without a boost circuit. Depending on the circumstances and application a boost converter may be required. There are two main ways of achieving the boost:

8-38

Grid Connected Converters and Renewable Energy Systems

L B

A

B

A

L

Figure 8.24: NPC with Vg > 0 and i > 0.

8.2 Photovoltaic Inverters

8-39

L B

A

B

A

L

Figure 8.25: NPC with Vg < 0 and i < 0.

8-40

Grid Connected Converters and Renewable Energy Systems PV array

Boost converter

Rectifier HF Transformer

DC link filter

Grid interface converter Switching harmonic filter

Figure 8.26: Basic structure of a single phase PV interface with a high frequency isolated boost converter. • a high frequency transformer. • a traditional boost converter with a low frequency transformer. Considering the first case, a traditional high frequency converter solution appears in Figure 8.26. As can be seen if is formed by placing a conventional H-bridge on the primary side of the a high frequency transformer, followed by a rectifier, filter and another H-bridge on the secondary side. Of course the traditional H-bridges we have in this diagram can be replaced for the H5, HERIC etc to get a more efficient circuit. Remark 8.36 The PV array can be grounded in this circuit since the PV array side is completely electrically isolated from the grid supply. There could be still some high frequency feed-through from the output side via the capacitance of the transformer. However if this is carefully designed this can be minimised. n An alternative to the isolated HF transformer is to use a low frequency transformer on the output of the PV grid interface inverter and the boost function is implemented using a conventional non-isolated boost converter. Figure 8.27 shows the basic layout of this type of converter. As can be seen from this figure the transformer is now on the low frequency side of the converter after the filter. Therefore this transformer is a mains frequency transformer, and would be much larger and heavier than an equivalent high frequency transformer capable of the same power throughput. However there are three fewer switches in this design as compared to the high frequency converter design. Remark 8.37 In both these boost converter systems the presence of the two converters means that the control for the system can be distributed. The MPPT for example can be handled by the boost converter, and the grid interface control issues by the output H-bridge. n Finally a note on three phase converters. These were very briefly introduced via Figure 8.11. However most three phase systems are built using single phase modules – i.e. they are three phase, four wire systems. This has been mainly done so that existing single phase modules can be used. The are essentially controlled as three single phase systems. An example of a commercial system that is built like this is the SMA Sunny Mini Central 8000TL. Other companies like Conergy, Refusol and Danfoss Solar are building true three phase inverters in the large power range of 10-15kW. In terms of efficiency, low leakage and performance they are on par with the H-bridge systems we have

8.2 Photovoltaic Inverters PV array

Filter

Non-isolated boost converter Filter

8-41 H-bridge

Filter

Low frequency transformer

Figure 8.27: Basic structure of a single phase PV interface with a low frequency transformer and non-isolated boost converter. studied. The main problem with three phase systems is the relatively high DC link voltage (minimum of 600VDC for a 400 Volt grid). Taking into account variations that must be catered for, this does not leave much headroom to 1000VDC, which is the maximum voltage for safety reasons in Europe [21].

8.2.3

Grid Requirements for PV Systems

Because PV inverters are generally (but not always) interfaced to the gird, then they have to satisfy certain requirements, known as the grid requirements in order to comply with the rules of connection. The main issues related to the grid interfacing are: Anti-islanding protection An island is formed if the grid is disconnected or fails and one or more PV inverters maintain the supply to the isolated section of the grid. The issues that arise with islanding are safety issues and quality of supply. Voltage and frequency limits If the grid voltage and/or frequency move outside certain limits then the PV inverter should disconnect. Indeed the movement of grid voltage and frequency is one of the passive methods to determine when islanding is occurring. DC current injection There is a possibility of injecting significant DC currents into the grid if the control of the inverter is not very good. Therefore the control has to be such that the DC injected current remains below a certain value. If a low frequency output transformer is used then DC injection (except transiently) will not occur. Power factor The current standard only allows small PV inverters to operate at near unity power factor. There are provisions in most standard to allow for inverters to operate at power factors other than unity, but this will also involve some supervisory control of these systems. Harmonics The inverter output filtering must be such that certain harmonic standards are satisfied.

8-42

Grid Connected Converters and Renewable Energy Systems We shall now consider these issues in a little more detail. Reference will be made to European Standards (these comments mainly sourced from [21]) and also from the relevant sections of the Australian Standards on grid connected converters. These are in Appendix F.3 for convenience and if the interested reader wishes to study them in more detail. As you can well imagine there is a high degree of commonality between standards from different countries. Obviously the standards committees would look at overseas standards when beginning to formulate their own. Inevitably there are differences as well they reflect different perspectives of the committees, different electrical conditions, different degrees of safety, and (somewhat cynically) the desire of most committees to justify their existence by doing something different. Even with these differences there is a fair degree of collaboration between countries in order to get the base of the grid standards the same. This helps facilitate equipment manufacturers that sell systems internationally. From an international perspective the most relevant bodies in relation to standards are the IEEE in the US, IEC (International Electrotechnical Commission) in Switzerland, and the DKE (German Commission for Electrical, Electronic and Information Technologies of DIN and VDE). The later is important, as Germany is a dominant player in the PV market at the moment. Standards Australia, who set the Australian Standards, are of course aware of all the overseas standards, and as shall be seen there is a large degree of similarity between them all. In the remainder of this section we shall look in a little more detail at the standards, and compare and contrast those of the US, IEC, VDE and the Australian Standards. This presentation is by no means exhaustive and complete, but nevertheless it will serve to high the main issues. The international context of these standards is very important for Australian manufacturers in this area who intend to export – they clearly have to satisfy the standards of the countries where they intend to export to. Most of the material used to write this chapter appears in a grid standards summary in [21] as well as in the AS4777.2-2005 which is titled “Grid connection of energy systems via inverters Part 2: Inverter requirements” and AS4777.3-2005 titled “Grid connection of energy systems via inverters Part 2: Grid protection requirements”. Relevant excerpts from these documents appear in Appendices F.3.1 and F.3.2. These are provided so that you can see how these standards are worded and their general structure. For your information the other part of this standard that are not directly relevant to this discussion is AS4777.1-2005 “Grid connection of energy systems via inverters Part 1: Installation requirements”. 8.2.3.1

Discussion of the International Standards

As mentioned in the previous section the IEEE, IEC and VDE have developed standards in relation to grid connection of converters. In this section we shall consider some aspects of these standards. IEEE Standard 1547, which is titled Standard for Interconnecting Distributed Resources with Electric Power Systems is probably the most influential standard in the US these days. This standard is noteworthy in that it is attempting to develop a single standard that applies to all technologies up to power levels of 10MW. It covers issues of the interconnection standards themselves, as well as how to test that these standards to adhered to.

8.2 Photovoltaic Inverters Underwriters Laboratories Inc. are an important body in the US with respect to standardisation. They have developed standards derived from the earlier IEEE 929 standard, which is designated as UL 1741 – Standard for Inverter, Converters, and Controllers for Use in Independent Power Systems. The latest version of this standard also acknowledges the development of the IEEE 1547 standard and says that UL 1741 should be used in conjunction with this standard. The IEC has been working towards bringing together the variety of international standards. For example they have developed IEC 61727 (Dec 2004) – Photovoltaic (PV) Systems – Characteristics of the Utility Interface, and the related standard IEC 62116 Ed 1 (2005) – Testing Procedure for Islanding Prevention Measures for Utility Interactive Photovoltaic Inverters. These standards have reasonable conformity with IEEE 1547. Germany in one of the largest PV markets in the world at the moment. Because of this fact any standards developed in Germany take on an importance that transcends the German domestic context. Amongst the plethora of standards developed was some about devices for automatic disconnection between generators and the public low-voltage grid. This standard was essentially about the prevention of islanding (an issue that we shall return to in some detail later). In its original form this standard stated that the auto disconnection device (which incidentally could be a software “device”) had to be able to detect a jump of 0.5Ω in the grid impedance in power balanced situation. After some experience with this requirement it was concluded that this standard was too tight – it resulted in too much false tripping of PV systems, especially when a number of PV inverters were connected in close proximity. In addition active detection techniques had to be used to try and satisfy it (i.e. injection of test signals in order to determine the grid impedance), and this result in a degradation of the power quality. The upshot of these problems was that a new revised standard VDE 01261-12006 was formulated, and this relaxed the impedance change detection from 0.5Ω to 1Ω. It is hoped that this will result in less problems with PV units on the grid, and at the same time not compromise the safety aspects. Another aspect to these VDE standards is the passive detection limits – i.e. the detection of under-voltage and over-voltage and the frequency deviation limits. These limits form a passive detection method for islanding, as well as making sure that the inverter is not operating on a dysfunctional grid. The VDE standard also describes test procedures to determine if a PV inverter will disconnect from the grid if there is too much DC current injection, or fault currents are exceeded, or there is not sufficient isolation from earth. I will not go into anymore detail on these issues here – the interested reader should look at the appropriate source for these standards to find the details. One issue that has not been touched on in the discussion thus-far is harmonics. PV inverters can of course introduce high frequency harmonics into the grid, and if there are large numbers of them the cumulative effect could be significant. The most significant standard with respect to harmonics that can be produced by equipment is the IEC61000 Electromagnetic Compatibility Standard. One specific part of this standard (IEC61000-3-2) is related to current harmonics for equipment with currents up to 16 Amp per phase. For equipment with currents greater than this but less than 75 Amp there is another standard IEC61000-2-12.

8-43

8-44

Grid Connected Converters and Renewable Energy Systems There are also corresponding standards for voltage related conditions such as flicker and fluctuations (IEC61000-3-3 and IEC61000-3-11) for the 16 Amp and 16 to 75 Amp conditions respectively. They specify limits and test conditions that are used to measure the performance of the equipment. These standards are for the low voltage public network – i.e. 220 to 250 V line to neutral at 50 Hz. Remark 8.38 The IEC61000 standards are related to the EMC of the equipment, and specify values of injected EMC from a piece of equipment into the grid and the means of testing the equipment for compliance. n The EN50160 are European Standards the related to the voltage quality of the public network from the customers perspective.2 For example permissible voltage ranges are given for the low voltage and medium voltage public network under normal operating conditions. These conditions must be met for 95% of the mandated test period. Voltage specifications that are of interest to manufacturers of PV inverter systems are [21]: • Voltage harmonic maximum THD is 8%. See Table 8.1 for the distribution of these limits amongst the various harmonics. • Voltage unbalance for three phase is less than 3% (this would be using the European definition of unbalance –

Vˆneg . Vˆpos

• Maximum voltage amplitude variation is ±10%. • Maximum frequency variation is ±1%. • Voltage dips should be less than 1 second duration and the maximum depth of the dip is 60% of the nominal voltage. As will be seen the PV standards exceed most of the above supply requirements. In respect of the voltage dips, there are currently no requirements in Europe for ride-through. However as the penetration of PV systems increases undoubtedly this will come in. Wind turbine systems for example already have to satisfy very stringent ride-through requirements. The EN50160 standards are related to normal operation of the public distribution grid. With respect to PV inverters, there are also standards as to how they should operate under the circumstance of abnormal distribution grid conditions. These standards are in many senses a type of passive anti-islanding standard. A comparison of the main international standards in respect of PV inverter disconnection when there is a voltage variation is shown in Table 8.2. Remark 8.39 The “Discon time” in Table 8.2 refers to the maximum length of time allowed from the onset of the abnormal voltage condition to the inverter disconnecting itself from the distribution grid. n 2 These standards are about defining what are the “normal” limits for the operating conditions for the gird itself. They do not define the performance of the equipment. However, if equipment was put onto the grid that resulted in these conditions not being met then clearly there is a problem.

8.2 Photovoltaic Inverters

8-45

Odd harmonics Not multiple of 3 Multiple of 3 Order h Relative Order h Relative voltage % voltage % 5 6 3 5 7 5 9 1.5 15 0.5 11 3.5 13 3 21 0.5 17 2 19 1.5 23 1.5 25 1.5

Even harmonics Order h 2 4 6 to 24

Relative voltage % 2 1 0.5

Table 8.1: EN50160 European standards for public distribution grid voltage harmonics limits.

IEEE 1547 Voltage range Discon (%) time (sec) Vˆ < 50 0.16 50 ≤ Vˆ < 88 2.00 110 < Vˆ < 120 1.00 ˆ V ≥ 120 0.16

IEC 61727 Voltage range Discon (%) time (sec) Vˆ < 50 0.10 50 ≤ Vˆ < 85 2.00 110 < Vˆ < 135 2.00 ˆ V ≥ 135 0.05

VDE 0126-1-1 Voltage range Discon (%) time (sec) 110 ≤ Vˆ < 85 0.2

Table 8.2: Comparison of US and European Standards on disconnection times for PV inverters under abnormal voltage variations.

8-46

Grid Connected Converters and Renewable Energy Systems IEEE 1547 Freq range Discon (Hz) time (sec) 59.3 → 60.5a 0.16

IEC 61727 Freq range Discon (Hz) time (sec) fn − 1 < f < 0.2 fn + 1 b

VDE 0126-1-1 Freq range Discon (Hz) time (sec) 47.5 → 50.2c 0.2

a For

systems with power < 30kW the lower limit can be adjusted to allow participation in frequency control. b The f is the nominal frequency of the supply. n c The lower frequency limit in this standard means that adaptive frequency synchronization is required.

Table 8.3: Comparison of European and US standard for disconnection with respect to frequency deviations. Remark 8.40 One can see from the above table that the VDE standard for is very stringent. There are very tight bounds on the voltage, and the time of disconnection is reasonably fast. This means that good quality instrumentation has be to used to satisfy this standard. n Remark 8.41 Even though the inverter power circuit should disconnect due to the conditions of Table 8.2 the instrumentation for the converter should remain connected. This is the allow conditions of the supply coming back into specification to be detected, and resychronisation of the inverter to this supply to allow automatic reconnection. n Similarly to the voltage variation disconnection standards there are also standards for disconnection if the distribution grid frequency moves outside certain limits. These limits, and the time delays associated with them are to help prevent nuisance tripping in weak grids, but at the same time satisfy the passive anti-islanding that is required for safety reasons. A comparison of the main US and European standards are shown in Table 8.3 Tables 8.2 and 8.3 provide the framework for passive anti-islanding of PV systems. This therefore defines when the PV system should disconnect from the grid using available measurements n the inverter. The next question that arises is when should an inverter that has been disconnected under these circumstances be reconnected to the grid. Table 8.4 shows a comparison of standards for the conditions required for reconnection after an out-of-limits trip. One can see that both the voltage and the frequency have to be within certain limits before the reconnection can occur. Also note that under the IEC standard that there is a 3 minute minimum delay before reconnection which is designed to make sure that the inverter is going to be properly synchronized before reconnection is attempted. Another aspect of the grid requirements, also from the inverter viewpoint, is the power quality requirements. These requirements fall into two main categories: • DC current injection limitations. • Injected current harmonics.

8.2 Photovoltaic Inverters

8-47

IEEE 1547

IEC 61727

88 < Vˆ < 100 (%) and 59.3 < f < 60.5 (Hz)

85 < Vˆ < 110 (%) and fn − 1 < f < fn + 1 (Hz) and Minimum delay of 3 mins.

VDE 0126-1-1

Table 8.4: European and US reconnection conditions for PV inverter systems after a trip [21]. IEEE 1574

IEC 61727

VDE 0126-1-1

IDC < 0.5 (%) of the rated RMS current

IDC < 1 (%) of the rated RMS current

IDC < 1 A Maximum trip time of 0.2 sec

Table 8.5: European and US DC current injection limitations • Power factor. We shall have a look at the international standards on these two issues. Table 8.5 shows various limits for DC injection into the grid from PV inverters. DC injection is a particular problem for transformerless PV inverters. If a PV inverter has a transformer (as is specified in much of the US) then DC injection into the grid cannot occur (since a transformer cannot pass DC in steady state). Remark 8.42 It should be noted however that one may wish to minimise the DC output to the isolation transformer in transformer based PV inverters because one can also get DC saturation of this isolation transformer. However, the problem is not as severe as in the grid case because the DC injection is limited to only the one inverter. n Remark 8.43 You will notice from Table 8.5 that the IEEE and IEC standards do not have any time specified for the trip time if DC trip limit is exceeded, whereas the VDE standard does specify a maximum time that the limit can be exceeded before the inverter should disconnect from the grid. n We have previously discussed harmonics from the point of view of the grid – i.e. the maximum harmonic levels that are allowed on the grid. The requirements for the injection of harmonics from the PV inverters is related to but at the same time separate from this. Clearly the standard for the inverters has to be set up on the assumption that there will be multiple inverters connected onto the grid, and therefore there is the potential that the harmonics may be cumulative. Remark 8.44 It should be emphasised that the harmonics for the grid in Table 8.1 are the voltage harmonics. The standards with respect to the inverters is with reference to the current harmonics. Clearly the interaction of the current harmonics with the grid system impedance will lead to voltage harmonics. n Table 8.6 show current harmonic limits from the IEEE 1547 and IEC 61727 standards. These harmonics are usually measured with an ideal grid voltage

8-48

Grid Connected Converters and Renewable Energy Systems IEEE 1547 and IEC 61727a Individual odd harmonic order (h)b

h < 11

11 ≤ h < 17

17 ≤ h < 23

23 ≤ h < 35

35 ≤ h

(%)c

4.0

2.0

1.5

0.6

0.3

a The

THD has to be less than 5.0% even harmonics are limited to 25% of the odd harmonic limits. c This is the percentage of the fundamental amplitude. b The

Table 8.6: IEC and IEEE standards for injected current harmonics Odd harmonics Order h Iˆ (A) 3 2.3 5 1.14 7 0.77 9 0.4 11 0.33 13 0.21 13 ≤ h ≤ 39 0.15 × 15 h

Even harmonics Order h Iˆ (A) 2 1.08 4 0.43 6 0.3 8 ≤ h ≤ 40 0.23 × h8

Table 8.7: IEC61000-3-2 current harmonic limits.

(i.e. from an ideal voltage source with no voltage harmonics). The IEC 61727 standard has not yet been approved in Europe. The standard currently being used is IEC 61000-3-2 (for equipment up to 16 A). These limits are shown in Table 8.7 The final aspect of power quality that shall be commented on is power factor. For the most part PV inverters are designed to operate with a power factor of unity or very close to it. The reason for this as that this power factor will minimise the rating of the power electronics for the real power that is going to be delivered to the grid. The IEC 61727 standard is the only one that mentions that a PV inverter should have an average lagging power factor greater than 0.9 when operating at 50% or greater output power. The IEEE 1574 and VDE 0126-1-1 standards do not include any specifications about PV inverter power factor. Remark 8.45 As the number of PV inverters on the grid increases, and also as the size of some of the installations gets bigger, then the possibility of PV inverters exchanging reactive power with the grid will become more of a prospect. Regulations will have to be developed. Furthermore, communications standards may also have to be developed that will allow some decentralised/centralised control of these reactive power sources. The presence of these devices will add a lot more actuators to the grid for control of voltage, but it will also make the grid control far more complicated. n

8.2 Photovoltaic Inverters 8.2.3.2

8-49

Anti-islanding Standards

The concept of islanding of PV inverters has been mentioned several times. Just as a reminder, islanding refers to the idea that a PV inverter will continue to operate and feed local loads even though the area of the grid where the inverter is located has been isolated from the main part of the grid, and the conventional grid generation sources. Islanding is an important issue for two reasons: • If islanding occurs when the inverter section of the grid is isolated due to a fault or intentional isolation for maintenance, then there is the potential that maintenance personnel or a member of the public can be electrocuted. • If the PV inverter continues to supply energy to the isolated section of the grid then there is the possibility of damage to equipment if a re-closure occurs. As far as the PV inverter is concerned if there is the potential to form an island then the inverter has to detect this and isolate itself from the grid. It is required that this task is performed without any supervisory control – i.e. the inverter has to be able to autonomously determine that islanding has occurred. In order to do this an anti-islanding algorithm has to be implemented in the inverter. The development of such algorithms is a very active research area in PV inverters, as all algorithms developed thus-far have some limitations in terms of the time to detect islanding, and the conditions under which islanding can be detected. Let us look at some of the standards to test whether a PV inverter satisfies the anti-islanding regulations. IEEE 1547/UL 1741 requires the distributed resource (in our case the PV inverter) to detect the islanding and cease to energise the area within 2 seconds of the island forming. In order to test whether a PV inverter is compliant with this, a standard test circuit has been established. This test circuit is shown in Figure 8.28. As can be seen a test RLC load is situated between the PV inverter and the grid. This is meant to simulate the local load when the grid has been disconnected. The load is set up so that the Q of the circuit is 1 and the natural frequency of the circuit is the nominal grid frequency fn . If Pn is the nominal output power (i.e. it is very close to the rated output power) of the PV inverter, then the values of the RLC load are established as follows: R

=

L = C

=

Vˆ 2 Pn Vˆ 2 2πfn Pn Q Pn Q 2πfn Vˆ 2

(8.40) (8.41) (8.42)

Remark 8.46 It is clear from (8.40) that the resistor has been chosen so that the load pulls the nominal output power of the inverter. n With the circuit configuration of Figure 8.28 established, then the power level to the grid is established at 2% of the nominal output power by fine tuning the parameters of the simulated local load. The switch S3 is then opened and

8-50

Grid Connected Converters and Renewable Energy Systems

RLC load Simulated Electrical Power System

Equipment under test

Figure 8.28: Test set up for testing the compliance of a distributed resource with the IEEE 1547 standard in anti-islanding.

the inverter should disconnect in less than 2 seconds to comply. For threephase four wire PV systems then each phase is tested with the circuit connected between the phase and neutral. For a three-phase three wire system the local RLC load is connected between the phases – i.e. it is a balanced three phase local load. The IEC 62116 standard and test for anti-islanding has many similarities to IEEE 1547. The test circuit, for example, is the same, and similar power balance conditions are established. One difference is that the tests are carried out at three different power levels – 100 → 105%, 50 → 66% and 25 → 33%. The voltage also is closely specified. The test is applied for the condition of no change in the real and reactive power, as well as a set of tests where these are stepped in increments of 5% in a range of ±10% around the nominal value for real and reactive power. Similar tests are applied at the other two power conditions where the increment in the powers is 1% around a range of ±5% of the particular power value. As with the IEEE 1547 standard, the maximum trip time after islanding occurs is 2 seconds. It should be noted that the IEC “standard” is still in development and is subject to review [21]. The final international anti-islanding standard is the VDE 0126-1-1 German standard. One test in this standard uses a different test circuit to determine when the PV system under test can detect a change in the grid impedance and disconnect itself. This test circuit is shown in Figure 8.29. As can be seen the circuit employs a local load simulated by a parallel RLC circuit, however is this case the Q = 2. The local active and reactive power is balanced using the variable RLC circuit, and then the switch S is opened in order to increase the grid impedance by 1.0Ω. The inverter should detect this change in the grid impedance and disconnect within 5 seconds. The test is repeated with different values of the simulated grid impedance (R2 , L2 ) in the magnitude range of 1Ω with a maximum inductive reactance of 0.5Ω. The second part of the VDE anti-islanding standard uses the same test circuit as IEEE 1547 – i.e. the circuit of Figure 8.28. The difference is that the Q = 2 as mentioned above and the rest of the parameters are set using (8.40), (8.41) and (8.42). With balanced power the PV inverter should disconnect when S3 is opened within 5 seconds. This test is carried out for power levels of 25%,

8.2 Photovoltaic Inverters

8-51

~

Semiconductor switch

DC-AC inverter Grid

Figure 8.29: VDE 0126-1-1 anti-islanding standard test circuit. 50% and 100% of the nominal inverter output power. 8.2.3.3

Australian Standards

The discussion of the PV grid connection standards thus-far have been with respect to the international standards in the US and Europe. As can be seen from this discussion, there is a commonality between these standards, but also some significant deviations in some aspects. The Australian standards with respect to this are no exception. The relevant standards are included in Appendix F.3. The Australian Standard appears as three related documents – Part 1 is related to the installation requirements of PV systems, Part 2 is titled “Inverter Requirements” and Part 3 “Grid protection requirements”. Only the last two are included in the Appendix. The inverter requirements relate to limits on certain parameters that the inverter can impose on the grid. For example, there are limits on the odd and even current harmonics that the inverter can inject, the nominal voltage that it operates at, the frequency, the power factor range that the inverter should operate at, limits on the transient voltages when the inverter is disconnected from the grid, and so on. These will not be reproduced here as the interested reader can look at the standards themselves that appear in the Appendix. A few comments on some of the standards. With respect to the current harmonics, one can see from comparing Table 8.6 with the equivalent one in Appendix F.3.1 that the Australian Standard is based on the IEEE/IEC standard in this area. The Australian Standard on DC current injection is very similar to those of the IEEE, IEC and VDE. As can be seen from Appendix F.3.1 the DC current is limited to 0.5% of the rated output current, or 5mA, which ever is the greater. These limits are to be tested under all the operating power levels. There is no requirement for tripping if this is exceeded in operation, as is the case with the VDE 0126-1-1 German standard. One other standard that was not mentioned in the discussion of international standards was the impulse protection standard. This is an important standard test that an inverter must pass to ensure that it can withstand a voltage impulse on the grid without being destroyed. Such impulses can occur due to circuit breaker intervention during faults, but also as a result of lightning strikes on the grid lines. Clearly if an inverter cannot withstand such events then it will have a very poor reliability. In the case of the Australian standard it resorts to a compliance test based on the IEC 60255-5 impulse testing procedure. Under the Australian Standard the PV inverter must be able to stand an impulse with 0.5 Joules of energy at a voltage of 5kV and and what is known as a 1.2/50

8-52

Grid Connected Converters and Renewable Energy Systems Voltage Vˆmin Vˆmax 1φ: 200 → 230V 1φ: 230 → 270V 3φ: 350 → 400V 3φ: 400 → 470V

Frequency fmin fmax 45 → 50Hz 50 → 55Hz

Table 8.8: Australian Standard voltage and frequency limits.

waveform. This type of waveform is shown in Figure 8.30 with the various time definitions on it. The name of the waveform arises from the fact that the nominal rise time tr is 1.2µsec, and the tail time tt is 50µsec. Remark 8.47 The impulse voltage waveform specification should not be confused with transient voltage specification. The later is all about transients that are produced by the disconnection of the inverter itself, whereas the later is externally imposed transient voltage waveforms. n The grid protection section of the standards has to do how the inverter responds to externally generated conditions such as over-voltage, under-voltage, frequency variations and islanding. So the specification says what the anti-islanding behaviour will be and the basic algorithms that should be used to achieve this, as well as physically how disconnection occurs (i.e. does an electromechanical switch need to be used). In the event of anti-islanding disconnection occurring the standard then specifies the reconnection procedure. As an example, islanding detection can be passive, which means that the inverters sensors are looking for voltages or frequencies that go outside the grid specifications. The other type of islanding that has to be present is active islanding detection. These techniques involve injection of some type of a test signal and then measuring the results and deducing whether the grid is still connected to the inverter. There are a number of different techniques for doing this, and it is still a very active area of research. For example, one technique is to look for grid impedance changes by the inverter injecting a current pulse into the grid and local load. The reconnection procedure under the Australian Standard is not dissimilar to the international standards. To under standard the reconnection conditions one needs to know the limitations on the voltage and frequency for the Australian system. These are summarised in Table 8.8. Given these definitions we can now summarise the reconnection procedure as follows: a. the voltage on the grid has to be maintained within the range Vˆmin → Vˆmax for at least 1 minute; and b. the frequency of the grid has to be maintained with the range fmin → fmax for at least 1 minute; and c. the inverter is phase synchronized with the grid at the time of reconnection. For more information about the Australian Standards on PV inverters the interested reader should read the detailed Standards in Appendix F.3.

8.2 Photovoltaic Inverters

8-53

Voltage

Time

Figure 8.30: Lightning impulse test waveform.

8.2.4

Grid Synchronization and Related Control for PV Systems

One of the key aspects of making a PV inverter system (or any other renewable source) operate with the grid is being able to synchronize the output of the inverter with the grid system. This synchronization needs to be very accurate, as small angle differences can result in large transfers of power from the inverter to the gird (or vice-versa). In addition to accurate phase knowledge, the grid voltage and inverter currents also have to be accurately known. These quantities are usually far from idea in nature, and can have considerable harmonic pollution and noise in them as raw measurements. Therefore any filtering or estimation technique has to be capable of rejecting the noise and harmonic pollution, and at the same time achieve reasonable bandwidth so that the PV inverter can see grid condition changes as quickly as possible. Grid synchronization is not only required for normal operation of the inverter, but it is also used as part of passive anti-islanding algorithms. Being synchronized to the grid allows accurate determination of the frequency of the supply, for example, which is one of the key values used for passive island detection. Furthermore, many grid synchronization techniques also allow accurate voltage magnitude to be determined, which again is required for passive islanding detection. Most of the techniques for grid synchronization are based on the use of a Phase Locked Loop (PLL), or a closely associated algorithm. The PLL was

8-54

Grid Connected Converters and Renewable Energy Systems

Reference

Phase detector

Loop filter

Voltage controlled oscillator Signal phase-locked to the reference

Figure 8.31: Classic PLL block diagram. originally a concept from communications – one of the main ways of demodulating FM for example is based on the use of hardware PLLs. We shall briefly review the concept of the PLL as applied in communication systems, and then consider some specific implementations used in PV inverters and other grid connected distributed generation systems. In addition to PLL methods for detecting synchronization, techniques using adaptive filtering will also be very briefly reviewed. 8.2.4.1

Brief review of PLLs

As mentioned in the previous section PLLs were originally introduced as a component in communications systems, and had particular application in the demodulation of Frequency Modulated (FM) signals. The earliest us of the concept was with the birth of “coherent communication” in 1932. One of the earliest uses of PLLs was in the horizontal and vertical sweeps used in television where a continuous clocking signal had to be synchronized with a periodic sync pulse. PLLs were also crucial to the development of colour television in the 1950s. In approximately 1965 the first analogue PLL integrated circuit was developed. This made the implementation of PLLs much simpler, and there was an explosion in their use. The first digital PLL appeared in 1970. Today PLLs can and are implemented entirely in software using sampled data. Every mobile phone, television, radio, pager, computer as well as many other things include PLLs as part of their circuitry or software. Subsequently they were used in other applications in communications. The PLL is essentially a control system, and therefore has been morphed into a variety of different forms to suit different applications. The use of these devices in PV inverters, and inverters in general, is but one of these additional uses. Figure 8.31 shows the general structure of a classic analogue communications PLL. As can be seen from this diagram there are three main components to a PLL – the phase detector, a loop filter (usually a first order low pass filter), and a voltage controlled oscillator. These components are arranged in a feedback control loop. Strictly speaking this feedback loop is a non-linear feedback system, however, when the loop is locked it can be analyzed using linear control theory since the behaviour is then small signal and the operation is essentially linear. The phase detector in Figure 8.31 is usually implemented in hardware with a Gilbert Cell, which is essentially an analogue hardware multiplier. The low pass

8.2 Photovoltaic Inverters

8-55

filter is usually (but does not have to be) a 1st order low pass filter. The voltage controlled oscillator (VCO) accepts an input signal and produces a sine wave at a frequency that is proportional to the input voltage. We shall now consider the operation of the PLL when it is essentially in lock under the condition that the PLL has been implemented with analogue components. We shall assume that the input signal is a sine waveform and the VCO produces a cosinusoidal waveform under steady state locked conditions. Assume that the input waveform is: uin (t) = U sin(ωi t + φi )

(8.43)

and the waveform from the VCO is: y(t) = Y cos(ωo t + φo )

(8.44)

Therefore the output of the phase detector is (since it is implemented as an analogue multiplier): x(t)

= =

∴ x(t)

uin (t)y(t)

(U sin(ωi t + φi ))(Y cos(ωo t + φo )) UY = [sin((ωi + ωo )t + φi + φo )) + 2 sin((ωi − ωo )t + (φi − φo ))]

(8.45) (8.46)

(8.47)

Remark 8.48 As can be seen from (8.47) there are two terms in this expression. One has a frequency of ωi + ωo and the other has a frequency of ωi − ωo . Clearly the second one will have a lower frequency than the first. n The waveform x(t) is subsequently filtered by a low pass filter that is designed to filter out the higher of the two frequencies present in the waveform. This would leave the term U2Y sin((ωi − ωo )t + (φi − φo )). The (ωi − ωo )t can be considered to be a low frequency changing phase denoted by φ(t). There if there is a nonzero (ωi − ωo ) term then as t becomes larger then φ(t) will become larger. This means that it is effectively integrating the frequency to get the phase. Of course if one continues to integrate frequency that the integrated value will continue to increase. Forgetting for a moment the φi − φo term, then this will mean that the VCO input would increase (albeit in a nonlinear way because of the sine function), and hence the output frequency of the VCO will change in such a way that the output frequency ωo will move towards ωi so the the φ(t) term will go to zero and therefore the integration will stop. Using this approximation we can write: UY UY UY sin((ωi − ωo )t + (φi − φo )) ≈ sin(φi (t) − φo (t)) = sin(φe (t)) (8.48) 2 2 2 where the φ(t) term representing the (ωi − ωo )t term has been folded into the φe (t) term. Remark 8.49 The implication of the previous paragraph is that the VCO is effectively acting as an integrator in the feedback loop. Unless the phase of the output of the VCO matches at all points in time the phase of the input signal then there will be a residual phase error that is integrated by the VCO to drive the phase error to zero. n

8-56

Grid Connected Converters and Renewable Energy Systems Phase detector Phase detector gain

LPF

Amplifier

+ VCO VCO gain

Figure 8.32: Block diagram of a PLL control system when in lock. Remark 8.50 The φi −φo term in (8.47) does not necessarily go to zero as there is no time term in this expression. Therefore this component of the phase error is not integrated and is only decreased by the loop proportional gain. Therefore when ωi − ωo = 0 then there can still be a static phase error. This means that the frequency of the VCO will match the input frequency, and the two waveforms are phase locked, albeit with a static phase error. n Remark 8.51 One will also note from (8.44) that the output of the VCO is a cosine waveform, whereas the input waveform is a sine waveform. Therefore there is a constant phase difference due to this alone of π2 radians. n Remark 8.52 Since the output frequency of the VCO is locked to the input frequency by the feedback process of the PLL then if the input frequency is modulated by audio for example, then in order for the PLL to remain locked the frequency of the VCO must track the modulated frequency changes. Therefore the input to the VCO will not be zero or a constant value but will track the frequency changes of the input. Therefore in an FM system this input if the demodulated signal. n When locked and the frequency related phase error is zero or very close to it the model of an electronic PLL becomes that shown in Figure 8.32. As can be seen in this figure there are gains associated with the phase detector and the VCO. Strictly speaking the loop is still non-linear since the term from the phase detector is still that in (8.48). However if the φe (t) term is small then we know that sin θ ≈ θ if θ is small, therefore we can represent the output of the phase detector as θe . Remark 8.53 It should be recognised that the above description of how the PLL works is only valid if ωi ≈ ωo . If this is the case then the assumption that Rt φe = 0 (ωi − ωo )dt + (φi − φo ) is valid. This integration is where the integrator comes from in the block diagram of Figure 8.32. Since the φe is driving the VCO until the frequency error becomes zero, and the φe value is effectively ω × t (and t is increasing as time does), then the VCO implicitly has an integrator in it (as mentioned previously). Incidentally this is not obvious. n

8.2 Photovoltaic Inverters

8-57

Remark 8.54 One aspect of VCO operation that we have not touched on is the fact the the VCO is set initially to output a non-zero frequency. This frequency is called the centre frequency, and it is usually set to be close to the expected input frequency. Classic PLLs have a capture range around this frequency, where the capture range is the maximum input frequency deviation from the centre frequency where the PLL will pull into lock. The process of capture is highly non-linear. We shall not discuss this here any further, but the interested read is encouraged to look further in the wealth of literature available on PLLs. n The following linear analysis of the PLL is essentially taken from [27]. We shall define the centre frequency of the VCO to be ωo . Therefore the output frequency of the VCO would be: ωosc = ωo + Ko Vo (8.49) Clearly the block diagram in Figure 8.32 is a classic feedback control system, and the transfer function is of the form: G(s) Y (s) = U (s) 1 + G(s)H(s) where the G(s) = KD AF (s) and H(s) = can be written as:

∴

Vo (s) φi (s)

=

Vo (s) φi (s)

=

Ko s .

(8.50)

Therefore the transfer function

Ko AF (s) 1 + KD AF (s) Kso Ko AF (s)s s + KD AF (s)Ko

(8.51) (8.52)

In communications applications one is usually interested in the response of the PLL to frequency inputs – i.e. how fast can the loop track loop variations. The above transfer function can be modified by realising that: ωi

=

⇒ ωi (s) = Vo (s) ∴ = ωi (s)

dφi dt sφi (s) 1 Vo (s) Ko AF (s) = s φi (s) s + KD AF (s)Ko

(8.53) (8.54) (8.55)

Remark 8.55 If F (s) = 1 the (8.55) is clearly a first order low pass filter. Loops with F (s) = 1 are therefore called first order PLLs. If should be noted that these loops cannot be used in practice as the double frequency component will not be filtered out and will disrupt the locking of the loop. n If (8.55) is made a 1st order loop, then the transfer function for the loop becomes:    Vo (s) Kv 1 = (8.56) ωi (s) s + Kv Ko where Kv = Ko KD A Remark 8.56 Equation (8.56) has a single -3db point of Kv rad/sec (in other words a time constant of τ1 secs), and a DC gain of K1o . Therefore the output voltage will response as a 1st order function with respect to a step change in the input frequency. n

8-58

Grid Connected Converters and Renewable Energy Systems

Closed loop pole

Open loop pole

(log scale) Root Locus

Closed-loop response

Figure 8.33: Root locus and Bode plot for a 1st order classic PLL. Figure 8.33 shows the Root Locus and Bode plot for the 1st order PLL. As can be seen the bandwidth of the loop is set by the open loop gain Kv and the DC gain by the inverse of the VCO gain. Due to the presence of the implicit integrator the PLL is a natural low pass filter. As mentioned previously the 1st order loop is never used because of the propagation of the high frequency terms around the loop. Most practical PLLs are 2nd order loops that employ a 1st order filter in the feedback path – i.e. F (s) is a 1st order filter using implemented with a resistor and capacitor on the case of integrated circuit PLLs. Therefore we can write the filter as: ! 1 F (s) = (8.57) 1 + ωs1 which allows the overall transfer function of the PLL to be now written as follow when we substitute into (8.55): ! 1 Vo (s) 1 = (8.58) 2 ωi (s) Ko 1 + Ks + ω sK v 1 v The Root Locus and Bode plot for this transfer function appears in Figure 8.34. Clearly the roots of the transfer function are: ! r 4Kv ω1 s=− 1± 1− (8.59) 2 ω1 Equation (8.58) can also be written in the classic 2nd order form as follows. This allows the easy identification of resonant frequency, resonant natural frequency and damping coefficient parameters. A brief review of 2nd order equations in Appendix A is recommended for the reader who has forgotten the details of this. Equation (8.58) can now be written as: ! 1 1 Vo (s) = (8.60) ωi (s) Ko ωs22 + ω2ζ s + 1 n n

8.2 Photovoltaic Inverters

8-59

(log scale)

Root Locus

Bode Plot

Figure 8.34: Root locus and Bode plot for the 2nd order PLL. where: ωn

=

ζ

=

p

Kv ω1 r 1 ω1 2 Kv

(8.61) (8.62)

Figure 8.34 shows the root locus and Bode plot for the 2nd order PLL. As can be seen as Kv increases the poles of the system become resonant in nature. This can be seen in the Bode plot, with the resonant peak in the frequency response at around Kv rad/sec. The loop bandwidth is primarily determined by Kv . To tune the loop Kv is chosen for the bandwidth required, and then ω1 is chosen as low as possible without causing unacceptable resonant behaviour in the loop. One good compromise is to chose the pole positions to be at the Butterworth filter positions which is a maximally flat response. This means that the poles at at an angle of 45◦ with respect to the real axis in the Root Locus. Mathematically this means that: 1 ζ=√ (8.63) 2 and we can therefore write: r 1 ω1 1 √ = (8.64) 2 Kv 2 which means that: ω1 = 2Kv

(8.65)

Remark 8.57 This last expression means that the filter pole and the overall loop gain (and therefore loop bandwidth) are not independent. Furthermore (although we have not shown it) the lock range is also dependent on Kv . Therefore one cannot can have a wide lock range, for example, and at the same time have good noise rejection. n This situation can be improved by the introduction of a zero into filter F (s). The if the zero is positioned correctly with respect to the pole of the filter, then

8-60

Grid Connected Converters and Renewable Energy Systems Loop gain with loop filter and zero (log scale)

Crossover frequency

1

Phase

Improved phase margin

Figure 8.35: Open loop Bode plots for a 2nd order PLL with zero added. sufficient phase margin can be achieved in the closed loop Bode plot to allow the filter bandwidth to be reduced (i.e. a low cut-off frequency for the feedback) independently of the lock range. The effect of adding a zero to the filter can be seen in the open loop frequency response of the PLL in Figure 8.35. As can be seen, at the unity gain point the phase of open loop phase is approximately < 180◦ as compared to 180◦ in the case of the simple 1st order filter. This means that the phase margin has been improved considerably, and the resonant peaking that could occur in the 2nd order PLL case can be more easily handled. Figure 8.36 shows the closed loop magnitude frequency response of the PLL with the zero added into the filter. Notice that there is another degree of freedom with the loop since the frequency response of the loop is determined by the interaction of three parameters – Kv , ω1 and ω2 . Therefore the lock range, which is directly related to the loop gain, can be determined independently of the closed loop bandwidth. 8.2.4.2

Brief Review of Synchronisation Techniques for Power Systems

The previous section presented an overview of the operation of the traditional PLL and various issues associated with the analysis and design of the loop for particular performance. In this section we shall build on this by giving an overview of how techniques related to the PLL are used for grid synchronisation in general.

8.2 Photovoltaic Inverters

8-61

40db/decade

Figure 8.36: Closed loop magnitude response of a 2nd order PLL with zero added. Remark 8.58 Grid synchronisation is required not only in photovoltaic systems that are interfacing to the grid, but to any system that needs to synchronise. These techniques there have widespread use in power system control in general. n The use of the PLL in power system applications leads to some issues that do not arise in communications applications. Consider (8.47) for the traditional PLL, which I have rewritten here for convenience:

x(t) =

UY [sin((ωi + ωo )t + φi + φo )) + sin((ωi − ωo )t + (φi − φo ))] 2

(8.66)

In communications applications the ωi frequency is usually very large, and ωo is small by comparison. Therefore the ωi + ωo frequency (the high frequency term) is large compared to ωi − ωo (the low frequency term). Therefore it is easy to set the bandwidth of the loop filter to get rid of the ωi + ωo term almost totally without affecting the desired ωi − ωo term. This in turn means that the bandwidth of the loop – i.e. its ability to track transient changes in the input phase, can be increased without causing any issues with the loop performance. In power systems applications the situation is slightly different. The phase/frequency we are attempting to lock onto is the grid frequency – in Australia 50Hz or 314 rad/sec. Therefore the terms that we have coming out of the phase detector section of the loop is, assuming that the loop is in lock for the moment, 100Hz (i.e. ωi + ωo ) and DC (since in lock and steady state ωi = ωo ). However during the lock phase the ωi − ω0 term will not be zero, and is required to provide the movement towards lock. In order not to attenuate this signal too much the bandwidth of the filter cannot be set too low. Consequently some of the undesired 100Hz signal will creep through to the VCO and propagate around the loop. Remark 8.59 The propagation of the 100Hz signal around the loop in power systems applications leads to the loop being disrupted. Consequently the analysis

8-62

Grid Connected Converters and Renewable Energy Systems Quadrature phase detector

VCO cosine PI controller

Quadrature signal generator

+ + +

+

sine

Figure 8.37: Basic in-quadrature PLL. of loop performance that appears in most books on PLLs is not applicable to power systems, since in the applications that these books consider the double frequency component is a much higher frequency than the loop bandwidth. In the power systems situation the effect of the 100Hz ripple getting through the filter is that the PLL takes a lot longer to lock compared to the time predicted by the theory. n In order to get better performance from PLLs when used in power systems applications, almost always some sort of in-quadrature based PLL is used. This approach allows the analysis that is applied to PLLs in communications to be applied to power systems PLLs. Remark 8.60 It is ironic that in the case of PLLs the use of three phase PLLs is simpler than the single phase counterparts. This is mainly due to the fact that an in-quadrature signal has to be generated somehow from the one input signal. n The essential idea behind in-quadrature PLLs is that from a single input waveform an orthogonal waveform is produced (i.e. 90◦ out of phase with the input). Clearly, if the input waveform in not a pure sinusoidal waveform then this process has to be applied to the various harmonic components as well. Remark 8.61 The production of the in-quadrature component produces a two phase system, and consequently its properties are the same as a three phase system, since any three phase system can be converted into an equivalent two phase system. n Now for a little more detail of what is behind in-quadrature processing for PLLs. The input signal, which we shall assume for the moment that the input signal is xin (t) = Xin sin(ωt + φ). This signal is input to the quadrature generator that produces an output signal xq (t) = −Xin cos(ωt + φ). These two signals are in turn multiplied by the feedback signals, which due to the operation of the PLL are 90◦ out of phase with the two input signals. Finally the two resultant signals from this multiplication are added together and effectively form the output of the phase detector. Figure 8.37 shows the basic structure of this type of PLL. In order to understand the advantage of this approach to the PLL a little mathematics is required. If we consider what is happening at the phase detector

8.2 Photovoltaic Inverters

8-63

multiplier we can write the following expressions: εpd

= X[sin(ωt + φ) cos(ω 0 t + φ0 ) − cos(ωt + φ) sin(ω 0 t + φ0 )] (8.67) = X[sin(ωt + φ − (ω 0 t + φ0 )] 0

(8.68)

0

= X[sin((ω − ω )t + (φ − φ ))]

(8.69)

Clearly if the loop is close to lock then ω − ω 0 is small and therefore the φ terms and the ω terms can be rolled into one to give the following expression: εpd ∴ εpd

= X sin(ωt + φ − (ω 0 t + φ0 )) 0

= X sin(θ − θ )

(8.70) (8.71)

where θ = ωt + φ and θ0 = ω 0 t + φ0 . Remark 8.62 One can see that the main advantage of the in-quadrature approach is that there is no longer an ω + ω 0 term appearing out of the phase detector. Therefore the signal emanating from the phase detector does not required the same degree of filtering. In the case of a power system synchronisation PLL where this double frequency component was disrupting the loop performance from the ideal behaviour, the use of the quadrature PLL means that the transient performance of the loop will now conform to the theory. n One can see from Figure 8.37 that the output of the phase detector is now fed into an PI controller. The use of the PI controller here will ensure that the phase detector error term εpd will be forced to zero when in lock, which in turn means that the θ − θ0 = 0 in (8.71). Therefore the PLL has locked onto the phase of the signal with zero phase error, and the PLL is also giving the frequency of the input signal, and the two quadrature components. Remark 8.63 The main issue with the in-quadrature approach when there is a single phase input signal is the production of the quadrature component of the signal. This is especially a problem when there are harmonics present in the input waveform. We will briefly consider in the following paragraphs some techniques to do this. n We can test the above algorithm by setting up a simple simulation. In this case the simulation has been carried out using the public domain dynamic system simulation and matrix computation system called Scilab/Xcos (available for Windows, Linux and Mac OSX from http://www.scilab.org). You can download this system and load up the file for this simulation if you want to experiment. It will be made available on the Blackboard system. Figure 8.38 shows the Xcos model for the in-quadrature PLL used for the simulation. The performance of this PLL is shown in Figures 8.39, 8.40 and 8.41. In this simulation the input frequency and the centre frequency are equal to 2π × 50 radians/sec at t = 0. At t = 1 sec the frequency becomes 2π×51 radians/sec. Figure 8.39 shows the input waveform and the fed back sine waveform (both normalised to unity amplitude). The part of the response shown is around the area where the input frequency undergoes the step change. One can see that there is virtually no difference between the two waveforms – they are sitting on top of each other. This can be seen from Figure 8.40 which is the error between the two normalised waveforms (i.e. both the input waveform and the output waveform have an amplitude of

8-64

Grid Connected Converters and Renewable Energy Systems

Figure 8.38: Xcos simulation model of the basic in-quadrature PLL. 1). Therefore the maximum error due to phase error is 5% in instantaneous amplitude. One can also see that the within about 200 msec this has converged back close to zero. The final figure, Figure 8.41 shows the output of the PI controller used in the PLL. The integrator in this controller essentially stores the frequency difference between the input and the output frequency. As can be seen from the Figure then difference becomes 2π at t = 1.0 secs. This difference is then added to the centre frequency to give the estimated input frequency. Once can see that the transient performance of this is quite good, with the correct input frequency being identified in approximately 20 to 30 msec. Remark 8.64 The transient response of the PLL can be improved by raising the feedback gain, but this also lets more noise into the loop. It is the inevitable trade-off between bandwidth and noise rejection. n The quadrature signal generator (Figure 8.38) is developed as follows. The step change generator in the diagram is the desired frequency (it is a step change generator to allow transient changes in frequency to be input for testing purposes). The frequency ω is passed into an integrator: Z θ=

t

ω dt

(8.72)

0

This θ term is in turn passed to a A × sin function and the output is A sin ωt as required. In order to generate the quadrature waveform this wave form is passed through an integrator. The output is: Z t A A A A sin ωt dt = − (cos ωt − 1) = − cos ωt + (8.73) ω ω ω 0 Therefore in order to get −A cos ωt we need to multiply the above expression by ω and subtract off A. Remark 8.65 In practice one cannot use this technique to generate the quadrature waveform – why is this the case? Answer: one would have to know the amplitude and radian frequency of the waveform. Since we do not control the input waveform we have no idea what these quantities are. n

8.2 Photovoltaic Inverters

Figure 8.39: Xcos simulation result – input waveform and feedback sine waveform.

Figure 8.40: Xcos simulation result – the error between the input waveform and the sine feedback waveform.

8-65

8-66

Grid Connected Converters and Renewable Energy Systems

Figure 8.41: Xcos simulation result – the output of the PI controller which indicates the difference between the input frequency and the loop centre frequency. The quadrature signal generator is simple to do in the case of the simulation since one can artificially create the waveforms. However, in the case of true input waveforms, which may contain harmonics, this task is not quite as simple. For example if the waveform was of the form: x(t) = A1 sin ω1 t + A2 sin ω2 t

(8.74)

then it is not known what the amplitudes are (i.e. we do not know A1 and A2 ) and we have an estimate of, say, ω1 only. The particular harmonic frequency may not be known. Therefore if the integration approach is taken to generate the quadrature component we have: Z t A1 A2 A1 A2 x(t) dt = − cos ω1 t − cos ω2 t + + (8.75) ω1 ω2 ω1 ω2 0 Remark 8.66 One can see from this expression that one would have to be able to pull the harmonic components apart to apply the correct to the amplitudes and to subtract off the offsets (if they are known). n Remark 8.67 One can also see from (8.75) that the correct phase relationship is maintained between the harmonics – for example, the A2 sin ω2 t term and the 2 −A ω2 cos ω2 t have the correct in-quadrature relationship. Therefore the integration does preserve this if one is attempting to get the PLL to synchronise to the ω2 frequency. n One can make a clear connection between the single phase in-quadrature signal processing an dq or space vector processing that we are familiar with in variable speed drives and other three-phase power systems applications. If one considers

8.2 Photovoltaic Inverters

8-67

Phase detector (PD)

Frequency to phase angle generator (FPG) PI controller

Quadrature signal generator

+ +

Figure 8.42: In-quadrature PLL implemented with a Park transformation. (8.67) one can see that the quadrature outputs of the quadrature generator can be written as:     vα sin(ωt + φ) vαβ = =X (8.76) vβ − cos(ωt + φ) Using some definitions from above we can write generate the εpd term out of the phase detector as: vd = vα cos θ0 + vβ sin θ0 (8.77) We know from the two phase stationary frame to two phase rotating frame transformations present in (B.79) in Section B.3.2 on page B-14 (repeated here for convenience in slightly different notation):      vd cos θ sin θ vα = (8.78) vq − sin θ cos θ vβ that the above quadrature signal generation is basically the same as a two stationary frame to rotating frame transformation – i.e. a Park transformation. In Figure 8.37 we are only utilising the vd component in the PLL. This realisation allows use to draw the PLL of Figure 8.37 in a slightly different form as shown in Figure 8.42. This PLL can also be used for three phase systems. The block diagram for this situation is shown in Figure 8.43. As can be seen the three phase values are fed into a Clark Transformation which essentially outputs the two phase stationary frame values which are equivalent to the quadrature values. Notice in this figure that we have drawn the PLL as a control system, explicitly showing the feedback processes that form the loop. Remark 8.68 If the control loop in Figure 8.42 is doing its job correctly then the xd signal will be driven to zero (by the action of the PI controller). If one considers the system to be a two phase system with xα and xβ inputs, then this means that the θ0 angle will be 90◦ out of phase with the angle of the xαβ space vector representation of the in-quadrature stationary frame inputs. n Remark 8.69 If one looks carefully at Figure 8.42 one can see that it is exactly the same as the model in Figure 8.38 n Figure 8.44 shows the space vector representation of the space vector of the quadrature signals relative to the stationary frame αβ axes, and the projection

8-68

Grid Connected Converters and Renewable Energy Systems

!®

vd¤

+

¢! + -

+

!

μ

vd

Park Transformation

vq

v¯

v®

va vb vc

Clark Transformation

Figure 8.43: The three phase quadrature PLL using a Park Transformation. of this vector onto the rotating dq axes. In this particular case the x vector is not aligned with the q axis, so there is a projection onto the positive d axis. It is this value that is multiplied by −1 and then pass it into the PI controller whose output becomes the ∆ω value that is added to the centre frequency of the PLL. The value of ∆ω in this particular case will be a negative value (since the vd value is negated before the PI controller), and this therefore means that the rotation speed of the dq frame will be slowed down as it will be effectively subtracted from centre frequency. This resultant frequency is then integrated and becomes the θˆ value that is used to generate the position of the dq axes. Since the frequency of the dq frame is being lowered this means that the angle θˆ increasing at a slower rate, which in turn means that the angle γ is increasing and the x is moving more in-line with the q axis. Eventually the x vector will be in-line with the q axis, and then there will be no projection of the vector onto the d axis. At this point the PLL has locked, and the θˆ value is at ∠x − π2 radians and ω ˆ = ω. Note that the q axis value is clearly |x| at this convergence point as well. This situation is shown in Figure 8.45. The in-quadrature PLL was programmed up in the Python language.3 This version shows how the algorithm may be programmed up, and also has the addition of generating a fifth harmonic in the input waveforms to see how the PLL copes with this. A listing of the software appears in Appendix G. This listing contains more than the code of the two phase PLL. It also contains code for other variants of PLLs (which are not the current subject of discussion as 3 Python is a very powerful freeware object oriented language that is flexible enough to be used to implement websites and coordinate nuclear explosion simulations at Los Almos. It has a very powerful numeric library that offers matrix manipulation facilities similar Matlab at compiled speeds. In addition there is a library that mimics the graphics plotting facilities of Matlab. For Windows the best version of Python(x,y) available at http://www.pythonxy.com. For the MAC the best version if Enthought Python available at http://www.enthought.com.

8.2 Photovoltaic Inverters

Figure 8.44: Space vector representation of the convergence process of a Park Transformation based quadrature PLL.

8-69

8-70

Grid Connected Converters and Renewable Energy Systems

Figure 8.45: Space vector representation when the Park Transformation quadrature based PLL is locked.

8.2 Photovoltaic Inverters

8-71

α axis values

50

0

50

100

4900

5000

5100

5200

5300

5400

Figure 8.46: Two phase PLL implemented in Python showing the estimated waveform versus the actual waveform. well). The test conditions for the following plots are: Amplitude of the input signal is 100; initial frequency of the input is 50Hz; the sampling frequency is 5kHz; there is a step change in the input frequency from 50Hz to 60 Hz at 5000 samples (i.e. 1 sec) into the simulation4 . The in-quadrature waveforms are simply defined as in-quadrature – i..e the simulation does not develop the inquadrature waveforms from a single phase waveform. Figure 8.46 shows the identified α axis waveform from the PLL (there is also an amplitude estimator so that the original waveform can be constructed from an estimated phase and amplitude). The true waveform is shown as a solid line, and the estimated waveform as a dashed line. One can see at the point of the step change that the true waveform line becomes visible. If one move to the right further in the waveform, then these two waveforms again merge over the top of one another. Figure 8.47 shows estimated ∆ω centre frequency error that is added to the centre frequency to generate the actual frequency. One can see that there is very rapid identification of the new frequency. The correct ∆ω value is 62.8 radians (i.e. 10Hz), and this is the value shown in this plot if a cursor is place on the line to the right of the 5000 sample point. The power supply is rarely an ideal sinusoid. One interesting question is how does this PLL operate under this condition. Figures 8.48 show the same plots as above, but for the situation where there is a significant 5th harmonic in the input 4 This step change in frequency is quite large, and far larger than would be experience in power systems applications. This change was chosen to demonstrate the tracking capability of this PLL.

8-72

Grid Connected Converters and Renewable Energy Systems

Estimated Frequency Error 60 50 40 30 20 10 0 4500

5000

5500

Figure 8.47: Two phase PLL implemented in Python showing the estimate frequency error from the centre frequency of the PLL. – the amplitude of the 5th harmonic is 30% of the fundamental. As can be seen there is significant distortion in the estimated waveform, and Figure 8.49 shows that there are very large oscillations in the estimated frequency error ∆ω. The filtering action of the frequency integrator smooths this to some degree, but still allows significant phase distortion through which would render the PLL unusable in these applications. A low pass filter can be placed in the ∆ω part of the loop, and the resulting ∆ω plot is shown in Figure ??. The gains in the PI feedback also have to be lowered to ensure that the loop is stable, but even with this there are substantial oscillations in ∆ω. The lower gains also mean that the phase convergence is very slow. Remark 8.70 The upshot of the simulations with the 5th harmonic input injection is that the two phase in-quadrature PLL does not work very well. n The issue of generation of the quadrature signal when the input is a single phase signal is not simple, especially when harmonics are present. One popular technique used when the frequency of the input is well known (such as in power system applications) is the T4 transport delay. Clearly this technique is based on the idea that a delay of T4 where T is the period of the fundamental waveform is effectively a −90◦ phase shift. The practical implementation of the T4 delay can be achieved by a digital shift register where the sampled digital values are shifted on each clocked sample. The length of the shift register is T4 secs. Remark 8.71 The

T 4

phase shift technique will have difficulties when there are

8.3 Wind Turbine Converter Systems

8-73

α axis values 100 50 0 50 100 4800

4900

5000

5100

5200

Figure 8.48: Two phase PLL implemented in Python showing the estimated waveform versus the actual waveform when there is a 30% 5th input harmonic.

harmonics in the supply and it the frequency of the supply varies over a wider range of frequencies. n STILL HAVE TO ADD MORE HERE ON OTHER TYPES OF SYNCHRONISING STRATEGIES.

8.2.5

Islanding Detection Techniques

Yet to be written.

8.3

Wind Turbine Converter Systems

Yet to be written.

8.3.1

Grid Requirements for Wind Turbine Systems

Yet to be written.

8.3.2

Grid Synchronization for Three Phase Systems

Yet to be written

8-74

Grid Connected Converters and Renewable Energy Systems

Estimated Frequency Error 300 200 100 0 100 200 4600

4700

4800

4900

5000

5100

5200

Figure 8.49: Two phase PLL implemented in Python showing the estimate frequency error from the centre frequency of the PLL when there is a 30% 5th input harmonic.

8.3 Wind Turbine Converter Systems

8-75

Estimated Frequency Error

120 100 80 60 40 20 0 200

2000

4000

6000

8000

10000

Figure 8.50: Two phase PLL implemented in Python showing the estimate frequency error from the centre frequency of the PLL when there is a 30% 5th input harmonic and filter.

8-76

Grid Connected Converters and Renewable Energy Systems

8.3.3

Brief Overview of Wind Turbine Converter Control

Yet to be written.

Part III

Appendices

Appendix A

Review of Second Order Circuits This appendix will give a brief review of second order circuits. This is included as second order series and parallel circuit inevitably come into high speed digital systems due to the presence of inductance and capacitance in the various circuits.

A.1

Series RLC Circuits

Consider a circuit of the form shown in Figure A.1. Carrying out standard loop analysis we can write the following differential equation for this circuit: R

di d2 i i dvin +L 2 + = dt dt C dt

(A.1)

Taking the Laplace Transform of (A.1) we can write the following transfer function for the current: i(s) sC = 2 vin (s) LCs + RCs + 1

transfer function

(A.2)

and therefore the transfer function for the voltage across the capacitor is: vo (s) 1 = 2 vin (s) LCs + RCs + 1

(A.3)

One can see that the poles of (A.3) are: R ± s=− 2L

r

R2 1 − 4L2 LC

poles

(A.4)

which can be written as: s = −α ±

p

α2 − ωo2

(A.5)

A-2

Review of Second Order Circuits

R

+ vin

C

vout

i

-

L Figure A.1: Series RLC circuit where: R 2L 1 ωo = √ LC α=

natural resonant frequency resonant frequency damping factor

(A.7)

One can get a better impression of the position of the poles if they are plotted on the complex plane. This is shown in Figure A.2. Note that this diagram is only showing one of the two conjugate poles. We can define several other terms from this diagram. The natural resonant frequency, ωd , is the frequency of oscillation of the natural response (i.e. source free response) of the circuit when there is resistance present. This is different from the resonant frequency, ωo , which is the resonant frequency of a lossless series RLC circuit.1 Another variable of interest is the damping factor . The formal definitions are: p ωo2 − α2 (natural resonant frequency) α ξ = cos θ = (damping factor) ωo

ωd =

critical damping

(A.6)

(A.8) (A.9)

From Figure A.2 one can see that if the poles are off the real axis of the complex plane then there is a projection of the complex vector onto the imaginary axis. This means that there is an oscillatory mode in the response of the circuit. If the angle θ is zero, then the two poles are coincident. This condition corresponds to critical damping.2 Because there is not projection onto the imaginary 1 The resonant frequency is the frequency at which a driven series RLC circuit will exhibit is minimum impedance.

A.1 Series RLC Circuits

A-3 Im wo

wd

wo

q

Re

a

Figure A.2: Series RLC circuit pole positions. axis there is no oscillatory or over shoot behaviour in the response. From the viewpoint of the equations critical damping corresponds to the condition: p ωd = ωo2 − α2 = 0 (A.10) Therefore critical damping means that: α = ωo 1 R =√ 2L LC r L ∴R=2 C

(A.11)

For the case where: α > ωo

(A.12)

we have two real poles generated. One the these poles will move towards the left on the real axis and the other to the right. The system response is now very slow, and it is said to be over-damped . There are no oscillations. Another important property of a series RLC circuit is its impedance. Rearranging (A.2) we can write the impedance transfer function: Z(s) =

vo (s) LCs2 + RCs + 1 = i(s) Cs

(A.13)

If we let s = jω (i.e. the resonant frequency), and substitute this into (A.13) we get: 1 ωL − jωC j  2  ω LC − 1 =R+j ωC

Z(s) = R +

2 Critical

damping gives the fastest response without overshoot.

(A.14)

over damped

A-4

Review of Second Order Circuits Clearly the magnitude of this expression has a minimum value when the imaginary term is zero. Therefore: ω 2 LC − 1 = 0 ⇒ ω = √

1 = ωo LC

(A.15)

The minimum impedance is R under this condition. As noted earlier, this occurs at the resonant frequency (ωo ), and not the natural resonant frequency (ωd ).

A.1.1

Quality Factor

Another important measure of resonant second order circuits is the quality factor – Q. When a circuit is being driven in resonance this is defined as: Q , 2π

Total energy stored in the circuit Energy dissipated per period

(A.16)

In the case of the series RLC circuit consider it to be driven with i(t) = Im cos ωo t. The expression for the instantaneous energy stored in the inductor is: 1 1 2 eL (t) = Li2 = LIm cos2 ωo t (A.17) 2 2 Similarly the energy stored in the capacitor can be calculated as follows. We know from the relationship between the current and voltage for a capacitor that: Z 1 t Im cos ωo t dt (A.18) v = C 0 Im ∴v = sin ωo t (A.19) ωo C We can therefore write: v2 =

2 Im sin2 ωo t 2 ωo C 2

(A.20)

Consequently we have: eC (t) =

2 1 2 1 Im I2 L Cv = sin2 ωo t = m sin2 ωo t 2 2 2 ωo C 2

(A.21)

using (A.15). Therefore the total energy is: eL (t) + eC (t) =

1 2 1 2 LI (cos2 ωo t + sin2 ωo t) = LIm 2 m 2

(A.22)

which is obviously a constant. The average power dissipation in a resistor with a sinusoidal input is: PR =

1 2 I R 2 m

(A.23)

and hence the energy dissipated over a period To is: PR T =

1 2 1 2 I RTo = I R 2 m 2fo m

(A.24)

A.1 Series RLC Circuits

A-5

Using (A.22) and (A.24) in (A.16) one can write: Q = 2π

1 2 2 LIm 1 2 2fo Im R

L = ωo R r 1 L ∴Q= R C

= 2πfo

L R

using ωo = √

1 LC

(A.25)

If Q = 0.5 then: 1 R= Q

r

r L L =2 C C

(A.26)

which is the same expression for the resistance when the circuit is critically damped. If Q = 1 then we have: r L (A.27) R= C which is the same expression for the characteristic impedance in transmission lines. It also means that the energy stored in the circuit is the same as the energy dissipated per cycle. Therefore the energy that has to be replace per cycle is the same as that energy dissipated in the resistor which is the same as the stored energy.

A.1.2

Time Domain Response

Let us now consider the time domain solution of (A.3). In this we shall be assuming that for t < 0 then vin (t) = V0 , and at t ≥ 0 vin (t) = 0 – i.e. the voltage drops to zero. Therefore the circuit becomes a source free circuit with an initial voltage on the capacitor of V0 volts. Therefore we only need to consider the natural response of the circuit. This situation will also give us a lot of information about the case when there is a positive step in the voltage. Examination of (A.1) suggests that a possible candidate solution is: v0 (t) = A1 es1 t + A2 es2 t

(A.28)

s1,2 = −α ± jωd

(A.29)

where: Expanding the exponential terms in this equation we can write: v0 (t) = e−αt [B1 cos ωd t + B2 sin ωd t]

(A.30)

where: B 1 = A1 + A2

(A.31)

B2 = j(A1 − A2 )

(A.32)

Remark A.1 Equation (A.30) is the solution for the underdamped situation in an RLC circuit. Underdamping is characterised by α2 < ω02 , which means that s1 and s2 in (A.28) are complex terms.

A-6

Review of Second Order Circuits In order that we can determine the B1 and B2 coefficients we apply some boundary conditions: v0 (0) = V0

(A.33)

dv0 (0) =0 dt

(A.34)

Applying the first of these conditions to (A.30) we can write: B1 = V0

(A.35)

Taking the derivative of (A.30) we get: dv0 = e−αt [(B2 ωd − αB1 ) cos ωd t − (B1 ωd + αB2 ) sin ωd t] dt

(A.36)

Applying (A.34) to this expression gives: αB1 = B2 ωd ⇒ B2 =

αV0 ωd

and hence the voltage equation becomes:   α sin ωd t v0 (t) = V0 e−αt cos ωd t + ωd

(A.37)

(A.38)

and the derivative of this is: dv0 (t) = −V0 dt

   α2 ωd + sin ωd t ωd

(A.39)

From (A.8), (A.7), (A.6) and (A.25) we can derive the following expressions: r

1 R2 − LC 4L2 r 1 1 = − LC 4LCQ2 r 1 1 =√ 1− 4Q2 LC

ωd =

(A.40)

We shall assume that Q > 0.5, which means that the circuit is underdamped and ωd > 0. If we want to find the point of the first maximum swing in the time response (i.e. the first maximum in the oscillatory response), then we know this must occur when ωd t = π. Therefore: π ωd √ π LC =q 1 1 − 4Q 2

tf m = ⇒ tf m

(A.41)

A.1 Series RLC Circuits

A-7

We also also write: v0 (tf m ) = −V0 eαtf m

since ωd tf m = π



∴ v0 (tf m ) = −V0 e

√ R  rπ LC − 2L 1− 1 2 4Q



= −V0 e

√

 



−π 4Q2 −1

(A.42)

Figure A.3 shows that time plot for a series RLC circuit. In this particular case the circuit Q is 6.3. From (A.42) we can drawn the conclusion that: 

Vovershoot /Vstep = e

√

−π 4Q2 −1



(A.43)

1 0.8

L R tO

e NM 2L QP -

0.6

Voltage v volts

0.4 0.2 0 -0.2 -0.4 - 0.6 -0.8 0

0.5

1

1.5

t fm = -p

v 0 (t fm ) = -V0e

4Q 2 -1

2 2.5 Time t (secs)

3

3.5

4

p LC 1 14Q 2

Figure A.3: Time response of a series RLC circuit with Q = 6.3.

A.1.2.1

Forced Response of Series RLC Circuit with Initial Inductor Current

In this section we shall consider the forced response of the series RLC circuit where we have an initial inductor current. The forced response will assumed to be a constant input voltage. More general forcing functions will not be considered as they are not required for the material in these notes. Consider (A.1) which is the general differential equation for the series RLC circuit. For a constant input voltage the equation becomes: R

d2 i i di +L 2 + =0 dt dt C

(A.44)

A-8

Review of Second Order Circuits The natural response for this circuit is of a similar form as that in (A.28) except that the left side of the equation is i(t). As per general theory for the solution of differential equations, the total solution is the sum of the natural response and the forced response. Therefore the solution is: i(t) = A1 es1 t + A2 es2 t + if

(A.45)

where if is the forced response. The forced response in the case of a constant input voltage is zero as the capacitor is an open circuit as time goes to infinity. Therefore the situation degrades to the simple natural response. Therefore, assuming the underdamped situation, the solution to the current equation is of the same form as (A.30) except that it is in terms of current and not voltage. It can be written as: i(t) = e−αt (B1 cos ωd t + B2 sin ωd t)

(A.46)

However the initial conditions are now different. We know the following at t = 0: i(0) = B1 = i0

(A.47)

where i0 is the initial inductor current. Taking the derivative of (A.46) we can write (similarly to (A.36)): di(t) = e−αt [(ωd B2 − αB2 ) cos ωd t − (ωd B1 + αB2 ) sin ωd ] dt

(A.48)

The second initial condition is with respect to the derivative of the current. We know that: di vL = L (A.49) dt therefore at t = 0 we have that: vL (0) Vin − i0 R di(0) = = dt L L

(A.50)

since the capacitor is assumed to be uncharged. Clearly at t = 0 the second term of (A.48) is zero, therefore we can write: Vin − i0 R L Vin − i0 R + αi0 L ∴ B2 = ωd L

ωd B2 − αi0 =

Substituting for B1 and B2 into (A.46) we can write:     Vin − i0 R + αi0 L i(t) = e−αt i0 cos ωd t + sin ωd t ωd L

A.2

(A.51) (A.52)

(A.53)

Parallel RLC Circuits

This section carries out a similar analysis for a parallel circuit RLC as was carried out above for the series RLC circuit. To a large extent the results for

A.2 Parallel RLC Circuits

A-9

this circuit configuration are a dual of those above, therefore some of the analysis here will be brief. The following discussion will be with reference to Figure A.4. If one applies nodal analysis to this figure one can write the following differential equation for the circuit: 1 dvin vin 1 diin d2 vin + + = (A.54) 2 dt RC dt LC C dt If we take the Laplace transform of this and rearrange we can get the following transfer function: 1 1 C(s2 + RC s + LC ) iin (s) = (A.55) vin (s) s

transfer function

iin

vin

R

L

C

Figure A.4: Parallel RLC circuit. The impedance transfer function can be simply written from a rearrangement of A.55 as: vin (s) s Z(s) = = (A.56) 1 1 iin (s) C(s2 + RC s + LC )

impedance transfer function

As in the series RLC circuit case we can now find the poles of this transfer function, which have a similar form to those for the series RLC circuit: p s = −α ± α2 − ωo2 (A.57)

poles

where: 1 2RC 1 ωo = √ LC α=

As with the series RLC circuit we can define: p ωd = ωo2 − α2

(A.58) (A.59)

(A.60)

Critical damping is defined similarly to that for series RLC circuits in that

Critical damping

A-10

Review of Second Order Circuits ωd = 0. This leads to: α = ωo 1 1 ∴ =√ 2RC LC r 1 1 ⇒R= 2 LC

(A.61)

The impedance of the circuit at resonance, as with the series RLC circuit, is of interest. Substituting s = jω into (A.56) and simplifying and taking the magnitude we can write: |Z(s)| = q

ω ω2 R2

+

1 L

(A.62) − Cω 2




√ If ω = ωo = 1/ LC then: |Z(s)| = R

(A.63)

which can be shown to be the maximum impedance of the circuit.

A.2.1

Quality Factor

This will not be evaluated in the same detail as was carried out in the series RLC circuit section since the development is so close. However, the key expressions will be presented. It is assumed that the input voltage has the form: vin = Vm cos ωo t Therefore the current into the inductor is: Z 1 t i= vin dτ L 0 Z 1 t = Vm cos ωo tdτ L 0 Vm ∴i= sin ωo t Lωo

(A.64)

(A.65)

The energy stored in the inductor is therefore: 1 2 Li 2 1 = Vm2 C sin2 ωo t 2

eL (t) =

(A.66)

Similarly the energy stored in the capacitor is: 1 2 Cv 2 in 1 = CVm2 cos2 ωo t 2

eC (t) =

(A.67)

A.2 Parallel RLC Circuits

A-11

The total stored energy is: eT (t) = eL (t) + eC (t) 1 = Vm2 C(sin2 ωo t + cos2 ωo t) 2 1 = Vm2 C 2

(A.68)

The energy dissipated in the resistor is: eR (t) = PR To = =

Vm2 To 2R

Vm2 2fo R

(A.69)

Applying the definition of quality factor (A.16) we can write: 1 2 V C Q = 2π 2 Vm2 m

2fo R

= 2πfo RC = ωo RC r C =R L

(A.70)

A-12

Review of Second Order Circuits

Appendix B

Introduction to Space Vectors B.1

Introduction

This appendix introduces the concept of space vectors. This introduction is carried out in a three stage process. Firstly consideration is given to machine windings to demonstrate that electrical machines can be accurately modeled using sinusoidal functions, even under conditions where there are non-sinusoidal waveforms present. The sinusoidal assumption is very important in machine modeling, and is developed because space vectors are developed based on sinusoidal function variations in machines. The second part of the appendix uses the sinusoidal assumption to develop dq models for electrical machines. Even though dq models were originally developed for electrical machines they find much more general use in power systems and power electronics where one has three phase supplies. Finally space vector models are developed as an extension of dq modeling, and the connections between them are shown.

B.2

The Sinusoidal Assumption

One of the main assumptions that is used in the modeling of many types of AC machines is the sinusoidal assumption. Essentially the assumption is that the windings in the machine are arranged so that the resultant mmf has a spatially sinusoidal distribution. A normal AC machine usually has three windings spaced at 120◦ electrical, each producing a spatially sinusoidal mmf when fed with a current. An amazing property of this arrangement is that if it is fed with three temporal sinusoidal currents, separated temporally by 120◦ , then the resultant mmf is a spatially moving sine wave around the machine (this will be shown mathematically in later sections in this Chapter). Why is this assumption so important? From a modeling point of view the sinusoidal functions have a rich set of mathematical properties which make the modeling of machines analytically tractable. One of the key properties of sinusoidal functions is their connection with vectors, and the consequent ability to take orthogonal components of them. In reality the mmf produced by real windings are not pure sinusoids. Most windings for real machines are confined to slots in the stator. This leads to an

B-2

Introduction to Space Vectors mmf that has step changes in it, and consequent higher order spatial harmonics. However, the winding configuration is designed to minimize these harmonics. As we shall see below, the significance of these winding harmonics on the performance of the machine also depends on the harmonics in the flux waveforms that interact with the windings. The sinusoidal assumption is not only applied to the mmf produced by the windings, but it is also applied to the resultant fluxes produced by the action of the mmf on the iron circuit of the machine. In the case of the SYNCREL the iron circuit reluctance varies in a complex fashion due to the rotor saliency. This means that the flux density produced by the mmf is in general not spatially sinusoidal. However, the harmonics in these waveforms are usually neglected, and only the fundamental component is considered from an analysis point of view. This may seem to be a gross approximation, but models developed using this approach have been shown to give reasonable representations of the behaviour of real machines. In the remainder of this section we shall look at some of the properties of a sinusoidally distributed winding. Specifically, the characteristics of a nonsinusoidal flux density interacting with a sinusoidal winding shall be considered. This is of particular relevance to the SYNCREL and other salient pole machines as their flux density distributions in general are not sinusoidal. The remainder of this section discusses the foundations of the sinusoidal assumption, and why it can be used successfully to simplify the modeling of machines, with special emphasis on the SYNCREL. Specific issues addressed are: • Consideration of some of the general properties of sinusoidally distributed windings (e.g. only link with fields of the same pole number). • Detailed analysis of the variation of inductance with rotor position for a two pole axially laminated rotor would be beneficial.

B.2.1

Winding Interaction with Spatial Flux Density Distribution

In this sub-section we shall consider the interaction of a spatially non-sinusoidal flux density distribution with an ideal sinusoidal winding. Such an ideal winding will produce a temporal sinusoidally varying current density around the machine. The following equation can be written for the conductor density as a function of the angle θp around the periphery of the machine: n(θp ) = na sin θp

(B.1)

This waveform has an amplitude of na conductors, and goes positive and negative. How can one have positive and negative numbers of conductors? The sign convention is based on the direction of the current in the conductor. The positive part of this conductor distribution carry currents in one direction, and the negative part carry the return currents [7]. Given this winding distribution, the mmf spatial distribution readily follows. If the a-phase is carrying ia amps, then the mmf can be calculated by implementing Ampere’s Law. This is achieved by carrying out a closed path integral

B.2 The Sinusoidal Assumption

B-3

Figure B.1: MMF calculation integration path. over the full coil span (see Figure B.1 for the path of integration): Z θp +π FaT (θp ) = na ia sin θp dθp θp

= 2na ia cos θp = 2Fˆa cos θp ∴ Fa (θp ) = Fˆa cos θp where Fˆa = na ia

(B.2)

The ‘2’ factor in the front of the right hand side of the above expression is there because the total mmf is expended across two air gaps, and the Fa (θp ) expression represents the mmf expended per air gap. The total number of coils in the winding is simply the sum of the number of coils at each θp position. Due to the continuous nature of the proposed distribution this sum becomes an integral: Z π Na = na sin θp dθp 0

= 2na

(B.3)

Therefore the peak mmf for the winding may be written as: Na i a Fˆa = 2 Now let us consider some general flux density waveform that varies in the following way spatially with respect to θp around the machine, and also has a

B-4

Introduction to Space Vectors time varying spatial phase angle δ(t): ˆn sin n(θp − δ(t)) B(θp ) = B

(B.4)

This flux waveform is a non-sinusoidal waveform as it contains a number of harmonics denoted by the integer value of n. Furthermore assume that the winding is on a machine with the following physical dimensions: l , the length of the machine. vB , the linear velocity of the B field. r , the radius of the stator of the machine. Therefore the B(θp ) field phase is changing in the following fashion: δ(t) =

vB t r

(B.5)

This expression implies that the B(θp ) field is spatially moving with respect to time. From basic physics we can say the following – the voltage induced in a length of conductor l, moving with a velocity of vB perpendicular to a magnetic flux density of B is: e = BlvB (B.6) In the case of a sinusoidally distributed coil the length of conductor for one side of the coil at some position θp is: lT = na l sin θp

(B.7)

therefore the induced voltage in the conductors at this angular position is: e(θp ) = BvB na l sin θp

(B.8)

The flux density at this position at a particular instant of time can be determined from (B.4), and consequently (B.8) becomes: ˆn sin θp sin n(θp − δ(t)) e(θp ) = vB na lB

(B.9)

ˆn . In order to calTo simplify the following manipulations let Kn , vB na lB culate the total voltage produced by these conductors we have to add up the contributions of all the conductors in the coil. This involves integrating the voltage at each position θp for the circumference of the machine. Therefore assuming a single pole pair machine we have: Z 2π vB t eT = Kn sin θp sin n(θp − )dθp (B.10) r 0 Using the trigonometric relation sin x sin y = 1/2[sin(x + y) + sin(x − y)] one can write:      Z 2π Kn nvB t nvB t eT = sin (n + 1)θp − + sin (n − 1)θp − dθp 2 r r 0 (B.11)

B.2 The Sinusoidal Assumption

B-5

For the specific case of n = 1 (i.e. only the fundamental harmonic present) then (B.11) can be integrated and becomes:   vB t eT = K1 π sin r = K1 π sin(ωB t)

(B.12)

i.e. the voltage induced by the winding is a temporal sinusoidal voltage (as expected). Now consider what happens to the higher order harmonics in the flux density waveform. If we carry out the integration of (B.11) for the case of n > 1 we have:      nvB t cos nvB t Kn − cos 2π(n + 1) − − 2π(n − 1) − eT = 2 n+1 r n−1 r     1 1 −nvB t + + cos (B.13) n+1 n−1 r If we consider the various terms in (B.13) using the trigonometric relation: cos(x − y) = cos x cos y + sin x sin y

(B.14)

we get the following:   nvB t 1 h cos nvB t 2π(n + 1) − =− − cos 2π(n + 1) cos n+1 r n+1 r nvB t i + sin 2π(n + 1) sin r nvB t 1 cos (B.15) =− n+1 r and similarly: cos − n−1

  nvB t nvB t 1 2π(n − 1) − =− cos r n−1 r

(B.16)

Therefore (B.13) can be written as:       Kn 1 1 1 1 nvB t −nvB t eT = + + + − cos cos 2 n+1 n−1 r n+1 n−1 r = 0; ∀ n > 1

(B.17)

Remark B.1 The implications of the above expression are that the higher order harmonics in the flux density spatial waveform do not link to the sinusoidally distributed winding. In other words the pole number of the flux density waveform has to be the same as that of the winding. This is a very important property of sinusoidal windings. One can then consider the flux density harmonics to be contributing to the leakage flux. Remark B.2 Real machine windings are not exactly sinusoidally distributed as in the ideal case above. Therefore there are spatial harmonics in the winding distribution itself. Consequently it is possible for higher order harmonics in the

B-6

Introduction to Space Vectors

Figure B.2: Dimensions of a single coil.

flux density waveform to link with same pole number harmonic in the winding distribution, resulting in a harmonic voltage. For example, most winding configurations contain a significant third harmonic spatial component, therefore the third harmonic in the flux density waveform (introduced by saturation effects) can link with the individual windings. Consequently third harmonic voltages can be seen in the phase voltages.

B.2.2

Winding Interaction with Temporal Flux Density Variation

In this section we consider a non-sinusoidal, spatially stationary flux density distribution which has a sinusoidal temporal variation, interacting with a sinusoidal winding distribution. For the sake of the following argument consider the flux density to have the following form: ˆn cos nθp B(θp ) = B

(B.18)

Let us firstly consider the n = 1 case. Consider a single coil which has the dimensions shown in Figure B.2. One can calculate the flux linking a coil at any position using the general expression: I φ=

B.dS

(B.19)

Consider the situation where there is only the fundamental flux density distribution. The above surface integral can be written as follows (using Figure B.2)

B.2 The Sinusoidal Assumption

B-7

for the flux at angle coil position θp 1 : Z

ˆ1 r φ(θp ) = B

θp +π

l

Z

cos θ dl dθ 0

θp

Z

ˆ1 r =B

θp +π

l cos θ dθ θp

ˆ1 rl sin θp = −2B

(B.20)

The dot product is eliminated in this situation as the flux density is perpendicular to the integration surface. In order to get the voltage induced in the coils at a particular position around the machine the following calculation has to be carried out: dφ(θp ) dt  d  ˆ1 rl sin θp −2B = na sin θp dt 2na rlB1 sin2 θp =− cos ωt ω

e(θp ) = n(θp )

(B.21)

(B.22)

Remark B.3 Equation (B.22) is obtained by realising that we are dealing with a sinusoidal temporal variation of a sinusoidal spatial distribution. Therefore the amplitude of the flux density is varying with respect to time in a sinusoidal manner. Therefore: ˆ1 = B1 sin ωt B (B.23) where ω is the frequency of the temporal variation. It is important to realise that the θp angle in (B.22) is constant with respect to time in this case. To find the total voltage for the whole winding the individual contributions for the number of turns at each position θp have to be added: Z π eT = e(θp ) dθp 0 Z −2na rlB1 cos ωt π 2 = sin θp dθp ω 0 −na rlB1 π = cos ωt (B.24) ω i.e. a temporal sinusoidal voltage is produced from the winding as one would expect. The more interesting case is when the flux density spatial distribution is non-sinusoidal as in (B.18). In this case the flux for a single coil is: Z

θp +π

Z

φ(θp )n = Bn r

cos nθ dl dθ θp

= 1 Note

coil.

l

0

Bn rl [sin n(θp + π) − sin nθp ] n

(B.25)

that the θp in the following expression is the angle of the most clockwise side of the

B-8

Introduction to Space Vectors Clearly φ(θp )n = 0 for n even. Therefore the even harmonics do not link to a single coil. For the n odd case it can be seen that the expression for the flux becomes: φ(θp )n =

−2Bn rl sin nθp n

(B.26)

To calculate the voltage in a single coil at some position θp we again apply (B.21). Carrying out the differentiation on (B.26) we get: e(θp )n =

−2na Bn rl sin θp sin nθp cos ωt nω

:n is odd

(B.27)

To get the total voltage due to the winding the individual contributions are integrated as in the previous case: Z −2na Bn rl cos ωt π sin θp sin nθp dθp (B.28) eT = nω 0 Rπ It can be shown that 0 sin θp sin nθp dθp = 0, therefore the total voltage due to the odd harmonics is zero. Therefore, as with the spatially moving flux density case, only the component of the flux density that has the same pole number as the winding links with the winding, even if the harmonics are space stationary and have a time varying amplitude. Remark B.4 The main implications of the above analysis is that the flux density component with the same pole number as the winding links with the winding. Therefore, for a pure sinusoidally distributed winding, the harmonics in the flux density only contribute to the leakage flux, and do not have a role in determining the performance of the machine. However, in reality a pure sinusoidal winding cannot be produced, and there are spatial harmonics in the winding distribution. Therefore, harmonics in the flux density waveform can link with similar pole number harmonics in the winding distribution resulting in higher order voltage harmonics being produced in the winding. These harmonics will also have an influence on machine performance.

B.3

dq Models

Most electrical machines with sinusoidally distributed windings are modeled mathematically using a technique called dq modeling. We actually used a restricted form of dq modeling in Section C.1, where the dq axes were strongly associated with the different permeance axes of the rotor. It is not the purpose of this chapter to give an exhaustive derivation of dq modeling of machines, as this has been done in many machines text books. However, an overview of the principles of dq modeling will be presented, and then the dq model for the SYNCREL will be derived. The fundamental assumption used as the basis of dq modeling is that the winding distribution in a machine is sinusoidal. In addition a number of other secondary assumptions are made, which are similar to the assumptions used in Section C.1, namely: a. The machine does not exhibit stator or rotor slotting effects.

B.3 dq Models

B-9

120

Figure B.3: Three phase to two phase transformation.

b. The machine iron is linear material, i.e. there is no saturation effects. The combined effect of these assumptions is that traditional linear circuit analysis techniques can be used to analyse the electrical circuit of a machine. The sinusoidal assumption means that various spatial quantities in the machine can be broken into orthogonal components. It is this that is used to carry out coordinate transformations from the three phase axes of a machine to the two phase dq axes.

B.3.1

Stationary Frame Transformations

The general idea of a dq type of transformation can be obtained by considering the transformation of the three phase currents to their two phase equivalents. Consider Figure B.3. This shows a conceptual diagram of a three phase machine. The windings represented by the concentrated coils are actually spatially sinusoidal distributed windings similar to that shown in Figure B.1. The lines through the centre of the coils are the axes of the associated winding mmfs, and therefore can be thought of as a vector that represents the sinusoidal quantities.

B.3.1.1

MMF transformations

Given that the space distribution of the mmfs for windings a, b and c can be modeled similarly to (B.2) then the following expressions can be written for the mmfs: Fa = Fˆa cos θp   2π Fb = Fˆb cos θp − 3   2π Fc = Fˆc cos θp + 3

(B.29) (B.30) (B.31)

B-10

Introduction to Space Vectors where θp is defined in Figure B.3. The resultant mmf distribution for the three phase machine is:     2π 2π ˆ ˆ ˆ FT = Fa cos θp + Fb cos θp − + Fc cos θp + (B.32) 3 3 Assuming that the three phase windings have identical turns, and they are being driven by three phase currents of the form: ia = Ipk cos ωt   2π ib = Ipk cos ωt − 3   2π ic = Ipk cos ωt + 3

(B.33) (B.34) (B.35)

then (B.32) can be written as:     h 2π 2π FT = N Ipk cos ωt cos θp + cos ωt − cos θp − 3 3    i 2π 2π + cos ωt + cos θp + 3 3 3 (B.36) = N Ipk cos(ωt − θp ) 2 i.e. the resultant mmf has a spatial sinusoidal distribution which is rotating around the machine at ωt electrical radians per second. Remark B.5 Note that this total mmf is expended across two air gaps. Therefore the mmf per air gap is half the value in FT . If the vectors associated with (B.29), (B.30) and (B.31) are resolved along two orthogonal axes called the dq axes then the following expressions can be written for the resultant dq axes mmfs: Fsdq = TFabc  s   1 1 − Fd √2 = i.e. s 3 Fq 0 2

(B.37) −√12 − 23







Fa  Fb  Fc

(B.38)

It can be shown that Fds + Fqs gives the same resultant mmf distribution around the machine as the original three phase machine. In other words that transformation has converted the three phase into an equivalent two phase machine with the same mmf distribution. Addition Add the proof that the DQ axes calculations give the same resultant mmf. In order to make this transformation invertible the T matrix and Fsdq vector are augmented as follows:      1 −√21 1 − Fds Fa √2  3  Fqs  =  − 23   Fb  (B.39)  0 2 1 1 1 s √ √ √ F Fγ c 2 2 2 i.e. Fsdqγ = SFabc −1

and Fabc = S

Fsdqγ

(B.40) (B.41)

B.3 dq Models

B-11

where:   S−1 = 

 =

i.e. S−1 =

√

2 3 − 31 − 31

0 √1 3 − √13

1

2 1  −2 3 − 12

0

√

3 2√ − 23

2 √3 2 √3 2 3

  

√1 2 √1 2 √1 2

2 T S 3

   (B.42)

√ The choice of the 1/ 2 augmentation of T was made so that the property in (B.42) was obtained. Note that the F γ term is zero if the three phase mmfs contain no zero sequence components, else this term is not zero. Therefore, for a star connected machine with an isolated neutral F γ always equals zero, since one cannot have zero sequence currents with this configuration. B.3.1.2

Current Transformations

Given the mmf transformation in the previous section, it is a simple matter to construct the transformation for the three phase currents to their equivalent two phase currents. This transformation can be handled in two sensible ways. The transformation could be carried out in such a way that the transformed machine produces the same total power as the original three phase machine. Such transformations are called power invariant transformations. Another transformation can be implemented such that the transformed machine produces 2/3rds the power of the three phase machine. This is one particular example of a power variant transformation. Usually the power variant transformation is used, since it turns out that in steady state the two phase currents and voltages have exactly the same amplitude as the phase voltages and currents of the three phase machine. If the magnitude of the two phase quantity is taken, and then projected onto the relevant three phase axis, then the instantaneous phase value can be found. This transformation is commonly used in the machine modeling literature because of this property. Consider the situation where the two phase machine has 2/3rds the resultant mmf compared to the three phase machine. It can be shown that this means that the right hand side of (B.40) has to be multiplied by 2/3. Therefore (B.40) and (B.41) can be written as: 2 SFabc 3 3 = S−1 Fsdqγ = ST Fsdqγ 2

Fsdqy =

(B.43)

Fabc

(B.44)

Now consider the mmf expressions expressed in terms of currents and winding turns: Fsdqγ = N2φ isdqγ

(B.45)

Fabc = N3φ iabc

(B.46)

B-12

Introduction to Space Vectors Using (B.43) one can write: N2φ isdqγ =

2 SN3φ iabc 3

(B.47)

where: N2φ , the number of turns for a winding of the two phase dqγ machine. N3φ , the number of turns for each winding of the three phase machine. Since the two phase dqγ machine is an artificial machine of our creation, we are free to choose the number of turns for each of the windings. Clearly if N2φ = N3φ , i.e. the two phase machine has the same number of turns on its windings as the three phase machine, and the is relationship has the same form as the mmf relationship. Consequently the isdqγ vector has 2/3rds the magnitude of the iabc resultant current vector. Therefore the current relationships between the two machines is: 2 (B.48) isdqγ = Siabc 3 T s iabc = S idqγ (B.49) B.3.1.3

Voltage Transformations

Similarly, one can derive the relationship between the three phase and two phase voltages. Consider the power relationships for the two machines: T P3φ = vabc iabc

P2φ =

sT vdqγ idqγ

(B.50) (B.51)

We want P2φ = 2/3P3φ . Therefore substituting (B.50) and (B.51) into this expression and using (B.48) one can obtain: 2 Svabc 3 s = ST vdqγ

s vdqγ =

(B.52)

vabc

(B.53)

Notice that this expression is in the same form as that for the current. Therefore it has the same property that the magnitude of the voltage vector is 2/3rds that of the voltage vector for the three phase machine. If one considers the case where the windings are excited by three phase currents of the form in (B.33), (B.34) and (B.35), then it is easy to show that: s idqγ = Ipk (B.54) i.e. the magnitude of the resultant dqγ vector is equal to the peak current in a phase in steady state. Similarly we can write: s vdqγ = Vpk (B.55) where Vpk , the peak of three phase sinusoidal voltages supplying the abc windings. Therefore the use of the 2/3rds power relationship has allowed one to easily correlate the dqγ voltages and currents to their abc counterparts.

B.3 dq Models B.3.1.4

B-13

Impedance Transformations

Next we need to consider the transformation of the machine parameters between the three phase and two phase machines. Consider the following general expressions for the two machines: vabc = Zabc iabc

(B.56)

s vdqγ

(B.57)

=

Zsdqγ isdqγ

Using (B.56) together with (B.49) and (B.53) one can write: 2 SZabc ST isdqγ 3

s vdqγ =

(B.58)

Comparing this expression with (B.57) one can see that: 2 SZabc ST 3 2 = ST Zsdqγ S 3

Zsdqγ = and Zabc

(B.59) (B.60)

These general impedance transformations can be used to generate specific transformations for the inductances and resistances for a three phase winding. For a three phase winding the impedance matrix can be written as: 

Zabc

Ra + Laa p Lba p = Lca p

Lab p Rb + Lbb p Lcb p

 Lac p  Lbc p Rc + Lcc p

(B.61)

where p , d/dt. By inspection it can be seen that the resistive and inductive transformations become: 2 SRabc ST 3 2 = ST Rsdqγ S 3 2 = SLabc ST 3 2 = ST Lsdqγ S 3

Rsdqγ =

(B.62)

Rabc

(B.63)

Lsdqγ Labc where: 

Rabc

Labc

 Ra 0 0 =  0 Rb 0  0 0 Rc   Laa Lab Lac =  Lba Lbb Lbc  Lca Lcb Lcc

(B.64) (B.65)

B-14

Introduction to Space Vectors To dqγ s Fsdqγ = 32 SFabc isdqγ = 32 Siabc s vdqγ = 23 Svabc s Ψdqγ = 32 SΨabc Lsdqγ = 23 SLabc ST Rsdqγ = 23 SRabc ST Zsdqγ = 23 SZabc ST

To abc Fabc = ST Fsdqγ iabc = ST isdqγ s vabc = ST vdqγ T Ψabc = S Ψsdqγ Labc = 23 ST Lsdqγ S Rabc = 23 ST Rsdqγ S Zabc = 23 ST Zsdqγ S

Table B.1: Summary of Stationary Frame Transformations B.3.1.5

Flux Linkage Transformations

Now that we have the inductance and current transformations it is possible to develop the transformations for the flux linkages. The flux linkage expressions for the three and two phase machines are: Ψabc = Labc iabc

(B.66)

Ψsdqγ

(B.67)

=

Lsdqγ isdqγ

If (B.64) and (B.48) are substituted into (B.67) then one gets: 2 2 SLabc ST Siabc 3 3 2 = SLabc iabc 3 2 = SΨabc 3 = ST Ψsdqγ

Ψsdqγ =

∴ Ψsdqγ and Ψabc

(B.68) (B.69)

The stationary frame transformations are summarized in Table B.1.

B.3.2

Rotating Frame Transformations

The transformation in (B.40) allows the three phase windings to be represented by an equivalent set of two phase windings. These winding are stationary with respect to the original three phase winding. It is then possible to project the stationary two phase windings onto two phase windings that are at some angle to the stationary winding axes and moving with respect to these axes. The following discussion is with respect to Figure B.4. This diagram shows a rotating dq axes with respect to the stationary dq axes derived in the previous section. The angle θsr is defined with reference to the rotating axis as this makes it easier to see the projections of the stationary quantities onto this axis. Using the normal convention for angle sign (anti-clockwise is positive angle), one can write the following expressions: Fdr1 = Fds cos θsr

(B.70)

Fdr2

(B.71)

Fqr1 Fqr2

π = Fqs cos(θsr + ) = −Fqs sin θsr 2 = Fqs cos θsr =

Fds

sin θsr

(B.72) (B.73)

B.3 dq Models

B-15

Clearly the total mmf on each of the rotating axes is: Fdr = Fdr1 + Fdr2 = Fds cos θsr − Fqs sin θsr Fqr

= =

Fqr1 + Fqr2 Fqs cos θsr

(B.74)

+ Fds sin θsr

(B.75)

This expression can be written more succinctly in matrix form: 

Fdr Fqr





cos θsr sin θsr

=

− sin θsr cos θsr



Fds Fqs

 (B.76)

The zero sequence component can be included by ensuring that it makes no contribution to the projected vectors as follows:   Fdr  Fqr  =  Fγr  s   Fd and  Fqs  =  Fγs 

cos θsr sin θsr 0 cos θsr − sin θsr 0

− sin θsr cos θsr 0 sin θsr cos θsr 0

 0 0  1  0 0  1

 Fds Fqs  Fγs  Fdr Fqr  Fγr

(B.77)

(B.78)

To make the θ definition consistent with the angle definition used to define the inductance expressions, use θsr = −θrs . Therefore the above can be written as:   Fdr  Fqr  =  Fγr  s   Fd and  Fqs  =  Fγs 

cos θrs − sin θrs 0 cos θrs sin θrs 0

sin θrs cos θrs 0 − sin θrs cos θrs 0

 0 0  1  0 0  1

 Fds Fqs  Fγs  Fdr Fqr  Fγr

(B.79)

(B.80)

These relationships can be written in short form as: Frdqγ = BFsdqγ

(B.81)

Fsdqγ = BT Frdqγ

(B.82)

The stationary to rotating frame transformation can be combined with the three phase to stationary two phase transformation to give the transformation from a three phase stationary frame to an arbitrary rotating frame. Clearly the transformations for the mmf are (using (B.43) and (B.44)): 2 CFabc 3 = CT Frdqγ

Frdqγ =

(B.83)

Fabc

(B.84)

B-16

Introduction to Space Vectors

Figure B.4: Two phase stationary to two phase rotating transformations. where: cos θrs C = BS =  − sin θrs 

√1 2

 cos(θrs + 2π cos(θrs − 2π 3 ) 3 ) 2π  − sin(θrs − 2π 3 ) − sin(θrs + 3 ) √1 2

√1 2



cos θrs − sin θrs  cos(θ − 2π ) − sin(θ − 2π ) T T T C =S B = rs rs 3 3 2π ) − sin(θ cos(θrs + 2π rs + 3 ) 3

√1 2 √1 2 √1 2

(B.85)

  

(B.86)

It can be shown that all the transformations from the abc frame to the dqγ r frame have the same form as the stationary frame transformations of Table B.1, except that C and CT are substituted for S and ST respectively, and the superscript on the variables becomes r . From Faraday’s law it is possible to express the voltages in terms of rate of change of flux linkage. In the case of the rotating transformations, this rate of change can be from two causes; (a) the time rate of change of flux linkage caused by the time rate of change of currents, and (b) the rate of change due to the relative movement of the frames. The general Faraday relationship is: vabc = pΨabc and Ψabc = therefore vabc =

T

C Ψrdqγ pCT Ψrdqγ

(B.87) (B.88) (B.89)

As can be seen from (B.85), the C matrix is a time dependent matrix, since θrs is changing with respect to time. Therefore expanding (B.89) using the

B.3 dq Models

B-17 To dqγ r Frdqγ = 23 CFabc irdqγ = 23 Ciabc r vdqγ = 23 Cvabc r Ψdqγ = 23 CΨabc Lrdqγ = 23 CLabc CT Rrdqγ = 23 CRabc CT Zrdqγ = 23 CZabc CT

To abc Fabc = CT Frdqγ iabc = CT irdqγ r vabc = CT vdqγ T Ψabc = C Ψrdqγ Labc = 32 CT Lrdqγ C Rabc = 32 CT Rrdqγ C Zabc = 23 CT Zrdqγ C

Table B.2: Summary of Rotating Frame Transformations chain rule one gets: vabc = {pCT }Ψrdqγ + CT {pΨrdqγ }

(B.90)

If one expands (B.90) by taking the appropriate derivatives, and then rearranges the result the following expression can be obtained:   r    ψd −ψqr   r vabc = CT p  ψqr  + ωrs  ψdr  = CT vdqγ (B.91)   r ψγ 0    r  ψd −ψqr r (B.92) ∴ vdqγ = p  ψqr  + ωrs  ψdr  ψγr 0 As we shall see in the next section, (B.92) is the form of the reluctance machine dq equations. A summary of the transformations from a stationary frame to a rotating frame appear in Table B.2.

B.3.3

Example – SYNCREL Linear dq Model

Using the transformations and inductance expressions from the previous sections we are now in the position to form a linear dq model for the three phase SYNCREL. The transformation process will be carried out in a two stage process. The first step in process is to convert the three phase model of the machine to the two phase stationary frame model of the machine. Then this model is converted to a two phase rotating model. The reason for this doing this two stage process is to expose the nature of the two phase stationary frame machine, whereas if a direct transformation to the rotating frame is carried out then this model is stepped over. The following discussion is with reference to Figure B.5. This diagram shows a three phase, two pole SYNCREL. The stationary dq frame is aligned with the d-axis along the a-phase mmf axis. The rotating d-axis is located along the high permeance axis of the rotor. Because the SYNCREL is a synchronous machine, the rotor has to be synchronized with the rotating field in steady state. Hence this frame is also synchronized with this field, and is known as a synchronously rotating reference frame. In this frame it will be seen that the angle dependence of the inductances disappears, and the currents and voltages are D.C. values in steady state.

B-18

Introduction to Space Vectors

Figure B.5: Conceptual diagram of a three phase SYNCREL. The most complicated part of the three phase machine to two phase machine conversion is the inductance transformation, so we shall look at this in detail. The inductances for this model were calculated in Section C.1 and appear in (C.56) and (C.57). These inductance expressions have to be transformed using the transformations in Table B.1. The inductance matrix in the stationary frame becomes:  2  L2 sin 2θpd 0 3 Ll + L1 + L2 cos 2θpd 3 2 0  (B.93) L2 sin 2θpd Lsdqγ =  3 Ll + L1 − L2 cos 2θpd 2 2 0 0 3 Ll Equation (B.93) can now be converted to the rotating frame by carrying out the BLsdqγ BT transformation using the fact that θrs = θpd (i.e. the reference frame d-axis is aligned with the high permeance axis of the rotor). After considerable manipulation one arrives at the following expression for the dq inductance matrix:   0 0 Ll + 23 (L1 + L2 ) 0 Ll + 32 (L1 − L2 ) 0  (B.94) Lrdqγ =  0 0 Ll If one assumes that the system has not zero sequence currents flowing (i.e. the machine has star connected windings with an open circuit neutral) then the last column and row can be deleted from the above matrices. Therefore the relevant matrix for the dq inductances is:   0 Ll + 32 (L1 + L2 ) r Ldq = (B.95) 0 Ll + 32 (L1 − L2 )

B.3 dq Models

B-19

Notice in (B.95) that the θpd dependent inductance values of the original three phase model have been converted to time invariant and θpd independent inductances in the dq frame. This results from the fact that the dq reference frame is tied to the rotor. If one were measuring the inductance whilst fixed to the rotor, the inductance will not change as the rotor is rotated (assuming a non-salient stator). In addition, the transformed windings that are fixed to this frame do not see any movement of the rotor from the moving d-axis, and therefore the mutual inductance term to the orthogonal winding is zero. A consequence of this simplification of the inductances is that the dq frame dynamic equations are much simpler than the three phase equations. In (B.92) we calculated the generic form of the dq dynamic equations taking into account only the voltage terms due to the flux linkages. If the three phase conversion process is carried out for the resistance it can be shown that the dq values are identical to the three phase values. Therefore, the generic dq equation can be rewritten in the following form if we include the resistive drop term and use the fact that the dq inductances are time invariant:    r    Ld −Lrq R r r r vdq = idq + pidq + ωpd irqd (B.96) Lrq R Lrd which can be written in scalar form as: dird dt dir Lrq dtq

vdr = Rird + Lrd

− ωpd Lrq irq

vqr = Rirq +

+ ωpd Lrd ird

) (B.97)

where: 3 Lrd = Ll + (L1 + L2 ) 2 3 r Lq = Ll + (L1 − L2 ) 2 Equation (B.97) is shown in diagram form in Figure B.6. It should be noted that the magnitude of the total flux linkage for the SYNCREL can be written in terms of the d and q-axis inductances as follows: q ψ = (Lrd ird )2 + (Lrq irq )2 (B.98) The expression for the torque in a doubly excited system can be shown to be [28]: dLsdq 1 2 dLsq 1 2 dLsd Te = isd + isq + isd isq (B.99) 2 dθpd 2 dθpd dθpd where the inductance terms are defined as in (B.93). Note that Lsdq is the mutual inductance between the d and q windings. Taking the derivatives in this expression, and introducing the 3/2 factor to account for three phases, we get the following expression for the torque in terms of the stationary frame dq currents: i 2 3 h s2 Te = (iq − isd )L2 sin 2θpd + 2L2 isd isq cos 2θpd (B.100) 2 Using the relationship: isdqγ = BT irdqγ (B.101)

B-20

Introduction to Space Vectors r r pd Lq iq

R

-

+

idr Lrd

vdr

d-axis

r r pd Ld id

R

+

-

iqr Lrq

vqr

q-axis

Figure B.6: Ideal dq equations.

one can substitute for isd and isq in (B.100) in terms of ird and irq , and obtain: 3 2L2 ird irq 2 = (Lrd − Lrq )ird irq

Te =

(B.102)

All of the analysis thus far has been for a two phase single pole pair machine. A three phase multiple pole machine only requires a slight modification to the torque expression, with the previously derived torque expression being multiplied by the pole pairs of the machine and 3/2: Te =

3 pp (Lrd − Lrq )ird irq 2

(B.103)

The only other transformation of immediate interest that has not been explicitly carried out is the current transformation. It was eluded to in Section B.3.1.3 that one property of the rotating transformations was that the magnitude of the current and voltage vectors was equal to that of a single phase of the three phase machine in steady state. Another property that occurs is that in steady state ird and irq have D.C. values if the dq-axes are rotating synchronously with the rotor. To formally show these properties consider the abc machine to be driven by currents of the form in (B.132–B.134). These currents are synchronized to the rotation of the rotor, and consequently so is the resultant current vector. Carrying out the transformation from the abc frame to the

B.4 Space Vector Model

B-21

dq stationary frame we get: 

isdqγ

 Ipk cos(θpd + γ) =  Ipk sin(θpd + γ)  0

(B.104)

and the further transformation to the dq rotating frame gives: 

irdqγ

 Ipk cos γ =  Ipk sin γ  0

(B.105)

Notice that if the phase angle γ is zero then the q-axis current is zero, and all the current lies in the d-axis–i.e. along the high permeance axis of the rotor. If the peak value of the abc currents is constant, then in the dq-axes we have a constant amplitude D.C. value equal to the abc phase amplitude.

B.4

Space Vector Model

An alternative method for modeling machines that has become popular is the space vector technique. This method of modeling is very similar to the dq modeling technique, and in fact it is very simple to convert between the two different types of models. This technique has become popular because of the growth in vector based control techniques and the fact that machine equations take a simpler form due to its notation. For example, the electrical dynamics of an induction machine can represented by two equations (instead of four with a dq model). The form of the equations also evokes a “resultant vector” way of thinking about the machine’s operation, as opposed to a component vector approach with the dq modeling technique. A full discussion of space vectors applied to the control of machines can be found in [14]. The application of space vectors to reluctance machines has not been as pervasive as it has with induction machines because the reluctance machine more naturally relates to a component viewpoint due to the presence of two different permeance axes. However, in some situations space vectors are a useful tool for viewing the machines operation. It should be emphasized that because the reluctance machine does not have any rotor winding we have no need to develop rotor expressions, as is the case with the induction machine. Space vector modeling is based on the concept that the mmf of a three phase machine can be represented by a resultant vector that has a physical location in space. This stems from the fact that the individual windings of the phases are sinusoidally distributed, and the vector for each of the windings can be considered to lie on the axis of the phases. It should be noted that the dq modeling developed in the previous sections used similar assumptions, but the modeling approach was different.

B-22

Introduction to Space Vectors

B.4.1

Current Space Vectors

B.4.1.1

Stationary Frame Current Vectors

In a manner similar to (B.32) we can write the following expression for the resultant mmf in a three phase machine: FTs = N3φ [ia (t)cosθp + ib (t)cos(θp −

4π 2π ) + ic (t)cos(θp − )] 3 3

(B.106)

where θp is the angle from the axis of the a-phase winding as defined previously. The notational simplicity of the space vector formulation is obtained by introducing complex notation. In the following equations the “ _ ” is used to denote vectors in the complex form. Equation (B.106) can be written as: FTs = N3φ Re[ia (t)e−jθp + ib (t)ej(2π/3−θp ) + ic (t)ej(4π/3−θp ) ] 2 3 = N3φ Re[ia (t) + aib (t) + a2 ic (t)]e−jθp 2 3

(B.107)

where a = ej2π/3 , and is a vector of unit length lying spatially along the axis of the b-phase. Similarly a2 = ej4π/3 , and lies along the c-phase axis. Notice that this complex notation implicitly means that we have a set of pseudo “dq” axes, which now correspond to the real and imaginary axes. If (B.107) is broken apart and the current section extracted, and then the real and complex components are collected together we can write: 2 [ia (t) + aib (t) + a2 ic (t)] 3 = |is | ejαs

is =

(B.108)

Figure B.7 shows pictorially what this expression means. The |is | vector is the magnitude of the resultant current vector. Notice that the direction of this vector is spatially the same direction as the original mmf vector (since mmf and current are related by a scalar). The αs angle is the angle of this vector with respect to the reference a-phase axis. If one were to add together the ia , ib , and ic current vectors graphically on this diagram, the resultant current vector would have the angle αs but be 3/2 times the magnitude. The 2/3rd term was introduced into (B.107), and then carried into (B.108), since the resultant current vector has the property that the vector can be directly projected back onto the three phase axes. It should be noted that implicit in this projection is that there are not zero sequence currents flowing (i.e. ia + ib + ic = 0). It can also be shown that under this restriction these projections can be represented by the following relationships: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> INPUTS : i n t e g r a t o r G a i n −− t h e g a i n o f t h e i n t e g r a t o r . This v a l u e has t o be t h e d i g i t a l gain value . i n t e g I n i t V a l u e −− t h e

initial

value of the integrator ( Default = 0.0)

i n t e g L i m i t s −− a t u p l e c o n t a i n i n g t h e ( l o w e r l i m i t , upper l i m i t ) o f t h e i n t e g r a t o r . ( d e f a u l t i s ( 0 . 0 , 0 . 0 ) which i s i n t e r p r e t e d as u n l i m i t e d ) . wrapping −− True means t h a t t h e i n t e g r a l v a l u e w i l l be wrapped t o t h a t t h e v a l u e l i e s between \pm \ pi , F a l s e means t h a t no wrapping o c c u r s . This i s a p p l i e d b e f o r e t h e i n t e g r a t o r l i m i t s . DEFAULT: F a l s e >>> Initialisation : kpGain −− Kp p r o p o r t i o n a l g a i n kiGain −− Ki i n t e g r a l g a i n −− t h e i n i t I n t e g V a l u e −− i n i t i a l

d i g i t a l gain value .

integrator value ( default

set to 0.0)

i n t e g L i m i t s −− a t u p l e c o n t a i n i n g t h e ( n e g a t i v e l i m i t , p o s i t i v e l i m i t ) o f t h e i n t e g r a t o r . ( d e f a u l t i s ( 0 . 0 , 0 . 0 ) which i s i n t e r p r e t e d as u n l i m i t e d . Returns : ( piOutput , i P a r t , l i m i t R e a c h e d ) −− Tuple c o n t a i n i n g t h e o u t p u t o f t h e a d d i t i o n o f t h e P and I p a r t s , t h e i n t e g r a l o u t p u t p a r t , and a b o o l e a n i n d i c a t i n g i f t h e i n t e g r a t o r l i m i t has been r e a c h e d . >> Initialisation :

0.0))

:

G-6

Python Listing for Two Phase PLL

( r e c u r s i v e C o e f f , n o n r e c u r s i v e C o e f f ) −− t u p l e c o n t a i n i n g t h e r e c u r s i v e and non r e c u r s i v e c o e f f i c i e n t s . > INITIALISATION INPUTS : a m p F i l t e r C o e f f s −− ( r e c u r s i v e c o e f f i c i e n t , non−r e c u r s i v e t h e a m p l i t u d e low p a s s f i l t e r .

coefficient ) for

p h a s e F i l t e r C o e f f s −− ( r e c u r s i v e c o e f f i c i e n t , non−r e c u r s i v e f o r t h e phase f e e d b a c k low p a s s f i l t e r .

coefficient )

piGains −− ( kp gain , k i g a i n ) f o r t h e PI f e e d b a c k c o n t r o l l e r ampIntegGain −− c o n t i n u o u s time g a i n o f t h e i n t e g r a t o r u s i n g i n t h e amplitude estimation s e c t i o n of the c o n t r o l l e r . vcoCentreFreq −− c e n t r e f r e q u e n c y o f t h e VCO e x p r e s s i o n i n H e r t z . sa m pl es Pe r Ce nt re Fr e qP er io d −− number o f sa mp le s i n one c y c l e o f a waveform w i t h t h e p e r i o d c o r r e s p o n d i n g t o t h e vcoCentreFreq . p i I n t e g r a t o r L i m i t s −− ( l o w e r i n t e g r a t o r l i m i t , upper i n t e g r a t o r l i m i t ) . The l o w e r and upper l i m i t s o f t h e i n t e g r a t o r . D e f a u l t i s ( 0 . 0 , 0 . 0 ) which means t h a t t h e r e a r e no i n t e g r a t o r l i m i t s . estAmpPhase −− ( e s t i m a t e d i n i t i a l a m p l i t u d e , e s t i m a t e d i n i t i a l phase ) . t u p l e c o n t a i n i n g v a l u e s o f t h e i n i t i a l e s t i m a t e d a m p l i t u d e and phase o f t h e waveform . The d e f a u l t v a l u e i s ( 0 . 0 , 0 . 0 ) . > Class i n i t i a l i s a t i o n : f b F i l t e r C o e f f s −− t u p l e c o n t a i n i n g t h e two f e e d b a c k f i l t e r c o e f f i c i e n t s , w i t h t h e o r d e r i n t h e t u p l e b e i n g ( r e c u r s i v e c o e f f i c i e n t , non−r e c u r s i v e coefficient ). piGains −− t u p l e c o n t a i n i n g t h e two PI c o n t r o l l e r g a i n s , w i t h t h e o r d e r i n the t u p l e being ( p r o p o r t i o n a l gains , i n t e g r a l gain ) . fundamentalFreq −− t h e e s t i m a t e d FUNDAMENTAL f r e q u e n c y . Frequency i s e x p r e s s e d i n Hz . NOTE THAT THIS IS THE FUNDAMENTAL FREQUENCY, AND IF HARMONCS ARE BEING CONSIDERED THEN SEE BELOW FOR OTHER PARAMETER. samplesPerFundCycle −− t h e number o f s am p les p e r c y c l e o f t h e e s t i m a t e d fundamental f r e q u e n c y .

G-9 harmonicNumberToLockTo −− t h e harmonic o f t h e fundamental t o l o c k t o . This harmonic number i s used t o d e t e r m i n e t h e c e n t r e f r e q u e n c y o f t h e VCO. DEFAULT VALUE IS 1 ( t h e fundamental ) . Returns : t u p l e − ( e s t i m a t e d i n p u t phase ( r a d i a n s ) , f r e q u e n c y c o r r e c t i o n ( Hz ) )

PARAMETERS alphaBetaComponents −− complex number r e p r e s e n t a t i o n t h e two phase s t a t i o n a r y frame components o f a harmonic r i c h waveform . frameAngle −− a r e a l number r e p r e s e n t i n g t h e a n g l e o f t h e r o t a t i n g frame r e l a t i v e t o t h e s t a t i o n a r y frame i n r a d i a n s .

RETURNS Complex number r e p r e s e n t i n g t h e dq components o f t h e harmonic i n t h e a l p h a + j b e t a components t h a t a r e s y n c h r o n i s e d w i t h t h e r o t a t i o n o f t h e frame . """ return s e l f . dq5thHarmonic . f i l t e r e d A m p ( alphaBetaComponents , f r a m e A n g l e ) #−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− def harmonicComponent ( s e l f , alphaBetaComponents , f r a m e A n g l e ) : """ PARAMETERS alphaBetaComponents −− complex number a l p h a + ( b e t a j ) which r e p r e s e n t s t h e two phase s t a t i o n a r y frame components o f a harmonic r i c h waveform . frameAngle −− a r e a l number r e p r e s e n t i n g t h e a n g l e o f t h e r o t a t i n g frame r e l a t i v e t o t h e s t a t i o n a r y frame i n r a d i a n s .

RETURNS

G-13

Complex number r e p r e s e n t i n g dq component sample o f t h e harmonic waveform whose f r e q u e n c y c o r r e s p o n d s t o t h e r a t e o f change o f t h e frameAngle . """ s e l f . dqWaveform [ s e l f . i ] = s e l f . __rotatingDqComponents ( alphaBetaComponents , frameAngle ) [ 0 ] # Now c o n v e r t t h e v a l u e ba ck t o a s t a t i o n a r y frame and r e t u r n # temp = parkXform ( s e l f . dqWaveform [ s e l f . i ] , −f r a m e A n g l e ) s e l f . i += 1 return temp

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c l a s s SynchronousTwoPhasePLL : """ INITIALISATION Ki −− t h e i n t e g r a l g a i n o f t h e f e e d b a c k PI −− t h e a n a l o g u e v a l u e . Kp −− t h e p r o p o r t i o n a l g a i n o f t h e f e e d b a c k PI fundamentalFreq −− t h e e s t i m a t e d FUNDAMENTAL f r e q u e n c y . Frequency i s e x p r e s s e d i n Hz . NOTE THAT THIS IS THE FUNDAMENTAL FREQUENCY, AND IF HARMONCS ARE BEING CONSIDERED THEN SEE BELOW FOR OTHER PARAMETER. samplesPerFundCycle −− t h e number o f s am p les p e r c y c l e o f t h e e s t i m a t e d fundamental f r e q u e n c y . f r e q L p f C o e f f −− a t u p l e c o n t a i n i n g t h e r e c u r s i v e and non−r e c u r s i v e f o r t h e low p a s s f i l t e r on t h e f r e q u e n c y e r r o r term . DEFAULT = ( 0 . 0 , 1 . 0 ) => f i l t e r not a c t i v e

coefficients

harmonicNumberToLockTo −− t h e harmonic o f t h e fundamental t o l o c k t o . This harmonic number i s used t o d e t e r m i n e t h e c e n t r e f r e q u e n c y o f t h e VCO. DEFAULT VALUE IS 1 ( t h e fundamental ) . i n i t i a l P h a s e −− an e s t i m a t e o f t h e DEFAULT VALUE i s 0 . 0 .

i n i t i a l phase o f t h e d a x i s .

DESCRIPTION This c l a s s implements a c l a s s i c a l t h r e e phase synchronous PLL . The PLL i s b a s i c a l l y t h e one p u b l i s h e d i n a paper by Kaura and B l a s k o i n 1 9 9 7 . """ def __init__ ( s e l f , Ki , Kp , f u n d a m e n t a l F r e q , samplesPerFundCycle , f r e q L p f C o e f f = ( 0 . 0 , 1 . 0 ) , harmonicNumberToLockTo = 1 , initialPhase = 0.0) : s e l f . fundamentalFreq = fundamentalFreq s e l f . harmonicNumber = harmonicNumberToLockTo # Calculate the centre frequency in rads / sec # s e l f . fundamentalOmega = 2 . 0 ∗ p i ∗ s e l f . f u n d a m e n t a l F r e q # # # # # #

Now c a l c u l a t e t h e c e n t r e f r e q u e n c y o f t h e VCO. Note t h a t t h e PLL i s b e i n g used t o e x t r a c t phase o f a two phase r e p r e s e n t a t i o n o f a s e t o f t h r e e phase waveforms . T h e r e f o r e we need t o c o n s i d e r t h e f a c t t h a t h i g h e r o r d e r harmonics o f t h e fundamental may c o n s t i t u t e a n e g a t i v e s e q u e n c e −− i . e . t h e s p a c e v e c t o r r o t a t e s i n t h e o p p o s i t e d i r e c t i o n as compared t o t h e fundamental .

G-14

Python Listing for Two Phase PLL # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #

The a l g o r i t h m t o c a l c u l a t e t h e phase s e q u e n c e i s b a s e d on c a l c u l a t i n g t h e e f f e c t i v e phase o f t h e harmonic waveform f o r each o f t h e phase b ac k a t t h e z e r o a n g l e . For example , f o r t h e 5 t h harmonic t h e r e i s 72 d e g s f o r a c o m p l e t e p e r i o d ( on t h e o r i g i n a l t h e t a a x i s f o r t h e fundamental ) . The ’ a ’ phase 5 t h harmonic s t a r t s as z e r o d e g r e e s a t t h e z e r o d e g r e e s on t h e fundamental t h e t a a x i s . The ’ b ’ phase harmonic s t a r t s a t an o f f s e t z e r o d e g r e e s a t 120 d e g r e e s on t h e fundamental t h e t a a x i s . S i n c e a p e r i o d o f t h e 5 t h harmonic i s 72 degs , t h e n t h e r e a r e 1 2/3 r d s p e r i o d s o f t h e 5 t h harmonic i n 120 d e g s o f t h e fundamental . T h e r e f o r e i f one s l i d e s ba ck t h e waveform o f t h e 5 t h harmonic t h a t s t a r t s a t t h e ’ b ’ phase ( i . e . 120 d e g s ) t h e n t h e r e w i l l be 1 2/3 r d s c y c l e s t o g e t ba ck t o z e r o d e g r e e s . The 2/3 r d s p a r t o f t h i s i s t h e i m p o r t a n t p a r t , i n t h a t i t means t h a t t h i s ’ b ’ phase harmonic l o o k s l i k e a waveform t h a t i s s h i f t e d by 120 d e g s . S i m i l a r l y t h e ’ c ’ phase o f f s e t 5 t h harmonic w i l l have 3 1/3 rd c y c l e s o f t h e 5 t h harmonic t o g e t ba ck t o z e r o d e g r e e s . The n e t r e s u l t i s t h a t t h e a p p a r e n t phase s e q u e n c e o f t h e 5 t h harmonic i s t h e r e v e r s e o f t h e fundamental . I f a s i m i l a r s t r a t e g y i s a p p l i e d t o t h e 7 t h harmonic , t h e n we have 2 1/3 c y c l e s p e r 120 d e g s . The 1/3 rd remainder p a r t means t h a t t h e ’ b ’ phase a l i g n e d v e r s i o n w i l l be i n t h e same phase r e l a t i o n s h i p as t h e normal p o s i t i v e phase s e q u e n c e . The g e n e r a l r u l e t h e r e f o r e i s t h a t i f remainder ( 1 2 0 / ( d e g s f o r harmonic c y c l e ) ) = 1/3 rd t h e n phase s e q u e n c e i s p o s i t i v e , e l s e 2/3 r d s t h e n n e g a t i v e .

if

There a r e i s s u e s w i t h d o i n g t h e c o m p a r i s i o n s w i t h t h i s due t o t h e i n a c c u r a t e r e p r e s e n t a t i o n o f numbers i n computers .

i f round ( modf ( 1 2 0 . 0 / ( 3 6 0 . 0 / s e l f . harmonicNumber ) ) [ 0 ] ) == 1 . 0 : # The phase s e q u e n c e i s n e g a t i v e # s e l f . centreOmega = − s e l f . harmonicNumber ∗ s e l f . fundamentalOmega else : # Phase s e q u e n c e p o s i t i v e # s e l f . centreOmega = s e l f . harmonicNumber ∗ s e l f . fundamentalOmega

# A c o u p l e o f u t i l i t y r o u t i n e s t h a t a r e used . They a r e c a r r i e d h e r e so t h a t # the c l a s s i s s e l f contained . # A l l o w s wrapping o f an i n p u t v a r i a b l e w i t h a range o f \pm \ p i or 0 t o 2\ p i # so t h a t i t w i l l be i n t h e range o f \pm\ p i # s e l f . w r a p S c a l a r = lambda x : ( fmod ( x , ( 2 ∗ p i ) ) − 2 . 0 ∗ p i ) \ i f ( x > p i ) e l s e ( ( fmod ( x , ( 2 ∗ p i ) ) + 2 ∗ p i ) i f ( x < −p i ) e l s e x ) # Scalar rectangular to polar conversion # s e l f . r e c t 2 P o l a r = lambda x : ( abs ( x ) , a r c t a n 2 ( x . imag , x . r e a l ) ) # P o l a r t o r e c t a n g u l a r . t h e i n p u t i s a t u p l e as produced by r e c t 2 P o l a r o f t h e # form ( a b s ( x ) , a n g l e o f x ) # s e l f . p o l a r 2 R e c t = lambda x : x [ 0 ] ∗ e ∗ ∗ ( x [ 1 ] ∗ 1 . 0 j ) # Park t r a n s f o r m a t i o n . The thetaNew2Old v a l u e i s t h e a n g l e between t h e new a x e s and # the old axes . # s e l f . parkXform = lambda x , thetaNew2Old : x ∗ e ∗∗(− thetaNew2Old ∗ 1 . 0 j ) # C l a r k Transformation ( power v a r i a n t form ) . This a c c e p t s t h r e e i n p u t # v a r i a b l e s and c o n v e r t s them t o two phase v a l u e s i n a s t a t i o n a r y r e f e r e n c e # frame . # s e l f . c l a r k X f o r m = lambda xa , xb , xc : ( 2 . 0 / 3 . 0 ∗ ( xa − 0 . 5 ∗ xb −0.5\ ∗ xc ) + ( ( 1 / s q r t ( 3 . 0 ) ∗ ( xb − xc ) ) ∗ 1 . 0 j ) ) # I n v e r s e C l a r k transform , Returns t h e t h r e e phase v a l u e s as a t u p l e .

G-15 # s e l f . i n v C l a r k X f o r m = lambda x : ( x . r e a l , ( −0.5 ∗ x . r e a l + s q r t ( 3 . 0 ) / 2 . 0 ∗ x . imag ) , \ ( −0.5 ∗ x . r e a l − s q r t ( 3 . 0 ) / 2 . 0 ∗ x . imag ) )

# Create an i n s t a n c e o f t h e PI c o n t r o l l e r used i n t h e f e e d b a c k p a t h # s e l f . f d B a c k P i = Pi (Kp , Ki / ( s e l f . f u n d a m e n t a l F r e q ∗ s a m p l e s P e r F u n d C y c l e ) ) # Create an i n s t a n c e o f a s i n g l e p o l e low p a s s # f i l t e r o s c i l l a t i o n s out of the frequency . #

filter

t o be used t o

s e l f . freqLPF = L p f 1 s t O r d e r ( f r e q L p f C o e f f ) # Create an i n s t a n c e o f t h e f r e q u e n c y i n t e g r a t o r # s e l f . f r e q I n t e g = I n t e g r a t o r ( 1 . 0 / ( s e l f . f u n d a m e n t a l F r e q ∗ s a m p l e s P e r F u n d C y cle ) , \ i n i t i a l P h a s e , ( 0 . 0 , 0 . 0 ) , wrapping = True ) # Use t o s t o r e t h e phase o f t h e i n p u t . # s e l f . phase = i n i t i a l P h a s e # Used t o s t o r e t h e f r e q u e n c y e r r o r # s e l f . freqErr = 0.0 # The f r e q u e n c y e s t i m a t e # s e l f . freqEst = 0.0 #−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− def p l l ( s e l f , ∗ a r g s ) : """ This method implements t o c o r e o f t h e t h r e e phase synchronous PLL . The r e f e r e n c e v a l u e f o r t h e d a x i s i s f i x e d a t z e r o ( by t h e f e e d b a c k ) , which means t h a t t h e a c t u a l phase a n g l e o f t h e waveform i s 90 d e g r e e s from t h i s −− i e . t h e q a x i s a l i g n s w i t h t h e synchronous frame . I n p u t s : Two phase s t a t i o n a r y frame q u a n t i t y i n a t u p l e as xd and xq , OR t h r e e phase q u a n t i t y i n a t u p l e as xa , xb , xc Returns : Tuple c o n t a i n i n g : − [ 0 ] t h r e e phase q u a n t i t i e s as a t u p l e −− xa , xb , xc ; − [ 1 ] phase : t h e phase o f t h e s p a c e v e c t o r ; − [ 2 ] two phase synchronous frame v a l u e as a complex v a l u e ; NB: The phase v a l u e s a r e n o r m a l i s e d −− peak v a l u e i s 1 . 0 . − [ 3 ] t h e e s t i m a t e d f r e q u e n c y e r r o r between t h e c e n t r e f r e q u e n c y and the actual frequency """ if

l e n ( a r g s ) == 2 : twoPhaseValues = a r g s [ 0 ] + a r g s [ 1 ] ∗ 1 . 0 j else : # F i r s t l y c o n v e r t t o a two phase r e c t a n g u l a r form u s i n g t h e C l a r k # transformation # twoPhaseValues = s e l f . c l a r k X f o r m ( a r g s [ 0 ] , a r g s [ 1 ] , a r g s [ 2 ] ) # Now c a r r y o u t t h e park t r a n s f o r m a t i o n t o t h e e s t i m a t e d t h e t a a x i s . # syncTwoPhaseValue = s e l f . parkXform ( twoPhaseValues , s e l f . p h a s e ) # Get t h e d a x i s component as t h e f e e d b a c k v a l u e # f d b c k E r r = −syncTwoPhaseValue . r e a l # Feed t h e e r r o r i n t o t h e PI c o n t r o l l e r and t h e n f i l t e r i t . # s e l f . f r e q E r r = s e l f . freqLPF . l p f ( s e l f . f d B a c k P i . p i ( f d b c k E r r ) [ 0 ] )

G-16

Python Listing for Two Phase PLL

# Now add t h e c e n t r e f r e q u e n c y ( a l s o known as t h e f e e d f o r w a r d component ) # s e l f . f r e q E s t = s e l f . f r e q E r r + s e l f . centreOmega # Now i n t e g r a t e t h e f r e q u e n c y e s t i m a t e t o g e t t h e e s t i m a t e d phase . Note # t h a t t h i s i n t e g r a t o r w i l l a l s o c a r r y o u t −p i < Theta