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WWW.AliSaler.Com MODEL NAME : Maple PCB NO : DA8000WL000 LA-B012PR01 D

D

C

C

Dell / Compal Confidential Schematic Document Intel Shark Bay ULT Maple 14"/15" Value UMA / DIS AMD 25W/S3+DDR3x4

B

2014-01-21

B

Rev: 1.0

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

MCP(1,2/19) eDP,XDP,MISC Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

1

of

55

5

4

3

2

1

WWW.AliSaler.Com

D

D

32bit

VRAM 128M*16 DDR 3 *2 VRAM 128M*16 32bit DDR 3 *2

AMD 25W S3-64 23x23

PEG 2.0 x4 Memory Bus (DDR3L)

DDRIII-DIMM X2

Dual Channel

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

1.35V DDR3L 1600 MHz

eDP Conn.

eDP

HDMI Conn.

DDI

8GB Max

USB 3.0

Intel Broadwell ULT-U Processor BGA 1168

Port 1 Port 0

USB2.0

Port 2 Port 1

USB 3.0 Conn. 1 USB 3.0 Conn. 2

C

C

Port 2

USB 2.0 Conn. 3

PCI-E x1

x1

Port 6

NGFF 2230 WiFi/WiGi /BT4.0

Port 3

Ethernet RTL8106E

Port 4

NGFF 2230 WiFi/WiGi/BT4.0

Port 7

Digital Camera (With Digital MIC)

Port 5

Touch Screen

Port 6

SATA HDD Conn.

Port 0

SATA Rediver

Card Reader RTS5179

SATA3.0

B

B

Digital Mic. HD Audio

SPI ROM

Audio Codec ALC3234

Headphone Jack / Mic. Jack combo Int. Speaker R / L

SPI

8MB LPC Bus

I2C

33MHz

Int.KBD

ENE KBC KB9012

PS/2

Touch Pad

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

Deciphered Date

2015/01/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Title

MCP(1,2/19) eDP,XDP,MISC Size

2

Document Number

Rev 1.0

LA-B012P Date:

Sheet

Tuesday, August 05, 2014 1

2

of

55

5

4

3

2

1

WWW.AliSaler.Com Compal Confidential File Name : LA-B012P D

D

C

C

USB

RJ45

FFC 16 pin

CardReader Slot

HDMI

USB

CardReader/B

USB Audio Jack

B

B

FFC 8 pin

M/B

LED/B A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

2015/01/19

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

MCP(1,2/19) eDP,XDP,MISC Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014

Sheet 1

3

of

55

5

4

3

2

1

Board ID Table for AD channel WWW.AliSaler.Com Vcc Ra

Board ID

D

C

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

3.3V +/- 1% 100K +/- 1% Rb 0 12K +/- 1% 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1% 75K +/- 1% 100K +/- 1% 130K +/- 1% 160K +/- 1% 200K +/- 1% 240K +/- 1% 270K +/- 1% 330K +/- 1% 430K +/- 1% 560K +/- 1% 750K +/- 1% NC

HSW BOARD ID Table V AD_BID typ 0.000V 0.354V 0.430V 0.550V 0.702V 0.819V 0.992V 1.185V 1.414V 1.650V 1.865V 2.031V 2.200V 2.329V 2.408V 2.533V 2.677V 2.800V 2.912V 3.300V

V AD_BID min 0.000V 0.347V 0.423V 0.541V 0.691V 0.807V 0.978V 1.169V 1.398V 1.634V 1.849V 2.015V 2.185V 2.316V 2.395V 2.521V 2.667V 2.791V 2.905V 3.000V

EC 0x00 0x0C 0x1D 0x27 0x31 0x3C 0x47 0x55 0x65 0x77 0x88 0x97 0xA4 0xAE 0xB8 0xC1 0xCA 0xD4 0xDD 0xE7

V AD_BID max 0.300V 0.360V 0.438V 0.559V 0.713V 0.831V 1.006V 1.200V 1.430V 1.667V 1.881V 2.046V 2.215V 2.343V 2.421V 2.544V 2.687V 2.808V 2.919V 3.300V

AD3 - 0x0B - 0x1C - 0x26 - 0x30 - 0x3B - 0x46 - 0x54 - 0x64 - 0x76 - 0x87 - 0x96 - 0xA3 - 0xAD - 0xB7 - 0xC0 - 0xC9 - 0xD3 - 0xDC - 0xE6 - 0xFF

Board ID 0 1 2 3 4 5 6 7 8 9 10 11

EC_SMB_CK1 EC_SMB_DA1

KB9012

EC_SMB_CK2 EC_SMB_DA2

KB9012

SMBCLK SMBDATA

ULT

SML0CLK SML0DATA

ULT

SML1CLK SML1DATA

ULT

BATT

V

Charger

VGA

DIMM

XDP

Thermal Sensor

FFS

V V

V V V

DIS(JET) DIS(Topaz)

USB3.0 SSI SSI

V Link

Board ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

Port1

USB connector 1

Port2

USB connector 2

D

PT PT PT

Port3

ST ST

Port4

ST 1.0

USB2.0

1.0 1.0

BDW BOARD ID Table

SMBUS Control Table SOURCE

UMA SSI

DIS(JET) DIS(Topaz) UMA Pre-SSI Pre-SSI Pre-SSI SSI SSI SSI PT PT PT ST ST ST 1.0 1.0 1.0

Port0

USB connector 1

Port1

USB connector 2

Port2

USB connector 3 (D/B)

Port3 C

ULT

Port4

MINI Card (WLAN)

Port5

Touch Screen Panel

Port6

Card Reader

Port7

Camera PCI EXPRESS

Lane 1 Lane 2 Lane 3

10/100 LAN

Lane 4

MINI Card (WLAN)

Lane 5

PEG (AMD JET/TOBAZ)

B

B

CLOCK SIGNAL

Lane 6

CLKOUT_PCIE0

SATA

CLKOUT_PCIE1

A

SATA0

CLKOUT_PCIE2

10/100 LAN

CLKOUT_PCIE3

MINI Card (WLAN)

CLKOUT_PCIE4

dGPU

HDD

SATA1 SATA2 SATA3 A

CLKOUT_PCIE5

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

2015/01/19

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

MCP(1,2/19) eDP,XDP,MISC Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014

Sheet 1

4

of

55

5

4

3

2

1

WWW.AliSaler.Com 2.2K

SMBUS Address [0x9a]

2.2K D

AP2

MEM_SMBCLK

AH1

MEM_SMBDATA

10K

+3.3V_ALW_PCH

+3VS

10K

N-MOS N-MOS

DDR_XDP_WLAN_TP_SMBCLK

202

DDR_XDP_WLAN_TP_SMBDAT

200

D

DIMM1

SMBUS Address [A0]

DIMM2

SMBUS Address [A4]

1K 202

+3.3V_ALW_PCH

1K

MCH Shark bay

AN1

SML0CLK

AK1

SML0DATA

200

0 ohm 0 ohm

2.2K 2.2K AN1

SML1_SMBCLK

AK1

SML1_SMBDATA

DDR_XDP_SMBCLK_R1

53

DDR_XDP_SMBDAT_R1

51

XDP1

SMBUS Address [TBD]

+3.3V_ALW_PCH N-MOS N-MOS

EC_SMB_CK2 EC_SMB_DA2

2.2K

C

2.2K 79

EC_SMB_CK2

80

EC_SMB_DA2

C

+3VALW

2.2K

+3VS_VGA

2.2K N-MOS N-MOS

VGA_SMB_CK2

T4

VGA_SMB_DA2

T3

UV28

GPU

SMBUS Address [0xXX]

2.2K 2.2K

KBC KB9012A4

B

77

EC_SMB_CK1

78

EC_SMB_DA1

+3VALW 0 ohm 0 ohm

SCL

11

SDA

10

100 ohm

3

100 ohm

1

PU701

PD1

POWER Charger

SMBUS Address [0x12]

4

BAT_ALERT

3

6

BATT_PRS

5

PBATT

B

BATT SMBUS Address [0x16] CONN

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

MCP(1,2/19) eDP,XDP,MISC Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

5

of

55

5

4

3

2

1

WWW.AliSaler.Com i3-4020U-15W-GT2-MP

UC1

I3R1@

UC2

I3R3@

CL8064701552800 QEZ5 D0 1.8G

CL8064701478202 SR16Q C1 1.7G A31!

SA00007MG0L

SA00006SX2L TBD





i5-4210U-15W-GT2-MP

D

UC4

I5R1@

UC5

I5R3@

CL8064701477802 QEAK D0 1.7G

CL8064701477702 SR170 C1 1.6G A31!

SA00007LO0L

SA00006SM3L TBD

C54 C55 B58 C58 B55 A55 A57 B57

DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3

DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3 UC6

i7-4510U-15W-GT2-MP UC7

UC8

Broadwell

I7R3@

UC9

CL8064701477301 QEAF D0 2G BGA

CL8064701477202 SR16Z C1 1.8G A31!

SA00007M70L

SA00006SL2L TBD

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

C51 C50 C53 B54 C49 B50 A53 B53

QG21@

CL8065801674128 QG21 C0 1.2G

I7R1@

HASWELL_MCP_E

UC3A

C45 B46 A47 B47

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

DDI

EDP

COMPENSATION PU FOR eDP

A45 B45

EDP_AUXN EDP_AUXP

D20 A43

EDP_RCOMP EDP_DISP_UTIL

UC10

2

EDP_COMP EDP_DISP_UTIL

1

2

EDP_BIA_PWM

Rev1p2

1 OF 19

CL8064701614813 QFSY C0 1.6G

CL8065801675027 QG22 C0 1.2G

SA00007AM0L

SA00007OT0L

+1.05VS_PCH +1.05VS_PCH

14 1

PCH_JTAG_TDO

PCH_JTAG_TDO

@

RC3

2 TDO_XDP 0_0402_1% RUNPWROK

1

PCH_JTAG_TDI

2 TDI_XDP 0_0402_1%

@

RC4

1

@

RC5

2 TDI_XDP_R 0_0402_1% RUNPWROK

1

PCH_JTAG_TMS

@

RC6

2 TMS_XDP 0_0402_1%

2 1 5 4 9

RUNPWROK

10

TRST#_XDP

12

RUNPWROK CC5

1

ESD@

0.1U_0402_10V7K

RUNPWROK

RUNPWROK

13

VCC

2

1A

3

1B

XDP_TDO

2

6

2B



XDP_TDI

Place near JXDP1

CFG0 CFG1

8

3B

XDP_OBS0_R XDP_OBS1_R

XDP_TMS

3OE 4A

11

4B

4OE

7

GND

2

XDP_TRST# H_CPUPWRGD PBTN_OUT#

CPU_PWR_DEBUG# SYS_PWROK

15



74CBTLV3126BQ_DHVQFN14_2P5X3

SYS_PWROK

CFG2 CFG3

CFG2 CFG3

2OE 3A

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

XDP_PREQ# XDP_PRDY# CFG0 CFG1

1OE 2A



CFG4 CFG5



CFG6 CFG7

CFG4 CFG5 CFG6 CFG7

RC7 RC9

1 XDP@ 1 XDP@

2 1K_0402_5% 2 0_0402_5%

H_VCCST_PWRGD_XDP CFD_PWRBTN#_XDP

RC11 RC12

1 XDP@ 1 XDP@

2 0_0402_5% 2 0_0402_5%

CPU_PWR_DEBUG#_R SYS_PWROK_XDP

1 2 3 4

8 7 6 5

DDR_XDP_SMBDAT_R1 DDR_XDP_SMBCLK_R1

DDR_XDP_WLAN_TP_SMBDAT DDR_XDP_WLAN_TP_SMBCLK PCH_JTAG_TCK

XDP_TCLK

RP1 0_8P4R_5%

reference Shark Bay ULT Validation Customer Debug Port Implementation Requirement Rev 1.0

+1.05VS_PCH

JXDP1



GND PAD

Place CC29 close to UC4

1

XDP@ CC3 0.1U_0402_10V7K

1

UC11 @

XDP@ CC2 0.1U_0402_10V7K

1

0.1U_0402_10V7K

RC2

CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils.

@

+3VS

C

1

24.9_0402_1%~D

@ RC1 0_0402_5%

QG22@

CC1

2

+VCCIOA_OUT

EDP_AUX# EDP_AUX

SA00007OS0L

QFSY@

D

C47 C46 A49 B49

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

EDP_TX0# EDP_TX0 EDP_TX1# EDP_TX1

XDP@

GND0 GND1 OBSFN_A0 OBSFN_C0 OBSFN_A1 OBSFN_C1 GND2 GND3 OBSDATA_A0 OBSDATA_C0 OBSDATA_A1 OBSDATA_C1 GND4 GND5 OBSDATA_A2 OBSDATA_C2 OBSDATA_A3 OBSDATA_C3 GND6 GND7 OBSFN_B0 OBSFN_D0 OBSFN_B1 OBSFN_D1 GND8 GND9 OBSDATA_B0 OBSDATA_D0 OBSDATA_B1 OBSDATA_D1 GND10 GND11 OBSDATA_B2 OBSDATA_D2 OBSDATA_B3 OBSDATA_D3 GND12 GND13 PWRGOOD/HOOK0 ITPCLK/HOOK4 HOOK1 ITPCLK#/HOOK5 VCC_OBS_AB VCC_OBS_CD HOOK2 RESET#/HOOK6 HOOK3 DBR#/HOOK7 GND14 GND15 SDA TD0 SCL TRST# TCK1 TDI TCK0 TMS GND16 GND17 SAMTE_BSH-030-01-L-D-A CONN@

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

CFG17 CFG16

CFG17 CFG16

CFG8 CFG9



CFG8 CFG9

CFG10 CFG11 CFG19 CFG18 CFG12 CFG13 CFG14 CFG15

CC4

CFG10 CFG11



CFG19 CFG18



CFG12 CFG13



CFG14 CFG15 RC8 1 XDP@ RC10 1 XDP@

CLK_XDP CLK_XDP#

2 XDP_RST#_R XDP_DBRESET#

C

1

2

Place CC30 close to RC51.1

0_0402_5% 0_0402_5%

CLK_CPU_ITP CLK_CPU_ITP#

PLT_RST# 2

RC13 1K_0402_5%

TDO_XDP TRST#_XDP TDI_XDP TMS_XDP 1 CFG3_R RC15 XDP@

ESD@

0.047U_0402_16V4Z



2 2

1

PLT_RST#



PLT_RST# +3VS

1



RC14 1K_0402_1% 1 2

XDP@

2 CFG3 1K_0402_5%

CC6 0.1U_0402_10V7K

+3VALW_PCH

2

H_CATERR# 49.9_0402_1% 2 H_PROCHOT# 62_0402_5%

@ RC16

1 RC18

PCH_JTAG_RST# 0_0402_1%

PCH_JTAG_JTAGX

2

@

1

1

@

2

0_0402_1%

XDP_TRST# RC17

@ RC19 1K_0402_5%

XDP_TCLK RC21

XDP_DBRESET#

1

1

2

+1.05VS_PCH

2 B

0_0402_5%

PCH_JTAG_TCK

1

TDO_XDP RC22

1

TDI_XDP_R RC23

XDP@

PCH_JTAG_TDO 0_0402_5%

2

PCH_JTAG_TCK 0_0402_5%

2

XDP@

1 XDP@

1

2

XDP_TCLK RC24

1

@

2

SYS_RESET#

SYS_RESET#

RC20 0_0402_1%

SYS_PWROK_XDP

B

ESD@ CC7 0.1U_0402_10V7K

Place near JXDP1.47

H_CPUPWRGD

HASWELL_MCP_E

1

UC3B

RC25 10K_0402_5%

1

2

2

CC8 100P_0402_50V8J @EMI@

H_CATERR# PECI_EC

PECI_EC

D61 K61 N62

PROC_DETECT CATERR PECI

MISC

PRDY PREQ PROC_TCK PROC_TMS PROC_TRST PROC_TDI PROC_TDO

JTAG

ESD solution

CAD Note: Avoid stub in the PWRGD path while placing resistors RC115

1 RC26

H_PROCHOT#

2

H_PROCHOT#_R 56_0402_5%

H_CPUPWRGD

K63

C61

H_PROCHOT#

1

DDR3 COMPENSATION SIGNALS 200_0402_1%

2

1 RC28

SM_RCOMP0

120_0402_1%

2

1 RC29

SM_RCOMP1

100_0402_1%

2

1 RC30

SM_RCOMP2

2

@EMI@ CC9 22P_0402_50V8J

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 DDR3_DRAMRST#_CPU DDR_PG_CTRL

AU60 AV60 AU61 AV15 AV61

PROCHOT

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1

THERMAL

XDP_PRDY# XDP_PREQ# XDP_TCK XDP_TMS XDP_TRST# XDP_TDI XDP_TDO

J60 H60 H61 H62 K59 H63 K60 J61

XDP_OBS0_R XDP_OBS1_R

PU/PD for JTAG signals 1

2

PCH_JTAG_RST#

PCH_JTAG_RST#

@ R1 0_0402_5%

XDP_TMS XDP_TDI XDP_PREQ# TDO_XDP

1 2 3 4

XDP_TDO XDP_TCK XDP_TRST#

1 2 3 4

+1.05VS_PCH

8 7 6 5

PWR

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

DDR3

RC27 @ @ @ @ @ @

1

@

2 0_0402_1% RP2 @ 51_8P4R_5%

T1 T2 T3 T4 T5 T6

8 7 6 5 RP3 51_8P4R_5%

Rev1p2

2 OF 19 A

J62 K62 E60 E61 E59 F63 F62

A

@

CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil

DDR3_DRAMRST#_CPU CC10

@ESD@

0.047U_0402_16V4Z

1

2

Place CC35 on BOT

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

2

Date:

MCP(1,2/19) eDP,XDP,MISC Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014

Sheet 1

6

of

55

5

4

3

2

1

WWW.AliSaler.Com Interleaved Memory UC3C

D





DDR_A_D[0..15]

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31

DDR_B_D[0..15]

DDR_A_D[16..31]

C

DDR_B_D[16..31]

AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51

HASWELL_MCP_E

HASWELL_MCP_E

UC3D

DDR_A_D[32..47]

D

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_CLK#0 SA_CLK0 SA_CLK#1 SA_CLK1 SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3 SA_CS#0 SA_CS#1

M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1

AU43 AW43 AY42 AY43

DDR_CKE0_DIMMA DDR_CKE1_DIMMA

AP33 AR32

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

M_CLK_DDR#0

M_CLK_DDR0

M_CLK_DDR#1

M_CLK_DDR1

DDR_CKE0_DIMMA DDR_CKE1_DIMMA



DDR_CS0_DIMMA# DDR_CS1_DIMMA#



AP32

SA_ODT0 SA_RAS SA_WE SA_CAS SA_BA0 SA_BA1 SA_BA2

AY34 AW34 AU34

DDR_A_RAS# DDR_A_WE# DDR_A_CAS#

AU35 AV35 AY41

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

DDR CHANNEL A

AU37 AV37 AW36 AY36

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

DDR_A_RAS# DDR_A_WE# DDR_A_CAS#

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_MA[0..15]

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_DQS#0 DDR_A_DQS#1 DDR_B_DQS#0 DDR_B_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_B_DQS#2 DDR_B_DQS#3

DDR_A_DQS#[0..1]

DDR_B_DQS#[0..1]

DDR_A_DQS#[2..3]

DDR_B_DQS#[2..3]



DDR_A_DQS0 DDR_A_DQS1 DDR_B_DQS0 DDR_B_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_B_DQS2 DDR_B_DQS3

DDR_B_D[32..47]



AP49 AR51 AP51

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1



DDR_A_DQS[0..1]

DDR_B_DQS[0..1]

DDR_A_DQS[2..3]

DDR_B_DQS[2..3]

DDR_A_D[48..63]

DDR_B_D[48..63]

+SM_VREF_CA +SM_VREF_DQ0 +SM_VREF_DQ1

AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AM29 AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25 AL25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_CK#0 SB_CK0 SB_CK#1 SB_CK1 SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3 SB_CS#0 SB_CS#1

M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3

AY49 AU50 AW49 AV50

DDR_CKE2_DIMMB DDR_CKE3_DIMMB

AM32 AK32

DDR_CS2_DIMMB# DDR_CS3_DIMMB#

M_CLK_DDR#2

M_CLK_DDR2

M_CLK_DDR#3

M_CLK_DDR3

DDR_CKE2_DIMMB DDR_CKE3_DIMMB



DDR_CS2_DIMMB# DDR_CS3_DIMMB#



AL32

SB_ODT0 SB_RAS SB_WE SB_CAS SB_BA0 SB_BA1 SB_BA2

DDR CHANNEL B

AM38 AN38 AK38 AL38

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

AM35 AK35 AM33

DDR_B_RAS# DDR_B_WE# DDR_B_CAS#

AL35 AM36 AU49

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

DDR_B_RAS# DDR_B_WE# DDR_B_CAS#



DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_MA[0..15]

C

DDR_A_DQS#4 DDR_A_DQS#5 DDR_B_DQS#4 DDR_B_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_B_DQS#6 DDR_B_DQS#7

DDR_A_DQS#[4..5]

DDR_B_DQS#[4..5]

DDR_A_DQS#[6..7]

DDR_B_DQS#[6..7]

DDR_A_DQS4 DDR_A_DQS5 DDR_B_DQS4 DDR_B_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_B_DQS6 DDR_B_DQS7

DDR_A_DQS[4..5]

DDR_B_DQS[4..5]

DDR_A_DQS[6..7]

DDR_B_DQS[6..7]

B

B

4 OF 19 3 OF 19

Rev1p2

Rev1p2

@ @

RC37 1.82K_0402_1%

1

1 1

RC35 2.2_0402_1% RC38 1.82K_0402_1%

2

CC11 0.022U_0402_16V7K

RC41 24.9_0402_1%~D

1

RC36 2.2_0402_1%

2

CC12 0.022U_0402_16V7K

change 22nF RC42 24.9_0402_1%~D

2

2

2

RC40 24.9_0402_1%~D

+SM_VREF_DQ0

2

RC39 1.82K_0402_1%

change 22nF

2

change 22nF

2

1

2

CC13 0.022U_0402_16V7K

2

1

1

RC33 1.82K_0402_1%

1

1

+SM_VREF_DQ0_DIMM1

2

2

RC34 2.2_0402_1%

+SM_VREF_DQ1

2

RC32 1.82K_0402_1%

1

1

1

+SM_VREF_DQ1_DIMM2

1

+SM_VREF_CA

2

RC31 1.82K_0402_1%

2

+SM_VREF_CA_DIMM

+1.35V

1

+1.35V

1

+1.35V

confirm by intel request PDG P141

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

MCP(3,4/19) DDR3 Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

7

of

55

5

4

3

2

1

WWW.AliSaler.Com 1

+RTCVCC

RTC Battery 2

RC43 330K_0402_1%

+RTCBATT D

PCH_INTVRMEN

2

1

+3VS

2

1 2

3

+CHGRTC

D

RC45 330K_0402_1%

JP2

2

1

1

+3VLP

2

@ RC46

PCH_AZ_SDOUT 1K_0402_5%

JUMP_43X39

INTVRMEN - INTEGRATED SUS 1.05V VRM ENABLE High - Enable Internal VRs Low - Enable External VRs

1

For GCLK

+RTCVCC W=20mils

1

JUMP_43X39

W=20mils DC1 BAT54CW_SOT323-3

1

1

@

W=20mils

2

1

2

JP1

2

+RTCVCC

RC44 1K_0402_5%

+CHGRTC

CC14 1U_0603_10V6K

PCH_RTCX1

PCH_RTCX1

FLASH DESCRIPTOR SECURITY OVERRIDE LOW = DESABLED (DEFAULT) HIGH = ENABLED

2 CC15 XTAL@ 1 2

1

PCH_RTCX1

1

XTAL@ RC47 10M_0402_5%

1

1M_0402_5%

1 RC48 1 RC49

+RTCVCC

C

PCH_RTCX2 INTRUDER# PCH_INTVRMEN SRTCRST# PCH_RTCRST#

2 2 2

20K_0402_5% 20K_0402_5%

2

1 1

1

2

SHORT PADS~D 2 1U_0402_6.3V6K

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

RTC

CC17 1U_0402_6.3V6K PCH_AZ_BITCLK PCH_AZ_SYNC PCH_AZ_RST# PCH_AZ_CODEC_SDIN0

PCH_AZ_CODEC_SDIN0

RTCX1 RTCX2 INTRUDER INTVRMEN SRTCRST RTCRST

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

2

@ CMOS1 1 CC18

AW5 AY5 AU6 AV7 AV6 AU7

1 RC51

ME_EN

2

PCH_AZ_SDOUT 1K_0402_5%

AW8 AV11 AU8 AY10 AU12 AU11 AW10 AV10 AY8

HDA_BCLK/I2S0_SCLK HDA_SYNC/I2S0_SFRM HDA_RST/I2S_MCLK HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_SDO/I2S0_TXD HDA_DOCK_EN/I2S1_TXD HDA_DOCK_RST/I2S1_SFRM I2S1_SCLK

AUDIO

SATA

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1 SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

CMOS place near DIMM



RTC discharge by EC

AU62 AE62 AD61 AE61 AD62 AL11 AC4 PCH_JTAG_JTAGX AE63 AV2 PCH_JTAG_RST# PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_JTAG_RST# PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_JTAGX

SRTCRST#

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37 PCH_TRST PCH_TCK PCH_TDI PCH_TDO PCH_TMS RSVD RSVD JTAGX RSVD

SATA_IREF RSVD RSVD SATA_RCOMP SATALED

JTAG

J5 H5 B15 A15

SATA_PRX_DTX_N0_C SATA_PRX_DTX_P0_C SATA_PTX_DRX_N0_C SATA_PTX_DRX_P0_C



SATA HDD

J6 H6 B14 C15

PCH Rx side need use strap pin to update PCIE +/+3VS

F5 E5 C17 D17

RC52 10K_0402_5%

V1 U1 V6 AC1

EC_SMI# PCH_GPIO35 ODD_DETECT# PCH_GPIO37

A12 L11 K10 C12 U3

SATA_IREF

RC53

1

SATA_RCOMP SATA_ACT#

RC54

1

EC_SMI#

+1.05VS_ASATA3PLL

ODD_DETECT#

SATA_ACT#

2 0_0603_1%

@

2 3.01K_0402_1%

within 500 mils

PCH_RTCRST#

6

@

G

2

D

B

5 OF 19

C

J8 H8 A17 B17

2

CC16 XTAL@ 15P_0402_50V8J 1 2 RC50

HASWELL_MCP_E

UC3E

2

2

XTAL@ YC1 32.768KHZ_12.5PF_Q13FC1350000

1

15P_0402_50V8J

SATA Impedance Compensation CAD note: Place the resistor within 500 mils of the PCH. Avoid routing next to clock pins. reference FFRD sch 0.5

Rev1p2 B

DMN66D0LDW-7_SOT363-6 QC1B

S

1

@

3

@

G

5

RTC_DIS

D

4

S

1

CMOS_CLR1

RC55 100K_0402_5%

Shunt

2

@

+3VS

HDA for Codec

DMN66D0LDW-7_SOT363-6 QC1A

CMOS setting Clear CMOS

Open

Keep CMOS

ME_CLR1

TPM setting

Shunt

Clear ME RTC Registers

Open

Keep ME RTC Registers

PCH_AZ_CODEC_SDOUT

PCH_AZ_CODEC_SYNC



PCH_AZ_CODEC_RST# PCH_AZ_CODEC_BITCLK

EMI@ R2

1

2 33_0402_5%

PCH_AZ_SDOUT

EMI@ R3

1

2 33_0402_5%

PCH_AZ_SYNC

EMI@ R4

1

2 33_0402_5%

PCH_AZ_RST#

EMI@ R5

1

2 33_0402_5%

PCH_AZ_BITCLK

ODD_DETECT# PCH_GPIO35 PCH_GPIO37

1 2 3 4

8 7 6 5 RP4 10K_8P4R_5%

1 @EMI@ CC19 27P_0402_50V8J

+1.05VS_PCH

2

@ RC56

2

1

PCH_JTAG_JTAGX 1K_0402_1%

@ RC57

2

1

PCH_JTAG_TCK 51_0402_1%

EMI depop location

A

A

+1.05VS_PCH

1 2 3 4

8 7 6 5

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

Issued Date

5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

RP5 51_8P4R_5%

2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

WWW.AliSaler.Com 3

Date:

2

MCP(5/19) RTC,SATA,HDA,JTAG Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

8

of

55

5

4

3

2

1

WWW.AliSaler.Com MEM Bus : DDR/XDP/WLAN/TP

+3VALW_PCH

+3VS

PCH_SPI_MOSI_1 PCH_SPI_MISO_1 PCH_SPI_WP1# PCH_SPI_HOLD1#

1 2 3 4

8 7 6 5

PCH_SPI_MOSI PCH_SPI_MISO PCH_SPI_WP# PCH_SPI_HOLD#

SPI

CL_CLK CL_DATA CL_RST

C-LINK

2

2

SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_MOSI SPI_MISO SPI_IO2 SPI_IO3

AF2 AD2 AF4

@ @ @

1 2

2

2 6

MEM_SMBCLK

1

DDR_XDP_WLAN_TP_SMBCLK

DDR_XDP_WLAN_TP_SMBDAT

QC1B DMN66D0LDW-7_SOT363-6

5

SML0CLK SML0DATA PCH_HOT# SML1_SMBCLK SML1_SMBDATA

S

RP39

2

AA3 Y7 Y4 AC2 AA2 AA4 Y6 AF1

R9 10K_0402_5%

G

PCH_SPI_CLK PCH_SPI_CS0#

R8 10K_0402_5%

PCH_SMB_ALERT# MEM_SMBCLK MEM_SMBDATA

3

MEM_SMBDATA T97 T98 T99

4 S

1

1

LPC

AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3

D

@EMI@ C2326 68P_0402_50V8J

SMBALERT/GPIO11 SMBCLK SMBDATA SML0ALERT/GPIO60 SMBUS SML0CLK SML0DATA SML1ALERT/PCHHOT/GPIO73 SML1CLK/GPIO75 SML1DATA/GPIO74

D

PCH_SPI_CLK_R

EMI@ R2333 2 15_0402_1%

LAD0 LAD1 LAD2 LAD3 LFRAME

G

EMI

+3VS

HASWELL_MCP_E

UC3G

AU14 AW12 AY12 AW11 AV12

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME#

R7 10K_0402_5%

1

R6 10K_0402_5%

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME#

D

1

1

D

QC1A DMN66D0LDW-7_SOT363-6

15_8P4R_5%

+3VALW_PCH R2334 1 R2335 1

2 1K_0402_1% 2 1K_0402_1%

7 OF 19

Rev1p2

@

SML1 Bus : EC/Sensors C

C

U2302 +3VALW_PCH

WINBOND +3VALW_PCH

64M W25Q64FVSSIQ SOIC 8P

QH1B

CS# VCC DO(IO1) HOLD#(IO3) WP#(IO2) CLK GND DI(IO0)

PCH_SPI_HOLD1# PCH_SPI_CLK_R PCH_SPI_MOSI_1

6

EC_SMB_CK2

EC_SMB_DA2

5

D

1

DMN66D0LDW-7_SOT363-6

G

8 7 6 5

8 7 6 5

4

SML1_SMBDATA

3 S

1 2 3 4

1 2 3 4

D

U2302 PCH_SPI_CS0# PCH_SPI_MISO_1 PCH_SPI_WP1#

SML1_SMBCLK

RP40 MEM_SMBCLK MEM_SMBDATA SML1_SMBCLK SML1_SMBDATA

S

SPI ROM ( 8MByte )

G

C2327 0.1U_0402_10V7K 1 2

2

+3VALW_PCH

SA000039A30

QH1A DMN66D0LDW-7_SOT363-6

2.2K_0804_8P4R_5%

64M EN25Q64-104HIP SOP 8P RP49 SML0CLK SML0DATA

@

1 2 3 4

8 7 6 5

For GCLK

1K_0804_8P4R_5%

XTAL24_IN

XTAL24_IN

CC6 15P_0402_50V8J 2 1

3 4

1 XTAL@

C43 C42 U2 B41 A41 Y5

10/100 LAN ------->

CLK_PCIE_LAN# CLK_PCIE_LAN LAN_CLKREQ#

WLAN(Mini Card)--->



CLK_PCIE_WLAN# CLK_PCIE_WLAN

CLK_PEG_VGA# CLK_PEG_VGA PEG_CLKREQ#

dGPU--->

C41 B42 AD1

CLK_PCIE_LAN# CLK_PCIE_LAN

B38 C37 N1

CLK_PCIE_WLAN# CLK_PCIE_WLAN WLAN_CLKREQ#_R

A39 B39 U5

CLK_PEG_VGA# CLK_PEG_VGA

B37 A37 T2 @ R2452 1

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 PCIECLKRQ0/GPIO18

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIECLKRQ2/GPIO20

3

WLAN_CLKREQ#_R

CLKOUT_LPC_0 CLKOUT_LPC_1 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 PCIECLKRQ4/GPIO22

K21 M21 C26

CLK_BIASREF

C35 C34 AK8 AL8 AN15 AP15

SWAP_1 SWAP_2

CC7 15P_0402_50V8J 2 1

RC13 XTAL@ 3.01K_0402_1% 2 +1.05VS_AXCK_LCPLL RP41 10K_8P4R_5% 1 8 SWAP_2 2 7 SWAP_1 3 6 4 5

CLKOUT_LPC0

1

2 R2336

1 EMI@ 22_0402_5%

B35 A35

CLK_PCI_LPC

CLK_CPU_ITP#

CLK_CPU_ITP

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 PCIECLKRQ5/GPIO23 6 OF 19

1 2 3 4

XTAL24_IN XTAL24_OUT

Rev1p2

8 7 6 5

A

2 G

Q2409

SIGNALS

A25 B25

@

RP42

S

1

D

WLAN_CLKREQ#

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

CLOCK

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 PCIECLKRQ3/GPIO21

+3VS_WLAN_NGFF +3VS

RSVD RSVD DIFFCLK_BIASREF

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 PCIECLKRQ1/GPIO19

2

0_0402_5%~D DII-DMN65D8LW-7~D A

XTAL24_IN XTAL24_OUT

B

XTAL@ XTAL@ YC2 24MHZ_12PF_X3G024000DC1H

1 2

2 HASWELL_MCP_E

UC1F

RC12 1M_0402_5%

B

10K_8P4R_5%

1

+3VS R2453 100K_0402_5%~D

2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

MCP(6,7/19) CLK,SMB,SPI,LPC Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

9

of

55

5

4

3

2

1

WWW.AliSaler.Com PCH_PLTRST# CC33 +3VALW_PCH

2

ME_SUS_PWR_ACK 10K_0402_5% 2 SUSACK# 10K_0402_5% 2 SUS_STAT#/LPCPD# 10K_0402_5%

+3VS

@ RC28

1 @ RC29

@ CC11 1 2

1

PCH_PLTRST# +3V_DSW

2

IN1 IN2

2

RC32

1 RC31

1 RC34

1 RC39

3

AC_PRESENT 10K_0402_5% 2 PCH_BATLOW# 8.2K_0402_5% 2 PCIE_WAKE#_R 1K_0402_5% 2 PCH_SLP_WLAN# 10K_0402_5%

RC33

1

2

2

PCH_RSMRST#_R 0_0402_5%

2

SUSACK# 0_0402_5%

@

ME_SUS_PWR_ACK_R RC35

1 @

CLKRUN# 8.2K_0402_5%

PLT_RST#

PLT_RST#

UC3 MC74VHC1G08DFT2G_SC70-5

R159 100K_0402_5%

DSWODVREN - On Die DSW VR Enable H Enable(DEFAULT) L Disable

Note: SUSACK# and SUSWARN# can be tied together if EC does not want to involve in the handshake mechanism for the Deep Sleep state entry and exit CAN be NC ,if not support Deep Sx

+3VS

RC36

1

PCH_DPWROK

4

OUT

2

1

D

0.1U_0402_10V7K

1

1

5

RC27

2

Place CC33 close to UC3.1 & UC3.2

VCC

1

GND

D

1

ESD@

0.047U_0402_16V4Z

*

+RTCVCC

DPWROK: Tired toghter with RSMRST# that do not support Deep Sx

HASWELL_MCP_E

UC1H

HIGH = ENABLED (DEFAULT) R2337 1 R2338 1

@

2 330K_0402_5% 2 330K_0402_5%

LOW = DISABLED

SYSTEM POWER MANAGEMENT

SYS_PWROK CC31

C



1

@ESD@

0.047U_0402_16V4Z

SUSACK#

SUSACK#

2

Place CC31 on BOT

DH1

PCH_PWROK CC34

1

@ESD@

0.047U_0402_16V4Z

SUSACK#_R SYS_RESET# SYS_PWROK_R PCH_PWROK_R PM_APWROK_R PCH_PLTRST#

0_0402_1%

SYS_RESET#

2 0_0402_1% 2 0_0402_1%

PBTN_OUT# 2 RB751V-40_SOD323-2

1

ACIN

2

@

RP50 0_8P4R_5% 1 RC41 @ 1 RC42 @

EC_RSMRST# ME_SUS_PWR_ACK

1 8 7 6 5

1 2 3 4

SYS_PWROK

SYS_PWROK PCH_PWROK

RC37

SIO_SLP_S0#

AK2 AC3 AG2 AY7 AB5 AG7

AW6 PCH_RSMRST#_R ME_SUS_PWR_ACK_R AV4 AL7 PBTN_OUT# AJ8 AC_PRESENT AN4 PCH_BATLOW# AF3 SIO_SLP_S0# AM5 PCH_SLP_WLAN#

SUSACK SYS_RESET SYS_PWROK PCH_PWROK APWROK PLTRST

DSWVRMEN DPWROK WAKE CLKRUN/GPIO32 SUS_STAT/GPIO61 SUSCLK/GPIO62 SLP_S5/GPIO63

RSMRST SUSWARN/SUSPWRDNACK/GPIO30 PWRBTN ACPRESENT/GPIO31 BATLOW/GPIO72 SLP_S0 SLP_WLAN/GPIO29

PCH_BATLOW# Need pull high to VCCDSW3_3 (If no deep Sx , connect to VCCSUS3_3)

2

SLP_S4 SLP_S3 SLP_A SLP_SUS SLP_LAN

8 OF 19

Place CC34 close to RP50.2&RP50.3

DSWODVREN - ON DIE DSW VR ENABLE

AW7 AV5 AJ5

DSWODVREN PCH_DPWROK PCIE_WAKE#_R

V5 AG4 AE6 AP5

CLKRUN# SUS_STAT#/LPCPD# SUSCLK SIO_SLP_S5#

AJ6 AT4 AL5 AP4 AJ7

SIO_SLP_S4# SIO_SLP_S3# @ T105 @

T107

@

T106

1

PCH_DPWROK

PCIE_WAKE#

2 PCIE_WAKE# @ RC97 0_0402_5%

C

SUSCLK SIO_SLP_S5# T103 PAD~D@ T104 PAD~D @ SIO_SLP_S4# SIO_SLP_S3# SLP_SUS#

Rev1p2

@

+3VS

+3VS

1

2

RC73

1

@

2

1

@

2

RC74 B

RC75

1

2

RC76

1

2

1

2

RC77 RC79

1

2

2

1

@ RC87 @ RC88

HASWELL_MCP_E

UC1I

DGPU_PWROK 10K_0402_5% PCH_TP_INT# 10K_0402_5% EDP_BIA_PWM 10K_0402_5% TS_RST# 10K_0402_5% DGPU_HOLD_RST# 10K_0402_5% FFS_INT1 10K_0402_5%

2

EDP_BIA_PWM

EDP_BIA_PWM PANEL_BKLEN

@ RC81 0_0402_1% 1

ENVDD_PCH

DGPU_PWROK

PXS_PWREN DGPU_HOLD_RST# FFS_INT1

ENVDD_PCH 100K_0402_5% CODEC_IRQ 1K_0402_1%

TS_RST#

PCH_TP_INT# TS_RST# CODEC_IRQ

EDP_BKLCTL PANEL_BKLEN ENVDD_PCH

B8 A9 C6

U6 DGPU_PWROK P4 PXS_PWREN DGPU_HOLD_RST# N4 N2 FFS_INT1 AD4 T117 @ U7 L1 L3 R5 L4

EDP_BKLCTL EDP_BKLEN EDP_VDDEN

PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME

CPU_DPB_CTRLDAT CPU_DPB_CTRLCLK CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT

DDPB_CTRLCLK DDPB_CTRLDATA DDPC_CTRLCLK DDPC_CTRLDATA

eDP SIDEBAND

DISPLAY

GPIO

GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP

DDPB_HPD DDPC_HPD EDP_HPD

9 OF 19

B9 C9 D9 D11

CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT

C5 B6 B5 A6

CPU_DPB_AUX# CPU_DPC_AUX# CPU_DPB_AUX CPU_DPC_AUX

C8 A8 D6

DPB_HPD DPC_HPD CPU_EDP_HPD#

Rev1p2

DPC_HPD

1 2 3 4

8 7 6 5

B

RP51 100K_8P4R_5%

DPB_HPD

2

1

2 G

3

1

CPU_EDP_HPD#

2

@ RC82 0_0402_1% 1

PCH_TP_INT#

EDP_CPU_HPD

RC89 100K_0402_5%

S

1 D

TP_INT#

RP52 2.2K_8P4R_5%

CPU_DPB_AUX# CPU_DPB_AUX CPU_DPC_AUX CPU_DPC_AUX#

2

8 7 6 5

RC84 100K_0402_5%

@

+3VS

CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT

1 2 3 4

QC3 2N7002K_SOT23-3

1 RC367

2 0_0402_5%

@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

MCP(8,9/19) DDI,EDP,GPIO Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

10

of

55

5

4

3

2

1

WWW.AliSaler.Com

D

D

+1.05VS_PCH +1.05VS_PCH

1

1 HASWELL_MCP_E

UC1J

2

R2346 1K_0402_5%

Close to R2346 CC28 100P_0402_50V8J @ESD@

ESD solution

2 PCH_GPIO56 SLATE_MODE_R WL_OFF# PCH_GPIO44 PCH_GPIO47 PCH_GPIO48 PCH_GPIO49 TS_INT#

+3VS

2

1

RC11

DEVSLP0 10K_0402_5%

2

1

SIO_EXT_SCI# 100K_0402_5%

2

1

PCH_GPIO56 100K_0402_5%

RC98 RC9

@ @ @

T174 PAD~D T124 PAD~D T125 PAD~D TS_INT#

PCH_GPIO14 PCH_GPIO25

@ T126 PAD~D @ T127 PAD~D

PCH_GPIO46 +3V_DSW

PCH_GPIO9 EC_SCI# DEVSLP0

EC_SCI# DEVSLP0

2

1

RC105

GPIO27 10K_0402_5%

SIO_EXT_SCI# HDA_SPKR

HDA_SPKR

GPIO56 GPIO57 GPIO58 GPIO59 GPIO44 GPIO47 GPIO48 GPIO49 GPIO50 HSIOPC/GPIO71 GPIO13 GPIO14 GPIO25 GPIO45 GPIO46

AM3 AM2 P2 C4 L2 N5 V2

GSPI0_CS/GPIO83 GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86 GSPI1_CS/GPIO87 GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89 GSPI_MOSI/GPIO90 UART0_RXD/GPIO91 UART0_TXD/GPIO92 UART0_RTS/GPIO93 UART0_CTS/GPIO94 UART1_RXD/GPIO0 UART1_TXD/GPIO1 UART1_RST/GPIO2 UART1_CTS/GPIO3 I2C0_SDA/GPIO4 I2C0_SCL/GPIO5 I2C1_SDA/GPIO6 I2C1_SCL/GPIO7 SDIO_CLK/GPIO64 SDIO_CMD/GPIO65 SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69

GPIO

LPIO

GPIO9 GPIO10 DEVSLP0/GPIO33 SDIO_POWER_EN/GPIO70 DEVSLP1/GPIO38 DEVSLP2/GPIO39 SPKR/GPIO81

+3VALW_PCH

10 OF 19

1

2

1

RC116

FFS_INT2 LCD_CBL_DET#

JET@ RC112 10K_0402_5%

PAD~D T177 @ PAD~D T176 @ PAD~D T175 @

PAD~D T178 @ PAD~D T179 @

TOPAZ@ RC113 10K_0402_5%

PAD~D T180 @ PAD~D T181 @ FFS_INT2

+3VS UMA@ RC100 10K_0402_5%

SERIRQ 10K_0402_5% LCD_CBL_DET# 10K_0402_5% CPPE# 100K_0402_5% CPUSB# 100K_0402_5% FFS_INT2 100K_0402_5%

DIS@ RC99 10K_0402_5%

RC363 RC364

2 2

@ @

1 0_0402_5% 1 0_0402_5%

PCH_GPIO66

RC365 RC366

2 2

@ @

1 0_0402_1% 1 0_0402_1%

1

2

1

2

1

2

1

2

1

RC102 RC106 RC108

C

RC111 RC115 RP53

1 2 3 4

I2C1_SDA I2C1_SCL I2C0_SDA I2C0_SCL

I2C0_SDA I2C0_SCL I2C1_SDA I2C1_SCL

2

8 7 6 5 2.2K_0804_8P4R_5%

I2C1_SDA_PNL I2C1_SCL_PNL I2C1_SDA_TP I2C1_SCL_TP



KB_RST# 10K_0402_5%

2

1 RC109

TS_INT#

2

1 RC114

10K_0402_5%

Rev1p2

@

KB_DET# 10K_0402_5% PCH_GPIO44 10K_0402_5% SLATE_MODE_R 10K_0402_5% PCH_AUDIO_EN 10K_0402_5%

+3VS

+3VS

@ RC119 10K_0402_5%

2

B

+3VALW_PCH

PCH_GPIO66

BBS_BIT

@ RC120 1K_0402_5%

1

1

B

@ RC121 1K_0402_5%

2

@ RC122 1K_0402_5%

RC123 1K_0402_5%

2

HOST_ALERT1_R_N

HDA_SPKR

2

+3VS

+3VS

2

@ RC118 1K_0402_5%

1

2 RC110

PCH_GPIO83 PCH_GPIO84 PCH_GPIO85 BBS_BIT DGPU_PRSNT# Project_ID PCH_GPIO89 PCH_GPIO90 CPPE# CPUSB# PCH_GPIO93 PCH_GPIO94

+3VS

2

1

1

1

2 RC104

1

2 RC103

R6 L6 N6 L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4 F2 F3 G4 F1 E3 F4 D3 E4 C3 E2

1

C

WL_OFF#

AG6 AP1 AL4 AT5 AK4 AB6 U4 Y3 P3 Y2 AT3 AH4 AM4 AG5 AG3

+3VS

1

0_0402_1%

2 RC101 49.9_0402_1%

2

KB_DET#

1

1

CPU/ MISC

KB_RST# SERIRQ

2

BT_ON#2 @

H_THERMTRIP# KB_RST# SERIRQ PCH_OPI_COMP

1

WAKE_PCH#

1 RC38

D60 V4 T4 AW15 AF20 AB21

2

@ T182 PAD~D EC_LID_OUT#

THERMTRIP RCIN/GPIO82 SERIRQ PCH_OPI_RCOMP RSVD RSVD

1

BMBUSY/GPIO76 GPIO8 LAN_PHY_PWR_CTRL/GPIO12 GPIO15 GPIO16 GPIO17 GPIO24 GPIO27 GPIO28 GPIO26

2

P1 AU2 AM7 PCH_GPIO12 AD6 EC_LID_OUT# Y1 T3 ODD_DA# AD5 BT_ON# AN5 GPIO27 HOST_ALERT1_R_N AD7 AN3 KB_DET# PCH_AUDIO_EN

RP54

8 7 6 5

1 2 3 4

ODD_DA# BT_ON# WL_OFF# PXS_PWREN

GPIO66

PXS_PWREN

8.2K_8P4R_5%

GPIO86

GPIO15

TOP-BLOCK SWAP OVERRIDE

BOOT BIOS STRAP BIT BBS

HIGH depop RC288 (DEFAULT) LOW pop RC288

HIGH LOW(DEFAULT)

LPC SPI

GPIO81

TLS CONFIDENTIALITY

NO REBOOT STRAP

HIGH LOW(DEFAULT)

HIGH LOW(DEFAULT)

GPIO15 NOT Used +3VALW_PCH

1

1

+3VALW_PCH

RC125 10K_0402_5%

2

2

RC124 10K_0402_5%

PCH_GPIO46

PCH_GPIO9

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

MCP(10/19) GPIO,LPIO,MISC Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

11

of

55

5

4

3

2

1

WWW.AliSaler.Com

D

D

HASWELL_MCP_E

UC1K







C



10/100 LAN



NGFF WLAN



PEG_CRX_GTX_N1 PEG_CRX_GTX_P1 PEG_CTX_GRX_N1 PEG_CTX_GRX_P1 PEG_CRX_GTX_N2 PEG_CRX_GTX_P2 PEG_CTX_GRX_N2 PEG_CTX_GRX_P2 PEG_CRX_GTX_N3 PEG_CRX_GTX_P3 PEG_CTX_GRX_N3 PEG_CTX_GRX_P3

PCIE_PRX_LANTX_N3 PCIE_PRX_LANTX_P3 PCIE_PTX_LANRX_N3 PCIE_PTX_LANRX_P3 PCIE_PRX_WLANTX_N4 PCIE_PRX_WLANTX_P4 PCIE_PTX_WLANRX_N4 PCIE_PTX_WLANRX_P4

PEG_CTX_GRX_N0 PEG_CTX_GRX_P0

DIS@ CC18 1 DIS@ CC19 1

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

PEG_CTX_GRX_C_N0 PEG_CTX_GRX_C_P0

F8 E8

PEG_CRX_GTX_N1 PEG_CRX_GTX_P1 PEG_CTX_GRX_N1 PEG_CTX_GRX_P1

DIS@ CC20 1 DIS@ CC21 1

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

PEG_CTX_GRX_C_N1 PEG_CTX_GRX_C_P1

DIS@ CC22 1 DIS@ CC23 1

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

PEG_CTX_GRX_C_N2 PEG_CTX_GRX_C_P2

DIS@ CC24 1 DIS@ CC25 1

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

PEG_CTX_GRX_C_N3 PEG_CTX_GRX_C_P3

CC32 1 CC40 1

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

PCIE_PTX_LANRX_N3_C PCIE_PTX_LANRX_P3_C

C29 B30 F13 G13

PCIE_PRX_WLANTX_N4 PCIE_PRX_WLANTX_P4 PCIE_PTX_WLANRX_N4 PCIE_PTX_WLANRX_P4

B22 A21 G11 F11

PCIE_PRX_LANTX_N3 PCIE_PRX_LANTX_P3 PCIE_PTX_LANRX_N3 PCIE_PTX_LANRX_P3

B21 C21 E6 F6

PEG_CRX_GTX_N3 PEG_CRX_GTX_P3 PEG_CTX_GRX_N3 PEG_CTX_GRX_P3

B23 A23 H10 G10

PEG_CRX_GTX_N2 PEG_CRX_GTX_P2 PEG_CTX_GRX_N2 PEG_CTX_GRX_P2

C23 C22

CC36 1 CC41 1

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

PCIE_PTX_WLANRX_N4_C PCIE_PTX_WLANRX_P4_C

B29 A29 G17 F17 C30 C31 F15 G15 B31 A31

+1.05VS_AUSB3PLL

RC91 3.01K_0402_1% 1 2

@ T120PAD~D @ T121PAD~D PCH_PCIE_RCOMP

E15 E13 A27 B27

PERN5_L0 PERP5_L0

USB2N0 USB2P0

PETN5_L0 PETP5_L0

USB2N1 USB2P1

PERN5_L1 PERP5_L1

USB2N2 USB2P2

PETN5_L1 PETP5_L1

USB2N3 USB2P3

PERN5_L2 PERP5_L2

USB2N4 USB2P4

PETN5_L2 PETP5_L2

USB2N5 USB2P5

PERN5_L3 PERP5_L3

USB2N6 USB2P6

PETN5_L3 PETP5_L3

USB2N7 USB2P7

PERN3 PERP3 PETN3 PETP3

USB3RN1 USB3RP1 USB

PCIe

PERN4 PERP4

USB3TN1 USB3TP1 USB3RN2 USB3RP2

PETN4 PETP4

USB3TN2 USB3TP2

AN8 AM8

USB20_JUSB1_N0 USB20_JUSB1_P0

AR7 AT7

USB20_JUSB2_N1 USB20_JUSB2_P1

AR8 AP8

USB20_JUSB3_N2 USB20_JUSB3_P2

USB20_JUSB1_N0 USB20_JUSB1_P0



USB Conn JUSB1

USB20_JUSB2_N1 USB20_JUSB2_P1



USB Conn JUSB2

USB20_JUSB3_N2 USB20_JUSB3_P2



USB Conn JUSB3

AR10 AT10 AM15 AL15

USB20_MINI1_N4 USB20_MINI1_P4

AM13 AN13

USB20_TOUCH_N5 USB20_TOUCH_P5

AP11 AN11

USB20_CR_N6 USB20_CR_P6

AR13 AP13

USB20_CAM_N7 USB20_CAM_P7

G20 H20

USB3RN1_JUSB1 USB3RP1_JUSB1

C33 B34

USB3TN1_JUSB1 USB3TP1_JUSB1

E18 F18

USB3RN2_JUSB2 USB3RP2_JUSB2

B33 A33

USB3TN2_JUSB2 USB3TP2_JUSB2

AJ10 AJ11 AN10 AM10

USBRBIAS

USB20_MINI1_N4 USB20_MINI1_P4



USB20_TOUCH_N5 USB20_TOUCH_P5 USB20_CR_N6 USB20_CR_P6

Mini Card (WLAN)





USB20_CAM_N7 USB20_CAM_P7



USB3RN1_JUSB1 USB3RP1_JUSB1



Touch screen panel Card Reader Camera C

USB3TN1_JUSB1 USB3TP1_JUSB1



USB3RN2_JUSB2 USB3RP2_JUSB2



USB3TN2_JUSB2 USB3TP2_JUSB2



USB Conn JUSB1

USB Conn JUSB2

PERN1/USB3RN3 PERP1/USB3RP3 PETN1/USB3TN3 PETP1/USB3TP3

USBRBIAS USBRBIAS RSVD RSVD

PERN2/USB3RN4 PERP2/USB3RP4 PETN2/USB3TN4 PETP2/USB3TP4

OC0/GPIO40 OC1/GPIO41 OC2/GPIO42 OC3/GPIO43

RSVD RSVD PCIE_RCOMP PCIE_IREF

11 OF 19

PAD~D T118 @ PAD~D T119 @

1



PEG_CRX_GTX_N0 PEG_CRX_GTX_P0 PEG_CTX_GRX_N0 PEG_CTX_GRX_P0

RC90 22.6_0402_1%~D

AL3 AT1 AH2 AV3

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

USB_OC0# USB_OC1#

2



F10 E10

PEG_CRX_GTX_N0 PEG_CRX_GTX_P0



CAD NOTE: Route single-end 50-ohms and max 500-mils length. Avoid routing next to clock pins or under stitching capacitors. Recommended minimum spacing to other signal traces is 15 mils.

Rev1p2

@ B

B

+3VALW_PCH

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

1 2 3 4

8 7 6 5 RP55 10K_8P4R_5%

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

MCP(11/19) PCIE,USB Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

12

of

55

5

4

3

2

1

WWW.AliSaler.Com VCCST_PG_EC C79

ESD@

+1.35V

+CPU_CORE

1

C40

1 220P_0402_50V8J D

2

+1.35V

ESD solution

1

L59 J58

2

VCCST_PG_EC

VCCST_PG_EC

Define EC OD pin, need double confirm.

+VCCIO_OUT

2

+CPU_CORE

VCCSENSE T38

VR_ON C80

0.1U_0402_10V7K

2

R252 75_0402_5%

C

1

+VCCIOA_OUT

2

+1.05VS_PCH

1

SVID ALERT

VR_SVID_ALRT#

Place C80 close to R250.1

Place the PU resistors close to CPU

R254 43_0402_1% 2 1

VR_SVID_CLK

VR_ON H_VR_READY

H_CPU_SVIDALRT#

1

@

2 R248

1 1

@ @

2 R250 2 R251

RF@ C5212 68P_0402_50V8J

Place the PU resistors close to CPU

T39 T40 T41 T42 T43 T44 T45 T46 T47 T48 T49 T50 T51

H_CPU_SVIDCLK

1

2 +1.05VS_PCH

R256 130_0402_1%

@ @ @ @ @ @ @ @ @ @ @ @ @

2 1

1

2

2

1

2

1

2

C74 10U_0603_6.3V6M

2

1

C45 10U_0603_6.3V6M

2

1

C42 10U_0603_6.3V6M

2

1

C72 10U_0603_6.3V6M

2

B

1

C41 10U_0603_6.3V6M

CAD Note: PD resistor on HW side

2

1

C39 10U_0603_6.3V6M

VSSSENSE

2

1

C38 2.2U_0402_6.3V6M

+1.35V : 470UF/2V/7343 *2 (PWR) 10UF/6.3V/0603 * 6 2.2UF/6.3V/0402 * 4

1

VSSSENSE

2

CAD Note: PU resistor on HW side

1

C37 2.2U_0402_6.3V6M

VCC VCC VCC VCC VCC VCC

VDDQ DECOUPLING

@ R255 10K_0402_5%

C36 2.2U_0402_6.3V6M

VCCSENSE

VCCST VCCST VCCST

C

+1.35V

C35 2.2U_0402_6.3V6M

VSS PWR_DEBUG VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

@

1

R1 100_0402_1%

HSW ULT POWER

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

Rev1p2

R253 INTEL Check list , XDP use only

CPU_PWR_DEBUG#

+CPU_CORE

VCCSENSE

D63 H59 P62 P60 P61 N59 N61 T59 AD60 AD59 AA59 AE60 AC59 AG58 U59 V59

AB57 AD57 AG57 C24 C28 C32

1

2

@ R253 150_0402_1%

12 OF 19

VIDALERT VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY

H_CPU_SVIDDATA

+1.05VS_PCH

B

VCC_SENSE RSVD VCCIO_OUT VCCIOA_OUT RSVD RSVD RSVD

AC22 AE22 AE23

+CPU_CORE

2

@ R257 0_0402_1% 2 1

VR_SVID_DAT

1

0_0402_1% 0_0402_1%

VCC RSVD RSVD

E63 AB23 A59 E20 AD23 AA23 AE59 L62 N63 L63 B59 F60 C59

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDATA VCCST_PG_EC VR12.5_VR_ON_R VR_READY_R CPU_PWR_DEBUG#

RF SVID DATA

0_0402_1%

CPU_PWR_DEBUG#

+1.05VS_PCH

SVID_DAT need to pull-up double side ( PWR_VR & CPU )

@

+VCCIO_OUT_R ESD@

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

F59 N58 AC58

1

R245 @ 0_0603_5%

D

RSVD RSVD

AH26 AJ31 AJ33 AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

R286 10K_0402_5%

+CPU_CORE

HASWELL_MCP_E

UC1L

22U_0603_6.3V6M @ESD@

+1.05VS_PCH

Place C79 between R286 and UC1

2

2

R2 100_0402_1%

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

MCP(12/19) Power Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

13

of

55

5

4

3

2

1

WWW.AliSaler.Com +1.05VS_PCH +1.05VS_PCH

+CPU_CORE C46

+

2

2

22U_0603_6.3V6M @ESD@ C47 1 2

@ESD@

@ESD@

2

Close to N8 C57 @1

+1.05VS_PCH

1

CD65 330U_D3_2.5VY_R6M

+

CD63 330U_D3_2.5VY_R6M

1

D

1

D

22U_0603_6.3V6M @ESD@

2 1U_0402_6.3V6K

ESD solution +RTCVCC

2

C58 C59

1 1

2 1U_0402_6.3V6K 2 100U_1206_6.3V6M

2.2UH_LQM2MPN2R2NG0L_30%

HASWELL_MCP_E

UC1M

+1.05VS_ASATA3PLL

L21

2

C63 C65

K9 L10 M9 N8 P9 B18 B11

+1.05VS_PCH

1 1

2 1U_0402_6.3V6K 2 100U_1206_6.3V6M

+1.05VS_PCH

2.2UH_LQM2MPN2R2NG0L_30%

+1.05VS_AUSB3PLL +1.05VS_ASATA3PLL

+1.05VS_APLLOPI R267 0_0805_1% 1 2 @ C69 2 L31 @ C70 2.2UH_LQM2MPN2R2NG0L_30%

1 @1

2 1U_0402_6.3V6K 2 100U_1206_6.3V6M

Y20 AA21 W21

+1.05VS_APLLOPI

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL RSVD VCCAPLL VCCAPLL

VCCSUS3_3 VCCRTC DCPRTC

RTC

VCCSPI

OPI

VCCASW VCCASW

1 1

C83 C84

2 L4 1 2.2UH_LQM2MPN2R2NG0L_30%

C

2 1U_0402_6.3V6K 2 100U_1206_6.3V6M

1

C92

@

1 RC142

2 1U_0402_6.3V6K 2 100U_1206_6.3V6M

J13

DCPSUS3

AH14

1

2

@

1 RC143 AH13

VCCHDA DCPSUS2

VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 DCPSUSBYP DCPSUSBYP VCCASW VCCASW VCCASW DCPSUS1 DCPSUS1

AXALIA/HDA

VRM/USB2/AZALIA CORE

@2 1U_0402_6.3V6K +3VALW_PCH +3V_DSW +3VS

AC9 AA9 AH10 V8 W9

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

GPIO/LCC

THERMAL SENSOR

+1.5VS

+3VS

+3VALW_PCH

+VCCHDA

RC127

1

2 0_0402_5%

RC128

1

@

2 0_0402_5%

RC129

1

@

2 0_0402_5%

C77

+VCCHDA

1

+1.05VS_AXCK_DCB +1.05VS_AXCK_LCPLL +1.05VS_PCH +1.05VS_PCH

2 0.1U_0402_10V7K

Reserve for HDA issue, C77 close to AH14

+3VALW_PCH

J18 K19 A20 J17 R21 T21 K18 M20 V21 AE20 AE21

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD VCCSUS3_3 VCCSUS3_3

SDIO/PLSS

C50 C53

1 1

2 1U_0402_6.3V6K 2 1U_0402_6.3V6K

+3V_DSW

C81

1

2 1U_0402_6.3V6K

Close to AH10

+3VALW_PCH

C78

1

2 22U_0603_6.3V6M

Close to AC9/AA9/AE20/AE21

+3VS

C82

1

2 22U_0603_6.3V6M

Close to V8

+1.05VS_PCH

C87

1

2 1U_0402_6.3V6K

Close to J17

+1.05VS_PCH

C88

1

2 1U_0402_6.3V6K

Close to R21

C75

2

1 0.1U_0402_10V7K

Close to AH14

B

+3VALW_PCH

1

@

1 R264

+3VALW_PCH

2 1U_0402_6.3V6K

2

2

1

2

+RTCVCC C52 1

+VCCRTCEXT

Y8

C68 1

@

2 0.1U_0402_10V7K

2 0.1U_0402_10V7K

AG14 AG13

VCCTS1_5 VCC3_3 VCC3_3

VCCSDIO VCCSDIO

+1.05VS_PCH

+1.05VS_PCH

J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8 AD10 AD8 J15 K14 K16

C60 C61 C62

1 1 1

2 10U_0603_6.3V6M 2 1U_0402_6.3V6K 2 1U_0402_6.3V6K

C66 C67

1 1

RC137

1 C93

@ 1

C71 1

2 22U_0603_6.3V6M 2 1U_0402_6.3V6K

ESD solution

+1.05VS_PCH

USB2

DCPSUS4 RSVD VCC1_05 VCC1_05

+1.35V C43

1

2

22U_0603_6.3V6M ESD@

+1.5VS +3VS

ESD solution U8 T9

C73 1

2

1U_0402_6.3V6K

+3VS +PCH_VCCDSW

SUS OSCILLATOR

C

+1.05VS_PCH

2 0_0402_5% +1.05VS_PCH 2 1U_0402_6.3V6K @

2 0.1U_0402_10V7K

2

22U_0603_6.3V6M @ESD@ C64 1U_0402_6.3V6K 1 2

+PCH_VCCDSW

@

+3VS C44

1

+1.05VS_PCH

+3V_DSW

LPT LP POWER

13 OF 19

+1.05VS_PCH

C51

USB3

@2 1U_0402_6.3V6K

0_0402_5% C91

1 1

C85 C86

2 L5 1 2.2UH_LQM2MPN2R2NG0L_30%

2

+VCCHDA +1.05VS_PCH

+1.05VS_AXCK_LCPLL

0_0402_5%

AH11 AG10 AE7

1

+3VALW_PCH SPI

+1.05VS_AXCK_DCB +1.05VS_PCH

2

0_0603_1% mPHY

1

0.1U_0402_10V7K C56

L11

0.1U_0402_10V7K C55

+1.05VS_AUSB3PLL

1U_0402_6.3V6K C54

+1.05VS_PCH

AB8

RC136

1

AC20 AG16 AG17

C5215

2 0_0402_5% @ +1.05VS_PCH 2 1U_0402_6.3V6K C90 @1 2 47U_0603_2.5V7 CC37 @1 2 47U_0603_2.5V7 CC38 @1

1

0.47U_0402_6.3V6K @

+1.05VS_PCH C76 1

2

Reserve for inrush current issue

2

1U_0402_6.3V6K

Rev1p2

@

Close to K9,M9 B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

MCP(13/19) Power Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

14

of

55

5

4

3

2

1

WWW.AliSaler.Com

D

D

B

UC1O

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

14 OF 19

AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20

AP22 AP23 AP26 AP29 AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49 AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63 AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

HASWELL_MCP_E

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 15 OF 19 Rev1p2 VSS

UC1P

AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31

D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49 D5 D50 D51 D53 D54 D55 D57 D59 D62 D8 E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61 G18 G22 G3 G5 G6 G8 H13

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

HASWELL_MCP_E

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_SENSE 16 OF 19 Rev1p2 VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

C

V58 AH46 V23 E62 AH16

VSSSENSE

1

C

HASWELL_MCP_E

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

X@ RC163 100_0402_1%

@

2

UC1N

A11 A14 A18 A24 A28 A32 A36 A40 A44 A48 A52 A56 AA1 AA58 AB10 AB20 AB22 AB7 AC61 AD21 AD3 AD63 AE10 AE5 AE58 AF11 AF12 AF14 AF15 AF17 AF18 AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57 AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

B

CAD Note: RC163 SHOULD BE PLACED CLOSE TO CPU

@

Rev1p2

@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

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Date:

2

MCP(14,15,16/19) VSS Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

15

of

55

5

4

3

2

1

WWW.AliSaler.Com

D

D

HASWELL_MCP_E

UC1Q DC_TEST_AY2_AW2 DC_TEST_AY3_AW3 DC_TEST_AY60 DC_TEST_AY61_AW61 DC_TEST_AY62_AW62 TP_DC_TEST_B2 DC_TEST_A3_B3 DC_TEST_A61_B61

@ T166PAD~D @ T167PAD~D

DC_TEST_B62_B63 DC_TEST_C1_C2

AY2 AY3 AY60 AY61 AY62 B2 B3 B61 B62 B63 C1 C2

DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_AY60 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_C2

HASWELL_MCP_E

UC1R

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4 DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62 DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3 DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63 17 OF 19 Rev1p2

A3 A4

DC_TEST_A3_B3 DC_TEST_A4

A60 A61 A62 AV1 AW1 AW2 AW3 AW61 AW62 AW63

DC_TEST_A60 DC_TEST_A61_B61 DC_TEST_A62 DC_TEST_AV1 DC_TEST_AW1 DC_TEST_AY2_AW2 DC_TEST_AY3_AW3 DC_TEST_AY61_AW61 DC_TEST_AY62_AW62 DC_TEST_AW63

RSVD RSVD RSVD RSVD

PAD~D T168 @ PAD~D T169 @ PAD~D T170 @ PAD~D T171 @ PAD~D T172 @

@ T128 PAD~D @ T132 PAD~D @ T134 PAD~D @ T135 PAD~D

AT2 RSVD_AT2 RSVD_AU44 AU44 RSVD_AV44 AV44 D15 RSVD_D15

@ T138 PAD~D @ T140 PAD~D @ T143 PAD~D

RSVD_F22 RSVD_H22 RSVD_J21

F22 H22 J21

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

RSVD RSVD RSVD

PAD~D T173 @ 18 OF 19

@

N23 R23 T23 U10

RSVD_N23 RSVD_R23 RSVD_T23 RSVD_U10

PAD~D PAD~D PAD~D PAD~D

@ T129 @ T130 @ T131 @ T133

AL1 AM11 AP7 AU10 AU15 AW14 AY14

RSVD_AL1 RSVD_AM11 RSVD_AP7 RSVD_AU10 RSVD_AU15 RSVD_AW14 RSVD_AY14

PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D

T136 T137 T139 T141 T142 T144 T145

@ @ @ @ @ @ @

Rev1p2

@

C

C

UC1S

HASWELL_MCP_E

CFG STRAPS for CPU

B



CFG16 CFG18 CFG17 CFG19

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

AC60 AC62 AC63 AA63 AA60 Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60

CFG16 CFG18 CFG17 CFG19

AA62 U63 AA61 U62

CFG_RCOMP

V63

@ T159PAD~D

A5

@ T161PAD~D @ T163PAD~D @ T164PAD~D @ T165PAD~D TDI_IREF

E1 D1 J20 H18 B12

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD_TP RSVD_TP RESERVED

RSVD_TP RSVD RSVD RSVD PROC_OPI_RCOMP

CFG16 CFG18 CFG17 CFG19

RSVD RSVD

CFG_RCOMP

VSS VSS

RSVD RSVD RSVD

RSVD RSVD RSVD RSVD TD_IREF 19 OF 19

AV63 AU63

PAD~D T146 @ PAD~D T147 @

C63 C62 B43

PAD~D T148 @ PAD~D T149 @ PAD~D T150 @

A51 B51

PAD~D T151 @ PAD~D T152 @

L60

PAD~D T153 @

N60

PAD~D T154 @

CFG4

W23 Y22 AY15

1

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

RC138 1K_0402_1%

2











B

PAD~D T155 @ PAD~D T156 @

Display Port Presence Strap

PROC_OPI_RCOMP

AV62 D58

PAD~D T157 @ PAD~D T158 @

1: Disabled; No Physical Display Port attached to Embedded Display Port 0: Enabled; An external Display Port device is connected to the Embedded Display Port

CFG4

P22 N21 P20 R20

PAD~D T160 @ PAD~D T162 @

Rev1p2

@

2

1

1

2

RC132 RC133

CFG_RCOMP 49.9_0402_1% TDI_IREF 8.2K_0402_1%

PROC_OPI_RCOMP 1 49.9_0402_1%

2 RC134

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

MCP(17,18,19/19) CFG,RSVD Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

16

of

55

5

4

3

2

1

WWW.AliSaler.Com H=4mm

+DIMM1_VREF_DQ +1.35V

+1.35V

2-3A to 1 DIMMs/channel

JDIMM1

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_DQS#[0..7]

DDR_A_D[0..63]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

DDR_A_D10 DDR_A_D11

All VREF traces should have 10 mil trace width

DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

Layout Note: Place near JDIMM1

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

+1.35V

2

1

2

CD11 1U_0402_6.3V6K

2

1

CD10 1U_0402_6.3V6K

2

1

CD9 1U_0402_6.3V6K

2

1

CD8 1U_0402_6.3V6K

2

1

CD7 1U_0402_6.3V6K

2

1

CD6 1U_0402_6.3V6K

1

CD5 1U_0402_6.3V6K

2

CD4 1U_0402_6.3V6K

1

C

DDR_CKE0_DIMMA

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1

+1.35V

2

2

1

2

+

2

CD15 330U_D3_2.5VY_R6M

2

1

1 CD14

2

1

10U_0603_6.3V6M CD13

2

1@

10U_0603_6.3V6M CD20

2

1

10U_0603_6.3V6M CD19

1

10U_0603_6.3V6M CD18

1@

10U_0603_6.3V6M CD12

10U_0603_6.3V6M CD17

2

10U_0603_6.3V6M CD16

10U_0603_6.3V6M

1



M_CLK_DDR0 M_CLK_DDR#0

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_BS0



DDR_A_WE# DDR_A_CAS#

DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDR_CS1_DIMMA#

DDR_CS1_DIMMA#

DDR_A_D40 DDR_A_D41

B

DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49

+0.675VS

DDR_A_DQS#6 DDR_A_DQS6

2

1

2

CD29 10U_0603_6.3V6M

2

1

CD28 10U_0603_6.3V6M

2

1

CD27 0.1U_0402_10V7K

2

1

CD26 0.1U_0402_10V7K

1

CD25 0.1U_0402_10V7K

2

CD24 0.1U_0402_10V7K

1

DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59 RD61

2 10K_0402_5%

1

+3VS

2

1

2

@

1

2

CD31 0.1U_0402_10V7K

10K_0402_5%

CD30 2.2U_0402_6.3V6M

RD7

+0.675VS

205 207

GND1 BOSS1

GND2 BOSS2

1 2

DDR3_DRAMRST# DDR_A_D14 DDR_A_D15

1

DDR_A_D20 DDR_A_D21

2

DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3

1

DDR3_DRAMRST#

2

DDR3_DRAMRST#_CPU

@ RD5 0_0402_1%

@ESD@ CD3 0.1U_0402_10V7K

CAD NOTE PLACE THE CAP NEAR TO DIMM RESET PIN

DDR_A_D30 DDR_A_D31

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

DDR_CKE1_DIMMA

DDR_CKE1_DIMMA

C

DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 M_ODT DDR_A_MA6 DDR_A_MA4

CD64 ESD@

DDR_A_MA2 DDR_A_MA0

0.1U_0402_10V7K

M_CLK_DDR1 M_CLK_DDR#1 DDR_A_BS1 DDR_A_RAS#

DDR_A_BS1

DDR_A_RAS#

DDR_CS0_DIMMA# M_ODT0

DDR_CS0_DIMMA#

+5VALW

QD2 BSS138-G_SOT23-3

1

3

DDR_A_D38 DDR_A_D39

1

2

1

2

1 R2348 1 R2349 1 R2350 1 R2352

M_ODT

R2347 220K_0402_5%~D

+SM_VREF_CA_DIMM

1

2

+1.35V

M_ODT1

DDR_A_D36 DDR_A_D37

1

Place CC31 between QD2 and R2349

DDR3L SODIMM ODT GENERATION

M_CLK_DDR1

M_CLK_DDR#1

CD22 0.1U_0402_10V7K

DDR_A_D34 DDR_A_D35

Layout Note: Place near JDIMM1.203,204

CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT

RD3 470_0402_5%

DDR_A_D12 DDR_A_D13

CD21

DDR_A_DQS#4 DDR_A_DQS4

CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT

DDR_A_D6 DDR_A_D7

2.2U_0402_6.3V6M

DDR_A_D32 DDR_A_D33

73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

D

+1.35V DDR_A_DQS#0 DDR_A_DQS0

S

DDR_A_D8 DDR_A_D9

DDR_A_D4 DDR_A_D5

D

DDR_A_D2 DDR_A_D3

VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS

2 G

2

VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS

1

2

1

DDR_A_D0 DDR_A_D1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

2

2

1

CD2 0.1U_0402_10V7K

Populate RD1, De-Populate RD7 for Intel DDR3 VREFDQ multiple methods M1 Populate RD7, De-Populate RD1 for Intel DDR3 VREFDQ multiple methods M3

CD1 2.2U_0402_6.3V6M

@ RD1 0_0402_1%

D

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

@ RD4 0_0402_1%

2

+SM_VREF_DQ0_DIMM1

2

@ R2351 2M_0402_5%

2 M_ODT0 66.5_0402_1% 2 M_ODT1 66.5_0402_1% 2 66.5_0402_1% 2 66.5_0402_1%

0.675V_DDR_VTT_ON

0.675V_DDR_VTT_ON

M_ODT2

M_ODT3



1

1

DDR_A_D44 DDR_A_D45 B

DDR_A_DQS#5 DDR_A_DQS5 +1.35V

DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53

U2303

1

DDR_PG_CTRL

2 3

DDR_A_D54 DDR_A_D55

NC

VCC

A Y

1

5 4

@ CD23 0.1U_0402_10V7K 2

0.675V_DDR_VTT_ON

GND 74AUP1G07GW_TSSOP5

DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63

DDR_XDP_WLAN_TP_SMBDAT DDR_XDP_WLAN_TP_SMBCLK



+0.675VS

206 208

BELLW_80001-1021 CONN@

A

A

+1.35V

+3VS CD62 1 2

22U_0603_6.3V6M ESD@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

ESD solution

2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

DDRIII DIMMA Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

17

of

55

5

4

3

2

1

WWW.AliSaler.Com +DIMM2_VREF_DQ

H=4mm

+1.35V

+1.35V

JDIMM2 +SM_VREF_DQ1_DIMM2

1

2

Populate RD4, De-Populate RD8 for Intel DDR3 VREFDQ multiple methods M1 Populate RD8, De-Populate RD4 for Intel DDR3 VREFDQ multiple methods M3

2

1

2

CD33 0.1U_0402_10V7K

1

CD32 2.2U_0402_6.3V6M

@ RD8 0_0402_1% D

DDR_B_D23 DDR_B_D17

DDR_B_D21 DDR_B_D18 DDR_B_D3 DDR_B_D2 DDR_B_DQS#0 DDR_B_DQS0



DDR_B_DQS#[0..7]

DDR_B_D0 DDR_B_D1

All VREF traces should have 10 mil trace width

DDR_B_D[0..63]

DDR_B_DQS[0..7]

DDR_B_MA[0..15]

DDR_B_D12 DDR_B_D8 DDR_B_DQS#1 DDR_B_DQS1

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

Layout Note: Place near JDIMM2

DDR_B_D14 DDR_B_D15 DDR_B_D31 DDR_B_D25

DDR_B_D27 DDR_B_D24 +1.35V

2

1

2

CD42 1U_0402_6.3V6K

2

1

CD41 1U_0402_6.3V6K

2

1

CD40 1U_0402_6.3V6K

2

1

CD39 1U_0402_6.3V6K

2

1

CD38 1U_0402_6.3V6K

2

1

CD37 1U_0402_6.3V6K

1

CD36 1U_0402_6.3V6K

2

CD35 1U_0402_6.3V6K

1 C

DDR_CKE2_DIMMB

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1

+1.35V

2

1

2

1

2

1 +

2

CD51 330U_D3_2.5VY_R6M

2

1

CD50 10U_0603_6.3V6M

1

CD49 10U_0603_6.3V6M

2

@

CD48 10U_0603_6.3V6M

2

1

CD47 10U_0603_6.3V6M

2

1

CD46 10U_0603_6.3V6M

@

1

CD45 10U_0603_6.3V6M

CD44 10U_0603_6.3V6M

2

CD43 10U_0603_6.3V6M

1

M_CLK_DDR2 M_CLK_DDR#2

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_BS0



DDR_B_WE# DDR_B_CAS#

DDR_B_MA10 DDR_B_BS0 DDR_B_WE# DDR_B_CAS# DDR_B_MA13 DDR_CS3_DIMMB#

DDR_CS3_DIMMB#

DDR_B_D36 DDR_B_D38

Layout Note: Place near JDIMM2.203,204

DDR_B_D40 DDR_B_D45

B

DDR_B_D43 DDR_B_D42 DDR_B_D52 DDR_B_D49

+0.675VS

DDR_B_DQS#6 DDR_B_DQS6

2

1

2

CD59 10U_0603_6.3V6M

2

1

CD58 10U_0603_6.3V6M

2

1

CD57 0.1U_0402_10V7K

2

1

CD56 0.1U_0402_10V7K

2

1

CD55 0.1U_0402_10V7K

CD54 0.1U_0402_10V7K

1

DDR_B_D50 DDR_B_D53 DDR_B_D63 DDR_B_D62

DDR_B_D58 DDR_B_D59

+0.675VS

2

@

1

2

CD61 0.1U_0402_10V7K

1

CD60 2.2U_0402_6.3V6M

2

+3VS 1 10K_0402_5%

RD13 10K_0402_5%

2 RD12

1

+3VS

205

VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2

G1

G2

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

2-3A to 1 DIMMs/channel DDR_B_D22 DDR_B_D16 DDR_B_DQS#2 DDR_B_DQS2

D

DDR_B_D19 DDR_B_D20 DDR_B_D4 DDR_B_D5 DDR3_DRAMRST# DDR_B_D6 DDR_B_D7 DDR_B_D13 DDR_B_D9

DDR_B_D11 DDR_B_D10 DDR_B_D30 DDR_B_D26 DDR_B_DQS#3 DDR_B_DQS3

DDR3_DRAMRST#

1

2

@ESD@ CD34 0.1U_0402_10V7K

CAD NOTE PLACE THE CAP NEAR TO DIMM RESET PIN

DDR_B_D29 DDR_B_D28

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14

C

DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 M_ODT3

M_CLK_DDR3

M_CLK_DDR#3

DDR_B_BS1

DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2 M_ODT3



+SM_VREF_CA_DIMM

1 DDR_B_D33 DDR_B_D34

1 DDR_B_D39 DDR_B_D37

2

1

2

CD53 0.1U_0402_10V7K

DDR_B_DQS#4 DDR_B_DQS4

73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

CD52 2.2U_0402_6.3V6M

DDR_B_D32 DDR_B_D35

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

2 @ RD10 0_0402_1%

DDR_B_D44 DDR_B_D41 DDR_B_DQS#5 DDR_B_DQS5

B

DDR_B_D47 DDR_B_D46 DDR_B_D51 DDR_B_D55

DDR_B_D48 DDR_B_D54 DDR_B_D56 DDR_B_D57 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D60 DDR_B_D61

DDR_XDP_WLAN_TP_SMBDAT DDR_XDP_WLAN_TP_SMBCLK



+0.675VS

206

BELLW_80011-1021 CONN@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

DDRIII DIMMB Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

18

of

55

5

4

3

2

1

WWW.AliSaler.Com

D

D

UG1

GCLK@

UG1

@

SLG3NB3375VTR TQFN 16P CRYSTAL SLG3NB3374VTR TQFN 16P CRYSTAL

SLG3NB3374V is for DIS by output 24M*1,25M*1, 27M*1, 32K*1 SLG3NB3375V is for UMA by output 24M81, 25M*1, 32K*1 +RTCVCC

+RTCBATT

+3VLP

+3VALW

CG4

2

1 RG2 @ 0_0402_5%

2

GCLK@

1

0.1U_0402_10V7K

CG3

2

GCLK@

1 0.1U_0402_10V7K

CG2

2

0.1U_0402_10V7K

C

1 GCLK@

CG10 CG5 22U_0805_6.3V6M

2

GCLK@

1 1 2 UG1 GCLK_VRTC

Place close to UG1.8

10 15

+3VLP

2

+3VALW

2

VBAT

VDD_RTC_OUT

3 CG9 2

25MHz_A

VDDIO_25M_B

25MHz_B

XTAL_IN XTAL_OUT

GCLK@ 1

OSC OSC

GCLK@

GND GND

4 7 13

YG1

1

27MHz

VDDIO_25M_A

GCLK@ 1

15P_0402_50V8J

PCH_RTCX1_R

SLG3NB274VTR_TQFN16_2X3

RG3

1

2

CPU_RTC 32.768k(P.8) Place RG3 close to YC1

GCLK@

PCH_RTCX1

12 6

LAN_X1_R

RG5

1

5

PCH_X1_R

RG6

1

2 33_0402_5%

1

XTLI_R RG8

GCLK@

2 22_0402_5% GCLK@

XTAL24_IN

CPU_CLK 24M(P.9) Place RG6 close to YC2

GND4

CLK_X1 CLK_X2 CLK_X1 CG8 2

1 16

VDDIO_27M

GND1 GND2 GND3

3

+1.05VS_PCH

9

0_0402_5%

VDD

1

2

GCLK@ CG7 5P_0402_50V8C

2 GCLK@

XTLI

0_0402_5%

LAN 25M(P.21) Place RG8 close to YL2

RG3,RG8, RG6 0ohm_0402 for isolated CLK tail

17

8

+LAN_VDD33

RTC_VOUT

C

GCLK@

+V3.3A 32kHz

11

14

2.2U_0603_6.3V6K CG6

0.1U_0402_10V7K

1 GCLK@

2

+LAN_VDD33

RG1 330_0402_5% GCLK@

2

+1.05VS_PCH

1

1

+RTCVCC

RG4 330_0402_5% @

2 @

4

25MHZ_10PF_7V25000014 CLK_X2

12P_0402_50V8J

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

Green CLK Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

19

of

55

5

4

3

2

1

WWW.AliSaler.Com

Place close to JHDMI

D

D

+VDISPLAY_VCC

DDI1_LANE_N1 DDI1_LANE_P1



DDI1_LANE_N0 DDI1_LANE_P0

CX14 2 CX15 2

1 0.1U_0402_10V7K 1 0.1U_0402_10V7K

TMDS_TX0N TMDS_TX0P

CX16 2 CX17 2

1 0.1U_0402_10V7K 1 0.1U_0402_10V7K

TMDS_TX1N TMDS_TX1P

CX18 2 CX19 2

1 0.1U_0402_10V7K 1 0.1U_0402_10V7K

TMDS_TX2N TMDS_TX2P

TMDS_TXCP

4

4 LX2

3

3

1

FX1 1.5A_6V_1206L150PR~D

TMDS_L_TXCP

EMI@

+3VS

1

2

10U_0603_6.3V6M



TMDS_TXCN TMDS_TXCP

2

+5VS

0.1U_0402_16V7K

DDI1_LANE_N2 DDI1_LANE_P2

1 0.1U_0402_10V7K 1 0.1U_0402_10V7K

W=40mils TMDS_L_TXCN

1 CX22

2

1



CX12 2 CX13 2

WCM-2012HS-900T_4P 2 1 2

TMDS_TX0N

1

TMDS_TX0P

4

WCM-2012HS-900T_4P 2 1 2

RX12 10K_0402_5% TMDS_L_TX0N

2

DDI1_LANE_N3 DDI1_LANE_P3

1

CX21



TMDS_TXCN

4 3 2 1

1 2 3 4

JHDMI RP58 680_8P4R_5%

4 LX3

3

3

TMDS_L_TX0P

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

HDMI_HPLUG

EMI@ CPU_DPB_CTRLDAT_R CPU_DPB_CTRLCLK_R

5 6 7 8

8 7 6 5

RP59 680_8P4R_5%

TMDS_L_TXCN

1

+3VS

TMDS_TX1N

1

TMDS_TX1P

4

D

C

1

2

WCM-2012HS-900T_4P 2 1 2

4 LX4

3

3

TMDS_L_TX1N

TMDS_L_TXCP TMDS_L_TX0N

TMDS_L_TX1P

TMDS_L_TX0P TMDS_L_TX1N

EMI@

TMDS_L_TX1P TMDS_L_TX2N

QX3 2N7002K_SOT23-3

G

TMDS_L_TX2P

S

20 21 22 23

C

3

RX13 100K_0402_5%

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

2

CONCR_099ATAC19NBLCNF CONN@ LX5 TMDS_TX2P

4

TMDS_TX2N

1

EMI@

4

3

1

2

3

TMDS_L_TX2P

2

TMDS_L_TX2N

46@

ROYALTY HDMI W/LOGO

Part Number

WCM-2012HS-900T_4P

RO0000002HM

TMDS_L_TXCN

@EMI@

CX23

1

2 3.3P_0402_50V8C

TMDS_L_TXCP

@EMI@

CX24

1

2 3.3P_0402_50V8C

TMDS_L_TX0N

@EMI@

CX25

1

2 3.3P_0402_50V8C

TMDS_L_TX0P

@EMI@

CX26

1

2 3.3P_0402_50V8C

TMDS_L_TX1N

@EMI@

CX27

1

2 3.3P_0402_50V8C

TMDS_L_TX1P

@EMI@

CX28

1

2 3.3P_0402_50V8C

TMDS_L_TX2N

@EMI@

CX29

1

2 3.3P_0402_50V8C

TMDS_L_TX2P

@EMI@

CX30

1

2 3.3P_0402_50V8C

Description HDMI W/Logo:RO0000002HM

+5VS

B

B

2

2

+3VS

1

+3VS

G

2

RX17 2.2K_0402_5%

1

RX16 2.2K_0402_5% QX4B DMN66D0LDW-7_SOT363-6 CPU_DPB_CTRLCLK_R

1

S

6 D

1

CPU_DPB_CTRLCLK

5

C

3

2 B

QX5 MMBT3904_NL_SOT23-3

G

4

CPU_DPB_CTRLDAT_R

3

D

CPU_DPB_CTRLDAT

S

QX4A DMN66D0LDW-7_SOT363-6

1

2

RX15 150K_0402_5%

DPB_HPD

HDMI_HPLUG

1

1

E

2

@ RX34 20K_0402_5%

CX20 220P_0402_50V8J

2

2

RX14 100K_0402_5%

1

A

A

Compal Secret Data

Security Classification Issued Date

2014/01/20

Deciphered Date

2015/01/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

WWW.AliSaler.Com 3

Date:

2

Compal Electronics, Inc. HDMI Document Number

Rev 1.0

LA-B012P Tuesday, August 05, 2014 1

Sheet

20

of

55

1

2

3

4

5

WWW.AliSaler.Com +LAN_IO rising time : >1ms and