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MODEL NAME : VAW11 PROJECT CODE : ANRVAW1100 PCB NO : LA-9102P (Mars Pro) DA60000UU00 LA-9102P M/B DA40001G400 LS-9105P POWER BUTTON/B DA40001FP00 LS-9102P USB/B DA40001FQ00 LS-9103P TP BUTTON/B DA40001FR00 LS-9104P ODD/B

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ｗｗｗ．６６６ｆｉｘ．ｃｏｍ好修网

Dell / Compal Confidential Schematic Document

2

2

Intel Chief River Ivy Bridge(BGA) + Panther Point OAK 17" UMA/DIS AMD Mars Pro 2012-09-25 Rev: 1.0

3

46@ : for 46 level @ : Nopop Component CONN@ : Connector Component KB9012@ : ENE KB9012 Implemented UMA@ : Only for UMA EMC@ : EMI/ESD parts 4

i3R1@ : CPU i3-3217 1.8G i3VOSR1@ : CPU i3-2365 1.4G i5R1@ : CPU i5-3317 1.7G i7R1@ : CPU i7-3517 1.9G CELR1@ : CPU Celeron 887 1.5G PENR1@ : CPU Pentium 997 1.6G

R1@ : R1 P/N R3@ : R3 P/N

GCLK@ : Green CLK implemented GCLKUMA@ : Green CLK for UMA GCLKDIS@ : Green CLK for DIS XTAL@ : X'tal implemented XTALDIS@ : X'tal with DIS implemented A

B

3

ZZZ

R1@

ZZZ

R3@

PCB 0T3 LA-9102P REV0 M/B

PCB-MB

DA60000UU00

DA80000R911

4

Compal Secret Data

Security Classification Issued Date

DIS@ : Only for Discrete TH@/THR1@ : Thames-XT MS@/MSR1@ : Mars Pro X76@ : SPI-ROM & VRAM Group

2012/09/25

Deciphered Date

2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C

D

Title

Compal Electronics, Inc. Cover Page

Size Document Number Custom

Rev 1.0

LA-9102P

Date:

Tuesday, September 25, 2012 E

Sheet

1

of

57

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ｗｗｗ．６６６ｆｉｘ．ｃｏｍ好修网 64M*16

P.40

VRAM * 4 VRAM * 4 P.30 P.30 DDR3 DDR3 1

Intel Ivy Bridge Processor

64bit

64M*16

AMD Thames-XT 24-26 W P.24~29

VRAM * 4 P.31 DDR3 128M*16

64bit

VRAM * 4 P.31 DDR3

CPU XDP Conn. P.6

Fan Control

128M*16

PEG 2.0 x8

Memory Bus (DDR3)

DDRIII-DIMM X2

Dual Channel

1

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 P.11~12

1.5V DDR3 1333 MHz

17W DC 8GB Max

BGA 1023 P.5~10

AMD Mars Pro, 128b, Radeon HD8650M, P7000-P8000 1GB DDR3 (8-64Mx16), 2GB DDR3 (8-128Mx16)

FDI x8

DMI x4

100MHz 2.7GT/s

100MHz 5GB/s

SATA3.0

Port 0

SATA HDD Conn.

LVDS

P.41

LVDS Conn.

P.21

Port 2

HDMI

SATA ODD Conn.

P.41

Daughter board

HDMI Conn.

2

2

P.22

Intel Panther Point PCH HM77

USB 3.0 USB2.0

Port 2

Mini Card WLAN/BT4.0 Half P.38

Port 0,1 Port 2,3

BGA 989 Balls

PCI-E x1

Port 1,2

P.32

P.36

USB 3.0 Conn. 3 USB 2.0 Conn. 4

P.37

Port 11

Digital Camera (With Digital MIC) P.21

Port 8

Mini Card WLAN (Half)

Port 1

Ethernet RTL8105E

USB 3.0 Conn. 1 USB 3.0 Conn. 2

Port 10

Daughter board

P.38

Card Reader P.34 RTS5170/RTS5179

3 in 1 Socket

P.34

3

3

RJ45

Port 9

P.32

Touch Screen

P.21

HD Audio P13~20

RTC CKT. Power On/Off CKT.

SPI ROM P.44

4MB

P.40

SPI ROM 2MB

Digital Mic.

SPI

P.13

SPI

LPC Bus

Audio Codec

33MHz

ALC3221

P.33

Headphone Jack / Mic. Jack combo

P.33

Int. Speaker R / L

P.33

P.13

ENE KBC KB9012 P.39

DC/DC Interface CKT.

P.35

PS/2 4

4

Int.KBD P.40

Touch Pad P.40

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2012/09/25

Deciphered Date

2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

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Title

Block diagram Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 E

Sheet

2

of

57

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E

Compal Confidential Project Code : VAW11 File Name : LA-9102P

ｗｗｗ．６６６ｆｉｘ．ｃｏｍ好修网

LS-9104P (ODD/B)

LS-9105P (PWR/B) 1

1

UE5 (SA00003VQ00)

Lid

4 pin-Hot Bar

SW1 (SN100004Y00)

JBTB2 12 pin

PBATT Battery

JMINI

PWR-BTN FFC

JODD

MINI Card

JLVDS 40 pin

4 pin

JKB 30 pin

PJPDC 5 pin

JHDMI

HDMI

JPWR 4 pin

JLAN

JUSB1

LS-9102P (USB/B)

JTP 6 pin

2

2

JBTB1 12 pin

JFAN 3 pin

USB

USB-DB FFC

XDP

RJ-45

8 pin

JXDP

LA-9102P M/B

USB RTC

JUSB2

USB

JUSB3

USB

JDB 8 pin

Top Side Bottom Side

JRTC 2 pin

JUSB4

8 pin Hot Bar

JHDD

(OAK 17") JREAD JSPK 4 pin

3

JHP

TP-MB FFC 6 pin

3

Card Reader

HP Led1

Led3 Led2

Led4

TP-Module

4

TP-BTN FFC

4

4 pin LS-9103P (TP-BTN/B)

SW2 A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 4 pin Hot Bar

2012/09/25

2013/09/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SW3 B

C

D

Title

DB block diagram Size Date:

Document Number

Rev 1.0

LA-9102P

Tuesday, September 25, 2012

Sheet E

3

of

57

A

Board ID Table for AD channel Vcc Ra Board ID

0 1 2 3 4 5 6 7

3.3V +/100K +/Rb 0 8.2K +/18K +/33K +/56K +/100K +/200K +/NC

5% 5%

5% 5% 5% 5% 5% 5%

BOARD ID Table V AD_BID min 0 V 0.168 V 0.375 V 0.634 V 0.958 V 1.372 V 1.851 V 2.433 V

V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V

V AD_BID max 0.155 V 0.362 V 0.621 V 0.945 V 1.359 V 1.838 V 2.420 V 3.300 V

ID 0 1 2 3 4 5 6 7

EC AD3 0x00-0x0C 0x0D-0x1C 0x1D-0x30 0x31-0x49 0x4A-0x69 0x6A-0x8E 0x8F-0xBB 0xBC-0xFF

PCB Revision 0.1 0.1 0.1 0.2 0.2 0.2 0.3 0.3 0.3 1.0 1.0 1.0 UMA

THM

Project ID Table Project Revision

ID 0 1 2 3 4 5 6 7

USB PORT#

UMA

DESTINATION

0

USB conn.2

1

USB conn.1

2

USB conn.3

3

USB conn.4 (DB)

4

NC

5

NC

6

NC

7

NC

8

MINI CARD (WLAN)

9

NC

10

Card Reader

11

Camera

12

NC

13

NC

DIS THAMES DIS MARS PRO

MARS

SMBUS Control Table SOURCE EC_SMB_CK1 EC_SMB_DA1

KB9012

EC_SMB_CK2 EC_SMB_DA2

KB9012

PCH_SML0CLK PCH_SML0DATA

PCH

PCH_SML1CLK PCH_SML1DATA

PCH

MEM_SMBCLK MEM_SMBDATA

PCH

MINI1

MINI2

BATT

SODIMM

Express Card

Thermal Sensor

FFS

VGA Thermal Sensor

VGA

XDP

Charger

V

PCH

V V

V Link

V

V

DIFFERENTIAL

V

V

DESTINATION

V FLEX CLOCKS

V DESTINATION

1

1

CLK

CLKOUT_PCIE0

10/100 LAN

CLKOUTFLEX0

None

CLKOUT_PCIE1

MINI CARD WLAN

CLKOUTFLEX1

None

CLKOUT_PCIE2

None

CLKOUTFLEX2

None

CLKOUT_PCIE3

None

CLKOUTFLEX3

None

CLKOUT_PCIE4

None

CLKOUT_PCIE5

None

CLKOUT_PCIE6

None

CLKOUT PCI0 CLKOUT_PCIE7 CLKOUT_PEG_B

DESTINATION PCH_LOOPBACK

None PCI1

EC LPC

PCI2

None

PCI3

None

PCI4

None

None

Symbol Note :

SATA

DESTINATION

PCI EXPRESS

DESTINATION

SATA0

HDD

Lane 1

10/100 LAN

SATA1

None

Lane 2

MINI CARD (WLAN)

SATA2

ODD

Lane 3

None

SATA3

None

Lane 4

None

SATA4

None

Lane 5

None

SATA5

None

Lane 6

None

Lane 7

None

Lane 8

None

: means Digital Ground

: means Analog Ground Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2012/09/25

Deciphered Date

2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

Title

Notes List Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012

Sheet

4

of

57

5

4

3

UC1

2

i3R1@

UC1

SA00005L52L

UC1

i5R3@

i3VOSR3@

SA00005UH2L

AV8062701313000-SR0U3-J1-1.4G_BGA1023~D

AV8062701313000-SR0U3-J1-1.4G_BGA1023~D

UC1

UC1

i7R1@

i7R3@

SA00005K53L

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D UC1

UC1

SA00005UH1L

AV8063801058401-SR0N9-L1-1.8G_BGA1023~D

SA00005K62L

(1)PEG_RCOMPO (G4) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC1. (2)PEG_ICOMPO use 12mil connect to RC1

i3VOSR1@

SA00005L53L

AV8063801058401-SR0N9-L1-1.8G_BGA1023~D UC1

1

i3R3@

CELR1@

SA00005K52L

AV8063801057605-SR0N6-L1-1.9G_BGA1023~D UC1

AV8063801057605-SR0N6-L1-1.9G_BGA1023~D

CELR3@

D

D

PEG_RCOMPO (G4)

R_COMP place close to CPU

SA00006021L

SA00006022L

width 4 mils PEG_ICOMPI (G3) Trace length Max is 500 mils

VCC_IO width 12 mils

PEG_ICOMPO (G1)

AV8062701085401-SR0VA-Q0-1.5G_BGA1023~D

AV8062701085401-SR0VA-Q0-1.5G_BGA1023~D

UC1

UC1

PENR1@

PENR3@

R_COMP SA00005ZZ1L

SA00005ZZ2L

+VCCP

AV8062701084801-SR0V5-Q0-1.6G_BGA1023~D

1

AV8062701084801-SR0V5-Q0-1.6G_BGA1023~D

RC2 24.9_0402_1%



DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

N3 P7 P3 P11



DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3



DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3







FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7







FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7



FDI_FSYNC0 FDI_FSYNC1

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_INT



FDI_LSYNC0 FDI_LSYNC1

FDI_LSYNC0 FDI_LSYNC1

K1 M8 N4 R2 K3 M7 P4 T3

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

U7 W11 W1 AA6 W6 V4 Y2 AC9

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

U6 W10 W3 AA7 W7 T4 AA3 AC8 AA11 AC12 U11 AA10 AG8

DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]

FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC

+VCCP

1

2

RC36

2

+EDP_COM

24.9_0402_1%

1

RC158

AF3 AD2 AG11

10K_0402_5%

@

AC3 AC4 AE11 AE7 AC1 AA4 AE10 AE6

eDP_COMPIO eDP_ICOMPO eDP_HPD# eDP_AUX# eDP_AUX eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

eDP

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance 4.75K INTEL recommand 1.1K PDG 0.71 rev -->200

RC28 39_0402_1%

1

CFG10_R CFG11_R

@ RC6 10K_0402_5%

2

1 RC13 1 RC15

@ @

1

@

1

2 2

0_0402_5% 0_0402_5%

CFG10 CFG11

1

RC132 0_0402_1% @

1



XDP_BPM#2 XDP_BPM#3

+VCCP

3

SYS_PWROK_XDP

GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17

CC36 0.1U_0402_16V7K

XDP_BPM#0 XDP_BPM#1

GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16

RC129

0_0402_5%

1

XDP_PREQ#_R XDP_PRDY#_R

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

CC35 0.1U_0402_16V7K

@ RC49 1K_0402_5%

2

D

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

CC33 0.1U_0402_16V7K

JXDP

UC3

1 2 3

PLT_RST#

5

NC VCC A GND Y

RC58

4

1

BUFO_CPU_RST#

2

BUF_CPU_RST#

43_0402_1%

2 @

RC128

1

H_THERMTRIP#

56_0402_1%

UC1B

F49

H_SNB_IVB#

RC124

2

110K_0402_5%

@

H_CATERR#

C49

A48

H_PECI

H_PECI

PROC_DETECT#

1

H_PROCHOT#

2 H_PROCHOT#_R 56_0402_1%

RC57

place RC57 near CPU

2

H_THERMTRIP#

1

C45

PECI

PROCHOT#

300mils ~1530mils 2

@

H_THERMTRIP#_R 0_0402_1%

RC130

D45

BCLK BCLK# DPLL_REF_CLK DPLL_REF_CLK# BCLK_ITP BCLK_ITP#

J3 H2

CLK_CPU_DMI CLK_CPU_DMI#



AG3 AG1

RC65 1 RC77 1

2 1K_0402_1% 2 1K_0402_1%

CLK_CPU_DPLL_R CLK_CPU_DPLL#_R

PU/PD for JTAG signals

+VCCP

Remove DPLL Ref clock (for eDP only)

+VCCP

N59 N58

CATERR#

VR1 TOPOLOGY

1 @ CC151 0.1U_0402_10V7K~D

C57

PROC_SELECT#

THERMAL

PROC_DETECT (Processor Detect): pulled to ground on the processor package. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present

B

i5R1@

2 H_CATERR# 49.9_0402_1%~D 2 H_PROCHOT# 62_0402_5%~D

MISC

RC44

2 @

CLOCKS

1

SM_DRAMRST#

DDR3 MISC

1 RC127

@ RC62 0_0402_5%

2

CC63 0.1U_0402_16V7K

1

@ +VCCP

1

SN74LVC1G07DCKR_SC70-5~D

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

AT30

H_DRAMRST#

BF44 BE43 BG43

SM_RCOMP0 140_0402_1% 1 SM_RCOMP1 25.5_0402_1%1 SM_RCOMP2 200_0402_1% 1

H_DRAMRST#

H_DRAMRST#

1 2 RC86 2 RC83 2 RC85

2

DDR3 Compensation Signals

@ CC143 0.1U_0402_25V6K

51_0402_5% 1

XDP_TDI_R

51_0402_5% 1

2 RC47

XDP_PREQ#

51_0402_5% 1

XDP_TDO

51_0402_5% 1

2 RC106

XDP_TCK_R

51_0402_5% 1

2 RC105

XDP_TRST#_R

51_0402_5% 1

2 RC104

2 RC46 @

2 RC48

B

Place close to CPU

THERMTRIP#

XDP_TMS_R

Place on BOTTOM(-4059,5169) area.

H_PM_SYNC

H_PM_SYNC

1

H_CPUPWRGD

2

VCCPWRGOOD_0_R 1K_0402_5%

RC25

PRDY# PREQ#

C48

B46

PM_SYNC

UNCOREPWRGOOD

RC64 VDDPWRGOOD CC141

VDDPWRGOOD_R @ CC142 0.1U_0402_25V6K

1

1

2

VDDPWRGOOD_R

BE45

SM_DRAMPWROK

130_0402_1% @

1

0.1U_0402_25V6K

2

BUF_CPU_RST#

D44

RESET#

2

PWR MANAGEMENT

250mils~2530 mils

JTAG & BPM

place RC129 near CPU

ESD request to reserve CC141

Place close to CPU

TCK TMS TRST# TDI TDO

N53 N55

XDP_PRDY# XDP_PREQ#

RC125 RC135

1 1

@ @

2 0_0402_5% 2 0_0402_5%

XDP_PRDY#_R XDP_PREQ#_R

L56 L55 J58

XDP_TCK XDP_TMS XDP_TRST#

RC136 RC137 RC126

1 1 1

@ @ @

2 0_0402_5% 2 0_0402_5% 2 0_0402_5%

XDP_TCK_R XDP_TMS_R XDP_TRST#_R

M60 L59

XDP_TDI_R XDP_TDO_R

RC50 RC92

1 1

@ @

2 0_0402_5% 2 0_0402_5%

XDP_TDI XDP_TDO

+3VS RC42

1

XDP_DBRESET#_R

DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

K58 XDP_DBRESET#_R

RC89

1

2 0_0402_5%

XDP_DBRESET#

G58 E55 E59 G55 G59 H60 J59 J61

XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R XDP_BPM#4_R XDP_BPM#5_R XDP_BPM#6_R XDP_BPM#7_R

RC95 RC91 RC101 RC102 RC103 RC97 RC88 RC87

1 1 1 1 1 1 1 1

@ @ @ @ @ @ @ @

2 2 2 2 2 2 2 2

0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

RC90 RC96 RC93 RC94

1 1 1 1

@ @ @ @

2 2 2 2

0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%

XDP_DBRESET#

XDP_DBRESET#_R

1K_0402_5%

1 CC144 0.1U_0402_25V6K

2

1 VCCPWRGOOD_0_R 10K_0402_5%

2 RC45

2

Place close to CPU

Avoid stub in the PWRGD path while placing resistors RC25 & RC130

CFG12 CFG13 CFG14 CFG15



AV8063801058002-SR0N8-L1-1.7G_BGA1023~D A

A

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

PROCESSOR(2/6) PM,XDP,CLK Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

6

of

57

4

UC1C

C

B

UC1D

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

D



DDR_A_BS0 DDR_A_BS1 DDR_A_BS2



DDR_A_CAS# DDR_A_RAS# DDR_A_WE#

2

i5R1@

DDR_A_D[0..63]

AG6 AJ6 AP11 AL6 AJ10 AJ8 AL8 AL7 AR11 AP6 AU6 AV9 AR6 AP8 AT13 AU13 BC7 BB7 BA13 BB11 BA7 BA9 BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37 BF36 BA28

BE39 BD39 AT41

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

DDR SYSTEM MEMORY A

3

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

AU36 AV36 AY26

M_CLK_DDR0 M_CLK_DDR#0 DDR_CKE0_DIMMA

AT40 AU40 BB26

M_CLK_DDR1 M_CLK_DDR#1 DDR_CKE1_DIMMA

BB40 BC41

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

AY40 BA41

M_ODT0 M_ODT1

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

M_CLK_DDR1

M_CLK_DDR#1

DDR_CKE1_DIMMA

M_ODT0 M_ODT1





DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

i5R1@

DDR_B_D[0..63]

M_CLK_DDR0

M_CLK_DDR#0

DDR_CKE0_DIMMA

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

1







DDR_B_BS0 DDR_B_BS1 DDR_B_BS2



DDR_B_CAS# DDR_B_RAS# DDR_B_WE#

AL4 AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9 BD13 BF12 BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59 AM60 AL59 AF61 AH60

BG39 BD42 AT22

AV43 BF40 BD45

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_CK[0] SB_CK#[0] SB_CKE[0]

SB_CK[1] SB_CK#[1] SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

DDR SYSTEM MEMORY B

5

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

BA34 AY34 AR22

M_CLK_DDR2 M_CLK_DDR#2 DDR_CKE2_DIMMB

BA36 BB36 BF27

M_CLK_DDR3 M_CLK_DDR#3 DDR_CKE3_DIMMB

BE41 BE47

DDR_CS2_DIMMB# DDR_CS3_DIMMB#

AT43 BG47

M_ODT2 M_ODT3

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

D

M_CLK_DDR2

M_CLK_DDR#2

DDR_CKE2_DIMMB

M_CLK_DDR3

M_CLK_DDR#3

DDR_CKE3_DIMMB

DDR_CS2_DIMMB# DDR_CS3_DIMMB#

M_ODT2 M_ODT3





DDR_B_DQS#[0..7]

C

DDR_B_DQS[0..7]

DDR_B_MA[0..15]

B

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

1

+1.5V

1

2

@

RC107

QC2

RC108 1K_0402_5%

0_0402_5%

D

3

H_DRAMRST#

1

DDR3_DRAMRST#

1

DDR3_DRAMRST#_R RC110

2 1K_0402_5%

DDR3_DRAMRST#

1

2

G

1

H_DRAMRST#

S

2

BSS138_SOT23

2 1

RC109 4.99K_0402_1%

RC111

@ 2 0_0402_1%

DRAMRST_CNTRL_PCH

@ CC145 0.1U_0402_25V6K

Place close to RC110

2

DRAMRST_CNTRL

DRAMRST_CNTRL

A

A

1 CC37 .047U_0402_16V7K

2

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

PROCESSOR(3/6) DDRIII Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

7

of

57

5

4

3

2

1

CFG Straps for Processor D

D

1

CFG2

2

RC116 1K_0402_1%

1

VCC_AXG_VAL_SENSE VSS_AXG_VAL_SENSE

2

H43 K43

VCC_VAL_SENSE VSS_VAL_SENSE

@ RC123 50_0402_1%

H45 K45

VCC_VAL_SENSE VSS_VAL_SENSE VAXG_VAL_SENSE VSSAXG_VAL_SENSE

@

1

2

1

@ RC120 50_0402_1%

2

RC21

TP_VCC_DIESENSE 1K_0402_5%

PAD~D PAD~D

T46 @ T36 @

PAD~D

T32 @

PAD~D PAD~D

T34 @ T35 @

PAD~D

T40 @

PAD~D

T42 @

PAD~D PAD~D

T47 @ T71 @

PAD~D PAD~D PAD~D PAD~D

T72 T51 T68 T49

@ @ @ @

F48 H48 K48 BA19 AV19 AT21 BB21 BB19 AY21 BA22 AY22 AU19 AU21 BD21 BD22 BD25 BD26 BG22 BE22 BG26 BE26 BF23 BE24

N42 L42 L45 L47

@ T14 @ T15 @ T16 @ T17

PAD~D PAD~D PAD~D PAD~D

M13 M14 U14 W14 P13

@ T22 @ T21 @ T19 @ T20 @ T18

PAD~D PAD~D PAD~D PAD~D PAD~D

AT49 K24

@ T23

PAD~D

AH2 AG13 AM14 AM15

@ T28 @ T27 @ T25 @ T26

PAD~D PAD~D PAD~D PAD~D

N50

@ T29

PAD~D

@ RC117 1K_0402_1%

RC115 1K_0402_1%

*0:Lane Reversed 1

CFG4

RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

C

Display Port Presence Strap

* 1 : Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port

VCC_DIE_SENSE

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27

RC112 1K_0402_1%

@

2

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

1:(Default) Normal Operation; Lane # definition matches socket pin map definition

CFG2 @

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58 DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

TP_DC_TEST_A4

@ T121 PAD~D

DC_TEST_C4_D3 TP_DC_TEST_D1 TP_DC_TEST_A58

@ T118 PAD~D @ T119 PAD~D

CFG6 CFG5

DC_TEST_A59_C59 DC_TEST_A61_C61 TP_DC_TEST_D61 TP_DC_TEST_BD61

1

PAD~D PAD~D

RSVD30 RSVD31 RSVD32 RSVD33

PEG Static Lane Reversal - CFG2 is for the 16x

1

2

CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

RSVD28 RSVD29

RC114 1K_0402_1% @ T120 PAD~D @ T122 PAD~D

RC113 1K_0402_1% @

2

@ RC119 50_0402_1%

1

C

@ RC121 50_0402_1%





1

2

+VCC_GFXCORE_AXG

PAD~D PAD~D

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17]

+SA_DIMM_VREFDQ

+SA_DIMM_VREFDQ +SB_DIMM_VREFDQ

2

+VCC_CORE

+SA_DIMM_VREFDQ

BE7 BG7

1

PAD~D

B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53

2

PAD~D

CFG0 T91 @ CFG2 T92 @ CFG4 CFG5 CFG6 CFG7 T66 @ T41 @ CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 T69 @ T89 @

2

CFG0

RESERVED

i5R1@

1

UC1E

DC_TEST_BE59_BE61 DC_TEST_BG59_BG61 TP_DC_TEST_BG58 TP_DC_TEST_BG4

@ T132 PAD~D @ T123 PAD~D

DC_TEST_BE3_BG3 DC_TEST_BE1_BG1 TP_DC_TEST_BD1

PCIE Port Bifurcation Straps @ T124 PAD~D

11: (Default) x16 - Device 1 functions 1 and 2 disabled

B

B

CFG[6:5]

*10: x8, x8 - Device 1 function 1 enabled ; function 2

disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

@ RC118 1K_0402_1%

2

1

CFG7

PEG DEFER TRAINING

CFG7

*1: (Default) PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

A

A

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

PROCESSOR(4/6) RSVD,CFG Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

8

of

57

5

4

UC1F i5R1@

3

POWER

2

1

+VCCP

+VCC_CORE

8.5A

D

VCCIO[1] VCCIO[3] VCCIO[4] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] VCCIO[9] VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29]

Iccmax current changed for PDDG Rev0.7

CPU Power Rail Table Voltage Rail

Voltage

VCC

0.65-1.3

VCCIO VAXG

VDDQ

1.5

*

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

53 8.5

0.0-1.1 1.8

+1.5V_MEM

S0 Iccmax Current (A)

1.05/1

VCCPLL

VCCSA

+VCCP

VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

33 1.2 5

0.65-0.9

6

1.5

12-16

*

Description

5A to Mem controller(+1.5V_CPU_VDDQ) 5-6A to 2 DIMMs/channel 2-5A to +1.5V_RUN & +0.75V_DDR_VTT

C

+3VS

VCCP_PWRCTRL Pull high on power side

W16 W17

2

VCCIO50 VCCIO51

RC141 10K_0402_5%

1

@

VCCIO_SEL

BC22

1

2 VCCP_PWRCTRL 0_0402_5%

@ RC140

+VCCP

B

+VCCP

RC147 130_0402_1%

RC145 75_0402_5%

A44 B43 C44

RC142 1 RC146 1 RC144 1

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

2 43_0402_1% 2 0_0402_1% @ @ 2 0_0402_1%

VR_SVID_ALRT#

VR_SVID_CLK

VR_SVID_DAT

+VCC_CORE

CAD Note: Place the PU resistors close to CPU RC147 close to CPU 300~1500mils

1

SVID

VIDALERT# VIDSCLK VIDSOUT

1

RC147 close to CPU

2

2

2

1

Note: Place the PU resistors close to CPU RC145 close to CPU 300~1500mils 1

VCCPQE[1] VCCPQE[2]

AM25 AN22

CC573 1U_0402_6.3V6K

QUIET RAILS

B

VCC[1] VCC[2] VCC[3] VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16] VCC[17] VCC[18] VCC[19] VCC[20] VCC[21] VCC[22] VCC[23] VCC[24] VCC[25] VCC[26] VCC[27] VCC[28] VCC[29] VCC[30] VCC[31] VCC[32] VCC[33] VCC[34] VCC[35] VCC[36] VCC[37] VCC[38] VCC[39] VCC[40] VCC[41] VCC[42] VCC[43] VCC[44] VCC[45] VCC[46] VCC[47] VCC[48] VCC[49] VCC[50] VCC[51] VCC[52] VCC[53] VCC[54] VCC[55] VCC[56] VCC[57] VCC[58] VCC[59] VCC[60] VCC[61] VCC[62] VCC[63] VCC[64] VCC[66] VCC[67] VCC[68] VCC[69] VCC[70] VCC[71] VCC[72] VCC[73] VCC[74] VCC[75] VCC[76]

CORE SUPPLY

C

A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

PEG IO AND DDR IO

33A ULV 17W , Max Current in Turbo Mode or HFM

D

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

VCCIO_SENSE VSS_SENSE_VCCIO

RC139 1 RC122 1

VCCSENSE_R VSSSENSE_R

2 RC98

10_0402_1%

2 0_0402_1% 2 0_0402_1%

@ @

VCCSENSE VSSSENSE

+VCCP

AN16 AN17

VCCIO_SENSE VSSIO_SENSE_R

1 RC133 AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

A

1

2

F43 G43



1

VCC_SENSE VSS_SENSE

RC131 100_0402_1%



2

SENSE LINES

RC138 100_0402_1%

2 10_0402_1%

Place RC98 close to CPU

A

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

PROCESSOR(5/6) PWR,BYPASS Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

9

of

57

5

4

3

2

1

+1.5V_CPU_VDDQ Source

RC149 0_0402_5% SUSP#

1

CPU1.5V_S3_GATE

1

2

+V_DDR_SMREF

+1.5V_CPU_VDDQ

2

RC80 1K_0402_1%

0_0402_5%

RC84 1K_0402_1%

3

1

+V_SM_VREF_CNT

1

1

2

@ QC5 NTR4503NT1G_SOT23-3~D

2

@

1

1

1 @ RC134

RC81 1K_0402_1%

2

D

2

@

RC78 1K_0402_1%

2

1

2

RUN_ON_CPU1.5VS3

2

@ RUN_ON_CPU1.5VS3# UC1G

i5R1@

1 0.1U_0402_10V7K~D

CC150

2

1 0.1U_0402_10V7K~D

1

2

VREF - 1.5V RAILS DDR3

1

2

1

2

1

2

1

2

1 +

2

1

2

1

2

1U_0402_6.3V6K CC259

2

2

1U_0402_6.3V6K CC258

1

1

CC167

2

2

1U_0402_6.3V6K CC257

1

1

330U_D2_2VM_R6M~D

2

2

1U_0402_6.3V6K CC256

1

1

CC166 10U_0603_6.3V6M

2

2

1U_0402_6.3V6K CC255

1

1

1U_0402_6.3V6K CC254

2

2

1U_0402_6.3V6K CC253

1

1

CC165 10U_0603_6.3V6M

2

+1.5V

CC164 10U_0603_6.3V6M

1

1U_0402_6.3V6K CC252

1

2

CC163 10U_0603_6.3V6M

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

CC162 10U_0603_6.3V6M

A

VCCSA[1] VCCSA[2] VCCSA[3] VCCSA[4] VCCSA[5] VCCSA[6] VCCSA[7] VCCSA[8] VCCSA[9] VCCSA[10] VCCSA[11] VCCSA[12] VCCSA[13] VCCSA[14] VCCSA[15] VCCSA[16]

QUIET RAILS SENSE LINES

L17 L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21 W20

VCCPLL[1] VCCPLL[2] VCCPLL[3]

VCCDQ[1] VCCDQ[2]

AM28 AN26 1

2

VDDQ_SENSE VSS_SENSE_VDDQ

VCCSA VID lines

2 1 2

2

1 0.1U_0402_10V7K~D

CC149

6A VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8] VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

1U_0402_6.3V6K CC251

2

1

6A

1U_0402_6.3V6K CC260

2

2

1U_0402_6.3V6K CC261

2

1

1

BB3 BC1 BC4

CC175 1U_0402_6.3V6K

2

1

1U_0402_6.3V6K CC262

2

1

2

CC174 1U_0402_6.3V6K

1

1U_0402_6.3V6K CC263

2

1

1U_0402_6.3V6K CC264

1

10U_0603_6.3V6M CC183

2

10U_0603_6.3V6M CC168

2

10U_0603_6.3V6M CC169

10U_0603_6.3V6M CC170

10U_0603_6.3V6M CC171

330U_D2_2VM_R6M~D CC172

2

2

1

2

1

1 0.1U_0402_10V7K~D

2

CC161 10U_0603_6.3V6M

VAXG_SENSE VSSAXG_SENSE

1.2A CC176

330U_D2_2.5VM_R6M~D

+VCCSA

+

2

CC179

VCCSA_SENSE

VCCSA_VID[0] VCCSA_VID[1]

CC574 1U_0402_6.3V6K

+1.8VS

1

CC178

+1.5V_CPU_VDDQ

1 F45 G45

RC100 100_0402_1%

1

5A

+1.5V_CPU_VDDQ

VCC_AXG_SENSE VSS_AXG_SENSE

1

+V_SM_VREF should have 10 mil trace width

CC180 10U_0603_6.3V6M

2

A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53 A9 AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56 AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46 AC6 AD17 AD20 AD4 AD61 AE13 AE8 AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59 AG10 AG14 AG18 AG47 AG52 AG61 AG7 AH4 AH58 AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48 AJ7 AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61 AM13 AM20 AM22 AM26 AM30 AM34

AY43

@ RC76 100_0402_1%

RC99 100_0402_1%

1

SM_VREF

1U_0402_6.3V6K CC250

+VCC_GFXCORE_AXG

VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22] VAXG[23] VAXG[24] VAXG[25] VAXG[26] VAXG[27] VAXG[28] VAXG[29] VAXG[30] VAXG[31] VAXG[32] VAXG[33] VAXG[34] VAXG[35] VAXG[36] VAXG[37] VAXG[38] VAXG[39] VAXG[40] VAXG[41] VAXG[42] VAXG[43] VAXG[44] VAXG[45] VAXG[46] VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54] VAXG[55] VAXG[56]

CC181 10U_0603_6.3V6M

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46 N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61

i5R1@

+V_SM_VREF_CNT

33A

B

+

UC1H

POWER

+VCC_GFXCORE_AXG

C



GRAPHICS

2

@ CC40 0.1U_0402_10V7K~D

SENSE LINES

1

1.8V RAIL

2

@

RC148 0_0402_1%

SA RAIL

QC7A 2N7002DW-7-F_SOT363-6

2

+1.5V

1

2

6

4

RC150 2M_0402_5%~D

1

2

4

2 3

5

RUN_ON_CPU1.5VS3#

1

CC38 10U_0805_10V6K

1 1 2

RUN_ON_CPU1.5VS3 CC39 0.1U_0603_50V_X7R

QC7B 2N7002DW-7-F_SOT363-6

D

1 2 3

RC151 470K_0402_5%

RC143 100K_0402_5%

+1.5V_CPU_VDDQ

8 7 6 5

1

QC3 AO4304L_SO8

B+_BIAS

RC152 20K_0402_5%

+1.5V +3VALW

BC43 BA43

U10

VCCSA_SENSE

D48 D49

VCCSA_VID0 VCCSA_VID1



VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

VSS

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

C

B

A

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

PROCESSOR(6/6) PWR,VSS Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

10

of

57

5

4

3

+1.5V

2

1

+1.5V JDIMM1

DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2

Layout Note: Place near JDIMM1

All VREF traces should have 10 mil trace width

DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25

+1.5V DDR_A_D26 DDR_A_D27

2

1

CD6

1

CD5

2

1U_0402_6.3V6K

CD4

1

1U_0402_6.3V6K

2

1U_0402_6.3V6K

CD3

1U_0402_6.3V6K

C

1

DDR_CKE0_DIMMA

DDR_CKE0_DIMMA

2

DDR_A_BS2

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 +1.5V

1

2

@

1 +

2

CD14 220U_2V_D2

2

M_CLK_DDR0 M_CLK_DDR#0

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_BS0

DDR_A_MA10 DDR_A_BS0



DDR_A_WE# DDR_A_CAS#

DDR_A_WE# DDR_A_CAS#



CD13

2

1

10U_0603_6.3V6M CD12

2

1

10U_0603_6.3V6M CD11

2

1

10U_0603_6.3V6M CD10

2

1

10U_0603_6.3V6M CD9

1

10U_0603_6.3V6M CD8

2

10U_0603_6.3V6M CD7

10U_0603_6.3V6M

1

DDR_A_MA3 DDR_A_MA1

DDR_A_MA13 DDR_CS1_DIMMA#

DDR_CS1_DIMMA#

B

+0.75VS

DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49

DDR_A_D50 DDR_A_D51

DDR_A_D58 DDR_A_D59

2

RD7

10K_0402_5%

+0.75VS

205

G1

G2

DDR_A_D30 DDR_A_D31

DDR_CKE1_DIMMA

DDR_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

C

DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR1 M_CLK_DDR#1

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA# M_ODT0

DDR_CS0_DIMMA# M_ODT0

M_ODT1

M_ODT1



+1.5V



RD4 1K_0402_1%

+VREF_CA

DDR_A_D36 DDR_A_D37

DDR_A_D38 DDR_A_D39

1

2

RD5 1K_0402_1%

1

2

DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5

B

DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 @ RD8

M3

DDR_A_D54 DDR_A_D55

1

2 0_0402_5% QD1

3

+SA_DIMM_VREFDQ

DDR_A_D60 DDR_A_D61

1 BSS138_NL_SOT23-3

+V_DDR_REFA

DDR_A_DQS#7 DDR_A_DQS7

DRAMRST_CNTRL

DRAMRST_CNTRL

DDR_A_D62 DDR_A_D63 @ RD9 PCH_SMBDATA PCH_SMBCLK

PCH_SMBDATA PCH_SMBCLK



1

2 0_0402_5% QD2

+0.75VS

3

+SB_DIMM_VREFDQ

1 BSS138_NL_SOT23-3

+V_DDR_REFB

206 G

2

2 10K_0402_5%

1

DDR_A_DQS#3 DDR_A_DQS3

D

1

1 RD6

DDR_A_D28 DDR_A_D29

S

2

CD21

1

CD22 2.2U_0603_6.3V6K

0.1U_0402_16V7K

+3VS

DDR_A_D22 DDR_A_D23

G

DDR_A_D56 DDR_A_D57

DDR_A_D20 DDR_A_D21

D

2

S

2

1

CD20 1U_0402_6.3V6K

2

1

CD19 1U_0402_6.3V6K

1

CD18 1U_0402_6.3V6K

2

CD17 1U_0402_6.3V6K

1

DDR_A_DQS#6 DDR_A_DQS6

DDR3_DRAMRST#

DDR_A_D14 DDR_A_D15

CD16

DDR_A_D40 DDR_A_D41

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

DDR3_DRAMRST#

CD15

DDR_A_D34 DDR_A_D35

CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2

DDR_A_D12 DDR_A_D13

0.1U_0402_16V7K

DDR_A_DQS#4 DDR_A_DQS4

Layout Note: Place near JDIMM1.203,204

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

D

DDR_A_D6 DDR_A_D7

2.2U_0603_6.3V6K

DDR_A_D32 DDR_A_D33

73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

DDR_A_DQS#0 DDR_A_DQS0

2

DDR_A_D10 DDR_A_D11

DDR_A_D4 DDR_A_D5

2

2

DDR_A_DQS#1 DDR_A_DQS1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

1

1

DDR_A_D8 DDR_A_D9 RD3 1K_0402_1%

VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26

2

2

VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25

1

2

DDR_A_D2 DDR_A_D3

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

2

+V_DDR_REFA

2

DDR_A_MA[0..15]

DDR_A_D0 DDR_A_D1

1 CD2

DDR_A_D[0..63]

1 CD1

RD1 1K_0402_1%

0.1U_0402_16V7K

DDR_A_DQS[0..7]

+V_DDR_REFA

+V_DDR_REFA

+1.5V

2.2U_0603_6.3V6K

D

DDR_A_DQS#[0..7]

1

BELLW_80001-5021 CONN@

DRAMRST_CNTRL

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

SP07000LZ00 A

A

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

DDRIII DIMMA Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

11

of

57

4

3

2

+1.5V

DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9

DDR_B_DQS[0..7]

DDR_B_D[0..63]

DDR_B_MA[0..15]

1

DDR_B_DQS#[0..7]

DDR_B_DQS#1 DDR_B_DQS1

2

RD16 1K_0402_1%

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

DDR_B_D10 DDR_B_D11 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19

All VREF traces should have 10 mil trace width

DDR_B_D24 DDR_B_D25

Layout Note: Place near JDIMMB

DDR_B_D26 DDR_B_D27

DDR_CKE2_DIMMB

DDR_CKE2_DIMMB

C

DDR_B_BS2

DDR_B_BS2

+1.5V

2

DDR_B_MA8 DDR_B_MA5

1

CD31

CD30

2

1

1U_0402_6.3V6K

CD29

2

1

1U_0402_6.3V6K

1U_0402_6.3V6K

CD28

1U_0402_6.3V6K

1

DDR_B_MA12 DDR_B_MA9

DDR_B_MA3 DDR_B_MA1

2

+1.5V

DDR_B_BS0



DDR_B_WE# DDR_B_CAS#

DDR_B_WE# DDR_B_CAS#

1

1

+

2

DDR_B_D32 DDR_B_D33 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35 DDR_B_D40 DDR_B_D41

B

DDR_B_D42 DDR_B_D43

Layout Note: Place near JDIMMB.203,204

DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D50 DDR_B_D51

+0.75VS

+3VS

2

1

+3VS +0.75VS

1

205 207 CD47

2

CD46

1

2.2U_0603_6.3V6K

0.1U_0402_16V7K

RD20 10K_0402_5%

RD19 10K_0402_5%

1

2

DDR_B_D58 DDR_B_D59

2

2

1

CD45 1U_0402_6.3V6K

2

1

CD44 1U_0402_6.3V6K

1

CD43 1U_0402_6.3V6K

2

CD42 1U_0402_6.3V6K

1

DDR_B_D56 DDR_B_D57

GND1 BOSS1

GND2 BOSS2

DDR_B_D12 DDR_B_D13

DDR3_DRAMRST#

DDR3_DRAMRST#

DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21

DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14

C

DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR3 M_CLK_DDR#3

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2

DDR_CS2_DIMMB# M_ODT2

M_ODT3

M_ODT3



+1.5V



RD17 1K_0402_1%

+VREF_CB

DDR_B_D36 DDR_B_D37

DDR_B_D38 DDR_B_D39

1

2

RD18 1K_0402_1%

1

2

CD41

2

DDR_CS3_DIMMB#

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

DDR_B_D6 DDR_B_D7

CD40

2

1

DDR_B_MA13 DDR_CS3_DIMMB#

CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT

D

DDR_B_DQS#0 DDR_B_DQS0

0.1U_0402_16V7K

2

DDR_B_MA10 DDR_B_BS0

CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT

DDR_B_D4 DDR_B_D5

2.2U_0603_6.3V6K

1

M_CLK_DDR2 M_CLK_DDR#2

CD39 220U_2V_D2

2

@ CD38

1

10U_0603_6.3V6M CD37

2

10U_0603_6.3V6M CD36

1

10U_0603_6.3V6M CD35

2

10U_0603_6.3V6M CD34

1

10U_0603_6.3V6M CD33

2

10U_0603_6.3V6M CD32

10U_0603_6.3V6M

1

M_CLK_DDR2 M_CLK_DDR#2



73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

1

2

VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS

2

1 2

DDR_B_D0 DDR_B_D1

1 CD26

CD27

2

0.1U_0402_16V7K

2.2U_0603_6.3V6K

1

VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS

1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

+V_DDR_REFB

+V_DDR_REFB

RD15 1K_0402_1% +V_DDR_REFB

+1.5V JDIMM2

+1.5V

D

1

2

5

DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5

B

DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53

DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63

PCH_SMBDATA PCH_SMBCLK

PCH_SMBDATA PCH_SMBCLK



+0.75VS

206 208

BELLW_80001-1021 CONN@

2

SP07000P700

A

Compal Secret Data

Security Classification Issued Date

A

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

DDRIII DIMMB Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

12

of

57

5

4

3

2

1

+3VS

PCH_RTCX1 XTAL@

2

PCH_RTCX2

10M_0402_5% YH1

1

2

1

CH1

close to YH1 D

+RTCVCC

@

2

32.768KHZ_12.5PF_9H03200019 XTAL@

1

PCH_RTCX1_R

2

18P_0402_50V8J

2

1

CH3 XTAL@

2

1 10K_0402_5%

PCH_INTVRMEN

RH13

2

PCH_INTVRMEN

RH16

2

1

HDD_DET#

RH12

2

1 10K_0402_5%

PCH_SATALED# RH14

2

1 10K_0402_5%

@

PCH_RTCX1 0_0402_5%

RH30

RH10

330K_0402_5%

GCLK@

2

1

CH2

1

HDA_SDOUT 10P_0402_50V8J

SERIRQ

HDA_BIT_CLK 10P_0402_50V8J

UH1

D

1

@

R3@

+3VS

330K_0402_5% CH4 XTAL@ 18P_0402_50V8J

INTVRMEN

* H：Integrated L：Integrated

+RTCVCC

2 RH2

1

VRM enable VRM disable

2

SM_INTRUDER#

BD82HM76-SLJ8E-C1_BGA989~D

1M_0402_5%

HDA_RST# 33_0402_5%

2

HDA_SYNC_R 33_0402_5%

RH7

1

1

1M_0402_5%

HDA_SPKR

HDA_SPKR

T10

HDA_RST#

K34

HDA_SDIN0

E34

HDA_SYNC

QH1 BSS138_SOT23 1 2 @ RH9 0_0402_5%

2 RH8

3

D

1

HDA_SDIN0

G34 C34 A34

1

ME_EN

2 HDA_SDOUT 1K_0402_1%

RH11

A36

HDA_SDOUT

1

HDA_SDOUT_AUDIO

2

HDA_SDOUT 33_0402_5%

RH15

C36 N32

RH24 100_0402_1%

1

J3

PCH_JTAG_TMS_R

H7

PCH_JTAG_TDI_R

K5

PCH_JTAG_TDO_R

H1

PCH_JTAG_TMS

PCH_JTAG_TCK PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

1

@

2

1

@

2

1

@

RH44 PCH_JTAG_TDI

LPC

HDA_SYNC SPKR HDA_RST# HDA_SDIN0

RH48 PCH_JTAG_TDO

SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXP

HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

HDA_SDO HDA_DOCK_EN# / GPIO33

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

HDA_DOCK_RST# / GPIO13 SATA5RXN SATA5RXP SATA5TXN SATA5TXP

JTAG_TCK JTAG_TMS JTAG_TDI

SATAICOMPO SATAICOMPI

JTAG_TDO SATA3COMPI

2

2 PCH_JTAG_TCK

HDA_BCLK

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA3RCOMPO

PCH_SPI_CLK

T3

PCH_SPI_CS0#

Y14

PCH_SPI_CS1#

T1

B

SERIRQ

PCH_JTAG_TDI_R

RH26 100_0402_1%

RH25 100_0402_1%

2

PCH_JTAG_TCK

INTVRMEN

1

PCH_JTAG_TMS_R

1

1

PCH_JTAG_TDO_R

@ RH20 200_0402_1%

2

@ RH19 200_0402_1%

2

@ RH18 200_0402_1%

2

+3V_PCH

1

+3V_PCH

1

+3V_PCH

INTRUDER#

LDRQ0# LDRQ1# / GPIO23

RH70

PCH_SPI_SI

V4

PCH_SPI_SO

U3

PCH_JTAG_TMS_R 0_0402_5% PCH_JTAG_TDI_R 0_0402_5% 2 PCH_JTAG_TDO_R 0_0402_5%

SPI_CLK

SATA3RBIAS

D36

LPC_FRAME#

LPC_FRAME#

V5

SERIRQ

SERIRQ

1 1

HDA_SDOUT RH23

L=>security measures defined in the Flash Descriptor will be in effect (default)

2

HDA_SYNC

SATA_PRX_DTX_N0

SATA_PRX_DTX_P0

SATA_PTX_DRX_N0_C

SATA_PTX_DRX_P0_C

2 0.01U_0402_16V7K 2 0.01U_0402_16V7K

HDD

This signal has a weak internal pull-down On Die PLL VR is supplied by 1.5V when smapled high 1.8V when sampled low Needs to be pulled High for Huron River platfrom

AM10 AM8 AP11 AP10 SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 SATA_PTX_DRX_N2 SATA_PTX_DRX_P2

SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 SATA_PTX_DRX_N2 SATA_PTX_DRX_P2



2

HDA_SYNC

ODD

1

RH32

1K_0402_5%

AB8 AB10 AF3 AF1

RTC Battery

Y7 Y5 AD3 AD1

+RTCBATT

Y3 Y1 AB3 AB1

Y10

SATA_COMP

1

2

RH21

37.4_0402_1%

W=20mils

+1.05VS_SATA3

AB12 AB13

SATA3_COMP

1

RBIAS_SATA3

49.9_0402_1%

1

2

+CHGRTC

2

RH28

SATALED# SATA0GP / GPIO21

SPI_MISO

SATA1GP / GPIO19

P3

PCH_SATALED#

V14

HDD_DET#_R

P1

BBS_BIT0_R

2

1

DH1 BAT54CW_SOT323-3

1

+3VLP

JUMP_43X39

750_0402_1%~D

@ RH268 1

2

PCH_SATALED#

2 0_0402_1% 1 10K_0402_5%

RH29

W=20mils

JP12

2

RH22

AH1

RH34 1K_0402_5%

+CHGRTC

+1.05VS_VCC_SATA

Y11

+RTCVCC W=20mils 1

SPI_MOSI

C

+3V_PCH

AD7 AD5 AH5 AH4

SPI_CS0# SPI_CS1#

1 1K_0402_5%

@

= Disabled *Low High = Enabled

H=>Flash Descriptor Security will be overridden

E36 K36

AM3 AM1 AP7 SATA_PTX_DRX_N0 CH7 AP5 SATA_PTX_DRX_P0 CH8

+3V_PCH

ME debug mode , this signal has a weak internal PD



2

L34

FWH4 / LFRAME# SRTCRST#

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

1

N34

HDA_SYNC

RTCRST#

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

3

HDA_BIT_CLK

RTCX2

C38 A38 B37 C37

1

HDA_SYNC_AUDIO

K22 C17

2 RH6

S

C

G22

SPI

1

D20

PCH_SRTCRST# SM_INTRUDER# CLRP2 SHORT PADS PCH_INTVRMEN ME CMOS CLP1 & CLP2 place near DIMM

+5VS

2

HDA_RST_AUDIO#

HDA_BIT_CLK 33_0402_5%

G

2

2 RH5

PCH_RTCRST#

HDA_SDO FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

SATA 6G

1

C20

RTCX1

SATA

CH6 1U_0603_10V6K

1

2

20K_0402_5%

1

2

RH4

HDA_BITCLK_AUDIO

PCH_RTCX2

20K_0402_5%

1

2

A20

RTC

2

PCH_RTCX1

SA00005FH1L

IHDA

1 RH3

CMOS CLRP1 SHORT PADS

R1@

JTAG

CH5 1U_0603_10V6K

2

1

1

UH1A +RTCVCC

1 1K_0402_5%

@

LOW=Default *HIGH=No Reboot

SA00005FH2L

keep away hot spot

2

HDA_SPKR RH17

Reserve for RF please close to UH1

2

1 RH1

HDD_DET#

HDD_DET#

CH12 1U_0603_10V6K

B

2

+3VS

BD82HM76-SLJ8E-C1_BGA989~D

+3V_PCH +3V_PCH +3V_PCH

SPI ROM FOR WIN8( 2MByte )

2 51_0402_5%

RH38

1 RH40

PCH_SPI_WP# 3.3K_0402_5%

1 RH36 2 RH37

UH2

2 0_0402_1% 1 33_0402_5%

PCH_SPI_CS1#_R PCH_SPI_SO_R PCH_SPI_WP#

2

1 2 3 4

CS# SO WP# GND

PCH_SPI_CS0# PCH_SPI_SO

X76@

VCC HOLD# SCLK SI

8 7 6 5

RH265

2 0_0402_1% 1 33_0402_5%

PCH_SPI_CS0#_R 1 2 PCH_SPI_SO_L 3 PCH_SPI_WP#

4

PCH_SPI_HOLD# PCH_SPI_CLK_R PCH_SPI_SI_R

2 RH27 2 RH39

133_0402_5% 133_0402_5%

1

2 UH6

1 RH264 2

CH98

PCH_SPI_CLK PCH_SPI_SI

CS# SO/SIO1 WP# GND

X76@

VCC HOLD# SCLK SI/SIO0

8 7 6 5

PCH_SPI_HOLD# PCH_SPI_CLK_L PCH_SPI_SI_L

2 RH266 2 RH267

133_0402_5% PCH_SPI_CLK 1 PCH_SPI_SI 33_0402_5%

EN25Q32B-104HIP_SO8

EN25QH16-104HIP_SO8

PCH_SPI_HOLD# 3.3K_0402_5%

EON EN25Q32B-104HIP_SO8

1

A

@

EON EN25QH16-104HIP_SO8

ZZZ

SPIEON@

ZZZ

SPIWB@

2

CH99 10P_0402_50V8J

ZZZ SPIMXIC@

X7644031L07 4

X7644031L08

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

X7644031L09 3

A

Compal Secret Data

Security Classification Issued Date

5

SPI ROM FOR ME ( 4MByte )

@

@

2

@ RH263 3.3K_0402_5%

1

RH35

PCH_SPI_CS1# PCH_SPI_SO

1

2

2

2

2

+3V_PCH

1

1

PCH_JTAG_TCK

@ RH33 3.3K_0402_5%

0.1U_0402_16V7K

1

CH11 @ RH262 3.3K_0402_5%

+3V_PCH

0.1U_0402_16V7K

+3V_PCH

1

NEC flash issue.

2

Title

PCH (1/8) SATA/HDA/SPI/LPC Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

13

of

57

5

4

3

2

1

1

SMBCLK

2

RH45

UH1B

Y40 Y39 J2

LAN_CLKREQ#

RH75 1 RH76 1 RH77 2

CLK_PCIE_WLAN# CLK_PCIE_WLAN +3VS WLAN_CLKREQ#

@ @

2 0_0402_1% 2 0_0402_1% 1 10K_0402_5%

PCIE_WLAN# PCIE_WLAN WLAN_CLKREQ#

AB49 AB47 M1 AA48 AA47

RH79 2

+3VS

1 10K_0402_5%

GPIO20

V10 Y37 Y36

RH74 2

+3V_PCH

GPIO25

A8 Y43 Y45

RH66 1

+3V_PCH

2 10K_0402_5%

GPIO26

L12

SML0DATA

C13

PCH_HOT#

E14

SML1CLK

M16

SML1DATA

PERN7 PERP7 PETN7 PETP7 PERN8 PERP8 PETN8 PETP8

CL_CLK1 CL_DATA1 CL_RST1#

RH83 1

2 10K_0402_5%

GPIO44

+3V_PCH

RH84 1

2 10K_0402_5%

GPIO56

L14 AB42 AB40 E6 V40 V42

RH88 1

+3V_PCH

2 10K_0402_5%

GPIO45

T13 V38 V37

RH90 1

+3V_PCH

RH91 1 RH92 1

CLK_CPU_ITP# CLK_CPU_ITP

@ @

2 10K_0402_5% 2 0_0402_1% 2 0_0402_1%

GPIO46

CLK_BCLK_ITP# CLK_BCLK_ITP

K12 AK14 AK13

CLKIN_DMI2# CLKIN_DMI2 CLKIN_DMI# CLKIN_DMI CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA# CLKIN_SATA CLK_PCH_14M

20090512 add double mosfet prevent ATI M92 electric leakage

P10

PEG_A_CLKRQ# / GPIO47 CLKOUT_PCIE0N CLKOUT_PCIE0P PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P

CLKOUT_PEG_A_N CLKOUT_PEG_A_P CLKOUT_DMI_N CLKOUT_DMI_P

PCIECLKRQ1# / GPIO18 CLKOUT_DP_N CLKOUT_DP_P CLKOUT_PCIE2N CLKOUT_PCIE2P CLKIN_DMI_N CLKIN_DMI_P

PCIECLKRQ2# / GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P

CLKIN_GND1_N CLKIN_GND1_P

PCIECLKRQ3# / GPIO25 CLKIN_DOT_96N CLKIN_DOT_96P CLKOUT_PCIE4N CLKOUT_PCIE4P CLKIN_SATA_N CLKIN_SATA_P

PCIECLKRQ4# / GPIO26

M10

PEG_A_CLKRQ#

AB37 AB38

CLK_PEG_VGA# CLK_PEG_VGA

AV22 AU22

CLK_CPU_DMI# CLK_CPU_DMI

+3VS

PEG_A_CLKRQ#

CLK_PEG_VGA# CLK_PEG_VGA



CLKOUT_PCIE5N CLKOUT_PCIE5P

REFCLK14IN

CLK_CPU_DMI# CLK_CPU_DMI



RH71 2.2K_0402_5%

SMBCLK

6

BF18 BE18

CLKIN_DMI# CLKIN_DMI

BJ30 BG30

CLKIN_DMI2# CLKIN_DMI2

G24 E24

CLKIN_DOT96# CLKIN_DOT96

AK7 AK5

CLKIN_SATA# CLKIN_SATA

CLKIN_PCILOOPBACK

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PCH_SMBCLK

3

SMBDATA

XTAL25_IN XTAL25_OUT

XCLK_RCOMP

4

PCH_SMBCLK

K45

CLK_PCH_14M

H45

CLK_PCI_LPBACK

V47 V49

XTAL25_IN XTAL25_OUT

Y47

XCLK_RCOMP

RH41

CLK_PCI_LPBACK

2

2

PCIECLKRQ7# / GPIO46 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

TP_SMBDATA

0_0402_1%

+3VS

RH80 2.2K_0402_5%

SMBCLK

CLKOUTFLEX1 / GPIO65

TP_SMBCLK

0_0402_1%

K43

CLK_FLEX0

F47

CLK_14M_R

H47 K49

@

T53

PAD~D

2 @ T54 22_0402_5% 2 CLK_LAN_25M_R @ 1 RH270 22_0402_5% 2 1 DGPU_PRSNT# +3VS RH269 10K_0402_5% UMA@

PAD~D

1 RH125

6

@

@

1

TP_SMBCLK

DMN66D0LDW-7_SOT363-6 @ QH7A

CLK_LAN_25M

RH81 2.2K_0402_5%

3

SMBDATA

4

TP_SMBDATA

DMN66D0LDW-7_SOT363-6 @ QH7B

RH261 10K_0402_5%

+3V_PCH

@ CH25 22P_0402_50V8J

@ RH63

2

1

1

2

33_0402_5%

2 @ CH26 22P_0402_50V8J

1

1

close to RH270 LAN_X1

1 RH31

2 CLK_LAN_25M 0_0402_5%

6

PCH_SMLCLK

DMN66D0LDW-7_SOT363-6 QH3A

GCLK@

Reserve for EMI please close to UH1

CH28 12P_0402_50V8J XTAL@

1

SML1CLK

2

5

1

2

@

+1.05VS_VCCDIFFCLKN

90.9_0402_1%

A

SML1DATA

4

3

PCH_SMLDATA

DMN66D0LDW-7_SOT363-6 QH3B

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

@

1

B

1 RH85

DIS@

3 GND OSC

GND OSC

2

1 RH87

PCH_SMBDATA

PCIECLKRQ6# / GPIO45 CLKOUTFLEX0 / GPIO64

4

2

XTAL@

PCH_SMBDATA

QH2B RH82 1 @ 2 0_0402_5%

CLKOUT_PCIE6N CLKOUT_PCIE6P

CLKOUT_PCIE7N CLKOUT_PCIE7P

DMN66D0LDW-7_SOT363-6

PEG_B_CLKRQ# / GPIO56

@ RH65 CLK_PCI_LPBACK 2 33_0402_5%

1

C

RH72 2.2K_0402_5%

1

DMN66D0LDW-7_SOT363-6 QH2A RH78 1 @ 2 0_0402_5%

XTAL25_OUT

YH2

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

+3VS

+3VS

PCIECLKRQ5# / GPIO44

1M_0402_5%

2

XTAL@

1

25MHZ_10PF_7V25000014

CH27 12P_0402_50V8J

2 2 2 2 2 2 2 2 2

AM12 AM13

XTAL25_IN 0_0402_5%

XTAL25_IN

A

1 1 1 1 1 1 1 1 1

If use extenal CLK gen, please place close to CLK gen else, please place close to PCH

+3V_PCH

XTAL@

1

RH54 RH55 RH56 RH57 RH58 RH59 RH60 RH61 RH62

No support iAMT

2

CLK_PCH_14M

2

1K_0402_5%

1

1

GCLK@

RH89

2

M7 T11

BD82HM76-SLJ8E-C1_BGA989~D R1@

PCH_X1

PCH_HOT#

RH64 10K_0402_5%

close to YH2

10K_0402_5%

1 RH53

Total device

PERN6 PERP6 PETN6 PETP6

2

RH86 DRAMRST_CNTRL_PCH

G12

10K_0402_5%

1

PCH_HOT#

2

+3V_PCH

B

CLK_CPU_ITP# CLK_CPU_ITP

SML1DATA / GPIO75

RH52

RH93

V45 V46



PERN5 PERP5 PETN5 PETP5

SML1CLK / GPIO58

DRAMRST_CNTRL_PCH

1

*PCIE REQ power rail: suspend: 0 3 4 5 6 7 core: 1 2

1 10K_0402_5%

SML1ALERT# / PCHHOT# / GPIO74

SML0CLK

2

PCIE_LAN# PCIE_LAN

PERN4 PERP4 PETN4 PETP4

DRAMRST_CNTRL_PCH

2

2 0_0402_1% 2 0_0402_1% 1 10K_0402_5%

SML0DATA

A12 C8

2

1



@ @

SML0CLK

D

2 2.2K_0402_5%

1

SMBALERT#

SML0ALERT# / GPIO60

2.2K_0402_5%

5

WLAN (Mini Card)--->

RH67 1 RH68 1 RH69 2

CLK_PCIE_LAN# CLK_PCIE_LAN +3V_PCH LAN_CLKREQ#

2

RH51

PERN3 PERP3 PETN3 PETP3

2.2K_0402_5%

1

SML1DATA

2

10/100 LAN --->

2

RH50

2



C

SMBDATA

1

1

BE38 BC38 AW38 AY38

C9

2.2K_0402_5%

1 RH49

SML1CLK

2

BG40 BJ40 AY40 BB40

RH47 SML0DATA

MEMORY

1

BJ38 BG38 AU36 AV36

SMBCLK

5

BG37 BH37 AY36 BB36

SMBDATA

SMBALERT#

2

BF36 BE36 AY34 BB34

PERN2 PERP2 PETN2 PETP2

E12 H14

2

BG36 BJ36 AV34 AU34

SMBCLK

2

1

2 0.1U_0402_10V7K~D 2 0.1U_0402_10V7K~D

BE34 BF34 BB32 AY32

SMBALERT# / GPIO11

SMBUS

CH21 1 CH22 1

PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 PCIE_PTX_WLANRX_N2_C PCIE_PTX_WLANRX_P2_C

PERN1 PERP1 PETN1 PETP1

Link

PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 PCIE_PTX_WLANRX_N2 PCIE_PTX_WLANRX_P2

2 0.1U_0402_10V7K~D 2 0.1U_0402_10V7K~D

Controller



CH19 1 CH20 1

FLEX CLOCKS

WLAN (Mini Card)--->

PCIE_PRX_LANTX_N1 PCIE_PRX_LANTX_P1 PCIE_PTX_LANRX_N1 PCIE_PTX_LANRX_P1

CLOCKS

D



2.2K_0402_5%

1

SML0CLK

PCI-E*

10/100 LAN --->

BG34 BJ34 AV32 AU32

+3V_PCH

2

RH46 PCIE_PRX_LANTX_N1 PCIE_PRX_LANTX_P1 PCIE_PTX_LANRX_N1_C PCIE_PTX_LANRX_P1_C

2.2K_0402_5%

1

SMBDATA

4

3

2

Title

PCH (2/8) PCIE/SMBUS/CLK Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

14

of

57

5

4

3

2

1

UH1C



DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

BE24 BC20 BJ18 BJ20



DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

AW24 AW20 BB18 AV18



DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

AY24 AY20 AY18 AU18

DMI0RXN DMI1RXN DMI2RXN DMI3RXN

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 FDI_INT

+1.05VS

BJ24 1

2 1

RH100

BH21

FDI_FSYNC0

DMI_IRCOMP

FDI_FSYNC1

DMI2RBIAS

FDI_LSYNC0

4mil width and place within 500mil of the PCH

Reserve for ESD CH105

1

FDI_LSYNC1

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7







BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7







AW16

FDI_INT

AV12

FDI_FSYNC0

FDI_INT

BC10

FDI_FSYNC1

AV14

FDI_LSYNC0

BB10

FDI_LSYNC1

D

UH1D

DSWVRMEN

C

C12

T57

1 SYS_PWROK RH104

@

2 SYS_PWROK_R

1

@

2

@

RH106

2

L10

0_0402_1%

B13

PM_DRAM_PWRGD

PM_DRAM_PWRGD

L22

0_0402_1%

1

PCH_PWROK

1

EC_RSMRST#

P12

0_0402_1%

RH105

K3

XDP_DBRESET#

XDP_DBRESET#

@

RH108

2PCH_RSMRST#_R

C21

0_0402_1%

K16

SUSWARN# Reserve for ESD PBTN_OUT#

1

PBTN_OUT#

@

RH110

1

2

E20

0_0402_1%

System Power Management

PAD~D

Please close to PCH

SUSACK# SYS_RESET# SYS_PWROK PWROK APWROK DRAMPWROK RSMRST#

DPWROK

A18

CTRL_CLK CTRL_DATA LVDS_IBG PAD~D

WAKE#

SUS_STAT# / GPIO61 SUSCLK / GPIO62 SLP_S5# / GPIO63 SLP_S4#

SUSWARN#/SUSPWRDNACK/GPIO30 PWRBTN#

SLP_S3# SLP_A#

T56



FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

2

LVDS_DDC_CLK LVDS_DDC_DATA



LVDS_ACLKLVDS_ACLK+

1

ACIN

2

2

AC_PRESENT_R

RB751V-40_SOD323-2 GPIO72

H20 E10

ACPRESENT / GPIO31

SLP_SUS#

B9

A10

BATLOW# / GPIO72

PMSYNCH

RI#

SLP_LAN# / GPIO29

AF37 AF36



LVDS_A0LVDS_A1LVDS_A2-



LVDS_A0+ LVDS_A1+ LVDS_A2+



LVDS_BCLKLVDS_BCLK+



LVDS_B0LVDS_B1LVDS_B2-



LVDS_B0+ LVDS_B1+ LVDS_B2+

AK39 AK40

LVDS_A0LVDS_A1LVDS_A2-

AN48 AM47 AK47 AJ48

LVDS_A0+ LVDS_A1+ LVDS_A2+

AN47 AM49 AK49 AJ47

LVDS_BCLKLVDS_BCLK+

AF40 AF39

LVDS_B0LVDS_B1LVDS_B2-

AH45 AH47 AF49 AF45

LVDS_B0+ LVDS_B1+ LVDS_B2+

AH43 AH49 AF47 AF43

PCH_RSMRST#_R

WAKE#

1

RH128

2 RH103

N3 G8

PCIE_WAKE#

0_0402_5%

PM_CLKRUN#

SUS_STAT#

N14 SUSCLK

1

T58

@

RH107

PAD~D

2

SUSCLK_R

0_0402_1%

D10

PM_SLP_S5#

H4

PM_SLP_S4#

F4

PM_SLP_S3#

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#



N48 P49 T49

CRT_DDC_CLK CRT_DDC_DATA

T39 M40

G10 G16

PM_SLP_SUS#

AP14

H_PM_SYNC

Place close to PCH RI#

T45 P39

LVDS_ACLKLVDS_ACLK+

M47 M49

DH4

T40 K47

L_BKLTEN L_VDD_EN

SDVO_TVCLKINN SDVO_TVCLKINP

L_BKLTCTL

SDVO_STALLN SDVO_STALLP

L_DDC_CLK L_DDC_DATA

SDVO_INTN SDVO_INTP

K14

BD82HM76-SLJ8E-C1_BGA989~D

T59

PAD~D

H_PM_SYNC

CRT_IREF

Can be left NC when IAMT is not support on the platfrom

If not using integrated LAN,signal may be left as NC.

T43 T42

AP43 AP45 AM42 AM40 AP39 AP40

L_CTRL_CLK L_CTRL_DATA LVD_IBG LVD_VBG

SDVO_CTRLCLK SDVO_CTRLDATA

LVD_VREFH LVD_VREFL LVDSA_CLK# LVDSA_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

0_0402_1% @

CLKRUN# / GPIO32

@

VGA_PWM

AE48 AE47

FDI_FSYNC0

1

J47 M45 P45

LVDS_DDC_CLK LVDS_DDC_DATA

DSWODVREN

E22 PCH_DPWROK

ENBKL PCH_ENVDD

ENBKL PCH_ENVDD

SYS_PWROK_R

0.1U_0402_16V7K

@ CH103 0.1U_0402_16V7K

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

DDPB_AUXN DDPB_AUXP DDPB_HPD

HDMI

LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED CRT_DDC_CLK CRT_DDC_DATA

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK DDPC_CTRLDATA DDPC_AUXN DDPC_AUXP DDPC_HPD

mDP

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_CTRLCLK DDPD_CTRLDATA

CRT_HSYNC CRT_VSYNC DAC_IREF CRT_IRTN

1

2

BG25

DMI_IRCOMP 49.9_0402_1% 2 RBIAS_CPY 750_0402_1%~D

RH99

DMI_ZCOMP

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

Digital Display Interface

BC24 BE20 BG18 BG20

LVDS

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

CRT

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

FDI



DMI

D

DDPD_AUXN DDPD_AUXP DDPD_HPD

DMC

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

P38 M39

PCH_SDVO_CTRLCLK PCH_SDVO_CTRLDATA

AT49 AT47 AT40

HDMI_DET

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

HDMI_A2N_VGA HDMI_A2P_VGA HDMI_A1N_VGA HDMI_A1P_VGA HDMI_A0N_VGA HDMI_A0P_VGA HDMI_A3N_VGA HDMI_A3P_VGA

HDMI_DET



HDMI_A2N_VGA HDMI_A2P_VGA HDMI_A1N_VGA HDMI_A1P_VGA HDMI_A0N_VGA HDMI_A0P_VGA HDMI_A3N_VGA HDMI_A3P_VGA







P46 P42 AP47 AP49 AT38

C

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 M43 M36 AT45 AT43 BH41 BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

BD82HM76-SLJ8E-C1_BGA989~D RH115 1K_0402_0.5%

R1@

2

Check EC for S3 S4 LED +3V_PCH R1@ B

GPIO72

RH116 1

2 10K_0402_5%

RI#

RH117 1

PCIE_WAKE#

RH118 1

AC_PRESENT_R

RH121 1

2 200K_0402_5%

DSWODVREN

RH119

2

SUSWARN#

RH124 1

2 10K_0402_5%

DSWODVREN

RH122

2

CH29

2

SUSCLK

2 10K_0402_5% @

B

1

@

+RTCVCC

10P_0402_50V8J

2 10K_0402_5% 1 330K_0402_5%

Reserve for RF please close to UH1

1

2

1

2

RH120 @

1 330K_0402_5%

RH126 1

WAKE#

RH127 1

EC_RSMRST#

2 10K_0402_5%

RH132

*

2 10K_0402_5%

1 2

1

2 2

1 1

VGATE

1 2

IN1 IN2

3

PCH_PWROK

2

1

1 OUT

SYS_PWROK

SYS_PWROK

RH239

LVDS_DDC_DATA

2

PCH_SDVO_CTRLCLK PCH_SDVO_CTRLDATA

2.2K_0402_5% @

RH238

4

LVDS_DDC_CLK

2.2K_0402_5%

RH234

VCC

PCH_PWROK

GND

2

1

1

PM_CLKRUN#

2.2K_0402_5%

RH233

UH3

CTRL_DATA

2.2K_0402_5%

RH138

5

2

ENBKL

100K_0402_5%

8.2K_0402_5%

2

RH137

CH30 0.1U_0402_16V7K

2

CTRL_CLK

2.2K_0402_5%

1 RH136 @

1

PCH_ENVDD

2.2K_0402_5%

RH135 +3VS

2 100K_0402_5%

RH134

1 RH133

LVDS_IBG

2.37K_0402_1%

1

+3VS

DSWODVREN - On Die DSW VR Enable H：Enable L：Disable

PM_CLKRUN#

10K_0402_5%

RH123

2

CRT_DDC_CLK

2.2K_0402_5% @

2

CRT_DDC_DATA

2.2K_0402_5%

MC74VHC1G08DFT2G_SC70-5

A

A

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

PCH (3/8) DMI/FDI/PM/GFX/DP Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

15

of

57

5

4

3

2

1

+3VS

UH1E

2 8.2K_0402_5%

PCI_PIRQA#

1

2 8.2K_0402_5%

PCI_PIRQD#

RH131

1

2 8.2K_0402_5%

PCI_PIRQB#

RH141

1

2 8.2K_0402_5%

PCI_PIRQC#

RH142

1

2 8.2K_0402_5%

GPIO51

RH146

1

2 8.2K_0402_5%

GPIO5

RH147

1

2 8.2K_0402_5%

GPIO52

RH148

1

2 8.2K_0402_5%

WL_OFF#

RH151

1

2 8.2K_0402_5%

ODD_DA#

RH153

1

2 8.2K_0402_5%

GPIO4

RH154

1

2 8.2K_0402_5%

PXS_PWREN

BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

+3VS

RH140

SSI: Port 1 USB Conn 1 Port 2 USB Conn 2 Port 3 USB Conn 3

C

2

1 10K_0402_5%

B21 M20 AY16 BG46

DGPU_HOLD_RST#

PT: Port 1 USB Conn JUSB2 Port 2 USB Conn JUSB1 Port 3 Cancel



USB3RN1_JUSB2 USB3RN2_JUSB1



USB3RP1_JUSB2 USB3RP2_JUSB1



USB3TN1_JUSB2 USB3TN2_JUSB1



USB3TP1_JUSB2 USB3TP2_JUSB1

USB3RN1_JUSB2 USB3RN2_JUSB1

USB3RP1_JUSB2 USB3RP2_JUSB1

USB3TN1_JUSB2 USB3TN2_JUSB1

USB3TP1_JUSB2 USB3TP2_JUSB1

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PXS_PWREN

WL_OFF#

D47 E42 F46

ODD_DA# GPIO4 GPIO5

G42 G40 C42 D44

GPIO51

Reserve for ESD

WL_OFF#

ODD_DA#

CH104

2

1

K40 K38 H38 G38

DGPU_HOLD_RST#C46 C44 GPIO52 E40 PXS_PWREN

DGPU_HOLD_RST#

BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30

PCH_PLTRST#

0.1U_0402_16V7K

PAD~D

Please close to PCH

K10

T60 @ PCH_PLTRST#

PCH_PLTRST#

C6

B

RH144 RH145

CLK_PCI_LPBACK CLK_PCI_LPC

CLK_PCI_LPBACK CLK_PCI_LPC

2 1

1 22_0402_5% 2 22_0402_5% PAD~D PAD~D PAD~D

T61 @ T62 @ T63 @

CLK_PCI0 CLK_PCI1 CLK_PCI2 CLK_PCI3 CLK_PCI4

H49 H43 J48 K42 H40

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

TP21 TP22 TP23 TP24

RSVD23 RSVD24 RSVD25 RSVD26 RSVD27

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

PIRQA# PIRQB# PIRQC# PIRQD#

RSVD28 RSVD29

USB

1

RH130

RSVD

RH129

PCI

D

REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P USBRBIAS# USBRBIAS

AY7 AV7 AU3 BG4

D

AT10 BC8 AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 AV5 AV10

Intel Anti-Theft Techonlogy

High=Endabled NV_ALE Low=Disable(floating)

* +1.8VS

@ RH139 1

NV_ALE

2 1K_0402_5%

AT8 AY5 BA2 AT12 BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB20_JUSB2_N0 USB20_JUSB2_P0 USB20_JUSB1_N1 USB20_JUSB1_P1 USB20_JUSB3_N2 USB20_JUSB3_P2 USB20_USBDB_N3 USB20_USBDB_P3

C33

USBRBIAS

USB20_JUSB2_N0 USB20_JUSB2_P0 USB20_JUSB1_N1 USB20_JUSB1_P1 USB20_JUSB3_N2 USB20_JUSB3_P2 USB20_USBDB_N3 USB20_USBDB_P3

USB20_MINI1_N8 USB20_MINI1_P8 USB20_TOUCH_N9 USB20_TOUCH_P9 USB20_CR_N10 USB20_CR_P10 USB20_CAM_N11 USB20_CAM_P11







USB20_MINI1_N8

USB20_MINI1_P8

USB20_TOUCH_N9

USB20_TOUCH_P9

USB20_CR_N10

USB20_CR_P10

USB20_CAM_N11

USB20_CAM_P11

USB Conn JUSB2 USB Conn JUSB1 USB Conn JUSB3

SSI: Port 0 Port 1 Port 2 Port 3 Port 4 Port 6 Port 12

USB Conn 1 USB Conn 4 (DB) USB Conn 2 USB Conn 3 Mini Card (WLAN) Card Reader Camera

PT: Port 0 Port 1 Port 2 Port 3 Port 8 Port 9 Port 10 Port 11

USB Conn JUSB2 USB Conn JUSB1 USB Conn JUSB3 USB Conn 4 (DB) Mini Card (WLAN) Touch panel Card Reader Camera

C

USB Conn 4 (DB)

Mini Card (WLAN) Touch panel Card Reader Camera

Within 500 2mils 1 RH143

22.6_0402_1%

+3V_PCH

B33

PME# PLTRST#

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

A14 K20 B17 C16 L16 A16 D14 C14

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

USB_OC0# USB_OC1# USB_OC2# USB_OC3#



USB_OC0#

10K_0402_5%

2

1 RH156

USB_OC1#

10K_0402_5%

2

1 RH158

USB_OC2#

10K_0402_5%

2

1 RH160

USB_OC3#

10K_0402_5%

2

1 RH166

USB_OC6#

10K_0402_5%

2

1 RH167

USB_OC5#

10K_0402_5%

2

1 RH170

USB_OC4#

10K_0402_5%

2

1 RH189

USB_OC7#

10K_0402_5%

2

1 RH211

B

CH31

2

1

CLK_PCI1

BD82HM76-SLJ8E-C1_BGA989~D R1@

@ 10P_0402_50V8J

Reserve for RF please close to PCH +3VS

1

2

@

0_0402_5%

2

RH149

+3VS CH101

1

O G

PLT_RST#

IN1

3

1

IN2

1

PCH_PLTRST#

2

SN74AHC1G08DCKR_SC70-5

2

4

P

UH5

1

2 0.1U_0402_25V6K

5

@ RH150 10K_0402_5%

RH155 100K_0402_5%

RH157 10K_0402_5%

1

2

@

A

A

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

PCH (4/8) PCI/USB/NVRAM Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

16

of

57

5

4

3

2

1

UH1F +3V_PCH

EC_SCI#

E38

EC_SMI#

EC_SMI#

C10

EC_LID_OUT# 1 RH73

EC_LID_OUT#

@

2 PCH_LID_SW_IN#

1

BT_ON#

@ RH225 10K_0402_5%

ODD_DETECT#

2

2

@ RH202 10K_0402_5%

2

@ RH179 10K_0402_5%

PCH_GPIO38

1

PCH_GPIO39

1

1

PCH_GPIO57

KB_DET#

C

System ID PCH_GPIO57

PCH_GPIO39

PCH_GPIO38

LOW

VAW00 15''

INSPIRON

Entry

HIGH

VAW10 17''

VOSTRO

Mainstream

G2

TACH0 / GPIO17 SCLOCK / GPIO22

E8

PCH_GPIO27

E16

PCH_GPIO28

P8

BT_ON#

K1

GPIO35

K4

ODD_DETECT#

V8

PCH_GPIO37

M5

PCH_GPIO38

N2

PCH_GPIO39

M3

PCH_GPIO48

V13

GPIO49

V3

PCH_GPIO57

D6

GPIO27

TS_VSS2 TS_VSS3 SATA2GP / GPIO36 TS_VSS4 SLOAD / GPIO38

BD1 BD49 BE1 BE49 BF1

GPIO28

BF49

H：On-Die voltage regulator enable L：On-Die PLL Voltage Regulator disable 2

VSS_NCTF_15

SATA5GP / GPIO49

VSS_NCTF_16

GPIO57

VSS_NCTF_17

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3

VSS_NCTF_21

VSS_NCTF_5

B47

1

NC_1

SDATAOUT1 / GPIO48

VSS_NCTF_4

A6

On-Die PLL Voltage Regulator This signal has a weak internal pull up

P4

GATEA20

AU16

PCH_PECI_R

P5

KB_RST#

1

PCH_PECI_R

0_0402_5%

AY11 AY10 T14 AY1

KB_RST#

H_CPUPWRGD H_THERMTRIP#_C 1 390_0402_5% INIT3_3V#

2

@

H_PECI

RH161



1

2

H_THERMTRIP#

H_THERMTRIP#

RH162

2

@ CH102 0.1U_0402_10V7K~D

Place CH102 close to RH161 & PCH.

DF_TVS

AH8 AK11

@ RH163 10K_0402_5%

AH10 AK10

INIT3_3V

This signal has weak internal PU, can't pull low

P37

C

SDATAOUT0 / GPIO39

B3

GPIO1

A40

SATA3GP / GPIO37

VSS_NCTF_18

+3VS

@ RH165

DF_TVS TS_VSS1

A5

*

INIT3_3V#

GPIO35

A46

B

THRMTRIP#

STP_PCI# / GPIO34

A45

1

PROCPWRGD

GPIO28

A44

2 RH164

RCIN#

GPIO24 / MEM_LED

A4

10K_0402_5%

A20GATE

SATA4GP / GPIO16

T5

KB_DET#

+3VS

C41

RH159 10K_0402_5%

PECI

D40

VGA_PWRGD

TACH7 / GPIO71

GPIO15

U2

PCH_GPIO22

@ RH181 10K_0402_5%

2

@ RH182 10K_0402_5%

2

2

@ RH244 10K_0402_5%

VGA_PWRGD

+3VS

1

+3VS

1

+3V_PCH

TACH6 / GPIO70

TACH3 / GPIO7

LAN_PHY_PWR_CTRL / GPIO12

0_0402_1% GPIO16

TACH5 / GPIO69

TACH2 / GPIO6

GPIO8

C4

TACH1 / GPIO1

PAD~D

VSS_NCTF_22 VSS_NCTF_23

VSS_NCTF_6

VSS_NCTF_24

VSS_NCTF_7

VSS_NCTF_25

VSS_NCTF_8

VSS_NCTF_26

VSS_NCTF_9

VSS_NCTF_27

VSS_NCTF_10

VSS_NCTF_28

VSS_NCTF_11

VSS_NCTF_29

VSS_NCTF_12

VSS_NCTF_30

VSS_NCTF_13

VSS_NCTF_31

VSS_NCTF_14

VSS_NCTF_32

BG2 BG48 BH3

PLACE RH150 CLOSE TO THE BRANCHING POINT ( TO CPU and NVRAM CONNECTOR)

BH47

Due to remove VCCDFERM jumper(PJP66), need to change the power rail to +1.8V_RUN for D12" only

BJ4 BJ44 BJ45

+1.8VS

RH149 need to close to CPU 1

H36

EC_SCI#

ODD_EN# @ T64

BJ46

RH152 2.2K_0402_5%

BJ5 BJ6

2

RH241

GPIO6

D

ODD_EN# GPIO69

1

PCH_GPIO28 10K_0402_5%

B41

1

PCH_LID_SW_IN# 1K_0402_5%

C40

2

1

TACH4 / GPIO68

CPU/MISC

1

2

A42

GPIO

2 RH240

GPIO1

BMBUSY# / GPIO0

2

T7

NCTF

D

C2

1

H_SNB_IVB#

2

DF_TVS 1K_0402_1%

RH358

C48 D1 D49

DMI & FDI Termination Voltage

E1 E49

Set to Vss when LOW DF_TVS

F1

Set to Vcc when HIGH B

F49

BD82HM76-SLJ8E-C1_BGA989~D R1@

+3VS

PCH_GPIO28

1K_0402_5%

ODD_DETECT#

1

GPIO16

1

2 200K_0402_5% RH171

2 10K_0402_5% RH172

BT_ON#

1

PCH_GPIO37 @ RH173

FDI TERMINATION VOLTAGE OVERRIDE

*

2

1

2 8.2K_0402_5% RH174

PCH_GPIO27 10K_0402_5%

KB_RST#

2 10K_0402_5% RH175

+3V_PCH

LOW - Tx, Rx terminated to same voltage (DC Coupling Mode)

1

VGA_PWRGD

1

2 10K_0402_5% RH242

PCH_GPIO22

1

2 10K_0402_5% RH176

+3VS

GPIO35

1

GPIO49

1

2 10K_0402_5% RH177

RH168

2

RH169

1

@

1 1K_0402_5%

PCH_GPIO37

2

PCH_GPIO37

PCH_GPIO28 needs to be connected to XDP_FN8 PCH_GPIO35 needs to be connected to XDP_FN9 PCH_GPIO15 needs to be connected to XDP_FN16

10K_0402_5%

2 10K_0402_5% RH180

GPIO6

Please refer to Huron River Debug Board DG 0.5

1

2 10K_0402_5% RH184

EC_SMI#

1

2 10K_0402_5% RH183 PCH_GPIO48

1

ODD_EN#

1

2 10K_0402_5% RH245

A

2 10K_0402_5%

A

RH178

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

PCH (5/8) GPIO/CPU/MISC Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

17

of

57

5

4

3

2

1

Reserve for LVDS issue +VCCA_LVDS D

D

1

2

CH106

@

1U_0402_6.3V6K

+1.05VS

+1.05VS

VSSADAC

1

RH186

VSSALVDS VCCTX_LVDS[1] VCCTX_LVDS[2]

+1.05VS_VCCDPLLEXP

AN19

+VCCA_LVDS

2

2

BJ22

+VCCAPLLEXP

1UH_LB2012T1R0M_20%~D

2

Near AP43

+VCCTX_LVDS CH39 1 0.01U_0402_16V7K

AM38 AP36

2

AN16 AN17

2@ +1.05VS

AN21 AN26 AN27 AP21

@

2

1

2

AP24

CH49 1U_0402_6.3V6K

2

1

CH48 1U_0402_6.3V6K

2

1

CH47 1U_0402_6.3V6K

1

2

CH45 10U_0805_4VAM~D

+3VS

1

CH46 1U_0402_6.3V6K

AP23 1

AP26 AT24 AN33

VCCIO[15] VCCIO[16]

VCCIO[19]

2925mA

VCC3_3[6]

V33

1

+3VS_VCC3_3_6

VCC3_3[7]

V34 2

RH188 @

2@

@ +1.05VS

1

BG6

2+1.05VS_VCCDPLL_FDI 0_0805_1%

AP17

AT16

AU20

3.3

0.001

VccADPLLA

1.05

0.08

VccADPLLB

1.05

0.08

VccCore

1.05

+3VS

1.3

VccDMI

1.05

0.042

CH43 0.1U_0402_10V7K~D

VCCIO[22] VCCIO[23] VCCIO[24]

VCCDMI[1]

AT20

1

+VCCP_VCCDMI

1 @

20mA VCCCLKDMI

AB36

1

2

VCCIO[26]

VCCDFTERM[1]

190mA VCCDFTERM[2]

VCC3_3[3]

VCCVRM[2] VccAFDIPLL

VCCDFTERM[3] VCCDFTERM[4]

2

+1.05VS

2 1U_0402_6.3V6K

0_0805_1% CH50 1U_0402_6.3V6K

AG16 +VCCPNAND

AG17

RH193

1

AJ16

1

AJ17

VCCDMI[2]

20mA

VCCSPI

V1

2.925 1.01

VccSPI

3.3

0.02

VccDSW

3.3

0.003

VccpNAND

1.8

0.19

VccRTC

3.3

6 uA

VccSus3_3

3.3

0.119

2

0_0805_1%

2

0_0805_1%

2

1

+3V_VCCPSPI

2

RH196

0_0805_1%

VccSusHDA

3.3 / 1.5

VccVRM

1.8 / 1.5

0.01 0.16

+1.8VS

@

VCCIO[27]

1.05 1.05

CH44

1

+1.05VS_VCC_DMI_CCI

VCCIO[25]

RH191

+VCCP

RH190

@

VCCIO[21]

VccIO VccASW

+VCCAFDI_VRM

RH195

+VCCP_VCCDMI

0.266

VccADAC

C

2

CH52 0.1U_0402_10V7K~D

1

+1.05VS_VCCAPLL_FDI

3.3

0.1uH inductor, 200mA

+VCCP_VCCDMI

FDI

0_0603_5%~D

0.001

Vcc3_3

0_0805_1%

1

VCCVRM[3]

DFT / SPI

Place CH53 Near BG6 pin

1

CH53 1U_0402_6.3V6K

2 RH194

AP16

5

2

VCCIO[20]

0.1U_0402_10V7K~D +VCCAFDI_VRM

0.001

V5REF_Sus

0.1UH_MLF1608DR10KT_10%_1608

1

2

1

VCCIO[18]

CH51

@

0.001

5

LH2

2

AP37

VCCIO[17]

+1.05VS

2

+1.8VS

CH41

1

@

BH29

+3VS_VCCA3GBG

1

2

22U_0805_6.3V6M CH40 0.01U_0402_16V7K

2

AN34

1.05

+3VS RH185 1 @ 0_0805_1%

AM37

S0 Iccmax Current (A)

V5REF

V_PROC_IO

CH34 10U_0805_4VAM~D

AK37

VCCAPLLEXP

HVCMOS

0_0603_5%~D

Place CH40 Near BJ22 pin

B

4.7UH_LQM18FN4R7M00D_20%

1

Voltage

1

VCCIO[28]

DMI

1+VCCAPLLEXP_R 1

1

RH192 0_0805_1%

VCCTX_LVDS[4]

AK36

1

2

@ LH3

CH42 10U_0805_4VAM~D

2 RH187

C

2 0_0603_1%

@

1 U47 2

1mA VCCALVDS

VCCIO

@

+VCCADAC

CH33 0.1U_0402_10V7K~D

CRT

VCCADAC

U48

CH32 0.01U_0402_16V7K

1mA

VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17]

60mA VCCTX_LVDS[3] +1.05VS

Voltage Rail

LH1

LVDS

2

+3VS

1300mA

VCC CORE

2

1

CH38 1U_0402_6.3V6K

1

CH37 1U_0402_6.3V6K

2

CH36 1U_0402_6.3V6K

2

1

CH35 10U_0805_4VAM~D

1

AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31

PCH Power Rail Table

POWER

UH1G

VccCLKDMI

1.05

0.02

VccSSC

1.05

0.095

VccDIFFCLKN

1.05

0.055

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.06

B

+3V_PCH

@

2 BD82HM76-SLJ8E-C1_BGA989~D

RH243

1

1 0_0603_5%~D

+3VS

CH54 1U_0402_6.3V6K

R1@

2

+1.5VS

+VCCAFDI_VRM

@

1

RH197

2 0_0603_1%

+VCCAFDI_VRM

1

2

CH100 1U_0402_6.3V6K

A

A

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

PCH (6/8) PWR Size

Document Number

Rev 1.0

LA-9102P Date:

Wednesday, September 26, 2012 1

Sheet

18

of

57

5

4

3

2

1

VCC3_3 = 266mA detal waiting for newest spec

+1.05VS @

1

2

2 0_0603_1%

@

AL24

1

2

@ CH62 1U_0402_6.3V6K

AA21

+1.05VS

1

2

CH66 22U_0805_6.3V6M

2

CH65 22U_0805_6.3V6M

AA24 1

AA26 AA27 AA29 AA31

1

2

1

2

CH70 1U_0402_6.3V6K

2

CH69 1U_0402_6.3V6K

1

+3VS

CH68 1U_0402_6.3V6K

AC26 C

AC27 AC29 AC31 AD29

@

1

2

RH215

AD31

0_0805_1%

W21 LH5 10UH_LBR2012T100M_20%

W23

2

+3VS_VCC_CLKF33

2

1

2

W24

CH75 1U_0402_6.3V6K

1

@

CH74 10U_0805_10V6K

1

W26 W29 W31 W33

119mA VCCSUS3_3[7]

VCCAPLLDMI2

VCCSUS3_3[8] VCCIO[14] DCPSUS[3]

VCCSUS3_3[9] VCCSUS3_3[10]

VCCASW[1] VCCASW[2]

VCCIO[34]

1010mA

1mA V5REF_SUS

VCCASW[3] VCCASW[4] VCCASW[5] VCCASW[6] VCCASW[7] VCCASW[8] VCCASW[9] VCCASW[10] VCCASW[11] VCCASW[12] VCCASW[13] VCCASW[14] VCCASW[15]

DCPSUS[4] VCCSUS3_3[1]

1mA V5REF VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCC3_3[1] VCC3_3[8]

VCCASW[16]

VCC3_3[4]

N16

+VCCRTCEXT @

2

1

RH219

1

+1.05VM_VCCSUS

0_0603_5%~D

Y49

+VCCAFDI_VRM

1

+3V_VCCPUSB

T24

1

V23 2

V24 P24

@

RH205 +3V_VCCAUBG

1

2

T26

+1.05VS_VCCAUPLL

M26

+PCH_V5REF_SUS

AN23

+VCCA_USBSUS

AN24

+3V_VCCPSUS_1

P34

+PCH_V5REF_RUN

1

1 2

P20

2

2

1

2

@

0_0603_1%

VCCASW[20]

W16

0_0805_1%

1

+3VS_VCCPPCI

1

AF13

VCCVRM[4]

VCCIO[13]

2

2

@

0_0603_1%

CH76 0.1U_0402_10V7K~D

2 2

@

+PCH_V5REF_RUN

CH72 1U_0603_10V6K

+3VS

RH216

1

C

DH3 RB751S40T1_SOD523-2~D

1

CH73 0.1U_0402_10V7K~D

2

2

DCPRTC

RH212 100_0402_1%

+3V_PCH

2

RH214

1

1

CH64 0.1U_0603_25V7K

+3VS

+3VS

AA16

+VCC3_3_2

+PCH_V5REF_SUS

2

@

1

+3VS_VCCPCORE

AJ2

DH2 RB751S40T1_SOD523-2~D

1

+5VS

RH217

VCC3_3[2]

RH208 100_0402_1%

+3V_PCH

0_0603_1%

CH71 1U_0402_6.3V6K

VCCASW[18] VCCASW[19]

+3V_PCH

1

RH213

P22

T34

2

2

@

RH210

+3V_VCCPSUS

1

N22

+1.05VS

0_0603_1%

1

N20

+5V_PCH

+VCCA_USBSUS

@

RH209

2 +3V_PCH 0_0603_1% @ 2 +3V_PCH 0_0603_1%

1 RH206

+3VS

VCCIO[12] CH79 0.1U_0402_10V7K~D

T23

VCCASW[17]

VCCIO[5] +1.05VS

1

VCC3_3[5]

VCCSUS3_3[6] AA19

RH203 20K_0402_5%

+VCCSUS1

RH207

2

AL29

CH57 0.1U_0402_10V7K~D

+VCCDPLL_CPY

2

BH23

2

+VCCAPLL_CPY_PCH

2

+1.05VS

1

1

PCH_PWR_EN#

1

@

2

T29

1

CH59 10U_0805_10V6K

0_0805_5%

VCCIO[33]

CH56 1U_0402_6.3V6K

2

T38

D

2

T27

@

@ CH58 0.1U_0402_10V7K~D

P28

CH63 1U_0402_6.3V6K

2

1

1

CH61 0.1U_0402_10V7K~D

1

VCCIO[32]

USB

+VCCAPLL_CPY

DCPSUSBYP

PCI/GPIO/LPC

2

1

3

0_0603_1%

CH67

+3VS_VCC_CLKF33

VCCIO[31]

@ LH4 10UH_LBR2012T100M_20%

RH204

3mA

Clock and Miscellaneous

@

1

VCCIO[30] VCCDSW3_3

0_0603_1%

2

@

RH201

+1.05VS

1

0.1U_0402_10V7K~D

V12

RH200

P26

CH60 0.1U_0402_10V7K~D

T16

+PCH_VCCDSW

VCCIO[29]

2

@

G

+VCCPDSW

2

VCCACLK

1

+1.05VS_VCCUSBCORE

D

CH55 0.1U_0402_10V7K~D

N26

S

1 AD49

1

+5V_PCH

QH5 AO3419L_SOT23-3

2 0_0603_1%

@

RH199

+1.05VS

+5VALW

POWER

UH1J

2

RH198

1

D

VCCDMI = 42mA detal waiting for newest spec

+VCCACLK 0_0603_5%~D

1

+3V_PCH

1

2

2

+1.05VS_SATA3

0_0603_1%

@

1

CH77 0.1U_0402_10V7K~D

AH13 AH14

2

+1.05VS_SATA3

2

RH218

1

0_0805_1%

+1.05VS

CH78 1U_0402_6.3V6K

2 BD47

+1.05VS_VCCA_B_DPL

BF47

1

2

@

RH223

+1.05VS_VCCDIFFCLKN

+1.05VS_SSCVCC

AG33

+1.05VS_VCCDIFFCLKN

1U_0402_6.3V6K

0_0603_1% 1

2

+1.05VS

2

1 CH84 1U_0402_6.3V6K

CH85 0.1U_0402_10V7K~D

1

2

@

2

+V_CPU_IO

0_0603_1%

1

2

1 CH87 4.7U_0603_6.3V6K

2

LH7 10UH_LBR2012T100M_20% +1.05VS

1

2

A22 1

1

2

+1.05VS_VCCA_A_DPL

1

2

+1.05VS_VCCA_B_DPL

+ A

2

1

2

1 +

2

CH95 220U_B2_2.5VM_R35

1

CH94 220U_B2_2.5VM_R35

LH8 10UH_LBR2012T100M_20%

RH222

VCCIO[2]

VCCIO[4]

95mA

AC16

1

+1.05VS_VCC_SATA

2 +1.05VS 0_0805_1%

@

AC17

1

AD17

DCPSST

+1.05VS

B

2

+1.05VS

DCPSUS[1] DCPSUS[2]

V_PROC_IO 1mA

VCCASW[22] VCCASW[23] VCCASW[21]

T21 V21 T19

2

1

2

1

2

1

2

VCCRTC

10mA VCCSUSHDA

P32

1

+VCCSUSHDA RH229

1

BD82HM76-SLJ8E-C1_BGA989~D 0.1U_0402_10V7K~D

CH93

2

R1@

@

@

2

+3V_PCH

0_0603_1%

If it support 3.3V audio signals POP:RH244 Depop RH245 / RH246 If it support 1.5V audio signals POP:RH245 / RH246 Depop R244

A

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

1 0_0805_5%

@ CH81 10U_0805_10V6K

CH97 1U_0402_6.3V6K

0_0805_1%

CH96 1U_0402_6.3V6K

RH232

2 +VCCA_DPLL_L

1

+VCCAFDI_VRM +1.05VS_VCC_SATA

+RTCVCC

@

1

@ CH86 1U_0402_6.3V6K

BJ8

CH89 0.1U_0402_10V7K~D

1 RH227

CH88 0.1U_0402_10V7K~D

2

T17 V19

CH92 1U_0402_6.3V6K

+VCCP

AF11

@ RH221

2

+1.05VM_VCCSUS

CH91 0.1U_0402_10V7K~D

1

VCCSSC

@ LH6 10UH_LBR2012T100M_20% 2 +VCCSATAPLL_R

1

+VCCSATAPLL +VCCAFDI_VRM

2 V16

2 0_0603_1%

CH90 0.1U_0402_10V7K~D

@

VCCIO[7] VCCDIFFCLKN[1] VCCDIFFCLKN[2] 55mA VCCDIFFCLKN[3]

VCCIO[3] CH82 1U_0402_6.3V6K

+VCCSST

1 RH224

VCCVRM[1]

AK1

1

2

VCCIO[6] VCCAPLLSATA

RH231 150_0402_1%

+1.05VS

AF17 AF33 AF34 AG34

MISC

B

VCCADPLLB 80mA

CH80

HDA

1

VCCADPLLA 80mA

CH83 1U_0402_6.3V6K

+1.05VS_VCCA_A_DPL +VCCDIFFCLK

AF14

2

2 0_0603_1%

CPU

@

RTC

1 RH220

SATA

+1.05VS

4

3

2

Title

PCH (7/8) PWR Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

19

of

57

5

4

3

2

1

UH1I

UH1H

H5 D

AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3

C

B

VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79]

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

BD82HM76-SLJ8E-C1_BGA989~D R1@

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3

VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258]

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

D

C

B

BD82HM76-SLJ8E-C1_BGA989~D R1@

A

A

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

PCH (8/8) VSS Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

20

of

57

5

4

3

2

1

+3VS

@

RV13 4.7K_0402_5%

@

1

BKOFF#

BKOFF#

D

2

QV3 2N7002BKW_SOT323-3~D

2

1

3

1

QV5 BSS138_SOT23~D

G

1

3

EC_ENVDD

2

S

RV18 10K_0402_5%

1

W=60mils

1

2

+LCDVDD +LCDVDD

1 CV20 4.7U_0805_10V4Z

4

USB20_CAM_P11

4

1

USB20_CAM_N11

3

1

2

LV24

2

3

USB20_CAM_P11_R

2

USB20_CAM_N11_R

@

1

2

CE_EN_R

CE_EN_R only for reserve.

2

RV210

CV18

1

EMC@

1

CV21 0.1U_0402_16V7K

2

0_0402_5%

DBC_EN_R

2

RV208

@

0_0402_5%



LVDS_A0LVDS_A0+

LVDS_A0LVDS_A0+



LVDS_A1LVDS_A1+

LVDS_A1LVDS_A1+



LVDS_A2LVDS_A2+

LVDS_A2LVDS_A2+



LVDS_ACLKLVDS_ACLK+

LVDS_ACLKLVDS_ACLK+



LVDS_B0LVDS_B0+

LVDS_B0LVDS_B0+



LVDS_B1LVDS_B1+

LVDS_B1LVDS_B1+



LVDS_B2LVDS_B2+

LVDS_B2LVDS_B2+



LVDS_BCLKLVDS_BCLK+

LVDS_BCLKLVDS_BCLK+

W=60mils

2

BAT54C-7-F_SOT23-3

D

2 3

EC_ENVDD

5P_0402_50V8C @

G

1

1

D

PCH_ENVDD

CV19 0.1U_0402_16V7K

1

5P_0402_50V8C CV17 @

QV4 AO3419L_SOT23-3 WCM-2012HS-900T_4P

S DV7

1

CH751H-40PT_SOD323-2~D

2

G

2

PCH_ENVDD

2

3

RV17 56K_0402_5%

10K_0402_5% RV16

2

2 1

1 1

D

JLVDS DISPOFF#

DV6

W=60mils

RV15 47K_0402_5%

RV14 100_0402_1%

2

CH751H-40PT_SOD323-2~D

S

2

+3VS

1

+5VALW

2

DV5 +LCDVDD

LVDS Conn.

1

LCD PWR CTRL



MIC_DATA MIC_CLK

MIC_DATA MIC_CLK

USB20_CAM_P11_R USB20_CAM_N11_R

2

1

MIC_CLK_R

1

RV30 0_0402_1% @

2

+3VS_CAM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

+LCDVDD +3VS

MIC_CLK_R

@ CV29 470P_0402_50V7K~D

MIC_DATA

LVDS_DDC_CLK LVDS_DDC_DATA

RV19 RV20

@ @

2 2

LCD_TEST EDID_CLK_LCD EDID_DATA_LCD INV_PWM DISPOFF#

LCD_TEST

1 1 0_0402_1% 0_0402_1%

@ CE_EN

CE_EN

RV62 1

2 0_0402_5%

CE_EN_R

DBC_EN

RV99 1

2 0_0402_5%

DBC_EN_R

D

S G

2

2

2 0_0805_1%

5P_0402_50V8C

1

CV26 0.1U_0603_50V_X7R

5P_0402_50V8C

1

CV27

CV28

2

LVDS_BCLK-

2 @ +LCDVDD_R 0_0402_1% RV31 0_0402_5%

DV8 LVDS_BCLK+

MIC_CLK_R

S

@

2 0_0805_5%

1

VGA_PWM

2

RV29

@

V I/O

USB20_CAM_P11_R

3

USB20_CAM_N11_R

INV_PWM

1

2 +3VS

RV231 @

+INV_PWR_SRC

2 +LCDVDD_R

6

@ QV9A

2 1

1

47K_0402_5% CV31 0.1U_0402_16V7K

2

3 2

@ QV9B 2N7002DW-7-F_SOT363-6

@

2

@

2

1 2

RV209

1

D

@ 2

RV33 100K_0402_5% @

G

@

1000P_0402_50V7K

RV34 100K_0402_5%

+3VS_CAM

5 4

S

3 1

1

1

+5VALW

QV8 SI2301CDS-T1-GE3_SOT23-3

CV319

B

680P_0402_50V7K

2

0_0603_1%

+3VS

2

* Reserved for LCD sequence tuning

+3VS_CAM

1

CV30

@

@ RV32 820_0805_1% 2N7002DW-7-F_SOT363-6

Webcam PWR CTRL

CMOS_ON#

V I/O

1 2

0_0402_1%

RV230 100K_0402_5%

B

V I/O

V BUS Ground

@

1

A

4

V I/O

IP4223CZ6_SO6~D @

+INV_PWR_SRC

QV7 2N7002BKW_SOT323-3~D

G

5 MIC_DATA

RV27 1

6

1

2

D

2

C

@

+5VS

2 +LCDVDD

1 RV28

1 EN_INVPWR

3

STARC_107K40-000001-G2 CONN@

SP01000XE00

* Reserved for EMI/ESD/RF need to close to JLVDS

@

2

1

PWR_SRC_ON

B+

D

+INV_PWR_SRC

1

3

1 2

RV24

RV26 100K_0402_5%

2

41 42 43 44 45 46

@

1

6 5 2 1

2

2

1

CV24 10U_0805_10V6K

RV25 100K_0402_5%

2

CV25 1000P_0402_50V7K

1

CV22

60mil

4

2

1

+INV_PWR_SRC

G1 G2 G3 G4 G5 G6

Place close to JLVDS

QV6 SI3457CDV-T1-E3_TSOP6~D +INV_PWR_SRC_R

B+

1

W=60mils

+LCDVDD

0.1U_0402_16V7K CV23

60mil

@ RV216 0_0402_5%

RV100 0_0402_5%

LCD backlight PWR CTRL

C

+3VS

0.1U_0402_16V7K

1

DBC_EN

1



1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

A

@

1

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

LVDS/webcam Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

21

of

57

5

4

3

2

1

W=40mils

Place close to JHDMI1 @



HDMI_A1N_VGA HDMI_A1P_VGA



HDMI_A2N_VGA HDMI_A2P_VGA

CV36 2 CV37 2

1 0.1U_0402_10V7K~D TMDS_TX0N 1 0.1U_0402_10V7K~D TMDS_TX0P

CV38 2 CV39 2

1 0.1U_0402_10V7K~D TMDS_TX1N 1 0.1U_0402_10V7K~D TMDS_TX1P

CV40 2 CV41 2

1

4

TMDS_TXCP

2

4

3

LV7

2 3

FV1

2 3 NC

+5VS

1

2

@ BAT1000-7-F_SOT23-3~D

TMDS_L_TXCP

1

1.5A_6V_1206L150PR~D

EMC@

+3VS

RV37 1

@

2 0_0402_5%

RV38 1

@

2 0_0402_5%

1 0.1U_0402_10V7K~D TMDS_TX2N 1 0.1U_0402_10V7K~D TMDS_TX2P

DV9 TMDS_L_TXCN

1

TMDS_TX0P

4

1

2

4

3

LV8

1

1

1

1

1 2

2

2

2

1

2

1

1

2

2

RV41 1 680_0402_1%

680_0402_1%

680_0402_1%

680_0402_1%

680_0402_1%

680_0402_1%

680_0402_1%

680_0402_1%

2

RV49

RV48

RV47

RV46

RV45

RV44

RV43

RV42

RV40 1

2

TMDS_L_TX0N

3

TMDS_L_TX0P

2 0_0402_5%

@

2 0_0402_5%

1

TMDS_TX1P

4

1

2

4

3

LV9

2 G

1

2

@ RV53 100K_0402_5%

S

TMDS_L_TXCN

RV50 1

2

TMDS_L_TX1N

TMDS_L_TXCP TMDS_L_TX0N

3

TMDS_L_TX1P

TMDS_L_TX0P TMDS_L_TX1N

EMC@ @

TMDS_L_TX1P TMDS_L_TX2N

2 0_0402_5% TMDS_L_TX2P

QV11 RV52 1

2N7002_SOT23-3

@

1

TMDS_TX2N

4

1

2

4

3

20 21 22 23

C

LOTES_ABA-HDM-022-K01 CONN@

2 0_0402_5%

WCM-2012HS-900T_4P TMDS_TX2P

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

2

TMDS_L_TX2P

3

TMDS_L_TX2N

DC232000B00

2

RV51

1

1

+3VS

D

3

C

0_0402_1%

DDC_DAT_HDMI DDC_CLK_HDMI

WCM-2012HS-900T_4P TMDS_TX1N

CV35

2

JHDMI

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

HDMI_HPLUG

EMC@ @

2

1

RV39 10K_0402_5%

WCM-2012HS-900T_4P TMDS_TX0N

1

1

HDMI_A0N_VGA HDMI_A0P_VGA

1 0.1U_0402_10V7K~D TMDS_TXCN 1 0.1U_0402_10V7K~D TMDS_TXCP

D

2



CV32 2 CV33 2

1

CV34

HDMI_A3N_VGA HDMI_A3P_VGA

0_1206_5%~D

2

+VDISPLAY_VCC

WCM-2012HS-900T_4P

1

TMDS_TXCN

RV36

2 0_0402_5%

10U_0603_6.3V6M

RV35 1

0.1U_0402_10V7K~D

D

LV10 RV54 1

B

EMC@ @

2 0_0402_5%

TMDS_TXCN

@ CV358

1

2 100P_0402_50V8J

TMDS_L_TXCN

CV349

1

2 3.3P_0402_50V8C~D

TMDS_TXCP

@ CV360

1

2 100P_0402_50V8J

TMDS_L_TXCP

CV350

1

2 3.3P_0402_50V8C~D

TMDS_TX0N

@ CV362

1

2 100P_0402_50V8J

TMDS_L_TX0N

CV351

1

2 3.3P_0402_50V8C~D

TMDS_TX0P

@ CV363

1

2 100P_0402_50V8J

TMDS_L_TX0P

CV352

1

2 3.3P_0402_50V8C~D

TMDS_TX1N

@ CV359

1

2 100P_0402_50V8J

TMDS_L_TX1N

CV353

1

2 3.3P_0402_50V8C~D

TMDS_TX1P

@ CV357

1

2 100P_0402_50V8J

TMDS_L_TX1P

CV354

1

2 3.3P_0402_50V8C~D

TMDS_TX2N

@ CV361

1

2 100P_0402_50V8J

TMDS_L_TX2N

CV355

1

2 3.3P_0402_50V8C~D

TMDS_TX2P

@ CV364

1

2 100P_0402_50V8J

TMDS_L_TX2P

CV356

1

2 3.3P_0402_50V8C~D

20111024 EMI ADD

B

20110805 EMI ADD

1

+3VS

RV57

C

2

QV13 MMBT3904_NL_SOT23-3

1

1

2

2

2

+5V_HDMI_DDC 2.2K_0402_5%

RV58

2

CV42 220P_0402_50V8J

DV11 BAV99-7-F_SOT23-3 @

3

1

@ RV59 200K_0402_5% RV55 100K_0402_5%

2

DDC_CLK_HDMI

HDMI_HPLUG

1

2

3

6

1

2 PCH_SDVO_CTRLCLK

QV12A DMN66D0LDW-7_SOT363-6

2

150K_0402_5%

5

1

1

HDMI_DET

1

2

@ 0_0402_1% RV56

@ DV10 RB751V-40_SOD323-2

B E

1

+5VS

+3VS

+3VS

PCH_SDVO_CTRLDATA

4

3

DDC_DAT_HDMI

1

2

RV60

2.2K_0402_5%

QV12B DMN66D0LDW-7_SOT363-6 A

A

46@

ROYALTY HDMI W/LOGO

Part Number RO0000002HM

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Description HDMI W/Logo:RO0000002HM

Compal Electronics, Inc. HDMI

Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

22

of

57

5

4

3

2

1

D

D

UG1

GCLKUMA@

SLG3NB244VTR TQFN 16P CLK GEN

SLG3NB244VTR SA000057I00 Intel-UMA SLG3NB300VTR SA00005RS00 Intel-DIS +RTCBATT

1

+RTCVCC

1

R787 GCLK@ 330_0402_5%

2

2

R788 @ 0_0402_5%

+VCCP

+LAN_IO

+3VLP C5

C7

2

C8

2

1 0.1U_0402_16V7K

C6

2

1 GCLK@ 0.1U_0402_16V7K

0.1U_0402_16V7K

Depop if GCLK with UMA

1 GCLK@

1 0.1U_0402_16V7K

GCLK@

GCLK@

2

GCLK@

1

22U_0805_6.3V6M

1

C9

2

UG1

2

10 +3VLP

15

+3VALW

2

+1.8VGS

11

VBAT

VDD_RTC_OUT

VDD

CLK_X1

2

25MHz_B

Y1

3 GCLK@

SLG3NB274VTR_TQFN16_2X3

GCLK@

OSC

GND

OSC

GND

2

6 5

PCH_RTCX1_R

GCLK@ 2 R785 VGA_X1_R 1 10_0402_1% LAN_X1_R 1 GCLK@ 2 R782 33_0402_5% 2 R783 PCH_X1_R 1 0_0402_5%

VGA_X1

PCH_X1

LAN_X1

1

GCLK@

XTAL_IN XTAL_OUT

1 1

2

VDDIO_25M_B

GCLK@

12P_0402_50V8J~D

C12

25MHz_A

4 7 13

C11

VDDIO_25M_A

9 12

GND4

CLK_X1 CLK_X2

1 16

27MHz

GND1 GND2 GND3

3

+VCCP

VDDIO_27M

2

GCLK@ C14 5P_0402_50V8C

17

8

+LAN_IO

C

GCLK@

+V3.3A 32kHz

Place close to UG1.8

14

2.2U_0603_6.3V6K C10

+1.8VGS

C

GCLKDIS@

4

25MHZ_10PF_7V25000014

1

12P_0402_50V8J~D

CLK_X2

B

B

R784 0_0402_5% LAN_X1_R

1

2 @

reserved for swing level adjustment (close to U2)

A

A

Compal Secret Data

Security Classification Issued Date

2012/09/25

Deciphered Date

2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. GCLK

Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

23

of

57

5

4

3

2

1

D

D

GFX PCIE LANE REVERSAL

PEG_HTX_C_GRX_P[7..0]

PEG_HTX_C_GRX_N[7..0]

SA00004WI0L

PEG_HTX_C_GRX_P[7..0]

UV1A

PEG_GTX_C_HRX_P[7..0]

THR1@

PEG_HTX_C_GRX_N[7..0]

PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0

AA38 Y37

PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1

Y35 W36

PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2

W38 V37

PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3

V35 U36

PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_N4

U38 T37

PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_N5

T35 R36

PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_N6

R38 P37

PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_N7

P35 N36 N38 M37 M35 L36 L38 K37 K35 J36 J38 H37 H35 G36

PCIE_RX0P PCIE_RX0N

PCIE_TX0P PCIE_TX0N

PCIE_RX1P PCIE_RX1N

PCIE_TX1P PCIE_TX1N

PCIE_RX2P PCIE_RX2N

PCIE_TX2P PCIE_TX2N

PCIE_RX3P PCIE_RX3N

PCIE_TX3P PCIE_TX3N

PCIE_RX4P PCIE_RX4N

PCIE_TX4P PCIE_TX4N

PCI EXPRESS INTERFACE

C

PEG_GTX_C_HRX_N[7..0]

PCIE_RX5P PCIE_RX5N PCIE_RX6P PCIE_RX6N PCIE_RX7P PCIE_RX7N PCIE_RX8P PCIE_RX8N PCIE_RX9P PCIE_RX9N PCIE_RX10P PCIE_RX10N PCIE_RX11P PCIE_RX11N PCIE_RX12P PCIE_RX12N PCIE_RX13P PCIE_RX13N

PCIE_TX5P PCIE_TX5N PCIE_TX6P PCIE_TX6N PCIE_TX7P PCIE_TX7N PCIE_TX8P PCIE_TX8N PCIE_TX9P PCIE_TX9N PCIE_TX10P PCIE_TX10N PCIE_TX11P PCIE_TX11N PCIE_TX12P PCIE_TX12N PCIE_TX13P PCIE_TX13N

Y33 Y32

PEG_GTX_C_HRX_P[7..0]

PEG_GTX_C_HRX_N[7..0]

PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0

220nF_0402_16V7K 220nF_0402_16V7K

2 2

1 CV43 DIS@ 1 CV44 DIS@

PEG_GTX_C_HRX_P0 PEG_GTX_C_HRX_N0

W33 PCIE_CRX_C_GTX_P1 W32 PCIE_CRX_C_GTX_N1

220nF_0402_16V7K 220nF_0402_16V7K

2 2

1 CV45 DIS@ 1 CV46 DIS@

PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_N1

U33 PCIE_CRX_C_GTX_P2 U32 PCIE_CRX_C_GTX_N2

220nF_0402_16V7K 220nF_0402_16V7K

2 2

1 CV47 DIS@ 1 CV48 DIS@

PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2

U30 PCIE_CRX_C_GTX_P3 U29 PCIE_CRX_C_GTX_N3

220nF_0402_16V7K 220nF_0402_16V7K

2 2

1 CV49 DIS@ 1 CV50 DIS@

PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_N3

T33 T32

220nF_0402_16V7K 220nF_0402_16V7K

2 2

1 CV51 DIS@ 1 CV52 DIS@

PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_N4

LVDS Interface UV1G

LVDS CONTROL

T30 T29

PCIE_CRX_C_GTX_P4 PCIE_CRX_C_GTX_N4

PCIE_CRX_C_GTX_P5 PCIE_CRX_C_GTX_N5

220nF_0402_16V7K 220nF_0402_16V7K

2 2

1 CV53 DIS@ 1 CV54 DIS@

PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_N5

P33 PCIE_CRX_C_GTX_P6 P32 PCIE_CRX_C_GTX_N6

220nF_0402_16V7K 220nF_0402_16V7K

2 2

1 CV55 DIS@ 1 CV56 DIS@

PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_N6

P30 PCIE_CRX_C_GTX_P7 P29 PCIE_CRX_C_GTX_N7

220nF_0402_16V7K 220nF_0402_16V7K

2 2

1 CV57 DIS@ 1 CV58 DIS@

PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_N7

VARY_BL DIGON

TXCLK_UP_DPF3P TXCLK_UN_DPF3N TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N TXOUT_U3P TXOUT_U3N

N33 N32

AK27 AJ27

AK35 AL36 AJ38 AK37 AH35 AJ36 AG38 AH37

C

AF35 AG36

LVTMDP

TXCLK_LP_DPE3P TXCLK_LN_DPE3N

N30 N29

TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N

L33 L32

TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N

L30 L29

TXOUT_L3P TXOUT_L3N

K33 K32 J33 J32

AP34 AR34 AW37 AU35 AR37 AU39 AP35 AR35 AN36 AP37

216-0833000-A11-THAMES-XT-M2_FCBGA962~D THR1@

G38 F37 F35 E37 B

PCIE_RX14P PCIE_RX14N

PCIE_TX14P PCIE_TX14N

PCIE_RX15P PCIE_RX15N

PCIE_TX15P PCIE_TX15N

K30 K29 H33 H32 RV61 2

1 0_0402_5%

@

B

+3VGS CLOCK

1

2

+1.0VGS RV198 [email protected]_0402_1%~D

+3VGS

5

PCIE_REFCLKP PCIE_REFCLKN CALIBRATION

2

AH16

1K_0402_5%

AA30

PCIE_CALRN

Y30

1.27K_0402_1% 1 TH@

Y29

2K_0402_1% 1 TH@ 1K_0402_1% 1 MS@

2 RV63 2 RV65 2 RV203

DGPU_HOLD_RST#

2

PCH_PLTRST#

+1.0VGS

IN1 IN2

Install 2K for Thames/Seymour

PERSTB

OUT

4

GPU_RST#

UV13 MC74VHC1G08DFT2G_SC70-5 DIS@

2

1

CV326 0.1U_0402_25V6K DIS@

1

GPU_RST#

PWRGOOD

3

PCIE_CALRP

DIS@

1 RV64

1

VCC

CLK_PEG_VGA CLK_PEG_VGA#

AB35 AA36

GND



CLK_PEG_VGA CLK_PEG_VGA#

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

Place CV326 Close to UV13

THAMES XT M2

2

DIS@ RV66 100K_0402_5%

UV1

THR3@

SA00004WI1L

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

UV1

MSR1@

UV1

SA00005X10L

A

MARS-PRO_FCBGA962~D

MSR3@

SA00005X10L

A

MARS-PRO_FCBGA962~D

MARS Pro UV1

CHR1@

UV1

CHR3@

Issued Date Chelsea Pro

5

4

Chelsea Pro

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2012/09/25

Deciphered Date

2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3

2

Title

ATI_ThamesXT_M2_PCIE/LVDS Size

Document Number

Rev 1.0

LA-9102P Date:

Tuesday, September 25, 2012 1

Sheet

24

of

57

4

3

2

Sam 1GR3@

X7644031L13

RV69

1

RV71

1

1

K4W2G1646E-BC11

Samsung 2GB SA00005SH0L(R1) SA00005SH1L(R3)

128Mx16 (2G)

RV68

RV69

0

RV71

1

1

H5TQ2G63DFR-11C

*

Hynix 2GB SA00003YO2L(R1) SA00003YO3L(R3)

128Mx16 (2G)

RV67

RV70

1

RV71

0

AJ21 AK21

PT

TX1P_DPC1P TX1M_DPC1N TX2P_DPC0P TX2M_DPC0N TXCDP_DPD3P TXCDM_DPD3N TX3P_DPD2P TX3M_DPD2N

SWAPLOCKA SWAPLOCKB

DPD

TX4P_DPD1P TX4M_DPD1N

1

H5TQ2G63DFR-11C

I2C

Micron 2GB SA00005XB0L(R1) SA00005XB1L(R3)

128Mx16 (2G)

DPC

AK26 AJ26

TX5P_DPD0P TX5M_DPD0N

STRAPS

+3VGS

VDDCI_VID

GPU_VID5

C

10K_0402_5% 1 TH@ 10K_0402_5% 1 TH@ 10K_0402_5% 1 @ 10K_0402_5% 1 10K_0402_5% 1 10K_0402_5% 1

2 2 2

@

2

@ @

2 2

10K_0402_5% 1 TH@ 10K_0402_5% 1 @ 10K_0402_5% 1 @

RV75 GPU_GPIO0 RV76 GPU_GPIO1 RV77 GPU_GPIO2



RV78 AC_BATT

GPU_VID4 GPU_VID3 GPU_VID2

RV79 GPU_GPIO8 RV80 GPU_GPIO9

2 2 2

RV89 1 @

RV81 GPU_GPIO11 RV82 GPU_GPIO12 RV83 GPU_GPIO13

GPU_VID1 T78

T79

+3VGS 10K_0402_5% 1 10K_0402_5% 1 10K_0402_5% 1

@ @ @

2 RV85 2 RV86 2 RV87

GPIO24_TRSTB GPIO25_TDI GPIO27_TMS

10K_0402_5% 1

@

2 RV88

GPIO26_TCK

AH20 AH18 AN16 AH23 AJ23 AH17 AJ17 AK17 AJ13 GPU_GPIO8 AH15 GPU_GPIO9 AJ16 GPU_VID5 AK16 GPU_GPIO11 AL16 GPU_GPIO12 AM16 GPU_GPIO13 AM14 GPU_VID4 AM13 GPU_VID3 AK14 GPU_VID2 AG30 THM_ALERT# AN14 2 10K_0402_5% AM17 AL13 GPU_VID1 GPIO21_BBEN AJ14 AK13 VGA_CLKREQ#_R AN13 GPIO24_TRSTB AM23 AN23 GPIO25_TDI AK23 GPIO26_TCK AL24 GPIO27_TMS AM24 GPIO28_TDO AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24 GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 VGA_SMB_DA2_R VGA_SMB_CK2_R AC_BATT VDDCI_VID

2 0_0402_5% 2 0_0402_5%

AK24

R RB

GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCSB GPIO_23_CLKREQB JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF_HPD5 GENERICG_HPD6

G GB B BB

DAC1

HSYNC VSYNC

+1.8VGS DIS@ 2 RV93 DIS@ 2 RV95

+1.8VGS

(Thames 75mA) 1U_0402_6.3V6K DIS@ CV83

1

1

AVDD AVSSQ VDD1DI VSS1DI R2/NC R2B/NC G2/NC G2B/NC B2/NC B2B/NC C/NC Y/NC COMP/NC H2SYNC/GENLK_CLK V2SYNC/GENLK_VSYNC

2

2 1 BLM15BD121SN1D_0402

AW35

1U_0402_6.3V6K DIS@ CV87

2

0.1U_0402_16V7K DIS@ CV88

10U_0603_6.3V6M DIS@ CV86

TS_FDO 1

1

2

AV33 AU34 AW34

2

+DPLL_VDDC

XTALIN XTALOUT

1

2

GPU_THERMAL_D+ AF29 GPU_THERMAL_D- AG29

Add 12/6 for MLPS AK32

TS_FDO

(Thames 5mA)

YV1 XTALDIS@ 27MHZ_10PF_7V27000050

GND

1

2

GND 4

2

2

1

1

3

1

2

3 CV94 10P_0402_50V8J

CV95 10P_0402_50V8J

XTALDIS@

2

10mil AJ32 AJ33

DIS@ CV93 0.1U_0402_16V7K

DIS@ CV91 10U_0603_6.3V6M

+1.8VGS

DIS@ CV92 1U_0402_6.3V6K

XTALIN

AL31

DIS@ (1.8V@20mA TSVDD) LV16 1 2 +TSVDD BLM15BD121SN1D_0402 1 1 1

RV97 XTALDIS@ 1M_0402_5% XTALOUT

R2SET/NC

AUX1P AUX1N

XTALIN XTALOUT

DDC2CLK DDC2DATA XO_IN AUX2P AUX2N

XO_IN2

DPLUS DMINUS

GPIO21

RESERVED

BIOS_ROM_EN

GPIO_22_ROMCSB

ENABLE EXTERNAL BIOS ROM

ROMIDCFG(2:0)

GPIO[13:11]

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

1

ACIN

2

XXX

V2SYNC

IGNORE VIP DEVICE STRAPS

0

DDCCLK_AUX4P DDCDATA_AUX4N

THERMAL

DDCCLK_AUX5P DDCDATA_AUX5N TS_FDO DDC6CLK DDC6DATA

TS_A/NC

DDCCLK_AUX7P DDCDATA_AUX7N

TSVDD TSVSS

RSVD

H2SYNC

RSVD

GENERICC

AUD[1]

HSYNC

AU22 AV21

AUD[0]

VSYNC

AT23 AR22

AMD RESERVED CONFIGURATION STRAPS

AU20 AT19

ACIN_65W

AT21 AR20

AE36 AD35

GPIO21

H2SYNC

AC36 AC38

GPIO2

+1.8VGS

AD34 AE34

+AVDD

AC33 AC34

+VDD1DI

10mil

65mA

PS_1

1

(1.8V@65mA AVDD)

100mA 10mil (1.8V@100mA VDD1DI) 1

AC30 AC31 AD30 AD31

2 499_0402_1%

1

2

1

2

2 +1.8VGS LV13DIS@ BLM15BD121SN1D_0402

1

1

2

1

2

LV12DIS@ BLM15BD121SN1D_0402

2 CV329

2

@

RV238 4.75K_0402_1% MS@

1

AD29 AC29 AG31 AG32

GENLK_CLK GENLK_VSYNC

T80 T81

2

MS@

1

3 S

@

2

0402 1% resistors are required.

TX_PWRS_ENB

Transmitter Power Saving Enable GPIO0 0: 50% Tx output swing for mobile mode 1: full Tx output swing (Default setting for Desktop)

TX_DEEMPH_EN

PCI Express Transmitter De-emphasis Enable GPIO1 0: Tx de-emphasis diabled for mobile mode 1: Tx de-emphasis enabled (Defailt setting for desktop)

Mars Pro MLPs Hynix

RV241

RV242

NC

4.75k

Bits [3:1] 000

Samsung

8.45k

2k

001

Micron

4.75k

NC

111

Internal VGA Thermal Sensor

+3VGS

+3VGS

PS_3

AF33

1

TH@

RV207 AA29

2 0_0402_5%

DIS@ RV90 10K_0402_5%

DIS@ RV91 10K_0402_5%

NC_TSVSSQ should be tied to GND on Thames/Seymour

1

AM26 AN26

6

EC_SMB_CK2

QV15A DIS@ DMN66D0LDW-7_SOT363-6 4

VGA_SMB_DA2 AM27 AL27

3

EC_SMB_DA2

B

QV15B DIS@ DMN66D0LDW-7_SOT363-6

AM19 AL19

@

AN20 AM20

1 RV92 @

2 0_0402_5%

1 RV94

2 0_0402_5%

AL30 AM30 AL29 AM29 AN21 AM21 AJ30 AJ31

VGA Thermal Sensor ADM1032ARMZ

AK30 AK29

Closed to GPU

+3VGS

MS@ CV85 0.1U_0402_16V7K

+3VGS

2

MS@

1

2 CV89 2

3

MS@ GPU_THERMAL_D2200P_0402_50V7K

2 XTALIN RV232 0_0402_5% GCLKDIS@

4

UV14 VDD D+ DTHERM#

SCLK SDATA ALERT# GND

8

RV96 4.7K_0402_5% VGA_SMB_CK2

7

VGA_SMB_DA2

6 5

THM_ALERT# 1

1

+3VGS 1 2 RV98 4.7K_0402_5% MS@

2

2 G

1

2

RV242 2K_0402_1% X76@

1

AG33 AD33

RV199 2.2K_0402_5% @

D

Need to CHECK CIS symbol

VGA_X1

PS_3

RV240 4.75K_0402_1% MS@ CV333

1

PS_2

close to YV1

CV331

Add 12/6 for MLPS

RV246

RV241 8.45K_0402_1% X76@

PS_2

2 +DPLL_PVDD 0_0402_5% RV247 1 2 DPLL_PVSS @ 0_0402_5%

AC32 AD32 AF32

RV239 10K_0402_1% @

PS_1

1

AF30 AF31 1 @

RV237 8.45K_0402_1% @

2

1

+3VGS

+1.8VGS C

RV84 1 DIS@

THR1@

+3VGS

11

GPIO8

+1.8VGS

AB34

1

PEG_A_CLKRQ#

0 AUD[1] AUD[0] 0 0 No audio function 0 1 Audio for DisplayPort and HDMI if dongle is detected 1 0 Audio for DisplayPort only 1 1 Audio for both DisplayPort and HDMI

GENERICC

GPU_THERMAL_D+

0

AF37 AE38

XTALDIS@

A

X

ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND NOT CONFLICT DURING RESET

AD39 AD37

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

2

0 0: disable 1: enable

2 VIP_DEVICE_STRAP_ENA

RV250 0_0402_5% @

AT17 AR16

VGA_SMB_CK2

PLL/CLOCK DPLL_VDDC

DDC1CLK DDC1DATA

DDCCLK_AUX3P DDCDATA_AUX3N

RV236 10K_0402_5% MS@

QV14A 2N7002DW-7-F_SOT363-6

DPLL_PVDD DPLL_PVSS DDC/AUX

+DPLL_VDDC AN31

XTALIN Voltage Swing: 1.8 V

RV235 10K_0402_5% @

(Thames 125mA) 0.935V@ Mars Pro

20mil

1

LV15DIS@

A2VDDQ/NC VREFG

20mil +DPLL_PVDD AM32 AN32 DPLL_PVSS

2

+3VGS

2

+1.0VGS

AH13

A2VSSQ/TSVSSQ

RV248 0_0402_1%

2

A2VDD/NC

20mil

+VREFG_GPU

AT15 AR14

5

PACIN#

DIS@

DAC2

HPD1

1 249_0402_1%

2 1 CV81 0.1U_0402_16V7K 1 DIS@ @

1

1

2

0.1U_0402_16V7K DIS@ CV84

B

1 499_0402_1%

+DPLL_PVDD 10U_0603_6.3V6M DIS@ CV82

LV14DIS@ 2 1 BLM15BD121SN1D_0402

RSVD

D

+1.8VGS RSET

VDD2DI/NC VSS2DI/NC

0.60 V level, Please VREFG Divider ans cap close to ASIC

QV14B 2N7002DW-7-F_SOT363-6 DIS@

AU14 AV13

SCL SDA GENERAL PURPOSE I/O

VGA_SMB_DA2 TH@ 1 RV251 VGA_SMB_CK2 TH@ 1 RV252

AT33 AU32

AU16 AV15

0

1

X7644031L06

RV67

TX0P_DPC2P TX0M_DPC2N

VGA ENABLED

AC_BATT

2

Micron 1GB SA00004Y20L(R1) SA00004Y21L(R3)

GPIO9

10K_0402_5%

DIS@ 4.7K_0402_5%

1

MT41J64M16JT-107G:G

64MX16 (1G)

0

BIF_VGA DIS

DIS@

RV74

AR32 AT31

2

Hyn2GR3@

RESERVED

1

ZZZ1

TX5P_DPB0P TX5M_DPB0N TXCCP_DPC3P TXCCM_DPC3N

GPIO8

2

Hyn2GR1@

0

0

RSVD

1

ZZZ6

RV72

0

RV73

2

RV70

1

AV31 AU30

2

RV67

0: 2.5GT/s 1: 5GT/s

1

Hynix 1GB SA000041S3L

X7644031L12

TX4P_DPB1P TX4M_DPB1N

Advertises PCIE speed when compliance test

0.68U_0402_10V

H5TQ1G63DFR-11C

64MX16 (1G) X7644031L05

DPB

GPIO2

X

5

0

X

RSVD

1

1

+3VGS

2

RV72

RV69

0

0: disable 1: enable

1

RV68

PCIE TRANSMITTER DE-EMPHASIS

2

Sam 2GR3@

PCIE FULL TX OUTPUT SWING

GPIO1

2

ZZZ2

GPIO0

TX_DEEMPH_EN

0.68U_0402_10V

64MX16 (1G) Sam 2GR1@

TX3P_DPB2P TX3M_DPB2N

TX_PWRS_ENB

+3VGS

AR30 AT29

RECOMMENDED SETTINGS

DESCRIPTION OF DEFAULT SETTINGS 0: 50% swing 1: Full swing

1

Samsung 1GB SA00004GS0L(R1) SA00004GS1L(R3)

TXCBP_DPB3P TXCBM_DPB3N

AT27 AR26

PIN

1

VRAM_ID0 VRAM_ID1 VRAM_ID2

K4W1G1646G-BC11 D

TX2P_DPA0P TX2M_DPA0N

1U_0402_6.3V6K CV76 DIS@

VRAM_ID0 VRAM_ID1 VRAM_ID2

DVPCNTL_MVP_0 DVPCNTL_MVP_1 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23

10U_0603_6.3V6M CV77 DIS@

Vendor

ZZZ7

AR8 AU8 AP8 AW8 AR3 AR1 AU1 AU3 AW3 AP6 AW5 AU5 AR6 AW6 AU6 AT7 AV7 AN7 AV9 AT9 AR10 AW10 AU10 AP10 AV11 AT11 AR12 AW12 AU12 AP12

X7644031L11

STRAPS

AU26 AV25

0.1U_0402_16V7K CV75 DIS@

X7644031L02

AT25 AR24

1

TX1P_DPA1P TX1M_DPA1N

2

DPA

3

TX0P_DPA2P TX0M_DPA2N

MUTI GFX

4

VRAM_ID2

AU24 AV23

1

TXCAP_DPA3P TXCAM_DPA3N

VRAM_ID1

2

VRAM_ID0

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

6

X76@ X76@ X76@ X76@ X76@ X76@

1

Micron1GR3@

2 2 2 2 2 2

1U_0402_6.3V6K CV79 DIS@

ZZZ3

Micron1GR1@

1 1 1 1 1 1

10U_0603_6.3V6M DIS@ CV80

ZZZ5

RV67 RV68 RV69 RV70 RV71 RV72

0.1U_0402_16V7K CV78 DIS@

X7644031L10

RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

+1.8VGS

X7644031L01

1

CONFIGURATION STRAPS

UV1B

2

ZZZ4

2

Sam 1GR1@

0.68U_0402_10V

5

ZZZ8

ADM1032ARMZ-2REEL_MSOP8 MS@

2

A

CV90 10P_0402_50V8J @

Address:100_1101

VGA_CLKREQ#_R

@ 2N7002_SOT23-3 QV28

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2 RV200 1 0_0402_5% @

2012/09/25

Deciphered Date

2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

ATI_ThamesXT_M2_Main_MSIC Size

Docum ent Num ber

Rev 1.0

LA-9102P Date:

Tues day, Septem ber 25, 2012 1

Sheet

25

of

57

5

4

3

2

1

Switch circuits in BACO desingns for Thanes/Seymour only Circuits to support BACO

+3VGS

2

[email protected], in BACO mode RV101 10K_0402_5% DIS@

+1.0VGS

1

D

+BIF_VDDC

+VGA_CORE

60mil 1

TH@

2

1

S

2

PX_EN

G

1

1

2 DIS@

2

+3VGS

1

IN1

1

2

1

RUNPWROK RV102

@

2 @

RV233 0_0402_1%

for PX4.0 and PX5.0

4

PX_MODE

PX_MODE

2

CV97 22U_0805_6.3V6M

PX_MODE=1 for Normal Operation

@

PX_MODE=0 for BACO mode to shut down power rails expcept VDDR3,PCIE_VDDC and 1.8V rail

1

2

@

2

PX_MODE 0_0402_1%

for PX5.0

CV100

+1.8VS TO +1.8VGS

+3VALW

1U_0603_10V6K

1

1

OUT

UV16 MC74VHC1G08DFT2G_SC70-5

3

IN2

0_0603_5%~D

2

@ DV12 RB751V-40_SOD323-2 PXS_PWREN

2

VCC

1

GND

RV104 5.11K_0402_1% DIS@

2

RV234

for PX5.0

+3VGS CV99 @ 0.1U_0402_16V7K

QV21 2N7002K_SOT23-3 DIS@

DIS@ RV105 20K_0402_5%

1

0_0805_5%

5

1

D

3

RV103

for PX4.0

D

60mil

MS@

+1.8VS

@

DIS@ RV109 100K_0402_5%

+1.8VGS

2

1 2MM

2

C

C

J9 UV35

PXS_PWREN#

DIS@

1 2 3

1

2N7002_SOT23-3

S

DIS@

2N7002H_SOT23-3 QV29 @

1

2 G S

2

330K_0402_5% RV128 DIS@

1 RV211

2

DIS@ 470K_0402_5%

S

2

QV10

Power Seguence of Thames and Mars Pro

+1.5VGS

1

RV212 0_0402_5% @

2N7002H_SOT23-3 DIS@

2

1

PXS_PWREN#

G +1.5VGPU

1 RV214

PXS_PWREN#

2

1 3

+1.5VGPU TO +1.5VGS

D

RV213 470_0603_5% @

D

B+_BIAS

PX4.0 +3VGS, +1.0VGS,+1.8VGS OFF PX5.0 +3VGS,+VGA_CORE,VDDCI,+1.5VGV,+1.0VGS,+1.8VGS OFF

CV321 1U_0603_10V6K

2 DIS@

1 2

Note: PX4.0 +VGA_CORE,VDDCI,+1.5VGS ON

1 CV320 10U_0805_10V6K

2 DIS@

3

QV25

1

8 7 6 5

D

PXS_PWREN 2 G

PXS_PWREN

3

4

1

DMN3030LSS-13_SOP8L-8

@

2 0_0402_5%

CV2 0.1U_0603_25V7K DIS@

JP9 @

2

1 2MM

UV17 DIS@ AO4304L_SO8 10U_0603_6.3V6M 1 10U_0603_6.3V6M 1 CV309 CV104 DIS@ DIS@

+VGA_CORE

1 2 3

10U_0603_6.3V6M

1

2

CV105 DIS@

2

B

1

CV106 DIS@ 1U_0603_10V6K

2

RV111 @ 470_0603_5%

4

2

8 7 6 5

1

+3VGS B

1 2

+VDDCI

D

B+_BIAS

2

1

+3VGS

2

PX_MODE#

1 2MM

1

3

DIS@ RV108

1 20K_0402_5%

1 DIS@

CV103 0.1U_0603_25V7K

DIS@ QV24

3 3

D

2 S

S

Deciphered Date

2

G QV23 2N7002K_SOT23-3 @

RV110 PXS_PWREN#

1

2 @

0_0402_5% A

2 2N7002H_SOT23-3

Compal Electronics, Inc. 2013/09/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4

RV106 470_0603_5% @

QV22 DIS@ AP2301GN-HF_SOT23-3

Compal Secret Data 2012/09/25

CV102 DIS@

2

1K_0402_5%

G

5

2

1

2

D

2

PXS_PWREN A

Security Classification

1U_0603_10V6K

CV101 DIS@

3

DIS@ RV107

1

2

+5VALW

Issued Date

10U_0603_6.3V6M

2 0_0402_5%

CV107 DIS@ 0.1U_0603_25V7K

1

2M_0402_5%~D

2

2

DIS@ RV115

1

1

DIS@ QV27A

@ 1 RV116

1

2

JP8 @

1

1

2

DMN66D0LDW-7_SOT363-6

DIS@ RV117 100K_0402_5%

PX_MODE# 2

DIS@ QV27B

5 4

PX_MODE

1

3 2

1ms and