Vhdl Code for 4 Bit Multiplayer and Division

VHDL code for 4 bit multiplayer library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Multiplier_

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VHDL code for 4 bit multiplayer

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Multiplier_VHDL is port ( a, b: in std_logic_vector(3 downto 0); y: out std_logic_vector(7 downto 0) ); end entity Multiplier_VHDL; architecture Behavioral of Multiplier_VHDL is begin y '0'); signal b : std_logic_vector(3 downto 0) := (others => '0'); --Outputs signal y : std_logic_vector(7 downto 0); -- No clocks detected in port list. Replace below with -- appropriate port name

-- constant _period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Multiplier_VHDL PORT MAP ( a => a, b => b, y => y );

-- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. a