• Author / Uploaded
• Eduardo Aramburu

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http://shop61976717.taobao.com http://shop61976717.taobao.com Topstar Digital technologies Co.,LTD D

D

Board name: MotherBoard Schematic

02. System block & Index

Project name: M42G

03. PWR Block & Description

Version: VerB

04. Notes & Annotations

Initial Date: MAY.9, 2008

05. Schematic Modify and History 54. CLOCK Distribution 55. Power Distribution

C

C

56. Power on & off Sequence 57. ACPI Mode Switch Timings 58. Power On Sequence & Reset Map

Topstar Confidential

B

Hardware drawing by:

Hardware check by:

Power drawing by:

Power check by:

EMI Check by:

B

Manager Sign by:

TOPSTAR TECHNOLOGY bent

A

Page Name

Title

Size B

M46G

Project Name

A

Rev B

Date: Sheet of Thursday, August 27, 2009 1 51 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

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http://shop61976717.taobao.com http://shop61976717.taobao.com

Topstar Confidential

ShenZhen Topstar Industry Co.,LTD

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CONTENT 01 Title 02 System Block & Index 03 PWR Block & Description 04 Notes and Annotations 05 Schematic Modify and History 06 CK505M(CY28516&ICS9LPR365) 07 PENRYN CPU(Host BUS)(1of 2) 08 PENRYN CPU(PWR&GND)(2 of 2) 09 CANTIGA (HOST)(1 of 6) 10 CANTIGA (Graphic)(2 of 6) 11 CANTIGA (DDRII)(3 of 6) 12 CANTIGA (DMI&CLK)(4 of 6) 13 CANTIGA (VSS&NCTF)(5 of 6) 14 CANTIGA (Power)(6 of 6) 15 DDR2 SODIMM0 16 DDR2 SODIMM1 17 DDR2 Series Termination 18 DDR2 Decoupling 19 LVDS&INVERTER CONN 20 VGA&SVIDEO&DC-IN 21 HDMI 22 ICH9_M(1 of 3) 23 ICH9_M(2 of 3) 24 ICH9_M(3 of 3) 25 SATA CONN(ODD&DVD) 26 Card Reader(UB6232 USB) 27 EXPRESS CARD 28 PCIE MINI SLOT1 29 PCIE MINI SLOT2 30 LAN/POWER Connector 31 ALC662 AZALIA CODEC 32 MDC & BT & FAN & OTP 33 USB2.0 & TPM & Gsensor & LED Conn 34 KBC(W83L951ADG) 35 ADAPTER IN 36 BATTERY IN 37 +V3.3AL +V5AL 38 +V1.8/+V0.9S DDR 39 +V1.5S/+V1.05S CHIPSET 40 +V1.5AL 41 Power Good Logic/OVP 42 +VCC_CORE 43 SYSTEM/DISCHARGE 44 CHARGER 45 THROUGH HOLE/EMI 46 ACPI mode switch timings 47 Clock Distribution 48 Power ON/OFF & Reset seq 49 Power On/off Sequence 50 Power Distribution

M46G SYSTEM BLOCK Ver:B CPU Thermal Sensor ASC7525

CY28548 /ICS9LPRS365

+VCC_CORE,+VCCP +VCCA1.5

+V3.3S

Backlight Connector

CK505M Clocking

Penryn 478 uFCPGA

+V3.3S,+V1.25S

+VDC

FSB 667MHz/800MHz/1066MHz

TFT

+V3.3S

DDR2 667/800

CANTIGA GM

LVDS

C

PCI-Express X16

R/G/B TMDS

VGA

+V5S

+V0.9S,+V1.8,+V3.3S

1329 FCBGA

DDR2 667/800

+V3.3S,+V1.5S, +VGFX_1_05S, +V1.05S,+V1.8

PCIE mini Card

DDR2 SODIMM1 667/800 +V0.9S,+V1.8,+V3.3S

RTL8102E

HDMI

PCIE 1X Control Link 0

DDR2 SODIMM0 667/800

+V3.3AL

RJ45

DMI x2/x4

SATA ODD PCIE mini Card for 3G

+V5S

BIOS

SPI

8Mbit

676 PBGA

+V3.3AL

USB1.1/2.0

USB PORT2

USB PORT1

BLUE TOOTH(V1.2)

+V5AL

BTM-203/CCOM NEW CARD(Type II)

+V3.3AL

Camera 1.3M/2.0M MODULE

S-ATA 2.5" HDD

+V1.05S,+V3.3S +V3.3AL,+V5AL +V1.5S,+V5S +V3.3A_RTC

PCIE 1X

B

ICH9-M

+V5AL

Card Reader ENE UB6232

+V5S,+V3.3S

USB1.1/2.0

LPC

SD/MMC/MS CARD

+V3.3S,+V3.3AL

AZALIA

+V3.3S

KB Controller/EC W83L951ADG/DG

USB PORT3

C

B

+V3.3AL,+V3.3S,+V5AL

+V5AL

TCM

L R AZALIA

LED/TouchPAD/Button/

DAUGHTER BOARD

MiC

ALC662

Q-key/LID

+V5S,+V3.3S

DAUGHTER BOARD

KB Matrix A

A

TOPSTAR TECHNOLOGY bent Page Name

System Block

Size C

M46G

Project Name

Rev B

Date: Sheet Thursday, August 27, 2009 2 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

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http://shop61976717.taobao.com M46G POWER BLOCK Ver:B http://shop61976717.taobao.com

注意:

Platform Logic

Charge ISL6251

D

VR_ON

虚线表示电源电压信号。

Battery

44A

+VCC_CORE

Page 55

D

VR_TT# Vcc_core

VIN V_5

VID[6...0] PSI#

IMVP-6

V_3

Vss_sense

Vcc_sense

Page 48,49

5A

DPRSLPVR

+VDC

Page 38

IMVP6_PWRGD

Power Switch

65W

DPRSTP# CLK_ENABLE#

Adapter

VCC_CORE ISL6262A

DPRSTP#

Always_On Power ISL62382

C

Chipset PWR TPS51124

ICH-M

DDR Power TPS51116 +V5S +V3.3S

Page 43

+V1.8 +V0.9S

+V3.3AL +V5AL +V1.5AL

+V1.5S +V1.05S

CLK CHIP

4A/2.5A

3A/5A

CPU-M C

Page 42

Page 41

CPU_PWRGD

PSI# PROCHOT#

System Power +V_S

4A/12A

Page 46

+V1.8GDDR 4A

B

B

BATT+

+V5AL

+V3.3AL

+V1.5S

+V1.8

+V1.05S

+VCC_CORE

OVP Circuit Page 43,52

A

A

TOPSTAR TECHNOLOGY bent Page Name

OVP 16.5V

5

OVP 5.6V

OVP 3.6V

OVP 2.0V

4

OVP 2.0V

OVP 2.0V

OVP 2.0V

Size A3

Project Name

PWR Block & description Rev B

M46G

Thursday, August 27, 2009 3 51 of Date: Sheet PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 3

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Voltage Rails

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http://shop61976717.taobao.com http://shop61976717.taobao.com I2C SMB Address

+VDC

Primary DC system power supply(9V-19V)

+VCC_CORE

Core voltage for processor

Device

Address

1.5V for CPU PLL

Clock Generator

1101 001x 1010 000x 1010 010x Variable Variable

D2 A0 A4 Variable Variable

SMB_ICH_S SMB_ICH_S SMB_ICH_S SMB_ICH_S SMB_ICH_S

0001 011x 1001 100x

16 98

I2C I2C

+V1.5S

SO-DIMM0

+V1.05S

1.05V for FSB VTT

SO-DIMM1

+V0.9S

0.9V DDR2 Termination voltage

NEW CARD

+V1.8

1.8V power rail for DDR2

PCIE Mini CARD

+V3.3AL

3.3V always on power rail

+V3.3S

3.3V main power rail

+V5AL

5V for USB Device

+V5S

5V main power rail

+V1.5AL

1.5AL for HDMI

Smart Battery CPU Thermal Sensor(ASC7525)

Hex

Bus

Master ICH9M ICH9M ICH9M ICH9M ICH9M

D

KB3926 KB3926

C

Board stack up description PCB Layers TOP GND IN1 IN2

Trace Impedence:55ohm +/-15%(Default)

Power States/AC mode

VCC

Signal

SLP_S3#

SLP_S4#

SLP_S5#

IN3

S0(Full On)

HIGH

HIGH

HIGH

ON

GND

S3(STM)

LOW

HIGH

HIGH

Bottom

S4(STD)

LOW

LOW

S5(SoftOff)

LOW

LOW

B

+V*AL

+V*S

Clock

ON

ON

ON

ON

ON

OFF

OFF

HIGH

ON

OFF

OFF

OFF

LOW

ON

OFF

OFF

OFF

+V*

B

USB Table USB Port#

A

Function Description

Wake up Events

0

Express Card

1

RESERVED

2

USB Port(on Main Board)

3

Mini PCIE Card(WLAN & ROBSON)

4

Mini PCIE Card(WLAN & ROBSON)

5

Bluetooth

6

USB Port(on I/O Board)

7

USB CAMERA(On VGA Board)

8

CARD Reader

Size A3

9

USB Port(on I/O Board)

Date: Thursday, August 27, 2009 Sheet 4 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

LID switch from EC Power switch from EC

ns: Component marked "ns" is not stuff A

TOPSTAR TECHNOLOGY

This is a lead free project,all component must be LF

bent Page Name Project Name

NOTE M46G

Rev B

5

4

Schematic modify Item and history:

C

B

2

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2007-10-26 Ver A initial release

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Cost Down list

2009-07-28 Ver B 1. 3.3AL/5AL电换phath,改用62382的电源芯片--PG 36 2.EC ROM封装colay。改上64K的EC ROM--PG 33 3.LIDR信号到EC 的电阻上上去。--PG33 4.RGB ESD管子上上去。--PG20 5.LVDS由双单通道改为双通道。并更换LCDCON。--PG20 6.增加TCM功能--PG31 7.CLK的驱动电阻由33ohm改为0ohm--PG6 8.HDMI做成CH7318与PS8101COLAY--PG21 9.更改PCB Mark 电阻--PG33 10.TP_CON1的footprint改为CNS6_1_R1--PG32 11.五个LED均更改成M12上所用，与S46P一致---PG50 12.3G开关第一版接法有误，更改；3G_LED的作用是反映硬件开关，故不由PCIE插槽引出，改由3G开关引出--PG28 13.调整TPA6017A2的增益倍数为10dB,与M12一致--PG30 14.南桥32.768K采用插件晶振--PG22 15.TP_CON1采用下接触，故将其连接关系反转--PG32 16.SATA_CON1更改footprint为SATA_S_50G--PG25 17.R645改为976OHM使VGA信号的上升时间与幅值满足规范--PG10 18.R211改为20ohm以改善眼图效果，同时预留一个并联电阻以备调节--PG23 19.C503更改为更低的电容以满足机构要求--PG13 20.去掉CR的12MHZ的晶振预留方案，以满足机构限高的要求--PG29 21.删除E2,H14,H19改为TH_197_88类型孔 22.改用AO4468的2S SI4800,在第一版用AO4468时上电不正常--PG42 23.CR改用+V3.3AL电，预留+V5AL--PG29 24.3.3AL，5AL，+V1.8预留RC 25.更改H4的footprint 26.将网卡TVS管改到靠近RJ45--PG51 27.LCDCON仍然改回第一版所用物料--PG20 28.BT_CON更改为X01所用--PG31 29.pc237与PC238colay，ns PC237

D

C

2009-08-27 Ver C release 1.HDMI Level shifter CH7318的第四pin由PU改为PD--PG21 2.WIFI改变symbol,改变螺柱定位孔的形状--PG27 3.3G卡槽增加一个定位螺柱PCIE_NUT3,预留，增加3G卡的接地效果--PG28 4.3G开关的信号只连到EC，并改由EC控制3G灯的状态--PG28,PG50,PG33 5.蓝牙增加预留线路，以满足不同的蓝牙模组信号和时序要求--PG31 6.改变3G与WIFI 指示灯的亮度，R881-->330 ohm,R719-->220 ohm--PG50 7.改变PCB Mark电阻--PG33 8.SIM卡改用X01所用的物料--PG28 9.LVDS connector 换成40PIN立式的，屏线也与S46P一致

B

A

A

TOPSTAR TECHNOLOGY bent Page Name Size Project Name Custom

Sch Modify and history M46G

Rev B

Date: Sheet of Tuesday, September 01, 2009 5 51 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

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FB271

2 FB0805

100ohm@100MHz,3A 2 1

C348 C0805 10UF/6.3V,X5R

{7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51} {7,8,9,12,13,14,22,24,31,38,40,41,42,44}

C346 C350 0.1UF/25V,Y5V C347 C0805 +V3.3S_CK_VDD 4.7UF/10V,Y5V 0.047uF/16V,Y5V +V3.3S_CK_VDD 0.1UF/25V,Y5V 0.1UF/25V,Y5V C351

D

U4

+V3.3S_CK_VDD

2 9 16 61

VDD_PCI VDD_48 VDD_PLL3 VDD_REF

+V3.3S_CK_VDD

39 55

VDD_SRC VDD_CPU

+VDDIO_CLK C344 10UF/6.3V,X5R C0805

C341

+VDDIO_CLK

0.1UF/25V,Y5V

C335 0.047uF/16V,Y5V

C115

ns 10UF/6.3V,X5R

0.1UF/25V,Y5V C336 10UF/6.3V,X5R C0805

C337

+VDDIO_CLK

+VDDIO_CLK +VDDIO_CLK +VDDIO_CLK

0.1UF/25V,Y5V ns

C338

C333

C339

C340

+VDDIO_CLK

{23} SATA_CLKREQ#

10UF/6.3V,X5R C0805 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V C345 10UF/6.3V,X5R C0805 ns

C342

SATA_CLKREQ#R180475,1% R884

{31} CLK_TCMPCI

22

TME {33} CLK_591PCI

+VDDIO_CLK

{28} CLK_debugPCI

0.1UF/25V,Y5V

{23} CLK_ICHPCI

C122

R173

22

R412

22

R171

22

27M_SEL PCIF_ITP_EN

27pF/50V,NPO

1

XTAL_IN XTAL_OUT

Y3 XS2

2

C121

{29} CLK_CR_48M

{23} 14.318180MHz

CLK_USB48 CLK_BSEL0

R761

22

R164

22

R166

2.2K

R172

33

27pF/50V,NPO

+V3.3S

CLK_BSEL1 {23}

CLK_ICH14 CLK_BSEL2

R176

PCI2/TME

5

PCI3/FSD

6 7

ns 10K 27M_SEL R410 10K

PCI4/SRC5_SEL

XTAL_IN

59

XTAL_OUT

10

USB_48/FSA

57 62

8 11 15 19 52 23 29 58 42

38 37

{15,16,23,26,27,28} {15,16,23,26,27,28}

PM_STPPCI# {23} PM_STPCPU# {23}

54 53

CPU0 CPU#0

RN11 1 3

2 0 4 RA0402_4

CLK_CPU_BCLK {7} CLK_CPU_BCLK# {7}

51 50

CPU1 CPU#1

RN9

1 3

2 0 4 RA0402_4

CLK_MCH_BCLK {9} CLK_MCH_BCLK# {9}

RN5

3 1

4 0 MiniCard 2 RA0402_4

CLK_PCIE_MINICARD {27} CLK_PCIE_MINICARD# {27}

47 46 34 35

SRC11/OE#_10 SRC11#/OE#_9

33 32

SRC9 SRC9#

30 31

RN2

3 1

4 0 2 RA0402_4

SRC7/OE#_8 SRC7#/OE#_6

44 43

RN6

1 3

SRC6 SRC6#

41 40

RN3

1 3

27 28

RN4

3 1

3G 2 0 4 RA0402_4 2 0 4 RA0402_4 4 0 2 RA0402_4

24 25

RN8

3 1

21 22

RN7

3 1

4 2 0 RA0402_4 4 0 2 RA0402_4

17 18

RN26 3 1

4 0 2 RA0402_4

DREFSSCLK DREFSSCLK#

{12} {12}

13 14

RN10 3 1

4 0 2 RA0402_4

DREFCLK DREFCLK#

{12} {12}

CLK_PWRGD

{23}

SRC4 FSB/TEST_MODE SRC4# REF0/FSC/TEST_SEL SRC3/OE#_0/2_B SRC3#/OE#_1/4_B VSS_PCI SRC2/SATA VSS_48 SRC2#/SATA# VSS_IO VSS_PLL3 SRC1/SE1 VSS_CPU SRC1#/SE2 VSS_SRC_1 VSS_SRC_2 SRC0/DOT96 VSS_REF SRC0#/DOT96# VSS_SRC3 CK_PWRGD/PWRDWN# CY28548 TSSOP64_0D5_6D1

B

SMB_DATA_S SMB_CLK_S

SRC10 SRC10#

PCIF5/ITP_EN

60

10K

R168

63 64

4

R411 10K

48

3

1

TCM

IO_VOUT SMB_DATA SMB_CLK

SRC5/PCI_STOP# VDD_IO SRC5#/CPU_STOP# VDD_PLL3_IO VDD_SRC_IO_1 CPU0 VDD_SRC_IO_2 CPU0# VDD_SRC_IO_3 VDD_CPU_IO CPU1 CPU1# PCI0/OE#_0/2_A SRC8/CPU2_ITP PCI1/OE#_1/4_ASRC8#/CPU2#_ITP

12 20 26 36 45 49

+VDDIO_CLK

C

+V3.3S +V1.05S

C349

FB26 FB0805

C343 C0805

1

+V3.3S_CK_VDD

100ohm@100MHz,3A

D

2

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+V3.3S

+V3.3S

3

EXP_CLKREQ MPCIE_CLKREQ

R147 475,1%R0402 ns R137 475,1%R0402

EXPCARD_CLKREQ# {26} PCIE_CLKREQ# {12}

不支持NEW CARD request

CLK_MCH_3GPLL {12} CLK_MCH_3GPLL# {12}

56

CLK_PCIE_3G {28} CLK_PCIE_3G# {28} CLK_PCIE_GLAN {51} CLK_PCIE_GLAN# {51} CLK_PCIE_EXPCARD {26} CLK_PCIE_EXPCARD# {26} CLK_PCIE_ICH {23} CLK_PCIE_ICH# {23} CLK_ICH_SATA {22} CLK_ICH_SATA# {22}

VerB:change the drive resistors from 33 ohm to 0ohm B

C736 0.1UF/25V,Y5V

+V1.05S

缝合电容

R408 56 ns

C

CLK_ICH14

C118

10PF/50V,NPO

CLK_USB48

C112

18pF/50V,NPO

+V3.3S

ns

C0402

SATA_CLKREQ# R181 10K

CLK_BSEL0

R165

1K

MCH_BSEL0 CLK_BSEL0

EXP_CLKREQ

{12} {7}

R143 10K

MPCIE_CLKREQ R138 10K

R409 1K ns

+V1.05S

CLK_debugPCI

C353

10PF/50V,NPO

ns

CLK_591PCI

C119

10PF/50V,NPO

ns

CLK_ICHPCI

C117

10PF/50V,NPO

ns

+V3.3S

C113 0.1UF/25V,Y5V

+V1.05S

TME

R177 10K

+V1.05S

A

R179 1K ns

R170 1K ns CLK_BSEL1

R167

1K

MCH_BSEL1 CLK_BSEL1

{12} {7}

CLK_BSEL2

R169 1K ns

bent R178

1K

MCH_BSEL2 CLK_BSEL2

{12} {7}

R175 1K ns

5

4

A

TOPSTAR TECHNOLOG Page Name

CK505M

Size A3

M46G

Project Name

Rev B

of Date: Thursday, August 27, 2009 Sheet 6 51 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 3

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{9}

H_ADSTB#1

{22} {22} {22} T20

H_A20M# H_FERR# H_IGNNE# R60 0

{22} H_STPCLK# {22} H_INTR {22} H_NMI {22} H_SMI# ns ns ns ns ns ns ns ns ns

ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP

TP_CPU_RSVD01 TP_CPU_RSVD02 TP_CPU_RSVD03 TP_CPU_RSVD04 TP_CPU_RSVD05 TP_CPU_RSVD06 TP_CPU_RSVD07 TP_CPU_RSVD08 TP_CPU_RSVD09

T9 TP2 TP1 T8 T19 T13 T16 T15 T11

Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

A6 A5 C4

A20M# FERR# IGNNE#

D5 C6 B4 A3

STPCLK# LINT0 LINT1 SMI#

M4 N5 T2 V3 B2 D2 D22 D3 F6

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]

F1 D20 B3

LOCK#

H4 C1 F3 F4 G3 G2

HIT# HITM#

G6 E4

BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#

ICTP

ns

H_ADS# H_BNR# H_BPRI#

{9} {9} {9}

H_DEFER# H_DRDY# H_DBSY#

{9} {9} {9}

H_BREQ#0

{9}

{9}

+V1.05S

THERMTRIP#

H_IERR# H_INIT#

H_RS#0 H_RS#1 H_RS#2

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

{22}

H_LOCK# {9} T17ICTP ns H_CPURST# {9} H_RS#0 {9} H_RS#1 {9} H_RS#2 {9} H_TRDY# {9} H_HIT# H_HITM#

H_BPM#0 H_BPM#1 H_BPM#2 H_BPM#3 H_PRDY# H_FREQ# H_TCK H_TDI H_TDO H_TMS H_TRST# H_DBR#

{9} H_DSTBN#0 {9} H_DSTBP#0 {9} H_DINV#0

{9} {9}

{9} H_D#[63:0]

D21 A24 B25

ICTP ICTP ICTP ICTP ICTP

ns ns ns ns ns

T6

ICTP

ns

H_DBR#

R61

H_TMS H_FREQ# H_TDI

R16 R15 R21

54.9,1% R0402 54.9,1% R0402 54.9,1% R0402

H_TCK H_TRST#

R19 R20

54.9,1% R0402 54.9,1% R0402

1K

ns +V1.05S

+V1.05S

VR_PROCHOT# H_THERMDA H_THERMDC

C7

PM_THRMTRIP# should connect to ICH9 and GMCH without T-ing(No stub)

R340 2K,1% R0402

CLK_CPU_BCLK {6} CLK_CPU_BCLK# {6}

CLK_CPU_BCLK NC

Layout Note: Z=55ohm,{9} 0.5" max for GTLREF {9} {9}

R341 1K,1% R0402

PM_THRMTRIP# {12,22,31}

A22 A21

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

+V3.3S

T1 T4 T3 T2 T7

H CLK BCLK[0] BCLK[1]

U10B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

R65 56 R0402 Place testpoint on H_IERR# with a GND 0.1" away

THERMAL PROCHOT# THERMDA THERMDC

H_D#[63:0]

B1 R589 100,1% R0402

H_DSTBN#1 H_DSTBP#1 H_DINV#1

ns

ICTP

T14

ns ns ns

ICTP ICTP ICTP

T5 T80 T18

{6} C248{6} {6}

R52

R49

1K R0402 ns

1K C0402 R0402 0.1UF/10V,X7R ns ns

CPU_TEST3 CPU_TEST4 CPU_TEST5 CPU_TEST6 CPU_TEST7

CLK_BSEL0 CLK_BSEL1 CLK_BSEL2 Place C30 close to the CPU_TEST4 pin. Make sure CPU_TEST4 routing is reference to GND and away from other noisy signals.

E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]

MISC

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]#

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

DATA GRP 2

H5 F21 E1

RESET# RS[0]# RS[1]# RS[2]# TRDY#

ICH

ns ICTP

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

IERR# INIT#

T10

H1 E2 G5

DATA GRP 1

C

H_A#[35:3]

K3 H2 K2 J3 L1

BR0#

ADDR GROUP 1

{9}

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

DEFER# DRDY# DBSY#

CONTROL

H_ADSTB#0 H_REQ#[4:0]

ADS# BNR# BPRI#

XDP/ITP SIGNALS

{9} {9}

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

DATA GRP 0

D

J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1

ADDR GROUP 0

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

DATA GRP 3

U10A

H_A#[35:3]

RESERVED

{9}

COMP[0] COMP[1] COMP[2] COMP[3]

R26 U26 AA1 Y1

DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#

E5 B5 D24 D6 D7 AE6

+V3.3S

{6,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}

+V1.05S

{6,8,9,12,13,14,22,24,31,38,40,41,42,44}

H_D#[63:0]

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

{9}

D

H_DSTBN#/H_DSTBP# should route as differential pair

H_DSTBN#2 {9} H_DSTBP#2 {9} H_DINV#2 {9} H_D#[63:0]

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

{9}

Layout note: Comp0,2 connec with Zo=27.4ohm,make trace length shorter than 0.5" Comp1,3 connec with Zo=55ohm,make trace length shorter than 0.5" H_DSTBN#3 {9} H_DSTBP#3 {9} H_DINV#3 {9}

COMP_CPU0 COMP_CPU1 COMP_CPU2 COMP_CPU3

R343 R342 R17 R18

H_DPRSTP# H_DPSLP#

27.4,1% 54.9,1% 27.4,1% 54.9,1%

{12,22,41} {22}

+V1.05S

R0402 R0402 R0402 R0402 ICTP T12 H_DPWR#

ns {9}

C

R38 200,1% R0402 ns

Remove H_PWRGD PU Resistor.

H_PWRGD H_CPUSLP# PM_PSI#

{22}

{9} {41}

Penryn

CLK_CPU_BCLK#

change ns to install Hads 2008-5-10

length:7mil,Space>10mil

Penryn

B

B

+V3.3S

NOTE VDD_1

会用到新的支持BJT MODEL的TS

BI-DIRECTIONAL PROCESSOR HOT

C279

EC SMBUS ADD:1001 100X

I2C_CLK I2C_DATA OVT_SHUTDOWN#

C281

THERM# delete for DFX By Johan 071228

R57 10K R0402

R350 10K R0402 EC_PROCHOT#

1 2

R0402

2

+V1.05S Q4 MMBT2222A SOT23 R37 1K R0402

Q6 MMBT2222A R64 1

{33}

Change to 75393 By Johan 071228

C291

C290

27pF/50V,NPO C0402 ns

27pF/50V,NPO C0402 ns

U11 VDD_1 H_THERMDA H_THERMDC THERM#

SOT23

VR_PROCHOT#

R371 10K R0402

A

+V1.05S R0402 1K

3

3

+V1.05S

1K

I2C_CLK {33} I2C_DATA {33} OVT_SHUTDOWN# {31}

H_THERMDC

+V3.3S

R31

2.H_THERMDA/C走线远离19V及VGA或高速线走线

0.1UF/25V,Y5V C0402

H_THERMDA

2200PF/25V,X7R C0402

A

1.H_THERMDA/C线宽10 MILS,并配对走线, 然后再包地处理.

R347 220 R0402

1 2 3 4

VDD SCL D+ SDA DALERT# THERM# GND

8 7 6 5

I2C_CLK I2C_DATA OVT_SHUTDOWN#

TOPSTAR TECHNOLOGY bent

F75393S

{41}

+V3.3S

Page Name

PENRYN(Host Bus)

Size C

M46G

Project Name

Rev B

Date: Sheet Friday, August 28, 2009 7 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com Demo:22uF*32 3mOhm 0.6nH Caps

+VCC_CORE {40,41} +V1.5S {14,22,24,26,27,28,30,38,40,42} +V1.05S {6,7,9,12,13,14,22,24,31,38,40,41,42,44}

U10D

VerB cost down

A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3

+VCC_CORE D

C269 10uF/6.3V,X5R C0805

ns

C270 10uF/6.3V,X5R C0805

C267 10uF/6.3V,X5R C0805

C268 10uF/6.3V,X5R C0805

C266 ns 10uF/6.3V,X5R C0805

ns

C258 10uF/6.3V,X5R C0805

ns

C265 10uF/6.3V,X5R C0805

C43 10uF/6.3V,X5R C0805

C42 10uF/6.3V,X5R C0805

C257 10uF/6.3V,X5R C0805 ns

+VCC_CORE

+VCC_CORE

C22 10uF/6.3V,X5R C0805

U10C

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

VCCA[01] VCCA[02]

B26 C26

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

AD6 AF5 AE5 AF4 AE3 AF3 AE2

VCCSENSE

AF7

VSSSENSE

AE7

C41 ns 10uF/6.3V,X5R C0805

C40 ns 10uF/6.3V,X5R C0805

C259 10uF/6.3V,X5R C0805

ns

C13 10uF/6.3V,X5R C0805

C14 10uF/6.3V,X5R C0805

C16 ns 10uF/6.3V,X5R C0805

C256 10uF/6.3V,X5R C0805

C251 10uF/6.3V,X5R C0805

C261 10uF/6.3V,X5R C0805

C25 ns 10uF/6.3V,X5R C0805

C253 ns 10uF/6.3V,X5R C0805

C260 ns 10uF/6.3V,X5R C0805

VerB cost down

+VCC_CORE

C24 C262 10uF/6.3V,X5R C0805

C255 10uF/6.3V,X5R C0805

C252 ns 10uF/6.3V,X5R C0805

C15 ns 10uF/6.3V,X5R C0805

ns 10uF/6.3V,X5R C0805

ns

C254 10uF/6.3V,X5R C0805

ns

+V1.05S +V1.05S

C17

C21

10uF/6.3V,X5R C0805

C33 10uF/6.3V,X5R C0805

10uF/6.3V,X5R C0805

+VCCA_PROC

+V1.5S

C34

C20

C18

C27

C31

C19

0.1UF/10V,X7R C0402

0.1UF/10V,X7R C0402

0.1UF/10V,X7R C0402

0.1UF/10V,X7R C0402

0.1UF/10V,X7R C0402

0.1UF/10V,X7R C0402

R345 0 R0603 C274 10uF/6.3V,X5R C0805

C272 0.01uF/16V,X7R C0402 Place near PIN B26

change to bi-sticky mylar By Johan 071224 BRACKET

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6

VCC_Sense/VSS-Sense lines between the Penryn processor and the VR should have a trace width of 18 mils on 7-mil spacing, with trace impedance of Zo=27.4 Ω. The VCC_Sense/VSS-Sense should be length matched to within 25 mils.

Penryn

C23 10uF/6.3V,X5R C0805

{41} {41} {41} {41} {41} {41} {41}

BRACKET1_Mylar

+VCC_CORE

R338 100,1% R0402

VCCSENSE

{41}

VSSSENSE

{41}

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

D

C

B

Penryn

R339 100,1% R0402

CPU_BRACKET

Mylar

ASSY

ASSY

HCPU1

HCPU2

1 2 3 4 5 6 7 8 9

1 2 3 4 5 6 7 8 9

CPU_HOLE ns

Change to ESD dischange point By Johan 071224 HCPU3

CPU_HOLE ns

HCPU4

CPU_HOLE ns

CPU_HOLE ns

1 2 3 4 5 6 7 8 9

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

ns

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]

1 2 3 4 5 6 7 8 9

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

1 2 3 4 5 6 7 8 9

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

1 2 3 4 5 6 7 8 9

B

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

1 2 3 4 5 6 7 8 9

C

A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

1 2 3 4 5 6 7 8 9

+VCC_CORE

VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]

Note : using ESD prtection Hole

A

A

TOPSTAR TECHNOLOGY bent Page Name

PENRYN(POWER&GND)

Size C

M46G

Project Name

Rev B

Date: Sheet of Tuesday, September 01, 2009 8 51 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com

+V1.05S

{6,7,8,12,13,14,22,24,31,38,40,41,42,44}

D

D

H_D#[63:0]

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

+V1.05S

R391 221,1% R0402 H_SWING

Close to the pin! R384 100,1% R0402

C299 0.1UF/10V,X7R C0402

C

H_RCOMP

R385 24.9,1% R0402

Trace should be 10mil wide with 20mil spacing!

F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6

H_SWING H_RCOMP

+V1.05S

C5 E3

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_SWING H_RCOMP

B

R360 1K,1% R0402

{7} {7}

H_CPURST# H_CPUSLP#

R372 R361 2K,1% R0402

0

C285 0.1UF/10V,X7R C0402

Loyout note: Place C76 with 100mils from GMCH

R0402 C286 0.1UF/10V,X7R C0402 ns

C12 E11

H_CPURST# H_CPUSLP#

A11 B11

H_AVREF H_DVREF

HOST

U13A {7}

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

J8 L3 Y13 Y1

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_A#[35:3]

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

{7}

C

H_ADS# {7} H_ADSTB#0 {7} H_ADSTB#1 {7} H_BNR# {7} H_BPRI# {7} H_BREQ#0 {7} H_DEFER# {7} H_DBSY# {7} CLK_MCH_BCLK {6} CLK_MCH_BCLK# {6} H_DPWR# {7} H_DRDY# {7} H_HIT# {7} H_HITM# {7} H_LOCK# {7} H_TRDY# {7}

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

{7} {7} {7} {7}

L10 M7 AA5 AE6

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

{7} {7} {7} {7}

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

L9 M8 AA6 AE5

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

B15 K13 F13 B13 B14

H_DSTBP#0 {7} H_DSTBP#1 {7} H_DSTBP#2 {7} H_DSTBP#3 {7} H_REQ#[4:0]

H_RS#_0 H_RS#_1 H_RS#_2

B6 F12 C8

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

{7} B

H_RS#0 H_RS#1 H_RS#2

{7} {7} {7}

CANTIGA_1p2

A

A

TOPSTAR TECHNOLOGY bent Page Name

CANTIGA(Host BUS)

Size C

M46G

Project Name

Rev B

Date: Sheet Thursday, August 27, 2009 9 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com +VCC_PEG

{14}

+V3.3S

{6,7,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}

+V3.3S D

D

R627 10K

R628 10K

+VCC_PEG U13C

+V3.3S

R630 49.9,1%

L_DDC_CLK

{19}

M29 C44 B43 E37 E38 C41 C40 B37 A37

L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

T157

H47 E46 G40 A40

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3

T161

H48 D45 F40 B40

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3

T158

A41 H38 G37 J37

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3

T159

B42 G38 F37 K37

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3

F25 H25 K25

TVA_DAC TVB_DAC TVC_DAC

H24

TV_RTN

C31 E32

TV_DCONSEL_0 TV_DCONSEL_1

{20} MCH_BLUE

E28

CRT_BLUE

{20} MCH_GREEN

G28

CRT_GREEN

{19} LVDS_VDDEN T156

LVDS_IBG LVDS_VBG

ns R632 2.37K,1%

{19} {19} {19} {19}

LVDS_CLKAM LVDS_CLKAP LVDS_CLKBM LVDS_CLKBP

{19} LVDS_YAM0 {19} LVDS_YAM1 {19} LVDS_YAM2 ns {19} LVDS_YAP0 {19} LVDS_YAP1 {19} LVDS_YAP2

C

ns {19} LVDS_YBM0 {19} LVDS_YBM1 {19} LVDS_YBM2 ns {19} LVDS_YBP0 {19} LVDS_YBP1 {19} LVDS_YBP2 TVA_DAC

R638

75,1%

TVB_DAC

R639

75,1%

TVC_DAC

R640

75,1%

ns TVA_DAC TVB_DAC TVC_DAC

根据车checklist HOMY1109 靠近MCH HOMY1109

MCH_BLUE

R641

150,1%

MCH_GREEN

R642

150,1%

MCH_RED

R643

{20} CRT_DDC_CLK {20} CRT_DDC_DATA {20} CRT_HSYNC

150,1%

150ohm电阻到GMCH 走线阻抗37.5ohm homy 1109 150ohm电阻到VGA口 走线阻抗50ohm homy 1109 PLACE 150 OHM RESISTORS CLOSE TO GMCH Homy 1109

MCH_RED

{20} CRT_VSYNC R645 976

R644

24.9,1%R0402

R64624.9,1% R0402

J28

CRT_RED

G29

CRT_IRTN

H32 J32 J29 E29 L29

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

VGA

{20}

B

TV

L_CTRL_DATA L_DDC_CLK L_DDC_DATA

LVDS

M33 K33 J33

change 33 to 24.9 hads 080514

Place the resistor within 300 mils (1.27 mm) of the (G)MCH.Homy 1019

PEG_COMPI PEG_COMPO

T37 T36

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46

C496 C495 C497 C498

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46

C499 0.1UF/10V,X7R C500 0.1UF/10V,X7R C501HDMI 0.1UF/10V,X7R C502HDMI 0.1UF/10V,X7R HDMI HDMI

PEG_COMP

+V3.3S

R633HDMI 20K R634HDMI 0 R0402 HDMI R635 7.5K,1%

0.1UF/10V,X7RHDMI 0.1UF/10V,X7RHDMI 0.1UF/10V,X7RHDMI 0.1UF/10V,X7RHDMI

R636 0 R0402 ns HDMI 1

2

{19}

LCTL_DATA L_DDC_CLK L_DDC_DATA

GRAPHICS

R629 2.2K

L_DDC_DATA

LCTL_CLK

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK

PCI-EXPRESS

R631 2.2K

L32 G32 M32

{19} LVDS_BKLTCTL {19} LVDS_BKLTEN

LCTL_CLK

3

LCTL_DATA

Q41 2N7002

C

MCH_HDMI_HPD#

{21}

R637HDMI 100K

IN_D2{21} IN_D1{21} IN_D0{21} MCH_CLK_D4- {21}

IN_D2+ {21} IN_D1+ {21} IN_D0+ {21} MCH_CLK_D4+ {21}

B

VerB:chang to 976 to improve VGA signal CANTIGA_1p2 1.02k demo

靠近MCH ，远离高速信号 HOMY1109

A

A

TOPSTAR TECHNOLOGY bent Page Name

CANTIGA(GRAPHIC)

Size C

M46G

Project Name

Rev B

Date: Sheet Tuesday, September 01, 2009 10 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com {15,17} {15,17} {15,17}

SA_RAS# SA_CAS# SA_WE#

BB20 BD20 AY20

MA_A_RAS# MA_A_CAS# MA_A_WE#

{15,17} {15,17} {15,17}

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

MA_DQS0 MA_DQS1 MA_DQS2 MA_DQS3 MA_DQS4 MA_DQS5 MA_DQS6 MA_DQS7 MA_DQS#0 MA_DQS#1 MA_DQS#2 MA_DQS#3 MA_DQS#4 MA_DQS#5 MA_DQS#6 MA_DQS#7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

MA_A_A0 MA_A_A1 MA_A_A2 MA_A_A3 MA_A_A4 MA_A_A5 MA_A_A6 MA_A_A7 MA_A_A8 MA_A_A9 MA_A_A10 MA_A_A11 MA_A_A12 MA_A_A13 MA_A_A14

MA_DM[7:0]

MA_DQS[7:0]

{15}

{15}

MA_DQS#[7:0]

MA_A_A[13:0]

{15}

{15,17}

MA_A_A14 MB_B_A14

MA_A_A14

{15,17}

MB_B_A14

{16,17}

CANTIGA_1p2

U13E MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

SB_BS_0 SB_BS_1 SB_BS_2

BC16 BB17 BB33

SB_RAS# SB_CAS# SB_WE#

AU17 BG16 BF14

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

MB_DQS0 MB_DQS1 MB_DQS2 MB_DQS3 MB_DQS4 MB_DQS5 MB_DQS6 MB_DQS7 MB_DQS#0 MB_DQS#1 MB_DQS#2 MB_DQS#3 MB_DQS#4 MB_DQS#5 MB_DQS#6 MB_DQS#7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

MB_B_A0 MB_B_A1 MB_B_A2 MB_B_A3 MB_B_A4 MB_B_A5 MB_B_A6 MB_B_A7 MB_B_A8 MB_B_A9 MB_B_A10 MB_B_A11 MB_B_A12 MB_B_A13 MB_B_A14

B

MA_A_BS#0 MA_A_BS#1 MA_A_BS#2

MEMORY

BD21 BG18 AT25

SYSTEM

{16} MB_DATA[63:0]

SA_BS_0 SA_BS_1 SA_BS_2

DDR

A

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

MEMORY

AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12

SYSTEM

C

U13D MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

DDR

{15} MA_DATA[63:0] D

MB_B_BS#0 MB_B_BS#1 MB_B_BS#2 MB_B_RAS# MB_B_CAS# MB_B_WE#

{16,17} {16,17} {16,17}

D

{16,17} {16,17} {16,17}

MB_DM[7:0]

{16}

MB_DQS[7:0]

{16}

MB_DQS#[7:0]

{16} C

MB_B_A[13:0]

{16,17}

CANTIGA_1p2

B

B

A

A

TOPSTAR TECHNOLOGY bent Page Name

CANTIGA(DDRII)

Size C

M46G

Project Name

Rev B

Date: Sheet Thursday, August 27, 2009 11 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

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3

2

1

5

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3

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http://shop61976717.taobao.com http://shop61976717.taobao.com

+V3.3S +V1.8 +V1.05S +V3.3AL

{6,7,10,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50 {13,14,15,16,37,40,42} {6,7,8,9,13,14,22,24,31,38,40,41,42,44} {19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51}

DIM_EXTTS#0

{15}

ns

ICTP

T42

RSVD14

T24

R95 10K R0402 PM_EXTTS#1

R98 ns

0

R0402

DIM_EXTTS#1

{16}

RSVD14

ns

ICTP

T24

RSVD15

ns

ICTP

T33

RSVD17

M1

RSVD17

ns

ICTP

RSVD20

AY21

RSVD20

ns ns ns ns ns

ICTP ICTP ICTP ICTP ICTP

T54 T86 T120 T123 T119 T127

RSVD21 RSVD22 RSVD23 RSVD24 RSVD25

B31

B2 BG23 BF23 BH18 BF18

RSVD

+V3.3S

RSVD15

RSVD21 RSVD22 RSVD23 RSVD24 RSVD25

VerA:reserve Pull-up and Pull-down resistor 071026 +V1.05S

ns

ns

{6} MCH_BSEL0 {6} MCH_BSEL1 {6} MCH_BSEL2 ns ICTP T41 ns ICTP T44

CFG5 CFG6 CFG7 CFG9 CFG10

ns ICTP T36

CFG12 CFG13

ns ICTP T39 ns ICTP T34

CFG16

ns ICTP T27 ns ICTP T38

{23} PM_SYNC# {7,22,41} H_DPRSTP#

B

ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP

T122 T121 T112 T109 T118 T56 T114 T129 T57 T116 T125 T130 T126 T128 T124 T115 T58 T117 T55 T111 T113 T110 T108 T107 T26

0 R133 0 R368 PM_EXTTS#0 PM_EXTTS#1 R0402 0 R158 R0402 100 R160 R0402 0 R130

TP_CN1 TP_CN2 TP_CN3 TP_CN4 TP_CN5 TP_CN6 TP_CN7 TP_CN8 TP_CN9 TP_CN10 TP_CN11 TP_CN12 TP_CN13 TP_CN14 TP_CN15 TP_CN16 TP_CN17 TP_CN18 TP_CN19 TP_CN20 TP_CN21 TP_CN22 TP_CN23 TP_CN24 TP_CN25

T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28

R29 B7 N33 P32 AT40 AT11 T20 R32

BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25

CLK

NC

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

R0402 R0402

ME_JTAG_TMS

PM

{23} PM_ICH_PWROK {19,23,26,27,28,31,33,51} BUF_PLT_RST# {7,22,31} PM_THRMTRIP# {23,41} PM_DPRSLPVR

CFG19 CFG20

ME_JTAG_TDO

AM35

CFG

ns ICTP T25

ME_JTAG_TDI

DMI

ns

AK34 AN35

ME

ns

ME_JTAG_TCK

MISC

R150R144R161R155 10K 10K 10K 10K

AL34

GRAPHICS VID

ns

HDA

ns

ME JTAG

ns

AP24 AT21 AV24 AU20

SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1

AR24 AR21 AU24 AV20

SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1

BC28 AY28 AY36 BB36

SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1

BA17 AY16 AV16 AR13

SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1

BD17 AY17 BF15 AY13

SM_RCOMP SM_RCOMP#

BG22 BH21

SM_RCOMP_VOH SM_RCOMP_VOL

BF28 BH28

SM_VREF SM_PWROK SM_REXT SM_DRAMRST#

AV42 AR36 BF17 BC36

DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#

R151R146R156R154 1K 1K 1K 1K C

ns

SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1

PEG_CLK PEG_CLK#

M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3

{15} {15} {16} {16}

M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 M_CKE0 M_CKE1 M_CKE2 M_CKE3

D

{15} {15} {16} {16}

CFG5

M_CS#0 M_CS#1 M_CS#2 M_CS#3 M_ODT0 M_ODT1 M_ODT2 M_ODT3

+V1.8

{15,17} {15,17} {16,17} {16,17}

R423 80.6,1% R0402

R422 20,1% R0603 ns

SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL

R413 20,1% R0603 ns

SM_VREF

LOW = Normal(Default) CFG19 (DMI Lane High =Lane Reversal Reversal)

+V3.3S

CFG20 R97 4.02K,1% ns

DREFCLK DREFCLK# DREFSSCLK DREFSSCLK#

{6} {6} {6} {6}

For DDR3:GMCH requires this pin never to be driven high before DDR voltage has ramped to stable value. For DDR2:connect to GND

AE41 AE37 AE47 AH39

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

AE40 AE38 AE48 AH40

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

AE35 AE43 AE46 AH42

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

AD35 AE44 AF46 AH43

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

B33 B32 G33 F33 E33

CFG20

LOW = Reverse Lane(default) CFG9 PCIe raphicsHigh = Normal opertion Lane

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

{23} {23} {23} {23}

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

{23} {23} {23} {23}

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

{23} {23} {23} {23}

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

{23} {23} {23} {23}

Design Note: Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time

R362 2.2K ns

CFG10

C

CFG12

R363 2.2K ns

CFG13

R135 2.2K ns

R132 2.2K ns

Reference CRB 1.201a CFG6 High =The iTPM Host Interface CFG6 (iTPM Host is disabled(default) Interface) Low =The iTPM Host Interface is enabled

R128 2.2K ns

CFG7

AH37 AH36 AN36 AJ35 AH34

R96 4.02K,1% ns

CFG9

CLK_MCH_3GPLL {6} CLK_MCH_3GPLL# {6}

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF

Low = Only Digital Display Port (SDVO/DP/iHDMI) or PCIE or is operational(Default) High = Digital Display Port(SDVO/DP/iHDMI) and PCIE are operating simultaneously via PEG port

CFG19

F43 E43

C34

R124 2.2K ns

LOW = Dynamic ODT Disable High = Dynamic ODT Enable(default)

R185 DDR2: Leave as No Connect. 499,1%

B38 A38 E41 F41

GFX_VR_EN

CFG16 (FSB Dynamic ODT)

+V3.3S

Loyout note: Route as short as possible

R414 80.6,1% R0402

+V3.3S

CFG7 (Intel ME Crypto Transport Strap)

Change to ns , PU at CLK GEN By Johan 071108

R122 10K R0402 ns

Low = AMT Firmware will use TLS cipher suite with no confidentiality (Isolators are bypassed) High = AMT Firmware will use TLS cipher suite with Confidentiality {Isolators are active (Default)}

Low =disabled(default) CFG10 (PCIE Loopback High=enabled enable)

CFG12 (ALL Z)

Low =disabled(default) High=ALL Z Mode enabled

CFG13 (XOR)

Low =disabled(default) High=XOR Mode enabled

R126 2.2K ns

+V1.8 B

R418 1K,1% R0402

PCIE_CLKREQ# +V1.05S SM_RCOMP_VOH

R159

0

R0402

MCH_CLVREF

R142 1K,1% R0402

CL_CLK0 {23} CL_DATA0 {23} PM_ICH_PWROK {23} CL_RST#0 {23}

1.These signals serve as DDC signals for iHDMI port C&B 2.SDVO_CTRLDATA&DDPC_CTRLDATA should both be high to enable display port

DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC#

N28 M28 G36 E36 K36 H36

TSATN#

B12

R354

0 R0402

HDMI_DDC_CLK {21} HDMI_DDC_DATA {21} PCIE_CLKREQ# {6} MCH_ICH_SYNC# {23}

R353 1K ns

R356 1K ns

R369 56 R370

C359 C0805

R419 3.01K,1% R0402

SM_RCOMP_VOL MCH_TSATN#

{33} C354

1

330 ns

1

1.Checklist:500ohm CRB:511ohm 2.use 500ohm resistor accord with the advice of KAM

B28 B30 B29 C29 A28

C355 0.01uF/16V,X7R C0402

+V1.05S

use for the AUX2 trip point

HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC

+V3.3AL

R145 499,1% R0402

C86 0.1UF/25V,Y5V C0402

0.01uF/16V,X7R C0402

Q16 MMBT3904-F ns

C358 C0805

R417 1K,1% R0402

Q20 MMBT3904-F ns

AZALIA_HDMI_BITCLK {22} AZALIA_HDMI_RST# {22} AZALIA_HDMI_SDATAIN2 AZALIA_HDMI_SDOUT {22} AZALIA_HDMI_SYNC {22}

+V1.8

R225 10K,1% ns {15,16,37} SM_VREF_L

{22} AZALIA_SDATAIN2

R647

33

R0402 AZALIA_HDMI_SDATAIN2 HDMI

5

R364 2.2K ns

LOW = DMI x 2 High =DMI x 4(Default)

CFG5

{15,17} {15,17} {16,17} {16,17}

CANTIGA_1p2

A

CFG16

{15,17} {15,17} {16,17} {16,17}

2.2uF/10V,X7R

R0402

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9

2.2uF/10V,X7R

0

M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12

3

R127 ns

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9

2

PM_EXTTS#0

T32 T35 T40 T43 T46 T49 T48 T47 T31

3

R123 10K R0402

ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP ICTP

2

D

ns ns ns ns ns ns ns ns ns

DDR CLK/ CONTROL/COMPENSATION

U13B +V3.3S

4

3

PR71

Close The CAP to GMCH

A

SM_VREF

0

TOPSTAR TECHNOLOGY C153 C155 0.1UF/25V,Y5V 0.1UF/25V,Y5V

R227 10K,1% ns

NOTE:If the voltage regulator for the system memory interface already supplies a VREF output and meets the voltage tolerance and current requirements for these pins, then a voltage divider would not be needed.

2

bent Page Name

CANTIGA(DMI&CLK)

Size C

M46G

Project Name

Rev B

Thursday, August 27, 2009 12 51 Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 1

5

4

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com

+V1.8 +V1.05S

{12,14,15,16,37,40,42} {6,7,8,9,12,14,22,24,31,38,40,41,42,44}

U13G

Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8

VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296

CANTIGA_1p2

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4

BH48 BH1 A48 C1

VSS_SCB_6

A3

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 NC_43

C360 C0402

0.1UF/10V,X7R

C362 C0805

C352 C0402

0.1UF/10V,X7R 10UF/6.3V,X5R

C356 C0402 0.1UF/10V,X7R

C105 C114 C106 C101 C109 C0402 C0402 C0402 C0402 C0402 ns ns ns 0.1UF/10V,X7R 0.1UF/10V,X7R ns 0.1UF/10V,X7R ns 0.1UF/10V,X7R 0.1UF/10V,X7R

+V1.05S

cost down

080510

hads

C503 + ns CT7343_19

220UF/2.5V,POSCAP VerB:change the type of C503 at the demand of ME

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48 A47

+V1.05S

BA36 BB24 BD16 BB21 AW16 AW13 AT13

VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC

Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42

AJ14 AH14

VCC_AXG_SENSE VSS_AXG_SENSE

VCC SM

1

U24 U28 U25 U29 AJ6

2

VSS_351 VSS_352 VSS_353 VSS_354 VSS_355

C124 C0805 10UF/6.3V,X5R

C

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

AV44 BA37 AM40 AV21 AY5 AM10 BB13

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

C111

C95

C107

C103

C93

C110

C108

C0402 C0402 C0603 C0603 C0603 C0603 C0603 0.1UF/10V,X7R 0.47UF/25V,Y5V 0.22UF/10V,X7R 1uF/10V,X7R 0.1UF/10V,X7R 0.22UF/10V,X7R 1uF/10V,X7R

R141 1K ns

VerA:Reserve PU&PD resistor though it's suggested that this two pin could be NC

D

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

B

R153 1K ns

CANTIGA_1p2

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC SM LF

VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

ns +

220UF/2.5V,POSCAP

VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35

VCC GFX NCTF

AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

C125 CT7343_19

+V1.05S AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29

VCC GFX

VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

1

VSS_235

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

2

BA16 AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13

VSS

VSS NCTF

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23

VSS SCB

VSS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233

1

B

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17

1

C

AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36

U13J

NC

U13I

POWER

+V1.8

D

CANTIGA_1p2

A

A

TOPSTAR TECHNOLOGY bent Page Name

CANTIGA(VSS&NCTF)

Size C

M46G

Project Name

Rev B

Date: Sheet Thursday, August 27, 2009 13 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com

CHANGED

+V3.3S +VCC_PEG +V1.8 +V1.5S +V1.05S

{6,7,10,12,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51} {10} {12,13,15,16,37,40,42} {8,22,24,26,27,28,30,38,40,42} {6,7,8,9,12,13,22,24,31,38,40,41,42,44}

+V3.3S +V1.05S +3.3S_A_CRT_DAC +V1.05S

C505 C504 0.1UF/10V,X7R 0.01uF/16V,X7R C0402

U13H

+V1.05S_HPLL C321

R398 R0603 +V1.8 1 C0402 C0402 C316 0.1UF/10V,X7R +V3.3S 10UF/6.3V,X5R 0.1UF/10V,X7R C0805 R139 0 +V1.5S R0603 ns R140 R0603 0

13.2mA C508 10UF/6.3V,X5R C0805

414uA

J48

VCCA_LVDS

J47

VSSA_LVDS

AD48

480mA~720mA C89 C0805

C97 C0603

C99 C0402

4.7uF/6.3V,X5R 0.1UF/10V,X7R 10UF/6.3V,X5R 1uF/10V,X7R

+V1.05S

FB9

R0603

0

R365

35mA

0

C56 C0402

C57 C0402

79mA

0 R0402

B24 A24

VCC_HDA OPTION changed 0805089

No HDMI

C53 C0603

A32

+V1.5S_QDACL28

157.2mA +V1.5S

50mA +V1.05S_PEGPLL AA47

C483

C484

M38 L37

FB35 R0603

HDMI

0 0.1UF/10V,X7R C0402

VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL

0.1UF/10V,X7R

+V1.5S_QDAC

VCC_HDA

R0402 0

C73 C0402

AF1

VCCD_TVDAC

VCCD_LVDS_1 VCCD_LVDS_2

60.31mA C511

0.01uF/16V,Y5V C0402

1uF/10V,X7R C0603 ns

AXF

321.35mA

B22 B21 A21

C59 C0402

C58 R105R0603 C0805

SM CK

VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34

T32

VCC_35

+V1.05S C

C76 C0805 10UF/6.3V,X5R

0

+V1.8

119.85mA~124mA BF21 BH20 BG20 BF20

VCC_TX_LVDS

K47

VCC_HV_1 VCC_HV_2 VCC_HV_3

C35 B35 A35

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4

AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23

0.1UF/10V,X7R10UF/6.3V,X5R

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

C357 C0402 0.1UF/10V,X7R

C361 R420 10UF/6.3V,X5R 1 C0805

2 FB0805

R0603 300ohm@100MHz,1.5A C363 10UF/6.3V,X5R C0805 +V_TXLVDS

105.3mA

+V1.8 R650

0

R0603

+V3.3S C55 C0402 0.1UF/10V,X7R

V48 +VCC_PEG U48 V47 U47 U46 AH48 AF48 AH47 AG47

FB28 1

C510 10UF/6.3V,X5R C0805 +VCC_PEG

+V1.05S

1782mA C312 C0603 1uF/10V,X7R

0 R0805

R399

0 R0805

C314 C302 10UF/6.3V,X5R C0805 C0805 10uF/6.3V,X5R

456mA(Only in 1.25V) C327 C0603

R379

+V1.05S

C334 CT7343_19 CT4 + 1uF/10V,X7R ns C0805 220UF/2.5V,POSCAP 10uF/6.3V,X5R 2

500uA

50mA

VCC_HDA

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33

1

R651

VCCA_TV_DAC_1 VCCA_TV_DAC_2

hads M25

0.1UF/10V,X7R 0.022uF/16V,X7R 1uF/10V,X7R +V1.05S

B

VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_SM_CK_3 VCCA_SM_CK_4 VCCA_SM_CK_5 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8

HV

+V1.5S

R0603

C509 0.022uF/16V,X7R C0402

AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23

PEG

1N4148WS SOD323

FB34

R1360 R0402

DMI

10 R0402

+V3.3S

C487

0.1uF/10V,X5R C0402

CANTIGA_1p2

VTTLF1 VTTLF2 VTTLF3

VTTLF

+V3.3S R87

2

+V1.05S

+V1.05S

C102 C100 C96 C0603 C0603 C0402 ns ns 1uF/10V,X7R 0.1UF/10V,X7R 10UF/6.3V,X5R 1uF/10V,X7R D7 1

Hads 080510

C80 C0805 10UF/6.3V,X5R

24mA~26mA

0

C104 C0805

+V1.05S

2898mA VerV:Ns C75

POWER

A CK

R0603

VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9

U13F

0.1uF/10V,X5R C0402 C488

TV

R157

AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16

D

C87 C0805 10UF/6.3V,X5R

C77 2.2uF/10V,X7R C0805

VCC NCTF

C98 C0805

C

VCCA_PEG_PLL

C78 C0805 10uF/6.3V,X5R

A SM

0 R0805

VCCA_PEG_BG

50mA

+V1.05S_PEGPLLAA48 R149

VCCA_HPLL VCCA_MPLL

C81 0.1UF/10V,X7R C0402

place close to (G)MCH +V1.05S

VCCA_DPLLB

AE1

HDA

CHANGED

+V1.05S_MPLL

C91 C75 C83 C0402 C0805 10UF/6.3V,X5R C0805 0.1UF/10V,X7R ns 10uF/6.3V,X5R

1

C322

VTT

64.8mA L48 24mAAD1

+V1.05S_DPLLB +V1.05S_PEGPLL

VCCA_DPLLA

D TV/CRT

50mA

F47

PLL

+V1.05S_DPLLA

+V1.05S FB23 1 2 FB0805 300ohm@100MHz,1.5A

VCCA_DAC_BG VSSA_DAC_BG

64.8mA

852mA

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

VCC CORE

+3.3S_A_CRT_DAC_BG A25 C506 B25 0.01uF/16V,X7R

C507 0.1UF/10V,X7R C0402

VCCA_CRT_DAC_1 VCCA_CRT_DAC_2

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25

POWER

414uA

R649 R0603 0

B27 A26

CRT

73mA

D

A LVDS

0

A PEG

R0603

LVDS

R648

A8 L1 AB2 C313

C310

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

B

C287

C0603 0.47UF/25V,Y5V C0603 0.47UF/25V,Y5V C0603 0.47UF/25V,Y5V

+V1.8

CANTIGA_1p2

+V1.05S

FB22

R0603

0

24mA+V1.05S_HPLL C319

L3

L1008 82nH ns 1

0.1UF/10V,X7R C318 10UF/6.3V,X5R C0805

DG:The usage of Ferrite bead is under investigation. A stuffing option should be provided in case the investigation results suggests the need of a Ferrite bead. The CRB schematics currently uses a Zero-Ohm resistor in place of the Ferrite bead.

+V1.05S

FB36

R0603

0

24mA+V1.05S_DPLLA

139.2mA A

FB24 1 2 FB0603 120ohm@100MHz,500mA R400

R0603

C512 10UF/6.3V,X5R C0805

+V1.05S_MPLL

C513 0.1UF/10V,X7R A

C328

CHANGED

139.2mA

0 0.1UF/10V,X7R FB37

C325 10UF/6.3V,X5R C0805

0

R0603

R652

R0603

+V1.05S_DPLLB 0

TOPSTAR TECHNOLOGY bent

C514 0.1UF/10V,X7R

C515 10UF/6.3V,X5R C0805

5

4

Page Name

CANTIGA(POWER)

Size C

M46G

Project Name

Rev B

Date: Sheet Thursday, August 27, 2009 14 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 3

2

1

5

4

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com

BA0 BA1

110 115

CS0 CS1

M_CS#0 M_CS#1 MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

10 26 52 67 130 147 170 185

DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7

109 113 108

WE CAS RAS

{12,17} M_CKE0 {12,17} M_CKE1

79 80

CKE0 CKE1

M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1

30 32 164 166

CK0 CK0 CK1 CK1

114 119

ODT0 ODT1

13 31 51 70 131 148 169 188

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

195 197

SDA SCL

198 200

SA0 SA1

199

VDDSPD

{11} MA_DM[7:0] {11,17} MA_A_WE# {11,17} MA_A_CAS# {11,17} MA_A_RAS#

C

{12} {12} {12} {12}

{12,17} M_ODT0 {12,17} M_ODT1 MA_DQS0 MA_DQS1 MA_DQS2 MA_DQS3 MA_DQS4 MA_DQS5 MA_DQS6 MA_DQS7

{11} MA_DQS[7:0]

{6,16,23,26,27,28} {6,16,23,26,27,28}

+V3.3S

B

C0402

R232 R233

Note: SO-DIMM0 SPD Address is 0xA0 SO-DIMM0 TS Address is 0x30

{12,16,37} SM_VREF_L C154

0.1UF/25V,Y5V C152

SMB_DATA_S SMB_CLK_S

2.2UF/10V,X7R C0805

R226

10K R0402 10K R0402

0

C166 0.1UF/25V,Y5V C0402

1 C169 2.2UF/10V,X7R

83 120 50 69 163

C0805

187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162

1010 000x

VREF1 NC1 NC2 NC3 NC4 NCTEST

47 133 183 77 12 48 184 78 71 72 121 122 196 193 8 18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177

close to DDR pin

DDRII

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33

{12,17} {12,17}

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7

11 29 49 68 129 146 167 186

MA_DQS#0 MA_DQS#1 MA_DQS#2 MA_DQS#3 MA_DQS#4 MA_DQS#5 MA_DQS#6 MA_DQS#7

+V1.8

1

107 106

5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194

C179 + ns

C160 C168 C173 C174 C156 C162 C158 ns ns ns C0402 C0805 C0805 C0402 C0805 C0402 C0805 CT7343_19 0.1UF/25V,Y5V 2.2UF/10V,X7R 2.2UF/10V,X7R 2.2UF/10V,X7R 2.2UF/10V,X7R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 220UF/2.5V,POSCAP 2

{11,17} MA_A_BS#0 {11,17} MA_A_BS#1

{11,17} MA_A_A14

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63

GND0 GND1

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2

D

MA_DATA[63:0] {11}

1, A minimum of 9 high frequency capacitors are recommended to be placed near each SO-DIMM of DDR2. 2, 2.2μF*5 per DIMM,0.1μF*4 per DIMM,330μF*1 per DIMM

+V1.8

C157

C172

C0805 C0402 2.2UF/10V,X7R 0.1UF/25V,Y5V

C164 C163 C159 C161 ns C0805 C0402 C0805 C0402 2.2UF/10V,X7R 2.2UF/10V,X7R 0.1UF/25V,Y5V 0.1UF/25V,Y5V C

Layout note:电容靠近DDR slot VDD PIN

B

MA_DQS#[7:0]

{11}

201 202

{11,17} MA_A_BS#2

102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85

SO-DIMM 0

1

MA_A_A0 MA_A_A1 MA_A_A2 MA_A_A3 MA_A_A4 MA_A_A5 MA_A_A6 MA_A_A7 MA_A_A8 MA_A_A9 MA_A_A10 MA_A_A11 MA_A_A12 MA_A_A13 MA_A_A14

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12

{11,17} MA_A_A[13:0]

VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

D

{6,7,10,12,14,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51} {12,13,14,16,37,40,42}

DIM1 DDR2_SODIMM200 DDR200RVS_5D2

112 111 117 96 95 118 81 82 87 103 88 104

+V1.8

+V3.3S +V1.8

{12} DIM_EXTTS#0

A

A

TOPSTAR TECHNOLOGY bent Page Name

DDR2 SODIMM0

Size C

M46G

Project Name

Rev B

Date: Sheet Thursday, August 27, 2009 15 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162

112 111 117 96 95 118 81 82 87 103 88 104

SO-DIMM 1

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2

{11,17} MB_B_BS#0 {11,17} MB_B_BS#1

107 106

BA0 BA1

110 115

CS0 CS1

10 26 52 67 130 147 170 185

DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7

109 113 108

WE CAS RAS

{12,17} M_CKE2 {12,17} M_CKE3

79 80

CKE0 CKE1

M_CLK_DDR2 M_CLK_DDR#2 M_CLK_DDR3 M_CLK_DDR#3

30 32 164 166

CK0 CK0 CK1 CK1

114 119

ODT0 ODT1

13 31 51 70 131 148 169 188

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

195 197

SDA SCL

198 200

SA0 SA1

199

VDDSPD

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

{11} MB_DM[7:0] {11,17} MB_B_WE# {11,17} MB_B_CAS# {11,17} MB_B_RAS# C

{12} {12} {12} {12}

{12,17} M_ODT2 {12,17} M_ODT3 MB_DQS0 MB_DQS1 MB_DQS2 MB_DQS3 MB_DQS4 MB_DQS5 MB_DQS6 MB_DQS7

{11} MB_DQS[7:0]

{6,15,23,26,27,28} {6,15,23,26,27,28}

SMB_DATA_S SMB_CLK_S R517 R514

Note: SO-DIMM1 SPD Address is 0xA4 SO-DIMM1 TS Address is 0x34

{12,15,37} SM_VREF_L

R241

10K R0402 10K R0402

0

1

VREF1

close to DDR pin199

2.2UF/10V,X7R C0805

83 120 50 69 163

close to DDR pin1

NC1 NC2 NC3 NC4 NCTEST

47 133 183 77 12 48 184 78 71 72 121 122 196 193 8 18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177

B

C197 0.1UF/25V,Y5V C0402

DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7

11 29 49 68 129 146 167 186

MB_DQS#0 MB_DQS#1 MB_DQS#2 MB_DQS#3 MB_DQS#4 MB_DQS#5 MB_DQS#6 MB_DQS#7

1010 010x

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33

C191 2.2UF/10V,X7R C0805

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

DDRII

C193 C200 0.1UF/25V,Y5V C0402

5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194

GND0 GND1

M_CS#2 M_CS#3

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63

MB_DATA[63:0] {11} D

+V1.8

C123 C211 C213 C218 C201 C203 C206 C215 C202 ns ns C0805 C0805 C0402 C0805 C0805 C0402 C0805 C0805 C0402 2.2UF/10V,X7R 2.2UF/10V,X7R 0.1UF/25V,Y5V 2.2UF/10V,X7R 10UF/6.3V,X5R 0.1UF/25V,Y5V 2.2UF/10V,X7R 2.2UF/10V,X7R 0.1UF/25V,Y5V +V1.8 C195 10uF/6.3V,X5R C0805

C194 10uF/6.3V,X5R C0805

+V1.8

C171 C205 C214 C204 C207 C199 C216 C212 ns ns ns C0402 C0805 C0805 C0402 C0805 C0402 C0805 C0805 0.1UF/25V,Y5V2.2UF/10V,X7R 2.2UF/10V,X7R 0.1UF/25V,Y5V 2.2UF/10V,X7R 0.1UF/25V,Y5V 2.2UF/10V,X7R 2.2UF/10V,X7R ns

C

Layout note:电容靠近DDR slot VDD PIN

MB_DQS#[7:0]

{11} B

201 202

{12,17} {12,17}

VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

{11,17} MB_B_BS#2

102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85

{11,17} MB_B_A14

+V3.3S

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12

{11,17} MB_B_A[13:0] MB_B_A0 MB_B_A1 MB_B_A2 MB_B_A3 MB_B_A4 MB_B_A5 MB_B_A6 MB_B_A7 MB_B_A8 MB_B_A9 MB_B_A10 MB_B_A11 MB_B_A12 MB_B_A13 MB_B_A14

{6,7,10,12,14,15,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51} {12,13,14,15,37,40,42}

DIM2 DDR2_SODIMM200,H9.2 DDR200RVS_9D2

+V1.8

D

+V3.3S +V1.8

{12} DIM_EXTTS#1

A

A

TOPSTAR TECHNOLOGY bent Page Name

DDR2 SODIMM1

Size C

M46G

Project Name

Rev B

Date: Sheet Thursday, August 27, 2009 16 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

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2

1

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+V0.9S

{18,37,42}

D

D

+V0.9S +V0.9S RN15 56x4 1 3 5 7

C

RA0402_8 2 4 6 8

MB_B_A9 MB_B_A12

RN24 56x4 1 3 5 7

RA0402_8 2 4 6 8

MB_B_A4 MB_B_A6 MB_B_A7 MB_B_A11

RN18 56x4 1 3 5 7

RA0402_8 2 4 6 8

MB_B_A8 MB_B_A5 MB_B_A1 MB_B_A3

RN19 56x4 1 3 5 7

RA0402_8 2 4 6 8

MA_A_A8 MA_A_A5 MA_A_A3 MA_A_A1

RN21 56x4 1 3 5 7

RA0402_8 2 4 6 8

RN17 56x4 1 3 5 7

RA0402_8 2 4 6 8

MA_A_A12 MA_A_A9

MB_B_BS#2

{11,16}

M_CKE2

{12,16}

RN23 56x4 1 3 5 7

RA0402_8 2 4 6 8

RN20 56x4 1 3 5 7

RA0402_8 2 4 6 8

RN14 56x4 1 3 5 7

RA0402_8 2 4 6 8

RN13 56x4 1 3 5 7

RA0402_8 2 4 6 8

MB_B_A0 MB_B_A2

MB_B_RAS# MB_B_BS#1

{11,16} {11,16}

MA_A_BS#0 MA_A_WE# MA_A_CAS#

{11,15} {11,15} {11,15}

MA_A_BS#1 MA_A_RAS#

{11,15} {11,15}

MA_A_A10

MA_A_A2 MA_A_A0

C

MA_A_BS#2

{11,15}

MB_B_A10 MB_B_BS#0 MB_B_WE# MB_B_CAS#

{11,16} {11,16} {11,16}

B

R519 56 R238 56 R291 56

R0402 R0402 R0402

R450 56 R237 56

R0402 R0402

MA_A_A11 MA_A_A7 MA_A_A6 MA_A_A4

MB_B_A13 MA_A_A13 M_CKE3

{12,16}

M_CKE0 M_CKE1

{12,15} {12,15}

M_CS#1 M_ODT1

{12,15} {12,15}

RN22 1 3

2 56 4 RA0402_4

RN25 1 3

2 56 4 RA0402_4

M_ODT2 M_CS#2

{12,16} {12,16}

RN16 1 3

2 56 4 RA0402_4

M_CS#3 M_ODT3

{12,16} {12,16}

RN12 1 3

2 56 4 RA0402_4

M_CS#0 M_ODT0

{12,15} {12,15}

B

+V0.9S R236 56 R292 56

{11,15} MA_A_A[13:0]

R0402 R0402

MA_A_A14 MB_B_A14

MA_A_A14 MB_B_A14

{11,15} {11,16}

{11,16} MB_B_A[13:0]

TOPSTAR TECHNOLOGY bent

A

A

Page Name

DDR2 Series Termination

Size B

M46G

Project Name

Rev B

Date: Sheet of Thursday, August 27, 2009 17 51 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

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+V0.9S

{17,37,42}

D

D

Layout note:Place one cap close toevery 2 pullup resistors terminatedto +V0.9S

每4个电阻两个0.1UF电容

+V0.9S

C

C233 0.1UF/25V,Y5V C0402

C386 0.1UF/25V,Y5V C0402

C231 0.1UF/25V,Y5V C0402

C184 0.1UF/25V,Y5V C0402

C385 0.1UF/25V,Y5V C0402

C186 0.1UF/25V,Y5V C0402

C187 0.1UF/25V,Y5V C0402

C188 0.1UF/25V,Y5V C0402

C185 0.1UF/25V,Y5V C0402

C232 0.1UF/25V,Y5V C0402

C457 0.1UF/25V,Y5V C0402

C388 0.1UF/25V,Y5V C0402

C459 0.1UF/25V,Y5V C0402

C456 0.1UF/25V,Y5V C0402

C390 0.1UF/25V,Y5V C0402

C227 0.1UF/25V,Y5V C0402

C228 0.1UF/25V,Y5V C0402

C458 0.1UF/25V,Y5V C0402

C454 0.1UF/25V,Y5V C0402

C389 0.1UF/25V,Y5V C0402

C183 0.1UF/25V,Y5V C0402

C391 0.1UF/25V,Y5V C0402

C229 0.1UF/25V,Y5V C0402

C387 0.1UF/25V,Y5V C0402

C455 0.1UF/25V,Y5V C0402

C

C230 0.1UF/25V,Y5V C0402

B

B

TOPSTAR TECHNOLOGY bent

A

A

Page Name

DDR2 Decoupling

Size B

M46G

Project Name

Rev B

Date: Sheet of Thursday, August 27, 2009 18 51 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

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http://shop61976717.taobao.com http://shop61976717.taobao.com 500mA

LCDCON LCDCON2X20 CNS40_LCDB

LCDVDD

D

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

{10} LVDS_YAM0 {10} LVDS_YAP0 {10} LVDS_YAM2 {10} LVDS_YAP2 {10} LVDS_YBM0 {10} LVDS_YBP0

PANEL INTERFACE

{10} LVDS_YBM2 {10} LVDS_YBP2

EDID_CLK EDID_DATA

+5VAL_Camera BKLT_PWM +VDC

High : Enable Low : Disable CLOSE TO INTCON

+V3.3S

FB18 R0805

INVT_VDD

0

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

41 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

41 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

R329

0

R330 {32,33}

D23 2 SOD323

1 1N4148WS

LIDR#

D46 2 SOD323

1 1N4148WS

D25 2 SOD323

1 1N4148WS

{23,33} PM_SUS_STAT#

D24 2 SOD323

1 1N4148WS ns

+V5S

{20,21,23,24,25,30,31,32,33,38,41,42}

D

{10} {10}

LVDS_CLKAP {10} LVDS_CLKAM {10} LVDS_YBM1 LVDS_YBP1

{10} {10}

LVDS_CLKBP {10} LVDS_CLKBM {10} EDID_PWR LVDS_CAM_USB_PN4 LVDS_CAM_USB_PP4 BKLT_ON

C245

R3371.5A T-Fuse ns R0603

0.1UF/25V,Y5V M46G VerB:change the LCDCON the same as VerA,down-lead two channels of LVDS signal from the GMCH VerC:change the LCDCON the same as S46P--xiezx

100K

{33} HW_OFF_BKLT#

{28,32,34,36,37,38,41,42,44} {24,29,32,36,37,39,40,42} {12,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51} {6,7,10,12,14,15,16,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}

LVDS_YAM1 LVDS_YAP1

R332 1K {10} LVDS_BKLTEN

+VDC +V5AL +V3.3AL +V3.3S

BKLT_ON

C241 1000pF/50V,X7R

C

C

+V3.3S Add AND Gate BY bent 080218

{10} LVDS_VDDEN

D44 2 SOD323

1 1N4148WS

D45 2 SOD323

1 1N4148WS

R624 1K LCDVDD_ON

R11

R0402 0

R14

R0402 0

CHK1

C485

1 4

{23} CAM_USB_PN7 {23} CAM_USB_PP7

1000pF/50V,X7R

R625 100K

LVDS_CAM_USB_PN4 LVDS_CAM_USB_PP4

2 3 1

L4_0805 90ohm@100MHz,0.5A D1 D2

R0402

ns 0

R0402

EGA10603V05A1-B ESDPAD_R0603 ns 2

R626

ns

1

BUF_PLT_RST#

2

{12,23,26,27,28,31,33,51}

EGA10603V05A1-B ESDPAD_R0603 ns

4 5 6

+V5S

S

Q13 AO6409

VerA:Q45由6401改为6409 071027 D G R726 0 R0805

3 2 1 +V3.3AL

+V3.3S LCDVDD

500mA

C2 10UF/6.3V,X5R R2 C6 100 0.1UF/25V,Y5V C0805 0.01uF/16V,X7R R0603

2

+VDC R1 2.2K ns R8 100K

1 3

3

3

PQ1 2N7002 SOT23 1 C4

{33}

R7 100K

1

Camera_ON

R572 100K ns R0402

B

+5VAL_Camera FB17 300ohm@100MHz,1.5A FB0805

0.01uF/25V,X7R C0402 ns

C243 470pF/50V,X7R C0402

C244 10UF/6.3V,X5R C0805

R569 10K R0402

ns

2

SPWG Require LCDVDD rising time is 0.5-10ms,1-10ms is better

100pF/50V,NPO

1

R571 1K R0402

F1

ns Q36 2N7002 SOT23

ns LCDVDD_ON

1.5A T-Fuse ns R0603 3

C486

R570 10K R0402

R6 100K PQ2 2N7002 SOT23

Q35 AO3415 SOT23

+V5AL

C3

Q14 2N7002E-T1 SOT23

1 R333 100K

0 R0805

2

0

0 R0603 ns

FB1

2

R331

C5 0.047uF/16V,X7R ns

R3

2

LCDVDD 的参数取值待定. LCDVDD_ON

R5 100K ns

3

R10 10K

LCDVDD_EN#

B

Using EC to enable camera Power By Johan 071224

ns

{33} EC_BKLT_PWM

R335

0

+V3.3S +V3.3AL BKLT_PWM

A

{10} LVDS_BKLTCTL

R336

0 ns

R334 10K

C242

R12

100pF/50V,NPO

R13

0

R0603 0

R0603

ns

{10} L_DDC_CLK {10} L_DDC_DATA

EDID_PWR

C7

{23} PANEL_ID0 {23} PANEL_ID1

0.1UF/10V,X7R

R681 R682

0 0

R683 R684

0 0

EDID_CLK EDID_DATA

A

ns ns

TOPSTAR TECHNOLOGY bent Page Name Size C

Project Name

LVDS&Inverter CONN M46G

Rev B

Date: Sheet Tuesday, September 01, 2009 19 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

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1

5

CRT

4

INTERFACE

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com

+V3.3S +V5S

{6,7,10,12,14,15,16,19,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51} {19,21,23,24,25,30,31,32,33,38,41,42}

try to delete these components for cost down(need enhanced test) Cross moat place

D

VerC: ns

Place close to VGA port

Cross moat place

+V5S

D

VGA CONNECTOR +V5_VGA

ID1 1

ROUT

IR1 150,1%

5.6pF/50V,NPO

IC1

IFB3 47ohm/100MHz,500mA 1FB0603 2

NV suggest:2pf

GND_VGA CONNECTOR TOP VIEW

GND_VGA

6 1 7 2 8 3 9 4 10 5

GND_VGA+V5_VGA GOUT

IC5

5.6pF/50V,NPO

5.6pF/50V,NPO

ID3 BAV99 SOT23

2

IC4

1

IR3 150,1%

GND_VGA

2 120ohm/100MHz,500mA IR2 FB0603 100K IC3 0.1UF/25V,Y5V GND_VGA

3

NV suggest:22pf

IFB2

2 1

2

5.6pF/50V,NPO

{10} MCH_GREEN

1N5819 SOD123

ID2 BAV99 SOT23

1

150ohm电阻前走线阻抗50ohm (From GPU to CONN)

IC2

GND NC

11

SDA G GND HSYNC B

12

5VDDCDA

13

HSYNC

R GND

NC NC VSYNC GND GND shell

MCH_BLUE

VSYNC

15

5VDDCCK

shell

C10518-11505-L

IC6 15PF/50V,NPO

IC7 15PF/50V,NPO

IC8 15PF/50V,NPO

IC9 15PF/50V,NPO

ns

IC11

IR4 150,1%

CLK

14

BOUT

3

IC10

5.6pF/50V,NPO

ID4 BAV99 SOT23

5.6pF/50V,NPO

1

C

2

{10}

GND_VGA+V5_VGA

2 IFB4 FB0603 47ohm/100MHz,500mA

16

GND_VGA

1

VGA1 VGADMF

17

IFB1 47ohm/100MHz,500mA 1FB0603 2

MCH_RED

3

{10}

GND_VGA GND_VGA+V5_VGA

ESD: NV suggest use +3.3V Layout note: 1. +3.3V and GND Route >15mils trace width 2. No more than 75mils 3. ESD diode should no more than 10pf cap.

ns

GND_VGA

S46/修改成跟M21一致的VGA Conn。LJ081223

C

GND_VGA

VerB:stuff ID2,ID3,ID4 +V5_VGA IC12 0.1UF/25V,Y5V

+V5_VGA IC13 0.1UF/25V,Y5V GND_VGA

GND_VGA

GND_VGA

+V5_VGA

+V3.3S reserved ciucuit possibility to Cost down 1G125 follow design guide--0929 +V5_VGA

VerC: Del VR7

R724 8.2K R0402

2

{10} CRT_HSYNC

1

OE#

2

A

3

GND

VCC

5

Y

4

IC14

IC15

0.1UF/25V,Y5V

0.1UF/25V,Y5V

IC16 0.1UF/25V,Y5V

3

{10} CRT_VSYNC

2

A

3

GND

VCC

5

Y

4

3

5VDDCDA

3

VerC: Change to bat54s

1 +V3.3S GND_VGA

+V3.3S

GND_VGA

VerB:BAV99由DIODES改为PHILIPS的 for cost down +V5_VGA071016

VerC: Change to bat54s

Near U5/U6 ASAP

+V5_VGA

IR7

39

HSYNC

IR8

39

VSYNC

2 HSYNC

3

IC17 0.1UF/25V,Y5V

R725 8.2K R0402 {10} CRT_DDC_CLK

Q38 BSS138 SOT23

2

ID8

2 3

5VDDCCK

3

1 BAT54SPT

CRT_V_SYNC

B

BAT54SPT SOT23

ID7

OE#

2

SOT23 CRT_H_SYNC

+V5_VGA

ID6

1

ID5 BAT54SPT

IU2 74AHCT1G125 SOT23_5

1

2

{10} CRT_DDC_DATA

IR6 2.2K

1

VSYNC IU1 74AHCT1G125 SOT23_5

B

IR5 2.2K

Q37 BSS138 SOT23

1 +V3.3S GND_VGA

1

+V5_VGA

BAT54SPT

SOT23

GND_VGA

SOT23

Demo has no voltage lever shifter

H18

1

HOLE TH_315_118_P ns

A

HOLE TH_315_118_P ns

1

IH1

IM1

IM3

1 1 FMARKS ns

1 1 FMARKS ns

A TOPSTAR TECHNOLOGY bent

IO_CASE_GND Page Name Size Project Name Custom

CRT Interface M46G

Rev A

Tuesday, September 01, 2009 20 51 Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

5

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Cross moat place

FB25

D31

1 +V3.3S

+V3.3S

+V3.3S

R655 4.7K R653 4.7K ns

DDC_EN

2 1

1N5819HW-F SOD123 HDMI

+V3.3AL +V3.3S +V5S

2120ohm@100MHz,500mA FB0603 HDMI

C94 0.1UF/25V,Y5V C0402 HDMI

R656 4.7K

ns

{12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51} {6,7,10,12,14,15,16,19,20,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51} {19,20,23,24,25,30,31,32,33,38,41,42}

R152 100K R0402 HDMI

TMS_EN

HDMI R657 0 ns

DDCBUF_EN

D

R654 4.7K

+V5_HDMI

R658 0

GND_HDMI

D

Add for EMC issue By Johan 071227

GND_HDMI

CFG

HDMI GND

GND HDMI

+V3.3S

C516 0.01uF/25V,X7R

R580HDMI 0 R0603 R582 0 HDMI R0603

TMS_EN

HDMIHP_C 5VDDCDA_HDMI 5VDDCCK_HDMI

DDC_EN

CFG DDCBUF_EN

G7 G6 36 35 34 33 32 31 30 29 28 27 26 25 G5 G4

{10} IN_D1+ {10} IN_D1{10} IN_D0+ {10} IN_D0{10} MCH_CLK_D4+ {10} MCH_CLK_D4-

g7 g6 GND7 FUNCTION4 FUNCTION3 VCC3V5 DDC_EN GND6 HPD_SINK SDA_SINK SCL_SINK GND5 VCC3V4 TMDS_EN g5 g4

colay common choke and res GND G1 49 24 23 22 21 20 19 18 17 16 15 14 13 G2 G3

CH7318 GND

4 1

3 2 ns

100M0.33A l4_0805

R584 0 R0603 R586 HDMI 0 R0603 HDMI

100M0.33A l4_0805 CHK10 4 1

3 2 ns

1 2 3 4 5

IFPC_TXD4P IFPC_TXD4N GND_HDMI GC104 ns IFPC_TXC IFPC_TXC# 0.1UF/25V,Y5V

1 2 3 4 5

LINE_1 LINE_2 VDD LINE_3 LINE_4

NC4 NC3 GND NC2 NC1

GU11 AZ1045 LINE_1 LINE_2 VDD LINE_3 LINE_4

NC4 NC3 GND NC2 NC1

100M0.33A R585 l4_0805 0 R0603 R587 HDMI 0 R0603

ns 10 9 8 7 6

IFPC_TXD6P 1 2 IFPC_TXD6N 3 IFPC_TXD5P 4 5 IFPC_TXD5N 6 IFPC_TXD4P 7 ns 10 8 IFPC_TXD4N 9 9 IFPC_TXC 10 8 7 11 IFPC_TXC# 12 6 13 14 5VDDCCK_HDMI 15 GND_HDMI 5VDDCDA_HDMI 16 17 18 +V5_HDMI HDMIHP_C 19

HDMI

HDMI +V3.3S GND intel demo 499 and chro demo 1.2k by homy 1029

HDMI OUT_D2+_ESD OUT_D2-_ESD

C520 0.01uF/25V,X7R

C521 0.01uF/25V,X7R

GND_HDMI

HDMI_D_1A 620401900007

C

HDMI

HDMI

OUT_D0+_ESD OUT_D0-_ESD CLK_D4+_ESD CLK_D4-_ESD +V3.3S

+V5_HDMI +V5_HDMI C522 0.01uF/25V,X7R R661 2.2K

R660 2.2K

5VDDCCK_HDMI 5VDDCDA_HDMI HDMI

by xiezx

GND

HDMI

{10}

MCH_HDMI_HPD#

499,1% PS8101

GND 7318

22 23

OUT_D1+_ESD OUT_D1-_ESD

R659

Colay 8101 and

20 21

GND_HDMI

HDMI +V3.3S R890 1.2K CH7318

D2+ D2 SHTELD D2D1+ D1 SHTELD D1D0+ GND1 D0 SHTELD GND2 D0CK+ CK SHTELD GND3 CKGND4 CEC RESERVED SCL SDA DCC/CEC_GND +5V HP_DET

GND HDMI_DDC_DATA HDMI_DDC_CLK

C

3 2 ns

CLK_D4+_ESD CLK_D4-_ESD

g1 gnd10 GND4 OUT_D1OUT_D1+ VCC3V3 OUT_D2OUT_D2+ GND3 OUT_D3OUT_D3+ VCC3V2 OUT_D4OUT_D4+ g2 g3

GND8 IN_D1IN_D1+ VCC3V6 IN_D2IN_D2+ GND9 IN_D3IN_D3+ VCC3V7 IN_D4IN_D4+

CHK8

CHK9 OUT_D0+_ESD 4 OUT_D0-_ESD 1

GND VCC3V FUNCTION1 FUNCTION2 GND1 ANALOG1(REXT) HPD_SOURCE SDA_SOURCE SCL_SOURCE ANALOG2 VCC3V1 GND2 gnd18

37 38 39 40 41 42 43 44 45 46 47 48

{10} IN_D2+ {10} IN_D2-

100M0.33A l4_0805

IFPC_TXD6P IFPC_TXD6N ns GND_HDMI GC97 IFPC_TXD5P IFPC_TXD5N 0.1UF/25V,Y5V

1 2 3 4 5 6 7 8 9 10 11 12 G8

GND

PC0 PC1

U20

3 2 ns

OUT_D1+_ESD OUT_D1-_ESD

C518 C519 0.01uF/25V,X7R 0.01uF/25V,X7R HDMI HDMI

GU10 AZ1045

OUT_D2+_ESD 4 OUT_D2-_ESD1

HDMI

+V3.3S

HDMI_CON

CHK7

C517 0.01uF/25V,X7R

HDMI GND

R581 HDMI 0 R0603 R583 0 R0603 HDMI

B

B

+V3.3S

R662 4.7K

R663 4.7K PS8101

R664 2.2K HDMI

+V5_HDMI HDMI_DDC_DATA

{12} R666

R0402 Colay 8101 and

R665 2.2K HDMI

PC1

ns PC0

+V3.3S

7318

R0402

HDMI_DDC_CLK

GC164

{12}

0.1UF/25V,Y5V C0402 HDMI

by xiezx change 4.7k to 2.2k 080508

hads

0

GND_HDMI R896 4.7K CH7318

HDMI GND

VerC:PC1 PD to GND for CH7318;PU for PS8101--XIEZX

GND_HDMI

A

A

TOPSTAR TECHNOLOGY GND_HDMI bent Page Name

HDMI

Size C

M46G

Project Name

Rev B

Date: Sheet Tuesday, September 01, 2009 21 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com Note:The new SRTCRST# signal is used to reset the RTC registers used for the Intel Management Engine when the on-board battery is changed. The external capacitor and the external resistor between SRTCRST# and VccRTC were selected to create an RC time delay, such that RTCRST# will go high some time after the battery voltage is valid. The RC time delay should be in the range of 18 ms to 25 ms. There must not be a jumper for SRTCRST# pin. The SRTCRST# does not impact the implementation of CMOS clearing.

ICH_EC_RTC 332K 1% PULL HIGH TO VBAT_RTC FOR ICH8M INTRNAL VR ENABLE(PULL LOW DISABLE)

C742 32XCLK0

C0402 R269 Y7 32.768KHz xd3_2X6 3 ASSY

1

D

+V3.3S {6,7,10,12,14,15,16,19,20,21,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51} ICH_EC_RTC {24} EC_RTC {36} +V1.05S {6,7,8,9,12,13,14,24,31,38,40,41,42,44} +V1.5S_PCIE_ICH {23,24} +V3.3AL {12,19,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51} +V1.5S {8,14,24,26,27,28,30,38,40,42}

Voltage Swing on RTCX1 pin should not exceed 1.0V.

332K,1% R0402

D

ICH_INTVRMEN

2

EC_RTC

15pF/50V,NPO

C743 32XCLK1

ICH_EC_RTC

D22

C0402

C235 1uF/10V,X7R C0603

+V3.3S R891

0

U6A 32XCLK1

C23 C24

RTCX1 RTCX2

RTC_RST# SRTC_RST#

A25 F20 C22

RTCRST# SRTCRST# INTRUDER#

B22 A22

INTVRMEN LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14 G13 D14

LAN_RXD0 LAN_RXD1 LAN_RXD2

D13 D12 E13

LAN_TXD0 LAN_TXD1 LAN_TXD2

R0402

4

4

1M R0402

ns

SM_INTRUDER# Delete RTCBat socket for mechanical conflict

ICH_INTVRMEN

If LAN interface is not used, this signal can be left as No Connect.

SPONGE_RTC1 RTCBAT GLUE

R282

0

R0402

ns

+V1.5S_PCIE_ICH RTC_BAT1

+ -

C373 ns

5.6pF/50V,NPO C0402 R438

{30} AZALIA_CODEC_BITCLK

RTCBAT with Cable

33

R487 24.9,1% R0402

R0402

GPIO56 B10

根据机构 定Cable尺寸

R200

{30} AZALIA_CODEC_SYNC

33

R0402

B28 B27 bitclk ACSYNC_D

R442

{30} AZALIA_CODEC_RST# +V3.3AL

33

ns

{12} AZALIA_SDATAIN2

R275 10K R0402

ICTP ns

R189

{30} AZALIA_CODEC_SDOUT

33

RST#

R0402

{30} AZALIA_SDATAIN0

ICTP

T137 T135 AC_SDOUT

R0402

HDA_DOCK_EN# GPIO56

ns ICTP {50}

R687 1K R0402

del

ns

hads 080514

1

B

R686 8.2K R0402

HDA_DOCK_EN#

2

R685 8.2K R0402 ns

+V3.3S

HDCP JOPEN RESISTOR_1 ns

SATA HDD

{25} {25} {25} {25}

SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0

SATA ODD

{25} {25} {25} {25}

SATA_RXN1 SATA_RXP1 SATA_TXN1 SATA_TXP1

C0402 0.01uF/25V,X7R

C0402 C369 C370 0.01uF/25V,X7R C0402 C134 C135 0.01uF/25V,X7R

GLAN_COMPI GLAN_COMPO HDA_BIT_CLK HDA_SYNC

AE7

HDA_RST# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

AG5

HDA_SDOUT

AG7 AE8

HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16 AH16 AF17 AG17

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

AH13 AJ13 AG14 AF14

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

K5 K4 L6 K2

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

FWH4/LFRAME#

K3

LPC_FRAME#

LDRQ0# LDRQ1#/GPIO23

GPIO56

AF4 AG4 AH3 AE5

T136

IDE_LED#

C0402 0.01uF/25V,X7R

AF6 AH4

RTC LPC

3

R262 R0402

32.768KHz XS4_8038

J9 C223 JOPEN 1uF/10V,X7R RESISTOR_1 C0603 ns

LAN / GLAN CPU

3

C430 1uF/10V,X7R C0603

IHDA

R268R0402 20K

R523 10M R0402

1 4

2

1K R0402 RTCBAT1 CONN2_R CNS2_R 1 1 2 2

2 3

1

R261 20K

R309

Y4

CMOS Settings J1 Clear CMOS Short Keep CMOS Open

SATA

BAT54C

32XCLK0

2

+V1.5S

0 ns R0402

VerB:chang the clk of 32.768 to dip

3

C

R293

15pF/50V,NPO

1

{28,31,33} R239 {28,31,33} 10K {28,31,33} R0402 {28,31,33} ns

R242 10K R0402 ns

+V1.05S

{28,31,33}

J3 J1

A20GATE A20M#

N7 AJ27

H_A20GATE H_A20M#

DPRSTP# DPSLP#

AJ25 AE23

R208 R444

FERR#

AJ26 AD22

H_PWRGD

{7}

AF25

H_IGNNE#

{7}

INIT# INTR RCIN#

AE22 AG25 L3

H_INIT# H_INTR H_RCIN#

{7} {7} {33}

NMI SMI#

AF23 AF24

H_NMI H_SMI#

{7} {7}

STPCLK#

AH27 AG26

TP12

R435

0 R0402

H_STPCLK# R216 T67 ICTP

ns

AH11 SATA4_RXN AJ11 SATA4_RXP AG12 AF12

R192

1K

R0402 ns

R191

1K

R0402 ns

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

AH9 SATA5_RXN AJ9 SATA5_RXP AE10 AF10

R194

1K

R0402 ns

R193

1K

R0402 ns

SATA_CLKN SATA_CLKP

AH18 AJ18 AJ7 AH7

H_DPRSTP# H_DPSLP#

{7}

Checklist:the series termination RES of FERR#/IERR#/THERMTRIP are 56/56/55ohm。 +V1.05S R215 56 R0402

{7} 54.9,1%

CLK_ICH_SATA# CLK_ICH_SATA R0402 24.9,1%

C

{7,12,41} {7}

R177 NEEDS BE PLACE WITHIN 2" OF ICH9, R173 NEEDS BE PLACED WITHIN 2" OF R177 WITHOUT STUB PM_THRMTRIP# {7,12,31}

R0402

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATARBIAS# SATARBIAS

R0402

R0402 R0402

H_FERR#

IGNNE#

AG27

0 0

R214 56

R207 56 R0402

CPUPWRGD

THRMTRIP#

R213 R454 56 56 ns ns R0402 R0402

{33} {7}

No stuff for SATA function

{6} {6}

R427 B

within 500 mils of the ICH9-M

ICH9M REV 1.0 Same distance to the ICH Close the ICH as possible

后盖打开就能看到。 +V1.05S

ns

+V1.05S

+V3.3S +V3.3S

C523 C0402

C526 0.01uF/25V,X7R C0402

5.6pF/50V,NPO ns HDMIR0402 R667

C732 0.01uF/25V,X7R C0402

33 bitclk

{12} AZALIA_HDMI_BITCLK {12} AZALIA_HDMI_SYNC

R668 HDMI

R0402 ACSYNC_D

{12} AZALIA_HDMI_SDOUT

缝合电容 BIT_CLK

33 R669 HDMI

{12} AZALIA_HDMI_RST# A

C731 0.01uF/25V,X7R C0402

C737 0.01uF/25V,X7R C0402

R0402 33

R670 HDMI 33

RST# AC_SDOUT

A

R0402

TOPSTAR TECHNOLOGY bent Page Name

Title

Size C

M46G

Project Name

Rev B

Tuesday, September 01, 2009 22 51 of Date: Sheet PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

Close ICH9 as possible

+V3.3AL {12,19,22,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51} +V3.3S {6,7,10,12,14,15,16,19,20,21,22,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51} +V1.5S_PCIE_ICH {22,24} +V5S {19,20,21,24,25,30,31,32,33,38,41,42}

http://shop61976717.taobao.com http://shop61976717.taobao.com +V3.3S

U6D

D3 E3 R1 C6 E4 C2 J4 A4 F5 D7

PLTRST# PCICLK PME#

C14 D4 R2

ICTPns

PCI_IRDY# T74 ICTPns PCI_RST# PCI_DEVSEL# PCI_PERR# PCI_LOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME# PLT_RST# CLK_ICHPCI

PCI_PME#

{6}

GPIO6 SV_SET_UP

R201 R429

10K 10K

GPIO7

R183

10K

PCI_GNT#0

PIRQA# PIRQB# PIRQC# PIRQD#

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

R324 0 ns

R326 0

5 R328 100K

GND

2

{27} {27} {27} {27}

PCIE_RXN4_ICH PCIE_RXP4_ICH PCIE_TXN4_ICH PCIE_TXP4_ICH

PLT_RST#

U9 74AHCT1G08GV SOT23_5

R530

3.3K

WP# 3

R555

3.3K

HOLD# 7

R231 R304

Co-lay VDD HOLD# SCK SI

10K

10K

SMB_ALERT#

R289

10K

CL_RST#1

R303

10K

SMLINK0

R272

10K

SMLINK1

R271

10K

GPIO13

R294

10K

LINKALERT#

R305

10K

PM_SLP_S3#

R273

10K

PM_BATLOW# R505

8.2K

PM_SYSRST#

R306

10K

SMB_CLK

R307

2.2K

SMB_DATA

R515

2.2K

VDD WP#

SI SO CE# SCK

5 2 1 6

SI SO CE# SCK

VSS

4

VSS

HOLD#

GPIO26

R276

10K

10K

ns PANEL_ID1

R512

10K

R278

10K

ns PANEL_ID0

with U28 8 VCC 7 HOLD# 6 CLK 5 D

3

CE# SO WP# VSS

1 2 3 4

SMB_CLK_S

SMB_DATA_S

{6,15,16,26,27,28}

CS# Q W# VSS

SMB_CLK_S

{6,15,16,26,27,28}

1

R513

+V3.3S

GNT0# 0 1 1

SPI_CS1# 1 0 1

10K 10K

{6} PM_STPPCI# {6} PM_STPCPU#

R488

MFG_MODE INT_SERIRQ PM_THRM# BIOS_REC_R

10K 10K

3

ns

R312 10K R0402

100K

1 2

R366

GND

Q19 2N2222 SOT23 ns

{12} {12} {12} {12}

DMI1RXN DMI1RXP DMI1TXN DMI1TXP

Y27 Y26 W29 W28

DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1

{12} {12} {12} {12}

DMI2RXN DMI2RXP DMI2TXN DMI2TXP

AB27 AB26 AA29 AA28

DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2

{12} {12} {12} {12}

DMI3RXN DMI3RXP DMI3TXN DMI3TXP

AD27 AD26 AC29 AC28

DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3

{12} {12} {12} {12}

DMI_CLKN DMI_CLKP

DMI_ZCOMP DMI_IRCOMP

PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP

USBP0N USBP0P USBP1N USBP1P SPI_CLK USBP2N SPI_CS0# USBP2P SPI_CS1#/GPIO58/CLGPIO6 USBP3N USBP3P SPI_MOSI USBP4N SPI_MISO USBP4P USBP5N OC0#/GPIO59 USBP5P OC1#/GPIO40 USBP6N OC2#/GPIO41 USBP6P OC3#/GPIO42 USBP7N OC4#/GPIO43 USBP7P OC5#/GPIO29 USBP8N OC6#/GPIO30 USBP8P OC7#/GPIO31 USBP9N OC8#/GPIO44 USBP9P OC9#/GPIO45 USBP10N OC10#/GPIO46 USBP10P OC11#/GPIO47 USBP11N USBP11P USBRBIAS USBRBIAS#

USB

T26 T25

CLK_PCIE_ICH# {6} CLK_PCIE_ICH {6}

AF29 AF28

DMI_IRCOMP_R R218

AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2

RI#

PM_SYSRST#

SUS_STAT#/LPCPD# SYS_RESET#

SMB_ALERT#

A17

SMBALERT#/GPIO11

A14 E19

STP_PCI# STP_CPU#

M6

0 0

PCIE_WAKE#_RE20 M5 AJ23

ns

EXTSMI#

ns ns

PM_STPPCI#

+V3.3AL

PM_STPCPU# R263 10K ns

+V3.3S

{33}

{19} PANEL_ID0 {19} PANEL_ID1 {6} SATA_CLKREQ#

R441 R202

D21 A20 AG19 AH21 AG21 A21 C12 C21 AE18 K1 AF8 AJ22 A9 D19 L1 AE19 AG22 AF21 AH24 A8

GPIO12 GPIO13 SV_SET_UP ICH_GPIO18 ICH_GPIO20 BIOS_REC_R PANEL_ID0 PANEL_ID1

ns ns

10K 10K MFG_MODE

M7 AJ24 B21 AH20 AJ20 AJ21

{30} AC_SPKR {12} MCH_ICH_SYNC# T78 ns T63 ns T65 ns T64 ns R317

Place within 500 mils of ICH

EXPCARD_USB_PN0 {26} EXPRESS Card EXPCARD_USB_PP0 {26} T164 ns T165 ns USB_PN2 {32} USB0 PORT USB_PP2 {32} MINICARD_USB_PN3 {28} Robson MINICARD_USB_PP3 {28} MINICARD_USB_PN4 {27} Echo Peak MINICARD_USB_PP4 {27} BT_USB_PN5 {31} BLUETOOTH BT_USB_PP5 {31} USB_PN6 {32} USB1 PORT USB_PP6 {32} CAM_USB_PN7 {19} CAMERA CAM_USB_PP7 {19} USB_CR_PN8 {29} USB_CR_PP8 {29} USB_PN9 {32} USB2 PORT USB_PP9 {32} T162 ns VerA:change the port sequence for the T163 ns convenience of layout T70 ns T71 ns

0

WAKE# SERIRQ THRM# VRMPWRGD TP11 GPIO1 GPIO6 GPIO7 GPIO8 GPIO12 GPIO13 GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 GPIO27 GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5 SPKR MCH_SYNC# TP3 TP8 TP9 TP10

ns

ns R205 R431 R434 R452

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37

SUSCLK

P1

T72

ns

SLP_S3# SLP_S4# SLP_S5#

C16 E16 G17

T143

ns

S4_STATE#/GPIO26

C10

GPIO26

PWROK

G20

CLK14 CLK48

PMSYNC#/GPIO0

CLKRUN#

ns

AH23 AF19 AE21 AD20

DPRSLPVR/GPIO16

H1 AF3

BATLOW#

B13

PWRBTN#

R3

LAN_RST# RSMRST#

CLK_ICH14 CLK_USB48

PM_ICH_PWROK

CLPWROK

R6

PM_ICH_PWROK PM_DPRSLPVR

{12}

B

{12,41}

PM_PWRBTN# {33} 0 0

PLT_RST#

ns R520

D22 R5

{26,33,40} {26,33,42}

PM_BATLOW#

R325 R327

D20

CK_PWRGD

{6} {6}

PM_SLP_S3# PM_SLP_S4#

100 PM_DPRSLPVR

R234

M2

10K 10K 10K 10K

R465

0

CLK_PWRGD PM_ICH_PWROK

{12}

+V3.3S

B16

CL_CLK0 CL_CLK1

F24 B19

CL_CLK0 CL_CLK1

{12} {27}

CL_DATA0 CL_DATA1

F22 C19

CL_DATA0 CL_DATA1

{12} {27}

CL_VREF0 CL_VREF1

C25 A19 F21 D18

MEM_LED/GPIO24 GPIO10/SUS_PWR_ACK GPIO14/AC_PRESENT WOL_EN/GPIO9

A16 C18 C11 C20

CL_RST#1 GPIO10 GPIO14

PM_RSMRST# {33,39,40}

C460 1000pF/25V,X7R

SLP_M#

SLP_M#

CL_RST0# CL_RST1#

100

{6}

CL_RST#0 CL_RST#1

R284

R287

3.24K,1%

3.24K,1%

{12} C217 R258 {27} 0.1UF/10V,X7R 453,1%

ICH_EXP_RST# {26} EC_RUNTIME_SCI#

+V3.3S

R288 C221 453,1% 0.1UF/10V,X7R

{33}

ICH9M REV 1.0

A

+V3.3AL 0 R323 20K 5

ns

C236ns

R315 10K

1

4 2 Q11

R321 1K

C237 U7 74AHCT1G08GV 0.1UF/10V,X7R SOT23_5 ns

2N7002E-T1

1 2

{41} CK505_CLK_EN#

5

4

VCC

3

ns

0.1UF/10V,X7R

3

A

The signal is required to be low for desktop applications and high for mobile app.It has a weak internal pull-up(20K)

VR_PWRGD_CK410_INV

GND 3

R322

C

ICH9M REV 1.0

U6C G16 SMBCLK A13 SMBDATA E17 LINKALERT#/GPIO60/CLGPIO4 C17 SMLINK0 B18 SMLINK1

GPIO1 GPIO6 GPIO7 {33}

+V1.5S_PCIE_ICH

24.9,1% R0402

Add for option(SATA interlock switch)

R4 G19

T75

D

R203R430R433R447 10K 10K 10K 10K

F19

R316 0 INT_SERIRQ PM_THRM#

J8 ns JOPEN RESISTOR_1

R264 100K EC_PWROFF#

DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0

+V3.3S

VR_PWRGD_CK410_INV

Note:1.GPIO57 Can be used as TPM Physical Presence pin for iTPM 2.The PM_RSMRST# iTPM function of chipset is disabled default

3

PM_ICH_PWROK

AG2 AG1

V27 V26 U29 U28

VerB:预留一个并联支路以调节偏置电阻大小,同时将R211改为20ohm，以改善眼图

L4

{26,27,28,33,51} PCIE_WAKE# {31,33} INT_SERIRQ

+V3.3AL U8

5 2

{33,41} IMVP_PWRGD

R0603 USB_RBIAS_PN Place within 500 mils of ICH 18.7,1% R0402

Boot BIOS SPI PCI LPC

R281 R489

T73 T134 R280

10K 10K

ns 300

{12} PM_SYNC#

PM_DPRSLPVR

ns

N4 N5 N6 P6 M1 N2 M4 M3 N3 N1 P5 P3

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

ns

PM_RSMRST#

10K

100K

D25 E23 10K

USB_OC#6

SMB_CLK SMB_DATA LINKALERT# SMLINK0 SMLINK1

+V3.3S

C240

D23 D24 F23

USB_OC#2

{32}

1

1

R235

C29 C28 D27 D26

Change OC connecttion By Johan071108

R211

2

74AHCT1G08GV SOT23_5 4

PERN5 PERP5 PETN5 PETP5

15 15 15 15

R463 R460

10K R510 10K R274

R355

VCC

E29 E28 F27 F26 R529 R531 R552 R526

+V3.3AL

+V5S

1

PERN4 PERP4 PETN4 PETP4

10K

R432 10K R480 10K R204 8.2K R199 10K

Q12

0.1UF/25V,Y5V

G29 G28 H27 H26

{31} PM_CLKRUN#

2N7002E-T1

{33,40} Main_PWROK

{32}

ns

+V3.3S

+V5S 3

0.1UF/10V,X7R MiniCard 0.1UF/10V,X7R MiniCard

10K

EC_RUNTIME_SCI# R511 EXTSMI# R270

SMB_DATA_S

SMB_CLK

C189 C192

R459

S25FL008A SOIC8_50_208

ns

2

PERN3 PERP3 PETN3 PETP3

U17

2

SMB_DATA

J29 J28 K27 K26

R277 10K R290

GPIO12 GPIO10 GPIO14

R310 2.2K

ns

0.1UF/10V,X7R 0.1UF/10V,X7R

PM_RI#

Q29 2N7002E-T1

C181 C182

ns T79 nsT79

{19,33} PM_SUS_STAT#

B

PERN2 PERP2 PETN2 PETP2

1K

R507

SLP_M#

R522 2.2K

L29 L28 M27 M26

U16

+V3.3S

The Bus switch prevents Leakage of the SMBus into devices powered on the switched rail.

0.1UF/10V,X7R 3G 0.1UF/10V,X7R 3G

W25X40 ns SO8_50_150

1K

PCIE_WAKE#_R R302

R279 10K

C175 C170

ns

R0402 VDD 8

R892

4

BUF_PLT_RST#

3

{12,19,26,27,28,31,33,51}

PCIE_RXN3_ICH PCIE_RXP3_ICH PCIE_TXN3_ICH PCIE_TXP3_ICH

R551

C239

1

{26} {26} {26} {26}

0

10K

0.1UF/25V,Y5V

VCC

EXPRESS Card

R553

ns

+V3.3AL

PCI_PME#

+V3.3AL

PCIE_RXN2_ICH PCIE_RXP2_ICH PCIE_TXN2_ICH PCIE_TXP2_ICH

+V3.3AL

PM_RI#

+V3.3S

{28} {28} {28} {28}

Echo Peak R554 0 ns

ICH9M REV 1.0

C

Robson

+V3.3AL +V3.3S

ns change to stuff for boot from ICH By Johan 071224

INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#

H4 K6 F2 G2

R497

ns

PERN1 PERP1 PETN1 PETP1

PCI-Express

IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME#

ICTPns

T144

N29 N28 P27 P26

C176 C178

Direct Media Interface

D8 B4 D6 A5

T145

0.1UF/10V,X7R 0.1UF/10V,X7R

{51} PCIE_RXN1_ICH {51} PCIE_RXP1_ICH {51} PCIE_TXN1_ICH {51} PCIE_TXP1_ICH

LAN IC

SPI

C/BE0# C/BE1# C/BE2# C/BE3#

Interrupt I/F

J5 E1 J6 C4

PCI_REQ#0 PCI_GNT#0 PCI_REQ#1 PCI_GNT#1 PCI_REQ#2 PCI_GNT#2 PCI_REQ#3 PCI_GNT#3

F1 G4 B6 A7 F13 F12 E6 F6

SATA GPIO

REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55

ns

SMB

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

PCI

1K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 10K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 10K

Clocks

D

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

R474 R265 R248 R501 R256 R485 R254 R252 R251 R246 R257 R494 R267 R266 R184 R498 R247 R486 R253 R493 R481 R245 R243 R479 R230

SYS GPIO Power MGT

D11 C8 D9 E12 E9 C9 E10 B7 C7 C5 G11 F8 F11 E7 A3 D2 F10 D5 D10 B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3

AC_SPKR PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_SERR# PCI_DEVSEL# PCI_PERR# PCI_LOCK# PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3 PCI_GNT#1 GPIO1 INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH# PM_CLKRUN# PCI_RST#

MISC GPIO Controller Link

U6B

TOPSTAR TECHNOLOGY bent Page Name

Title

Size C

M46G

Project Name

Rev B

Tuesday, September 01, 2009 23 51 Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 2

1

5

4

3

C226

C147 0.1UF/10V,X7R

+V1.5S_PCIE_ICH

646mA

C376 C0805

CT9 C0805

CT10 C0805

C379

FB131

L1

1

C426

Place within 100 mils on the bottom or 140 mil on the top of ICH

2 FB0603

C384 CT7343_19 220UF/2.5V,POSCAP ns

1

0.68uH/150mA

47mA

ns C131 C0805

C132 C0603

C133

10UF/6.3V,X5R 1uF/10V,X7R

0.1UF/10V,X7R

VCC1_5_B[1] VCC1_5_B[2] VCC1_5_B[3] VCC1_5_B[4] VCC1_5_B[5] VCC1_5_B[6] VCC1_5_B[7] VCC1_5_B[8] VCC1_5_B[9] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] VCC1_5_B[47] VCC1_5_B[48] VCC1_5_B[49]

AJ19

VCCSATAPLL

+V1.5S R436

1342mA

0 R0805

C378 C0603

C398 C0603

C396

C365 C0603

+V1.5S R451

0

10mA(VccUSBPLL)

R0603 C394

ns ns 0

R0603 C220

+V1.5S 0 R0603

AC18 AC19

VCC1_5_A[18] VCC1_5_A[19]

AC21

VCC1_5_A[20]

G10 G9

VCC1_5_A[21] VCC1_5_A[22]

AC12 AC13 AC14

VCC1_5_A[23] VCC1_5_A[24] VCC1_5_A[25]

AJ5

VCCUSBPLL

AA7 AB6 AB7 AC6 AC7

VCC1_5_A[26] VCC1_5_A[27] VCC1_5_A[28] VCC1_5_A[29] VCC1_5_A[30]

TP_VCCLAN1.05_ICH_1 A10 TP_VCCLAN1.05_ICH_2 A11

T76 T77

19mA R249

VCC1_5_A[17]

23mA

VCCLAN3_3[1] VCCLAN3_3[2]

A27

VCCGLANPLL

D28 D29 E26 E27

VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4]

A26

VCCGLAN3_3

C210 +V1.5S R250

0 R0603

80mA 0.1UF/10V,X7R C198

R283

A

0 R0603

2

A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18

VCCDMIPLL

R29

VCC_DMI[1] VCC_DMI[2]

W23 Y23

V_CPU_IO[1] V_CPU_IO[2]

AB23 AC23

VCC3_3[1]

AG29

VCC3_3[2]

AJ6

VCC3_3[7]

AC10

VCC3_3[3] VCC3_3[4] VCC3_3[5] VCC3_3[6]

AD19 AF20 AG24 AC20

VCC3_3[8] VCC3_3[9] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] VCC3_3[14]

FB16 1 2 FB0603 120ohm@100MHz,500mA C167

23mA

1 Place within 100 mils on the bottom or 140 mil on the top of ICH

C165 C0805 0.01uF/16V,X7R +V1.05S 10UF/6.3V,X5R

48mA C405

The voltage of VCC_DMI change from 1.25V to 1.05V

CT7 C0805 10UF/6.3V,X5R

0.01uF/16V,X7R +V1.05S

2mA C402

R4570 R0603 C408 C0805

C395

0.1UF/10V,X7R 4.7UF/10V,Y5V 0.1UF/10V,X7R

308mA Close to AF29

+V3.3S

C380

+V1.5S +V3.3S_1.5S_HDA

Close to AD2

R4430 R0603

C374

C377

0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R

B9 F9 G3 G6 J2 J7 K7

VCCHDA

AJ4

VCCSUSHDA

AJ3

VCCSUS1_05[1] VCCSUS1_05[2]

AC8 F17

VCCSUS1_5[1]

AD8

VCCSUS1_5[2]

F18

VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4]

A18 D16 D17 E22

VCCSUS3_3[5]

AF1

VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20]

T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7

Place within 100 mils on the bottom or 140 mil on the top of ICH C438

R672 R508 C435

C450

0

0 R0603 +V3.3S_1.5S_HDA

0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R

11mA

+V3.3A_1.5A_HDA

+V1.5AL

C136 +V3.3A_1.5A_HDA 0.1UF/10V,X7R

11mA TP_VCCSUS1_05_ICH1 T138 TP_VCCSUS1_05_ICH2 T142

ns ns

C145 0.1UF/10V,X7R

TP_VCCSUS1_5_ICH

212mA C436

R671

0

+V3.3AL R4990 R0603

C439

0.1UF/10V,X7R 0.1UF/10V,X7R

C407 C0805

0.1UF/10V,X7R

0.1UF/10V,X7R TP_VCCSUS1_5_ICH

R688

0

+V3.3A_1.5A_HDA

ns

G22 TP_VCCCL1_05_ICH

VCCCL1_5

G23 VCCCL1_5_INT_ICH A24 B24

R4580 R0603 C415

C413

4.7UF/10V,Y5V

VCCCL1_05

VCCCL3_3[1] VCCCL3_3[2]

U6E +V1.5S R223 R0603

R509

+V3.3S 0 R0603

C451 0.1UF/10V,X7R ns

C433

C432 C0603

0.1UF/10V,X7R 1uF/10V,X7R ns ns

C431 C0603 1uF/10V,X7R ns

AA26 AA27 AA3 AA6 AB1 AA23 AB28 AB29 AB4 AB5 AC17 AC26 AC27 AC3 AD1 AD10 AD12 AD13 AD14 AD17 AD18 AD21 AD28 AD29 AD4 AD5 AD6 AD7 AD9 AE12 AE13 AE14 AE16 AE17 AE2 AE20 AE24 AE3 AE4 AE6 AE9 AF13 AF16 AF18 AF22 AH26 AF26 AF27 AF5 AF7 AF9 AG13 AG16 AG18 AG20 AG23 AG3 AG6 AG9 AH12 AH14 AH17 AH19 AH2 AH22 AH25 AH28 AH5 AH8 AJ12 AJ14 AJ17 AJ8 B11 B14 B17 B2 B20 B23 B5 B8 C26 C27 E11 E14 E18 E2 E21 E24 E5 E8 F16 F28 F29 G12 G14 G18 G21 G24 G26 G27 G8 H2 H23 H28 H29

VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106]

VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198]

H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25

VSS_NCTF[1] VSS_NCTF[2] VSS_NCTF[3] VSS_NCTF[4] VSS_NCTF[5] VSS_NCTF[6] VSS_NCTF[7] VSS_NCTF[8] VSS_NCTF[9] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]

A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29

D

C

B

ICH9M REV 1.0

ICH9M REV 1.0

1uF/10V,X7R C0603 ns

+V3.3S

VCCLAN1_05[1] VCCLAN1_05[2]

A12 B12

VCC1_05[1] VCC1_05[2] VCC1_05[3] VCC1_05[4] VCC1_05[5] VCC1_05[6] VCC1_05[7] VCC1_05[8] VCC1_05[9] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26]

GLAN POWER

0.1UF/10V,X7R

USB CORE

R301

AC9

C393

0.1UF/10V,X7R 0.1UF/10V,X7R

+V3.3S

VCC1_5_A[9] VCC1_5_A[10] VCC1_5_A[11] VCC1_5_A[12] VCC1_5_A[13] VCC1_5_A[14] VCC1_5_A[15] VCC1_5_A[16]

C397

0.1UF/10V,X7R 0.1UF/10V,X7R 1uF/10V,X7R 1uF/10V,X7R

B

AC11 AD11 AE11 AF11 AG10 AG11 AH10 AJ10

ATX

+V1.5S

VCC1_5_A[1] VCC1_5_A[2] VCC1_5_A[3] VCC1_5_A[4] VCC1_5_A[5] VCC1_5_A[6] VCC1_5_A[7] VCC1_5_A[8]

ARX

C372 C0603

1uF/10V,X7R 1uF/10V,X7R

AC16 AD15 AD16 AE15 AF15 AG15 AH15 AJ15

VCCA3GP

1 2

C428

10UF/6.3V,X5R 10UF/6.3V,X5R 0.22UF/10V,X7R 0.1UF/10V,X7R 10UF/6.3V,X5R 10UF/6.3V,X5R 0.1UF/10V,X7R 0.1UF/10V,X7R

120ohm@100MHz,500mA

+

C416 C0603

AA24 AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE25 AE26 AE27 AE28 AE29 F25 G25 H24 H25 J24 J25 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T24 T27 T28 T29 U24 U25 V24 V25 U23 W24 W25 K23 Y24 Y25

CORE

C149 1uF/10V,X7R C0603 ns

0 R0805

+V1.5S

V5REF_SUS

VCCP_CORE

2

1N4148WS SOD323

+V1.5S

C

V5REF

PCI

Layout note: 0.1uF needs be placed within 100mils of pin G4 of ICH8M

Place above cap with 100milof ICH on the bottom or 140 mil on the top near D28 T28 AD28

VCCRTC

VCCPSUS

R224 10 R0402

C429 C0805

A6

1 D17

300 OHM@100MHz BEAD IN INTEL DEMO CIRCUIT

U6F A23

AE1

C219 0.1UF/10V,X7R

1uF/10V,X7R C0603 ns

FB31

C424 C423 CT8 C410 C421 C414 C427 CT11 ns C0603 C0805 C0805 C0805 C0805 C0805 + CT7343_19 0.1UF/10V,X7R 10UF/6.3V,X5R10UF/6.3V,X5R 10UF/6.3V,X5R 1uF/10V,X7R 220UF/2.5V,POSCAP 10UF/6.3V,X5R 10UF/6.3V,X5R

VCCPUSB

2

2mA

2mA

+V5AL

C222

1634mA

+V5S {19,20,21,23,25,30,31,32,33,38,41,42} +V5AL {19,29,32,36,37,39,40,42} +V3.3AL {12,19,22,23,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51} +V3.3S {6,7,10,12,14,15,16,19,20,21,22,23,25,26,27,28,29,30,31,33,38,40,41,42,50,51} +V1.5S_PCIE_ICH {22,23} ICH_EC_RTC {22} +V1.5S {8,14,22,26,27,28,30,38,40,42} +V1.05S {6,7,8,9,12,13,14,22,31,38,40,41,42,44} +V1.5AL {39}

1

0.1UF/10V,X7R 0.1UF/10V,X7R

+V3.3AL D

hads

+V1.05S

1

1

C224 D21

Layout note: 0.1uF needs be placed 1N4148WS SOD323 within 100mils of ICH8M PIN A16

VerB nS CT8 C410 080510

Layout note:Distribute near pin ICH9 Package edge

+V3.3S

R285 10 R0402

1

http://shop61976717.taobao.com http://shop61976717.taobao.com

ICH_EC_RTC +V5S

2

1mA

A

TOPSTAR TECHNOLOGY bent Page Name

ICH9M(3 of 3)

Size C

M46G

Project Name

Rev B

Date: Sheet Tuesday, September 01, 2009 24 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com +V5S +V3.3S

{19,20,21,23,24,30,31,32,33,38,41,42} {6,7,10,12,14,15,16,19,20,21,22,23,24,26,27,28,29,30,31,33,38,40,41,42,50,51}

D

D

SATAHDD_B1

SATAHDD_B2

+V3.3S FB20

0

R0805 ns CT2

V3.3_SATA 4.7uF/10V,Y5V C0805 ns

C250 0.1UF/25V,Y5V ns

C249 0.1UF/25V,Y5V ns

Screw 2*5mm ASSY

+V5S

Screw 2*5mm ASSY

Average 1A,Peak 1.5A FB19

0 R0805 CT1

V_HDD 4.7uF/10V,Y5V C0805

C247 0.1UF/25V,Y5V

C246 0.1UF/25V,Y5V

Close to connector as possible the same distance to connector

{22} {22} {22} V3.3_SATA {22}

SATA_TXP0 SATA_TXN0 SATA_RXN0 SATA_RXP0

C263 C264

V_HDD

+V5S FB32

0

Average 1A,Peak 1.5A

R0805 CT12

4.7uF/10V,Y5V C0805

C452 0.1UF/25V,Y5V

V_ODD C453 0.1UF/25V,Y5V

2 0.01uF/25V,X7R 3 C0402 5 C0402 6 0.01uF/25V,X7R 8 9 10

SATA_HDD1 TX TX# RX# RX

GND0 GND1 GND2

1 4 7

VCC3_0 VCC3_1 VCC3_2

GND3 GND4 GND5

11 12 13

14 15 16 18

VCC5_0 VCC5_1 VCC5_2 REEVE

GND6

17

GND7

19

20 21 22

VCC12_0 VCC12_1 VCC12_2

GND23 GND24

23 24

SATA_HDD CONN SATA_D_50B

C

C

SATA_CON1

{22} SATA_TXP1 {22} SATA_TXN1 {22} SATA_RXN1 {22} SATA_RXP1

C467 C464

S1 S2 S3 S4 0.01uF/25V,X7R S5 0.01uF/25V,X7R S6 S7

GND1 A+ A- GND6 GND2 BB+ GND3

P1 P2 P3 P4 P5 P6

DP +5V_1 +5V_2 MD GND7 GND4 GND5

14

VerB:del the screws of SATA_CON1

V_ODD

B

15 B

SATA_ODD CONN SATA_S_50G VerB:change the footprint the same as S46P

A

A

TOPSTAR TECHNOLOGY bent Page Name

SATA HDD&ODD

Size C

M46G

Project Name

Rev B

Date: Sheet Thursday, August 27, 2009 25 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

+V3.3S

4

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com +V3.3S +V1.5S +V3.3AL

+V1.5S

{6,7,10,12,14,15,16,19,20,21,22,23,24,25,27,28,29,30,31,33,38,40,41,42,50,51} {8,14,22,24,27,28,30,38,40,42} {12,19,22,23,24,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51} EP_MYLAR1

U15 R5538 QFNS20_0D5_0D85G

C420 0.1uF/10V,X5R

C434 0.1uF/10V,X5R

12 14 2 4

+V3.3AL

D

17 C425

PM_SLP_S3#

1

0.1uF/10V,X5RPM_SLP_S4# SYS_RST# RCLKEN

add power

1.5Vin1 1.5Vin2

EXP_AUX_3.3V

3.3Vauxout

15

3.3Vauxin

1.5Vout1 1.5Vout2

11 13

STBY#

PERST#

8

EXP_RST#

CPPE#

10

EXP_CPPE#

CPUSB# GND2 GND3 GND1

9 G1 G2 7

CP_USB#

3.3Vin1 3.3Vin2

20

SHDN#

6 16 18 19

SYSRST# NC RCLKEN OC#

PVC

EXP_3.3V

3 5

3.3Vout1 3.3Vout2

Change mylar type follow ME advised By Johan 071228

ASSY D

EXP_1.5V EP_CON1 Shield ASSY 621000000002

{12,19,23,27,28,31,33,51}

sw

BUF_PLT_RST#

{23} ICH_EXP_RST#

R476

0

R484

0 ns

SYS_RST#

EP_B1

PM_SLP_S3# PM_SLP_S4#

{23,33,40} PM_SLP_S3# {23,33,42} PM_SLP_S4#

ASSY

EP_B2

ASSY

Screw 2*5mm

Screw 2*5mm

C

C

2

+V3.3AL

PM_SLP_S4# ns

D34 BAT54S SOT23 J7

PETp0

{23} PCIE_TXN3_ICH

24

PETn0

{23} PCIE_RXP3_ICH

22

PERp0

{23} PCIE_RXN3_ICH

21

PERn0

19

REFCLK+

{6} CLK_PCIE_EXPCARD

18

{6} CLK_PCIE_EXPCARD# EXP_CPPE# EXP_RST#

SMB_CLK_S

D20

CPPE#

13

PERST#

RESV2

5

+3.3VS_2

15

+3.3VS_1

14

GND0

26

+3.3VAUX

12

SMB_DATA

7

SMB_CLK

4

CPUSB#

3

USB_D+

EXP_3.3V

+V1.5S 650mA MAX R240 R0805 ns 0

EXP_1.5V

EXPCARD_CLKREQ# {6}

change to power sw

RCLKEN B

C209

EXP_AUX_3.3V

23

+1.5V_1 +1.5V_2

10 9

GND2

20

C180

GND3

1

GND4 GND5

27 28

0.1uF/10V,X5R C177 10UF/10V,Y5V C1206 ns

EXP_1.5V

+V3.3AL

C196 10UF/10V,Y5V C1206 ns

GND1

G2

R255 R0805 ns 0

+V3.3AL 275mA MAX R244 R0805 ns 0 EXP_AUX_3.3V

C208 10UF/10V,Y5V C1206 ns

0.1uF/10V,X5R

USB_D-

+V3.3S1300mA MAX

ns EXP_3.3V

C190

WAKE#

G1

EGA1-0603-V05 EGA1-0603-V05 ESDPAD_R0603 ESDPAD_R0603 ns ns

EXP_CARD_CLKREQ#

0.1uF/10V,X5R

8

2

6

ns

R471 R466 100K 100K

R470 100K ns

CP_USB# EXP_CPPE# EXP_CARD_CLKREQ#

Chang the CAP type from X7R to X5R

PECA00-000LBS4Z4N0 NEW_CARD3

G2

D19

1

CP_USB#

2

{23} EXPCARD_USB_PP0 {23} EXPCARD_USB_PN0

R229 0 R0402 L4_0805 CHK3 2 1 3 4 ns 90ohm@100MHz,0.5A R228 0 R0402

RESV1

2

{6,15,16,23,27,28}

SMB_DATA_S

1

{6,15,16,23,27,28}

16

REFCLK-

17

11

{23,27,28,33,51} PCIE_WAKE#

CLKREQ#

0

Q27 2N7002E-T1-E3 SOT23 2 3

ns

3 25

G1

B

{23} PCIE_TXP3_ICH

R482

1

R483 100K

1

+V3.3AL

A

A

TOPSTAR TECHNOLOGY bent Page Name

EXPRESS CARD

Size A3

M46G

Project Name

Rev B

Date: Thursday, August 27, 2009 Sheet 26 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com H12 2*6mm

+DATA3 -DATA3

+V3.3S +V1.5S +V3.3AL +VDC

{6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,28,29,30,31,33,38,40,41,42,50,51} {8,14,22,24,26,28,30,38,40,42} {12,19,22,23,24,26,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51} {19,28,32,34,36,37,38,41,42,44}

1

D30 ESDPAD_R0603 EGA1-0603-V05

1

MiniCard D29 ESDPAD_R0603 EGA1-0603-V05

+V3.3S

+V3.3AL

+V3.3AL +V3.3S

ns

CHK5 3 2

{23} MINICARD_USB_PN4 {23} MINICARD_USB_PP4

R0402 MiniCard R0402 MiniCard

ns 4 1

-DATA3 +DATA3

{6} CLK_PCIE_MINICARD# {6} CLK_PCIE_MINICARD {23} PCIE_TXN4_ICH {23} PCIE_TXP4_ICH

Delete in series 0ohm RES By Johan 0711081231

ns T100 nsT100 +V3.3AL

ns T99 nsT99 R404 0 MiniCard

{23} {23} {23}

11 13

REFCLKREFCLK+

31 33

PETN0 PETP0

23 25

{23} PCIE_RXN4_ICH {23} PCIE_RXP4_ICH

CL_CLK1 CL_DATA1 CL_RST#1

R405 R406 R407

0 0 0

17 19

R403 0 MiniCard37 39 41 43 ns 45 ns 47 ns 49 51

PERN0 PERP0 RESERVED0 RESERVED1 RESERVED_PCIE0 RESERVED_PCIE1 RESERVED_PCIE2 RESERVED_PCIE3 RESERVED_PCIE4 RESERVED_PCIE5 RESERVED_PCIE6 RESERVED_PCIE7

48 28 6

24

USB_DUSB_D+

L4_0805 90ohm@100MHz,0.5A

C

B

36 38

R390 10K ns

与mini PCI不同，此处为低有效 注意修改LED等处的电路

+1.5V0 +1.5V1 +1.5V2

+3.3V0 +3.3V1

R386 0 R387 0

2 52

Keep USB2.0 Signal stub short

+V3.3AL

+V1.5S R394 0 R0603 MiniCard

R393 0 R0603 MiniCard

+3.3VAUX

R392 0 R0603 ns 3V3PCIE1

PCIE mini Card

2

D

ns

2

D

R397 10K ns

minicard_CLKREQ# minicard_Wake#

LED_WPAN# LED_WLAN# LED_WWAN#

46 44 42

PERST# WAKE# CLKREQ#

22 1 7

T88

ns

T89

ns

Wireless_LED# {50} C

SMB_DATA SMB_CLK

32 30

BUF_PLT_RST# {12,19,23,26,28,31,33,51} PCIE_WAKE# {23,26,28,33,51}

minicard_Wake# R396 0 ns minicard_CLKREQ# Don't

use minipcie clock request function.

R389 0 R388 0

ns ns

SMB_DATA_S {6,15,16,23,26,28} SMB_CLK_S {6,15,16,23,26,28} 确定此处smbus的作用?

CHANNEL_CLK CHANNEL_DATA

R541 0 ns R542 0 ns

5 3

RESERVED_DISABLE

20

R395 0

RESERVED_SIM0 RESERVED_SIM1 RESERVED_SIM2 RESERVED_SIM3 RESERVED_SIM4

16 14 12 10 8

ns ns ns ns ns

CH_CLK CH_DATA

MiniCard

{28,31} {28,31}

HW_RATIO_OFF#

T91 T93 T92 T94 T90

{33}

R383 R490 10K 10K ns MINICARD B

+V3.3AL

GND14 GND15 GND16 GND17 GND18 GND19 GND20

3V3PCIE1 C528 0.1UF/25V,Y5V C0402

55 56 57 58 59 60 61

9 15 21 27 29 35 4 18 26 34 40 50 53 54

GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13

+V3.3S +V3.3AL

MPCIE1 MINIPCIE_L6 PCIE CARD MiniCard

MiniCard

C529 0.1UF/25V,Y5V C0402

MiniCard

C298 10UF/6.3V,X5R C0805

MiniCard

C308 0.1UF/25V,Y5V C0402

C301 10UF/6.3V,X5R C0805

MiniCard

MiniCard

C296 0.1UF/25V,Y5V C0402

MiniCard

VerC: change the footprint of wifi,add some GND hole to the position hole--xiezx +V1.5S

TOPSTAR TECHNOLOGY bent

A

Page Name C304 C303 10UF/6.3V,X5R 0.1UF/25V,Y5V C0805 MiniCard MiniCard

5

C307 0.1UF/25V,Y5V MiniCard

C306 0.1UF/25V,Y5V MiniCard

Size B

C309 0.1UF/25V,Y5V

Rev B

M46G

Date: Sheet of Thursday, August 27, 2009 27 51 PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

MiniCard

4

Project Name

A

PCIE MINI SLOT 1

3

2

1

+V3.3S +V1.5S +V3.3AL +VDC

{6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,29,30,31,33,38,40,41,42,50,51} {8,14,22,24,26,27,30,38,40,42} {12,19,22,23,24,26,27,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51} {19,32,34,36,37,38,41,42,44}

http://shop61976717.taobao.com http://shop61976717.taobao.com H17

3G Hole+Dowel

注意3G卡功耗比较大

+DATA8 +V3.3AL

1

D36 EGA10603V05A1-B

D35 EGA10603V05A1-B

ESDPAD_R0603 ns

R500 0 R0603 ns

ESDPAD_R0603 ns 2

+V3.3AL

Hole+Dowel R506 0 R0603 3G

2

R504 0 R0603 3G

TH_200_132_118 +V1.5S

1

1

PCIE_NUT3

+V3.3S

-DATA8

ns

48 28 6

PETN0 PETP0

{23} PCIE_RXN2_ICH {23} PCIE_RXP2_ICH

23 25

PERN0 PERP0

17 19

RESERVED0 RESERVED1

37 39 41 43 45 47 49 51

RESERVED_PCIE0 RESERVED_PCIE1 RESERVED_PCIE2 RESERVED_PCIE3 RESERVED_PCIE4 RESERVED_PCIE5 RESERVED_PCIE6 RESERVED_PCIE7

R533

ICTP ICTP

T150 T146

R532 0 3G R0603

0 3G

R0603 +V3.3S

+V3.3AL

A1 A2 A17

+V3.3AL +V3.3S +VDC

C271 0.1UF/25V,Y5V {12,19,23,26,27,31,33,51} BUF_PLT_RST# 3G {6} CLK_DEBUGPCI {22,31,33} LPC_FRAME#

A3 A9 A12

PCIRST# PCICLK LFRAME#

{22,31,33} LPC_AD0 {22,31,33} LPC_AD1 {22,31,33} LPC_AD2 {22,31,33} LPC_AD3

A5 A6 A8 A10

LAD0 LAD1 LAD2 LAD3

3G PCIE

SMB_DATA SMB_CLK

32 30

ns ns

T147

ns

VerB:the SW1 controll the 3G_LED

WAKE# R538 MiniPCIE_REQ# R382 R381

0 0

20

RESERVED_SIM0 RESERVED_SIM1 RESERVED_SIM2 RESERVED_SIM3 RESERVED_SIM4

16 14 12 10 8

R503 R693

3G 0

BUF_PLT_RST# {12,19,23,26,27,31,33,51} PCIE_WAKE# {23,26,27,33,51}

ns

ns ns

R537 R543

5 3

RESERVED_DISABLE

0

MiniPCIE_REQ#

WAKE#

SMB_DATA_S {6,15,16,23,26,27} SMB_CLK_S {6,15,16,23,26,27}

0 ns 0 ns

CH_CLK {27,31} CH_DATA {27,31}

0 3G

HW_RATIO_OFF_3G#

SIM_VPP SIM_REST SIM_CLK SIM_DATA SIM_PWR

R491 10K ns

{33}

R492 10K 3G

+V3.3S +V3.3AL REFRESH_EN#

A15

PWR_SW_VCC PWRSW#

A18 A19

DEBG_URXD DEBG_UTXD

A13 A14

NC

A20

GND14 GND15 GND16 GND17

A4 A7 A11 A16

EC_DEBG_Enable

{33}

PWR_SW_VCC2

{32,33,36} SIM_PWR

EC_DEBG_URXD {33} EC_DEBG_UTXD {33}

D47 ESDPAD_R0603 EGA1-0603-V05 ns

R694 R0402

C533 0.1UF/25V,Y5V C0402

SIM_CLK

C531 0.1UF/25V,Y5V C0402

D49

C536 0.1UF/25V,Y5V C0402 D50 ns

ns

3G

3G

3G

ns

ns

+V3.3AL

3G

5

0

C445 10UF/6.3V,X5R C0805 3G

C443 0.1UF/25V,Y5V C0402

VCC1 RESET CLK

C5 C6 C7

GND VPP IO

HOLE0 HOLE1

G1 G2

CD SIMCARD SIMCARD_3 PCIE2

Add SIM card Swain 081111

VerC:change the SIMCARD the same as XO1--xiezx ns SIM card periphery current 许沐锌 081222

3G

5

4 4 1 3 2

R869

C1 C2 C3

CD

R695 56 R0402 ns

3G_OFF# 3GVDD_ON

SIM_VPP SIM_DATA C537 47pF/50V,NPO C0402 D51 ns 2

2 {33}

D48 ns

1

1

C530 0.1UF/25V,Y5V C0402

1

C468 0.1UF/25V,Y5V C0402

+V3.3AL

VerB:the SW1 controll the 3G_LED

C535 100pF/50V,NPO C0402

SIMCARD SIM_PWR SIM_REST

R867 10K R0402 3G

SIM_DATA

8.2K

C534 1uF/10V,X7R C0603

3V3PCIE C437 10UF/6.3V,X5R C0805

2

+VDC

22 1 7

CHANNEL_CLK CHANNEL_DATA

9 15 21 27 29 35 4 18 26 34 40 50 53 54

ns ns

+V3.3AL

PERST# WAKE# CLKREQ#

T148 T166

1

31 33

46 44 42

2

{23} PCIE_TXN2_ICH {23} PCIE_TXP2_ICH

PCIE mini Card

REFCLKREFCLK+

GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13

11 13

LED_WPAN# LED_WLAN# LED_WWAN#

R539 10K ns

1

USB_DUSB_D+

ns {6} CLK_PCIE_3G# {6} CLK_PCIE_3G

VerC: add a hole for position stud of 3G connector--xiezx

2

-DATA8 36 +DATA8 38

R540 10K ns

Hole

{23} MINICARD_USB_PN3 {23} MINICARD_USB_PP3

+V3.3AL

55

CHK6 90ohm@100MHz,0.5A L4_0805 3 4 2 1

+V3.3S

+1.5V0 +1.5V1 +1.5V2

3G 3G

+3.3VAUX

0 0

+3.3V0 +3.3V1

R495 R496

2 52

Keep USB2.0 Signal stub short

24

3V3PCIE MPCIE2 MINIPCIE_DEBUG_R

1

1 3 2

3G_SW1 LSS-12M-V-B SW_W_S7A

2

7

+V1.5S

7

6

6

3 Assy

VerC: connect the 3G_OFF# to EC to control the 3G_LED and the HW_RATIO_OFF for 3G--xiezx C441 10UF/6.3V,X5R C0805 3G

C447 0.1UF/25V,Y5V C0402 3G

C446 0.1UF/25V,Y5V C0402 3G

C442 0.1UF/25V,Y5V C0402 3G

C440 0.1UF/25V,Y5V C0402

3G

TOPSTAR TECHNOLOGY bent Page Name

Robson

Size C

M46G

Project Name

Rev B

Thursday, August 27, 2009 28 51 Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

5

4

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com

D3.3V

REG18V

All of by-pass capacitors must be closed to IC

D3.3V REG18V REG3.3V

VDD18

+V3.3S +V3.3AL

{6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,30,31,33,38,40,41,42,50,51} {12,19,22,23,24,26,27,28,31,32,33,34,35,36,37,38,39,40,41,42,50,51}

+V5AL

{19,24,32,36,37,39,40,42}

D3.3V

REG3.3V R733 30K R0402

DGND REG3.3V

REG18V

C588 0.1UF/25V,Y5V C0402

DGND

D

REG33Vin REG18Vout SM/SD/MS D7 GPIO6 SM/SD/MS D6 GPIO5 TC SM/SD/MS D5 GPIO1 GPIO4 VSS REG33Vout

36 35 34 33 32 31 30 29 28 27 26 25

C592 4.7uF/10V,X5R C0805

GPIO7 Clk12M_out SM_CE/SD_WP SM_WP/SD_CLK/MS_CLK VSS SM_WR EE_SDA SD/MS/xD EE_CLK AVDD33 DP DM AVSS

REG5Vin GPIO0/LED SM/SD/MS D4 RST GPIO3 ClkSel SM/SD/MS D3 SM_CD SM_ALE PWR_SW VDD33 VSS

IT1337E-48

SM_D2 VDD18

XTALI

IT1337E-48 QFPS48_0D5_1D6

CLK_CR_48M SM_WPSW SM_RD SM_RNB SM_D0 SM_D1

{23} USB_CR_PP8 {23} USB_CR_PN8

R196 R0603

0

C591 0.1UF/25V,Y5V C0402

+V3.3AL

R195 R0603

XTALO XTALI xD_CD Clk48M SM_WP_SW/SD_CMD/MS_BS SM_RD/MS_INS SM_RNB/SD_CD SM/SD/MS D0 SM/SD/MS D1 SM_CLE SM/SD/MS D2 VDD18

C

0

IT1337E-48 PIN MUX

ns

C589 2.2uF/10V,X7R C0805

C593 2.2uF/10V,X7R C0805

24 23 22 21 20 19 18 17 16 15 14 13

RST ClkSel SM_D3

0 +V5AL ns M46G VerB:Change this power rail to +V3.3AL followed latest IT1337E Demo,PWR_SW2 Reserve +V5AL power rail 090703

C594 0.1UF/25V,Y5V C0402

PWR_SW2 C595 1uF/10V,X7R C0603

PWR_SW2

D3.3V

DGND

C596 0.1UF/25V,Y5V C0402

SM_WP

R736 0

R0402

PINs 05

SM/xD SM_WPSW

06

SM_RD

07

SM_RNB

SD/MMC SD_CMD

D

MS MS_BS MS_INS

SD_CD

08

SM_D0

SD_D0

MS_D0

09

SM_D1

SD_D1

MS_D1

11

SM_D2

SD_D2

MS_D2

18

SM_D3

SD_D3

MS_D3

22

SM_D4

SD_D4

MS_D4

29

SM_D5

SD_D5

MS_D5

32

SM_D6

SD_D6

MS_D6

34

SM_D7

SD_D7

MS_D7

39

SM_CE

SD_WP

40

SM_WP

SD_CLK

C

MS_CLK

SD_CLK

+V3.3S

1 2 3 4 5 6 7 8 9 10 11 12

D3.3V

R197 R0603

REG3.3V

R0402

R0402

C590 4.7uF/10V,X5R C0805

RST

U30

37 Clk12M-out 38 SM_CE 39 SM_WP 40 DGND 41 42 EE_SDA 43 EE_SCL 44 D3.3V 45 46 47 DGND 48

R734 0 R735 0

3IN1 CONN

C733 0.01uF/25V,X7R C0402

VDD18

use 48Mhz crystal　 ClkSel

R737

J13A

0 R0402

B

CLK_CR_48M {6}

SM_D2 SM_D3 SM_WPSW

2 3 4

DAT2_SD DAT3_SD CMD_SD

SD_CLK

7

CLK_SD

SM_D0 SM_D1 SM_RNB SM_CE

9 10 1 11

use 12Mhz crystal　

D3.3V

DAT0_SD DAT1_SD CD_SD# WP_SD#

PWR_SW2 VDD_SD

CARD_3V3

6

C598 1uF/10V,X7R C597 C0603 0.1uF/10V,X7R

SD+MMC VSS_SD2

8

VSS_SD1

5

VCC_MS

13

B

3IN1 PWR_SW2

R738

EEprom Setting

C599 0.1UF/25V,Y5V C0402 ns

U31 1 2 3 4

A0 A1 A2 VSS

VCC WP SCL SDA

8 7 6 5

J13B

XTALI

VerB:cancel the obligating of 12Mhz crystal by xie

EE_SCL EE_SDA

S-24CS02AFJ-TB-G SO8_50_150 ns

0 Clk12M-out Int-12MHz R0402

R740 0 R0402

R741 0 R0402 ns

SD_CLK

14

CLK_MS

SM_D3 SM_RD SM_D2 SM_D0 SM_D1 SM_WPSW

15 16 17 18 19 20

DAT3_MS INS_MS DTA2_MS DTA0_MS DTA1_MS BS_MS

CARD_3V3

MS VSS_MS1 VSS_MS2 GND1 GND2

C601 1uF/10V,X7R C600 0.1uF/10V,X7RC0603

12 21 22 23

3IN1

S0=P12=EEP_SDA S1=P13=EEP_SCK TOPSTAR TECHNOLOGY

A

A

Robin Page Name Size Project Name Custom

Cardreader(ITE1337) Rev A

S46

Thursday, August 27, 2009 29 51 of Date: Sheet PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

2

2

GPIO0

ns

A_GPIO1

3

GPIO1

T68 ICTP

FRONT-OUT-L

35

FRONT-OUT-R

36

LINE1-VREFO-R

37

D

11

{22} AZALIA_CODEC_RST#

6

{22} AZALIA_CODEC_BITCLK

{22} AZALIA_CODEC_SDOUT R210

{22} AZALIA_SDATAIN0

R0402

1uF/10V,X7R

R221 4.7K

C143 100pF/50V,NPO

R220 4.7K

All of JD resistors should be placed as close as possible to the sense pin of codec.

R440

5.11K,1% R0402 ns

JACK_DET_A

R188

5.11K,1% R0402

HP_DET

R187

20K,1%

MIC1_JD

JACK_DET_B

R573

ns

13

JD1

14

LINE2-L

15

LINE2-R

LINE2-VREFO

31

MIC1-VREFO-R

32

DCVOL

33

ALC662

JD2

34

CEN-OUT

43

LFE-OUT

44 45

R416

75

R0402 C367

4.7uF/10V,X5R

C0805 16

MIC2-L

SIDESURR-OUT-L

MIC2_R

R415

75

R0402 C364

4.7uF/10V,X5R

C0805 17

MIC2-R

SIDESURR-OUT-R

46

SPDIFI/EAPD

47

SPDIFO

48

SURR-OUT-L

39

ICTPT131

ns

ICTPT132

ns C129 C128

JACK_DET_B

PC-BEEP

1uF/10V,Y5V C0603 1uF/10V,Y5V C0603

VerA:follow the DEMO design in MIC1&MIC2 071108

18

CD-L

20

CD-R

21

MIC1-L

22

MIC1-R

23

LINE1-L

24

LINE1-R

20K,1% QFPS48_0D5_1D6

C0805 10UF/6.3V,X5R 4.7K R0402

VREFOUT R206

MIC2_L

INT_MIC_L

C

30

AGND1 AGND2

75K

29

MIC2-VREFO

JDREF

40

SURR-OUT-R

41

R209 10K ns

FB14 1

SURR_OUT_R

FB10 1

C116 0.1uF/10V,X7R

GND_AUD

GND_AUD

GND_AUD

INT_MIC_L_R D16

1N4148WS 2 SOD323 D12 1N4148WS 1 2 SOD323

VCC5CDC

R D

AZALIAJACK AUDIO8B

1

1 2

used for enhancing Audio quality and ESD ability.

MIC2_REF 1

GND_AUD

R212 4.7K R0402

D42 ESDPAD_R0603 EGA1-0603-V05 ns

MIC2_L

FB15 1

MIC2_R

FB12 1

2300ohm@100MHz,1.5A FB0805 2300ohm@100MHz,1.5A FB0805

R0402 SHUTDOWN#

0

L

GND_AUD

INPUT:HEADPHONE/LINE-OUT OUTPUT:FRONT L/R 4.7K R0402 ns

1 4 2 5 6 3 7 8

GND_AUD

Headphone Jack

R182 4.7K R0402

GND_AUD

Solve audio curve cut issue By Johan 071224 D43 ESDPAD_R0603 EGA1-0603-V05 ns MIC_IN1

AMP_OUT_L R445

C137 C120 100pF/50V,NPO100pF/50V,NPO C0402 C0402 ns ns change to ns for esd By Johan 071228

GND_AUD INT_MIC_L_R

JACK_DET_B

EAPD R453 ns

2300ohm@100MHz,1.5A FB0805 2300ohm@100MHz,1.5A FB0805

HP_DET D9 ESDPAD_R0603 EGA1-0603-V05 ns

MIC2_REF

R217

SURR_OUT_L

20K,1%

1 4 2 5 6 3 7 8

MIC1_JD

GND_AUD AMP_OUT_R

D14 ESDPAD_R0603 EGA1-0603-V05 ns

ALC662

26 42

C140 C0603

JACK_DET_A R219

SDIN

12

CD-GND

AC_SPKR

1uF/10V,X7R

SDOUT

8

GND1 GND2

{23}

C138 C0603

5

4 7

BTL_BEEP

R0402

LINE1-VREFO-L

LINE_OUT1

4.7uF/10V,X5R C0805 R424 75 R0402 SURR_OUT_L 100uF/10V R421 75 R0402 SURR_OUT_R 100uF/10V 4.7uF/10V,X5R C0805 C142 0.1UF/25V,Y5V C144

SYNC

19

{33}

51K

22

27 28

BITCLK

10

{22} AZALIA_CODEC_SYNC

VREF MIC1-VREFO-L

REST#

CT6 ns ct6032 CT5 ns ct6032 C366

1

A_GPIO0

2

ns

C371

1

ICTP

AVDD1 AVDD2

VDD1 VDD2

T69

Cross moat place

U5 GND_AUD

VerA:Reserve +1.5S power rail for GM

C383

0.1UF/25V,Y5V

2

0.1UF/25V,Y5V

1

0.1UF/25V,Y5V

2FB0805

C381 10UF/6.3V,X5R C0805

{6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,31,33,38,40,41,42,50,51} {19,20,21,23,24,25,31,32,33,38,41,42} {8,14,22,24,26,27,28,38,40,42} GND_AUD GND_AUD GND_AUD Solve audio curve cut issue By Johan 071224 D40 D41 R0402 R0402 ESDPAD_R0603 ESDPAD_R0603 100pF/50V,NPO100pF/50V,NPO EGA1-0603-V05 EGA1-0603-V05 R190 R174 ns ns

2

C382

+

0.1UF/25V,Y5V

C141

+

0.1UF/25V,Y5V

C150 10UF/6.3V,X5R C0805

25 38

C146

1 9

C151

+V5S

FB30

600ohm@100MHz,1.5A 1

R426 0 R0402

R222

1

+V3.3S +V5S +V1.5S GND_AUD Change to cap for esd By Johan 071228

http://shop61976717.taobao.com http://shop61976717.taobao.com VCC5CDC

2

3

+V3.3S

1

4

+V1.5S

C139

GND_AUD connecr mic1_jd to senseB and reserved route to senseA By Johan 071224

C148

C130

100pF/50V,NPO 0.1uF/10V,X7R C0402 ns

2

5

GND_AUD GND_AUD

100pF/50V,NPO C0402 ns GND_AUD

L R C

AZALIAJACK AUDIO8B

GND_AUD

change to ns for esd By Johan 071228

Stereo Microphone Jack INPUT:STEREO MIC-IN OUTPUT:CENT/LFE

T133GND_AUD ICTP

MIC2_L

ns MIC2_R

add cap for esd By Johan 071228

INT_MIC_L_R

FB11 FB0805

R468 10K

R478 10K

GND_AUD GND_AUD

C375 ns

ns 2FB0805 300ohm@100MHz,1.5A

C0603 0.22uF/10V,X7R

GND_AUD

0.1UF/25V,Y5V AMP_OUT_L C422

C0603 0.22uF/10V,X7R

R464

C406 R455 10K 0.47uF/25V,Y5V C0603 C401 0.22uF/10V,X7R C0603 R462 10K

SHUTDOWN# GND_AUD

10K

SURR_OUT_R PQ35 2N7002 SOT23

PQ37 2N7002 SOT23

3

GND_AUD

3

PQ36 2N7002 SOT23

AMP_SHDW1

B

2

1 2

1

GND_AUD

VCC5CDC

U14 TPA6017A2 sop20_0d65_4d4g

VerB:chang the gain to 6dBand change r464,r462 to 10k--090729 AMP_OUT_R C419

3

AMP_SHDW1

INPUT:STEREO MIC-IN OUTPUT:CENT/LFE onboard stereo microphone

VerB:chang the gain to 10dB--090716

FB29 1

SURR_OUT_L PQ38 2N7002 SOT23

GND_AUD

ns

ns

100pF/50V,NPO C0402

ASSY

R477 10K

GND_AUD

17

RIN-

7

RIN+

9

R475 10K

ROUT+

18

+INTSPR

ROUT-

14

-INTSPR +INTSPL -INTSPL

LOUT+

4

10

BYPASS LOUT-

8

5 12

LINNC

16 6 15 1 11 13 20 21

19

GAIN0

2

GAIN1

3

LIN+

VDD PVDD1 PVDD2 SHDWN# GND1 GND2 GAIN0 GND3 GND4 GAIN1 GND5

SHUTDOWN# 3

1

GAIN0 GAIN1

GND_AUD

Q25 2N7002 VCC5CDC

1

{33} AMP_SHDW

2

1

15.6dB 21.6dB

R473 10K

C493 100pF/50V,NPO C0402

MIC1 Microphone BZ_D6027

2

B

Av(inv) 6dB 10dB

C492 100pF/50V,NPO C0402

C127

3

VCC5CDC VCC5CDC

GAIN0 GAIN1 0 0 0 1 1 0

1 2

1

1 2 300ohm@100MHz,1.5A D13 ESDPAD_R0603 EGA1-0603-V05 ns

2

1K

2

INT_MIC_L R186

+

R446 10K

C418 0.1UF/10V,X7R

R469 100K

SOT23

C409 4.7uF/10V,Y5V C0805 C417 0.1UF/10V,X7R GND

GND_AUD

GND_AUD GND_AUD

A

IO_INTSPK1 CNS4_V

GND 5

5

6

6

1 2 3 4

A

1 2 3 4

+INTSPR -INTSPR +INTSPL -INTSPL TOPSTAR TECHNOLOGY bent AZALIA(ALC883)

Size C

M46G

Project Name

Rev B

Date: Sheet Thursday, August 27, 2009 30 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

GND_AUD

5

Page Name

4

3

2

1

5

4

R893ns

Q10 AO3415

ns

R320

3

0 R0805

BT

BT

R296 100K BT

1 2 11 3 4 12 5 6 7 8 9 10

11 BT_ON#

ns

12 R295

BT 1K

3

0

BT 1K

Q9 2N7002E-T1-E3 SOT23 BT

1 R259 100K BT

BT 0 R0402 BT 0 R0402

0.1UF/10V,X7R

+V1.5S

{8,14,22,24,26,27,28,30,38,40,42}

+V1.5AL

{24,39}

H16

1 2 3 4 5 6 7 8 9 10

CHK4 90ohm@100MHz,0.5A 2 1 3 4 ns R314 R313 R300

R299 BT_CON M46 VERB:CHANGE BT_CON THE SAME AS X01--XIEZX C234

2

R260

{33} BT_PWRON

R297 R298

{6,7,8,9,12,13,14,22,24,38,40,41,42,44} {6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,33,38,40,41,42,50,51} {19,20,21,23,24,25,30,32,33,38,41,42} {12,19,22,23,24,26,27,28,29,32,33,34,35,36,37,38,39,40,41,42,50,51}

H13

D

R286

C238

TPCON_USB CNS10_0D8_R

1

C225 1000pF/50V,X7R BT

+V1.05S +V3.3S +V5S +V3.3AL

0

R894 100K

BT_USB_PP5 BT_USB_PN5

ns ns ns

CH_CLK CH_DATA CH_CLK

{23} {23}

D

Hole+Dowel Hole+Dowel TH_230_132_118_6

{27,28} {27,28} {27,28}

TH_200_132_118

BT_ON# 0 Billiton和CCOM的要求不一样 BT_PWRON

+V5S

+V3.3AL +V3.3S

R107 10K ns

R359 10K

VerB:H14闲置不用，删除 xie

FAN_BACK

For FAN&Heatsink use R351

R308

ns

10K

CH_CLK

R311

ns

10K

CH_DATA

R357 10K

ns

0.22uF/10V,X7R

BT

+V3.3S

ns

0 0 0

L4_0805

R897 ns 0

BT_ON

{33}

3

R319

2 BT

1K

1

ns

C284

{33}

FAN_TACH_ON

2

BT 0 R0805

1

R318

1

FAN Controller Circuit http://shop61976717.taobao.com http://shop61976717.taobao.com

BT

0

+V3.3S

2

1 2 3 4 5 6 7

+V5S

3

1000pF/50V,X7R

+V5S

Q17 2N2222 SOT23 ns

R352 0

ns Q5 Vfan

CPUFAN1

R886 10K ns

R887 10K TCM

LPCPD#

LPCPD# LPCPP LPCPP R888 10K TCM

R889 10K TCM

9 3

BA0 BA1

7

PP

14

C741 1uF/10V,X7R C0603 TCM

GND1 GND2 GND3 GND4

4 11 18 25

NC NC1 NC2 NC3 NC4 NC5 NC6

1 2 5 6 8 12 13

0 TCM

0.1UF/25V,Y5V

8

R885 R0805

+

1 C738 10uF/6.3V,X5R TCM

C739 0.1UF/25V,Y5V TCM

2

1

4

5

5

CONN3_V CNS3_V FAN_FB

U1A LM358 so8_50_150 3

C

Shut-Down

+V3.3S 1

10 19 24

2

VDD1 VDD2 VDD3

4

2

R36 1K

LFRAME# LRESET# LCLK LAD0 LAD1 LAD2 LAD3 SERIRQ CLKRUN# LPCPD#

1 2 3

5.11K,1%

C740 0.1UF/25V,Y5V TCM

C26

2 R349 R22 4.7K R0402

10K,1% 2

1

U36 22 16 21 26 23 20 17 27 15 28

1N4148WS SOD323

R346

VCC_358 C30

4

+V3.3S C

0.1UF/25V,Y5V

C275 10uF/10V,Y5V C1206

1

1 2

+V3.3S

{22,28,33} LPC_FRAME# {12,19,23,26,27,28,33,51} BUF_PLT_RST# {6} CLK_TCMPCI {22,28,33} LPC_AD0 {22,28,33} LPC_AD1 {22,28,33} LPC_AD2 {22,28,33} LPC_AD3 {23,33} INT_SERIRQ {23} PM_CLKRUN#

D26 R24 10 R0402

1 2 3

1

C276

R35 1K

TCM

2

BCP69-16 SOT223 4 2

1

3

0.1UF/25V,Y5V R26 100K 2 1

R25 200K

R0402

FAN1_V

Throttling/ Un-throttling

High-5V {33} Middle-4V Low-3V

FAN1_V=3.30V,Vfan=5V FAN1_V=2.65V,Vfan=4V FAN1_V=1.98V,Vfan=3V

NC-P TCM SOP28_0D65_6D1

VerB：add the TCM function

C28

C32 4.7UF/10V,Y5V C0805

0.1uF/25V,Y5V C0402 50

55

60

65

70

75

80

85

90

95

100

+V3.3S +V1.05S R547 10K

B

B

R548 4.7K R0402 ns

VerA:Add RC circuit 071106

3

ns

R549ns 5

3

{7,12,22} PM_THRMTRIP#

{33}

2N7002E-T1

1

ALT_ON

470

C470

R561 100K

1K 2 R556 Q30 R0402 MMDT3904 SC70_6 ns

0.1UF/25V,Y5V ns

2

Use for temperature alarm driver.

R545 100K ns

4

Q31

SHDN_LOCK#

SHDN_LOCK# {40}

6

VerB:Add R618,LJ070712 4.7K

1

R559 100K

R550 100 R0402 ns

R546

2 Q32 MMDT3904 SC70_6

1

5 C479 1000pF/50V,X7R

4

{7} OVT_SHUTDOWN#

10K

6

3

SHDN_LOCK#

R560

C471 2.2uF/10V,X7R C0805 ns

ns

OVP CIRCUIT ns hads

080514

VerA:Delete GMCH_TEMP signal and components 071026

A

CPU THRMTRIP#

Shut Down

PCB1 R20 MB

Throttling on AND

PCB

SHDN#

THERM_ALERT# VDC

PCBA

CPU Temperature 85

90

95

100

(Degree)

5

+

6

-

A

TOPSTAR TECHNOLOGY bent

U1B LM358 so8_50_150 7

5

4

Page Name

MDC&BT/FAN/OTP

Size C

M46G

Project Name

Rev B

Tuesday, September 01, 2009 31 51 Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

4

Thermal sensor

Throttling Off 0

PCBA1 R20 PCBA

8VCC_358

VIN

3

2

1

5

4

USB Board CONN

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com +V3.3S +V5S +V3.3AL +V5AL +VDC AD+

{6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51} {19,20,21,23,24,25,30,31,33,38,41,42} {12,19,22,23,24,26,27,28,29,31,33,34,35,36,37,38,39,40,41,42,50,51} {19,24,29,36,37,39,40,42} {19,28,34,36,37,38,41,42,44} {34}

24pin 0.5mm bot FFC

D

+VDC

{23} {23}

USB_OC#6 USB_OC#2

{23} {23}

USB_PN9 USB_PP9

{23} {23}

USB_PN6 USB_PP6

{23} {23}

USB_PN2 USB_PP2

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

C734 0.01uF/25V,X7R C0402

26 25

D

+VDC

C735 0.01uF/25V,X7R C0402

26 25

USB_CONN

+V5AL

C

C

{33}

TPCLK

TPCLK

2

+V5S

+V3.3AL

R728 10K R0402

Q39 2N7002E-T1

TP_TPCLK_R

3

TR1

1

1

+V3.3AL

{33}

TPDAT

TPDAT

2

0 R0402 ns

TR2

+V5S

R729 10K R0402

Q40 2N7002E-T1

TP_TPDAT_R

3

power button Conn

0 R0402 ns

PWRCONN1

AD+

B

R730 LEFT 1K R0402

4

{34,43} Isense_SYSP {28,33,36} PWR_SW_VCC2

3

3 C586

D52 100pF/50V,NPO

7

7

8

8

1 2 3 4 5 6

1 2 3 4 5 6

+V5S TP_TPDAT_R TP_TPCLK_R

BAT54SPT

1 3 5 7 9 11 13 15 17 19

21 2 4 6 8 10 12 14 16 18 20 22

21 2 4 6 8 10 12 14 16 18 20 22

AD+

B LIDR# +V3.3AL

{19,33}

88242_2001

2

2 TLSW1 TMG-534-V BUTTON4_S

1

1

1 3 5 7 9 11 13 15 17 19

CNS2x10_1_R 620902010002

+V5S

LEFT RIGHT

CNS6_1_R1 Conn 6Pin TP_CON1

R0402

R731 1K

RIGHT

+V3.3AL

VerB:converse the connection of TP_CON1

4 3

3 C587

A

C311

C315

R99 47K R0402

C0603 0.1UF/25V,Y5V 1UF/10V,Y5V C0402

R401 47K R0402

Add pull res TPDAT TPCLK

C300 C0402 0.1UF/25V,Y5V

D53

1

2 TRSW1 TMG-534-V BUTTON4_S

BAT54SPT

A

TOPSTAR TECHNOLOGY

2

100pF/50V,NPO

1

+V5S

bent +V5S

Page Name Size A3

Project Name

USB2.0&&LED CONN&Qkey CONN M46G

Rev B

Date: Tuesday, September 01, 2009 Sheet 32 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

5

4

+V5S

3

+V3.3AL C66

Q23 2N7002E-T1

1

C64

2

A20GATE

3 ns

D28 1

C61

C50

C48

C51

0.1UF/25V,Y5V

0.1UF/25V,Y5V

0.1UF/25V,Y5V

0.1UF/25V,Y5V

Should have a 0.1uF capacitor close to every GND-VCC pair + one larger cap on the supply.

C575 0.1UF/25V,Y5V C0402

C576 1uF/10V,X7R C0603 Vin>=1.5V turn on the cup FAN.

V18R

1

Q21 2N7002E-T1

C60

0.1UF/25V,Y5V

V18R

2

0.1UF/25V,Y5V 0.1UF/25V,Y5V

HDD_ZOUT HDD_YOUT HDD_XOUT

V18R

EC Output Signal!

GA20/GPIO00 KBRST#/GPIO01 SCI#/GPIO0E ECRST#

EC Input Signal!

AD0/GPI38 AD1/GPI39 AD2/GPI3A AD3/GPI3B

63 64 65 66

PWM0/GPIO0F PWM1/GPIO10 PWM2/GPIO11 PWM3/GPIO19

21 23 25 34

MSIC

{23} EC_RUNTIME_SCI#

1 2 20 EC_RESET#37

PWM

A20GATE RCIN#

SYS_I_Sense HDD_ZOUT HDD_YOUT HDD_XOUT

SYS_I_Sense

+V3.3AL CHG_ON R94 10K ALW_PWROK need move to other place.pin110&111 follow the sequence of R18EC C494

SCANIN4 SCANIN5 SCANIN6 SCANIN7

ns

Double confirmed By Johan 0711081231

change to DG By Johan 071224

+V3.3AL 10K

ns

BT_PWRON

R55 1K +V3.3AL

R69

PCIE_WAKE#

76 75

{23,41} IMVP_PWRGD {23,40} MAIN_PWROK

+V3.3AL

+V3.3AL

GPI43 GPI42 E51CS#/GPIO52 E51TXD/GPIO16 E51RXD/GPIO17/E51CLK E51TMR0/GPIO54/WDT_LED# E51INT0/GPIO55/SCROLED# E51TMR1/GPIO53/CAPSLED# E51INT1/GPIO56

80 79 78 77

I2C_DATA I2C_CLK SM_BAT_SDA2 SM_BAT_SCL2

GPXIOA00/SDICS# GPXIOA01/SDICLK GPXIOA02/SDIMOSI GPXIOA03 GPXIOA04 GPXIOA05 GPXIOA06 GPXIOA07 GPXIOA08 GPXIOA09 GPXIOA10 GPXIOA11

GPXIOD0/SDIMISO GPXIOD1 GPXIOD2 GPXIOD3 GPXIOD4 GPXIOD5 GPXIOD6 GPXIOD7

109 110 112 114 115 116 117 118 119 120 126 128

XCLK32K/GPIO57 XCLKI XCLKO

121 122 123

MCH_TSATN# CHG_ON {43} HW_RATIO_OFF_3G# {28} EC_PWROFF# {23} HW_OFF_BKLT# {19} AC_OFF {34} BAT_OV_REV {35}

HW_OFF_BKLT#

3G_OFF# ALW_PWROK

PCB_Mark0 PCB_Mark1 PCB_Mark2

2

+V5S

{12}

3G_LED#

R71

10K

EC_DEBG_Enable_R

R108

10K

EC_PWROFF# PCIE_WAKE#_EC VOLUMEVOLUME+ Media Mute ALT_ON

R103 R68 R73 R76 R88 R83 R48

10K ns 10K 10K 10K 10K 10K 10K ns

R85 10K

Fuction P.M2 P.M1 P.M0 PCB_Mark0 PCB_Mark1 PCB_Mark2

R89 10K

VerA VerB

0 0

0

1

Verc

0

1

1

R578

0

{28} {36,39} EC_V3.3AL

BATT_IN#

ns

0

0

R84 10K ns

{50}

BIU configuration should match flash speed used

3G

4.7K R0402

SPI_CS# SPI_MISO WP#1 VSS

1 2 3 4

CS# Q W# VSS

8 7 6 5

VCC HOLD# CLK D

VCC_SPI R23 HOLD#1 R0603 SPI_SCK R0402 SPI_MOSI

0 4.7K R763

LABEL1 Topstar Soft BIOS Ver: X.XX EC Ver: X.XX XXXX年XX月XX日

EC_V3.3AL EC_V3.3AL

EC/BIOS Label

W25X80A

{35}

R0402

ASSY

ns SOIC8_50_208 U35 VCC_SPI

8

VDD

WP#1

3

WP#

HOLD#1

7

32XCLK1 32XCLK0

SI SO CE# SCK

5 2 1 6

VSS

4

HOLD#

SPI_MOSI SPI_MISO SPI_CS# SPI_SCK VSS

W25X40 SO8_50_150 EC_V3.3AL

GND GND GND GND GND

B

R378 10K R0402

VerB: Colay tow roms,stuff U35

EC_RESET#

R58

Q8 2N7002E-T1

4.7K

2

3

ns EC Input Signal! PROCHOT#

Q22 MMBT3904-F

1 R0603

100 R0402

+V3.3AL R111

4.7K

R115

4.7K

R0402

R0402

ns 0 R116

EC_BUF_PLT_RST#

C292

R588 0 R0402

0.01uF/16V,Y5V C0402

ns

R373 10K R0402

R0402 C37

EC_PCI_RST# 32XCLK0

R63 10K R0402 ns

R30

121K,1%

1

1

5.6K

LIDR#

R90 10K

R92 10K

SPI_MISO SPI_MOSI SPI_SCK SPI_CS#

R0402

0

5.6K

R110

4.7K

change vera to verb hads R895 0

R762

EC_DEBG_Enable_R EC_BUF_PLT_RST#

ns

R91

R118

SM_BAT_SCL2

ns

CHG_LED# {50} BTL_LED# {50} PM_PWRBTN# {23} AMP_SHDW {30}

+V3.3AL

{7} EC_PROCHOT#

4.7K

SM_BAT_SDA2

GPXIOA00

R0402

C46

R120

C

R93 10K ns

+V3.3S R344 0

PM_SLP_S3#

100pF/50V,NPO

I2C_DATA

10K

C288 4.7UF/10V,Y5V C0805

PM_SLP_S4#

C44

R732

KB3926

The 0ohm RES will across the isolate island of anolog GND and digital GND

2N7002E-T1C0402 1000pF/50V,X7R

1M

100pF/50V,NPO

GPXIOA00

{7} {7} {35} {35}

R593 R70

I2C_CLK

C45

1

{28,32,36} PWR_SW_VCC2

{31}

R100 0

3

PWRSW#

Q7

R104 100K

FAN_BACK

SOD323

TPCLK {32} TPDAT {32} BT_PWRON {31} HW_RATIO_OFF# {27} OV_BAT_ALART {35} EXTSMI# {23}

MISO MOSI SPICLK/GPIO58 SPICS# change to DG By Johan 071224

113 94 35 24 11

69

R66 10K R0402

1 D8 1N4148WS

{31} {19}

EC_DEBG_Enable {28}

AGND

Mute

83 84 85 86 87 88

97 98 99 100 101 102 103 104 105 106 107 108

CLK

B

90 30 31 92 93 91 95

VOLUMEVOLUME+ Media

R0402

{31} FAN1_V Camera_ON

10K 10K 10K 10K

U2

8051

PROCHOT# {28} EC_DEBG_UTXD {28} EC_DEBG_URXD

AMP_SHDW

SDA1/GPIO47 SCL1//GPIO46 SDA0/GPIO45 SCL0/GPIO44

SPI

ns

BT_ON

R574 R575 R577ns R576ns ns R119ns

+V3.3AL

R101 10K

swap for DG By Johan 071224

EC_FAN_BACK

28 29 26 27 R579 1K

ns

GPXIOD

0

{19,23} PM_SUS_STAT#

KSO17/GPIO49 KSO16/GPIO48 KSO15/GPIO2F/E51_RXD(ISP) KSO14/GPIO2E KSO13/GPIO2D KSO12/GPIO2C KSO11/GPIO2B KSO10/GPIO2A KSO9/GPIO29 KSO8/GPIO28 KSO7/GPIO27 KSO6/GPIO26 KSO5/GPIO25 KSO4/GPIO24 KSO3/GPIO23/TP_ISP KSO2/GPIO22/TP_ANA_TEST KSO1/GPIO21/TP_PLL KSO0/GPIO20/TP_TEST

EC_PMSUSStat# 6 GPIO04 0 ns PCIE_WAKE#_EC 14 GPIO07/i_clk_8051 15 GPIO08/i_clk_peri {34} AC_IN 16 GPIO0A/CIR_RX2 {23,39,40} PM_RSMRST# R72 1K 17 GPIO0B/ESB_CLK {19,32} LIDR# PWRSW# R67 1K 18 GPIO0C/ESB_DAT_O/ESB_DAT_I 19 GPIO0D {23,26,40} PM_SLP_S3# 32 GPIO18 {23,26,42} PM_SLP_S4# 36 GPIO1A/NUMLED# {38} V1_5S_ON EC_IR_IN 73 R46 1K EC_IMVP_ON 74 GPIO40/CIR_RX {41} IMVP_ON GPIO41/CIR_RLC_TX 89 GPIO50 {31} ALT_ON 127 GPIO59/TEST_CLKSPICLKI {38} V1_05S_ON R56EC_PMSUSStat# 68 {36} ALWAYS_ON GPO3C 70 GPO3D {42} MAIN_ON 71 GPO3E {37} V1_8_ON 72 GPO3F {37} V0_9S_ON {23,26,27,28,51}

R121

82 81 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39

GPXIOA

EC_IMVP_ON EC_IR_IN

10K ns 10K

SCANOUT15 SCANOUT14 SCANOUT13 SCANOUT12 SCANOUT11 SCANOUT10 SCANOUT9 SCANOUT8 SCANOUT7 SCANOUT6 SCANOUT5 SCANOUT4 SCANOUT3 SCANOUT2 SCANOUT1 SCANOUT0

PSCLK1/GPIO4A/P80CLK PSDAT1/GPIO4B/P80DAT PSCLK2/GPIO4C PSDAT2/GPIO4D PSCLK3/GPIO4E PSDAT3/GPIO4F

SET_I

SPI_CS# SPI_MOSI SPI_MISO SPI_SCK

3300pF/50V,X7R C0402

R27 10M R0402

ns

C0402 Y2 32.768KHz xd3_2X6 3 ASSY

15pF/50V,NPO

2

不用的pin上拉到+V3.3AL. R47 R106

SCANIN0 SCANIN1 SCANIN2 SCANIN3

KSI7/GPIO37 KSI6/GPIO36 KSI5/GPIO35 KSI4/GPIO34 KSI3/GPIO33 KSI2/GPIO32 KSI1/GPIO31 KSI0/GPIO30/E51_TXD(ISP)

{30} POWERLED# {50} {43} EC_BKLT_PWM {19}

3

4.7K 2 4 6 8 ns RN28 4.7K 1 2 3 4 5 6 7 8

62 61 60 59 58 57 56 55

BTL_BEEP

2

RN1 1 3 5 7

SCANIN7 SCANIN6 SCANIN5 SCANIN4 SCANIN3 SCANIN2 SCANIN1 SCANIN0

GPIO

+V3.3AL

+V3.3AL

FANFB0/GPIO14 FANFB1/GPIO15 FANPWM0/GPIO12 FANPWM1/GPIO13

SMBUS

SCANOUT15 SCANOUT10 SCANOUT11 SCANOUT14 SCANOUT13 SCANOUT12 SCANOUT3 SCANOUT6 SCANOUT8 SCANOUT7 SCANOUT4 SCANOUT2 SCANIN7 SCANOUT1 SCANOUT5 SCANIN4 SCANIN5 SCANOUT0 SCANIN2 SCANIN3 SCANOUT9 SCANIN1 SCANIN0 SCANIN6

EC_PCI_RST# CLKREQ

CLKREQ

PS2

28 27

R717 4.7K R0402

PCICLK SERIRQ LFRAME# LAD0 LAD1 LAD2 LAD3 PCIRST#/GPIO05 CLKRUN#/GPIO1D

FAN

C

+V3.3AL

12 3 4 10 8 7 5 13 38

KB3926

{6} CLK_591PCI {23,31} INT_SERIRQ {22,28,31} LPC_FRAME# {22,28,31} LPC_AD0 {22,28,31} LPC_AD1 {22,28,31} LPC_AD2 {22,28,31} LPC_AD3

LPC

EC_BUF_PLT_RST#

0

KB

KBCON1 ACES 85201-2602 CNS26_1_R_1D7

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

D

{43}

SYS_I_Sense R59

BUF_PLT_RST#

R0402

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 28 6 27 5 4 3 2 1

10K 10K 10K

U29

ADC

1N4148WS SOD323

111 96 33 22 9 125

RCIN#

3

D27 1

{12,19,23,26,27,28,31,51}

R33 R42 R32

ns

2

H_RCIN#

1

C277

124

{22}

EC_V3.3AL

+V3.3AL

1N4148WS SOD323

+V5S

R375 10K

D

EC_V3.3AL

C47 10UF/6.3V,X5R C0805

R75 0 R0805

FB21 120ohm/100MHz,500mA 1 2FB0603

C273 +V3.3S

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C0402

0.1UF/16V,Y5V

EC Output Signal!

1

{6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,38,40,41,42,50,51} {12,19,22,23,24,26,27,28,29,31,32,34,35,36,37,38,39,40,41,42,50,51} {19,20,21,23,24,25,30,31,32,38,41,42} {19,28,32,34,36,37,38,41,42,44}

VCC VCC VCC VCC VCC VCC

{22} H_A20GATE

C0402

0.1UF/16V,Y5V

R0402

2

+V3.3S +V3.3AL +V5S +VDC

67

R380 8.2K

+V3.3S

AVCC

+V3.3S

C29 32XCLK1

C0402 15pF/50V,NPO

A

A

R718

0

R0603

TOPSTAR TECHNOLOGY bent Page Name

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Size Project Name Custom

M46G

Rev B

Tuesday, September 01, 2009 33 51 Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

BATT+ +VDC AD+ +V3.3AL

http://shop61976717.taobao.com http://shop61976717.taobao.com PR44 15K R0402 PR45

PR94 100K R0402

PC102 0.01uF/25V,X7R C0402

S G

4

1 2 3

D

8 7 6 5

PQ10 SI4435BDY SO8_50_150

PR96 51K R0402

PD35

SBM54PT SMB

ns

Change from 0.020ohm to 0.025ohm 071026

5A

1 1

PD36 SBM54PT

PD3 1

SSM34PT SMA

SO8_50_150 SI4435BDY PQ4

4

SSM34PT SMA

PR15

7A

3 2 1

0.025,1% R2512

7A

5 6 7 8

BATT+

SMB 1

5A

PD2 1

S

AD+

{36}

G

ALW_EN PC35 0.1uF/25V,X7R C0603

10 R0402

D

PR39 3.3K R0402

{35,43} {19,28,32,36,37,38,41,42,44} {32} {12,19,22,23,24,26,27,28,29,31,32,33,35,36,37,38,39,40,41,42,50,51}

ns

7A

PC105 0.1uF/25V,Y5V C0402

{32,43} Isense_SYSP

PD1 SSM34PT SMA

{40,43} Isense_SYSN PR98 51K R0402

colay sbm54pt

7A

080514

1 2 3

PR112 51K R0402

S

D

G

4 AC_OFF

3

3

3

PR97 100K R0402

PQ27 2N7002 SOT23

1

+VDC

{40} BAT_OV#

PQ25 2N7002 SOT23

1

SHDN#

{35}

PR113 51K R0402

PC113 C0402 1000pF/50V,X7R

PR100 510K R0402

PC103 C0402 1000pF/50V,X7R

+V3.3AL

PR95 100K R0402

3

AD+

2

2

2

{33}

PQ28 2N7002 SOT23 1

7A

PQ6 SI4435BDY SO8_50_150

PR19 510K R0402

PR101 510K R0402

8 7 6 5

PQ26 2N7002 SOT23

PR109 51K R0402 PC104 1000pF/50V,X7R C0402

AC_IN

2

1

PR99 20K R0402

{33}

PR102 1K R0402

TOPSTAR TECHNOLOGY bent Page Name

ADAPTER IN

Size A3

M46G

Project Name

Rev B

Date: Thursday, August 27, 2009 Sheet 34 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

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PFB4 100ohm@100MHz,3A 1 2

GND_BAT

PC198 PF1 0.1uF/25V,Y5V 8A C0402 FUSE1206 ns 1 2

FB0805 PFB3 100ohm@100MHz,3A 1 2

BATT+

PC7 1000pF/50V,X7R SM_BAT_SDA2

{33} SM_BAT_SDA2

FB0805 PFB2 100ohm@100MHz,3A 1 2 FB0805

080514

BATCON1

7A

BATT+

7

BAT_B1

BAT_B2

KEY PR8

SM_BAT_SCL2

{33} SM_BAT_SCL2

PF2 8A FUSE1206 1 2

add 0.1u for EMI hads

SM_BAT_SDA

6

SDAT

SM_BAT_SCL

5

SCLK

4

TEMP

3

BAT_IN#

2

GND

1

GND

Screw 2*8mm

Screw 2*8mm

711000000013

711000000013

PR1

0 R0402 ns

PR7

0 R0402 ns

PR9

0 R0402 ns

change to 2*11mm By Johan 071224 GND_BAT

8

PR3

100 R0402 100 R0402

9

7A

{34,43} {32,34} {12,19,22,23,24,26,27,28,29,31,32,33,34,36,37,38,39,40,41,42,50,51}

SK-C103A3-100A

+V3.3AL

+V3.3AL +V3.3AL

SM_BAT_SDA2

PZD2

GND_BAT PR2 300K R0402

PZD1

2

SM_BAT_SCL2

PC1 0.1uF/25V,Y5V C0402

change to 5.6pF,070428

2 3

1

SM_BAT_SDA PC3 0.1uF/25V,Y5V C0402

3

SM_BAT_SCL

1

PR6 PC6 5.6pF/50V,NPO C0402

PC2 5.6pF/50V,NPO C0402

BATT_IN#

BAT54S SOT23

{33}

BAT54S SOT23

R0402 1K GND_BAT GND_BAT

GND_BAT

{33}

BAT_OV_REV

BAT_OV# PD16 +V3.3AL 1N4148WS SOD323

2

1

{34}

PQ31 2N2907 SOT23

PR122 1K R0402

PR47 51K R0402

3

3

1

PQ32 2N2222 SOT23

1 2

GND_BAT

PR125 2K R0402

PC121 0.1UF/25V,X7R C0603

OV_BAT_ALART {33}

Delete reserve TOPSTAR TECHNOLOGY bent Page Name

BATTERY IN

Size A3

M46G

Project Name

Rev B

Date: Thursday, August 27, 2009 Sheet 35 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

5

4

3

2

1

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+V3.3AL +VDC AD+ +V5AL EC_RTC

{12,19,22,23,24,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,50,51 {19,28,32,34,37,38,41,42,44} {32,34} {19,24,29,32,37,39,40,42} {22}

1.输入电容要靠近MOSFET漏极 2.MOS管尽量靠近IC芯片

C0402 PC228 0.01uF/25V,X7R

12

OCSET1

OCSET2

29

13

EN1

EN2

28

14

PHASE1

PHASE2

27

15

UGATE1

UGATE2

26

16

BOOT1

BOOT2

25

D G

PC244 0.22uF/16V,X7R C0603

PR292 10K R0402 ns

LL2

PR295 5.11K,1% R0402

24

G2 G1

23

4

PR293 0 R0402

0

3A PC251 4.7uF/10V,X5R C0805

PR297 3.01K,1% R0402

GND_ISL62382 PR296 R0402

PQ81 AO4468 SO8_50_150

3 2 1

R0402

LDO5 22

21

20

19

18

G3 G4 G5 17

D G S

0 PQ80 AO4468 SO8_50_150

PC248 4.7uF/25V,X7R C1206

1

PL15 PR301 5.2uH/5.5A ns LS2_1040 2.2 R0805

5 6 7 8

G2 G1

LGATE2

PGND

LDO5

VIN

LDO3IN

LDO3

LDO3FB

S

1 2 3

+VDC

V5AL1 TestP TPC60 ns

PR288 20K R0402

3 2 1

8 7 6 5

GND_ISL62382

+V5AL 6A

PC242 0.047uF/50V,X7R C0603

PD38 1N5819 SOD123

ns PC254 0.01uF/25V,X7R C0402

ns

+

PZ13 BZT52C5V6S-F/5.6 SOD323 PC249 1000pF/50V,X7R C0402

PC250 220UF/6.3V,OSCON CAP6_6x7_3

6A

B

M46G VerB:add the RC circuit to improve the power quality--xiezx

EC_RTC PC252 4.7uF/10V,X5R C0805 PR298 R0402 10

3

PD40 BAT54C SOT23

EN_V5AL

EN_V3AL PC253 1000pF/50V,X7R C0402

PR299 100K R0402

PR300 0

GND_ISL62382

A

R0402

8 7 6 5

PR294

4

1 2 3

1

PQ78 AO4468 SO8_50_150 4

1

{34} ALW_EN

C

S

PR302 ns PD37 2.2 PC247 R0805 1N5819 220UF/6.3V,OSCON CAP6_6x7_3 SOD123 ns PC255 0.01uF/25V,X7R C0402

1

2

EN_V5AL

0

PD39 1N4148WS SOD323

{33} ALWAYS_ON

PR286 20K R0402

PR291

R0402

M46G VerB:add the RC circuit to improve the power quality--xiezx

{28,32,33} PWR_SW_VCC2

1

4

30

PC238 4.7uF/25V,X7R C1206

090803:PC237与PC238colay,ns PC237--xiezx VERC:去掉COLAY--XIEZX

1

2

VCC2

ISEN2

PC237 ns 10uF/ 25V,X7R C1210

PR284 R0402 22.1K,1%

G

B

5

ISEN1

PC236 0.1uF/25V,X7R C0603

D

1

+

VCC1

11

15K R0402

PC243 0.22uF/16V,X7R C0603

1

PC245 1000pF/50V,X7R C0402

0

PL14 3.3uH/4.8A LS2_8836

1

2

1

ns

6

PR285

PR290 PR289 10K R0402 ns

1

PZ12 BZT52C3V6S-F/3.6 SOD323

7

31

4 PQ79 AO4468 SO8_50_150

32

S

PC246 4.7uF/25V,X7R C1206

FB2

PC235 1000pF/50V,X7R C0402

PR282 680 R0402

G

PR287 15K R0402

GND_ISL62382

PC240 1000pF/50V,X7R C0402

VOUT2

PU11 ISL62382HRTZ

2A

PR280 3.01K,1% R0402

D

V3.3AL1 TestP TPC60 ns

PR277 20K,1% R0402

VOUT1

EN_V3AL

+VDC

GND_ISL62382

10

C

PC241 0.047uF/50V,X7R C0603

FB1

LDO3EN

9

FSET1

PC239 1000pF/50V,X7R C0402

PR281 R0402 680

R0402 PR283 45.3K,1%

+V3.3AL 3A

PR278 0 R0402 ns

PC231 C0402 0.01uF/25V,X7R

ALW_PWROK

8

GND_ISL62382

PC234 1000pF/50V,X7R C0402

PGOOD1

PC233 0.1uF/25V,X7R C0603

100K

G3 G4 G5 LGATE1

PC232 10uF/ 25V C1210

PR275 R0402

PR279 R0402 10K,1%

4.信号地和电源地在输出电容的负极连到一起

LDO5

PGOOD2

{33,39} ALW_PWROK

PR276 10 R0402

PR274 20K,1%

2

2A

VDC1 TestP TPC60 ns

R0402

FSET2

+V3.3AL

3

+VDC

PR273 10 ns R0402 GND_ISL62382

FCCM

GND_ISL62382

D

2

PC230 1uF/10V,X7R C0603

1

PC229 1uF/10V,X7R C0603

3.芯片的Thermal GND用至少5个过孔连到信号地,用来散热

1

GND_ISL62382

2

GND_ISL62382

5 6 7 8

D

R0402

GND_ISL62382

TOPSTAR TECHNOLOGY

GND_ISL62382

A

Hads Page Name

+V3.3AL/+V5AL/+V1.5AL

Size A3

M42G

Project Name

Rev B

Date: Tuesday, September 01, 2009 Sheet 36 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

+V0.9S +V5AL +V3.3AL +VDC +V1.8

{17,18,42} {19,24,29,32,36,39,40,42} {12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,38,39,40,41,42,50,51} {19,28,32,34,36,38,41,42,44} {12,13,14,15,16,40,42}

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PC151 PC159 10uF/6.3V,X5R10uF/6.3V,X5R C0805 C0805 ns

2

VTT

3

VTTGND

5

GND

CS

15

V5IN

14

PGOOD

13

PGND

16

21

V0_9S1 TestP ns TPC60

VTTSNS

10

TGND

2.5A +V0.9S

4

VDDQSET

5 6 7 8

F_5VAL

DDR_PWG

2

1

1 +

+V1.8

4A

PC200 220uF/2.5V,POSCAP CT7343_19 ns

1

3 2 1 +V5AL

+V3.3AL

PC143 4.7UF/6.3V,X5R C0805

400KHz

Change from 22uf to 10uf 1108 Steven

1

2.2uH/9A LS2_6530 ns PC256 0.01uF/25V,X7R colay pl13 C0402

PC135 C0402 PC136 220UF/6.3V,OSCON 0.1uF/10V,X7R CAP6_6x7_3 +

PZ4 BZT52C2V0S-F/2.0V SOD323 ns

10 PR160 R0402

PR162 R0402 20K PR166 100K R0402 ns

5 6 7 8

TPS51116 DRVL 4

PC140 1000pF/50V,X7R C0402

PL13 ns

2

3 2 1

TPS51116 DRVL 4

D-CAP

+V1.8

1

PD20 PR303 SSM34PT ns SMA 2.2 R0805

2

500mA

PQ56 AO4468 SO8_50_150

V1_8 TestP TPC60 ns

1

DDR_GND

S5

8

PQ50 AO4468 SO8_50_150

1

12

COMP

PR244 R0603 0

1

R0402

S3

DRVL

17

4A

500mA

S

200K

VTTREF

18

PL10 5.2uH/5.5A LS2_1040

G

PR167

R0402 R0402

11

LL

+VDC

PC138 10uF/25V,X5R C1210 ns CO_Lay

D

V1_8_ON

7

R0402

200K 10K

MODE

19

S

PR163 PR168

10K

6

DRVH

PR150 10K

G DDR_PWG

R0402 PR172 0

{40}

M46G VerB:add the RC circuit to improve the power quality--xiezx

F_5VAL

PC145 1uF/10V,X7R C0603 ns

DDR_GND

1

V1_8_ON

DDR_GND

+V3.3AL +V5AL

PR266 51K R0402

DDR_PWG

PR268 1K R0402

PQ75 2N7002E-T1-E3 SOT23

2

2

1

1

3

+V0.9S

PR267 20K R0402

J12 JOPEN RESISTOR_1 ns

3

PJ4 JOPEN RESISTOR_1 ns

1

PQ76 MMBT2222A SOT23

2

+V3.3AL

2

{33}

PR165

V0_9S_ON

VDDQSNS

4

500mA

D

DDR_GND

9

PC142 0.1uF/25V,X7R C0603

S

PC152 0.1uF/10V,X7R C0402

VBST

PQ49 AO4468 SO8_50_150

PR243 R0603 0

PC137 4.7uF/25V,X7R C1206

G

12,15,16} SM_VREF_L

VLDOIN

PC141 0.1uF/25V,X7R C0603 20

5 6 7 8

PC150 4.7UF/6.3V,X5R C0805

1

{33}

PC144 1000pF/50V,X7R C0402

PU8 TPS51116 SOP20_0D65_4D4G

D

PC147 0.1UF/10V,X7R C0402

1.5A

3 2 1

2.5A

+V1.8

PR269 20K R0402 TOPSTAR TECHNOLOGY bent Page Name

+V1.8/+V0.9S DDR

Size A3

M46G

Project Name

Rev B

Date: Tuesday, September 01, 2009 Sheet 37 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

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+V1.05S +VDC +V5S +V3.3S +V1.5S +V3.3AL

{6,7,8,9,12,13,14,22,24,31,40,41,42,44} {19,28,32,34,36,37,41,42,44} {19,20,21,23,24,25,30,31,32,33,41,42} {6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,40,41,42,50,51} {8,14,22,24,26,27,28,30,40,42} {12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,39,40,41,42,50,51}

2A +VDC PC48 4.7uF/25V,X7R C1206

R0402 AO4468 PQ15

G2 GND2

12 DRVL2

11 LL2

10

9

DRVH2

EN2

VBST2

8

7 PG2

13

TRIP2

14

VO1

PGND1

18

19

2

1

1

3 2 1 5 6 7 8

12A

V1_05S1 TestP PZ2 TPC60 BZT52C2V0S-F/2.0V ns SOD323 ns

GND_51124 Change from 23.7k to 9.31k 1108 Steven +V5S FILT124 PC60 1uF/10V,X7R C0603 PR61 15K R0402

PC62 1000pF/50V,X7R C0402 ns

G1

20

VBST1

21

24

PR59 4.99K,1% R0402

+

GND_51124

ns

PR53

GND1

17

DRVL1

TRIP1

LL1

VFB1

DRVH1

16

22

1

C0402

9.31K,1% 15 FILT124 PR58 R0402 2.2

V5IN

EN1

2

QFNS24_0D5_1G

PG1

GND

23

3

PC188 1uF/10V,X7R C0603 ns

PC57 1000pF/50V,X7R

PGND2

V5FILT

TPS51124

GND_51124

TONSEL

PQ14 AO4706 SO8_50_150

+

1

1

PC59 0.01uF/16V,X7R C0402 ns

12A PC132 220UF/6.3V,OSCON CAP6_6x7_3

1

VFB2

PU2 tps51124

FILT124

4

PQ77 AO4706 SO8_50_150 ns

+V1.05S

1.0uH/11A

S

R0402 ns

TPS51124_LDR2 4

G

TPS51124_LDR2 4

S

5

VO2

PD19 SSM34PT SMA

1

500mA

G

6 GND_51124

1

D

PR246 R0603 0

PC130 220UF/6.3V,OSCON CAP6_6x7_3

PL7

lx2

5 6 7 8

lx2

D

PC55 0.22uF/16V,X7R C0603

PR55 4.99K,1% R0402

GND_51124

S

500mA

GND_51124

PR56 1K

4

2

HDR2 PR48 10K

PC56 470pF/25V,X7R C0402 ns

CO_Lay

G

500mA

CHIPPWROK

+V1.05S PR57 2K,1% R0402

PC65 10uF/25V,X5R C1210 ns

CO_Lay

2

PR245 R0603 0

PR51 R0402 20K ns

PC53 1000pF/50V,X7R C0402

D

GND_51124 +V3.3S

PC47 10uF/25V,X5R C1210 ns

5 6 7 8

PR52 200K

3 2 1

V1_05S_ON

PC52 0.1uF/25V,X7R C0603

R0402 10K

3 2 1

{33}

PR49

PC64 4.7uF/25V,X7R C1206

GND_51124

PC58 C0603 1uF/10V,X7R

GND_51124

GND_51124

V1_5S_ON

4

1 2

2

PZ3 BZT52C2V0S-F/2.0V SOD323 ns

+V1.5S +V1.5S

PL9 3.3uH/4.8A LS2_8836

D

SO8_50_150 AO4468 PQ16

4A

V1_5S1 TestP ns TPC60

G

500mA

4A

1

PR54 10K

S

PR63 200K R0402

PR248 R0603 0

lx1

3 2 1

500mA

PR62 R0402 10K

GND_51124 V1_05S_ON

+V3.3AL

+V3.3AL

PC50 4.7uF/25V,X7R C1206

PR50 0 R0402

1 PJ3 JOPEN RESISTOR_1 ns

2

1

V1_5S_ON

2

{33}

CHIPPWROK

PC133 Delete PC70 220UF/6.3V,OSCON CAP6_6x7_3

5 6 7 8

{40} CHIPPWROK

PC189 1uF/10V,X7R ns C0603

5 6 7 8

D

SO8_50_150 AO4468 PQ17

PD7 1N5819 SOD123

1

1

4

1

+V1.5S

PR247 R0603 0

G

500mA

+

PC63 0.22uF/16V,X7R C0603

S

PC61 470pF/25V,X7R C0402 ns

3 2 1

GND_51124 PR60 4.99K,1% R0402

PC51 0.1uF/25V,X7R C0603

PJ2 JOPEN RESISTOR_1 ns GND_51124

CO_Lay

PC49 10uF/25V,X5R C1210 ns

TOPSTAR TECHNOLOGY bent

PC54 1000pF/50V,X7R C0402

1A

+VDC

Page Name

+V1.5S/+V1.05S CHIPSET

Size A3

M46G

Project Name

Rev B

Date: Thursday, August 27, 2009 Sheet 38 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

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+V1.5AL +V5AL +V3.3AL

+V1.5AL

PR270 301,1%

PC196 10uF/6.3V,X5R C0805

PC197 10uF/6.3V,X5R C0805 PR272 60.4,1%

PR271 1K R0402

Add 0ohm By Johan 071224

PR212 0 R0402

{33,36} ALW_PWROK

PR136 +V5AL 0 R0402

ns

PC69 0.1uF/10V,X7R C0402 ns

ns

PC73 0.22uF/10V,X7R C0603 ns

+V3.3AL

PR70 10K R0402

5

+

6

-

PR161 1K R0402 PU3B ns LM358 SO8_50_150 PD8 RSMRST# 1 7 ns 1N5819 SOD123 ns

2 HMBT3906 3

PM_RSMRST# {23,33,40}

ns +V3.3AL R516 10K PR164 510K R0402 ns

ns

D37 1N4148WS ns

D38 1N4148WS ns

1

PC139 0.22uF/10V,Y5V C0402 ns

0

ns Q28

1

PR69 10K R0402 ns

R518

1

ns

+V3.3AL

1

PU10 KIA1117 SOT223

0.5A

2 4

8

VOUT Vo

4

VIN

D39 1N4148WS ns

R521 10K ns

PR66

0 R0402 ns

R525 5.11K,1% ns

+V5AL

8

3

3

+

2

-

PU3A LM358 SO8_50_150 ns 1 TOPSTAR TECHNOLOGY

4

0.5A

1

+V3.3AL

1N4148WS SOD323 1 ns

ADJ/GND

PD34

{24} {19,24,29,32,36,37,40,42} {12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,40,41,42,50,51}

bent Page Name

+PEX_VDD/+V1.8GDDR

Size A3

M46G

Project Name

Rev B

Date: Thursday, August 27, 2009 Sheet 39 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

http://shop61976717.taobao.com http://shop61976717.taobao.com +V3.3S +V5AL +V3.3AL +V1.05S +V1.5S +VCC_CORE +V1.8 AD+

+V3.3S

Power Good Logic CIRCUIT PR171 10K R0402

{6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,41,42,50,51} {19,24,29,32,36,37,39,42} {12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,41,42,50,51} {6,7,8,9,12,13,14,22,24,31,38,41,42,44} {8,14,22,24,26,27,28,30,38,42} {8,41} {12,13,14,15,16,37,42} {32,34}

Delete NVVDD_PWROK

Delete IO_PWRGD 1108 Steven MAIN_PWROK {23,33} PR170 {38} CHIPPWROK

1K R0402

PD30

{37} DDR_PWG

1 1N4148WS

SOD323 PD24

1 1N4148WS PQ58 DTB114EK SOT23 2 3

SOD323

C469 0.1uF/10V,X7R C0402

{34,43} Isense_SYSN

SHDN#

{34}

PR196 20K

2

PR181 20K R0402

PR199

0 R0402

PR198 20K R0402

1 3

{31} SHDN_LOCK#

+V5AL

SOD323 1

2

PZ8 2

5

BZT52C5V6S-F/5.6

+V3.3AL

PZ6 ns 2

SOD323 1

BZT52C3V6S-F/3.6

PQ57 2N7002

6

PQ53

PQ61 DTB114EK SOT23 PC162 0.01uF/25V,X7R C0402 1

3

PR201 100K R0402

PC170 0.1uF/25V,Y5V C0402

1

PD28

3

1K

R0402

MMDT3904

PC168 1uF/10V,X7R C0603

SOT23

2

PR194 100 R0402

1

R544 {23,26,33} PM_SLP_S3#

OVP CIRCUIT

1 1N4148WS

SOD323

4

{23,33,39} PM_RSMRST#

SC70_6

PC166 1000pF/50V,X7R C0402

PR185 20K R0402

PR180 20K R0402

PZ5 +V1.8

+V1.5S

+V1.05S

+VCC_CORE

2

1

ns BZT52C2V0S-F/2.0V SOD323 PZ7 2 1 ns BZT52C2V0S-F/2.0V SOD323 PZ9 2 1 ns BZT52C2V0S-F/2.0V SOD323 PZ11 2 1 ns BZT52C2V0S-F/2.0V SOD323

TOPSTAR TECHNOLOGY bent Page Name Size A3

Project Name

Power Good Logic/OVP M46G

Rev B

Date: Thursday, August 27, 2009 Sheet 40 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com

27

500mA

1000pF/50V,X7R

4

PC36 220UF/2.5V,POSCAP CT7343_19

PC37 220UF/2.5V,POSCAP CT7343_19

22A

0.68uH/28A ns

AOL1426

PC32 1000pF/50V,X7R C0402

+V5S

PC26 0.1uF/25V,X7R C0603

PC25 10uF/25V,X7R C1210

PC24 10uF/25V,X7R C1210

3A

CPU_GND

10

IMVP_PWRGD#

+VDC

PC27 1uF/25V,Y5V C0805 ns +VDC

B

4.02K,1%

PR12 1K,1% R0402

PR80

10K,1% R0402

IMVP_VI Test Debug

1

1

2

2

2

A

1

J1 JOPEN RESISTOR_1 ns

2

PC91 0.047uF/50V,X7R C0603

CPU_GND

PR33 PR36 PR37 PR34 PR35 PR41

1

CHANGE from Y5V to X7R

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6

2

PC90 0.22uF/16V,X7R C0603

{8} {8} {8} {8} {8} {8} {8}

1

0 R0402

PQ8 2N7002 SOT23 ns

1

PR82 4.53K,1% R0402

1

PC94 0.1UF/10V,X7R C0402

2

CPU_GND

PR32 1K R0402 ns

+V1.05S

PR79 1K,1% R0402

CPU_GND

+V3.3AL

PR78 R0402 3.57K,1%

3

PC13 C0402 330pF/50V,X7R

1000pF/50V,X7R

2

PC93 C0402

IMVP_PWRGD

IMVP_ON

3

PR13

{33}

PR16 0 R0402

PR77

PC195 1uF/10V,X7R C0603 ns

PL5

PQ29

PR11 R0402

PC14 1000pF/50V,X7R C0402

PR86 PR87 10K 10 R0402 R0402 0.36uH/30A LS2_1040 PL4

PC12 0.1uF/25V,X7R C0603

PC15 0.1UF/10V,X7R C0402

VSSSENSE

PC96 C0603 0.22uF/16V,X7R

SO8_50_150_PPAK

CPU_GND {8}

1

3 2 PR40 10K

R0603

PC11 1uF/10V,X7R C0603

PC17 1000pF/50V,X7R C0402

PD13 SBM54PT SMB

AOD448 PQ11

PR237 0 CPU_GND

PR10 R0402 10

2K

2

PC9 0.22uF/16V,X7R C0603

PC97 0.01uF/25V,X7R C0402 ns PR85 5.11K,1% R0402 PR88 2.2 R0805 ns

3

NC

25

VCC_OUT

3 2 1

500mA

ISEN1

26

24

ISEN2 ISEN2

BOOT2

PC38 220UF/2.5V,POSCAP CT7343_19

C

1

ISEN1

23

22

VDD

GND 21

VIN 20

VSUM 19

VDIFF

FB2

VO

FB

2

UGATE2

44A

PC86

4.7uF/10V,X5R

2

COMP

+

0.22uF/16V,X7R C0603

VSUM

+V5S

PR238 0 R0603

ISEN1

500mA

30

R0603

ISEN2

500mA

28

31

0

PC194 + 1uF/10V,X7R C0603 ns

PC95

PC85 0.01uF/25V,X7R C0402 ns

5 6 7 8 9

38

37

VID1

VIO0

40

41

42

39 VID2

VID3

VID4

29

PHASE2

PVCC LGATE2

PR236

+VCC_CORE

PR84 10 R0402

2

PC16 1uF/10V,X7R C0603 ns

43

PGND2

VW

13

VCC_OUT

PR17 10 R0402

VCCSENSE

VID5

OCSET

9

32

PR83 10K R0402

22A

D

PC23 C0402

IVD6

8

33

PD10 SBM54PT SMB

VCC_IMVP1 TestP TPC60 ns

PC39 220UF/2.5V,POSCAP CT7343_19

PL20.36uH/30A LS2_1040

PR75 2.2PR81 5.11K,1% R0805 ns R0402

500mA

G

{8} B

45

SOFT

ISL6262A_0

PR27 R0402

44

NTC

7

PR20 R0603 6.04K,1% ns

10

VR_ON

6

PGND1 LAGTE1

1

500mA

S

PR26 R0402

46

500mA

VR_TT#

11

PR28 75K R0402

DPRSTP#

RBIAS

5

12

PC19 100pF/50V,NPO C0402

DPRSLPVR

4

10

PC31 3300pF/50V,X7R C0402

47

500mA

18

R0402 6.98K,1%

34

VSUM

PR25

PHASE1

VCC_OUT

1000pF/50V,X7R C0402

PMON

DFB

0.022uF/16V,X7R

PC21

3

17

CPU_GND

35

DROOP

PC22 C0402

UGATE1

PQ3 AOD448

0

PC83 1000pF/50V,X7R C0402

0.68uH/28A

1

1

PR29 10K R0402

PC20 1000pF/50V,X7R C0402

NTC

PSI#

RTN

PR30 470K,1% R0603

C0402 PC18 1000pF/50V,X7R

BOOT1

2

16

CPU_GND

C

{7} VR_PROCHOT#

PGOOD

36

15

PR24 147K,1% R0402

CPU_GND PR31 4.02K,1% R0402

48 3V3

PR23 0 R0402

1000pF/50V,X7R

ns PL1

PC84 0.1uF/25V,X7R C0603

1

PC30 C0402

PR22 0 R0402

PM_PSI#

SO8_50_150_PPAK

1

CPU_GND

{7}

PR74 10K

PC81 10uF/25V,X7R C1210

1

{23,33} IMVP_PWRGD

PMON1 TestP TPC60 ns

PC8 0.22uF/16V,X7R C0603 PR235 R0603

1

VSEN

ns

14

+V1.05S

CLK_EN#

PU1

PR21 100K R0402

{8}

AOL1426 S

H_VID0

PR18 2K R0402

4

PC80 10uF/25V,X7R C1210

1

1uF/10V,X7R

+V3.3S

500mA

G

PC34 C0603

CPU_GND

PC82 1uF/25V,Y5V C0805 ns

PQ23

2

{8}

D

2

{8}

H_VID1

3 2 1

{23} CK505_CLK_EN#

1

{8}

H_VID2

1

H_VID3

D

{7,12,22} H_DPRSTP#

1

R0402

{8}

5 6 7 8 9

470

H_VID4

+VDC

3A

1

PR14

{12,23} PM_DPRSLPVR

{8}

1

IMVP_ON

{8}

H_VID5

1

{33}

H_VID6

{6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,42,50,51} {19,20,21,23,24,25,30,31,32,33,38,42} {19,28,32,34,36,37,38,42,44} {8,40} {12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,42,50,51} {6,7,8,9,12,13,14,22,24,31,38,40,42,44}

1

D

+V3.3S +V5S +VDC +VCC_CORE +V3.3AL +V1.05S

+

4

+

5

56 56 56 56 56 56

R0402 R0402 R0402 R0402 R0402 R0402

ns ns ns ns ns ns

PR38 100K R0402 ns

J2 J6 J4 JOPEN JOPEN JOPEN RESISTOR_1 RESISTOR_1 RESISTOR_1 ns ns ns ns ns J3 J5 JOPEN JOPEN RESISTOR_1 RESISTOR_1

PR43 PQ9 10K 2N7002 ns R0402 SOT23 ns IMVP_PWRGD# 1 PR42 510K ns R0402

A

TOPSTAR TECHNOLOGY bent Page Name

+VCC_CORE

Size A3

M46G

Project Name

Rev B

Date: Thursday, August 27, 2009 Sheet 41 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

5

4

3

2

http://shop61976717.taobao.com http://shop61976717.taobao.com PR187 1K R0402

100mA 2

+VDC

D

1

PR178 100K R0402

3

9--19V

50mA

PQ55 DTB114EK SOT23

PC161 0.01uF/25V,X7R C0402

1

+VDC +V5S +V3.3S +V5AL +V3.3AL +V0.9S +V1.05S +V1.5S +V1.8

{19,28,32,34,36,37,38,41,44} {19,20,21,23,24,25,30,31,32,33,38,41} {6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,50,51} {19,24,29,32,36,37,39,40} {12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,50,51} {17,18,37} {6,7,8,9,12,13,14,22,24,31,38,40,41,44} {8,14,22,24,26,27,28,30,38,40} {12,13,14,15,16,37,40} D

+V3.3AL +V5AL

50mA

5 6 7 8

3 2

PR205 510K R0402

SOT23

3 2 1

PC172 0.1uF/25V,Y5V C0402

PC146 4.7uF/10V,Y5V C0805

V5S1 TestP TPC60 ns

PC165 0.1uF/25V,Y5V C0402

S

PR206 1K R0402

PR188 75K R0402

5A

V3_3S1 TestP TPC60 ns

G

EC

+V5S

PR195 51K R0402

1

MAIN_ON

4

S

{33}

G

PQ62 2N7002

+V3.3S PQ59 AO4468 SO8_50_150

D

D

MAIN_PWR_DN#

4

PD31 1N4148WS SOD323 1

PC257 4.7uF/10V,Y5V C0805 ns

5 6 7 8

5A

PQ52 SI4800BDY SO8_50_150

3 2 1

PR183 33K R0402

PR182 1K R0402

4A PC171 4.7uF/10V,Y5V C0805

M46G VerB:改用AO4468的2S SI4800,在第一版用AO4468时上电不正常--xie

C

C

2

2 PR143 100 R0402

PR144 100 R0402

PR141 510K R0402

1

PR158 100 R0402 ns

1

PR159 100 R0402 ns

+VDC

18mA

2

2 PR154 100 R0402

PR152 100 R0402

1

PR146 100 R0402 ns

+V0.9S

21mA

1

PR145 100 R0402 ns

1

1

1

PR148 100 R0402

+V1.05S

70mA 2

100mA

2

2

30mA PR147 100 R0402

+V3.3S

1

+V5S

2

+V1.5S

MAIN_PWR_DN#

1

3

PQ43 2N7002 SOT23

PQ46 2N7002 SOT23 ns

1 1

PQ40 2N7002 SOT23 1

3

3

PQ41 2N7002 SOT23 ns1

3

3

PQ42 2N7002 SOT23

B

DISCHG

2

2

2

2

2

2

B

PQ39 2N7002 SOT23 1

3

DISCHG

PR142 200K R0402

+V1.8

+VDC

2

2

36mA PR151 100 R0402

PR149 100 R0402

10K R0402

3

3

1 PQ44 2N7002 SOT23

1

V1_8DISCHG

A

TOPSTAR TECHNOLOGY

2

PR155

PR140 510K R0402

2

{23,26,33} PM_SLP_S4#

A

PQ48 2N7002 SOT23 1

1

V1_8DISCHG

bent

PR153 200K R0402

Page Name

SYSTEM/DISCHARGE

Size A3

M46G

Project Name

Rev B

Date: Thursday, August 27, 2009 Sheet 42 51 of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR 5

4

3

2

1

http://shop61976717.taobao.com http://shop61976717.taobao.com BATT+ +V5AL +V3.3AL +V3.3S

{34,35} {19,24,29,32,36,37,39,40,42} {12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51} {6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}

CHG_GND PU4 PR107

PC100 0.1uF/50V,Y5V C0603

PR89 {34,40} Isense_SYSN

20

DCIN

24

UGATE

17

CSIP

PR93 R0402

CSIN

PR91 R0402

PC109 5600pF/50V,Y5V C0603

ICOMP

ISL6251HAZ

BOOT

16

2.39V_Vref PR110 10.5K,1% R0402

设置适配器限流值为 82mV/25m ohm=3.28A.

0.643Vref

8

SYS_CURRENT 1A 4.2A 4.7A

13

CSOP

21

0

CHLIM

R0402

PQ24 AO4468 SO8_50_150

VREF

10

ACLIM

23

ACPRN

CSON

22

CELLS

4

ICM

7

GND

12

PD12 1N5819 SOD123

15uH/3.6A LS2_1040 PR213 2.2 R0805 ns

PC182 4.7uF/25V C1206

PC87 10uF/ 25V C1210 ns

PC92 1uF/25V,Y5V C0805

PC181 0.01uF/25V,X7R C0402 ns

2.2 R0402

1uF/10V,X7R C0603

CHG_GND PR103 SYS_I_Sense 100

PR111

PC89 BATT+ 0.1uF/25V,X7R 12.63V C0603

2A

1

PR92 PC99

R0402

PC112 3300pF/50V,X7R C0402

{33}

Layout note: Far away from critical signal trace

BOM:change to 0402

0 R0402

CHG_GND change to signal gnd By Johan 071224

PGND

4

EN

PR106 20K,1% R0402

SYS_I_Sense 400mV 1.67V 1.87V

14

1

0A 200mA 2A

PC227 0.1uF/10V,X7R C0402

LGATE

S

充电电流

9

phase

PR214

VADJ

G

0V 0.33V 3.3V

3

CHG_ON

18

PL3

D

SET_I

PHASE 11

Change from 10k to 6.98k PR104 10K R0402

SET_I

VCOMP

PR76 0.05,1% R2512

S

{33}

6

10K

3.3V

CHG_GND

{33}

0.01uF/25V,X7R

Add cap for emi By Johan 071228

PQ5 AO4468 SO8_50_150

VDDP

4

{34,40}

PC28 4.7uF/25V,X7R C1206

G

R0402

PC107 C0402

PC29 10uF/ 25V C1210 ns 070906VA：Co-lay。

0

PC101 1N4148WS/75V/150mA PR90 10K SOD323 R0402 0.1uF/50V,Y5V C0603 phase

SSOP24_25_150 PC111

PC10 0.1uF/25V,X7R C0603

0

PD11

5

PC33 1000pF/50V,X7R C0402

PD14 SOD323 1N4148WS/75V/150mA ns

D

C0402

Isense_SYSN

PC106 0.1uF/50V,Y5V C0603

VDD

R0402 PC108 1000pF/25V,X7R

1.5A

0 R0402

1

10

19

2

5 6 7 8

{32,34} Isense_SYSP

1

ACSET

3 2 1

PC110 1uF/10V,X7R C0603

CHG_GND

VDDP

5 6 7 8

PR108 5V_internal_LDO 4.7 R0402

15

3 2 1

VDDP

1

PC98 1uF/10V,X7R C0603

CHG_GND CHG_GND Change solution from OZ8602 to ISL6251

SYS_CURRENT >3.6A 1.8V