Philips Chassis
Colour Television Chassis Q552.4E LA Contents Page 1. 2. 3. 4. 5. 6. 7. 8. 9. Revision List 2 Technical Specs, Div
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Colour Television
Chassis
Q552.4E LA
Contents
Page
1. 2. 3. 4. 5. 6. 7. 8. 9.
Revision List 2 Technical Specs, Diversity, and Connections 2 Precautions, Notes, and Abbreviation List 7 Mechanical Instructions 11 Service Modes, Error Codes, and Fault Finding 20 Alignments 39 Circuit Descriptions 47 IC Data Sheets 53 Block Diagrams Drawing 69 Wiring diagram 4000 series 32" Wiring diagram 4000 series 37" 70 Wiring diagram 4000 series 42" 71 Wiring diagram 4000 series 47" 72 Wiring diagram 5000 & 5500 series 32" 73 Wiring diagram 5000 & 5500 series 40" 74 Wiring diagram 5000 & 5500 series 46" 75 Wiring diagram 5000 series 55" 76 Block Diagram Video 77 Block Diagram Audio 78 Block Diagram Control & Clock Signals 79 Block Diagram I2C 80 Supply Lines Overview 81 10. Circuit Diagrams and PWB Layouts Drawing A 715G5194 PSU 32" & 37" 3500/4000 series 82 A01 715G5246 PSU 42" 3500/4000 series 88 B 313912365313 SSB 93 B 313912365333 - 313912365334 SSB 130 J 272217190529 Sensor board 167 J 272217190532 Sensor board 169 J 715G5255 Sensor board 171 E 2722171 90545, 90547, 90549, 90552, 90558 Keyboard control panel 173 E 715G5252 Keyboard control panel 3500/4000 series 175 11. Styling Sheets Drawing 177 4000 series 32" 4000 series 37" 178 4000 series 42" 179 4000 series 47" 180 5000 series 32" 181 5000 series 40" 182 5000 series 46" 183 5000 series 55" 184
Published by ER/TY 1266 Quality
PWB 82-82 91-92 128-129 163-166 168 170 172 174 175
Printed in the Netherlands
Subject to modification
EN 3122 785 19222 2012-Jun-29
2012
©
TP Vision Netherlands B.V.
All rights reserved. Specifications are subject to change without notice. Trademarks are the property of Koninklijke Philips Electronics N.V. or their respective owners. TP Vision Netherlands B.V. reserves the right to change products at any time without being obliged to adjust earlier supplies accordingly. PHILIPS and the PHILIPS’ Shield Emblem are used under license from Koninklijke Philips Electronics N.V.
EN 2
1.
Revision List
Q552.4E LA
1. Revision List Manual xxxx xxx xxxx.0 • First release. Manual xxxx xxx xxxx.1 • Chapter 2: Table 2-1 updated (added CTNs). Manual xxxx xxx xxxx.2 • Chapter 4: added additional LVDS cable handling info; see section 4.4.2.
2. Technical Specs, Diversity, and Connections Index of this chapter: 2.1 Technical Specifications 2.2 Directions for Use 2.3 Connections 2.4 Chassis Overview
2.1
Technical Specifications For on-line product support please use the CTN links in Table 2-1. Here is product information available, as well as getting started, user manuals, frequently asked questions and software & drivers.
Notes: • Figures can deviate due to the different set executions. • Specifications are indicative (subject to change). Table 2-1 Described Model Numbers and Diversity
Styling
Sheet
Name
J (Sensor Board)
SSB
Supply lines
I2C
Audio
E (Keyboard/Leading Edge)
Block Diagrams
Power Supply
11
Schemat ics
Control & Clock
10
Assembly Removal
CTN
Wire Dressing Dressing
Connection Overview
Mechanics
9
Video
4
Wiring Diagram
2
32PFL4007H/12
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4007H/60
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4007K/12
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4007M/08
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4007T/12
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4007T/60
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4027H/12
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4027H/60
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4027K/12
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4027T/12
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4027T/60
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4037H/12
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4037H/60
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4037K/12
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4037T/12
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4037T/60
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL4047T/12
2.3
4-1
4.4
9.1
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.1
32PFL5007H/12
2.3
4-5
4.4
9.5
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.5
32PFL5007H/60
2.3
4-5
4.4
9.5
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.5
32PFL5007K/12
2.3
4-5
4.4
9.5
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.5
32PFL5007M/08
2.3
4-5
4.4
9.5
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.5
32PFL5007T/12
2.3
4-5
4.4
9.5
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.5
32PFL5007T/60
2.3
4-5
4.4
9.5
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.5
32PFL5507H/12
2.3
4-5
4.4
9.5
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.5
32PFL5507H/60
2.3
4-5
4.4
9.5
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.5
32PFL5507K/12
2.3
4-5
4.4
9.5
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.5
32PFL5507M/08
2.3
4-5
4.4
9.5
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.5
32PFL5507T/12
2.3
4-5
4.4
9.5
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.5
32PFL5507T/60
2.3
4-5
4.4
9.5
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.5
37PFL4007H/12
2.3
4-2
4.4
9.2
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.2
37PFL4007K/12
2.3
4-2
4.4
9.2
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.2
37PFL4007M/08
2.3
4-2
4.4
9.2
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.2
37PFL4007T/12
2.3
4-2
4.4
9.2
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.2
37PFL4007T/60
2.3
4-2
4.4
9.2
9.9
9.10
9.11
9.12
9.13
10.1
10.4
10.7
10.9
4000
11.2
2012-Jun-29
back to div. table
EN 3
Styling
Name
J (Sensor Board)
SSB
Supply lines
I2C
Audio
E (Keyboard/Leading Edge)
Block Diagrams
Power Supply
11
Schemat ics
Control & Clock
10
Assembly Removal
CTN
Wire Dressing Dressing
Connection Overview
Mechanics
2.
9
Video
4
Wiring Diagram
2
Q552.4E LA
Sheet
Technical Specs, Diversity, and Connections
40PFL5007H/12
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.6
40PFL5007H/60
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.6
40PFL5007K/12
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.6
40PFL5007M/08
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.6
40PFL5007T/12
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.6
40PFL5007T/60
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.6
40PFL5507H/12
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5507H/60
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5507K/12
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5507M/08
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5507T/12
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5507T/60
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5527H/12
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5527H/60
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5527K/12
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5527M/08
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5527T/12
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5527T/60
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5537H/12
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5537H/60
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5537K/12
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5537M/08
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5537T/12
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
40PFL5537T/60
2.3
4-6
4.4
9.6
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.6
42PFL4007H/12
2.3
4-3
4.4
9.3
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.3
42PFL4007K/12
2.3
4-3
4.4
9.3
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.3
42PFL4007M/08
2.3
4-3
4.4
9.3
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.3
42PFL4007T/12
2.3
4-3
4.4
9.3
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.3
42PFL4007T/60
2.3
4-3
4.4
9.3
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.3
42PFL4047T/12
2.3
4-3
4.4
9.3
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.3
42PFL4307H/12
2.3
4-3
4.4
9.3
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.3
42PFL4307K/12
2.3
4-3
4.4
9.3
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.3
42PFL4307T/12
2.3
4-3
4.4
9.3
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.3
42PFL4317K/12
2.3
4-3
4.4
9.3
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.3
46PFL5007H/12
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.7
46PFL5007K/12
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.7
46PFL5007M/08
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.7
46PFL5007T/12
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.4
10.5
10.8
5000
11.7
46PFL5507H/12
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5507H/60
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5507K/12
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5507M/08
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5507T/12
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5507T/60
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5527H/12
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5527H/60
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5527K/12
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5527M/08
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5527T/12
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5527T/60
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5537T/60
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5537H/12
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5537H/60
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5537K/12
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5537M/08
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
46PFL5537T/12
2.3
4-7
4.4
9.7
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.7
47PFL4007H/12
2.3
4-4
4.4
9.4
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.4
47PFL4007H/60
2.3
4-4
4.4
9.4
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.4
47PFL4007K/12
2.3
4-4
4.4
9.4
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.4
47PFL4007M/08
2.3
4-4
4.4
9.4
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.4
47PFL4007T/12
2.3
4-4
4.4
9.4
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.4
47PFL4007T/60
2.3
4-4
4.4
9.4
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.4
47PFL4037T/12
2.3
4-4
4.4
9.4
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.4
47PFL4047T/12
2.3
4-4
4.4
9.4
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.4
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2012-Jun-29
Technical Specs, Diversity, and Connections
2.2
Block Diagrams
Styling
Sheet
Name
J (Sensor Board)
SSB
Supply lines
E (Keyboard/Leading Edge)
11
Schemat ics
Power Supply
10
Assembly Removal
CTN
Wire Dressing Dressing
Connection Overview
Mechanics
9
I2C
4
Control & Clock
2
Audio
Q552.4E LA
Video
2.
Wiring Diagram
EN 4
47PFL4307H/12
2.3
4-4
4.4
9.4
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.4
47PFL4307K/12
2.3
4-4
4.4
9.4
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.4
47PFL4307T/12
2.3
4-4
4.4
9.4
9.9
9.10
9.11
9.12
9.13
10.2
10.4
10.7
10.9
4000
11.4
55PFL5507H/12
2.3
4-8
4.4
9.8
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.8
55PFL5507H/60
2.3
4-8
4.4
9.8
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.8
55PFL5507K/12
2.3
4-8
4.4
9.8
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.8
55PFL5507M/08
2.3
4-8
4.4
9.8
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.8
55PFL5507T/12
2.3
4-8
4.4
9.8
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.8
55PFL5507T/60
2.3
4-8
4.4
9.8
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.8
55PFL5527H/12
2.3
4-8
4.4
9.8
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.8
55PFL5527K/12
2.3
4-8
4.4
9.8
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.8
55PFL5527M/08
2.3
4-8
4.4
9.8
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.8
55PFL5527T/12
2.3
4-8
4.4
9.8
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.8
55PFL5537H/12
2.3
4-8
4.4
9.8
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.8
55PFL5537K/12
2.3
4-8
4.4
9.8
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.8
55PFL5537M/08
2.3
4-8
4.4
9.8
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.8
55PFL5537T/12
2.3
4-8
4.4
9.8
9.9
9.10
9.11
9.12
9.13
-
10.3
10.6
10.8
5000
11.8
Directions for Use You can download this information from the following websites: http://www.philips.com/support http://www.p4c.philips.com
2012-Jun-29
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Technical Specs, Diversity, and Connections 2.3
Q552.4E LA
2.
EN 5
Connections
REAR CONNECTORS
SIDE CONNECTORS CI
NETWORK
AUDIO IN AUDIO IN DVI/VGA
1
Y/Pb/Pr
Y/Pb/Pr
2
SERV.U
3
10
4
11 DIGITAL AUDIO OUT (OPTICAL)
12
BOTTOM REAR CONNECTORS USB 3
5
6
7
8
9 13
USB 2
HDMI SIDE VGA
SCART
(RGB/CVBS)
(3)
(2)
(1) ARC
75 Ω
14
USB 1
TV ANTENNA
HDMI
19220_007_120222.eps 120222
Figure 2-1 Connection overview Note: The following connector colour abbreviations are used (acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= Grey, Rd= Red, Wh= White, Ye= Yellow. 2.3.1
3 - Cinch: Video YPbPr - In, Audio - In Gn - Video Y 1 VPP / 75 ohm Bu - Video Pb 0.7 VPP / 75 ohm Rd - Video Pr 0.7 VPP / 75 ohm Rd - Audio - R 0.5 VRMS / 10 kohm Wh - Audio - L 0.5 VRMS / 10 kohm
Rear Connections
jq jq jq jq jq
1 - RJ45: Ethernet 4 - Service Connector (UART) 1 - Ground Gnd 2 - UART_TX Transmit 3 - UART_RX Receive 10000_025_090121.eps 120320
2.3.2
Figure 2-2 Ethernet connector 1 2 3 4 5 6 7 8
- TD+ - TD- RD+ - CT - CT - RD- GND - GND
Transmit signal Transmit signal Receive signal Centre Tap: DC level fixation Centre Tap: DC level fixation Receive signal Gnd Gnd
2 - Cinch: Audio - In (VGA/DVI) Rd - Audio R 0.5 VRMS / 10 kohm Wh - Audio L 0.5 VRMS / 10 kohm
H k j
Rear Connections - Bottom 5 - VGA: Video RGB - In 1
k k j
5 10
6
15
11
10000_002_090121.eps 090127
Figure 2-3 VGA Connector j H H
1 2 3 4 5 6
jq jq back to div. table
- Video Red - Video Green - Video Blue - n.c. - Ground - Ground Red
0.7 VPP / 75 ohm 0.7 VPP / 75 ohm 0.7 VPP / 75 ohm Gnd Gnd
j j j H H 2012-Jun-29
EN 6 7 8 9 10 11 12 13 14 15
2.
Q552.4E LA
- Ground Green - Ground Blue - +5VDC - Ground Sync - n.c. - DDC_SDA - H-sync - V-sync - DDC_SCL
Technical Specs, Diversity, and Connections
Gnd Gnd +5 V Gnd
H H j H
DDC data 0-5V 0-5V DDC clock
j j j j
8 - Aerial - In - - IEC-type (EU)
D
Coax, 75 ohm
9 - USB 1: USB2.0
1
2
3
4
10000_022_090121.eps 090121
Figure 2-6 USB (type A) 6 - SCART: Video RGB - In, CVBS - In, Audio - In 20
21
1 2 3 4
2
1
10000_001_090121.eps 090121
2.3.3
Figure 2-4 SCART connector 1 2 3 4 5 6 7 8
- n.c. - Audio R - n.c. - Ground Audio - Ground Blue - Audio L - Video Blue - Function Select
9 10 11 12 13 14 15 16
- Ground Green - n.c. - Video Green - n.c. - Ground Red - Ground P50 - Video Red - Status/FBL
17 18 19 20 21
- Ground Video - Ground FBL - n.c. - Video CVBS - Shield
0.5 VRMS / 10 kohm
j
Gnd Gnd 0.5 VRMS / 10 kohm 0.7 VPP / 75 ohm 0 - 2 V: INT 4.5 - 7 V: EXT 16:9 9.5 - 12 V: EXT 4:3 Gnd
H H j jk
0.7 VPP / 75 ohm
15 16 17 18 19 20
- DDC_SCL - DDC_SDA - Ground - +5V - HPD - Ground
2012-Jun-29
jk
11 - Head phone (Output) Bk - Head phone 32 - 600 ohm / 10 mW
j H j
1
2
3
4
10000_022_090121.eps 090121
H H j j H H
1 2 3 4
1 VPP / 75 ohm Gnd
j H
14 - HDMI SIDE: Digital Video, Digital Audio - In
Figure 2-7 USB (type A) - +5V - Data (-) - Data (+) - Ground
k jk jk H
Gnd
19 18
1 2
10000_017_090121.eps 090428
1 2
Hot Plug Detect Gnd
k
13 - USB 2, 3: USB2.0
Gnd Gnd 0.7 VPP / 75 ohm 0 - 0.4 V: INT 1 - 3 V: EXT / 75 ohm Gnd Gnd
Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Control channel Audio Return Channel (optional) DDC clock DDC data Gnd
ot
12 - Optical: S/PDIF - Out Bk - Coaxial Optical signal
Figure 2-8 HDMI (type A) connector 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Figure 2-5 HDMI (type A) connector - D2+ - Shield - D2- D1+ - Shield - D1- D0+ - Shield - D0- CLK+ - Shield - CLK- Easylink/CEC - ARC (optional)
Gnd
10 - Common Interface 68p - See diagram B05G 10-3-15
10000_017_090121.eps 090428
1 2 3 4 5 6 7 8 9 10 11 12 13 14
k jk jk H
Side Connections
7 - HDMI: Digital Video - In, Digital Audio with ARC - In/Out (optional) 19 18
- +5V - Data (-) - Data (+) - Ground
j H j j H j j H j j H j jk k j jk H j j H
2.4
- D2+ - Shield - D2- D1+ - Shield - D1- D0+ - Shield - D0- CLK+ - Shield - CLK- Easylink/CEC - n.c. - DDC_SCL - DDC_SDA - Ground - +5V - HPD - Ground
Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Control channel
j H j j H j j H j j H j jk
DDC clock DDC data Gnd
j jk H j j H
Hot Plug Detect Gnd
Chassis Overview Refer to chapter Block Diagrams for PWB/CBA locations.
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Precautions, Notes, and Abbreviation List
Q552.4E LA
3.
EN 7
3. Precautions, Notes, and Abbreviation List Index of this chapter: 3.1 Safety Instructions 3.2 Warnings 3.3 Notes 3.4 Abbreviation List
3.3.2
Schematic Notes •
•
3.1
Safety Instructions Safety regulations require the following during a repair: • Connect the set to the Mains/AC Power via an isolation transformer (> 800 VA). • Replace safety components, indicated by the symbol h, only by components identical to the original ones. Any other component substitution (other than original type) may increase risk of fire or electrical shock hazard.
• • • •
Safety regulations require that after a repair, the set must be returned in its original condition. Pay in particular attention to the following points: • Route the wire trees correctly and fix them with the mounted cable clamps. • Check the insulation of the Mains/AC Power lead for external damage. • Check the strain relief of the Mains/AC Power cord for proper function. • Check the electrical DC resistance between the Mains/AC Power plug and the secondary side (only for sets that have a Mains/AC Power isolated power supply): 1. Unplug the Mains/AC Power cord and connect a wire between the two pins of the Mains/AC Power plug. 2. Set the Mains/AC Power switch to the “on” position (keep the Mains/AC Power cord unplugged!). 3. Measure the resistance value between the pins of the Mains/AC Power plug and the metal shielding of the tuner or the aerial connection on the set. The reading should be between 4.5 M and 12 M. 4. Switch “off” the set, and remove the wire between the two pins of the Mains/AC Power plug. • Check the cabinet for defects, to prevent touching of any inner parts by the customer.
3.2
3.3.3
• • •
3.3.4
Notes
3.3.1
General •
•
BGA (Ball Grid Array) ICs Introduction For more information on how to handle BGA devices, visit this URL: http://www.atyourservice-magazine.com. Select “Magazine”, then go to “Repair downloads”. Here you will find Information on how to deal with BGA-ICs. BGA Temperature Profiles For BGA-ICs, you must use the correct temperature-profile. Where applicable and available, this profile is added to the IC Data Sheet information section in this manual.
3.3.5
Lead-free Soldering Due to lead-free technology some rules have to be respected by the workshop during a repair: • Use only lead-free soldering tin. If lead-free solder paste is required, please contact the manufacturer of your soldering equipment. In general, use of solder paste within workshops should be avoided because paste is not easy to store and to handle. • Use only adequate solder tools applicable for lead-free soldering tin. The solder tool must be able: – To reach a solder-tip temperature of at least 400°C. – To stabilize the adjusted temperature at the solder-tip. – To exchange solder-tips for different applications. • Adjust your solder tool so that a temperature of around 360°C - 380°C is reached and stabilized at the solder joint. Heating time of the solder-joint should not exceed ~ 4 sec. Avoid temperatures above 400°C, otherwise wear-out of tips will increase drastically and flux-fluid will be destroyed. To avoid wear-out of tips, switch “off” unused equipment or reduce heat. • Mix of lead-free soldering tin/parts with leaded soldering tin/parts is possible but PHILIPS recommends strongly to avoid mixed regimes. If this cannot be avoided, carefully clear the solder-joint from old tin and re-solder with new tin.
All ICs and many other semiconductors are susceptible to electrostatic discharges (ESD w). Careless handling during repair can reduce life drastically. Make sure that, during repair, you are connected with the same potential as the mass of the set by a wristband with resistance. Keep components and tools also at this same potential. Be careful during measurements in the high voltage section. Never replace modules or other components while the unit is switched “on”. When you align the set, use plastic rather than metal tools. This will prevent any short circuits and the danger of a circuit becoming unstable.
3.3
Spare Parts For the latest spare part overview, consult your Philips Spare Part web portal.
Warnings •
All resistor values are in ohms, and the value multiplier is often used to indicate the decimal point location (e.g. 2K2 indicates 2.2 k). Resistor values with no multiplier may be indicated with either an “E” or an “R” (e.g. 220E or 220R indicates 220 ). All capacitor values are given in micro-farads ( 10-6), nano-farads (n 10-9), or pico-farads (p 10-12). Capacitor values may also use the value multiplier as the decimal point indication (e.g. 2p2 indicates 2.2 pF). An “asterisk” (*) indicates component usage varies. Refer to the diversity tables for the correct values. The correct component values are listed on the Philips Spare Parts Web Portal.
Measure the voltages and waveforms with regard to the chassis (= tuner) ground (H), or hot ground (I), depending on the tested area of circuitry. The voltages and waveforms shown in the diagrams are indicative. Measure them in the Service Default Mode with a colour bar signal and stereo sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and picture carrier at 475.25 MHz for PAL, or 61.25 MHz for NTSC (channel 3). Where necessary, measure the waveforms and voltages with (D) and without (E) aerial signal. Measure the voltages in the power supply section both in normal operation (G) and in stand-by (F). These values are indicated by means of the appropriate symbols.
3.3.6
Alternative BOM identification It should be noted that on the European Service website, “Alternative BOM” is referred to as “Design variant”. The third digit in the serial number (example: AG2B0335000001) indicates the number of the alternative B.O.M. (Bill Of Materials) that has been used for producing the specific TV set. In general, it is possible that the same TV model on the market is produced with e.g. two different types of displays, coming from two different suppliers. This will then
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2012-Jun-29
EN 8
3.
Q552.4E LA
Precautions, Notes, and Abbreviation List
result in sets which have the same CTN (Commercial Type Number; e.g. 28PW9515/12) but which have a different B.O.M. number. By looking at the third digit of the serial number, one can identify which B.O.M. is used for the TV set he is working with. If the third digit of the serial number contains the number “1” (example: AG1B033500001), then the TV set has been manufactured according to B.O.M. number 1. If the third digit is a “2” (example: AG2B0335000001), then the set has been produced according to B.O.M. no. 2. This is important for ordering the correct spare parts! For the third digit, the numbers 1...9 and the characters A...Z can be used, so in total: 9 plus 26= 35 different B.O.M.s can be indicated by the third digit of the serial number.
AARA
ACI
ADC AFC
AGC Identification: The bottom line of a type plate gives a 14-digit serial number. Digits 1 and 2 refer to the production centre (e.g. SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M. code, digit 4 refers to the Service version change code, digits 5 and 6 refer to the production year, and digits 7 and 8 refer to production week (in example below it is 2010 week 10 / 2010 week 17). The 6 last digits contain the serial number.
AM AP AR ASF
ATSC
ATV Auto TV
AV AVC AVIP B/G BDS BLR BTSC
10000_053_110228.eps 110228
B-TXT C CEC
Figure 3-1 Serial number (example) 3.3.7
Board Level Repair (BLR) or Component Level Repair (CLR)
CL CLR ComPair CP CSM CTI
If a board is defective, consult your repair procedure to decide if the board has to be exchanged or if it should be repaired on component level. If your repair procedure says the board should be exchanged completely, do not solder on the defective board. Otherwise, it cannot be returned to the O.E.M. supplier for back charging! 3.3.8
•
•
3.4
CVBS
Practical Service Precautions
DAC DBE
It makes sense to avoid exposure to electrical shock. While some sources are expected to have a possible dangerous impact, others of quite high potential are of limited current and are sometimes held in less regard. Always respect voltages. While some may not be dangerous in themselves, they can cause unexpected reactions that are best avoided. Before reaching into a powered TV set, it is best to test the high voltage insulation. It is easy to do, and is a good service precaution.
DCM
DDC D/K DFI DFU DMR DMSD DNM
Abbreviation List 0/6/12
2012-Jun-29
SCART switch control signal on A/V board. 0 = loop through (AUX to TV),
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6 = play 16 : 9 format, 12 = play 4 : 3 format Automatic Aspect Ratio Adaptation: algorithm that adapts aspect ratio to remove horizontal black bars; keeps the original aspect ratio Automatic Channel Installation: algorithm that installs TV channels directly from a cable network by means of a predefined TXT page Analogue to Digital Converter Automatic Frequency Control: control signal used to tune to the correct frequency Automatic Gain Control: algorithm that controls the video input of the feature box Amplitude Modulation Asia Pacific Aspect Ratio: 4 by 3 or 16 by 9 Auto Screen Fit: algorithm that adapts aspect ratio to remove horizontal black bars without discarding video information Advanced Television Systems Committee, the digital TV standard in the USA See Auto TV A hardware and software control system that measures picture content, and adapts image parameters in a dynamic way External Audio Video Audio Video Controller Audio Video Input Processor Monochrome TV system. Sound carrier distance is 5.5 MHz Business Display Solutions (iTV) Board-Level Repair Broadcast Television Standard Committee. Multiplex FM stereo sound system, originating from the USA and used e.g. in LATAM and AP-NTSC countries Blue TeleteXT Centre channel (audio) Consumer Electronics Control bus: remote control bus on HDMI connections Constant Level: audio output to connect with an external amplifier Component Level Repair Computer aided rePair Connected Planet / Copy Protection Customer Service Mode Color Transient Improvement: manipulates steepness of chroma transients Composite Video Blanking and Synchronization Digital to Analogue Converter Dynamic Bass Enhancement: extra low frequency amplification Data Communication Module. Also referred to as System Card or Smartcard (for iTV). See “E-DDC” Monochrome TV system. Sound carrier distance is 6.5 MHz Dynamic Frame Insertion Directions For Use: owner's manual Digital Media Reader: card reader Digital Multi Standard Decoding Digital Natural Motion
Precautions, Notes, and Abbreviation List DNR DRAM DRM DSP DST
DTCP
DVB-C DVB-T DVD DVI(-d) E-DDC
EDID EEPROM EMI EPG EPLD EU EXT FDS FDW FLASH FM FPGA FTV Gb/s G-TXT H HD HDD HDCP
HDMI HP I I 2C I2D I2S IF IR IRQ ITU-656
Digital Noise Reduction: noise reduction feature of the set Dynamic RAM Digital Rights Management Digital Signal Processing Dealer Service Tool: special remote control designed for service technicians Digital Transmission Content Protection; A protocol for protecting digital audio/video content that is traversing a high speed serial bus, such as IEEE-1394 Digital Video Broadcast - Cable Digital Video Broadcast - Terrestrial Digital Versatile Disc Digital Visual Interface (d= digital only) Enhanced Display Data Channel (VESA standard for communication channel and display). Using E-DDC, the video source can read the EDID information form the display. Extended Display Identification Data (VESA standard) Electrically Erasable and Programmable Read Only Memory Electro Magnetic Interference Electronic Program Guide Erasable Programmable Logic Device Europe EXTernal (source), entering the set by SCART or by cinches (jacks) Full Dual Screen (same as FDW) Full Dual Window (same as FDS) FLASH memory Field Memory or Frequency Modulation Field-Programmable Gate Array Flat TeleVision Giga bits per second Green TeleteXT H_sync to the module High Definition Hard Disk Drive High-bandwidth Digital Content Protection: A “key” encoded into the HDMI/DVI signal that prevents video data piracy. If a source is HDCP coded and connected via HDMI/DVI without the proper HDCP decoding, the picture is put into a “snow vision” mode or changed to a low resolution. For normal content distribution the source and the display device must be enabled for HDCP “software key” decoding. High Definition Multimedia Interface HeadPhone Monochrome TV system. Sound carrier distance is 6.0 MHz Inter IC bus Inter IC Data bus Inter IC Sound bus Intermediate Frequency Infra Red Interrupt Request The ITU Radio communication Sector (ITU-R) is a standards body subcommittee of the International Telecommunication Union relating to radio communication. ITU-656 (a.k.a. SDI), is a digitized video format used for broadcast grade video. Uncompressed digital component or digital composite signals can be used.
iTV LS
LATAM LCD LED L/L'
LPL LS LVDS Mbps M/N MHEG
MIPS
MOP MOSFET MPEG MPIF MUTE MTV NC NICAM
NTC NTSC
NVM O/C OSD OAD
OTC P50 PAL
PCB PCM back to div. table
Q552.4E LA
3.
EN 9
The SDI signal is self-synchronizing, uses 8 bit or 10 bit data words, and has a maximum data rate of 270 Mbit/s, with a minimum bandwidth of 135 MHz. Institutional TeleVision; TV sets for hotels, hospitals etc. Last Status; The settings last chosen by the customer and read and stored in RAM or in the NVM. They are called at start-up of the set to configure it according to the customer's preferences Latin America Liquid Crystal Display Light Emitting Diode Monochrome TV system. Sound carrier distance is 6.5 MHz. L' is Band I, L is all bands except for Band I LG.Philips LCD (supplier) Loudspeaker Low Voltage Differential Signalling Mega bits per second Monochrome TV system. Sound carrier distance is 4.5 MHz Part of a set of international standards related to the presentation of multimedia information, standardised by the Multimedia and Hypermedia Experts Group. It is commonly used as a language to describe interactive television services Microprocessor without Interlocked Pipeline-Stages; A RISC-based microprocessor Matrix Output Processor Metal Oxide Silicon Field Effect Transistor, switching device Motion Pictures Experts Group Multi Platform InterFace MUTE Line Mainstream TV: TV-mode with Consumer TV features enabled (iTV) Not Connected Near Instantaneous Compounded Audio Multiplexing. This is a digital sound system, mainly used in Europe. Negative Temperature Coefficient, non-linear resistor National Television Standard Committee. Color system mainly used in North America and Japan. Color carrier NTSC M/N= 3.579545 MHz, NTSC 4.43= 4.433619 MHz (this is a VCR norm, it is not transmitted off-air) Non-Volatile Memory: IC containing TV related data such as alignments Open Circuit On Screen Display Over the Air Download. Method of software upgrade via RF transmission. Upgrade software is broadcasted in TS with TV channels. On screen display Teletext and Control; also called Artistic (SAA5800) Project 50: communication protocol between TV and peripherals Phase Alternating Line. Color system mainly used in West Europe (colour carrier = 4.433619 MHz) and South America (colour carrier PAL M = 3.575612 MHz and PAL N = 3.582056 MHz) Printed Circuit Board (same as “PWB”) Pulse Code Modulation 2012-Jun-29
EN 10
3.
PDP PFC PIP PLL
POD
POR PSDL PSL PSLS
PTC PWB PWM QRC QTNR QVCP RAM RGB
RC RC5 / RC6 RESET ROM RSDS R-TXT SAM S/C SCART
SCL SCL-F SD SDA SDA-F SDI SDRAM SECAM
SIF SMPS SoC SOG SOPS SPI
S/PDIF SRAM SRP SSB SSC STB STBY SVGA SVHS SW
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Precautions, Notes, and Abbreviation List
Plasma Display Panel Power Factor Corrector (or Preconditioner) Picture In Picture Phase Locked Loop. Used for e.g. FST tuning systems. The customer can give directly the desired frequency Point Of Deployment: a removable CAM module, implementing the CA system for a host (e.g. a TV-set) Power On Reset, signal to reset the uP Power Supply for Direct view LED backlight with 2D-dimming Power Supply with integrated LED drivers Power Supply with integrated LED drivers with added Scanning functionality Positive Temperature Coefficient, non-linear resistor Printed Wiring Board (same as “PCB”) Pulse Width Modulation Quasi Resonant Converter Quality Temporal Noise Reduction Quality Video Composition Processor Random Access Memory Red, Green, and Blue. The primary color signals for TV. By mixing levels of R, G, and B, all colors (Y/C) are reproduced. Remote Control Signal protocol from the remote control receiver RESET signal Read Only Memory Reduced Swing Differential Signalling data interface Red TeleteXT Service Alignment Mode Short Circuit Syndicat des Constructeurs d'Appareils Radiorécepteurs et Téléviseurs Serial Clock I2C CLock Signal on Fast I2C bus Standard Definition Serial Data I2C DAta Signal on Fast I2C bus Serial Digital Interface, see “ITU-656” Synchronous DRAM SEequence Couleur Avec Mémoire. Colour system mainly used in France and East Europe. Colour carriers = 4.406250 MHz and 4.250000 MHz Sound Intermediate Frequency Switched Mode Power Supply System on Chip Sync On Green Self Oscillating Power Supply Serial Peripheral Interface bus; a 4wire synchronous serial data link standard Sony Philips Digital InterFace Static RAM Service Reference Protocol Small Signal Board Spread Spectrum Clocking, used to reduce the effects of EMI Set Top Box STand-BY 800 × 600 (4:3) Super Video Home System Software
SWAN SXGA TFT THD TMDS TS TXT TXT-DW UI uP UXGA V VESA VGA VL VSB WYSIWYR
WXGA XTAL XGA Y Y/C YPbPr
YUV
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Spatial temporal Weighted Averaging Noise reduction 1280 × 1024 Thin Film Transistor Total Harmonic Distortion Transmission Minimized Differential Signalling Transport Stream TeleteXT Dual Window with TeleteXT User Interface Microprocessor 1600 × 1200 (4:3) V-sync to the module Video Electronics Standards Association 640 × 480 (4:3) Variable Level out: processed audio output toward external amplifier Vestigial Side Band; modulation method What You See Is What You Record: record selection that follows main picture and sound 1280 × 768 (15:9) Quartz crystal 1024 × 768 (4:3) Luminance signal Luminance (Y) and Chrominance (C) signal Component video. Luminance and scaled color difference signals (B-Y and R-Y) Component video
Mechanical Instructions
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4.
EN 11
4. Mechanical Instructions Index of this chapter: 4.1 Cable Dressing 4000 Styling (xxPFL4xx7x/xx series) 4.2 Cable Dressing 5000 styling (xxPFL5xx7x/xx series) 4.3 Service Positions 4.4 Assy/Panel Removal 4.5 Set Re-assembly
4.1
Notes: •
Figures below can deviate slightly from the actual situation, due to the different set executions.
Cable Dressing 4000 Styling (xxPFL4xx7x/xx series)
19220_009_120223.eps 120223
Figure 4-1 Cable dressing 32PFL4xx7x/xx
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EN 12
4.
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Mechanical Instructions
19220_010_120223.eps 120223
Figure 4-2 Cable dressing 37PFL4xx7x/xx
19220_011_120223.eps 120223
Figure 4-3 Cable dressing 42PFL4xx7x/xx
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Mechanical Instructions
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4.
EN 13
19220_012_120223.eps 120223
Figure 4-4 Cable dressing 47PFL4xx7x/xx
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EN 14 4.2
4.
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Mechanical Instructions
Cable Dressing 5000 styling (xxPFL5xx7x/xx series)
3 × tape (150 m.m.) 11 × tape (100 m.m.) 3 × clamp 1 × adhesive saddle 19220_014_120223.eps 120223
Figure 4-5 Cable dressing 32PFL5xx7x/xx
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Mechanical Instructions
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4.
EN 15
4 × tape (150 m.m.) 11 × tape (100 m.m.) 1 × adhesive clamp 19220_015_120223.eps 120223
Figure 4-6 Cable dressing 40PFL5xx7x/xx
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EN 16
4.
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Mechanical Instructions
2 × tape (200 m.m.) 2 × tape (150 m.m.) 10 × tape (100 m.m.) 6 × tape (80 m.m.) 3 × tape (50 m.m.) 2 × clamp 19220_016_120223.eps 120223
Figure 4-7 Cable dressing 46PFL5xx7x/xx
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Mechanical Instructions
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EN 17
19220_083_120229.eps 120229
Figure 4-8 Cable dressing 55PFL5xx7x/xx
4.3
Service Positions For easy servicing of a TV set, the set should be put face down on a soft flat surface, foam buffers or other specific workshop tools. Ensure that a stable situation is created to perform measurements and alignments. When using foam bars take care that these always support the cabinet and never only the display. Caution: Failure to follow these guidelines can seriously damage the display! Ensure that ESD safe measures are taken.
4.4
Assy/Panel Removal Instructions below apply to the 32PFL5507K/12, but will be similar for other models.
4.4.1
1
Rear Cover Warning: Disconnect the mains power cord before removing the rear cover. Attention: Before lifting the rear cover, unplug the Keyboard Control connector [1], as indicated in Figure 4-9.
19220_066_120229.eps 120229
Figure 4-9 Rear cover removal
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EN 18 4.4.2
4.
Mechanical Instructions
Q552.4E LA
Small Signal Board (SSB) Caution: it is mandatory to remount all different screws at their original position during re-assembly. Failure to do so may result in damaging the SSB.
3
ATTENTION! The LVDS connector(s) require(s) a special procedure for disconnecting. Refer to Figure 4-10 to Figure 4-13 for clarification. 1. Press the catches [1] simultaneously. 2. Slide the LVDS cable sidewards carefully [2]. Failure to pressing the catches leads to a damaged LVDS cable [3]! Any LVDS cable that is damaged at the notch area must be replaced with a new one to avoid future unnecessary repair actions.
LVDS CABLE
19220_068_120229.eps 120229
Figure 4-12 LVDS cable - damaged notch area [3]
1
Upon re-connecting the LVDS cable, ensure the catches are locked after having inserted the LVDS cable.
LVDS CABLE
2
Click!
1 19220_067_120229.eps 120229
Figure 4-10 LVDS connector - correct handling
LVDS flat foil
Click!
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Figure 4-13 SSB LVDS - catch locking 4.4.3
19054_001_111010.eps 111010
IR/LED panel 1. Unlock the catches at both sides. 2. Flip the board upside-down. 3. Unlock the cable from the connector. When defective, replace the whole unit.
Figure 4-11 Unlocking LVDS connector
4.4.4
Keyboard Control Panel The keyboard control panel is located in the rear cover. When defective, replace the whole unit.
4.4.5
LCD Panel Refer to Figure 4-14 for details. 1. Remove the SSB as described earlier. 2. Remove the PSU. 3. Remove the stand. 4. Remove the stand bracket. 5. Remove the mains plug together with its subframe. 6. Remove the woofer. 7. Remove the IR/LED panel as earlier described. 8. Remove the WiFi module.
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Mechanical Instructions 4.5
9. Remove the speakers together with their subframes. 10. Remove all remaining boards and cables that do not belong to the LCD panel. 11. Remove the rims [1] and [2] at both sides of the set. 12. Lift the LCD panel from the bezel. When defective, replace the whole unit.
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EN 19
Set Re-assembly To re-assemble the whole set, execute all processes in reverse order. Notes: • While re-assembling, make sure that all cables are placed and connected in their original position. • Pay special attention not to damage the EMC foams in the set. Ensure that EMC foams are mounted correctly.
2
1 19220_069_120229.eps 120229
Figure 4-14 LCD panel removal
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EN 20
5.
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Service Modes, Error Codes, and Fault Finding
5. Service Modes, Error Codes, and Fault Finding Index of this chapter: 5.1 Test Points 5.2 Service Modes 5.3 Stepwise Start-up 5.4 Service Tools 5.5 Error Codes 5.6 The Blinking LED Procedure 5.7 Protections 5.8 Fault Finding and Repair Tips 5.9 Software Upgrading
5.1
– –
How to Activate SDM For this chassis there are two kinds of SDM: an analogue SDM and a digital SDM. Tuning will happen according Table 5-1. • Analogue SDM: use the standard RC-transmitter and key in the code “062596”, directly followed by the “MENU” (or “HOME”) button. Note: It is possible that, together with the SDM, the main menu will appear. To switch it “off”, push the “MENU” (or "HOME") button again. Analogue SDM can also be activated by grounding for a moment the solder path on the SSB, with the indication “SDM” (see Service mode pad). • Digital SDM: use the standard RC-transmitter and key in the code “062593”, directly followed by the “MENU” (or "HOME") button. Note: It is possible that, together with the SDM, the main menu will appear. To switch it “off”, push the “MENU” (or "HOME") button again.
Test Points As most signals are digital, it will be difficult to measure waveforms with a standard oscilloscope. However, several key ICs are capable of generating test patterns, which can be controlled via ComPair. In this way it is possible to determine which part is defective. Perform measurements under the following conditions: • Service Default Mode. • Video: Colour bar signal. • Audio: 3 kHz left, 1 kHz right.
5.2
Automatic volume levelling (AVL). Skip/blank of non-favourite pre-sets.
Service Modes Service Default mode (SDM) and Service Alignment Mode (SAM) offers several features for the service technician, while the Customer Service Mode (CSM) is used for communication between the call centre and the customer.
SDM
This chassis also offers the option of using ComPair, a hardware interface between a computer and the TV chassis. It offers the abilities of structured troubleshooting, error code reading, and software version read-out for all chassis. (see also section “5.4.1 ComPair”). 19220_070_120229.eps 120229
Note: For the new model range, a new remote control (RC) is used with some renamed buttons. This has an impact on the activation of the Service modes. For instance the old “MENU” button is now called “HOME” (or is indicated by a “house” icon). 5.2.1
Figure 5-1 Service mode pad After activating this mode, “SDM” will appear in the upper right corner of the screen (when a picture is available).
Service Default Mode (SDM) How to Navigate When the “MENU” (or “HOME”) button is pressed on the RC transmitter, the TV set will toggle between the SDM and the normal user menu.
Purpose • To create a pre-defined setting, to get the same measurement results as given in this manual. • To override software protections detected by stand-by processor and make the TV start up to the step just before protection (a sort of automatic stepwise start-up). See section “5.3 Stepwise Start-up”. • To start the blinking LED procedure where only LAYER 2 errors are displayed. (see also section “5.5 Error Codes”).
How to Exit SDM Use one of the following methods: • Switch the set to STAND-BY via the RC-transmitter. • Via a standard customer RC-transmitter: key in “00”sequence.
Specifications
5.2.2
Table 5-1 SDM default settings Region
Freq. (MHz)
Default system
Europe, AP(PAL/Multi)
475.25
PAL B/G
Europe, AP DVB-T
546.00 PID Video: 0B DVB-T 06 PID PCR: 0B 06 PID Audio: 0B 07
• • •
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Service Alignment Mode (SAM) Purpose • To perform (software) alignments. • To change option settings. • To easily identify the used software version. • To view operation hours. • To display (or clear) the error code buffer. How to Activate SAM Via a standard RC transmitter: Key in the code “062596” directly followed by the “INFO” or “OK” button. After activating SAM with this method a service warning will appear on the screen, continue by pressing the “OK” button on the RC.
All picture settings at 50% (brightness, colour, contrast). Sound volume at 25%. All service-unfriendly modes (if present) are disabled, like: – (Sleep) timer. – Child/parental lock. – Picture mute (blue mute or black mute).
Contents of SAM • Hardware Info.
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Service Modes, Error Codes, and Fault Finding
5.
EN 21
–
•
•
•
• • •
•
A. SW Version. Displays the software version of the main software (example: Q555X-1.2.3.4 = AAAAB_X.Y.W.Z). • AAAA= the chassis name. • B= the software branch version. This is a sequential number (this is no longer the region indication, as the software is now multi-region). • X.Y.W.Z= the software version, where X is the main version number (different numbers are not compatible with one another) and Y.W.Z is the sub version number (a higher number is always compatible with a lower number). – B. STBY PROC Version. Displays the software version of the stand-by processor. – C. Production Code. Displays the production code of the TV, this is the serial number as printed on the back of the TV set. Note that if an NVM is replaced or is initialized after corruption, this production code has to be re-written to NVM. ComPair will foresee in a possibility to do this. Operation Hours. Displays the accumulated total of operation hours (not the stand-by hours). Every time the TV is switched “on/off”, 0.5 hours is added to this number. Errors (followed by maximum 10 errors). The most recent error is displayed at the upper left (for an error explanation see section “5.5 Error Codes”). Reset Error Buffer. When “cursor right” (or “OK” button) pressed here, followed by the “OK” button, the error buffer is reset. Alignments. This will activate the “ALIGNMENTS” submenu. See Chapter 6. Alignments. Dealer Options. Extra features for the dealers. Options. Extra features for Service. For more info regarding option codes, see chapter 6. Alignments. Note that if the option code numbers are changed, these have to be confirmed with pressing the “OK” button before the options are stored, otherwise changes will be lost. Initialize NVM. The moment the processor recognizes a corrupted NVM, the “initialize NVM” line will be highlighted. Now, two things can be done (dependent of the service instructions at that moment): – Save the content of the NVM via ComPair for development analysis, before initializing. This will give the Service department an extra possibility for diagnosis (e.g. when Development asks for this). – Initialize the NVM.
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Display option code
19220_075_120229.eps 120229
Figure 5-2 Location of Display Option Code sticker •
•
•
• •
•
Note: When the NVM is corrupted, or replaced, there is a high possibility that no picture appears because the display code is not correct. So, before initializing the NVM via the SAM, a picture is necessary and therefore the correct display option has to be entered. Refer to Chapter 6. Alignments for details. To adapt this option, it’s advised to use ComPair (the correct values for the options can be found in Chapter 6. Alignments) or a method via a standard RC (described below). Changing the display option via a standard RC: Key in the code “062598” directly followed by the “MENU” (or "HOME") button and “XXX” (where XXX is the 3 digit decimal display code as mentioned on the sticker in the set). Make sure to key in all three digits, also the leading zero’s. If the above action is successful, the front LED will go out as an indication that the RC sequence was correct. After the display option is changed in the NVM, the TV will go to the Stand-by mode. If the NVM was corrupted or empty before this action, it will be initialized first (loaded with default values). This initializing can take up to 20 seconds.
•
•
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Store - go right. All options and alignments are stored when pressing “cursor right” (or the “OK” button) and then the “OK”-button. Operation hours display. Displays the accumulated total of operation hours of the screen itself. In case of a display replacement, reset to “0” or to the consumed operation hours of the spare display. SW Maintenance. – SW Events. In case of specific software problems, the development department can ask for this info. – HW Events. In case of specific software problems, the development department can ask for this info : - Event 26: refers to a power dip, this is logged after the TV set reboots due to a power dip. - Event 17: refers to the power OK status, sensed even before the 3 x retry to generate the error code. Test settings. For development purposes only. Development file versions. Not useful for Service purposes, this information is only used by the development department. Upload to USB. To upload several settings from the TV to an USB stick, which is connected to the SSB. The items are “Channel list”, “Personal settings”, “Option codes”, “Alignments”, “Identification data” (includes the set type and prod code + all 12NC like SSB, display, boards), “History list”. The “All” item supports to upload all several items at once. First a directory “repair\” has to be created in the root of the USB stick. To upload the settings, select each item separately, press “cursor right” (or the “OK” button), confirm with “OK” and wait until the message “Done” appears. In case the download to the USB stick was not successful, “Failure” will be displayed. In this case, check if the USB stick is connected properly and if the directory “repair” is present in the root of the USB stick. Now the settings are stored onto the USB stick and can be used to download into another TV or other SSB. Uploading is of course only possible if the software is running and preferably a picture is available. This method is created to be able to save the customer’s TV settings and to store them into another SSB. Download from USB. To download several settings from the USB stick to the TV, same way of working needs to be followed as described in “Upload to USB”. To make sure that the download of the channel list from USB to the TV is executed properly, it is necessary to restart the TV and tune to a valid preset if necessary. The “All” item supports to download all several items at once. NVM editor. For NET TV the set “type number” must be entered correctly. Also the production code (AG code) can be entered here via the RC-transmitter. Correct data can be found on the side/rear sticker.
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Service Modes, Error Codes, and Fault Finding
How to Navigate • In SAM, the menu items can be selected with the “CURSOR UP/DOWN” key on the RC-transmitter. The selected item will be highlighted. When not all menu items fit on the screen, move the “CURSOR UP/DOWN” key to display the next/previous menu items. • With the “CURSOR LEFT/RIGHT” keys, it is possible to: – (De) activate the selected menu item. – (De) activate the selected sub menu. • With the “OK” key, it is possible to activate the selected action.
How to Navigate By means of the “CURSOR-DOWN/UP” knob on the RCtransmitter, can be navigated through the menus. Contents of CSM The contents are reduced to 3 pages: General, Software versions and Quality items. The group names itself are not shown anywhere in the CSM menu. General • Set Type. This information is very helpful for a helpdesk/ workshop as reference for further diagnosis. In this way, it is not necessary for the customer to look at the rear of the TV-set. Note that if an NVM is replaced or is initialized after corruption, this set type has to be re-written to NVM. ComPair will foresee in a possibility to do this. The update can also be done via the NVM editor available in SAM. • Production Code. Displays the production code (the serial number) of the TV. Note that if an NVM is replaced or is initialized after corruption, this production code has to be re-written to NVM. ComPair will foresee in a possibility to do this. The update can also be done via the NVM editor available in SAM. • Installed date. Indicates the date of the first installation of the TV. This date is acquired via time extraction. • Options 1. Gives the option codes of option group 1 as set in SAM (Service Alignment Mode). • Options 2. Gives the option codes of option group 2 as set in SAM (Service Alignment Mode). • 12NC SSB. Gives an identification of the SSB as stored in NVM. Note that if an NVM is replaced or is initialized after corruption, this identification number has to be re-written to NVM. ComPair will foresee in a possibility to do this. This identification number is the 12nc number of the SSB. • 12NC display. Shows the 12NC of the display. • 12NC supply. Shows the 12NC of the power supply. • 12NC 200Hz board. Shows the 12NC of the 200Hz Panel (when present). • 12NC AV PIP. Shows the 12NC of the AV PIP board (when present).
How to Exit SAM Use one of the following methods: • Switch the TV set to STAND-BY via the RC-transmitter. • Via a standard RC-transmitter, key in “00” sequence, or select the “BACK” key. 5.2.3
Customer Service Mode (CSM) Purpose When a customer is having problems with his TV-set, he can call his dealer or the Customer Helpdesk. The service technician can then ask the customer to activate the CSM, in order to identify the status of the set. Now, the service technician can judge the severity of the complaint. In many cases, he can advise the customer how to solve the problem, or he can decide if it is necessary to visit the customer. The CSM is a read only mode; therefore, modifications in this mode are not possible. When in this chassis CSM is activated, a test pattern will be displayed during 5 seconds (1 second Blue, 1 second Green and 1 second Red, then again 1 second Blue and 1 second Green). This test pattern is generated by the PNX51X0 (located on the 200Hz board as part of the display). So if this test pattern is shown, it could be determined that the back end video chain (PNX51X0 and display) is working.For TV sets without the PNX51X0 inside, every menu from CSM will be used as check for the back end chain video. When CSM is activated and there is a USB stick connected to the TV set, the software will dump the CSM content to the USB stick. The file (CSM_model number_serial number.txt) will be saved in the root of the USB stick. This info can be handy if no information is displayed.
Software versions • Current main SW. Displays the build-in main software version. In case of field problems related to software, software can be upgraded. As this software is consumer upgradeable, it will also be published on the Internet. Example: Q55xx1.2.3.4 • Stand-by SW. Displays the build-in stand-by processor software version. Upgrading this software will be possible via ComPair or via USB (see section 5.9 Software Upgrading). Example: STDBY_83.84.0.0. • e-UM version. Displays the electronic user manual software-version (12NC version number). Most significant number here is the last digit. • FPGA software.
When in CSM mode (and a USB stick connected), pressing “OK” will create an extended CSM dump file on the USB stick. This file (Extended_CSM_model number_serial number.txt) contains: • The normal CSM dump information, • All items (from SAM “load to USB”, but in readable format), • Operating hours, • Error codes, • Software/Hardware event logs. To have fast feedback from the field, a flashdump can be requested by development. When in CSM, push the “red” button and key in serial digits ‘2679’ (same keys to form the word ‘COPY’ with a cellphone). A file “Dump_model number_serial number.bin” will be written on the connected USB device. This can take 1/2 minute, depending on the quantity of data that needs to be dumped.
Quality items • Signal quality. Bad / average /good (not for DVB-S). • Ethernet MAC address. Displays the MAC address present in the SSB. • Wireless MAC address. Displays the wireless MAC address to support the Wi-Fi functionality. • BDS key. Indicates if the set is in the BDS status. • CI module. Displays status if the common interface module is detected. • CI + protected service. Yes/No. • Event counter : S : 000X 0000(number of software recoveries : SW EVENT-LOG #(reboots) S : 0000 000X (number of software events : SW EVENTLOG #(events) H : 000X 0000(number of hardware errors)
Also when CSM is activated, the LAYER 1 error is displayed via blinking LED. Only the latest error is displayed (see also section 5.5 Error Codes). How to Activate CSM Key in the code “123654” via the standard RC transmitter. Note: Activation of the CSM is only possible if there is no (user) menu on the screen! 2012-Jun-29
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Service Modes, Error Codes, and Fault Finding H : 0000 000X (number of hardware events : SW EVENTLOG #(events).
EN 23
The abbreviations “SP” and “MP” in the figures stand for: • SP: protection or error detected by the Stand-by Processor. • MP: protection or error detected by the MIPS Main Processor.
Stepwise Start-up When the TV is in a protection state due to an error detected by stand-by software (error blinking is displayed) and SDM is activated via shortcutting the SDM solder path on the SSB, the TV starts up until it reaches the situation just before protection. So, this is a kind of automatic stepwise start-up. In combination with the start-up diagrams below, you can see which supplies are present at a certain moment. Caution: in case the start-up in this mode with a faulty FET 7U0X (diagram B02A) is done,
Mains off
Mains on
- WakeUp requested - Acquisition needed - Tact switch pushed
St by
5.
you can destroy all IC’s supplied by the +1V8 and +1V1, due to overvoltage (12V on XVX-line). It is recommended to measure first the FET 7U0X or others FET’s on shortcircuit before activating SDM via the service pads.
How to Exit CSM Press “MENU” (or "HOME") / “Back” key on the RC-transmitter.
5.3
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WakeUp requested
Semi St by
- stby requested and no data Acquisition required
Active - St by requested - tact SW pushed
Tact switch pushed
Hibernate
WakeUp requested (SDM)
- Tact switch pushed - last status is hibernate after mains ON
GoToProtection GoToProtection
Protection
18770_250_100216.eps 100402
Figure 5-3 Transition diagram
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EN 24
5.
Service Modes, Error Codes, and Fault Finding
Q552.4E LA
Off Stand by or Protection
Mains is applied
Standby Supply starts running. All standby supply voltages become available.
st-by µP resets
Initialise I/O pins of the st-by µP: - Switch reset-AVC LOW (reset state) - Switch reset-system LOW (reset state) - Switch reset-Ethernet LOW (reset state) - Switch reset-USB LOW (reset state) - Switch reset-DVBs LOW (reset state) - keep Audio-reset and Audio-Mute-Up HIGH - Switch CTRL-DISP3 LOW(2D mode) - Switch BL-DIM LOW - Switch BL-I-CTRL LOW
If the protection state was left by short circuiting the SDM pins, detection of a protection condition during startup will stall the startup. Protection conditions in a playing set will be ignored. The protection mode will not be entered.
start keyboard scanning, RC detection. Wake up reasons are off.
- Switch Audio-Reset high. It is low in the standby mode if the standby mode lasted longer than 10s.
Switch ON Platform and display supply by switching LOW the Standby line.
+12V, +24Vs, AL and Bolt-on power is switched on, followed by the +1V2 DCDC converter Detect2 is moved to an interrupt. The detection is on interrupt base now Detect2 high received within 2 seconds?
Yes
No
12V error: Layer1: 3 Layer2: 16
Enter protection
Enable the DCDC converters (ENABLE-3V3n LOW)
Wait 50ms
Enable the supply detection algorithm
Set I²C slave address of Standby µP to (A0h)
Detect EJTAG debug probe (pulling pin of the probe interface to ground by inserting EJTAG probe)
EJTAG probe connected ?
An EJTAG probe (e.g. WindPower ICE probe) can be connected for Linux Kernel debugging purposes.
Yes
No No
No
Cold boot?
Yes Release AVC system reset Feed warm boot script
Release AVC system reset Feed cold boot script
Release AVC system reset Feed initializing boot script disable alive mechanism
19220_071_120229.eps 120229
Figure 5-4 “Off” to “Semi Stand-by” flowchart (part 1)
2012-Jun-29
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Service Modes, Error Codes, and Fault Finding
This cannot be done through the bootscript, the I/O is on the standby µP
Q552.4E LA
Reset-system is switched HIGH by the AVC at the end of the bootscript
Reset-system is switched HIGH by the AVC at the end of the bootscript
AVC releases Reset-Ethernet, Reset-USB and Reset-DVBs when the end of the AVC bootscript is detected
AVC releases Reset-Ethernet, Reset-USB and Reset-DVBs when the end of the AVC bootscript is detected
Reset-Audio and Audio-Mute-Up are switched by MIPS code later on in the startup process
Reset-Audio and Audio-Mute-Up are switched by MIPS code later on in the startup process
Wake up reason coldboot & not semistandby?
No
EN 25
Startup screen shall only be visible when there is a coldboot to an active state end situation. The startup screen shall not be visible when waking up for reboot reasons or waking up to semi-standby conditions or waking up to enter Hibernate mode.
yes
No
Timing need to be updated if more mature info is available.
5.
Startup screen cfg file present? The first time after the option turn on of the startup screen or when the set is virgin, the config file is not present and hence the startup screen will not be shown. Yes
Bootscript ready in 1250 ms?
No
Yes
85500 sends out startup screen
Set I²C slave address of Standby µP to (60h) 85500 & FPGA start up the display. RPC start (comm. protocol) Startup screen visible Flash to Ram image transfer succeeded within 30s?
No Code = Layer1: 2 Layer2: 15
See the Semi-standby to On description for the detailed display startup sequence. During the complete display time of the Startup screen, the preheat condition of 100% PWM is valid.
Yes
Code = Layer1: 2 Layer2: 53
Switch AVC PNX85500 in reset (active low)
Wait 10ms
No
SW initialization succeeded within 20s?
Yes
Enable Alive check mechanism Disable all supply related protections and switch off the +3V3 +5V DC/DC converter. MIPS reads the wake up reason from standby µP.
Wait until AVC starts to communicate
Wait 5ms
3-th try?
switch off the remaining DC/DC converters
Initialize audio
Switch Standby I/O line high and wait 4 seconds
Initialize tuner and channel decoders
Yes Blink Code as error code
Enter protection
Initialize source selection
Initialize video processing IC's - local contrast FPGA - 5120's, 21/9 scaler and MPC if present
initialize AutoTV by triggering CHS AutoTV Init interface
Initialize Ambilight with Lights off.
Semi-Standby 19220_072_120229.eps 120229
Figure 5-5 “Off” to “Semi Stand-by” flowchart (part 2)
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2012-Jun-29
EN 26
5.
Q552.4E LA
Service Modes, Error Codes, and Fault Finding
The assumption here is that a fast toggle (SEMI ->ON. In these states, the AVC is still active and can provide the 2s delay. A transition ON->SEMI->STBY->SEMI->ON cannot be made in less than 2s, because the standby state will be maintained for at least 4s. CPipe already generates a valid output clock in the semi-standby state: display startup can start immediately when leaving the semi-standby state.
Semi Standby Wait until previous on-state is left more than 2 seconds ago. (to prevent LCD display problems) Assert RGB video blanking and audio mute
Display already on? (splash screen)
Yes
No Send display startup and shutdown targets to FPGA Switch on the display power by switching LCD-PWR-ONn low Wait x ms
The exact timings to switch on the display (LVDS delay, lamp delay) are defined in the display file.
Switch on LVDS output in the 85500
Switch Off LCD Backlight
Switch on the display By sending I2C “Display_On” command to FPGA
Initialize audio and video processing IC's and functions according needed use case.
Wait 10ms(tbc)
Set BL-DIM & BL-I-CTRL according to Display file (For Splash Screen, fix BL-DIM at high[100%], BL-I-CTRL at low[0%]) Wait 10ms(tbc)
Delay BL-ON with the sum of LVDS delay and the Lamp delay indicated in the display file
Switch on LCD backlight (BL-ON)
Start POK line detection algorithm
Wait until valid and stable audio and video, corresponding to the requested output is delivered by the AVC Switch Audio-Reset low and wait 5ms Release audio mute and wait 100ms before any other audio handling is done (e.g. volume change)
return
unblank the video. Switch on the Ambilight functionality according the last status settings. Startup screen Option and Installation setting Photoscreen ON? Yes Display cfg file present and up to date, according correct display option? No Yes
No
Prepare Start screen Display config file and copy to Flash
Active 19220_074_120229.eps 120229
Figure 5-6 “Semi Stand-by” to “Active” flowchart
2012-Jun-29
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Service Modes, Error Codes, and Fault Finding
Q552.4E LA
5.
EN 27
Active Mute all sound outputs via softmute
Wait 100ms
Set main amplifier mute (I/O: audio-mute)
Force ext audio outputs to ground (I/O: audio reset) And wait 5ms
Switch off POK line detection algorithm
switch off LCD backlight
switch off Ambilight
Mute all video outputs Wait until Ambilight has faded out: Output power Observer should be zero
CTRL-DISP3=high? (3D mode?)
Yes Switch CTRL-DISP3 to LOW
No
Wait x ms (display file)
The exact timings to switch off the display (LVDS delay, BL-ON delay) are defined in the display file.
Switch off the display by sending I2C “Display_Off” command to FPGA
Switch off LVDS output in 85500
Wait x ms
Switch off the display power by switching LCD-PWR-ONn high
Semi Standby 19220_073_120229.eps 120229
Figure 5-7 “Active” to “Semi Stand-by” flowchart
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2012-Jun-29
EN 28
5.
Q552.4E LA
Service Modes, Error Codes, and Fault Finding
Semi Stand by
If ambientlight functionality was used in semi-standby (lampadaire mode), switch off ambient light (see CHS ambilight)
Delay transition until ramping down of ambient light is finished. *)
*) If this is not performed and the set is switched to standby when the switch off of the ambilights is still ongoing, the lights will switch off abruptly when the supply is cut.
transfer Wake up reasons to the Stand by µP.
Switch Memories to self-refresh (this creates a more stable condition when switching off the power).
Switch AVC system in reset state (reset-system and reset-AVC lines) Switch reset-USB, Reset-Ethernet and Reset-DVBs LOW
Wait 10ms
Disable all supply related protections and switch off the DC/DC converters (ENABLE-3V3n)
Wait 5ms
Switch OFF all supplies by switching HIGH the Standby I/O line
Important remarks: release reset audio 10 sec after entering standby to save power Also here, the standby state has to be maintained for at least 4s before starting another state transition.
Stand by 18770_256_100216.eps 100216
Figure 5-8 “Semi Stand-by” to “Stand-by” flowchart
2012-Jun-29
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Service Modes, Error Codes, and Fault Finding 5.4
Service Tools
5.5
Error Codes
5.4.1
ComPair
5.5.1
Introduction
Introduction ComPair (Computer Aided Repair) is a Service tool for Philips Consumer Electronics products. and offers the following: 1. ComPair helps to quickly get an understanding on how to repair the chassis in a short and effective way. 2. ComPair allows very detailed diagnostics and is therefore capable of accurately indicating problem areas. No knowledge on I2C or UART commands is necessary, because ComPair takes care of this. 3. ComPair speeds up the repair time since it can automatically communicate with the chassis (when the µP is working) and all repair information is directly available. 4. ComPair features TV software up possibilities.
• •
How to Connect This is described in the chassis fault finding database in ComPair.
•
TO TV
ComPair II RC in
RC out
•
TO UART SERVICE CONNECTOR
•
Multi function
Optional Power Link/ Mode Switch Activity
I2C
EN 29
New in this chassis is the way errors can be displayed:
•
TO I2C SERVICE CONNECTOR
5.
The error code buffer contains all detected errors since the last time the buffer was erased. The buffer is written from left to right, new errors are logged at the left side, and all other errors shift one position to the right. When an error occurs, it is added to the list of errors, provided the list is not full. When an error occurs and the error buffer is full, then the new error is not added, and the error buffer stays intact (history is maintained). To prevent that an occasional error stays in the list forever, the error is removed from the list after more than 50 hrs. of operation. When multiple errors occur (errors occurred within a short time span), there is a high probability that there is some relation between them.
Specifications ComPair consists of a Windows based fault finding program and an interface box between PC and the (defective) product. The ComPair II interface box is connected to the PC via an USB cable. For the TV chassis, the ComPair interface box and the TV communicate via a bi-directional cable via the service connector(s). The ComPair fault finding program is able to determine the problem of the defective television, by a combination of automatic diagnostics and an interactive question/answer procedure.
TO UART SERVICE CONNECTOR
Q552.4E LA
•
RS232 /UART
If no errors are there, the LED should not blink at all in CSM or SDM. No spacer must be displayed as well. There is a simple blinking LED procedure for board level repair (home repair) so called LAYER 1 errors next to the existing errors which are LAYER 2 errors (see Table 5-2). – LAYER 1 errors are one digit errors. – LAYER 2 errors are 2 digit errors. In protection mode. – From consumer mode: LAYER 1. – From SDM mode: LAYER 2. Fatal errors, if I2C bus is blocked and the set reboots, CSM and SAM are not selectable. – From consumer mode: LAYER 1. – From SDM mode: LAYER 2. In CSM mode. – When entering CSM: error LAYER 1 will be displayed by blinking LED. Only the latest error is shown. In SDM mode. – When SDM is entered via Remote Control code or the hardware pins, LAYER 2 is displayed via blinking LED. Error display on screen. – In CSM no error codes are displayed on screen. – In SAM the complete error list is shown.
PC
Basically there are three kinds of errors: • Errors detected by the Stand-by software which lead to protection. These errors will always lead to protection and an automatic start of the blinking LED LAYER 1 error. (see section “5.6 The Blinking LED Procedure”). • Errors detected by the Stand-by software which not lead to protection. In this case the front LED should blink the involved error. See also section “5.5 Error Codes, 5.5.4 Error Buffer”. Note that it can take up several minutes before the TV starts blinking the error (e.g. LAYER 1 error = 2, LAYER 2 error = 15 or 53). • Errors detected by main software (MIPS). In this case the error will be logged into the error buffer and can be read out via ComPair, via blinking LED method LAYER 1-2 error, or in case picture is visible, via SAM.
ComPair II Developed by Philips Brugge
HDMI I2C only
Optional power 5V DC
10000_036_090121.eps 091118
Figure 5-9 ComPair II interface connection Caution: It is compulsory to connect the TV to the PC as shown in the picture above (with the ComPair interface in between), as the ComPair interface acts as a level shifter. If one connects the TV directly to the PC (via UART), ICs can be blown!
5.5.2
How to Read the Error Buffer Use one of the following methods: • On screen via the SAM (only when a picture is visible). E.g.: – 00 00 00 00 00: No errors detected – 23 00 00 00 00: Error code 23 is the last and only detected error. – 37 23 00 00 00: Error code 23 was first detected and error code 37 is the last detected error. – Note that no protection errors can be logged in the error buffer.
How to Order ComPair II order codes: • ComPair II interface: 3122 785 91020. • Software is available via the Philips Service web portal. • ComPair UART interface cable for Q55x.x. (using 3.5 mm Mini Jack connector): 3138 188 75051. Note: When you encounter problems, contact your local support desk. back to div. table
2012-Jun-29
EN 30 • • 5.5.3
5.
Service Modes, Error Codes, and Fault Finding
Q552.4E LA
Via the blinking LED procedure. See section 5.5.3 How to Clear the Error Buffer. Via ComPair.
content, as this history can give significant information). This to ensure that old error codes are no longer present. If possible, check the entire contents of the error buffer. In some situations, an error code is only the result of another error code and not the actual cause (e.g. a fault in the protection detection circuitry can also lead to a protection). There are several mechanisms of error detection: • Via error bits in the status registers of ICs. • Via polling on I/O pins going to the stand-by processor. • Via sensing of analog values on the stand-by processor or the PNX8550. • Via a “not acknowledge” of an I2C communication.
How to Clear the Error Buffer Use one of the following methods: • By activation of the “RESET ERROR BUFFER” command in the SAM menu. • If the content of the error buffer has not changed for 50+ hours, it resets automatically.
5.5.4
Error Buffer
Take notice that some errors need several minutes before they start blinking or before they will be logged. So in case of problems wait 2 minutes from start-up onwards, and then check if the front LED is blinking or if an error is logged.
In case of non-intermittent faults, clear the error buffer before starting to repair (before clearing the buffer, write down the Table 5-2 Error code overview
Description
Layer 1
Layer 2
Monitored by
Error/ Prot
Error Buffer/ Blinking LED
Device
Defective Board
I2C3
2
13
MIPS
E
BL / EB
SSB
SSB
I2C2
2
14
MIPS
E
BL / EB
SSB
SSB
I2C4
2
18
MIPS
E
BL / EB
SSB
SSB
PNX doesn’t boot (HW cause)
2
15
Stby µP
P
BL
SSB
SSB
12V
3
16
Stby µP
P
BL
/
Supply
Inverter or display supply
3
17
MIPS
E
EB
/
Supply
HDMI mux
2
23
MIPS
E
EB
Sil9x87A
SSB
I2C switch
2
24
MIPS
E
EB
PCA9540
AV-PIP board
8
25
MIPS
E
EB
SSB AV PIP board
Channel dec DVB-C
2
27
MIPS
E
EB
TDA10024
SSB
Channel dec
2
27
MIPS
E
EB
TC90157
SSB
Channel dec DVBT2
2
27
MIPS
E
EB
CXD2820
SSB
Channel DVB-S
2
28
MIPS
E
EB
STV0903
SSB
14v/18v OLP LNB controller
2
32
MIPS
E
EB
LNB controller R3
2
31
MIPS
E
EB
LNBH 23
SSB
LNB controller R4
2
31
MIPS
E
EB
LNBH 25
SSB
Tuner1
2
34
Stby µP
P
EB
DTT71300
SSB
main NVM
2
35
MIPS
E
x
STM24C64
SSB
SSB
Tuner DVB-S
2
36
MIPS
E
EB
STV6110
SSB
Class-D
2
37
MIPS
E
EB
TAS5711PHP
SSB
FPGA backlight
2
38
MIPS
E
EB
LX 4
SSB
Temperature sensor LED driver/TCON
7
42
MIPS
E
EB
LM 75
Temperature sensor
Temperature sensor SSB/set
2
42
MIPS
E
EB
LM 75
FAN
7
43
MIPS
E
EB
Temperature sensor FAN
FPGA PQ
2
45
MIPS
E
EB
LX 25
SSB
MIPS doesn’t boot (SW cause)
2
53
Stby µP
P
BL
PNX8550
SSB
Extra Info • Rebooting. When a TV is constantly rebooting due to internal problems, most of the time no errors will be logged or blinked. This rebooting can be recognized via a ComPair interface and Hyperterminal (for Hyperterminal settings, see section “5.8 Fault Finding and Repair Tips, 5.8.6 Logging). It’s shown that the loggings which are generated by the main software keep continuing. In this case diagnose has to be done via ComPair. • Error 13 (I2C bus 3, SSB bus blocked). Current situation: when this error occurs, the TV will constantly reboot due to the blocked bus. The best way for further diagnosis here, is to use ComPair. • Error 14 (I2C bus 2, TV set bus blocked). Current situation: when this error occurs, the TV will constantly reboot due to the blocked bus. The best way for further diagnosis here, is to use ComPair. • Error 18 (I2C bus 4, Tuner bus blocked). In case this bus is blocked, short the “SDM” solder paths on the SSB during startup, LAYER error 2 = 18 will be blinked. • Error 15 (PNX8550 doesn’t boot). Indicates that the main processor was not able to read his bootscript. This error will point to a hardware problem around the PNX8550 (supplies not OK, PNX 8550 completely dead, I2C link between PNX and Stand-by Processor broken, etc...). 2012-Jun-29
•
•
•
•
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When error 15 occurs it is also possible that I2C1 bus is blocked (NVM). I2C1 can be indicated in the schematics as follows: SCL-UP-MIPS, SDA-UP-MIPS. Other root causes for this error can be due to hardware problems regarding the DDR’s and the bootscript reading from the PNX8550. Error 16 (12V). This voltage is made in the power supply and results in protection (LAYER 1 error = 3) in case of absence. When SDM is activated we see blinking LED LAYER 2 error = 16. Error 17 (Invertor or Display Supply). Here the status of the “Power OK” is checked by software, no protection will occur during failure of the invertor or display supply (no picture), only error logging. LED blinking of LAYER 1 error = 3 in CSM, in SDM this gives LAYER 2 error = 17. Error 23 (HDMI). When there is no I2C communication towards the HDMI mux after start-up, LAYER 2 error = 23 will be logged and displayed via the blinking LED procedure if SDM is switched on. Error 24 (I2C switch). When there is no I2C communication towards the I2C switch, LAYER 2 error = 24 will be logged and displayed via the blinking LED procedure when SDM is switched on. Remark: this only works for TV sets with an I2C controlled screen included.
Service Modes, Error Codes, and Fault Finding •
•
•
•
•
•
• •
Error 28 (Channel dec DVB-S). When there is no I2C communication towards the DVB-S channel decoder, LAYER 2 error = 28 will be logged and displayed via the blinking LED procedure if SDM is switched on. Error 31 (Lnb controller). When there is no I2C communication towards this device, LAYER 2 error = 31 will be logged and displayed via the blinking LED procedure if SDM is activated. Error 34 (Tuner). When there is no I2C communication towards the tuner during start-up, LAYER 2 error = 34 will be logged and displayed via the blinking LED procedure when SDM is switched on. Error 35 (main NVM). When there is no I2C communication towards the main NVM during start-up, LAYER 2 error = 35 will be displayed via the blinking LED procedure when SDM is switched “on”. All service modes (CSM, SAM and SDM) are accessible during this failure, observed in the Uart logging as follows: ">> PFPOW_.C: First Error (id19, Layer_1= 2 Layer_= 35)". Error 36 (Tuner DVB-S). When there is no I2C communication towards the DVB-S tuner during start-up, LAYER 2 error = 36 will be logged and displayed via the blinking LED procedure when SDM is switched “on”. Error 37 (Class-D amplifier). When there is no I2C communication towards the TAS5731PHP Class-D Amplifier during start-up, LAYER 2 error = 37 will be logged and displayed via the blinking LED procedure when SDM is switched “on”. Note: TV in normal working condition, but without Audio out from speaker. Error 42 (Temp sensor). Only applicable for TV sets equipped with temperature devices. Error 53. This error will indicate that the PNX8550 has read his bootscript (when this would have failed, error 15 would blink) but initialization was never completed because of hardware problems (NAND flash, ...) or software initialization problems. Possible cause could be that there is no valid software loaded (try to upgrade to the latest main software version). Note that it can take a few minutes before the TV starts blinking LAYER 1 error = 2 or in SDM, LAYER 2 error = 53.
5.6
The Blinking LED Procedure
5.6.1
Introduction
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5.
EN 31
5. When all the error codes are displayed, the sequence finishes with a LED blink of 3 s (spacer). 6. The sequence starts again. Example: Error 12 8 6 0 0. After activation of the SDM, the front LED will show: 1. One long blink of 750 ms (which is an indication of the decimal digit) followed by a pause of 1.5 s 2. Two short blinks of 250 ms followed by a pause of 3 s 3. Eight short blinks followed by a pause of 3 s 4. Six short blinks followed by a pause of 3 s 5. One long blink of 3 s to finish the sequence (spacer). 6. The sequence starts again. 5.6.2
How to Activate Use one of the following methods: • Activate the CSM. The blinking front LED will show only the latest layer 1 error, this works in “normal operation” mode or automatically when the error/protection is monitored by the Stand-by processor. In case no picture is shown and there is no LED blinking, read the logging to detect whether “error devices” are mentioned. (see section “5.8 Fault Finding and Repair Tips, 5.8.6 Logging”). • Activate the SDM. The blinking front LED will show the entire content of the LAYER 2 error buffer, this works in “normal operation” mode or when SDM (via hardware pins) is activated when the tv set is in protection.
5.7
Protections
5.7.1
Software Protections Most of the protections and errors use either the stand-by microprocessor or the MIPS controller as detection device. Since in these cases, checking of observers, polling of ADCs, and filtering of input values are all heavily software based, these protections are referred to as software protections. There are several types of software related protections, solving a variety of fault conditions: • Related to supplies: presence of the +5V, +3V3 and 1V2 needs to be measured, no protection triggered here. • Protections related to breakdown of the safety check mechanism. E.g. since the protection detections are done by means of software, failing of the software will have to initiate a protection mode since safety cannot be guaranteed any more.
The blinking LED procedure can be split up into two situations: • Blinking LED procedure LAYER 1 error. In this case the error is automatically blinked when the TV is put in CSM. This will be only one digit error, namely the one that is referring to the defective board (see table “5-2 Error code overview”) which causes the failure of the TV. This approach will especially be used for home repair and call centres. The aim here is to have service diagnosis from a distance. • Blinking LED procedure LAYER 2 error. Via this procedure, the contents of the error buffer can be made visible via the front LED. In this case the error contains 2 digits (see table “5-2 Error code overview”) and will be displayed when SDM (hardware pins) is activated. This is especially useful for fault finding and gives more details regarding the failure of the defective board. Important remark: For an empty error buffer, the LED should not blink at all in CSM or SDM. No spacer will be displayed.
Remark on the Supply Errors The detection of a supply dip or supply loss during the normal playing of the set does not lead to a protection, but to a cold reboot of the set. If the supply is still missing after the reboot, the TV will go to protection. Protections during Start-up During TV start-up, some voltages and IC observers are actively monitored to be able to optimise the start-up speed, and to assure good operation of all components. If these monitors do not respond in a defined way, this indicates a malfunction of the system and leads to a protection. As the observers are only used during start-up, they are described in the start-up flow in detail (see section “5.3 Stepwise Start-up”). 5.7.2
When one of the blinking LED procedures is activated, the front LED will show (blink) the contents of the error buffer. Error codes greater then 10 are shown as follows: 1. “n” long blinks (where “n” = 1 to 9) indicating decimal digit 2. A pause of 1.5 s 3. “n” short blinks (where “n”= 1 to 9) 4. A pause of approximately 3 s,
Hardware Protections The only real hardware protection in this chassis appears in case of an audio problem e.g. DC voltage on the speakers. This protection will only affect the Class D audio amplifier (item 7D60; see diagram B06A) and puts the amplifier in a continuous burst mode (cyclus approximately 2 seconds).
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2012-Jun-29
EN 32
5.
Q552.4E LA
Service Modes, Error Codes, and Fault Finding
Repair Tip • There still will be a picture available but no sound. While the Class D amplifier tries to start-up again, the cone of the loudspeakers will move slowly in one or the other direction until the initial failure shuts the amplifier down, this cyclus starts over and over again. The headphone amplifier will also behaves similar.
5.8
+3V3-STANDY (3V3 nominal) is the permanent voltage, supplying the Stand-by microprocessor inside PNX855xx. Supply voltage +1V1 is started immediately when +12V voltage becomes available (+12V is enabled by STANDBY signal when "low"). Supply voltages +3V3, +2V5, +1V8, +1V2 and +5V-TUN are switched "on" by signal ENABLE-3V3 when "low", provided that +12V (detected via 7U40 and 7U41) is present.
Fault Finding and Repair Tips
+12V is considered OK (=> DETECT2 signal becomes "high", +12V to +1V8, +12V to +3V3, +12V to +5V DC-DC converter can be started up) if it rises above 10V and doesn’t drop below 9V5. A small delay of a few milliseconds is introduced between the start-up of 12V to +1V8 DC-DC converter and the two other DC-DC converters via 7U48 and associated components.
Read also section “5.5 Error Codes, 5.5.4 Error Buffer, Extra Info”. 5.8.1
Audio Amplifier The Class D-IC 7D60 has a powerpad for cooling. When the IC is replaced it must be ensured that the powerpad is very well pushed to the PWB while the solder is still liquid. This is needed to insure that the cooling is guaranteed, otherwise the Class DIC could break down in short time.
5.8.2
Description DVB-S2: • LNB-RF1 (0V = disabled, 14V or 18V in normal operation) LNB supply generated via the second conversion channel of 7TP2 (diagram B03B) LNB supply control IC. It provides supply voltage that feeds the outdoor satellite reception equipment. • +3V3-DVBS (3V3 nominal), +2V5-DVBS (2V5 nominal) and +1V-DVBS (1.03V nominal) power supply for the silicon tuner and channel decoder. +1V-DVBS is generated via a 5V to 1V DC-DC converter and is stabilized at the point of load (channel decoder) by means of feedback signal SENSE+1V0-DVBS. +3V3-DVBS and +2V5-DVBS are generated via linear stabilizers from +5V-DVBS that by itself is generated via the first conversion channel of 7TP2.
AV PIP To check the AV PIP board (if present) functionality, a dedicated tespattern can be invoke as follows: select the “multiview” icon in the User Interface and press the “OK” button. Apply for the main picture an extended source, e.g. HDMI input. Proceed by entering CSM (push ‘123654’ on the remote control) and press the yellow button. A coloured testpattern should appear now, generated by the AV PIP board (this can take a few seconds).
5.8.3
At start-up, +24V becomes available when STANDBY signal is "low" (together with +12V for the basic board), when +3V3 from the basic board is present the two DC-DC converters channels inside 7TP2 are activated. Initially only the 24V to 5V converter (channel 1 of 7TP2 generating +5V-DVBS) will effectively work, while +V-LNB is held at a level around 11V7 via diode 6TP5.
CSM When CSM is activated and there is a USB stick connected to the TV, the software will dump the complete CSM content to the USB stick. The file (Csm.txt) will be saved in the root of the USB stick. If this mechanism works it can be concluded that a large part of the operating system is already working (MIPS, USB...)
5.8.4
If +24V drops below +15V level then the DVB-S2 supply will stop, even if +3V3 is still present.
DC/DC Converter Note: +24V audio is used in 4000 series, 4300 & 5000 series use +12V audio.
Description basic board The basic board power supply consists of 4 DC/DC converters and 5 linear stabilizers. All DC/DC converters have +12V input voltage and deliver: • +1V1 supply voltage (1.15V nominal), for the core voltage of PNX855xx, stabilized close to the point of load; SENSE+1V1 signal provides the DC-DC converter the needed feedback to achieve this. • +1V8 supply voltage, for the DDR2 memories and DDR2 interface of PNX855xx. • +3V3 supply voltage (3.30V nominal), overall 3.3 V for onboard IC’s, for non-5000 series SSB diversities only. • +5V (5.15V nominal) for USB, WIFI and Conditional Access Module and +5V5-TUN for +5V-TUN tuner stabilizer.
Debugging The best way to find a failure in the DC/DC converters is to check their start-up sequence at power “on” via the mains cord, presuming that the stand-by microprocessor and the external supply are operational. Take STANDBY signal "high"-to-"low" transition as time reference. When +12V becomes available (maximum 1 second after STANDBY signal goes "low") then +1V1 is started immediately. After ENABLE-3V3 goes "low", all the other supply voltages should rise within a few milliseconds. Tips • Behaviour comparison with a reference TV550 platform can be a fast way to locate failures. • If +12V stays "low", check the integrity of fuse 1U40. • Check the integrity (at least no short circuit between drain and source) of the power MOS-FETs before starting up the platform in SDM, otherwise many components might be damaged. Using a ohmmeter can detect short circuits between any power rail and ground or between +12V and any other power rail. • Short circuit at the output of an integrated linear stabilizer (7UC0) will heat up this device strongly. • Switching frequencies should be 500 kHz ...600 kHz for 12 V to 1.1 V and 12 V to 1.8 V DC-DC converters, 900 kHz for 12 V to 3.3 V and 12 V to 5 V DC-DC converters. The DVB-S2 supply 24 V to 5 V and 24 V to +V LNB DC-DC converters operates at 300 kHz while for 5 V to 1.1 V DC-DC converter 900 kHz is used.
The linear stabilizers are providing: • +1V2 supply voltage (1.2V nominal), stabilized close to PNX855xx device, for various other internal blocks of PNX855xx; SENSE+1V2 signal provides the needed feedback to achieve this. • +2V5 supply voltage (2.5V nominal), for LVDS interface and various other internal blocks of PNX855xx. Stabilizer 7UC0 is used (diagram B02B). • +3V3 supply voltage (3V3 nominal), is provided by 7UD1 (diagram B02C); the 12 V to 3V3 DC-DC converter delivers the supply voltage to the PNX855xx. • +5V-TUN supply voltage (5V nominal) for tuner and IF amplifier.
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Service Modes, Error Codes, and Fault Finding 5.8.5
Exit “Factory Mode”
EN 33
Some failures are indicated by error codes in the logging, check with error codes table (see Table “5-2 Error code overview”).e.g. => PLFPOW_MERR.C : First Error (id=10,Layer_1=2,Layer_2=23). • I2C bus error mentioned as e.g.: “ I2C bus 4 blocked”. • Not all failures or error messages should be interpreted as fault.For instance root cause can be due to wrong option codes settings => e.g. “DVBS2Suppoprted : False/True. In the Uart log startup script we can observe and check the enabled loaded option codes.
Logging
Defective sectors (bad blocks) in the Nand Flash can also be reported in the logging.
When something is wrong with the TV set (f.i. the set is rebooting) you can check for more information via the logging in Hyperterminal. The Hyperterminal is available in every Windows application via Programs, Accessories, Communications, Hyperterminal. Connect a “ComPair UART”cable (3138 188 75051) from the service connector in the TV to the “multi function” jack at the front of ComPair II box. Required settings in ComPair before starting to log: - Start up the ComPair application. - Select the correct database (open file “Q55X.X”, this will set the ComPair interface in the appropriate mode). - Close ComPair After start-up of the Hyperterminal, fill in a name (f.i. “logging”) in the “Connection Description” box, then apply the following settings: 1. COMx 2. Bits per second = 115200 3. Data bits = 8 4. Parity = none 5. Stop bits = 1 6. Flow control = none During the start-up of the TV set, the logging will be displayed. This is also the case during rebooting of the TV set (the same logging appears time after time). Also available in the logging is the “Display Option Code” (useful when there is no picture), look for item “DisplayRawNumber” in the beginning of the logging. Tip: when there is no picture available during rebooting you are able to check for “error devices” in the logging (LAYER 2 error) which can be very helpful to determine the failure cause of the reboot. For protection state, there is no logging. 5.8.7
5.
•
When an “F” is displayed in the screen’s right corner, this means the set is in “Factory” mode, and it normally happens after a new SSB is mounted. To exit this mode, push the “VOLUME minus” button on the TV’s local keyboard for 10 seconds (this disables the continuous mode). Then push the “SOURCE” button for 10 seconds until the “F” disappears from the screen. 5.8.6
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Startup in the software upgrade application and observe the Uart logging: Starting up the TV set in the Manual Software Upgrade mode will show access to USB, meant to copy software content from USB to the DRAM.Progress is shown in the logging as follows: “cosupgstdcmds_mcmdwritepart: Programming 102400 bytes, 40505344 of 40607744 bytes programmed”. Startup in Jett Mode: Check Uart logging in Jet mode mentioned as : “JETT UART READY”. Uart logging changing preset: => COMMAND: calling DFB source = RC6, system=0, key = 4”.
5.8.8
Loudspeakers Make sure that the volume is set to minimum during disconnecting the speakers in the ON-state of the TV. The audio amplifier can be damaged by disconnecting the speakers during ON-state of the set!
5.8.9
PSL In case of no picture when CSM (test pattern) is activated and backlight doesn’t light up, it’s recommended first to check the inverter on the PSL + wiring (LAYER 2 error = 17 is displayed in SDM).
Guidelines Uart logging 5.8.10 Tuner Description possible cases: Attention: In case the tuner is replaced, always check the tuner options!
Uart loggings are displayed: • When Uart loggings are coming out, the first conclusion we can make is that the TV set is starting up and communication with the flash RAM seems to be supported. The PNX855xx is able to read and write in the DRAMs. • We can not yet conclude : Flash RAM and DRAMs are fully operational/reliable.There still can be errors in the data transfers, DRAM erros, read/write speed and timing control.
5.8.11 Display option code Attention: In case the SSB is replaced, always check the display option code in SAM, even when picture is available. Performance with the incorrect display option code can lead to unwanted side-effects for certain conditions. While in the download application (start up in TV mode + “OK” button pressed), the display option code can be changed via 062598 HOME XXX special SAM command (XXX=display option in 3 digits).
No Uart logging at all: • In case there is no Uart logging coming out, check if the startup script can be send over the I2C bus (3 trials to startup) + power supplies are switched on and stable. • No startup will end up in a blinking LED status : error LAYER 1 = “2”, error LAYER 2 = “53” (startup with SDM solder paths short). • Error LAYER 2 = “15” (hardware cause) is more related to a supply issue while error LAYER 2 = “53” (software cause) refers more to boot issues. Uart loggings reporting fault conditions, error messages, error codes, fatal errors: • Failure messages should be checked and investigated.For instance fatal error on the PNX51x0: check startup of the back-end processor, supplies..reset, I2C bus. => error mentioned in the logging as: *51x0 failed to start by itself*. back to div. table
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5.8.12 SSB Replacement
For a more general overview of steps to follow, refer to figure 5-12 SSB replacement flowchart.
Follow the instructions in the flowchart in case a SSB has to be exchanged. See table 5-3 SSB replacement instructions.
Table 5-3 SSB replacement instructions
Step #
Action to do
Advise / Attention points / Remarks
1
Ensure ESD protection by using a wristband
-
2
If SSB is still functional: Go via SAM to “upload to USB” and copy Personal settings - Option codes - Alignments (Presets) - Set Identification. Advice: because of differences in memory allocation, it is advised to upgrade main SW before copying data from existing SSB. Copy of Preset list is possible from normal user interface.
Upload to USB: A directory “repair” will be created on the USB, and all data will be copied in this directory. On sets with software before Q552-xx-140-x-x, there was an issue by copying the program map table, so it is advised to reinstall the programs from Virgin mode instead of using copy via USB.
3
Disconnect set from mains and from antenna.
Safety and ESD!
4
Open the set and disconnect LVDS flat cable. Disconnect other cables / connections.
Always take care for ESD! Be extra careful when removing connectors!
5
Dismount the (defective) SSB from the set.
Do not damage SSB copper tracks with your tools! Do not scratch bottom of SSB (be very careful by moving SSB over SSB supports). See Figure 5-10 and Figure 5-11.
6
Place new SSB in the set, and fixate/mount carefully.
Do not damage SSB copper tracks with your tools! Do not scratch bottom of SSB (be very careful by moving SSB over SSB supports). See Figure 5-10 and Figure 5-11.
7
Connect PSU and other connectors. Insert the optional WiFi module.
Make sure that the connectors are correctly plugged-in and locked (click). Special attention for the optional WiFi module: a defective WiFi module can give reboots or no start-up of the SSB. In this case do a trial without WiFi module.
8
Connect LVDS connector(s).
Be very careful: wrong or bad connection can damage the TCON part on the SSB and damage the LCD display. Check if flat cables are fitted correctly before closing the connector lock.
9
Connect set to mains and switch TV “On”.
Check start-up of the set, backlight switch “On”…
10
If the set does not start (or reboots) check: - The connectors from the power supply, - The power supply cable and connection pins, - LVDS cable connection.
Power supply connector must “snap” into the socket.
11
Before programming the new SSB, upgrade to latest software. If set is starting Some SSB’s will start-up in software upgrade mode, and software needs to be installed before you up in software upgrade mode, then first install new software via software can program the Display Option codes. It’s adviced to use an autorun.upg file for software Upgrade Menu or via the autorun.upg file. upgrade, this in case you have no OSD on the screen.
12
If set is starting up without picture or menu (OSD), first program the correct Display Option codes.
Use blind service mode “062598” + “Home” button, directly followed by the Display Option code (3 digits). Set will switch to Standby after Display Option code is entered.
13
Go to SAM and program “Set type” and “Serial number”. This is possible via the NVM editor and virtual keyboard. In case personal settings were recovered from the defective SSB, you can use an “Upload from USB”.
Programming “Set type” and “Serial number” is mandatory to have all functionality of the set, like DLNA, Net TV… For certain sets you may need to use ComPair for this.
14
Check if option codes are correct, and keys are present. SSBs with integrated Attention, check if Tuner on defect board and new board is the same. If not, the same Tuner option TCON needs TCON alignment in SAM. Adjust White point colour temperature code nbr 1 needs to be adapted (add or substract 512). refer to General Service Info GSC_89308. Validity of HDCP, CI+, Marlin, and WDRM keys can be checked via ComPair. alignment for normal, warm and cool according to values in section 6.3.1.
15
Update to latest software (Standby and main software). This step is necessary to make sure that the (optional) 200 Hz T-CON board has the latest software. Display drive, and White point colour temperature needs to be aligned! See section 6.3.1.
Even when the SSB already has the latest software, it is mandatory to upgrade again the software to update the 200 Hz T-CON part. At the end of the main software update process, a dedicated software is loaded, from the main processor via the LVDS connection, to upgrade the 200 Hz T-CON part. For certain LCD displays, a dedicated Display software patch (autoscript) is available. See General Service info GSC_85590.
16
Once the set is playing, check cable connection between PSU and SSB, by moving the cable if there are no bad connections.
Check the two power connectors 1M95 and 1M99. Bad contact or bad connection here can give reboots.
17
Fill in the Electronic DDF (Defect Description Form): Fault symptom, TV type It is mandatory to fill in the E-DDF form (see the “At Your Service” web portal). and TV serial number.
18
Install presets or check if all presets are OK. Check in CSM if Type number, Serial number, Main and Standby software are correct.
19
Check connectivity to Net TV and DLNA. Check AmbiLight functionality.
Only for sets having these functionalities.
20
Inform customer about Memory Card, USB, or Hard drive PVR (Personal Video Recording) recordings.
Inform customer that previous recordings made on Memory Card (movie download), USB, or Hard drive will be lost. USB or Hard drive needs to be re-formatted and matched with new SSB (WDRM Keys!).
Special attention for Standby software: check if Standby software ID is matching with the D-RAM’s mounted on the SSB (2 × Elpida = 73, 4 × Elpida = 64, 2 × Hynix = 72, 4 × Hynix = 63).
SSB fixation points
Significant risk of damaging the board by the fixation point Blue arrows: traces of friction Red arrows: damaged components
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Figure 5-10 Mounting attention points [1/2]
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Figure 5-11 Mounting attention points [2/2]
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Service Modes, Error Codes, and Fault Finding
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In st ru ct io n n o t e SSB rep lacem en t Q55x.x
ST AR T
Before starting: - prepare a USB memory stick with the latest software - download the latest Main Software (Fus) from www.p4c.philips.com - unzip this file - create a folder ”upgrades” in the root of a USB stick (size > 50 MB) and save the autorun.upg file in this "upgrades" folder. Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in case there are more than one "autorun.upg" files on the USB stick.
Set is still oper ating? No Yes
C onnect the U SB stick to the set, go to SAM and save the current TV settings via “Upload to USB”
1. D ismount the defective SSB. 2. Replace the SSB by a Service SSB.
Start-up the set Due to a possible wrong display option code in the received Service SSB (NVM), it’s possible that no picture is displayed. Due to this the download application will not be shown either. This tree enables you to load the main software step-by-step via the UART logging on the PC (this for visual feedback). No pictur e displayed
1) Start up the TV set, equiped with the Service SSB, and enable the UART logging on the PC.
Set behaviour?
Pictur e displayed Set is starting up without software upgrade menu appearing on screen
Pictur e displayed Set is starting up with software upgrade menu appearing on screen
2) The TV set will start-up automatically in the download application if main TV software is not loaded. 1) Plug the USB stick into the TV set and select the “autorun .upg” file in the displayed browser.
3) Plug the prepared USB stick into the TV set. Follow the instructions in the UART log file, press “Right” cursor key to enter the list. Navigate to the “autorun.upg” file in the UART logging printout via the cursor keys on the remote control. When the correct file is selected, press “Ok”.
2) Now the main software will be loaded automatically, supported by a progress bar. 4) Press "Down" cursor and “Ok” to start flashing the main TV software. Printouts like: “L: 1-100%, V: 1-100% and P: 1-100%” should be visible now in the UART logging. 3) Wait until the message “Operation successful !” is displayed and remove all inserted media. Restart the TV set.
5) Wait until the message “Operation successful !” is logged in the UART log and remove all inserted media. Restart the TV set.
Set the correct “Display code” via “062598 -HOME- xxx” where “xxx” is the 3 digit display panel code (see sticker on the side or bottom of the cabinet)
After entering the “Display Option” code, the set is going to Standby (= validation of code) Restart the set
No
Connect PC via the ComPair interface to Service connector.
Saved settings on USB stick?
Yes
Start TV in Jett mode (DVD I + (OSD)) Open ComPair browser Q54x
Go to SAM and reload settings via “Download from USB” function.
In case of settings reloaded from USB, the set type, serial number, display 12 NC, are automatically stored when entering display options.
Program set type number, serial number, and display 12 NC Program E - DFU if needed. If not already done: Check latest software on Service website. Update main and Stand-by software via USB.
Attention point for Net TV: If the set type and serial number are not filled in, the Net TV functionality will not work. It will not be possible to connect to the internet.
- Check if correct “display option” code is programmed. - Verify “option codes” according to sticker inside the set. - Default settings for “white drive” > see Service Manual.
Check and perform alignments in SAM according to the Service Manual. Option codes, colour temperature, etc.
Final check of all menus in CSM. Special attention for HDMI Keys and Mac address. Check if E - D F U is present.
End
Q55x.E SSB Board swap – ER on behalf of VDS Updated 28-07-2011
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Figure 5-12 SSB replacement flowchart
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Set is st art in g u p in F act o ry m o d e
Set is starting up in F actory m ode?
Noisy picture with bands/lines is visible and the RED LED is continuous on.
An “F” is displayed (and the HDMI 1 input is displayed).
- Press the “volume minus” button on the TVs local keyboard for 5 ~10 seconds - Press the “SOURCE” button for 10 seconds until the “F” disappears from the screen or the noise on the screen is replaced by “blue mute”
The noise on the screen is replaced with the blue mute or the “F” is disappeared!
Unplug the mains cord to verify the correct disabling of the Factory mode.
Program display option code via “062598 MENU”, followed by the 3 digits code of the display (this code can be found on a sticker on - or inside - the set).
After entering “display option” code, the set is going in stand-by mode (= validation of code)
R estart the set
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Figure 5-13 SSB replacement flowchart - Factory mode
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Service Modes, Error Codes, and Fault Finding
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Figure 5-14 SSB start-up
5.9
Software Upgrading
5.9.1
Introduction
Automatic Software Upgrade In “normal” conditions, so when there is no major problem with the TV, the main software and the default software upgrade application can be upgraded with the “AUTORUN.UPG” (FUS part of the one-zip file: e.g. 3104 337 05661 _FUS _Q555X_ x.x.x.x_prod.zip). This can also be done by the consumers themselves, but they will have to get their software from the commercial Philips website or via the Software Update Assistant in the user menu (see eUM). The “autorun.upg” file must be placed in the root of the USB stick. How to upgrade: 1. Copy “AUTORUN.UPG” to the root of the USB stick. 2. Insert USB stick in the set while the set is operational. The set will restart and the upgrading will start automatically. As soon as the programming is finished, a message is shown to remove the USB stick and restart the set.
The set software and security keys are stored in a NANDFlash, which is connected to the PNX855xx. It is possible for the user to upgrade the main software via the USB port. This allows replacement of a software image in a stand alone set, without the need of an E-JTAG debugger. A description on how to upgrade the main software can be found in the electronic User Manual. Important: When the NAND-Flash must be replaced, a new SSB must be ordered, due to the presence of the security keys! (CI +, MAC address, ...). Perform the following actions after SSB replacement: 1. Set the correct option codes (see sticker inside the TV). 2. Update the TV software => see the eUM (electronic User Manual) for instructions. 3. Perform the alignments as described in chapter 6 (section 6.5 Reset of Repaired SSB). 4. Check in CSM if the CI + key, MAC address.. are valid. For the correct order number of a new SSB, always refer to the Spare Parts list! 5.9.2
Manual Software Upgrade In case that the software upgrade application does not start automatically, it can also be started manually. How to start the software upgrade application manually: 1. Disconnect the TV from the Mains/AC Power. 2. Press the “OK” button on a Philips TV remote control or a Philips DVD RC-6 remote control (it is also possible to use a TV remote in “DVD” mode). Keep the “OK” button pressed while reconnecting the TV to the Mains/AC Power. 3. The software upgrade application will start.
Main Software Upgrade •
Attention! In case the download application has been started manually, the “autorun.upg” will maybe not be recognized. What to do in this case: 1. Create a directory “UPGRADES” on the USB stick.
The “UpgradeAll.upg” file is only used in the factory.
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2. Rename the “autorun.upg” to something else, e.g. to “software.upg”. Do not use long or complicated names, keep it simple. Make sure that “AUTORUN.UPG” is no longer present in the root of the USB stick. 3. Copy the renamed “upg” file into this directory. 4. Insert USB stick into the TV. 5. The renamed “upg” file will be visible and selectable in the upgrade application. Back-up Software Upgrade Application If the default software upgrade application does not start (could be due to a corrupted boot sector) via the above described method, try activating the “back-up software upgrade application”. How to start the “back-up software upgrade application” manually: 1. Disconnect the TV from the Mains/AC Power. 2. Press the “CURSOR DOWN”-button on a Philips TV remote control while reconnecting the TV to the Mains/AC Power. 3. The back-up software upgrade application will start. 5.9.3
Stand-by Software Upgrade via USB In this chassis it is possible to upgrade the Stand-by software via a USB stick. The method is similar to upgrading the main software via USB. Use the following steps: 1. Create a directory “UPGRADES” on the USB stick. 2. Copy the Stand-by software (part of the one-zip file, e.g. StandbyFactory_88.0.0.0.upg) into this directory. 3. Insert the USB stick into the TV. 4. Start the download application manually (see section “ Manual Software Upgrade”. 5. Select the appropriate file and press the “OK” button to upgrade.
5.9.4
Content and Usage of the One-Zip Software File Below the content of the One-Zip file is explained, and instructions on how and when to use it. • AmbiCpld_Q55XX_x.x.x.x_prod.zip. Contains the program instruction and software content, needed to upgrade the ambilight CPLD on the TV550 platform. • BalanceFPGA_Q555X_x.x.x.x_prod.zip. Contains the BalanceFPGA software in “upg” format. • FUS_Q555X_x.x.x.x_prod.zip. Contains the “autorun.upg” which is needed to upgrade the TV main software and the software download application. • PNX5130UPG_Q555X_x.x.x.x_prod.zip. Contains the PNX5130 software in “upg” format. • StandbySW_Q555X_x.x.x.x_prod.zip. Contains the StandbyFactory software in “upg” format. • ProcessNVM_Q55XX_x.x.x.x_prod.zip. Default NVM content. Must be programmed via ComPair or can be loaded via USB, be aware that all alignments stored in NVM are overwritten here.
5.9.5
UART logging 2K10 (see section “5.8 Fault Finding and Repair Tips, 5.8.6 Logging)
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Alignments
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6. Alignments Index of this chapter: 6.1 General Alignment Conditions 6.2 Hardware Alignments 6.3 Software Alignments 6.4 Option Settings 6.5 Reset of Repaired SSB 6.6 Total Overview SAM modes
6.1
•
6.3.1
•
•
6.2
100
Brightness
50
Colour
0
Light Sensor
Off
Picture format
Unscaled
In menu “Picture”, choose “Pixel Plus HD” and set picture settings as follows:
Picture Setting Dynamic Contrast
Off
Dynamic Backlight
Off
Colour Enhancement
Off
Gamma
0
•
Go to the SAM and select “Alignments”-> “White point”.
White point alignment LCD screens: • Use a 100% white screen (format: 720p50) to the HDMI input and set the following values: – “Colour temperature”: “Cool”. – All “White point” values to: “127”.
First, set the correct options: – In SAM, select “Option numbers”. – Fill in the option settings for “Group 1” and “Group 2” according to the set sticker (see also paragraph 6.4 Option Settings). – Press OK on the remote control before the cursor is moved to the left. – In submenu “Option numbers” select “Store” and press OK on the RC. OR: – In main menu, select “Store” again and press OK on the RC. – Switch the set to Stand-by. Warming up (>15 minutes).
In case you have a colour analyser: • Measure, in a dark environment, with a calibrated contactless colour analyser (Minolta CA-210 or Minolta CS-200) in the centre of the screen and note the x, y value. • Change the pattern to 90% white screen. If a Quantum Data generator is used, select the “GreyAll” test pattern at level = 230. • Adjust the correct x, y coordinates (while holding one of the White point registers R, G or B on 127) by means of decreasing the value of one or two other white points to the correct x, y coordinates (see Table 6-1 White D alignment values - LED - Minolta CA-210, or 6-2 White D alignment values - LED - Minolta CS-200). Tolerance: dx: 0.002, dy: 0.002. • Repeat this step for the other colour temperatures that need to be aligned. • When finished press OK on the RC and then press STORE (in the SAM root menu) to store the aligned values to the NVM. • Restore the initial picture settings after the alignments.
Hardware Alignments Not applicable.
6.3
Contrast
•
Alignment Sequence •
Choose “TV menu”, “Setup”, “More TV Settings” and then “Picture” and set picture settings as follows:
Picture Setting
Perform all electrical adjustments under the following conditions: • Power supply voltage (depends on region): – AP-NTSC: 120 VAC or 230 VAC / 50 Hz ( 10%). – AP-PAL-multi: 120 - 230 VAC / 50 Hz ( 10%). – EU: 230 VAC / 50 Hz ( 10%). – LATAM-NTSC: 120 - 230 VAC / 50 Hz ( 10%). – US: 120 VAC / 60 Hz ( 10%). • Connect the set to the mains via an isolation transformer with low internal resistance. • Allow the set to warm up for approximately 15 minutes. • Measure voltages and waveforms in relation to correct ground (e.g. measure audio signals in relation to AUDIO_GND). Caution: It is not allowed to use heat sinks as ground. • Test probe: Ri > 10 M, Ci < 20 pF. • Use an isolated trimmer/screwdriver to perform alignments. 6.1.1
White Point •
General Alignment Conditions
LATAM models: an NTSC M TV-signal with a signal strength of at least 1 mV and a frequency of 61.25 MHz (channel 3).
Software Alignments Put the set in SAM mode (see Chapter 5. Service Modes, Error Codes, and Fault Finding). The SAM menu will now appear on the screen. Select ALIGNMENTS and go to one of the sub menus. The alignments are explained below. The following items can be aligned: • White point • Ambilight.
Table 6-1 White D alignment values - LED - Minolta CA-210
To store the data: • Press OK on the RC before the cursor is moved to the left • In main menu select “Store” and press OK on the RC • Switch the set to stand-by mode.
Value
Cool (9420K)
Normal (8120K)
Warm (6080K)
x
0.282
0.292
0.320
y
0.298
0.311
0.345
Table 6-2 White D alignment values - LED - Minolta CS-200
For the next alignments, supply the following test signals via a video generator to the RF input: • EU/AP-PAL models: a PAL B/G TV-signal with a signal strength of at least 1 mV and a frequency of 475.25 MHz • US/AP-NTSC models: an NTSC M/N TV-signal with a signal strength of at least 1 mV and a frequency of 61.25 MHz (channel 3).
Value
Cool (11000K)
Normal (9000K)
Warm (6500K)
x
0.276
0.287
0.313
y
0.282
0.296
0.329
If you do not have a colour analyser, you can use the default values. This is the next best solution. The default values are average values coming from production. • Select a COLOUR TEMPERATURE (e.g. COOL, NORMAL, or WARM). • Set the RED, GREEN and BLUE default values according to the values in Table 6-3 to Table 6-10. back to div. table
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When finished press OK on the RC, then press STORE (in the SAM root menu) to store the aligned values to the NVM. Restore the initial picture settings after the alignments.
6.4
Option Settings
6.4.1
Introduction
Table 6-3 White tone default setting 32" (4000 series) White Tone
The microprocessor communicates with a large number of I2C ICs in the set. To ensure good communication and to make digital diagnosis possible, the microprocessor has to know which ICs to address. The presence / absence of these PNX51XX ICs (back-end advanced video picture improvement IC which offers motion estimation and compensation features (commercially called HDNM) plus integrated Ambilight control) is made known by the option codes.
e.g. 32PFL4xx7x/xx
Colour Temperature R
G
B
Normal
126
115
122
Cool
112
110
127
Warm
127
104
81
Table 6-4 White tone default setting 37" (4000 series) White Tone
Notes: • After changing the option(s), save them by pressing the OK button on the RC before the cursor is moved to the left, select STORE in the SAM root menu and press OK on the RC. • The new option setting is only active after the TV is switched “off” / “stand-by” and “on” again with the mains switch (the NVM is then read again).
e.g. 37PFL4xx7x/xx
Colour Temperature R
G
B
Normal
105
127
126
Cool
105
94
127
Warm
127
94
85
Table 6-5 White tone default setting 42" (4000 series) 6.4.2 White Tone
Colour Temperature R
G
B
Normal
111
114
127
Cool
124
115
127
Warm
127
99
76
For dealer options, in SAM select “Dealer options”. See Table 6-12 SAM mode overview. 6.4.3
Table 6-6 White tone default setting 47" (4000 series) White Tone
G
B
Normal
127
112
118
Cool
115
119
127
Warm
127
100
76
6.4.4
e.g. 32PFL5xx7/xx G
B
Normal
96
84
127
Cool
127
99
102
Warm
127
83
44
Table 6-8 White tone default setting 40" (5000 series) White Tone
e.g. 40PFL5xx7/xx
Colour Temperature R
G
B
Normal
115
121
127
Cool
97
108
127
Warm
127
117
92
Table 6-9 White tone default setting 46" (5000 series) White Tone
e.g. 46PFL5xx7.xx
Colour Temperature R
G
B
Normal
97
92
127
Cool
127
101
109
Warm
127
84
53
Diversity Not all sets with the same Commercial Type Number (CTN) necessarily have the same option code! Use of Alternative BOM => an alternative BOM number usually indicates the use of an alternative display or power supply. This results in another display code thus in another Option code. Refer to Chapter 2. Technical Specs, Diversity, and Connections.
Table 6-10 White tone default setting 55" (5000 series) White Tone
e.g. 55PFL5xx7/xx
Colour Temperature R
G
B
Normal
98
85
127
Cool
127
104
105
Warm
127
83
45
2012-Jun-29
Opt. No. (Option numbers) Select this sub menu to set all options at once (expressed in two long strings of numbers). An option number (or “option byte”) represents a number of different options. When you change these numbers directly, you can set all options very quickly. All options are controlled via eight option numbers. When the NVM is replaced, all options will require resetting. To be certain that the factory settings are reproduced exactly, you must set both option number lines. You can find the correct option numbers on a sticker inside the TV set. Example: The options sticker gives the following option numbers: • 32776 00001 15421 02235 • 43847 36615 33024 00012 The first line (group 1) indicates hardware options 1 to 4, the second line (group 2) indicate software options 5 to 8. Every 5-digit number represents 16 bits (so the maximum value will be 65536 if all options are set). When all the correct options are set, the sum of the decimal values of each Option Byte (OB) will give the option number.
Table 6-7 White tone default setting 32" (5000 series)
Colour Temperature R
(Service) Options From 2011 onwards, it is not longer possible to change individual option settings in SAM. Options can only be changed all at once by using the option codes as described in section 6.4.4.
e.g. 47PFL4xx7/xx
Colour Temperature R
White Tone
Dealer Options
e.g. 42PFL4xx7/xx
6.4.5
Option Code Overview Refer to the sticker in the set for the correct option codes. Important: after having edited the option numbers as described above, you must press OK on the remote control before the cursor is moved to the left!
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Alignments 6.4.6
Option Bit Overview
Q552.4E LA
6.
EN 41
Caution When manipulating option codes, know what you’re doing. Wrong option codes could damage the set. Prescribed option codes below are an example, not valid for all sets and are subject to modification. The correct option codes are always present on a sticker inside the set!
For test purposes, please find below an overview of the Option Codes on bit level. With a bin/dec converter, you can calculate the Option Code.
Table 6-11 Option codes at bit level (Option 1 - Option 8) Option & Bit Dec. Value Option Name
Prescribed Value1) Description
Option 1 (prescribed value 327761)) Bit 15 (MSB) 32768
Video Store Streaming
11)
0 = OFF 1 = ON
Bit 14
16384
Multi App
001)
Bit 13
8192
00 = none 01 = multi app 10 = AVPIP + multi app 11 = future use
Perfect Pixel
001)
00 = Pixel Plus HD 01 = Pixel Precise HD 10 = Perfect Pixel HD 11 = future use
Tuner Type
0001)
000 = TH2603 (Europe/CH) 001 = FA2307 (Brazil) 010 = VA1E1ED2411 011 = SUT-RE2144 100 = future use 101 = future use 110 = future use 111 = future use
PQ Profiles
0001)
000 = OFF 001 = ON 010 = future use 011 = future use 100 = future use 101 = future use 110 = future use 111 = future use
DNM
011)
00 = Perfect Natural Motion 01 = HD Natural Motion 10 = future use 11 = future use
MOP AL
01)
0 = OFF 1 = ON
AL Optical Syst
001)
00 = 140 nit 01 = 200 nit 10 = 110 nit 11 = future use
Bit 12
4096
Bit 11
2048
Bit 10
1024
Bit 9
512
Bit 8
256
Bit 7
128
Bit 6
64
Bit 5
32
Bit 4
16
Bit 3
8
Bit 2
4
Bit 1
2
Bit 0 (LSB)
1
Option 2 (prescribed value 000011)) Bit 15 (MSB) 32768
AL Shop Mode
01)
0 = boost mode in shop is OFF 1 = boost mode in shop is ON
Bit 14
AL settings storage location
01)
0 = stored in AL modules 1 = stored in SSB 0 = OFF 1 = ON
16384
Bit 13
8192
Wall Adaptive AL
01)
Bit 12
4096
Sunset
01)
0 = OFF 1 = ON
Ambient Light
00001)
0000 = none 0001 = 2-sided (3/3) 0010 = 2-sided (4/4) 0011 = 2-sided (5/5) 0100 = 2-sided (6/6) 0101 = 2-sided (7/7) 0110 = 3-sided (4/7/4) 0111 = 3-sided (5/5)(9/9)(5/5) 1000 = 3-sided (3/6/3) 1001 = 3-sided (5/5)(10/10)(5/5) 1010 = 2-sided (8/8) 1011 = 3-sided (5/12/15) 1100 = 2-sided (1/1) 1101 = 2-sided (2/2) 1110 = 3-side (4/10/4) 1111 = 3-side (6/6)(11/11)(6/6)
FPGA3Dact/1Ddimm
01)
0 = OFF 1 = ON 0 = AL2k10 1 = AL2k11
Bit 11
2048
Bit 10
1024
Bit 9
512
Bit 8
256
Bit 7
128
Bit 6
64
AL Select
01)
Bit 5
32
3D Passive
01)
0 = 2D 1 = 3D passive 0 = off 1 = on (200 Hz board present) 0 = Super Resolution SD 1 = Super Resolution HD
Bit 4
16
Smart Bit Enhancement (SBE)
01)
Bit 3
8
Super Resolution
01)
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EN 42
6.
Q552.4E LA
Alignments
Option & Bit Dec. Value Option Name
Prescribed Value1) Description
Light Sensor Type
001)
00 = future use 01 = future use 10 = future use 11 = future use
Light Sensor
11)
0 = OFF 1 = ON
Bit 2
4
Bit 1
2
Bit 0 (LSB)
1
Option 3 (prescribed value 154211)) Bit 15 (MSB) 32768
Side IO
01)
0 = not present 1 = present
Bit 14
16384
AV3
0111)
Bit 13
8192
Bit 12
4096
000 = none 001 = CVBS 010 = YPbPr 011 = YPbPr/LR:Europe 100 = YPbPr/HV/LR 101 = CVBS/LR:Brazil 110 = CVBS/Yc/LR 111 = YPbPr/CVBS/LR
Bit 11
2048
AV2
111)
Bit 10
1024
00 = Scart/CVBS/RGB/LR 01 = CVBS 10 = YPbPr/LR 11 = none:Europe and Brazil
Bit 9
512
AV1
001)
Bit 8
256
00 = Scart/CVBS/RGB/LR:Europe 01 = CVBS/YC/YPbPr/HV/LR 10 = CVBS/YC/YPbPr/LR 11 = YPbPr/LR:Brazil
Bit 7
128
3D Prepared
01)
0 = not prepared 1 = prepared
Bit 6
64
Sound in Stand
01)
0 = OFF 1 = ON
1)
Bit 5
32
Headphone
1
0 = OFF 1 = ON
Bit 4
16
Seamless System
11)
0 = OFF 1 = ON 0 = OFF 1 = ON
Bit 3
8
ViewPort 21_9/PQL
11)
Bit 2
4
HDMI Side
11)
0 = OFF 1 = ON (HDMI 4) 0 = OFF 1 = ON
Bit 1
2
HDMI 3
01)
Bit 0 (LSB)
1
HDMI 2
11)
0 = OFF 1 = ON
Cabinet
000011)
Cabinet type (no detailed info available)
Region
0001)
000 = Europe (/02, /05 & /12) 001 = AP PAL multi 010 = AP NTSC 011 = future use 100 = Latam (/78 & /77) 101 = Australia 110 = China (/93) 111 = future use
Display MSB
11)
0 = display option =< 255 1 = display option > 255 0 = OFF 1 = ON
Option 4 (prescribed value Bit 15 (MSB) 32768 Bit 14
16384
Bit 13
8192
Bit 12
4096
Bit 11
2048
Bit 10
1024
Bit 9
512
Bit 8
256
Bit 7
128
022351))
Bit 6
64
S Video
01)
Bit 5
32
Video Store USB
11)
0 = OFF 1 = ON 0 = OFF 1 = ON (automatic software upgradable via internet)
Bit 4
16
Internet software Upgrade
11)
Bit 3
8
Online Service
11)
0 = OFF 1 = ON (connection to internet provider Philips) 0 = OFF 1 = ON (wireless connection to ethernet; no link with “Ethernet option” bit “0”)
Bit 2
4
WiFi
01)
Bit 1
2
DLNA
11)
0 = OFF 1 = PC link
Ethernet
11)
0 = OFF 1 = Ethernet vonnector and HW present
Bit 0 (LSB)
1
Option 5 (prescribed value 438471)) Bit 15 (MSB) 32768
8 Days EPG
11)
0 = OFF 1 = ON (country dependent)
Bit 14
16384
DVBC Installation
011)
Bit 13
8192
00 = OFF 01 = Country dependent 10 = ON 11 = future use
Bit 12
4096
DVBT Installation
011)
Bit 11
2048
00 = OFF 01 = Country dependent 10 = ON 11 = future use
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Alignments Option & Bit Dec. Value Option Name
Prescribed Value1) Description
Bit 10
DVB-S
01)
0 = OFF 1 = ON (ATSC/DVB should be ON) 0 = OFF 1 = ON (ATSC/DVB should be ON)
1024
Q552.4E LA
Bit 9
512
DVB-C
11)
Bit 8
256
DVB
11)
0 = analogue only 1 = DVBT (and C/S depending DVBC/S option)
Display Type
010001111)
Display Type (ex.: 327)
E-sticker
11)
0 = OFF 1 = ON
Hotel Mode
001)
00 = OFF 01 = 1V1 10 = 1V2 11 = future use
Virgin
01)
0 = ON 1 = OFF
Bit 7
128
Bit 6
64
Bit 5
32
Bit 4
16
Bit 3
8
Bit 2
4
Bit 1
2
Bit 0 (LSB)
1
6.
EN 43
Option 6 (prescribed value 366151)) Bit 15 (MSB) 32768 Bit 14
16384
Bit 13
8192
Bit 12
4096
Bit 11
2048
empty
-
-
Bit 10
1024
Auto Store Mode
111)
Bit 9
512
00 = none 01 = PDC_VPS 10 = TXT page 11 = PDC_VPS_TXT
Bit 8
256
Temp sensor on SSB
11)
0 = OFF 1 = ON
Bit 7
128
Ginga
001)
Bit 6
64
00 = OFF 01 = Country dependent 10 = ON 11 = future use
Bit 5
32
MHP
001)
Bit 4
16
00 = OFF 01 = Country dependent 10 = ON 11 = future use
Bit 3
8
Over the Air Download
011)
Bit 2
4
00 = OFF 01 = Country dependent 10 = ON 11 = future use
Bit 1
2
DVBC light
11)
0 = OFF 1 = ON (when DVBC Installation is OFF or when ON but selected country is OFF, this option is used)
Bit 0 (LSB)
1
DVBT light
11)
0 = OFF 1 = ON (when DVBT Installation is OFF or when ON but selected country is OFF, this option is used)
Visual Identity
11)
0 = User Interface 2k10 1 = User Interface 2k11 (always ON)
Red LED Config LUT
0001)
000 = LUT 0 001 = LUT 1 010 = future use 011 = future use 100 = future use 101 = future use 110 = future use 111 = future use
Board Identifier
001)
not used, should always be “00”
Manet
01)
0 = all sets except Manet 1= Manet 0 = OFF 1 = ON
Option 7 (prescribed value Bit 15 (MSB) 32768 Bit 14
16384
Bit 13
8192
Bit 12
4096
Bit 11
2048
Bit 10
1024
Bit 9
512
330241))
Bit 8
256
Auto Power Down
11)
Bit 7
128
Light Guide
01)
0 = OFF 1 = ON 0 = integrated set 1 = e-box/monitor
Bit 6
64
E-box
01)
Bit 5
32
Temp LUT
0001)
Bit 4
16
Bit 3
8
000 = future use 001 = future use 010 = future use 011 = future use 100 = future use 101 = future use 110 = future use 111 = future use
Bit 2
4
Temp Sensor
001)
Bit 1
2
00 = no temp sensor 01 = temp sensor in display 10 = temp sensor on additional board 11 = temp sensor in AL module
Bit 0 (LSB)
1
FAN
01)
0 = no fan 1 = fan(s) present)
01)
Cabinet
Option 8 (prescribed value Bit 15 (MSB) 32768
000121)) MSB Cabinet
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2012-Jun-29
EN 44
6.
Q552.4E LA
Alignments
Option & Bit Dec. Value Option Name
Prescribed Value1) Description
Bit 14
01)
16384
3D goggles
0 = 2K10 Xpand 1 = 2k11 Real D
Bit 13
8192
empty
-
-
Bit 12
4096
3D Overdrive LUT
0001)
Bit 11
2048
Bit 10
1024
000 = no overdrive LUT 001 = LUT1 010 = LUT2 011 = LUT3 100 = LUT4 101 = LUT5 110 = LUT6 111 = LUT7
Bit 9
512
ISF
01)
0 = OFF 1 = ON
Bit 8
256
DVB-S channel decoder + new LNB 01)
Bit 7
128
MSB Light Sensor type
01)
-
64
DVB-T2 Sony channel decoder
11)
0 = OFF 1 = channel decoder T2: CXD2834ER 0 = not present 1 = present
Bit 6
0 = OFF 1 = channel decoder STV 0903BAC + LNBH25
Bit 5
32
FPGA PQ
01)
Bit 4
16
2player gaming
11)
0 = OFF 1 = ON 0 = OFF 1 = ON
Bit 3
8
WM DRM10
11)
Bit 2
4
HBBTV
11)
0 = OFF 1 = ON 0 = no installation 1 = country depending 0 = OFF 1 = channel decoder 2
Bit 1
2
DVB-T2 Installation
01)
Bit 0 (LSB)
1
DVB-T2
11)
Note 1). Example
6.5
6.5.1
SSB identification Whenever ordering a new SSB, it should be noted that the correct ordering number (12nc) of a SSB is located on a sticker on the SSB. The format is . The ordering number of a “Service” SSB is the same as the ordering number of an initial “factory” SSB.
Reset of Repaired SSB A very important issue towards a repaired SSB from a Service repair shop (SSB repair on component level) implies the reset of the NVM on the SSB. A repaired SSB in Service should get the service Set type “00PF0000000000” and Production code “00000000000000”. Also the virgin bit is to be set. To set all this, you can use the ComPair tool or use the “NVM editor” and “Dealer options” items in SAM (do not forget to “store”). After a repaired SSB has been mounted in the set (set repair on board level), the type number (CTN) and production code of the TV has to be set according to the type plate of the set. For this, you can use the NVM editor in SAM. This action also ensures the correct functioning of the “Net TV” feature and access to the Net TV portals. The loading of the CTN and production code can also be done via ComPair (Model number programming). After a SSB repair, the original channel map can be restored, provided that the original channel map was stored on a USB stick before repair was commenced and that basic functionality of the TV, needed for this procedure, was not hampered as a result of the defect. The procedure of “channel map cloning” is clearly described in the (electronic) user manual.
18310_221_090318.eps 090319
Figure 6-1 SSB identification
In case of a display replacement, reset the “Operation hours display” to “0”, or to the operation hours of the replacement display.
2012-Jun-29
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Alignments 6.6
Q552.4E LA
6.
EN 45
Total Overview SAM modes Table 6-12 SAM mode overview Main Menu
Sub-menu 1
Sub-menu 2
Hardware Info
A. software version
e.g. “Q5551_0.9.1.0
Sub-menu 3
B. Stand-by processor version e.g. “STDBY_83.84.0.0” C. Production code
Description Display TV & Stand-by software version and CTN serial number
e.g. “see type plate”
Operation hours
Displays the accumulated total of operation hours.TV switched “on/off” & every 0.5 hours is increase one
Errors
Displayed the most recent errors
Reset error buffer Alignment
Clears all content in the error buffer White point
Colour temperature
Normal
3 different modes of colour temperature can be selected
Warn Cool White point red
LCD White Point Alignment. For values, see Table 6-3 White tone default setting 32" (4000 series) to 6-10 White tone default setting 55" (5000 series)
White point green White point blue Ambilight
Select module Brightness Select matrix
Dealer options
Virgin mode
Off/On
Select Virgin mode On/Off. TV starts up / does not start up (once) with a language selection menu after the mains switch is turned “on” for the first time (virgin mode)
E-sticker
Off/On
Select E-sticker On/Off (USP’s on-screen)
Auto store mode
None PDC/VPS TXT page PDC/VPS/TXT
Option numbers
Miscellaneous
Hotel mode
Group 1
e.g. “00008.00001.15421.02239”
Off
The first line (group 1) indicates hardware options 1 to 4
Group 2
e.g. “44816.34311.33024.00000”
The second line (group 2) indicates software options 5 to 8
Store
Store after changing
Initialise NVM
N.A.
Store
Select Store in the SAM root menu after making any changes
Operation hours display
Software maintenance
Hotel mode is Off
Software events
0003
In case the display must be swapped for repair, you can reset the “”Display operation hours” to “0”. So, this one does keeps up the lifetime of the display itself (mainly to compensate the degeneration behaviour)
Display
Display information is for development purposes
Clear Test reboot Test cold reboot Test application crash Hardware events
Display
Display information is for development purposes
Clear Test setting
Digital info
Current frequency: 538 QAM modulation: 64-qam
Display information is for development purposes
Symbol rate: Original network ID: 12871 Network ID: 12871 Transport stream ID: 2 Service ID: 3 Hierarchical modulation: 0 Selected video PID: 35 Selected main audio PID: 99 Selected 2nd audio PID: 8191 Install start frequency
000
Install start frequency from “0” MHz
Install end frequency
999
Install end frequency as “999” MHz
Digital only
Select Digital only or Digital + Analogue before installation
Default install frequency Installation
Digital + Analogue
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EN 46
6.
Main Menu
Q552.4E LA
Alignments
Sub-menu 1
Sub-menu 2
Development file versions Development 1 file version
Sub-menu 3
Display parameters DISPT5.0.9.29
Description Display information is for development purposes
Acoustics parameters ACSTS 5.0.6.20 PQ - TV550 1.0.27.22 PQS- Profile set PQF - Fixed settings PQU - User styles Ambilight parameters PRFAM 5.0.5.2 Development 2 file version
12NC one zip software
Display information is for development purposes
Initial main software NVM version Q55x1_0.4.5.0 Flash units software Temp com file version none Upload to USB
Channel list
To upload several settings from the TV to an USB stick
Personal settings Option codes Alignments Identification data History list All (options included) Download from USB
Channel list
To download several settings from the USB stick to the TV
Personal settings Option codes Alignments Identification data All (options included) NVM editor
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Type number
see type plate
AG code
see type plate
NVM editor; re key-in type number and production code after SSB replacement
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Circuit Descriptions
Q552.4E LA
7.
EN 47
7. Circuit Descriptions Index of this chapter: 7.1 Introduction 7.2 Power Supply 7.3 Video and Audio Processing - PNX855xx
For Service, the platform is supporting Remote Diagnostics (“IP Remote Diagnostics and Repair”). Detailed information will follow via the regular communication channels. The Q552.4E LA chassis comes with the following stylings: • 4000 (series xxPFL4xxx), • 5000 (series xxPFL5xxx).
Notes: • Only new circuits (circuits that are not published recently) are described. • Figures can deviate slightly from the actual situation, due to different set executions. • For a good understanding of the following circuit descriptions, please use the wiring-, block- (see chapter 9. Block Diagrams) and circuit diagrams (see chapter 10. Circuit Diagrams and PWB Layouts).Where necessary, you will find a separate drawing for clarification.
Implementation Key components of this chassis are: • PNX855xx System-On-Chip (SOC) TV Processor • SUT-RE214Z Hybrid Tuner (DVB-T/C, analogue) • STV6110A DVB-S Satellite Tuner • SII9x87 HDMI Switch • TAS5731 Class D Power Amplifier • LAN8710 Dual Port Gigabit Ethernet media access controller.
Introduction The Q552.4E LA is part of the TV550 “R4” 2012 platform. It uses the (same) PNX855xx chipset as its predecessor Q552.2E LA, part of the TV550 2011 platform. The major deltas versus the Q552.2 are: • integrated Wifi in 5000 & 5500 series • implementation of “active” 3D for 5500 series • 2 to 3D conversion • TV video call feature.
7.1.2
TV550 Architecture Overview For details about the chassis block diagrams refer to chapter 9. Block Diagrams. An overview of the TV550 “R4” 2012 architecture can be found in Figure 7-1 and Figure 7-2.
2 × LVDS for 4000s 4 × LVDS for 5000 s/5500s
Cell FHD@120
FLASH 512 MB DDR 512 MB 4 × 1 Gb (× 8)
32
7.1
7.1.1
PWM BOOST
BL PNX85500
Hybrid Tuner DVB T2 DVB-S2 Tuner
NR DEI PQ Enhancement FRC 3D: Active
Backlight 3D goggle drive Ambilight CPLD 8x PWM
Not Applicable for 5000 series
FPGA Spartan 6 LX4 3D-IR PWM: temp. ctrl Glass
DVB S2
SPI AL
Ambilight CPLD
AL mods.
2
HDMI 9287
Audio ETH PHY
USB HUB
IS
I2C/Analog
CI+
∗CLASS-D
Temp Sensor Shop
Class D Amplifier ∗Series supply voltage 40x7 43x7 50x7
24 V 12 V 12 V
Temp Sensor 3D active 19220_017_120224.eps 120224
Figure 7-1 Architecture of TV550 R4 platform (4000-5000 range)
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2012-Jun-29
EN 48
7.
Circuit Descriptions
Q552.4E LA
4 × LVDS
32
DDR 512MB 4 × 1Gb (× 8)
PNX85500
Hybrid Tuner DVB T2 DVB-S2 Tuner
4 × LVDS
BL
PWM BOOST
FPGA Spartan 6 LX25T Only required for Active 3D
NR DEI PQ Enhancement FRC 3D: Active
Cell FHD@120
Entry 2D3D Backlight 3D goggle drive
FLASH 512MB
8x PWM
3D-IR PWM: temp. ctrl Glass
DVB S2
SPI
HDMI 9287
Audio ETH PHY
USB HUB
Ambilight CPLD
AL mods.
∗CLASS-D
I2S
I2C/Analog
CI+
Temp Sensor Shop
Class D Amplifier ∗Series supply voltage 55x7
12v
Temp Sensor 3D active
19220_022_120227.eps 120227
Figure 7-2 Architecture of TV550 R4 platform (5500 range; supporting “active” 3D)
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Circuit Descriptions 7.1.3
Q552.4E LA
7.
EN 49
SSB Cell Layout
19220_023_120227.eps 120227
Figure 7-3 SSB layout cells (top view; 4000-5000 range)
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EN 50
7.
Q552.4E LA
Circuit Descriptions
LX25 2D-3D Processing LX25
19220_024_120227.eps 120227
Figure 7-4 SSB layout cells (5500 range; supporting “active” 3D)
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Circuit Descriptions 7.2
Power Supply
7.2.1
Power Supply Unit 4xx7 series
Q552.4E LA
7.
EN 51
No pinning table is available. Refer to section 10.1 and 10.2 for schematics. 7.2.2
Power Supply Unit 5xx7 series Table 7-1 Connector overview 5xx7 series, all screen sizes Connector no.
1308
1316
1M95
Description
Mains
to display
to SSB
1M99 to SSB
Pin
CN1
CN2
CN4
CN5
1
N
A1
+3V3SB
GND_AL
2
L
n.c.
Standby
12V3
3
n.a.
n.c.
GND1
GND_AL
4
n.a.
C1
GND1
12V3
5
n.a.
C2
+12V3
GND1
6
n.a.
C3
+12V3
+12V3
7
n.a.
C4
+Vsnd
GND1
8
n.a.
n.a.
+Vsnd
+12V3
9
n.a.
n.a.
GND_SND
n.a.
10
n.a.
n.a.
GND_SND
n.a.
11
n.a.
n.a.
BL_ON
n.a.
12
n.a.
n.a.
BL_DIM
n.a.
13
n.a.
n.a.
BL_I_CTRL
n.a.
14
n.a.
n.a.
POK
n.a.
No schematics are available.
7.3
Video and Audio Processing - PNX855xx The PNX855xx is the main audio and video processor (or System-on-Chip) for this platform. It has the following features: • • • • • • • • • • •
Multi-standard digital video decoder (MPEG-2, H.264, MPEG-4) Integrated DVB-T/DVB-C channel decoder Integrated CI+ Integrated motion accurate picture processing (MAPP2) High definition ME/MC 2D LED backlight dimming option Embedded HDMI HDCP keys Extended colour gamut and colour booster Integrated USB2.0 host controller Improved MPEG artefact reduction compared with PNX8543 Security for customers own code/settings (secure flash).
The TV550 combines front-end video processing functions, such as DVB-T channel decoding, MPEG-2/H.264 decode, analog video decode and HDMI reception, with advanced back-end video picture improvements. It also includes next generation Motion Accurate Picture Processing (MAPP2). The MAPP2 technology provides state-of-the-art motion artifact reduction with movie judder cancellation, motion sharpness and vivid colour management. High flat panel screen resolutions and refresh rates are supported with formats including 1366 × 768 @ 100Hz/120Hz and 1920 × 1080 @ 100Hz/120Hz. The combination of Ethernet, CI+ and H.264 supports new TV experiences with IPTV and VOD. On top of that, optional support is available for 2D dimming in combination with LED backlights for optimum contrast and power savings up to 50%. For a functional diagram of the PNX855xx, refer to Figure 7-5.
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2012-Jun-29
EN 52
7.
Q552.4E LA
Circuit Descriptions
PNX85500x
MEMORY CONTROLLER
TS input
DVB
MPEG SYSTEM PROCESSOR
CI/CA
TS out/in for PCMCIA
PRIMARY VIDEO OUTPUT
LVDS
LVDS for flat panel display (single, dual or quad channel)
DVB-T/C channel decoder AV-PIP SUB-PICTURE VIDEO DECODER
CVBS, Y/C, RGB
3D COMB SECONDARY VIDEO OUTPUT
Low-IF
SSIF, LR
DIGITAL IF
MPEG/H.264 VIDEO DECODER
VIDEO ENCODER
analog CVBS
AUDIO DACS
analog audio
Motion-accurate pixel processing SCALER, DE-INTERLACE AND NOISE REDUCTION
AUDIO DEMOD AND DECODE
AUDIO IN
SPDIF
AUDIO DSP AUDIO OUT HDMI RECEIVER
HDMI
450 MHz AV-DSP 560 MHz MIPS32 24KEf CPU
SYSTEM CONTROLLER (8051)
I 2S SPDIF
DRAWING ENGINE
DMA BLOCK
I2C
PWM GPIO
IR
ADC
SPI
UART
I 2C
GPIO Flash USB 2.0 SD Ethernet Memory MAC x8 Card
18770_241_100201.eps 111103
Figure 7-5 PNX855xx functional diagram
2012-Jun-29
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IC Data Sheets
Q552.4E LA
8.
EN 53
8. IC Data Sheets This chapter shows the internal block diagrams and pin configurations of ICs that are drawn as “black boxes” in the electrical diagrams (with the exception of “memory” and “logic” ICs).
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2012-Jun-29
EN 54 8.1
8.
IC Data Sheets
Q552.4E LA
Diagram 10-3-3 DC/DC B02A, TPS53126PW (IC7U03)
Block diagram
Pinning information VBST1
1
28
NC
2
27
LL1
EN1
3
26
DRVL1 PGND1
DRVH1
4
25
5
24
TRIP1
NC
6
23
VIN
22
VREG5
GND
7
TEST1
8
NC
9
TPS53124
VO1 VFB1
21
V5FILT
20
TEST2 TRIP2
VFB2
10
19
VO2
11
18
PGND2
EN2
12
17
DRVL2
NC
13
16
LL2
14
15
DRVH2
VBST2
18310_300_090319.eps 100416
Figure 8-1 Internal block diagram and pin configuration
2012-Jun-29
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IC Data Sheets
8.
EN 55
Diagram 10-3-4 DC/DC, 1.8 V to 1.2 V conversion B02B, RT9025 (IC 7UA4-1)
Block diagram
VOUT
VIN SD
OCP Error Amplifier
OTP
VDD
POR
0.8V
-
EN
+
8.2
Q552.4E LA
Mode
ADJ PGOOD
RT9025
+
0.72V
GND
Pinning information RT9025
PGOOD EN
2
VIN
3
VDD
8
GND
7
ADJ
GND 9 6 4 5
VOUT NC
SOP-8 (Exposed Pad) 19220_028_120227.eps 120227
Figure 8-2 Internal block diagram and pin configuration
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2012-Jun-29
EN 56 8.3
8.
IC Data Sheets
Q552.4E LA
Diagram 10-3-5 DC/DC, 12 V to 5 V/3.3 V conversion B02C, RT8293AHGSP (IC 7UD0)
Block diagram VIN Internal Regulator
Oscillator Slope Comp
Shutdown Comparator VA VCC 1.2V +
Foldback Control
-
EN
5k
+ UV Comparator
Current Sense Amplifier + -
VA
0.4V
Lockout Comparator + 2.7V
BOOT S + R Current Comparator
3V VCC 6µA 0.8V
SS
85mΩ
Q
85mΩ
SW
GND
RT8293A
+ +EA -
FB
Q
COMP
Pinning information
(TOP VIEW) BOOT VIN
2
SW GND
3
RT8293A 8
SS
7
EN
6
COMP
5
FB
GND 9
4
SOP-8 (Exposed Pad) 19220_030_120227.eps 120227
Figure 8-3 Internal block diagram and pin configuration
2012-Jun-29
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IC Data Sheets 8.4
Q552.4E LA
8.
EN 57
Diagram 10-3-6 DVBS supply B03A, TPS54227DDA (IC 7T00)
Block diagram
EN
EN
1
VIN
TPS54227
Logic
VIN 8
VREG5 Control Logic
Ref
+
SS
+ PWM
7
1 shot
VFB
SW
VO
6
-
2
VBST
XCON ON
VREG5
VREG5
Ceramic Capacitor
3
SGND SS
SS 4
5
Softstart
GND
PGND
SGND
+ OCP -
SW PGND
VIN
UVLO
VREG5 UVLO
REF
TSD
Protection Logic
Ref
Pinning information
1
EN
2
VFB
VIN
5
VBST
6
SW
7
GND
8
TPS54227 (HSOP8) 3
VREG5
4
SS
Power PAD
19220_029_120227.eps 120227
Figure 8-4 Internal block diagram and pin configuration
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2012-Jun-29
EN 58 8.5
8.
IC Data Sheets
Q552.4E LA
Diagram 10-3-7 Core voltage supply for DVBS demodulator B03B, LNBH25PQ (IC 7TP2)
Block diagram ADDR
SCL
SDA
LNBH25
LX PWM CTRL
I2C Digital core DETIN DSQOUT
Tone detector DAC Drop control Tone ctrl Diagnostics Protections
FLT
Isense
DSQIN
PGND VUP
Current Limit selection
Linear Regulator
Gate ctrl
BPSW VOUT
Voltage reference
GND
BYP VCC
ISEL
Pinning information 24
NC
23
22
DSQOUT DSQIN/ DSQIN EXTM
21
20
19
VUP
VOUT
DETIN
1
NC
BPSW
18
2
FLT
VCC
17
3
LX-A LX
VBYP
16
LNBH25 4
PGND
GND
15
5
NC
NC
14
6
ADDR
NC
13
SCL
SDA
ISEL
NC
NC
NC
7
8
9
10
11
12
19220_027_120227.eps 120227
Figure 8-5 Internal block diagram and pin configuration
2012-Jun-29
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IC Data Sheets 8.6
Q552.4E LA
8.
EN 59
Diagram 10-3-9 PNX 85500: Power B05A, PNX855xx (IC7S00)
Block diagram PNX8550x
MEMORY CONTROLLER
TS input
MPEG SYSTEM PROCESSOR
CI/CA
TS out/in for PCMCIA
PRIMARY VIDEO OUTPUT
LVDS
LVDS for flat panel display (single, dual or quad channel)
DVB-T/C channel decoder
DVB
AV-PIP SUB-PICTURE VIDEO DECODER
CVBS, Y/C, RGB
3D COMB SECONDARY VIDEO OUTPUT
Low-IF
MULTISTANDARD VIDEO DECODER
DIGITAL IF
Direct-IF
analog CVBS
AUDIO DACS
analog audio
analog Y/C
Motion-accurate pixel processing SCALER, DE-INTERLACE AND NOISE REDUCTION
AUDIO DEMOD AND DECODE
SSIF, LR
VIDEO ENCODER
AUDIO IN
SPDIF
AUDIO DSP AUDIO OUT HDMI RECEIVER
HDMI
450 MHz AV-DSP 500 MHz MIPS32 24KEf CPU
SYSTEM CONTROLLER (8051)
I2S SPDIF
DRAWING ENGINE Scatter/Gather TS Demux
I2C
PWM Px_x
IR
ADC
SPI
UART
I2C
GPIO Flash USB 2.0 SD Ethernet Memory MAC x 10 Card
Pinning information ball A1 index area
PNX8550xE 2 4 6 8 10 12 14 16 18 20 22 24 26 1 3 5 7 9 11 13 15 17 19 21 23 25
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Transparent top view 18770_308_100217.eps 100217
Figure 8-6 Internal block diagram and pin configuration
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2012-Jun-29
EN 60 8.7
8.
IC Data Sheets
Q552.4E LA
Diagram 10-3-17 PNX 85500: Headphone B05I, TS489IST (IC 7NN1)
Block diagram VDD 8
VDD/2 2
IN 1−
3
BYPASS
VO1 1
− +
TPA6111A2 6
IN 2−
5
SHUTDOWN
VO2 7
− +
4
Bias Control
Pinning information D OR DGN PACKAGE (TOP VIEW)
VO1 IN1− BYPASS GND
1
8
2
7
3
6
4
5
VDD VO2 IN2− SHUTDOWN 18770_309_100217.eps 110602
Figure 8-7 Internal block diagram and pin configuration
2012-Jun-29
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IC Data Sheets 8.8
Q552.4E LA
8.
EN 61
Diagram 10-3-23 PNX 85500: Temperature sensor B05O, LM75BDP (IC 7USA)
Block diagram VCC
LM75B BIAS REFERENCE
POINTER REGISTER
CONFIGURATION REGISTER
BAND GAP TEMP SENSOR
COUNTER
TEMPERATURE REGISTER
TIMER
TOS REGISTER
COMPARATOR/ INTERRUPT
THYST REGISTER
11-BIT SIGMA-DELTA A-to-D CONVERTER
OSCILLATOR
POWER-ON RESET
OS
LOGIC CONTROL AND INTERFACE
A2
A1
A0
SCL SDA
GND
Pinning information
SDA
1
8
VCC
SCL
2
7
A0
6
A1
5
A2
OS
3
GND
4
LM75BDP
18770_300_100217.eps 100217
Figure 8-8 Pin configuration
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2012-Jun-29
EN 62 8.9
8.
IC Data Sheets
Q552.4E LA
Diagram 10-3-25 Class-D amplifier B06A, TAS5731PHP (IC 7D60)
Block diagram OUT_A 2 HB FET Out SDIN
Serial Audio Port
OUT_B
th
S R C
Digital Audio Processor (DAP)
4 -Order Noise Shaper and PWM
OUT_C 2 HB FET Out
OUT_D
Protection Logic MCLK SCLK LRCLK
SDA SCL
Sample Rate Autodetect and PLL
TAS5731
Click and Pop Control
Microcontroller Based System Control
Serial Control
Terminal Control
PGND_CD
PGND_CD
NC
OUT_C
BST_C
NC
NC
BST_B
NC
PGND_AB
OUT_B
PGND_AB
Pinning information
48 47 46 45 44 43 42 41 40 39 38 37
OUT_A
1
36
OUT_D
PVDD_AB
2
35
PVDD_CD
PVDD_AB
3
34
PVDD_CD
BST_A
4
33
BST_D
NC
5
32
GVDD_OUT
SSTIMER
6
31
VREG
NC
7
30
AGND
PBTL
8
AVSS
9
TAS5731 (Top View)
29
GND
28
DVSS
PLL_FLTM
10
27
DVDD
PLL_FLTP
11
26
STEST
VR_ANA
12
25
RESET
SCL
SDA
SDIN
SCLK
PDN
LRCLK
VR_DIG
DVSSO
OSC_RES
MCLK
A_SEL
AVDD
13 14 15 16 17 18 19 20 21 22 23 24
19220_086_120229.eps 120229
Figure 8-9 Internal block diagram and pin configuration
2012-Jun-29
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IC Data Sheets
Q552.4E LA
8.
EN 63
8.10 Diagram 10-3-26 USB hub B06B, CY7C65632-28LTXCT (IC 7FL5)
Block diagram ADDR
SCL
SDA
LNBH25
LX PWM CTRL
I2C Digital core DETIN DSQOUT
Tone detector DAC Drop control Tone ctrl Diagnostics Protections
FLT
Isense
DSQIN
PGND VUP
Current Limit selection
Linear Regulator
Gate ctrl
BPSW VOUT
Voltage reference
GND
BYP VCC
ISEL
Pinning information 24
NC
23
22
DSQOUT DSQIN/ DSQIN EXTM
21
20
19
VUP
VOUT
DETIN
1
NC
BPSW
18
2
FLT
VCC
17
3
LX-A LX
VBYP
16
LNBH25 4
PGND
GND
15
5
NC
NC
14
6
ADDR
NC
13
SCL
SDA
ISEL
NC
NC
NC
7
8
9
10
11
12
19220_027_120227.eps 120227
Figure 8-10 Internal block diagram and pin configuration
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2012-Jun-29
EN 64
8.
IC Data Sheets
Q552.4E LA
8.11 Diagram 10-3-27 Ethernet & service B06C, LAN8710A-EZKH (IC 7N10)
Block diagram MODE0 MODE1 MODE2 nRST
MODE Control
AutoNegotiation
10M Tx Logic
Management Control
100M Tx Logic
Reset Control
SMI
RMIISEL
HP Auto-MDIX
10M Transmitter
TXP / TXN
Transmit Section
RXP / RXN
100M Transmitter MDIX Control
TXD[0:3] TXEN TXER TXCLK
CRS COL/CRS_DV
RMII / MII Logic
RXD[0:3] RXDV RXER RXCLK
100M Rx Logic
DSP System: Clock Data Recovery Equalizer
PLL
Analog-toDigital
XTAL2
Interrupt Generator
nINT
100M PLL
Receive Section
LED Circuitry 10M Rx Logic
Squelch & Filters 10M PLL
MDC MDIO
XTAL1/CLKIN
LED1 LED2
Central Bias
RBIAS
PHY Address Latches
PHYAD[0:2]
RBIAS
RXP
RXN
TXP
TXN
VDD1A
RXDV
TXD3
32
31
30
29
28
27
26
25
Pinning information
VDD2A
1
24
TXD2
LED2/nINTSEL
2
23
TXD1
LED1/REGOFF
3
22
TXD0
XTAL2
4
21
TXEN
XTAL1/CLKIN
5
20
TXCLK
VDDCR
6
19
nRST
RXCLK/PHYAD1
7
18
nINT/TXER/TXD4
RXD3/PHYAD2
8
17
MDC
SMSC LAN8710/LAN8710i 32 PIN QFN (Top View)
13
14
15
16
COL/CRS_DV/MODE2
MDIO
VDDIO
CRS
12
RXD0/MDE0
RXER/RXD4/PHYAD0
10
11
RXD1/MODE1
9 RXD2/RMIISEL
VSS
18770_302_100217.eps 100217
Figure 8-11 Internal block diagram and pin configuration
2012-Jun-29
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IC Data Sheets
Q552.4E LA
8.
EN 65
8.12 Diagram 10-3-28 HDMI B06D, SiI9x87B (IC 7NC1)
Block diagram
Pinning information
18770_303_100217.eps 100217
Figure 8-12 Internal block diagram and pin configuration
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2012-Jun-29
EN 66
8.
Q552.4E LA
IC Data Sheets
8.13 Diagram 10-3-29 FPGA, power & control B07A, LD1117DT12 (IC 7J20)
Block diagram
LD1117DT
Pinning information
DPAK
F_15710_166.eps 100402
Figure 8-13 Internal block diagram and pin configuration
2012-Jun-29
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IC Data Sheets
Q552.4E LA
8.
EN 67
8.14 Diagram 10-3-31 Tuner, channel decoder B08A, CXD2834ER (IC 7KC0)
Block diagram MPEG Decoder
TUNER IF+ IF-
(RFAGC-MON)
TAINP (IF) TAINM (IF)
RFAIN
12-bit ADC
10-bit ADC
DVB-T2 Demodulator
LDPC/BCH Decoder
Stream Processor
TSCLK TSCLK TSVALID TSIF
(RFAGC)
GPIO1 (PWM)
TSSYNC
GPIO DVB-T Demodulator
IFAGC
SCL SDA
TIFAGC
TSDATA7-0 RS Decoder
AGC
DVB-C Demodulator
TSDATA7-0
TS Smoothing
SCL
TTUSCL I2C IF
TTUSDA
41MHz or 20.5 MHz
TSVALID TSSYNC
SDA
SCL SDA
OSC PLL XTALI XTALO
Pinning information
19220_025_120227.eps 120227
Figure 8-14 Internal block diagram and pin configuration
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EN 68
8.
Q552.4E LA
IC Data Sheets
8.15 Diagram 10-3-32 DVBS, FE B08B, STV6110AT (IC 7RA0)
Block diagram STV6110AT
RF_OUT IP
RF_IN
IN QP AGC QN PLL, dividers XTAL_IN XTAL_INN
DC offset compensation SCL 2
I C bus interface
Amplifier
SDA
XTAL_OUT
18770_304_100217.eps 110601
Figure 8-15 Internal block diagram and pin configuration
2012-Jun-29
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Block Diagrams
Q552.4E LA
9.
EN 69
9. Block Diagrams 9.1
Wiring diagram 4000 series 32"
WIRING DIAGRAM 32" 4000 Series
DISPLAY PANEL
1316
(SP02)
14P 3P
1D02
14P
1M95
1M95
WOOFER
1G51
(1053)
51P
MAIN POWER SUPPLY
B
SSB (1150)
1D01
4P
1C20
11P
E1M95
MOD CONTROL BOARD (Q1057)
E1G51
TO DISPLAY
INLET
TWEETER
TWEETER
(SP01)
(SP01)
SENSOR BOARD (Q1056)
1M95 (B01A) 1. +3V3STBY 2. STANDBY 3. GND 4. GND 5. +12Vin 6. +12Vin 7. +12VAUDIO 8. +12VAUDIO 9. GND 10. GND 11. BL-ON-1 12. BL-DIM-1 13. BL-I-CTRL-1 14. POWER-OK-1
1C20 (B01B) 1G51 (B09A) 1. +VDISP 2. +VDISP 3. +VDISP 4. +VDISP | | 51.
1. LIGHT-SENSOR 2. 3D-LED 3. LED-2 4. GND 5. KEYBOARD 6. +3V3-STANDBY 7. RC 8. +5V 9. SCL-SET 10. GND 11. SDA-SET
1D01 (B06A)
1D02 (B06A)
1. 2. 3. 4.
1. LEFT-+ 2. GND 3. RIGHT--
LEFT-+ LEFT-RIGHT-+ RIGHT--
19220_018_120224.eps 120224
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Block Diagrams 9.2
Q552.4E LA
9.
EN 70
Wiring diagram 4000 series 37"
WIRING DIAGRAM 37" 4000 Series
E1M95
DISPLAY PANEL
1316
WOOFER (SP02)
14P 3P
1D02
14P
1M95
1M95
1G51
(1053)
51P
MAIN POWER SUPPLY
1D01
4P
1C20
11P
MOD CONTROL BOARD (Q1057)
B
SSB (1150)
E1G51
TO DISPLAY
INLET
TWEETER
TWEETER
(SP01)
(SP01)
SENSOR BOARD (Q1056)
1M95 (B01A) 1. +3V3STBY 2. STANDBY 3. GND 4. GND 5. +12Vin 6. +12Vin 7. +12VAUDIO 8. +12VAUDIO 9. GND 10. GND 11. BL-ON-1 12. BL-DIM-1 13. BL-I-CTRL-1 14. POWER-OK-1
1C20 (B01B) 1G51 (B09A) 1. +VDISP 2. +VDISP 3. +VDISP 4. +VDISP | | 51.
1. LIGHT-SENSOR 2. 3D-LED 3. LED-2 4. GND 5. KEYBOARD 6. +3V3-STANDBY 7. RC 8. +5V 9. SCL-SET 10. GND 11. SDA-SET
1D01 (B06A)
1D02 (B06A)
1. 2. 3. 4.
1. LEFT-+ 2. GND 3. RIGHT--
LEFT-+ LEFT-RIGHT-+ RIGHT--
19220_019_120224.eps 120224
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Block Diagrams 9.3
Q552.4E LA
9.
EN 71
Wiring diagram 4000 series 42"
WIRING DIAGRAM 42" 4000 series
DISPLAY PANEL
1316
MAIN POWER SUPPLY
E1M95
14P 3P
(SP02)
1M95 14P
WOOFER
1D02
1M95
51P
1G51
(1053)
B
SSB (1150)
1D01
4P
1C20
11P
MOD CONTROL BOARD (Q1057)
INLET
E1G51
TO DISPLAY
TWEETER (SP01)
TWEETER (SP01) SENSOR BOARD (1122) SENSOR BOARD (Q1056) 1M95 (B01A) 1. +3V3STBY 2. STANDBY 3. GND 4. GND 5. +12Vin 6. +12Vin 7. +12VAUDIO 8. +12VAUDIO 9. GND 10. GND 11. BL-ON-1 12. BL-DIM-1 13. BL-I-CTRL-1 14. POWER-OK-1
1C20 (B01B) 1G51 (B09A) 1. +VDISP 2. +VDISP 3. +VDISP 4. +VDISP | | 51.
1. LIGHT-SENSOR 2. 3D-LED 3. LED-2 4. GND 5. KEYBOARD 6. +3V3-STANDBY 7. RC 8. +5V 9. SCL-SET 10. GND 11. SDA-SET
1D01 (B06A)
1D02 (B06A)
1. 2. 3. 4.
1. LEFT-+ 2. GND 3. RIGHT--
LEFT-+ LEFT-RIGHT-+ RIGHT--
19220_020_120224.eps 120224
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Block Diagrams 9.4
Q552.4E LA
9.
EN 72
Wiring diagram 4000 series 47"
WIRING DIAGRAM 47" 4000 series
DISPLAY PANEL
MAIN POWER SUPPLY
E1M95
14P 3P
(SP02)
1M95 14P
WOOFER
1D02
1M95
51P
1G51
(1053)
B
SSB (1150)
1D01
4P
1C20
11P
MOD CONTROL BOARD (Q1057)
INLET
E1G51
TO DISPLAY
TWEETER (SP01)
TWEETER (SP01) SENSOR BOARD (1122) SENSOR BOARD (Q1056) 1M95 (B01A) 1. +3V3STBY 2. STANDBY 3. GND 4. GND 5. +12Vin 6. +12Vin 7. +12VAUDIO 8. +12VAUDIO 9. GND 10. GND 11. BL-ON-1 12. BL-DIM-1 13. BL-I-CTRL-1 14. POWER-OK-1
1C20 (B01B) 1G51 (B09A) 1. +VDISP 2. +VDISP 3. +VDISP 4. +VDISP | | 51.
1. LIGHT-SENSOR 2. 3D-LED 3. LED-2 4. GND 5. KEYBOARD 6. +3V3-STANDBY 7. RC 8. +5V 9. SCL-SET 10. GND 11. SDA-SET
1D01 (B06A)
1D02 (B06A)
1. 2. 3. 4.
1. LEFT-+ 2. GND 3. RIGHT--
LEFT-+ LEFT-RIGHT-+ RIGHT--
19220_021_120224.eps 120224
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Block Diagrams 9.5
Q552.4E LA
9.
EN 73
Wiring diagram 5000 & 5500 series 32"
WIRING DIAGRAM 32" 5000 and 5500 Series
8M95 DISPLAY PANEL
1M95
1M95
WOOFER 1D02
(5214)
14P 3P
1316
14P
1G51
(1005)
51P
MAIN POWER SUPPLY
1C30 1D01
8G51
41P
(1150)
4P
8G50
1308
SSB
4P
2p3
1G50
B
TO DISPLAY
8C20
11P
1C20
TO DISPLAY
INLET
MOD CONTROL BOARD
(1114)
8308
TWEETER
TWEETER
(5216)
(5216) 8F24
WIFI (1115)
SENSOR BOARD (1122)
1M95 (B01A) 1. +3V3STBY 2. STANDBY 3. GND 4. GND 5. +12Vin 6. +12Vin 7. +12VAUDIO 8. +12VAUDIO 9. GND 10. GND 11. BL-ON-1 12. BL-DIM-1 13. BL-I-CTRL-1 14. POWER-OK-1
1C20 (B01B) 1G50 (B09A) 1. GND 2. GND | | | | 41.
1G51 (B09A) 1. +VDISP 2. +VDISP 3. +VDISP 4. +VDISP | | 51.
1. LIGHT-SENSOR 2. 3D-LED 3. LED-2 4. GND 5. KEYBOARD 6. +3V3-STANDBY 7. RC 8. +5V 9. SCL-SET 10. GND 11. SDA-SET
1D01 (B06A)
1D02 (B06A)
1C30 (B06B)
1. 2. 3. 4.
1. LEFT-+ 2. GND 3. RIGHT--
1. 2. 3. 4.
LEFT-+ LEFT-RIGHT-+ RIGHT--
2012-Jun-29 back to
div. table
+5V USB-WIFI-DDn USB-WIFI-DDp GND
19220_006_120215.eps 120223
Block Diagrams 9.6
Q552.4E LA
9.
EN 74
Wiring diagram 5000 & 5500 series 40"
WIRING DIAGRAM 40" 5000 and 5500 Series
DISPLAY
8M95
PANEL
WOOFER 1M95 14P
1G51 51P
1D02 3P
(5214)
1M95 14P
1G50 41P
1316
SSB (1150)
8G50
8308
MAIN POWER SUPPLY
1C30 4P
1D01 4P
INLET
B
8G51
2p3
1308
TO DISPLAY
TO DISPLAY
8C20
MOD CONTROL BOARD
(1114)
1C20 11P
(1005)
TWEETER
TWEETER
(5216)
(5216)
8F24
WIFI (1115)
SENSOR BOARD (1122)
1M95 (B01A) 1. +3V3STBY 2. STANDBY 3. GND 4. GND 5. +12Vin 6. +12Vin 7. +12VAUDIO 8. +12VAUDIO 9. GND 10. GND 11. BL-ON-1 12. BL-DIM-1 13. BL-I-CTRL-1 14. POWER-OK-1
1C20 (B01B) 1G50 (B09A) 1. GND 2. GND | | | | 41.
1G51 (B09A) 1. +VDISP 2. +VDISP 3. +VDISP 4. +VDISP | | 51.
1. LIGHT-SENSOR 2. 3D-LED 3. LED-2 4. GND 5. KEYBOARD 6. +3V3-STANDBY 7. RC 8. +5V 9. SCL-SET 10. GND 11. SDA-SET
1D01 (B06A)
1D02 (B06A)
1C30 (B06B)
1. 2. 3. 4.
1. LEFT-+ 2. GND 3. RIGHT--
1. 2. 3. 4.
LEFT-+ LEFT-RIGHT-+ RIGHT--
2012-Jun-29 back to
div. table
+5V USB-WIFI-DDn USB-WIFI-DDp GND
19220_013_120223.eps 120223
Block Diagrams 9.7
Q552.4E LA
9.
EN 75
Wiring diagram 5000 & 5500 series 46"
WIRING DIAGRAM 46" 5000 and 5500 Series
DISPLAY PANEL
8M95
1316
1M95 14P
WOOFER (5214)
MAIN POWER SUPPLY
8G50
B
SSB (1150)
1D01 4P
2p3
1M95 14P
1G50 41P
8G51
1G51 51P
1D02 3P
(1005)
1C20 11P
1C30 4P
1308
8308
TO DISPLAY
TO DISPLAY
8C20
MOD CONTROL BOARD (1114)
INLET
TWEETER
TWEETER
(5216)
(5216)
8F24
WIFI (1115)
SENSOR BOARD (1122)
1M95 (B01A) 1. +3V3STBY 2. STANDBY 3. GND 4. GND 5. +12Vin 6. +12Vin 7. +12VAUDIO 8. +12VAUDIO 9. GND 10. GND 11. BL-ON-1 12. BL-DIM-1 13. BL-I-CTRL-1 14. POWER-OK-1
1C20 (B01B) 1G50 (B09A) 1. GND 2. GND | | | | 41.
1G51 (B09A) 1. +VDISP 2. +VDISP 3. +VDISP 4. +VDISP | | 51.
1. LIGHT-SENSOR 2. 3D-LED 3. LED-2 4. GND 5. KEYBOARD 6. +3V3-STANDBY 7. RC 8. +5V 9. SCL-SET 10. GND 11. SDA-SET
1D01 (B06A)
1D02 (B06A)
1C30 (B06B)
1. 2. 3. 4.
1. LEFT-+ 2. GND 3. RIGHT--
1. 2. 3. 4.
LEFT-+ LEFT-RIGHT-+ RIGHT--
2012-Jun-29 back to
div. table
+5V USB-WIFI-DDn USB-WIFI-DDp GND
19220_008_120223.eps 120223
Block Diagrams 9.8
Q552.4E LA
9.
EN 76
Wiring diagram 5000 series 55"
WIRING DIAGRAM 55" 5000 and 5500 series
DISPLAY PANEL
8M95
1M95 14P
MAIN POWER SUPPLY
14P 3P
1D02
1M95
51P
1G51
(1005)
B
SSB
1D01
4P
41P
(1150)
TO DISPLAY
INLET
8C20
TO DISPLAY
4P
MOD CONTROL BOARD (1114)
8G51 8308
11P
(5214)
1C30
WOOFER
1C20
8G50
1308
1G50
2p3
TWEETER (5216)
TWEETER (5216) 8F24
SENSOR BOARD (1122) SENSOR BOARD (1122)
WIFI (1115) 1M95 (B01A) 1. +3V3STBY 2. STANDBY 3. GND 4. GND 5. +12Vin 6. +12Vin 7. +12VAUDIO 8. +12VAUDIO 9. GND 10. GND 11. BL-ON-1 12. BL-DIM-1 13. BL-I-CTRL-1 14. POWER-OK-1
1C20 (B01B) 1G50 (B09A)
1G51 (B09A)
1. GND 2. GND | | | | 41.
1. +VDISP 2. +VDISP 3. +VDISP 4. +VDISP | | 51.
1. LIGHT-SENSOR 2. 3D-LED 3. LED-2 4. GND 5. KEYBOARD 6. +3V3-STANDBY 7. RC 8. +5V 9. SCL-SET 10. GND 11. SDA-SET
1D01 (B06A)
1D02 (B06A)
1C30 (B06B)
1. 2. 3. 4.
1. LEFT-+ 2. GND 3. RIGHT--
1. 2. 3. 4.
LEFT-+ LEFT-RIGHT-+ RIGHT--
2012-Jun-29 back to
div. table
+5V USB-WIFI-DDn USB-WIFI-DDp GND
19220_096_120301.eps 120301
Block Diagrams 9.9
Q552.4E LA
9.
EN 77
Block Diagram Video
VIDEO B05G
COMMON INTERFACE
B05
1P00 17
+5VCA
18 51 52
7F01 74LVC245APW 20
VIDEO OUT - LVDS 1G50 32 PX1
B05J VIDEO OUT-LVDS
TO DISPLAY +3V3
68P
PCMCIA
B09A
PNX85500
7S00 PNX85637EB
B05F CONDITIONAL ACCESS
LOUT1 PX2
CONDITIONAL ACCESS
MDO(0-7)
BUFFER
CA-MDO(0-7)
ONLY 5000 SERIES 100Hz PANEL SSB 3139 123 6532x
3
MD0
CA-MDI(0-7)
1G51 40
LOUT2
MDI
PX3
B08B
DVBS-FE
7RA0 STV6110A 1R01
DVB-S TUNER
4 SAT IN 30 16M
1RA0
B08A
7RA1 STV0903BAC
31
DVB-S CHANNEL 8 DECODER
21
IP
20 32 18
XTAL QP
122 12
19
QM
11
2
AGC
16
7
IM
TUNER-CHANNEL DECODER
TO DISPLAY
9RC2-1
78 75 74
TS-INT-VALID TS-INT-SOP TS-INT-CLOCK
9RC2-2
73
TS-INT-DATA
9RC2-3
TS-CHDEC-VALID TS-CHDEC-SOP TS-CHDEC-CLK
9RC2-4
PX4
R23 TNR_SER1_MIVAL R22 TNR_SER1_SOP T22 TNR_SER1_MICLK T21 TNR_SER1_DATA
TS-CHDEC-DATA
OR
B10A
FPGA I/O BANKS
11
7K01 XC65LX25
ONLY x000 SERIES SSB 3139 123 6532x
1G50 32
7KC0 CXD2834R
PX1
PX1
PX2
PX2
LOUT3
TO DISPLAY
ONLY **PFL***7/K**
TUNER-CHANNEL DECODER
DVBT2 CHANNEL DECODER
1F00 SUT-RE214Z
AGC2
B06D
3 5KC9
3KA1 IF-P-DVBT2
5KC0 2KCE 3KCA
38
3FA4
3S4V
7 5FA4
3FA3
3S4W
26
DRX2DRX1+
25 24
DRX1DRX0+
23 RXD 22
AF12
DRX0-
21
DRXC+
20
12
DRXC-
19
ARX2ARX1+
71 70
ARX1ARX0+
69 RXA 68
65
7N06 EF
CVBS-MON-OUT1 AV1-STATUS
PX3
PX4
PX4
AV1-BLK
AF11
CVBS1_OUT
B05B STANDBY CONTROLLER
R-VGA G-VGA B-VGA H-SYNC-VGA
1
11
V-SYNC-VGA
1
BRX2+
8
3
BRX2BRX1+
7 6
BRX1BRX0+
5 RXB 4
BRX0-
3
BRXC+
2
12
BRXC-
1
B05M
B05B STANDBY CONTROLLER
EXT 3
1M54 1
AF24 AE23
PNX-SPI-CLK PNX-SPI-SDO
67 66
AF25 AF23
PNX-SPI-SDI PNX-SPI-CS-BLn
62 61
9
FPGA BL
B01B
USB HUB 7FL5 CY7C65632
+5V-USB1 1P08 1
4 B05C MIPS
USB_DN USB_DP
R26
USB-DM
1
R25
USB-DP
2
+5V-USB2 1P07 1
AV3-PR
AD15 AC15
PB_B1
B05F
4
+5V-USB3 1P06 1
NANDFLASH
XIO_D
E21 NAND-CE1n F21 NAND-RDY1n NAND-WPn A21
B05E SDRAM
B04A VREF_1 VREF_2
A2 V1
4
NAND FLASH
XIO-D(00-07)
11
9 7 19
+5V
3
10
4
DDR2-D(0-31)
13 12
12
CRXC-
11
+3V3-HDMI
9,27,64
VCC33
HDMIA-RX0HDMIA-RX1+ HDMIA-RX1HDMIA-RX2+ HDMIA-RX2-
A1 E2 A
A1 E2
SDRAM 128Mx8
A1 E2
D(24-31)
SDRAM 128Mx8
D(16-23)
SDRAM 128Mx8
7B02 EDE1108AGBG
7B03 EDE1108AGBG
SDRAM 128Mx8 VDDL VREF
CRX0CRXC+
HDMIA-RX0+
7B01 EDE1108AGBG
VDDL VREF
9 10
RXC
W25 RXC_A_P W26 RXC_A_N V25 RX2_A_P V26 RX2_A_N U25 RX1_A_P U26 RX1_A_N T25 RX0_A_P T26 RX0_A_N W24 RREF
7B00 EDE1108AGBG
VDDL VREF
15 14
HDMIA-RXC+ HDMIA-RXC-
2 3 4 5
USB-WIFI-DDn USB-WIFI-DDP
+3V3
D(8-15)
CRX1CRX0+
B05E HDMI_DV 62 TXC_P 63 TXC_N 60 TX0_P 61 TX0_N 58 TX1_P 59 TX1_N 56 TX2_P 57 TX2_N
SIDE USB CONNECTOR
DDR
VDDL VREF
17 16
4 6 7
1C30 1
DDR2-VREF-CTRL2 DDR2-VREF-CTRL3
D(0-7)
18
CRX2CRX1+
2 3
USB3-DM USB3-DP
6 7
PR_R_C1
3S0W
1 2 19 18
HDMI 1 CONNECTOR
CRX2+
2 3
USB2-DM USB2-DP
12 13
USB HUB
VCC 12,37
AV3-PB
2 3
USB1-DM USB1-DP
15 16
DQ
3
5 RES
B06B
1P02 1
1A04 3
26AMBI-SPI-OUT-CCLK
ANALOGUE EXTERNALS B
Y_G1
INTERFACE CONNECTORS
27AMBI-SPI-OUT-MOSI
AF16 VGA_R AD16 VGA_G AE16 VGA_B AB18 HSYNC_IN AC18 VSYNC_IN
AE15
TO PSU
BL-DIM1-8
NAND_CE1 NAND_RDY1 NAND_WP_
AV3-Y
POWER CONNECTORS
7J01 XC65LX4
7S0A H27U4G8F2DTR
1 3 13 14
B01A
FPGA - I/O BANKS
1N05
VGA CONNECTOR
1P03
9 10
B07B
VGA 2
11 ONLY 5500 SERIES SSB 3139 123 6530x
B05F NANDFLASH
B05N
5
19 18
66
ARXC-
IF_AGC
HDMI SWITCH
3
ARXC+
6
7N05 EF
7N03
72
12
AD12
9
ARX2+
HDMI 3 CONNECTOR
EXT 1
AV1-CVBS
17
1
67
TUNER_N
AC13 AV1_R AE13 AV1_G AD13 AV1_B AB15 CVBS_Y1
AV1-B
5
10
1 2
SOC-IF-N
AV1-R AV1-G
18
15
9 10
ARX0-
1 2
2S78
TUNER_P
1VA1
6
1 2 19 18
DRX2+
3
9 10
19 18
AE12
ANALOGUE EXTERNALS A
10 14
1
1P04
HDMI 2 CONNECTOR
SOC-IF-P
SOC-IF-AGC
1P05
4 6 7
2S77
9
B05L
4 6 7
PX3
TO DISPLAY
PNX85500: ANALOG VIDEO
8 5FA5
7NC1 SII9287BC
HDMI SIDE CONNECTOR
B05K ANALOG VIDEO
ONLY **PFL***7/T**
B05K
HDMI
4 6 7
TS-CHDEC-DATA
1
IF2-_P
37
3 2
IF2-_N
5KC1 2KCF 3KCB
4
MAIN HYBRID TUNER
3KA0 IF-N-DVBT2
1G51 40
12M
RF IN
48
2 5KC8
3
FPGA 2D>3D BL
LOUT4
1FL5
IF1-_N
IF_AGC
4
TS-CHDEC-VALID TS-CHDEC-SOP TS-CHDEC-CLK
PNX85637
AGC1 IF1-_P
4 3 5 8
3S4U
B08A
A1 E2 DDR2-A(0-14) +1V8 DDR2-VREF-DDR
+3V3 19220_003_111223.eps 111223
2012-Jun-29 back to
div. table
Block Diagrams 9.10
Q552.4E LA
9.
EN 78
Block Diagram Audio
AUDIO COMMON INTERFACE
B05
1P00 17
+5VCA
18 51 52
7F01 74LVC245APW 20
CONDITIONAL ACCESS
MDO(0-7)
+3V3
B05F CONDITIONAL ACCESS
CA-MDO(0-7)
BUFFER
1R01
DVB-S TUNER
4 SAT IN
21
30 16M
1RA0
B08A
7RA1 STV0903BAC
31
20 32 18
XTAL QP
122 12
19
QM
11
2
AGC
16
IM
5D75
WS AD2 I2S_OUT_SD1 AE1 SCK AD1
MD0
WSI2SOUT
20
SDI2SOUT1
22 9D53
I2SCLK
TUNER-CHANNEL DECODER 9RC2-1
78 75 74
TS-INT-VALID TS-INT-SOP TS-INT-CLOCK
9RC2-2
73
TS-INT-DATA
9RC2-3
9RC2-4
TS-CHDEC-VALID TS-CHDEC-SOP TS-CHDEC-CLK
R23 TNR_SER1_MIVAL R22 TNR_SER1_SOP T22 TNR_SER1_MICLK T21 TNR_SER1_DATA
TS-CHDEC-DATA
P0.6
21
5D80
R-
5D72 5D71
AB19
AA22
1D01 1
L+
6D60
RESET-AUDIO
7D50-2 25
CLASS D POWER AMPLIFIER
DETECT2
46 L39 R+ 36 R-
5D81
L-
DVBT2 CHANNEL DECODER 5KC1 2KCF 3KCB
37
3 5KC9
3KA1 IF-P-DVBT2
5KC0 2KCE 3KCA
38
5D83
AGC2
8 5FA5
3S4V
7 5FA4
3FA3
3S4W
1 2 19 18
DRX2+
26
3
DRX2DRX1+
25 24
DRX1DRX0+
23 RXD 22
DRX0-
21
9 10
DRXC+
20
12
DRXC-
19
1P04
1 2
B05K ANALOG VIDEO
R-
2S77 2S78
72
3
ARX2ARX1+
71 70
ARX1ARX0+
69 RXA 68
19 18
67
ARXC+
66
HDMI 3 CONNECTOR
12
ARXC-
65
AF12 AD12
TUNER_N IF_AGC
AF10 AIN1_R AE10 AIN1_L
ANALOGUE EXTERNALS B 1VA4
HDMI SWITCH
ARX2+
ARX0-
SOC-IF-N SOC-IF-AGC
TUNER_P
AV1_B
1
9 10
AE12
SOC-IF-P
AUDIO-IN1-R AUDIO-IN1-L
CVBS_Y1 AF9
AUDIO-IN3-R
YPbPr AUDIO
AIN3_R AE9 AIN3_L
AUDIO-IN3-L
1N09
AC9
AUDIO-IN4-R
PC AUDIO
AIN4_R AD9 AIN4_L
AUDIO-IN4-L
B05H
+3V3
SPDIF-OPT
7S09 2 & 1
1 2 19 18
HDMI 2 CONNECTOR
BRX2+
8
3
BRX2BRX1+
7 6
BRX1BRX0+
5 RXB 4
9 10
BRX0-
3
BRXC+
2
12
BRXC-
1
7NN1-1,2 B05H PNX85500 AUDIO
ADAC3 ADAC4
5
SEL-HDMI-ARC
AF7
ADAC(3)
2
AD6
ADAC(4)
6
AMPLIFIER
1NN2
1 7
HEADPHONE OUT 3.5 mm
B06B
USB HUB 7FL5 CY7C65632
+5V-USB1 1P08 1
P0_4
4
USB_DN USB_DP
R26
USB-DM
1
R25
USB-DP
2
+5V-USB2 1P07 1
B05F
4
+5V-USB3 1P06 1
NANDFLASH
NAND_CE1 NAND_RDY1 NAND_WP_
E21 NAND-CE1n F21 NAND-RDY1n NAND-WPn A21
B04A VREF_1 VREF_2
A2 V1
11
9 7 19
+5V
3
10
4 VCC 12,37
B05E SDRAM
4
NAND FLASH
XIO-D(00-07)
DDR2-D(0-31)
12
CRXC-
11 9,27,64
VCC33
HDMIA-RX0HDMIA-RX1+ HDMIA-RX1HDMIA-RX2+ HDMIA-RX2-
+3V3-HDMI ARC-eHDMI+
5CN2
eHDMI+
A1 E2 A
A1 E2
SDRAM 128Mx8
A1 E2
D(24-31)
D(16-23)
SDRAM 128Mx8
7B02 EDE1108AGBG
7B03 EDE1108AGBG
SDRAM 128Mx8 VDDL VREF
12 14
13
SDRAM 128Mx8
7B01 EDE1108AGBG
VDDL VREF
HDMI 1 CONNECTOR
CRX0CRXC+
HDMIA-RX0+
7B00 EDE1108AGBG
VDDL VREF
9 10
RXC
2 3 4 5
USB-WIFI-DDn USB-WIFI-DDP
+3V3
D(8-15)
15 14
W25 RXC_A_P W26 RXC_A_N V25 RX2_A_P V26 RX2_A_N U25 RX1_A_P U26 RX1_A_N T25 RX0_A_P T26 RX0_A_N W24 RREF
SIDE USB CONNECTOR
DDR
VDDL VREF
CRX1CRX0+
B05E HDMI_DV HDMIA-RXC+ HDMIA-RXC-
62 TXC_P 63 TXC_N 60 TX0_P 61 TX0_N 58 TX1_P 59 TX1_N 56 TX2_P 57 TX2_N
1C30 1
DDR2-VREF-CTRL2 DDR2-VREF-CTRL3
D(0-7)
17 16
4 6 7
3S0W
18
CRX2CRX1+
19 18
1 2
CRX2+
2 3
USB3-DM USB3-DP
DQ
3
2 3
USB2-DM USB2-DP
12 13
USB HUB
1P02 1
2 3
USB1-DM USB1-DP
15 16
B05C MIPS
AF5 SPDIF-OUT AF18
2.0
5
XIO_D SPDIF-OUT-PNX
4
7NN1 TS489
6 7
B02G STANDBY 8
1P03 1
HEADPHONE
PNX85500 AUDIO
3
5D80
7S0A H27U4G8F2DTR
4
4 6 7
B05I
+3V3 1N10 2 1 3
3
SPEAKER R
B05F NANDFLASH
SPDIF OUT
2 SPEAKER L
AV1_G
B05M
5D75
LR+
B05H PNX85500 AUDIO
23 19
ACTIVE 2.1
1D01 1
L+
1VA1 EXT 1
1
4 6 7
TS-CHDEC-DATA
ANALOGUE EXTERNALS A
7NC1 SII9287BC
HDMI SIDE CONNECTOR
8
9
1P05
SPEAKER WOOFER
5D77
PNX85500: ANALOG VIDEO
3FA4
B05L
4 6 7
TS-CHDEC-VALID TS-CHDEC-SOP TS-CHDEC-CLK
ONLY **PFL***7/T**
HDMI
3
4
12M
IF2-_P
4 3 5
1FL5
IF2-_N
B06D
48
3KA0 IF-N-DVBT2
B05K
MAIN HYBRID TUNER
2
SPEAKER L 3
R+ R-
PNX85637
RF IN
IF_AGC
2 5KC8
3S4U
IF1-_P IF1-_N
1D02 1
2
SPEAKER R
1F00 SUT-RE214Z 4
PASSIVE 2.1
19
7KC0 CXD2834R
TUNER-CHANNEL DECODER
AGC1
SPEAKER WOOFER
SPEAKER R
ONLY **PFL***7/K**
B08A
3
4
7D61 AUDIO-MUTE-UP
7D50-1 P3.2
2
SPEAKER L 3
R+
9D52 15 B05B STANDBY CONTROLLER P0.7 AC19
MDI
1D02 1
2
1 L+
DVB-S CHANNEL 8 DECODER 7
IP
L+
1
7RA0 STV6110A
1D01 1
3 2
DVBS-FE
5D78 7D60 TAS5731
L-
CA-MDI(0-7)
B08B
CLASS-D AMPLIFIER
B05H PNX85500 AUDIO
68P
PCMCIA
B06A
PNX85500
7S00 PNX85637EB
4
B05G
A1 E2 DDR2-A(0-14) +1V8 DDR2-VREF-DDR
+3V3 19220_002_111223.eps 111223
2012-Jun-29 back to
div. table
Block Diagrams 9.11
Q552.4E LA
9.
EN 79
Block Diagram Control & Clock Signals
CONTROL + CLOCK SIGNALS
RXD TXD
ETH-RXCLK
AA3
20
ETH-TXCLK
AA2
RXCLK TXCLK
7B02 H5PS1G83EFR
SDRAM 128Mx8
SDRAM 128Mx8
F8 E8
F8 E8
7B03 H5PS1G83EFR
SDRAM 128Mx8
B01A
7B01 H5PS1G83EFR
B05C
F8 E8
CLK_N CLK_P
B05C CONTROL
RXD1-MIPS
Y23
3
TXD1-MIPS
Y24
B07B B10A
B07B
B07A
FPGA-I/O BANKS
FPGA PWR & CTL 7J26 NCP803
TS-INT-DATA TS-INT-CLK
9RC2-4 9RC2-2 9RC2-1
TS-INT-SOP TS-INT-VALID RESET-DVBS
T21 T22
TS-CHDEC-SOP TS-CHDEC-VALID
TNR_SER1_DATA TNR_SER1_MICLK
R22 TNR_SER1_SOP R23 TNR_SER1_MIVAL
36 37
4 TS-CHDEC-VALID TS-CHDEC-SOP 3 DVBT2 CHANNEL 5 TS-CHDEC-CLOCK
DECODER 8
TS-CHDEC-DATA
29
RESET-FUSION-OUTn
COMMON INTERFACE 7F00
1P00 1 20
MOCLK
CA-MOCLK
K24
62 63
MOVAL MOSTRT
CA-MOVAL CA-MOSTRT
L23 L22
VS_2 MOVAL MOSTRT MDI
PCMCIA
CONDITIONAL ACCESS
+3V3
MDO(0-7)
COMMON INTERFACE
7S0A H27U4G8F2DTR
MDO
CA-MDO(0-7) 7F02 7F03
B05F FLASH
CA-A(00-14)
XIO-A(0-15)
XIO_A
7F04 7F05
CA-D(0-7)
XIO_D
XIO-D(00-15)
B05C PNX-SPI-CS-BLn PNX-SPI-CLK PNX-SPI-SDI
D11
PNX-SPI-SDO
D12
7K22 M25P40
E11
GPIO_7
RESET_SYS
BL-DIM1
F9
B05C
3D-LR
17
B05C
3D-LR
F12
46
B09A
5500 SERIES
PNX-SPI-CS-BLn
AE4
RESET-SYSTEMn
AD5
BL-DIM
9U41
LED2
AC25 PWM_1
KEYBOARD
AD23 P5_0
RC
AD19 P1_0
+3V3-STANDBY
8
+5V
10
B01B
LED-1
7U43 EF
BL-ON STANDBY POWER-OK BL-I-CTRL
USB_DM USB_DP
BL-DIM
B05C
4000 AND 5000 SERIES 9U43
BL-DIM1 B07B B10A 5500 SERIES
B05P B08B B06C B06B
BL-PWM B09A
B01A B05L
ENABLE-3V3-5V ENABLE-1V8 DETECT2
B02C
B02E
B02A
B06A
B05B B06A
B06A
CSO-B-LX25
1
PQ-FPGA SW
5500 SERIES
B08A
USB-DM
1
R25
USB-DP
2
V23
BL-I-CTRL-PNX
GPIO_1
Y22
3D-LR
+5V-USB1 1P08 1 2 3
USB1-DM USB1-DP
15 16
+5V-USB2 1P07 1
B05D
4
B07B B09A B10A
+5V-USB3 1P06 1
HDMI SWITCH
3S0W +3V3
45
DRX-HOTPLUG 1P05-19
4 11
+5V 3
10 19 18
RREF W24
41
TO PIN: ARX-HOTPLUG 1P02-19 BRX-HOTPLUG 1P03-19 CRX-HOTPLUG 1P04-19
31 35
P1_2 AF19
B05B
B05D
PNX85500: STANDBY CONTROLLER
1C30 1
SIDE USB CONNECTOR
2 3 4 5
USB-WIFI-DDn USB-WIFI-DDP
4
1P02-13 4x HDMI 1P03-13 PCEC-HDMI 1P04-13 CONNECTOR 1P05-13
7NC0 EF
CEC-HDMI
2 3
USB3-DM USB3-DP
6 7
HDMIA-RX
2 3
USB2-DM USB2-DP
12 13
USB HUB
B06D HDMI
AV1-STATUS
PNX85500-CONTROL
P2_0 P0_1
P0_4
AE18 P0_3 AD18 P1_1
P3_0
AC20
RESET-DVBS
AA18
RESET-ETHERNETn RESET-USBn DETECT2
CADC_2
AA22 P3_2
AV1-BLK
AD22 P3_5
RESET-SYSTEMn
AB22 P3_3
RESET-AUDIO
AB19 P0_6
AUDIO-MUTE-UP
AC19
ENABLE-3V3n
AD21
B09A B09A 7F52 M25P05-AVMN6P
SPI_CSB SPI_SDO SPI_SDI
LCD-PWR-ONn
B09A
CTRL-DISP2 CTRL-DISP3 B07B B10A
P2_2 AF20 P2_3 AC21 P2_6
AE25
CTRL-DISP1
AA21 AB21 AB17
AE20
SPI_CLK P6_5 B05L
T3
FLASH 16Mbit
P12
7FL5 CY7C65632
R26
GPIO_10
P2_5 P0_0
B05D 9U44
6
B07B B10A
P3_1 P1_7 RESET_IN P6_4
PNX-SPI-CLK
6
AE22 AF23 AE23
PNX-SPI-WPn
3
AF25
PNX-SPI-CSBn PNX-SPI-SDO PNX-SPI-SDI
1 5 2
AF18
SEL-HDMI-ARC
AE21 AF21 AB20 AA26
RXD-UP
XTAL_IN
XTAL_OUT
VCC
8
+3V3-STANDBY
STANDBY SW 1F51 3 1 LEVEL SHIFTED 2 FOR DEBUG USE 4 ONLY 5
TXD-UP
AF22
FF04 SDM FF29 SPI-PROG
7S20 NCP303LSN28G
AE17
AF17
FLASH 512K
B05H
SDM RESET-STBYn SPI-PROG +3V3-STANDBY
P0_7 P2_7
AF24
1S02
B05B
2 5
CCLK-LX25
AD26 PWM_0
LED1
PNX85500: STANDBY CONTROLLER
1M95 11
MOSI-LX25
R11
4 BL_PWM
P2_4
POWER CONNECTORS
BL-DIM-1
RESET-FUSION-OUTn
MISO-LX25
T10
USB HUB
B07B B10A cS53
P10
5500 SERIES
B06B
PNX85500: MIPS
V22
3D-LR-DISP
B07B B10A
LED-2
6 7
AE26 P5_1
B05B
B01A
54M
3D-LED
5
+3V3-STANDBY LED-1 B01A
CONTROL
M9
P11
17
3D-LR-DISP
FPGA-SYS-CLK-LX25
F10
BL-DIM1
B05C
B05E HDMI_DV LIGHT-SENSOR
2 3 4
2 3 4
+12V +3V3-STANDBY
BL-DIM
B05C
B01A
B05B STANDBY
POWER CONNECTORS
1C20 1
12
2
FPGA-SYS-CLK 4
7K20
FPGA
7NC1 SII9287BCNU
B01A
1C22 1
2 3 13
50
12M
XIO-D(00-07)
INTERFACE CONNECTORS
TO POWER SUPPLY
62
5500 SERIES B05C CONTROL
RX
B01A
66
B09A
68 MAIN SW
TO SENSOR 5 & 6 CONTROL 7 BOARD 8
PNX-SPI-SDO
7J23 74LVC1GU04
67
FPGA SUPPLY & CTL
3
RESET 1 GND
B05B
7F01
B01B
B05C PNX-SPI-CS-BLn PNX-SPI-CLK PNX-SPI-SDI
VCC
B10B
12M
IF-P-DVBT2 IF-N-DVBT2
TO DISPLAY
7K00 XC6SLX25
+3V3
1FL5
B05G
12,37
7 61
B10A
FPGA-I/O BANKS
FPGA 7KC0 CXD2834R
CA-MDI(0-7)
VCC
42
1J21
52
NANDFLASH
NAND FLASH
BL-DIM
2
B05B
B05C
B05F
TS-CHDEC-DATA TS-CHDEC-CLOCK
43
3D-LR-DISP
1 2
SENSE+1V0-DVBS
9RC2-3
PNX85637
B03A
73
74 MULTI 11 75 STANDARD 7 DEMODULATOR 78 8 FOR SAT DIG TV 62
12
18 QP 19 QM 21 IP 20 IM
PROG-B
37
B05F VIDEO STREAM B05C
122
32 XTAL
44
CTRL-DISP2
OTHER PANEL
7RA1 STV0903BAC
SATELLITE TUNER
CTRL-DISP1
GPIO_3
7J01 XC6SLX4
7RA0 STV6110A
1G51 51
GPIO_2
1
DVBT2
B05B B05B
DDR-CLK_N DDR-CLK_P
N5 N4
CTRL-DISP3
4
2
B05B
F8 E8
DDR2-A(0-13)
A B05B
1N06
B08A
TO DISPLAY
LGD 50Hz 3D PANEL
25M
1N70
RESET-ETHERNETn
19
DVBS-FE
42
SDRAM 128Mx8
4
B08B
44
3D-LR
5
ETHERNET CONNECTOR RJ45
UART SERVICE CONNECTOR
BL-PWM
1
7
7B00 H5PS1G83EFR
1G51 51
CTRL-DISP3
B05B
3 2
ETHERNET
VIDEO OUT - LVDS
DDR2-D(0-31)
DQ
D(24-31)
ETH-RXD ETH-TXD
B05E SDRAM
B09A
DDR
D(16-23)
7N10 LAN8710A-EZK
1N00
B04A
PNX85500
7S00 PNX85637EB B05C ETHERNET
D(8-15)
B05x
ETHERNET + SERVICE
D(0-7)
B06C
2 3
INP OUTP GND
1
RES
RESET-STBYn B05C
BL-I-CTRL-PNX
9F51
BL-I-CTRL
B01A 19220_005_120111.eps 120215
2012-Jun-29 back to
div. table
Block Diagrams
Q552.4E LA
9.
EN 80
Block Diagram I2C
9.12
I²C PNX85500-CONTROL
B05O
P3_1
3F62
MAIN NVM SW
P3_0
7S0A H27U4G8F2DTR
RXD-UP
3F65
TXD-UP
3F64
AF21
1F52 3
3F63
39
DEBUG ONLY
1
40
16
BRX-DDC-SCL
15
1 2
7J01 XS65LX4
7R01 STV903BAC
FPGA BL
CHANNEL DEC DVBS
ERR 31
ERR 37
ERR 38
ERR 28
1P02 CRX-DDC-SDA
16
CRX-DDC-SCL
15
DRX-DDC-SDA
44
DRX-DDC-SCL
B06D
HDMI
16
D(8-15)
D(0-7)
3FC2
15
5
10
12
VGA CONNECTOR
RES
DDCA-SCL +3V3
HDMI_DV
SDRAM A
4_SDA
B24
3S60
DQ
4_SCL
A23
3S61
B08A
TUNER
SDA-TUNER
1FA0 3
SCL-TUNER
1 3FA1 5FA7
DDR2-A(0-13)
ERR 18
D(24-31)
1N05
15
+3V3
DDCA-SDA
Y26
OPTIONAL
11
9FC4
RES
Y25
3FC1
3NCP-1
9FC3 9FC2
DDR2-D(0-31)
SDRAM 128Mx8
VGA-SCL-EDID-HDMI
VGA-SCL-EDID
DDC_A_SDA DDC_A_SCL
9FC1
VGA-SDA-EDID
7B03 EDE1108AGBG
D(16-23)
7B02 EDE1108AGBG
3KC3
HDMI CONNECTOR SIDE
3NCU-4
B05E
B05E
12
1P05
1
48
VGA-SDA-EDID-HDMI
3S5V-3
3NCU-2
SDRAM 128Mx8
DVBT2 CHANNEL DECODER
+5V-VGA
3S5V-1
DEBUG ONLY RES
3FA2 5FA6
SDRAM 128Mx8
13
7KC0 CXD2820R
VGA
AD24
3S6G
7B01 EDE1108AGBG
SCLT
ERR 36
15
AD25
3S6F
7B00 EDE1108AGBG
SDAT
19
6
EDID SW
VGA_EDID_SDA VGA_EDID_SCL
SDRAM 128Mx8
47
PNX85500: ANALOG VIDEO
3NCP-3
B05K
ANALOGUE VIDEO
11
10
1F00 SUT-RE214Z MAIN TUNER ERR 34
ETHERNET + SERVICE
AC1
22 23 24 25
ETH-TXD(0) ETH-TXD(1) ETH-TXD(2) ETH-TXD(3)
AA1 AA4 AB1 AB2
20
ETH-TXCLK
AA2
7
ETHERNET CONNECTOR RJ45
AA3
3S6C
1G51
SDA-DISP
3G2W
50
SCL-SET
9S11
SCL-DISP
3G2Y
49
3C83
1T71 3
3C81
1
LVDS CONNECTOR
+3V3
RXD_0 RXD_1
ERR 14
RXD_2 RXD_3 RXCLK TXD_0 TXD_1
3S5W
VIDEO OUT - LVDS
9S12
GPIO_4 GPIO_5
W21
2
+3V3
1
7S01 PCA9540B RXD2-MIPS TXD2-MIPS
W22
TXD_2 TXD_3
2 CHAN. MULTIPLEX. ERR 24
TXCLK
B06C
+3V3
4
ERR 64
3S66
ETH-RXD(3) ETH-RXCLK
A25
B08A SDA-SET
3S68
8
ETH-RXD(2)
Y5 Y6 AB4
2_SCL
3S58
3S65
ETH-RXD(0) ETH-RXD(1)
B26
3S67
ETHERNET
11 10 9
2_SDA
3S80
7N10 LAN8710A-EZK
3S6B
+3V3
3S81
B06C
B01B
5
TS1
INTERFACE CONNECTORS
7 8
GPIO_3
Y24
3S84
3S83
Y23
RXD1-MIPS
3N53-4 3N53-3
TXD1-MIPS
3N53-2 3N53-1
9S13
SDA-BL
9S10
SCL-BL
3 2 1
UART SERVICE CONNECTOR
SDA-TEMP1
1
3123
SCL-TEMP1
2
7104 LM75ADP TEMP SENSOR
1C20 3C95
11
3C94 SW
3124
1
RES
GPIO_2
TEMP SENSOR
1T02 3
ETHERNET + SERVICE
1N06
9
CONTROL
RES
Programmable via USB
OPTIONAL
2012-Jun-29 back to
div. table
20
DIN-5V
+5V-EDID
DDR
18
OPTIONAL
B05N B05K
21
SATELITE TUNER
FLASH
B04A
97
TUNER CHANNEL DECODER
7R02 STV6110A
HDMI CONNECTOR 2
43
XIO_D
MAIN SW
3RA7
3RA8
3J03
3J04
3D56
3D55
3TPB
3TPD
98
AUDIO AMPLIFIER
1P03 BRX-DDC-SDA
HDMI CONNECTOR 1
RES
B05F
41
LNB CONTROLLER
HDMI CONNECTOR 3
1F51 3
uP LEVEL SHIFTED 1 FOR DEBUG USE ONLY
40
7D60 TAS5731
7TP2 LNBH25
19 18
3NC1-3
15
CIN-5V
RES
ERR 35
3S1H
3S1G
AE21
3NC1-1
34 EEPROM (NVM)
3S2G
FLASH
33
24
1 2
AC24
ERR 23
23
19 18
3S2F
16
ARX-DDC-SCL
3NCT-1
ERR 42
9
1 2
6
ARX-DDC-SDA
BIN-5V
HDMI MUX
6
3NCT-2
AC23 MC_SDA
+3V3-STANDBY
XIO-D(00-07)
B08A
DVBS-FE
19 18
ERR 53
MC_SCL
FLASH (4Gx16)
B08B
1 2
ERR 15
30
7F58 M24C64
RES
B05F
PNX85500: MIPS
1P04
19 18
STANDBY SW
5
STANDBY
29
3NCA-2
PNX-SPI-CSBn PNX-SPI-SDO PNX-SPI-SDI
7NC1 SII9287B
TEMP SENSOR
+3V3-STANDBY
54
3NCA-1
1 5 2
AF24 SPI_CLK AE22 P6_5 AF23 SPI_CSB AE23 SPI_SDO AF25 SPI_SDI
PNX85500: STANDBY CONTROLER
3S6W
PNX-SPI-WPn
53
2
7FD1 LM75BDP
SDA-UP-MIPS SCL-UP-MIPS
3S6V
512K
B05B
B05B
1
AIN-5V
3NCA-4
1_SCL
PNX-SPI-CLK
B05C
SCL-FE
3F59
3S57
1_SDA
3
FPGA I/O BANKS
SDA-FE
3F60
C26
3S6A
C25
3S56
3S69
CONTROL
6
B07B
cS52
ERR 13
PNX85637
FLASH
CLASS-D AMPLIFIER
cS51
+3V3
VCC
B06A
SCL-SSB-550 3FD3
3_SCL
8
DVBS-SUPPLY
SDA-SSB-550
3NCA-3
3S5Z
3NC3
3S5Y
A24
3_SDA
+3V3-STANDBY
B03B
HDMI
3NC5
B25
3S6D
B05C
7F52 M25P05-AVMN6P
B06D
TEMP SENSOR
+3V3
3KC2
B05D
PNX85500: MIPS 7S00 PNX85637EB
3FD4
B05C
PNX85500: CONTROL
3S6`L
B05D
19220_001_111223.eps 111223
Block Diagrams 9.13
Q552.4E LA
9.
EN 81
Supply Lines Overview
SUPPLY LINES OVERVIEW B01A
STANDBY
B05B
+12VD
cU40
1U40
9 GND1 10 GND1 11 BL-ON-1 12 BL-DIM-1 13 BL-I-CTRL-1 14 POWER-OK-1
+12V
+12V
7 8
B01b,B02a, B02b,B02c, B03b
+12V-AUDIO
B04A
14
B02b +3V3
B02a
+3V3
B01B B01a B02c
B01a
INTERFACE CONNECTORS
+3V3-STANDBY
1C85
5C53
+12V
+1V1
+1V2
+1V2
+1V8
+1V8
1T71 4
RES
B05M
B05B
B05N
B01a
VGA
B07a 1N05 9
VGA CONNECTOR
+2V5
+5V-VGA
VCCO3
5J22
VCCO2
5J23
VCCO1
5J24
VCCO0
+3V3
B07a
B05O
TEMP SENSOR B07a
+3V3
B02c
B07b B07b B07b B07b B07b
FPGA - I/O BANKS VAUX
VCCINT
VCCINT
VCCO3
VCC03
B06d
B07a
+2V5-LVDS
VCCO2
VCCO2
VCCO1
VCCO1
VCCO0
VCCO0
+3V3
+3V3-STANDBY
PNX85500: STANDBY CONTROLLER
+1V1
B02a
5J21
VAUX
B07a
B05P
DC / DC
+1V1
+3V3-STANDBY
VDISP - SWITCH
B02c
+3V3-STANDBY
+12VD
+12VD
5FA0
7FA0
+VCC-TUNER
IN OUT COM
+3V3
+3V3-STANDBY
B01a
TUNER-CHANNEL DECODER
+5V
B02c
+3V3
B02c B03a
+3V3
5KC6
+1V2-FE
5KC7
+3V3-DVBT2-D +1V2-DVBT2-C
+3V3-STANDBY
3KCE
B01a
1UU0
7UU0
+3V3-STANDBY
+3V3-STANDBY
B07B
+3V3
B08A
TEMP SENSOR (OPTIONAL)
VCCINT
ANALOGUE EXTERNALS B
+3V3
B01a
B01a
+5V
B01a
T 1.0A
B02A
+3V3
+5V
+2V5-AUDIO
+3V3-STANDBY
+3V3
+3V3
B07a
+1V1
+3V3
B02c
ANALOGUE EXTERNALS A
PNX85500: POWER
+2V5-LVDS
B02b +3V3-STANDBY
+3V3
B05L
B07b
7J20 IN OUT COM
DDR2-VREF-DDR
+2V5-AUDIO
B05h
VAUX
+3V3
B08b
B02c
+2V5
B02b
+3V3 5J20
+3V3
B02c
B05A
FPGA - POWER & CONTROL
+3V3
B02c
+1V8 3B20
BL-ON B05B BACKLIGHT-PWM_BL-VS B05C BL-I-CTRL B05D POWER-OK B05B
+3V3-STANDBY
B03a
+V-LNB
DDR
B07A
HEADPHONE
+3V3-STANDBY
B02c
LNB 20 CONTROLLER
+1V8
B02a
11 12 13
B05I B01a
B02c
B06a
9 10
+12V-DVBS
7TP2 LNBH25PQ 3
B02a
B02c
1TP1 T 3.0A
B05p
T 3.0A 7 8
B01b,B02a, B01a B05a,B05b, B05c,B05d, B05i,B05p, B06a,B06d
CORE VOLTAGE SUPPLY FOR DVBS DEMODULATOR
6
5C54
+VDISP
+1V2-DVBT2-P
B09a
T 2.0A +12V
+12V
7U03 TPS53126PW
B05C +3V3
B02c 12V/1V8 CONVERSION
7U02-1
12 Dual Synchronous 7U02-2 Step-Down Controller 14
7U01
1
PNX85500: CONTROL
7U04
B05a,B05b
+3V3-STANDBY
B01a
+3V3-AUDIO
7D80
B02c 5D84
+3V3-STANDBY +12V-AUDIO
B01a
+5V
+3V3-DVBS
5RA1
+3V3
+3V3-STANDBY
B01a
7RC1 IN OUT COM
+3V3-DEMOD
CLASS-D AMPLIFIER 7RC0
+3V3
B03a +12V-AUDIO B03b
+5V
+3V3RF +2V5-DVBS
IN OUT COM
+3V3D
B02c
+1V1
5U01
5RC0
5RA0
B06A B05D
DVBS-FE
+5V
+3V3-STANDBY
+3V3 12V/1V1 CONVERSION
B02c
B01a B02b, B03a,B04a, B05a,B05e, B10b
B08B
7UU2 LCD-PWR-ONn +3V3
+3V3-STANDBY
+1V8
5U00
PNX85500: MIPS
+1V0-DVBS
B03a
+1V0-DVBS
+V-LNB
+V-LNB
B02c
23
B05E ENABLE-1V8
10
3
B01A
+1V8
B02a
B02B B01a B02c B02a
DC / DC
+12V
+12V
+5V
+5V
+1V8
7UA4 VOLT. REG.
+1V2
7UC0 VOLT. REG.
+2V5
B06B
PNX85500: SDRAM +1V8 3S20
DDR2-VREF-CTRL3
3S06
DDR2-VREF-CTRL2
+3V3
B09A
USB HUB
+3V3
B02c
+3V3
+5V
B02c
+5V 3F32 3F34-4
3FL2
B05a
+3V3
3FL4-4
3FL7
PNX85500: NANDFLASH CONDITIONAL ACCESS
+3V3
B05a
+T
3FL8-4
+3V3
B10b
+5V-USB3
B10b
USB-OVR3
B06C
COMMON INTERFACE
+3V3
+3V3
+3V3
B02c
+3V3 5N08
+5V
DC / DC 7UD0
B01a
+12V
5UD0
+5V
VOLT. REG.
ENABLE-3V3-5V
7UD1 5UD3
B03A B02c B02c B08b B03b
B02a
VOLT. REG.
ENABLE-3V3-5V
DVBS-SUPPLY +3V3
+5V
+5V
+2V5-DVBS +12V-DVBS
+1V8
B01a,B01b, B02b,B03a, B05a,B05c, B05d,B05e, B05f,B05g, B05h,B05i, B05l,B05m, B05o,B05p, B06b,B06c, B06d,B07a, B09a,B08a, B08b,B10b
B01A
+3V3
+2V5-DVBS 5T00
5T03
7T00 VOLT. REG. 7T03 VOLT. REG.
3F01
B02b,B03a, B05d,B05g, B05l,B06b, B06d,B08a, B08b,B10b
+3V3
B02b
B08a
HDMI
+3V3
+3V3
+3V3-STANDBY
B01a
+5V-VGA
B05n
+1V2-LX25
VCCO3-LX25
VCC03-LX25
VCCO2-LX25
VCCO2-LX25
VCCO1-LX25
VCCO1-LX25
VCCO0-LX25
VCCO0-LX25
B02c
FPGA - POWER & CONTROL
+3V3
+3V3 5K20
VAUX-LX25
5K21
VCCO3-LX25
5K22
VCCO2-LX25
5K23
VCCO1-LX25
5K24
VCCO0-LX25
+3V3-HDMI +3V3-STANDBY +5V-VGA
B10a B10a B10a B10a
+5V-EDID +5V
B02c
B05H
PNX85500: AUDIO HDMI 3 CONNECTOR
+2V5 +3V3
HDMI 2 CONNECTOR
+3V3-ARC
7S08 IN OUT COM
+1V2-FE
VAUX-LX25
+1V2-LX25
+3V3-ET-ANA
5NC0
3S11 B08b
B06D B02c
+3V3
B02c
B10b
FPGA - I/O BANKS
VAUX-LX25
B10B
+5VCA
+T
+2V5
+1V0-DVBS
+VDISP
+5V
B02c
B01A
B10b
ETHERNET + SERVICE
B02c
B02C
B10b B10b
B05G
+VDISP
B10A
USB-OVR2
B05a,B05h
+2V5-LVDS
B05p
USB-OVR1
B02c B02c
+3V3
B02c
+5V-USB2
+T
B05F
VIDEO OUT - LVDS
+3V3
+5V-USB1
+T
+3V3
B02c
6NC1
+VSND +VSND
+3V3-STANDBY
2 3 4 5
5U02
PSU
B03B
POWER CONNECTORS
1M95 1
3D83
1M95 1 3V3SB 2 STANDBY 3 GND1 4 GND1 5 +12V3 6 +12V3
+2V5-AUDIO
B05a
HDMI 1 CONNECTOR HDMI SIDE CONNECTOR
+5V B02a
1P04 18
AIN-5V
1P03 18
BIN-5V
1P02 18
CIN-5V
1P05 18
DIN-5V
B10a
7K24
B02c
+1V8
+5V
IN OUT COM
+1V2-LX25
B10a
+5V
19220_004_111229.eps 111229
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Circuit Diagrams and PWB Layouts
Q552.4E LA
10.
EN 82
10. Circuit Diagrams and PWB Layouts 10.1 A 715G5194 PSU 32" & 37" 3500/4000 series 10-1-1
AC Side
A01
AC Side
A01 HOT
! SG9901 SPG-201M-LF
NR9902
C9903
1 3
!
12MH
3 2
4 12MH
C9904 470PF 250V
47PF-NC R9901 510K-NC
SG9902 SPG-201M-LF
R9905 220K 1/4W-NC
SG9904 SPG-201M-LF
3
BD9901 TS6B06G-05-X0 FB9906
! 4
2
NR9901
11
B+
2 BEAD
C9912
FB9902
C9906 47UF 450V
+
C9909 47UF 450V
+
C9907 47UF 450V
+
1
+
10NF
C9913 47UF 450V-NC
BEAD
2
2 1
t
1
1
!
C9901 220NF
!
2
R9902 220K 1/4W-NC
3
4
C9902 220NF
L9902
!
RV9903 TVR14561KFAOZF-NC
!
IC9901 CAP004DG-NC 8 NC NC 7 D1 D2 6 D1 D2 5 NC NC
R9906 2M2 5% 1/2W
!
F9901 FUSE T4.0AH/250V
1 2 3 4
!
L9901
2 BEAD
COLD R9903 220K 1/4W-NC
2
RV9901 TVR14561KFAOZF
1 2 4
!
1 R9904 510K-NC
NTCR
CN9901 AC SOCKET
!
FB9901
SG9903 SPG-201M-LF
2
1
FUSE-NC
C9905 470PF 250V
C9911 1NF 250V-NC
1
t
2
T4.0AH/250V 3 1
-
4 2
+
F9902
N L
NTCR RV9902 TVR14561KFAOZF-NC
SG9905 SG9906 DA38-622MT-A21F-NC DA38-622MT-A21F-NC
BO CN9902 CONN-NC
!
HS9902 1 2 3 4
HEAT SINK-NC
HS9101 1 2 3 4
HEAT SINK-NC
HS9102 1 2 3 4
HEAT SINK
HS9302 1 2 3 4
1
HS9901
!
HEAT SINK
1 2 3 4
C9908 1NF 250V-NC
C9910 470PF 250V
!
HEAT SINK
FB9302 BEAD
2
!
1
AC Side
2012-01-09
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Circuit Diagrams and PWB Layouts
10.
EN 83
LED
A02
LED
A02 DIM
+24V1
L8102 3UH
1
2
1
D8102
+12V2
2
COMP
IC8102 1 2 3 4
EN VLED
DIM COMP EN GM VCC ISET LED GND
8 7 6 5
PF7700S
SR510-22
L8101 25UH
C8125 12UF 160V
1
R8124 22OHM +-5% 1/8W
R8120 100K
+
R8122 100K
C8109 470NF 50V
NC
Q8101 AOD4126 R8123 10K OHM +-5% 1/8W
DIM
D8101 SS1060FL
EN
2
+12V2
+12V2
R8117 820K 1%
R8131 0 OHM +-5% 1/8W
R8126 200 OHM 1/4W
DIM Q8103 MMBT3906-NC 3
+12V
C8120 1N 50V 100KOHM +-5% 1/8W R8118
2 R8130 10K OHM +-5% 1/8W-NC
EN +12V2 +12V2
9
C8124 100N 50V
DIM COMP EN GM VCC ISET LED GND
8 7 6 5
PF7700S
R8128 10K OHM +-5% 1/8W-NC
470NF 50V C8111
R8103
EN
CN8102
LED3 LED6 LED2 VLED
1
LED5
3
LED4
5
LED1
2 4
10K OHM +-5% 1/8W-NC R8129 ON/OFF
6 7
C8113 100N 50V-NC
8
Q8102 MMBT3904-NC
+12V2
1 2 3 4
14
+12V2 DIM
12 11 10 9 8 7 6 5 4 3 2 1
EN +12V2
COMP
IC8101 1 2 3 4
DIM COMP EN GM VCC ISET LED GND
LED1 PF7700S
8 7 6 5
C8105 1UF 16V
DIM COMP EN GM VCC ISET LED GND
LED3 PF7700S
8 7 6 5
C8104 1UF 16V
COMP
IC8106 1 2 3 4
DIM COMP EN GM VCC ISET LED GND
8 7 6 5
C8102 1UF 16V
R8111 10K 1/8W 1%
LED6 PF7700S 470NF 50V C8106
R8102
R8108 10K 1/8W 1% NC
470NF 50V C8115
R8105
R8110 10K 1/8W 1% NC
0.47UF 50V C8110
13
VLED
CN8101
COMP
IC8103
EN
LED2 LED6 LED3
DIM EN
DIM
LED4 LED1 LED5
NC
R8132 9.1K OHM-NC
CONN-NC
VLED
C8103 1UF 16V
R8107 10K 1/8W 1%
LED4 R8133 24K 1/8W 1%-NC
C8126 1N 50V
COMP
IC8104 1 2 3 4
1
FB GM RT CS
PF7900S
VCC OUT GND DIM
8 7 6 5 1 2 3 4
0R05 1/4W
FB R8127 180K +-1% 1/8W
R8112
NC
C8122 NC R8113 91KOHM +-1% 1/8W
2 1
IC8107
R8104 10K 1/8W 1%
510K 1% 1/8W DIM
C8123 100N 50V
C8101 1UF 16V
COMP
R8119
ZD8101 MTZJ13B-NC
8 7 6 5
470NF 50V C8107
R8114
FB
+
DIM COMP EN GM VCC ISET LED GND PF7700S
R8134 0 OHM +-5% 1/8W-NC +12V
COMP
IC8105 1 2 3 4
LED5
R8116 0.05R
C8127 10UF 50V
R8109
C8132 220UF 100V
R8115 820K 1%
R8125 2R2 +-5% 1/8W
R8121 100K
+
C8119 1UF 16V
R8101 10K 1/8W 1%
LED2 C8108 150UF 35V
+
10
10-1-2
Q552.4E LA
CONN
R8106
NC
1
LED
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Circuit Diagrams and PWB Layouts
10.
EN 84
Main Power
Main Power
A03
A03
B+_main
HOT
COLD
R9104 100 OHM 1/4W
R9147 2Mohm 1/4W +/-1%-NC
R9103 100 OHM 1/4W B+_main
R9105 100 OHM 1/4W
R9148 2Mohm 1/4W +/-1%-NC T9101 8
9 10
C9120 1.5NF R9113 100KOHM +-5% 2WS
15 16 14
6 5
C9103 1.5NF
D9102 FMEN210A 2
VCC1
Q9108 TK2P60D-NC C9132 100N 50V-NC
1
13 12
D9101 PR1007
R9155 10K OHM +-5% 1/8W
L9101 3UH
C9106 470UF 35V
1
R9149 2Mohm 1/4W +/-1%-NC
+12V +12V1
! 3
C9108 10NF
R9164 24R 1%
R9182 24R 1%
R9163 24R 1%
R9181 24R 1%
R9106 24R 1%
R9153 24R 1%
R9102 24R 1%
R9152 24R 1%
R9107 24R 1%
R9154 24R 1%
C9105 470UF 35V
+
C9107 270UF 25V
+
C9112 0.47UF 50V
+
R9158 R9159 R9160 R9161 R9162 1.5K 1/4W 1.5K 1/4W 1.5K 1/4W 1.5K 1/4W-NC1.5K 1/4W-NC
11 R9177 100KOHM +-5% 1/8W-NC
POWER X'FMR
R9111 10K OHM +-5% 1/8W
IC9103
R9129 0 OHM +-5% 1/8W
BNO COMP NC CS
22OHM +-5% 1/8W R9109
8 7 6 5
OVP VCC OUT GND
1 Q9101 TK6A65D
LD7523GS
R9127 100R 1/8W 5%
C9113 470NF 50V
R9110 10K OHM +-5% 1/8W
+24V2
C9102 1.5NF
C9104 560UF 35V
+
+ C9109 560UF 35V
+24V
+24V1
C9101 220UF 35V
R9180 10K 1/4W-NC
R9178 10K 1/4W-NC
R9179 10K 1/4W-NC
R9137 680 OHM 1/4W-NC R9173 100KOHM +-5% 1/8W-NC
ZD9107 P6KE27A-NC
Q9111 2SD1624T-TD-E
R9172 1K OHM +-5% 1/8W
R9174 100KOHM +-5% 1/8W-NC
C9128 1N 50V
1 C9131 100N 50V +12V1
C9111 0.47UF 50V
+
2
MMBT3904-NC Q9112
R9176 3K 1/8W +/-1%
R9135 27K 1/8W 1%-NC
R9156 680 OHM 1/4W-NC C9124 100N 50V-NC
ZD9104 B6V2-NC
1
220 OHM 1/4W R9112
C9125 1N 50V-NC
ZD9106 MTZJ27B
R9171 470R
Q9107 AOD409-NC
1
C9135 1uF-NC
2
C9134 1uF-NC C9136 1uF-NC
R9138 10 OHM 1/4W-NC
1
R9108 0.27R
+24V2
L9102 3UH
2 C9114 100N 50V
+24V
+24V1
D9103 FMXA-2202S 2
VCC1
R9151 1K OHM +-5% 1/8W-NC
IC9105 AS431AN-E1-NC
R9175 1K OHM +-5% 1/8W-NC
R9136 3K 1/8W +/-1%-NC R9115 470OHM +-5% 1/8W
+12V
+24V1
+24V1
C9117 6.8nF
IC9101 PC123X8YFZOF
470PF 250V
! 2
C9130 470PF 250V
2
C9126 470NF 50V-NC
C9127 470NF 50V-NC
C9110 4.7uF 25V
DV5
R9117 1K8 +/-1% 1/8W
AS431AZTR-E1 IC9102
1
!
R9101 5K1 1/8W 1%
R9139 R9140 R9141 R9142 R9143 R9144 R9145 R9146 R9165 R9166 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC 10K 1/4W-NC
D9107 BAV99 ZD9105 MTZJ15B
BEAD
R9116 120KOHM +-1% 1/8W
3
C9122 1NF 250V-NC
2
C9123 4.7uF 25V
5.2V
Q9106 MMBT3906 PNP
R9126 110R R9128 200 OHM 1/4W
HOT
5.2V
R9134 10K OHM +-5% 1/8W
Protect R9123
5.2V R9130 10K 1/4W
R9131 0 OHM +-5% 1/8W
+12V
2
R9125 100KOHM +-5% 1/8W VCC1 ZD9103 MTZJ18B
D9105 SS1060FL R9122 10K OHM +-5% 1/8W
D9106 SS1060FL
R9170 5.1K 1/4W
C9118 4.7UF 50V-NC
+
PS_ON C9116 100N 50V
R9119 100KOHM +-5% 1/8W-NC
R9120 100KOHM +-5% 1/8W
2
R9168 1K OHM +-5% 1/8W
C9121 100N 50V-NC
1 1
Q9110 MMBT3906
2
ZD9101 MTZJ18B
R9133 20K +-5% 1/8W
Q9104 2N7002K
1
ZD9102 MTZJ30B
1 1
D9108 SS1060FL
R9132 100KOHM +-5% 1/8W-NC
!
PC123X8YFZOF Q9105 2N7002K-NC
2
Q9103 2SD1624T-TD-E
Protect
1
2
3
IC9104
R9167 1K OHM +-5% 1/8W
2
R9169 10K OHM +-5% 1/8W
1
2K 1/8W 5% +24V
4
VCC
2
FB9905
R9118 9K1 1/8W 1%
C9119 100N 50V
! 1
R9114 3K 1/8W +/-1%
1
C9133
2
C9129 1NF 250V-NC
1
R9124 2K 1/8W 1%-NC
4
R9150 2K 1/8W 1%
SS1060FL D9104 2
3
1 2 3 4
3
10-1-3
Q552.4E LA
MMBT3904 Q9102 C9115 470NF 50V
R9121 10K OHM +-5% 1/8W
1
Main Power
2012-01-09
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Circuit Diagrams and PWB Layouts 10-1-4
Q552.4E LA
10.
EN 85
Standby
Standby
A04
A04 C9137
FB9304
C9139
!
1
CN9301
2
BEAD 470PF 250V-NC220PF 250V
COLD
1
HOT
R9319 47 OHM 1/4W
1 B+
R9303 47 OHM 1/4W
C9301 1.5NF
R9304 47 OHM 1/4W R9301 100KOHM +-5% 2WS-NC
ZD9315 P6KE160A
2
R9309 10K 1/4W
5.2V
2 9 10
+
C9316 100UF 50V
L9301 3UH +
1
3 5 R9305 2R2 +-5% 1/4W
+
C9303 470UF 10V
D9308
+
C9313 270UF 25V
C9304 470UF 10V
C9305 0.47UF 50V
4 D9303 PR1007
D9304 PR1007
R9306 1.5M 1%
R9313 1.5M 1%
+
1
2 13 12 11 10 9 8 7 6 5 4 3 2 1
ON/OFF DIM
SR240S-NC R9307 220R 1%
+12V
C9306 100UF 50V
1
R9311 8K2 1/8W 1%
5
D9305 SS1060FL 2
2
IC9302
A6069H C9308 1N 50V
4
8 7
3
S/OCP D/ST BR D/ST GND FB/OLP VCC
1
IC9301 1 2 3 4
PC123X8YFZOF
!
PS_ON
1K OHM +-5% 1/8W R9312 C9307 220N 50V
GND_Audio
5.2V P_OK
CONN-NC
CONN
R9315 4.7M 5% 1/8W
+
5.2V
C9309 10UF 50V
R9316 9K1 1/8W 1%
R9318 43K 1/8W 1%
2
C9311 100N 50V
ZD9316 GDZJ5.6B
Q9301 2N7002K
R9323 10K 1/4W-NC
10K OHM +-5% 1/8W R9320
R9321 0R05 1/4W-NC
DV5 1
R9317 560K 1/8W 1%
13 12 11 10 9 8 7 6 5 4 3 2 1
R9314 1K OHM +-5% 1/8W
IC9303 AS431AN-E1 C9310 220NF
CN9304
CN9302 POWER X'FMR
VCC R9308 0.75R
CONN-NC
3
6 7
2
D9301 1N4007
CONN-NC
D9302 FMW-2156
!
1
1.5NF C9302
L9302 3UH-NC
T9301 1
C9312 10NF
R9310 1.5M 1%
12 11 10 9 8 7 6 5 4 3 2 1
2 BEAD
BO
D9306 SJPW-T4VL-NC 2
B+_main
FB9301
0.1R R9302
12 11 10 9 8 7 6 5 4 3 2 1
+24V
CN9303
R9332 100KOHM +-5% 1/8W
P_OK
EN R9324 0 OHM +-5% 1/8W
ON/OFF
C9314 470PF 250V
C9317 1NF 250V-NC
! 1
Standby
2012-01-09
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Circuit Diagrams and PWB Layouts
10.
EN 86
Power layout top
GND4
CN9301
CN8101
CN9303
J937 J947
GND10
J942
L8102
D8102
CN8102
GND11
GND3
J943
10-1-5
Q552.4E LA
J924
J938
J925
C8128
C8125
L8101
J939
C9101
J940
J927 J928
J923
J950
C9107
J922
J951
CN9302
J934
J933
J952 J965
J935
ZD9104
CTI1
L9101
J944
ZD9107
J949
J948
J945
C8108
L9102 CN9304
J931
C8129
J932
J930
C8132
R8116
L9302
C9316
J966 J967
C9109 C9313
J946
J954
J953
R9171 ZD9106
J955
J960
J957
J959
HS9302
GND9 J969
C9304 C9303 J963
J912
J919
C9310
R9308
C9312
J968
IC9104
IC9302
C9306
C9309
R9310
RV9903
R9302
C9901
FB9906
J910
J964
R9904
L9902 C9913
BD9901
SG9903
NR9901 R9906
NR9902 J972
J902
CN9902
RV9901
C9129 SG9905 F9902
J906
J905
HS9902 HS9901
C9133
F9901 RV9902
SG9906
C9909
C9902
FB9901
C9907 C9906
J901
C9903
SG9904
FB9902
GND8
L9901
R9901
J911
SG9902
R9306
SG9901
C9912
FB9301
J908
J904
J909
C9904
J903
J907
GND5
C9905
D9301
HS9101
J970
C9908
C9911
J916
R9313
C9108
ZD9316
J915
IC9301
ZD9315
Q9101
GND12
J917
C9118
R9301
FB9302
C9910
C9314 D9303
C9137 C9302
FB9905
R9108
ZD9103 J918
D9304
J913
D9101
R9113
C9120
IC9101 J974
C9122
T9301
C9139
T9101 ZD9105
FB9303
C9130
J973
IC9102
FB9304
C9317
J920
J971
D9102
GND13
L9301
D9302
C9103
GND2
C9301
D9308 J962
J958
J961
C8127
C9106 J956
J926
J941
C9105
ZD9102
J921
D9103
HS9102
ZD9101
C9102
GND7
J929
J936
C9104
CN9901 GND1
GND6
1
Power layout top
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R9905 C9117
R9129
D9104 R9110
R9127
R9112
C9307
TEST1
R9137
R9156
R8124
R9145
R8123
R9142
R9118
C9124
Q9111
R9124
R9135 R9151
R8126
C8120
R8127
C8126
C8124
C8123
R8117
R8122
Q8101
R8125
D8101
IC8107
R8113
C8122
R8114
R8120
R8115
Q552.4E LA
R9136
IC9105
R9175
RJ910
R9174 Q9112
R9138
R9126
R9172
R9173
C9125
Q9107
RJ905
C9127
RJ908
R9116
R9163
R8102
C9126
R9181
R9102
C8113 R8130
C9123
R9152
R9164
R9105
RJ901
C9110
RJ914
R9182
R9106
R9153
R9107 R9104
R8128 R8131
D9107
R9115
RJ909 R9154
RJ915
R9103
R8109
C9128
IC9103
R9111
R9148
R8118
C9113
R9147
R9150
R8105
C9114
Q9108
RJ916
R8119
C8110
R8110
Q8103
Q8102
R8104 R8133
C8105 R8106
R9155
R8108 R8129
C8109
IC8101
C8103
RJ911
RJ904
C9135
RJ906 R8101
R8132
C8119
R8112
IC8102
C8111
IC8104
R8107
C8115
R8111 C8104
C8101
R9162
R9158
R8103
IC8103
C8107
IC8105
C9112
R8121
R9177
RJ913
C8106
C8102
R9160
R9179
IC8106
R9309
R9161
R9180
R9178
C9305
D9306
R9323
R9321
C9111
C9132
R9170 R9319
R9303
R9304
D9106
D9105
R9159
C9136
C9134
Q9103
R9315
D9108
C9311
RJ903 R9307
IC9303
R9314
R9169
R9167
R9122
C9115
R9130
R9318
R9317
C9308
R9320 R9332
D9305
R9128 R9311 R9316
RJ902
RJ917 Q9110
R9168
R9312
R9131 Q9105
R9121
Q9301
Q9102
Q9106
R9134
IC9901
R9119
R9133 R9132 Q9104
R9324
R9123
C9116
R9120
10-1-6
C9121
Circuit Diagrams and PWB Layouts 10. EN 87
Power layout bottom
R9141
R9143
R9140
R9139
R9144
R9146 R9165
R8134
R9166
C9131
R9176
C9119 R9101
R9117
R9114
R9125
R9305
R9149
R9109
RJ907 RJ919
R9902 R9903
Power layout bottom 1
2012-Jun-29 back to
div. table 2011-12-21
715G5194 19240_505_120215.eps 120215
Circuit Diagrams and PWB Layouts
Q552.4E LA
10.
EN 88
10.2 A01 715G5246 PSU 42" 3500/4000 series Power Circuit
Power Circuit
A01 FB9803
D9802 1N5408-11
2
1
L9801 300UH
2
TS10B06G-06-X0
1
1
2 BEAD
+
1 2
C9171 2.2NF
+ C9801 47UF 450V
+ C9802 47UF 450V
R9327
R9326
R9328
100K
100K
1NF C9331
C9803 470PF1KV
C9805 47UF 450V
ZD9302 P6KE160A
C9906 470PF 250V
C9907 470PF 250V
C9825
22N 50V
3
R9334 220 OHM 1/4W
D9306 1N4148
D/ST D/ST VCC
8 7
+
C9337 47UF 50V
5
R9342
!
R9301 1.2R
B1+
C9335 100N 50V
R9345 DIM R9320 510K 1% 1/8W
R9816 680K OHM +-1% 1/4W
R9815
R9814
ZD9303 GDZJ15B
1
C9343 220N 50V
R9317 1.5M 1% 1/4W
10K 1/8W R9819
BOX
R9150
R9142
1M 1% 1/4W
1.5M 1% 1/4W
1.5M 1% 1/4W
D9113 UF4007
1K 1/8W R9164
12MH
D9114
R9155
1 2 3 4 5 6 7 8 9
!
R9145
C9145 100N 50V
20K 1/8W 1%
C9909 470PF 250V
Vsen Vcc FB GND Css OC RC Reg RV
NC NC VGH VS VB NC NC VGL COM
C9152 1.5NF
!
D9112 RB160M 2
2 2
2
1
DV5 24V +24V
R9154 47OHM +-5% 1/8W
10 POWER X'FMR
! R9103
R9156 10K 1/8W 1%
NR9902 NTCR
D9116 FMEN-2308
L9103 5uH
L9105 5uH 24V-LED
2
Q9102 TK10A50D
ZD9104 GDZJ15B
1UF
R9341 NC
2 13 12
R9340 NC
9 8
VBoot
VCC1
t
D9115 FMEN-2308
6 7
1
1
!
PS-On 5.2V P_OK
R9338 7.87K 1%
CONN
1 2
10K 1/8W 1%
C9153
D145T60P7_5-1_2-R
Q9301 NC
IC9304 AZ432AZTR-G1
11
15 14
R9153
18 17 16 15 14 13 12 11 10
SSC9512S-TL
C9151 1UF
!!
T9101
47OHM +-5% 1/8W
IC9101
C9910 470NF 305V
!
Q9101 TK10A50D
R9152
R9165 10K 1/8W
C9162 100N 50V
VCC1
1MOHM +-5% 1/2W
C9908 470PF 250V
1
R9151 10 OHM
100 OHM 1/4W
!
R9901
R9102 10 OHM
RB160M 2
NTD4906NT4G Q9104
4
1
SG9902 GS41-201MA 1
R9339 NC
1
FR107
!
1
SG9903 GS41-201MA
ZD9304 NC
2
R9144
D9304
1
0.1R
!
R9319 1.5M 1% 1/4W
VBoot
B1+
! 2 L9901 3
!
R9318 1.5M 1% 1/4W
3
C9832 100N 50V
R9141
2
!
13 12 11 10 9 8 7 6 5 4 3 2 1
12V 24V
3
!
R9336 1K 1/8W 1%
3
!
NC CN902
C9334 1N 50V
VCC1
On/Off
R9337 12.7 KOHM +-1% 1/8W
C9333 0.47UF 50V
680K OHM +-1% 1/4W
1K 1/8W R9818 Q9802 NTD4906NT4G
EN 0 OHM 1/8W
IC9303 PC123X8YFZOF
680K OHM +-1% 1/4W
0R05 R9817
P_OK
3K3 1/8W 5%
10UF 50V
10K 1/8W 1%
R9343 On/Off
R9335
2
100N 50V
R9811 R9810 13K OHM 1%
C9827 100P 50V
220N 50V
IC9301 A6069H S/OCP BR GND FB/OLP
2 3 4
R9801 0.05R
D9307 FR103
+ C9336
C9829 100 OHM 1/4W
C9824
5.2V
!1
C9828 100N 50V
CONN
C9342 100N 50V
C9341 470uF 16V
R9323
R-
R9806 56K 1/8W
C9901 NC
C9830 10UF 50V
+ C9344
1
2 +
C9826 220pF 50V
FR107
!
R9809 30 OHM R9813 10K 1/4W
R9804 NC
R9805 200KOHM 1/8W +/-5%
Q9801 TK18A60V
1
4
!
+ NC
4.7M OHM +-5% 1/4W
ZD9106 ZD9107 BZT52-B5V1 BZT52-B22
R2A20113ASP
8 7 6 5
NC D2 D2 NC
2
R9808 10R 1/8W 5%
1
R9905 510K
D9803 RB160M
R9807 470 OHM 1/4W 8 7 6 5
FB VCC COMP OUT RT GND VREF CS
C9340 470uF 16V
2
NC D1 D1 NC
1 2 3 4
+
VCC1
1
1 2 3 4
R9332 2R2 +-5% 1/4W
D9305
NC
IC9901 NC
DIM On/Off 5.2V
5uH
POWER X'FMR
C9831
2
!
L9304
2 VCC
CONN-NC
IC9801
!
1NF C9338 D9308 FMW-2156
9 10
4 R-
R9904 510K
6 7
3 5
CN904 C9911 470NF 305V
12 11 10 9 8 7 6 5 4 3 2 1
R9331 47 OHM 1/4W 2
100K
+ C9804 47UF 450V
12MH BOX
R9325 100K
CN903
R9330 47 OHM 1/4W
!
0.1R
FB9802
C9833 47pF
T9301
2
L N
!
2
1
C9820 1UF 450V
SG9905 DSPL201M-A21F 3
3
4 L9903 1
BD9901
24V R9329
2
3
SG9904 DSPL201M-A21F
4
!
FMN-1106S D9801
1
1
1
6
R-
+
-
B1+
FB9801 BEAD
3
4
FB9804 BEAD
1
!
!
FB902 BEAD
SB+
60R 2
1
RV9902 TVR14561KFAOZF
1
A01
2
10-2-1
C9160 560UF 35V
10 OHM
+
+
C9161
+ R9174 5.1K 1/4W
560UF 35V
C9165 100N 50V
C9164 330UF 35V
R9171 5.1K 1/4W
R9172 5.1K 1/4W
R9173 5.1K 1/4W
t
D145T60P7_5-1_2-R 470 OHM 1/8W R9149
C9156
RV9901 C9150 0.47UF 50V
R9148 NC
R9101 200R 1/8W 1%
C9154 560P 50V
2 4
TVR14561KFAOZF
100PF1KV
!
C9155 1N 50V
L9106 5uH
C9157
12V
27NF
+
24V
HS9101
C9168 470UF 25V
3 4 R9147
12V
1
R9161 24K 1/8W 1%
C9159 330NF 50V
C9148 4.7UF 10V
VCC1
VCC
R9160
R9178 5.1K 1/4W
10K 1/8W 1%
Q9303 2SD1624T-TD-E
IC9107 AS431AZTR-E1 C9904 NC
!
HEAT SINK (D9308)
HEAT SINK
2
1 2 3 4
! 1
!
HS9102 3 4
C9912 470PF 250V 2
SB+ 470PF 250V
HEAT SINK
!
!
2 R9333
R9324
1K 1/8W 1%
1K 1/8W 1%
D9109 1N4148
D9110 1N4148
Q9304 2N7002
D9301
Q9302
20K OHM
100K 1/6W 5%
2
Q9106
R9303
PC123X8YFZOF
!R9302
1
RK7002BM PS-On C9345 100N 50V
R9310 100K 1/8W 1%
C9301 100N 50V
R9304 100K 1/8W 1%
RB160M
Q9103
MMBT3906 PNP
R9139 100 OHM 1%
C9144 100N 50V
R9140
R9138 PMBS3904 1K 1/8W 1%
1K 1/8W 1%
FB9904
1 2
NC
ZD9102 GDZJ15B
HS9103
!
BEAD
C9903
NC
1
FB9302
HS9802
ZD9301 GDZJ18B
R9111
R9309 100K 1/8W 1%
IC9302
+ C9302 22UF 50V
3
FB903 NC
HS9301
R9143
5.2V R9307 10K 1% 1/4W
RB160M
4
HS9801
ZD9101 GDZJ30B
Main_ov R9311 NC
D9302
R9306 10K 1/8W 1% R9163 2K 1/8W 1%
1
1 2 3 4
R-
C9166 NC
ZD9105 NC
R9308 10K 1/8W 1%
R9346 1K 1/4W
12V
5.2V
MMBT3906 PNP
C9158 NC
2
CN905 CONN
IC9106 PC123X8YFZOF
C9149 100N 50V
1 2
1 2 3 4
!
3
CN901 SOCKET
C9170 100N 50V
Q9305 R9180 27K 1/8W 1%
1
2
HEAT SINK HS9901
R9177 1.5K 1/4W
DV5
5.2V
DV5
R9159 3.3K 1/4W
1 2
1
4
R9146 2K43 1/8W 1%
R9176 1.5K 1/4W
24V
HEAT SINK
2
!
R9175 1.5K 1/4W
Main_ov
24V
R9158 3.9K 1/4W
2
!
470 OHM 1/8W
SHIELD
C9169 470UF 25V
1 2
2
1 3
FUSE
1 2 3
+
470UF 25V
F9901
1
C9163 +
2
!
+ C9147 22UF 50V
1
C9146 100N 50V
1
!
1
NR9901 NTCR
1
C9905 470PF 250V 2
1 2 3 4
BEAD 1
HEAT SINK
Power Circuit
2012-01-10
715G5246 19240_506_120213.eps 120320
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 89
24 V to VLED
24 V to VLED
A02
A02 1 2
2
1
24V-LED
VLED
3 L8101 D8120 MBRF10150CT
C8118
Q8101
R8154 100K
+ C8108 100UF 100V
+
100UF 100V
4
3
25UH
R8155 100K
R8156 100K
R8145 270K 1/4W
TK12A10K3
R8147 110K OHM 1%
12V_LED
R8177 NC
R8157 10K 1/8W 1%
R8175 0.1R
R8161 2.2 OHM 1/8W
R8144 430K 5%
1
R8158 22 OHM 1/8W
LED-COMP
D8118 RB160M 2
R8141 20K 1% 1/8W
8 7 6 5
C8121+
C8106 NC
R8162 1K 1/8W 1% R8153
R9316 NC
Q9306 MMBT3906 PNP
12V
12V_LED R9313 15K 1% 1/8W
DIM 0 OHM 1/8W
1 2 3 4
22UF 50V
IC8103
PF7900S
ZD8103 BZT52-B13
C8111 100N 50V
FB VCC GM OUT RT GND CS DIM
2
12V
R8176 0 OHM 1/4W
1
10-2-2
Q552.4E LA
R9344 10K 1/8W
R8148 1K 1/8W 1%
R8163 200K 1%
C8105 1N 50V
R9312 51K OHM
C8119 NC C8113 1N 50V
EN R9321 Q9308 PMBS3904
On/Off 33K OHM
C9346 100N 50V
R9315 3.9K1% 1/8W R9322 100K 1/8W 1%
1
24 V to VLED
2012-01-10
715G5246 19240_507_120213.eps 120213
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts 10-2-3
Q552.4E LA
10.
EN 90
LED Driver
LED Driver
A03
A03 IC8501 1 2 3 4
DIM EN 12V_LED LED-1
DIM COMP FLAG GM VCC ISET LED GND
LED-COMP DIM R8501 11K 1%
PF7703S C8158
IC8502
8 7 6 5
C8501 1UF 16V
EN 12V_LED LED-6
1 2 3 4
IC8503 8 7 6 5
LED-COMP
R8502 11K 1%
PF7703S
C8157 100N 50V
+
DIM COMP FLAG GM VCC ISET LED GND
1 2 3 4
DIM EN 12V_LED LED-2 C8502 1UF 16V
DIM EN 12V_LED LED-5
DIM COMP FLAG GM VCC ISET LED GND
LED-COMP
R8503 11K 1%
C8503 1UF 16V
C8529 100N 50V
IC8504 1 2 3 4
8 7 6 5
PF7703S
C8523 100N 50V
NC
DIM COMP FLAG GM VCC ISET LED GND
IC8506 IC8505
8 7 6 5
LED-COMP DIM R8504 11K 1%
PF7703S
EN 12V_LED LED-3
C8504 1UF 16V
1 2 3 4
DIM COMP FLAG GM VCC ISET LED GND
8 7 6 5
PF7703S
C8518 100N 50V
DIM EN 12V_LED LED-4
LED-COMP
R8505 11K 1%
1 2 3 4
8 7 6 5
DIM COMP FLAG GM VCC ISET LED GND
LED-COMP
R8506 11K 1%
PF7703S
C8505 1UF 16V
C8506 1UF 16V
C8530 100N 50V
C8524 100N 50V
IC8507 DIM EN 12V_LED LED-8
1 2 3 4
DIM COMP FLAG GM VCC ISET LED GND
8 7 6 5
IC8508 LED-COMP DIM R8507 11K 1%
NC
EN 12V_LED LED-7
C8507 1UF 16V
1 2 3 4
DIM COMP FLAG GM VCC ISET LED GND
8 7 6 5
1 2 3 4
DIM R8508 11K 1%
NC
C8519 100N 50V
IC8509 LED-COMP
C8508 1UF 16V
EN 12V_LED LED-14
8 7 6 5
DIM COMP FLAG GM VCC ISET LED GND
R8509 11K 1%
PF7703S
C8525 100N 50V
LED-COMP
C8509 1UF 16V
C8531 100N 50V
IC8510 DIM EN 12V_LED LED-15
1 2 3 4
DIM COMP FLAG GM VCC ISET LED GND
8 7 6 5
IC8511 LED-COMP DIM R8510 11K 1%
PF7703S
EN 12V_LED LED-12
C8510 1UF 16V
1 2 3 4
DIM COMP FLAG GM VCC ISET LED GND
IC8512 8 7 6 5
LED-COMP R8511 11K 1%
PF7703S
C8520 100N 50V
1 2 3 4
DIM
C8511 1UF 16V
EN 12V_LED LED-16
8 7 6 5
DIM COMP FLAG GM VCC ISET LED GND
LED-COMP R8512 11K 1%
CN8503 C8512 1UF 16V
PF7703S
C8526 100N 50V
C8532 100N 50V
VLED
IC8513 DIM EN 12V_LED LED-9
1 2 3 4
DIM COMP FLAG GM VCC ISET LED GND
8 7 6 5
IC8514 LED-COMP DIM EN
R8513 11K 1% C8513 1UF 16V
NC
12V_LED LED-10
1 2 3 4
DIM COMP FLAG GM VCC ISET LED GND
8 7 6 5
LED-COMP VLED
IC8516
EN 12V_LED LED-11
1 2 3 4
DIM COMP FLAG GM VCC ISET LED GND PF7703S C8522 100N 50V
8 7 6 5
DIM EN 12V_LED LED-13
LED-COMP
R8515 11K 1%
C8515 1UF 16V
1 2 3 4
DIM COMP FLAG GM VCC ISET LED GND PF7703S
8 7 6 5
CN8502
C8514 1UF 16V
C8527 100N 50V
IC8515
NC
VLED CN8501
R8514 11K 1%
NC
C8521 100N 50V
DIM
1 2 3 4 5 6 7 8
LED-11 LED-16 LED-12 LED-15 LED-13 LED-14
LED-COMP C8516 1UF 16V
R8516 11K 1%
12 11 10 9 8 7 6 5 4 3 2 1
LED-9 LED-10 LED-11 LED-12 LED-13 LED-14 LED-15 LED-16
LED-1 LED-2 LED-3 LED-4 LED-5 LED-6 LED-7 LED-8
CN8504
12 11 10 9 8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8
VLED LED-4 LED-3 LED-5 LED-2 LED-6 LED-1
NC
C8528 100N 50V
NC
NC VLED
VLED
1
LED Driver
2012-01-10
715G5246 19240_508_120213.eps 120213
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts 10-2-4
Q552.4E LA
10.
EN 91
Power layout top
J8536 J8540
L8101
J8501
J8504
J8502
J8507
J8505
J8510
J8508
J8514
J8511
J8517
J8515
J8518
J8521
J8564
J8531
J8524
J8522
J8537
D8120
J8539
J8538
J9118
HS9101
J8525
R8175 L9105
J8547
C9164
J8546
J8544
C8121
J8553
J8527 J8551
J8565
HS9103
J9102
J8550
J8549
J8530
J8526
Q8101
J8520
ZD9105
C8158 IC9107
D9115
IC9106
C9820
J9117
J8548
J9101
J8542
J8545
J8523
J8519
J8516
J8512
J8509
J8506
J8503
J8529
J8543
J8554
J8541
J8552
J8528
D9116
C9152
L9801
CN903
C8108
J8534
C8118
J8533 J8532
J9108
CN8502
J9106
CN8501
J8535
CN8503 J8558
J8513
CN8504
C9163
D9114
J9307
C9337
J9105
J9104
J9103
J9111
J8561
J9109
J9112
ZD9101 D9109
ZD9102 D9110
C9338 J9304
IC9304
IC9303 R9302
FB903
ZD9304
IC9302
J9306
HS9802 C9909
ZD9303
C9903
J9308
D9306
J9303
C9908
HS9301
D9307
J9302
C9906 C9907
J9309
IC9301
C9336
J9301
RV9901
D9308
T9301
J9305
C9802 C9805 C9801 C9804
NR9901 F9901
C9910
C9161
J9107 R9329
L9304
C9905
D9305
J9907
C9331
R9901
J9901
SG9902
C9160
C9157
ZD9302
C9830
L9901
R9904
FB9904
BD1
HS9801
C9344
C9340
C9912
FB9302
J9115
R9301
R9905
C9803
J9908
CN902
C9341
J9113
J9905
D9304
C9901
J9116
C9156
L9103
J9904 J9903
SG9903 FB9803
SG9905
C9147
D9801
NR9902
C9169
R9141
D9802 J9909
J9912
J9911
SG9904
FB9804
Q9801
T9101
Q9101
FB9801
RV9902
C9911
C9168
J9114
FB902
C9171
FB9802
L9903
Q9102 HS9102
C9833
J9906
CN904
L9106
J9110
J9902
J9910
BD9901
HS9901
R9801
ZD9104
ZD9301
CN901 CN905
C9302
C9904
GND1 1
Power layout top
2011-12-22
715G5246 19240_509_120215.eps 120215
2012-Jun-29 back to
div. table
R9309
R9307 R9308
R9178 D9302
R9339
R9325
C9334
C9342
R9327 JR9104
R9317 R9318
R9323
2012-Jun-29 back to
div. table
C9832
R9819 C9827 R9806
ZD9106
R9808
R9807
R9164
R9804
C9826
R9816
C9829
R9805
IC9801
R9809
D9803
R9815
C9824
R9814
C9828
R9342
R9810
R9144
R9818
R9150
R9101
C9148
C9149
C9151
C9146
ZD9107
R9142 C9145
R9146
JR9101
JR9103
R9102
IC9101
R9811
R9153 C9154
R9145
Q9802
R9817
R9174 R9147
C9153
R9154
C8513
R8513
C8514
R8514
C8515
R8515
C8511
R8511
C8516
C8501
R8501
C8503
R8503
C8505
R8505
C8506
R8506
C8504
R8504
C8502
R8502
C8508
R8508
C8507
R8507
IC8513
C8521
IC8514
C8527
IC8515
C8522
IC8511
C8526
IC8501
C8157
IC8503
C8529
IC8505
C8524
IC8506
C8530
IC8504
C8518
IC8502
C8523
IC8508
C8525
IC8507
C8509
R8509
C8510
R8510
IC8509
C8531
IC8510
C8520
IC8512 C8512
IC8516
R8512
R8144 R8147
R8141
C8106
C8532
C8519
C8119 C8113
R9344
R8155
R8156
R8154
10.
R9148
R9175
C9150
R9156
Q9104
C9346
D9112
JR9102 R8516
C8111
ZD8103
C8528
R9321
D9113
Q9308
R9312
Q9306
R8177
R9155
R9177 R9103
C9158 C9166
R9316
R9345
C8105 R8163
R9315
R9152
R9159
C9159
R9160
R9161
IC8103
D8118
R8148
R9326
R9328
R9180
R9158
R8176
R8153
R8158
R8161
R8157 R8162
Q552.4E LA
IC9901
R9331
R9330
R9173
R9172
R9171
R8145
R9320
R9138
R9332
D9301
C9170
JR8101
C9333
C9335
R9334
R9335
C9343
R9336
R9338
R9143
R9324
R9346
R9341 Q9301
R9333
Q9305
R9340
C9301
R9303
C9345
Q9106
Q9103
R9111
R9310
R9304
C9165
R9176
Q9304
Q9302
C9144
R9311
R9343
10-2-5
R9139
Circuit Diagrams and PWB Layouts EN 92
Power layout bottom
R9322
R9313
R9163
R9151
R9149 C9155
C9162
R9165
R9813 C9831
C9825
R9319
R9140
R9337 Q9303
R9306
Power layout bottom 1 2011-12-22
715G5246 19240_510_120215.eps 120215
Circuit Diagrams and PWB Layouts
Q552.4E LA
10.
EN 93
10.3 B 313912365313 SSB Power connectors
Power connectors
+5V +3V3-STANDBY
+12V-AL
RES 10K
**
GND-AL
3U75
RES 10K
LED-2
FU48
**
3U74
GND-AL
1 2 3 4 5 6 7 8
+3V3-STANDBY
+3V3
To be connect directly to 1A04 with 3mm Track width ** 1M99 **
IU43
9U41
2041145-8
RES 10K
**
3U69
BL-DIM1 BL-DIM2 BL-DIM3 BL-DIM4 BL-DIM5 BL-DIM6 BL-DIM7 BL-DIM8
10K
100R 100R 100R 100R 100R 100R 100R 100R
3U68
8 7 6 5 8 7 6 5
10u
1 2 3 4 1 2 3 4
1n0 1n0 1n0 1n0 1n0 1n0 1n0 1n0
2041145-9
3U84-1 3U84-2 3U84-3 3U84-4 3U85-1 3U85-2 3U85-3 3U85-4
10n
FU7A FU7B FU7C FU7D FU7F FU7G FU7H FU7J FU7K
1 2 3 4 5 6 7 8 9
* AL 2U56
* 1M54
B01A
* AL 2U89
B01A
2U81 2U82 2U83 2U84 2U85 2U86 2U87 2U88
4 Pin stuffing variant 1M11
RES RES RES RES RES RES RES RES
6 Pin stuffing variant 1M1B
IU44 IU45 9U42 RES
LED-1
LED2
LED2
3U59 10K RES
7U42 RES BC847BW
+12VIN IU47
+3V3
3U70
7U43 BC847BW
10n
RES 2U8D
3U41 10K RES
GND-AL
LED1
LED1
10K
3U53 10K
1u0
10n 2U68
3U71
STANDBY
3U82
100R
10n
1K0 RES 1 3U83-1 8
7U48-1 BC857BS(COL) FU77 6
2U54
STANDBY-1
1
2U47
+3V3-STANDBY
ENABLE-3V3-5V
cU40
100K
4 3U83-4 5
+12VD 1U40
+12V +3V3-STANDBY 4
10n
T 3.0A 32V
3
+12VIN 2U50
100n
2U71
2
100K
1M95 FU58 FU59 FU60
100HZ 3D with LX4 & LX25
100HZ 2D
LGD 50HZ 3D TM100
x x --
x -x
--x
7U48-2 BC857BS(COL)
+12V-AUDIO
3U61
10K
2 3U62-2 7
2
RES 10K
10K 5
22K
22K
3U60-3
4K7
6 6 8 7U41-1 BC847BS(COL) 1 10K
2
5 3U60-4 4
5
FU76
ENABLE-3V3n
22K
4 RES 10K
10n 2U46
3U62-1 1
7U41-2 BC847BS(COL)
3U63
1n0 2U45 RES
100p
100K
3K3
2U44
3
3U73 +3V3-STANDBY
DETECT2
3
POWER-OK
1
ENABLE-1V8
FU72
3U80
BL-DIM BL-I-CTRL
1K0
1n0
7U40-1 BC847BPN(COL)
3U60-2
100R
IU49
FU73
22K
7
3U43
IU55
3U64
3
100K
100K
1 3U60-1 8
6
2
2U55
100R
IU51
BL-DIM1
3U62-4
4 FU55
3U42
* 9U43 * 9U44
1K0
*
FU53
100R
3U72
3U45
FU51
PDZ6.2B(COL)
BL-ON BL-PWM
FU52
3U83-3
3
1u0 RES
IU56 10K
6U40
3U81
+3V3
1-2041145-4
6
5
10n
2U49
BL-ON-1 BL-DIM-1 BL-I-CTRL-1 POWER-OK-1
2 3U83-2 7 4
IU48
3
FU66
FU67
7U40-2 BC847BPN(COL)
10K
3U42 9U43 9U44
3U62-3
FU63 FU75
6
5
*
3U65
1 2 3 4 5 6 7 8 9 10 11 12 13 14
2U53
10-3-1
Power connectors
3139 123 6533
4
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3
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2
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Circuit Diagrams and PWB Layouts 10-3-2
Q552.4E LA
10.
EN 94
Interface connectors
Interface connectors
B01B
B01B
1C04
IC79
FC9F
+3V3
100K RES
V-AMBI
FC87
T 1.0A63V
3C75
100p
100R
2C77
3C76
100p
IC73
100R
2C78
IC74
3C77
100p
LIGHT-SENSOR 2C93
100p
100R
2C80
FC95
10K
KEYBOARD
100n
3C79 2C82
10R
1C86
100p
2.0A 63V
6C02
2041145-8
**
SDA-SET
9 10
FC97
FC98
100R
10p
6
RXD2-MIPS
100p
1u0 2C99 100p
2C97
RES 2C86 TXD2-MIPS
IRQ-CRP
FC9G
RES 3C71 RES 100R 3C73 47R RES 3C7A 47R
FC9H FC9J
100p
502386-0470
TEMPERATURE SENSOR
RES 2C72
10p 2C84
2C83
5
1 2 3 4
cC01
10p
3C83
TACHO
10p RES 2C7C
FC86
20
100R
1T71
FC96
19
FC9D
RES 2C7B
3C81 100R
13
FC9B
47R
502386-0870
FC85
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
FC9A
47R
3C72
3D-LED
12
RES 1C21 FH52-18S-0.5SH
0R3
RES 3C94 RES 3C95
SCL-SET
10p
AMP1 AMP2
**+T3C97
10p RES 2C87
+5V +12V
+5V
1C20 FH52-11S-0.5SH 1 2 3 4 5 6 7 8 9 10 11
**
1 2 3 4 5 6 7 8
** 2C91
**
RES * 1C03
* HOTEL TV
FC9L FC9K
4K7
100R 100R
3C96
* *
RES 3C98 RES 3C99
IC7H
1u0
2C90
+3V3-STANDBY
GND-AL
+3V3
T 1.0A 63V
30R
RES 5C53 +12V
2C85
5C54 +3V3
1u0
FC99
RES 1C85
SDA-BL
+5V
1 2 3 4 5 6 7 8
100n
3C78
2C81
IC75
LED-1
+12V-AL
GND-AL
SCL-BL
FC94
AMBI-SPI-OUT-CCLK
FH34SRJ-18S-0.5SH(50)
FH34SRJ-18S-0.5SH(50)
RXD1-MIPS TXD1-MIPS
RES PDZ5.6B(COL)
FC92 FC93
100p
T
FC91
+3V3-STANDBY 2C79
AV2-STATUS
FC77
FC90
RES
9C07
AMBI-SPI-OUT-MOSI
FC89
6C05
GND-AL
33R 10p 33R 10p
**
1C22
FC88
RES 6C07 PDZ5.6B(COL)
30R 100R
RES 2C94
FC76
20
100R
1u0
AMBI-TEMP
5C55 3C70
100n 2C70
FC73 FC74 FC75
3C7G 2C7M 3C7H 2C7N
To sensor & control
PDZ5.6B(COL)
10n
10u RES 2C7L
RES 2C7K
IC7G RES 9C09
LED-2
9C06
2C71
GND-AL
47n RES
10n
IC7D
FC71 FC72
10u 2C96
30R
2C95
RES 5C57
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
RC
19
IC7A RES 9C08
20
1u0
2C7F
1u0
1A04
19
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
+3V3
RES 3C7F
RES 1A05
V-AMBI
V-AMBI
RES 2C7G
RESERVED
6C03 RES
30R
2C76
PDZ5.6B(COL)
5C56
3C74
+3V3
IC78
Interface connectors
30R
3139 123 6533
4
2012-04-23
3
2011-12-12
2
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2012-Jun-29 back to
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Circuit Diagrams and PWB Layouts 10-3-3
Q552.4E LA
10.
EN 95
DC/DC
B02A
DC/DC
B02A 5U03 RES 30R 5U02
FU05
IU22 +12V
1u0
2U20
10u
10u
7 8
IU10
12V/1V8 CONVERSION
1
2
3R3
3U11
2U19
2U25
7U02-1 SI4952DY
10u
10u
2U23
2U24
0R
FU02
2U21
5U00
FU03 +1V8 22u
47u
2U16
1
47R
47R 3U23-1 2
2U15
7
8
3u6
5 6 4
IU23 1n0
2U17
3
IU09
3U23-2
6 3
4
7U02-2 SI4952DY
47R
47R 3U23-3
5
220p 3U23-4
IU11
IU15
IU08
5 6 7 8
IU12
4
3U14 IU07
20
VIN
V5FILT VREG5
3U28 GND-SIG
18 19
FU04
1u0
2U05
10u
2U04
6
10K
2U14
22u
IU17
IU25
GND
+1V1 100n
RES 100u 2.0V
7 17
2U13
1 2
47u
TEST
2U12
1 TRIP 2
22 15
10R RES
1 2
+1V1
3U20
PGND
FU01
2u0 47R
1 VFB 2
5U01
FU06
24 13
47R 3U24-1
1 2
3U24-2
SW
47R
1 VO 2
12V/1V1 CONVERSION
1 12
47R 3U24-3
1 2
1 2 3
STPS2L30A
DRVH
4 IU14
1n0
GND-SIG
1 EN 2
5 6 78
IU16
23 14
2U11
IU02
12K
GND-SIG
21 16
1 2
RES 2U06
IU18 1u0
2U10
GND-SIG
1n0
2U09
GND-SIG
FU00
3U21 IU19
SENSE+1V1
GND-SIG
2U07
22K
3U10
GND-SIG
CU01 CU02 CU03 CU04 CU05
5K6
FU08
100n
1% 330R 1% 1K0
CU00
3U19
FU09
IU04
2U08
3U22 1K0 1% 3U09
330R 1%
1K0 1%
3U08 +1V8
100p RES
IU20
RES 2U29
3U17 3U18
100R 1%
RES 100p
10K RES 3U01
+3V3-STANDBY
IU01 3U03
22K
3
1 2
RES 3U00
5 8
DRVL
7U04 SI4778DY-GE3
3U24-4
1n0 RES
2U03 IU03
4 9
+1V1 +1V8
1 VBST 2
220p
6U00
3 10
ENABLE-1V8
3R3
2U01
100n
2 11
IU24
GND-SIG 3U02
3U05
7U03 TPS53126PW
IU13
10R
2U02 100n
RES 7U00 BC847BW
3R3
2U22 IU06
IU05
RES
1 2 3
3R3
10u
2U00
10R
3U04
1n0
3U27
2U18
7U01 SI4778DY-GE3
IU21
GND-SIG
GND-SIG
GND-SIG
GND-SIG GND-SIG
DC/DC
3139 123 6533
4
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2
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Circuit Diagrams and PWB Layouts
10.
EN 96
DC/DC, 1.8 V to 1.2 V conversion
DC/DC 1.8 V to 1.2 V conversion
B02B
+12V
+5V
1
IN
OUT
FUA4
3
PDZ5.1B(COL)
2UB6
2
1u0
2UA4
COM FUA0
6UA0
7UC0 LF25ABDT
22u 16V
RES 9UA0
4K7
4K7
4 3UB0-4 5
4K7
3 3UB0-3 6
4K7
2 3UB0-2 7
1 3UB0-1 8
+3V3
CUA0
+2V5
+2V5-LVDS
2UB1 1u0
ADJ PGOOD
1 5
9
3UB1
FUA5 SENSE+1V2
3K9 1% 82K
3UB3
7UA4-2 RT9025-12GSP
7
3UB2
22 23 24 25 26
8
NC GND GND HS
+1V2
1n0
EN
FUA3
6
2UB3
VOUT
10K 1%
10u
2
VIN
10u
VDD 3
+1V8
2UB2
4
7UA4-1 RT9025-12GSP
VIA 18 19 20 21
VIA
VIA
10 11 12 13
VIA 14 15 16 17
B02B
2UB0
10-3-4
Q552.4E LA
DC/DC 1.8 V to 1.2 V conversion
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
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Circuit Diagrams and PWB Layouts
10.
EN 97
DC/DC, 12 V to 5 V/3.3 V conversion
B02C
DC/DC 12 V to 5 V/3.3 V conversion
B02C
12V/5V CONVERSION 7UD0 RT8293AHGSP
100u 16V
100u 16V RES 2UDF
RES 2UDH
22u
2UDC
10K 1%
22u
2K2 1%
RES 1n0
ENABLE-3V3-5V
IUDA 470p
RES
2UDG
10n
SS2_GND
15K RES 2UD7
cUD1 3UD1
2UD3
IUDH
22u 3UD5
4
SS2_GND
6
12K 3UD4
COMP GND GND HS
+5V
IUD6
2UDB
VIA
FUD3
10u
3UD3
10
5UD1
100n
22u 2UDA
FB
SS
1R0
3 5
2UD5
2UDD
100n
8
SW
IUD7
3UD0
IUD3
10R
IUDC
EN
1
RES
2UD4
BOOT
3UD2
7 10u
2UD2
10u
2UD1
10u
2UD0
0R
VIN
3n3
2
2UD6
IUD0
9
5UD0 +12V
SS2_GND SS2_GND SS2_GND SS2_GND
12V/3V3 CONVERSION 7UD1 RT8293AHGSP
IUD9
SS1_GND
RES
SS1_GND
470p
cUD2
100u 16V
100u 16V RES 2UFB
RES 2UFA
22u
22u RES 2UF9
22u RES 2UF8
22u 2UF7
1K5 1%
3UF4
IUD4
4K7 1% 2UF6
+3V3
100K 3UF6
SS1_GND
6
FUD2
10u
IUD5
3UF5
COMP GND GND HS
5
5UD2
100n
10R
VIA
1R0
3
2UF2
2UF5
ENABLE-3V3-5V
FB
IUD8
RES
10
SS
3UF1
3UF3
8
SW
4
100n
IUDG
EN
IUD2
10n
2UF1
7
1
12K RES 2UF4
10u
2UF0
10u
2UD9
10u
IUDF
BOOT
3UF2
0R
VIN
3n3
2
2UF3
IUD1
9
5UD3 +12V
2UD8
10-3-5
Q552.4E LA
SS1_GND SS1_GND
SS1_GND
DC/DC 12 V to 5 V/3.3 V conversion
3139 123 6533
4
2012-04-23
3
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2
2011-05-25
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Circuit Diagrams and PWB Layouts
10.
EN 98
DVBS supply
DVBS supply
B03A
5T00
IT00 7T00 TPS54227DDA
Φ
SS
1
SW
EN VREG5
7
IT02
2T05 5T01
100n 6
IT18
3
IT24
FT06
2T10
10 11
5
9
3T00 RES 68K 3T04 RES
10n
8K2 1% 2T13
GND-1V0
1%
1n0 RES 2T14
22K
GND-1V0
470K
IT04
RES 3T02
2T04
1n0
RES 2T03
GND-1V0
VIA
1u0
IT01 GND_HS GND
+1V0-DVBS
3u0 22u
4 +2V5-DVBS
VBST
VFB
22u 2T12
2
RES 2T15
VIN
STEP DOWN
3T01
100n
10u 2T02
10u
2T01
30R
8
+12V-DVBS
22p 3T05
GND-1V0
FT07
SENSE+1V0-DVBS
8K2 1% 3T06 68K
cT01
+5V
+3V3
7T03-2 RT9025-12GSP
2T16
22 23 24 25 26
GND-1V0
VIA
5T03
EN
ADJ PGOOD
NC GND GND HS
6
+1V2-FE
7 1 5
VIA
VIA
VIA 14 15 16 17
VOUT
10u RES 2T20
VIN
10 11 12 13
9
10u
2
8
3
FT09
18 19 20 21
220u 6.3V
VDD
2T18
30R
1u0
4
7T03-1 RT9025-12GSP
+1V8
2T17
B03A
2T00
10-3-6
Q552.4E LA
DVBS supply
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
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2012-Jun-29 back to
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Circuit Diagrams and PWB Layouts
10.
EN 99
Core voltage supply for DVBS demodulator
Core voltage supply for DVBS demodulator
B03B
+12V
+12V-DVBS
1TP1 T
3.0A 32V
+12V-DVBS
100n
10u
5TP5
B230LA-M3
6TP6
RS1D
6TP5
2TPH
47u 35V
2TPG
17
7TP2 LNBH25PQ
+12V-DVBS +V-LNB
470n
10u 2TPC
ITPJ
10u 2TPD
VCC
47R
7
SDA-SSB-550
3TPD
47R
8 19
F22-DISECQ-TX 3TP3
DEBUG 6TP1
1K0
LTST-C190KGKT
DEBUG
3TPF
2 18
SCL SDA
DSQ
DETIN
NC
IN OUT FLT BPSW
ITP2 9
VIA
ISEL GND_HS
+V-LNB
FTPA
20 1 5 10 11 12 13 14 24 26 27 28 29 30 31 32 33
ITPG
25
4
PGND
22K GND
+5V
22 23
VOUT
2TPF
3TPB
ADDR
470n
21
47u 35V
SCL-SSB-550
VUP
2TPJ
B230LA-M3
6
16
ITPF
6TP4
VBYP
ITP4
3
220n
LX
2TPK
Φ
15
B03B
2TPL
10-3-7
Q552.4E LA
Core voltage supply for DVBS demodulator
3139 123 6533
4
2012-04-23
3
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2
2011-05-25
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Circuit Diagrams and PWB Layouts
10.
EN 100
DDR
DDR
3B28
DDR2-CLK_P
240R
DDR2-CLK_N
G2 G3 G1
DDR2-BA2
DDR2-ODT RES 3B01
F9 E8 F8 F2 G8 F7 G7 F3 B3
240R
DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM2
3B23
0 1 2 3 4 5 6 7
DQS
C8 3 C2 D7 1 D3 D1 D9 3B00-4 4 B1 B9 3B00-1 1
2 6 3B02-3 33R 3 8 3B02-1 33R 2 3B02-2 5 3B02-4 4 33R 8 33R
B7 A8
NU|RDQS
3B00-2
7 33R 6 3B00-3 33R 7 33R 5 33R
3B12 33R
3B13 2B44 RES
0 1 BA 2
2p2
DDR2-D16 DDR2-D17 DDR2-D18 DDR2-D19 DDR2-D20 DDR2-D21 DDR2-D22 DDR2-D23
DDR2-DQS2_P DDR2-DQS2_N
33R
A2
H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 G1
DDR2-BA0 DDR2-BA1 DDR2-BA2
DDR2-ODT
ODT
RES 3B03
CK CKE CS RAS CAS WE DM|RDQS VSS
NC
L3 L7
DDR2-A14
VSSQ
VSSDL
F9 E8 F8 F2 G8 F7 G7 F3 B3
240R
DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM3
3B24 33R
2B17 100n 2B37 100p VDD
VDDL
E2
A9 C1 C3 C7 C9
E1
A1 E9 L1 H9
100n
100n 2B16
100n 2B15
100n 2B14
100n 2B13
100n 2B12
100n 2B11
100n 2B10
47u 2B09
E2
E1
A9 C1 C3 C7 C9
DQ
A3 E3 J1 K9
33R
2B41
2B36 100p 2B08 100n
DDR2-BA0 DDR2-BA1
SDRAM
DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13
VREF
VDDQ
Φ
0 1 2 3 4 5 6 A 7 8 9 10 11 12 13
SDRAM DQ
0 1 2 3 4 5 6 7
DQS
C8 3B05-3 C2 3B04-3 D7 D3 D1 D93B04-4 B1 B93B04-1
4 1
B7 A8
NU|RDQS
3B14 33R
3B15 2B45 RES
0 1 BA 2
3B04-2 2 7 6 33R 6 33R 33R 33R 2 7 3B05-2 1 8 3B05-1 33R 5 5 3B05-4 33R 4 33R 8 33R
3 3
DDR2-D24 DDR2-D25 DDR2-D26 DDR2-D27 DDR2-D28 DDR2-D29 DDR2-D30 DDR2-D31
DDR2-DQS3_P DDR2-DQS3_N
33R
2p2
A2
ODT CK CKE CS RAS CAS WE DM|RDQS VSS
+1V8
NC
L3 L7
DDR2-A14
VSSQ
VSSDL
A7 B2 B8 D2 D8
DDR2-CLK_P DDR2-CLK_N
7B03 EDE1108AGBG-1J-F
VREF
VDDQ
Φ
B04A
DDR2-VREF-DDR
E7
3B27 240R
VDDL
A3 E3 J1 K9
DDR2-CLK_N
VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13
A7 B2 B8 D2 D8
DDR2-CLK_P
240R
H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8
E7
3B22
DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13
A1 E9 L1 H9
7B02 EDE1108AGBG-1J-F
AT T-POINT
+1V8
DDR2-VREF-DDR
100n
100n 2B07
100n 2B06
100n 2B05
100n 2B04
100n 2B03
100n 2B02
100n 2B01
47u 2B00
+1V8
2B40
B04A
+1V8 DDR2-VREF-DDR
DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM0
FB00
1X20 HOOK1
1X21 HOOK1
1X22 HOOK1
1X23 HOOK1
3B25 33R
0 1 2 3 4 5 6 7
DQS
C8 C23B08-4 4 D7 D3 3B08-2 2 D1 D9 3B07-4 4 B1 B9 3B07-1 1
B7 A8
NU|RDQS
2 5 33R 7 33R 5 33R 8 33R
2p2
3 1 3
3B07-2
7 33R 6 3B07-3 33R 8 3B08-1 33R 6 3B08-3 33R
3B16 33R
3B17 2B46 RES
0 1 BA 2
DDR2-D0 DDR2-D1 DDR2-D3 DDR2-D2 DDR2-D4 DDR2-D5 DDR2-D6 DDR2-D7
DDR2-DQS0_P DDR2-DQS0_N
33R
A2
DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13
H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8
DDR2-BA0 DDR2-BA1
G2 G3 G1
DDR2-BA2
DDR2-ODT
ODT
3B09
CK CKE CS RAS CAS WE DM|RDQS VSS
NC
VSSDL
L3 L7
DDR2-A14
VSSQ
DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM1
RES 240R
3B26 33R
F9 E8 F8 F2 G8 F7 G7 F3 B3
2B35 100n 2B39 100p VDD
VDDL
VDDQ
E2
A9 C1 C3 C7 C9
E1
A1 E9 L1 H9
100n
100n 2B34
100n 2B33
100n 2B32
100n 2B31
100n 2B30
100n 2B29
100n 2B28
47u 2B27
E2
E1
DQ
A3 E3 J1 K9
3B21
DDR2-VREF-DDR
240R
F9 E8 F8 F2 G8 F7 G7 F3 B3
Φ
SDRAM
VREF
Φ
0 1 2 3 4 5 6 A 7 8 9 10 11 12 13
SDRAM DQ
0 1 2 3 4 5 6 7
DQS
C8 C2 3B11-3 3 D7 3B10-3 33R 3 D3 D1 D93B10-4 4 B1 B93B10-1 1
B7 A8
NU|RDQS
2 1 5 3B11-1 33R 4 8 33R
3B10-2
2p2
7 33R
7 3B11-2 8 33R 33R 3B11-4 33R
5
3B18 33R
3B19 2B47 RES
0 1 BA 2
2 6 6 33R
DDR2-D8 DDR2-D14 DDR2-D10 DDR2-D11 DDR2-D12 DDR2-D13 DDR2-D9 DDR2-D15
DDR2-DQS1_P DDR2-DQS1_N
33R
A2
ODT CK CKE CS RAS CAS WE DM|RDQS VSS
NC
VSSDL
L3 L7
DDR2-A14
VSSQ A7 B2 B8 D2 D8
3B20
180R 1%
RES 3B06
7B01 EDE1108AGBG-1J-F
VREF
E7
DDR2-BA2
DDR2-ODT
VDDQ
A3 E3 J1 K9
G2 G3 G1
VDDL
2B43
2B26 100n 2B38 100p
DDR2-BA0 DDR2-BA1
VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13
A7 B2 B8 D2 D8
H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8
E7
+1V8
DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13
A1 E9 L1 H9
7B00 EDE1108AGBG-1J-F
A9 C1 C3 C7 C9
100n
100n 2B25
100n 2B24
100n 2B23
100n 2B22
100n 2B21
100n 2B20
100n 2B19
47u 2B18
2B42
DDR2-VREF-DDR
180R 1%
10-3-8
Q552.4E LA
1X24 HOOK1
DDR
3139 123 6533
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2012-04-23
3
2011-12-12
2
2011-05-25
19220_038_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 101
PNX 85500: Power
PNX 85500: Power
B05A
5S80
IS3Q
30R
1
100n
2S5A
10u
2
+1V1 2S6A
B05A
5S81 10u
2S5B
5S82
VDD_3V3_SBY
10u
2S5D
2S4M
100n
1 10u
2S4P
100n
2S4N
VSSA_USB
VDDA_2V5_VADC VDDA_2V5_VDAC VDDA_3V3_USB
100n
2S4Y
10u
2S50
100n
2S4Z
6.3V 10u
100n
c000
SENSE+1V2
Y17 D13 T20 Y13
+2V5-AUDIO
Y10
100n
VDDA_2V5_USB
+1V2 30R
R21
R20
VSSA_2V5_LVDS_BG
100n
2S45
+2V5-AUDIO
5S87 +2V5 1u0
2S56
100n
2S55
30R
5S88 30R
10u
100n 2S57
2S5M
+2V5-LVDS
+2V5 100n 2S58
30R
1
10u
2 100n 2S6K
1
2S6H
2
5S89
5S90 +2V5 10u
100n 100n
2S53
2S4T
30R
2SHW
5S92 1u0
100n 2S59
2
+3V3 30R
1
100n 2S6L
2S6M
2
IS58
1
VDD_1V1_DDR
VSSA_1V1_LVDS_PLL
VDDA_2V5_LVDS_BG
+2V5 5S84
AA9 AA7
30R
30R
2S46
VDDA_2V5_DCS
5S95
Y12
1u0 2S4W
+1V1 IS3L
2S52
VDDA_2V5_ADAC
5S83
B13
2S51
VDDA_2V5_AADC
10u
100n
Y19 Y18
AA15 Y15 VDDA_1V2 AA13 VDDA_2V5
2S6P
2
+3V3-STANDBY
IS3K VDDA_1V1_LVDS_PLL
+3V3
30R
1
100n
100n 2S6C
2 100n 2S6N 1
2
W20 P20 M20 K20 V7 Y8
100n 1 2S6G 2
5S85
10u 2S4U
VDD_1V1
C7 C9 C11 C14 C16 C18
2S4V
VDD_3V3
+2V5-LVDS
N6 N7
2S6F
VDD_2V5_LVDS
U22
1
VDD_2V5
220u 6.3V
2
100n 2S6R 2
U20 U21
2S6D
HDMI_VDDA_2V5
+2V5
30R
1
HDMI_VDDA_1V1
V20 V21
HDMI_VDDA_3V3_TERM
C13
1u0
2S21
100n
2 1
VDD
HDMI_AGND
J7
30R
VDD_1V8
A13
2S29
220u 2V0
7
5 100n
4
100n 2S5J-4
100n 2S5J-2 2
3 5S94
+1V1
2S5P
VSS
10u
VSS
VSS
2S4S
VSS
M7 N2 N20 P10 P12 P14 P16 P18 P4 P6 P7 T10 T12 T14 T16 T18 T2 T6 T7 U4 V10 V12 V14 V16 V18 V2 Y20
AF1 AE2 AD3 AC4 AB5 H20 F11 G11 F13 G13 F15 G15 F17 G17 F19 G19 J9 J11 J13 J15 J17 L9 L11 L13 L15 L17 N9 N11 N13 N15 N17 R9 R11 R13 R15 R17 U9 U11 U13 U15 U17 J6 AA6 Y7 W7 F9 G9
U24 V24
100u
2S23
5 100n
4
100n 2S5H-4
6 3
100n 2S5H-3
8 100n 2S5H-2 8 100n 2S5J-1
5
6
1
3
4
100n 2S5J-3
6
7
AA16 AA8 Y11 Y14 Y16 Y9 VSSA
G14 G16 G18 G2 G20 G8 H4 H6 H7 J20 K10 K12 K14 K16 K18 K2 K6 K7 L20 L4 M10 M12 M14 M16 M18 M6
A1 A10 A12 A15 A17 A19 A26 A3 A8 B1 B20 C20 C4 D2 D20 E13 E20 E4 F10 F12 F14 F16 F18 F20 F8 G10 G12
100n 2S5K-4
100n 2S5K-3
100n 2S5K-2 2
1
2S5K-1
8
4
2
6
5
1
100n 2S5H-1
100n 2S5G-4
3
100n 2S5G-3
7 2
100n 2S5G-2
2S5G-1 1
22u
22u 2S4R
100n
2S4Q
100n
2S27
2S28
2S43
8
7
+1V1
30R
5S93 L6 L7 R6 R7 U7 A5 A6 B5 B6 C6 D6 E6 F6 G6 F7 G7
7S00-10 PNX85500
7S00-12 PNX85500
100n
2S5C
2
+3V3
c001
SENSE+1V1
30R
1
100n
2S6B
2
+2V5
IS3S
100n
100n 2S68
100n 2S67
100n 2S66
100n 2S65
100n 2S64
100n 2S63
100n
2S62
100n 2S61
100u 2S60
2S26
+1V8
100n
10-3-9
Q552.4E LA
PNX 85500 Power
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_039_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts 10-3-10
Q552.4E LA
10.
EN 102
PNX 85500: Standby controller
PNX 85500: Standby controller
B05B
+1V1
B05B
100n
1u0 2S10
2S13
30R
RES 5S04
IS3B
2S37 1u0 2S11
IS20
10K 3S3T 10K
+3V3-STANDBY 3S1H 10K
3S1G
RXD-UP TXD-UP
10K 3S2A
RXD-UP TXD-UP DETECT2
AE21 0 AF21 1 AA22 2 AB22 P3 3 AC22 4 AD22 5
RESET-SYSTEMn AV2-BLK AV1-BLK KEYBOARD LIGHT-SENSOR AV1-STATUS AV2-STATUS
AD23 0 AE26 1 AE25 P5 2 AE24 3
DETECT2
10K RES 3S1K 10K RES
RESET-SYSTEMn 3S1J 100K RES
KEYBOARD 2S4C 100n
3S1L 10K
SPI-PROG
SPI-PROG PNX-SPI-WPn
AF22 4 AE22 P6 5
PSEN MC
54M
1S02
AC17
AF26
VDD_XTAL
ALE
RESET-STBYn
AB24
EA
AB23
ALE
AC26
PSEN
AC23 SDA AC24 SCL
AD26 0 AC25 PWM 1
3S2F 100R
100R
3S2G
100R
3S2K
3S2H 100R
SDA-UP-MIPS SCL-UP-MIPS LED1 LED2
AE23 SDO AF25 SDI SPI AF24 CLK AF23 CSB
IS3F
3S44
IS3G
10K
3S43
IS3D
10K 3S42
10K
EA ALE PSEN RES
SDA-UP-MIPS SCL-UP-MIPS
3S6V
RES
LED1 LED2
3S4A
100R
FS0Y IS2Z
CTRL-DISP3 RESET-DVBS RESET-USBn RESET-ETHERNETn SEL-HDMI-ARC RESET-AVPIP RESET-AUDIO AUDIO-MUTE-UP
CTRL-DISP3 RESET-DVBS RESET-USBn RESET-ETHERNETn SEL-HDMI-ARC RESET-AVPIP RESET-AUDIO AUDIO-MUTE-UP
3S1P
4K7
RES
3S41
10K 10K
PNX-SPI-SDO PNX-SPI-SDI PNX-SPI-CLK PNX-SPI-CSBn
AB17 0 AA18 1 AD18 2 AE18 3 AF18 P0 4 AA19 5 AB19 6 AC19 7
3S6W
4K7
RES RES RES RES RES RES
3S2L 3S46 3S3Y 3S47 3S2S 3S2M 3S3W 3S49
10K 10K 10K 10K 10K 10K 10K 10K
+3V3-STANDBY
+3V3-STANDBY
7S20 NCP803
10K
RES 3S3S
EA
AA26
3S2V
10K
AC20 0 AD20 1 AE20 2 AF20 3 AA21 P2 4 AB21 5 AC21 6 AD21 7
+3V3-STANDBY
10p
VCC RESET GND
FS0Z
2
RESET-STBYn
1n0
3S3P
LCD-PWR-ONn EJTAG-DETECTn BL-ON STANDBY CTRL-DISP1 CTRL-DISP2 POWER-OK ENABLE-3V3n
RESET_IN
STANDBY
10p 2S4F
AF17
RES 2S4L
10K
LCD-PWR-ONn EJTAG-DETECTn BL-ON STANDBY CTRL-DISP1 CTRL-DISP2 POWER-OK ENABLE-3V3n
1
3
3S3M
RES 10K 3S3N RES 10K 3S3Q RES 10K 3S3R 10K RES
2 4
AE17
1
3S3L
10K
7S00-9 PNX85500
XTAL_OUT
2S4G
3
1
XTAL_IN
AD17
3S1A 10K +3V3-STANDBY
AD19 0 AE19 1 AF19 2 P1 AA20 3 AB20 7
100n
10K 3S1D 27K
RES 10K RES 3S1F
RC TACHO CEC-HDMI BACKLIGHT-PWM-ANA-DISP SDM
VDDA_ADC2V5
3S1C
RC TACHO CEC-HDMI BACKLIGHT-PWM-ANA-DISP SDM
VSS_XTAL
2S4D 1n0
3S1B
DS50
2S4K
+3V3-STANDBY
VDDA_1V1_DCS
AA17
POL
100n
PNX 85500 Standby controller
3139 123 6533
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2012-04-23
3
2011-12-12
2
2011-05-25
19220_040_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
B05C
* 3D ACTIVE
+3V3
7S00-3 PNX85500
CONTROL
3D-LR
3S82
BL-I-CTRL-PNX
+3V3 10K
RES 3S21
10K 10K
+3V3
FS10 TXD2-MIPS FS11 RXD2-MIPS IS04
* 9S09
GPIO6 PNX-SPI-CS-BLn
BL-I-CTRL-PNX GPIO6
SELECT-SAW
PNX-SPI-CS-BLn
+3V3
USB-DM USB-DP
10K
SELECT-SAW
2
SDA SCL
3
SDA SCL
4
SDA SCL
RESET_SYS
5K6
+3V3
3S55
10K
RES 3S64
GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_10 GPIO_11
TRSTN TMS R26 DN TCK R25 USB DP TDO IS4Z R24 RREF TDI
10K RES 3S62
IS16
BL_PWM
FS64
CLK_54_OUT
3S83
3S5Y
B25 A24
1 100R
B24 A23
3S60 1 2 100R
2 3S5W
2
3S6C
2K2
SDA-SSB-550 SCL-SSB-550
SDA-SSB-550 SCL-SSB-550
3S6L
2K2
1 100R
2
3S61
SDA-TUNER SCL-TUNER
SDA-TUNER SCL-TUNER
3S6G
2K2
3S6B
2K2
3S6D
2K2
3S6F
2K2
3S6K
EJTAG-TRSTn-PNX85500 EJTAG-TMS-PNX85500 EJTAG-TCK-PNX85500 EJTAG-TDO-PNX85500 EJTAG-TDI-PNX85500
1 10K
8 3S6H-1 10K 3 6 3S6H-3 10K 2 10K
+3V3-STANDBY 7 3S6H-2 5 3S6H-4 4 10K RES 1F10
RESET-SYSTEMn
33R
AD5
SDA-SET SCL-SET
3S5Z
3S00
4K7
4K7
2
EJTAG-TRSTn-PNX85500 EJTAG-TMS-PNX85500 EJTAG-TCK-PNX85500 EJTAG-TDO-PNX85500 EJTAG-TDI-PNX85500
AE4
3S6A
1 100R
AA25 AA24 AA23 AB26 AB25
BL-DIM
AC5
RXD1-MIPS
+3V3
1 100R
SDA-SET SCL-SET
3S69
SDA-UP-MIPS SCL-UP-MIPS
cS51 cS52 cS53
SDA-SSB-550 SCL-SSB-550
RESET-SYSTEMn
SDA-FE SCL-FE RESET-FUSION-OUTn
FS44
EJTAG-TRSTn-PNX85500 EJTAG-TMS-PNX85500 EJTAG-TDO-PNX85500 EJTAG-TCK-PNX85500 EJTAG-TDI-PNX85500
FS49 FS50 FS51 FS52
EJTAG-DETECTn
FS53
3D-VS
10K 3S84
TXD1-MIPS
+3V3
+3V3
3S72
BL-DIM
10 9
+3V3
1 2 3 4 5 6 7 8
FOR FACTORY USE ONLY
100R
10K
+3V3
FS57
BM08B-SRSS-TBT
RES
+3V3 RES 2S89 100n RES 7S01 PCA9540B
VDD
SCL-SET SDA-SET
1 2
+3V3
3
3S80 3S81
IS17
3S58 1 2 100R
B26 A25
SDA-UP-MIPS SCL-UP-MIPS
10K
FS54
10K
Y21 Y22 Y23 Y24 W21 W22 W23 V22 V23 U23
2 3S57
3S27
* 3S40
BOOTMODE 3D-LR RXD1-MIPS TXD1-MIPS RXD2-MIPS TXD2-MIPS
1 100R
10K
10K
3S56 1 2 100R
C25 SDA C26 SCL
3S26
1
BOOTMODE
RES 3S6J
IS05
3S45 +3V3
+3V3 +3V3
EN 103
PNX 85500: MIPS
B05C
+3V3
10.
PNX 85500: MIPS
10K
10-3-11
Q552.4E LA
SCL SDA
INP FIL
I 2 C -BUS CTRL
SC0
5
SCL-DISP
SC1
8
SCL-BL
SD0
4
SDA-DISP
SD1
7
SDA-BL
SCL-DISP
RES 3S65
4K7
SCL-BL
RES 3S66
4K7
SDA-DISP
RES 3S67
4K7
SDA-BL
RES 3S68
4K7
6
VSS
FS31
9S10 RES IS08 SCL-SET
7S00-4 PNX85500
+3V3
3S85-3 3S85-2 3S86-2 3S85-4
3 2 2 4
6 7 7 5
47K 47K 47K 47K
SDIO-CMD SDIO-DAT0 SDIO-WP SDIO-DAT2
3S86-4 3S85-1 3S86-3 3S86-1
4 1 3 1
5 8 6 8
47K 47K 47K 47K
SDIO-DAT3 SDIO-DAT1 SDIO-CDn
RES 3S87 47K
SDIO-CLK
SDA-SET
AA3
ETH-RXD(0) ETH-RXD(1) ETH-RXD(2) ETH-RXD(3)
Y5 0 Y6 1 AB4 RXD ETH 2 AC1 3
IS50
ETH-RXDV ETH-RXER
AC2 RXDV Y4 RXER
SDIO-DAT3 SDIO-CLK SDIO-CMD SDIO-DAT0 SDIO-DAT1 SDIO-DAT2 SDIO-CDn SDIO-WP
W2 W1 W6 W5 W4 W3 U6 V6
FS2W
SCL-DISP
9S12
FS2Y
SDA-DISP
9S13 RES
SDA-BL
ETHERNET
ETH-RXCLK
RXCLK
IS09
SCL-BL
9S11
TXCLK 0 1 2 3 TXEN TXER COL CRS MDC MDIO
TXD ETH
CC_DAT3 CLK CMD 0 SDIO 1 DAT 2 SDCD SDWP
AA2
ETH-TXCLK
AA1 AA4 AB1 AB2 AA5 AB3 AC3 Y2 Y3 Y1
ETH-TXD(0) ETH-TXD(1) ETH-TXD(2) ETH-TXD(3) ETH-TXEN ETH-TXER ETH-COL ETH-CRS ETH-MDC ETH-MDIO
PNX 85500 MIPS
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3
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2
2011-05-25
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div. table
Circuit Diagrams and PWB Layouts
10.
EN 104
PNX 85500: Control
PNX 85500: Control
+3V3-STANDBY
B05D
+3V3-STANDBY
+3V3
3F66
2
PNX-SPI-SDI
Q
Φ
512K FLASH
D C
5
PNX-SPI-SDO
6
PNX-SPI-CLK
1
S
PNX-SPI-CSBn IF54
3
W
7
HOLD
BL-I-CTRL 7F53 RES PDTA114EU
PNX-SPI-WPn
IF55
BL-I-CTRL-PNX
+5V
+3V3-STANDBY FF28
VSS
FF29
7F54-1 RES BC847BPN(COL) 6
7F54-2 RES BC847BPN(COL)
SPI-PROG
4
IF56 4
IF57 FF03
47K
VCC
3F68 RES
RES 3F67
7F52 M25P05-AVMN6
+3V3
+3V3
10K
8
3F52
100n RES
2F52
100p
2F49
+3V3-STANDBY
10K RES
B05D
10K
2 1
5
FF04
SDM 3 RES 3F53
FF58
DEBUG ONLY 2F58 RES
1 2 3
0 1 2
FF61
ADR SDA
1K0
100R FF62
SDA-SSB-550
8
WC
RES 3F54
RES 1F52
3F62
3F63
FF63
SCL
4
100R
SCL
1 2 3
SDA 5
7 6 5
FF55
3F59 100R
3F60
SCL-UP-MIPS
FF56
SDA-UP-MIPS
100R
4
IF59
Φ (8K × 8) EEPROM
10K
3F58
9F51
SCL-SSB-550
100n 7F58
10K
MAIN NVM
+3V3
RES 3F69
RES 2F53
10K
1u0
10-3-12
Q552.4E LA
FF57
LEVEL
DEBUG / RS232 INTERFACE
TXD-UP RXD-UP RESET-STBYn SPI-PROG
FF65
3F64
FF66
100R
SHIFTED
RES 1F51 FF64
3F65 100R
7
6
1 2 3 4 5
UP
FOR DEBUG USE ONLY
PNX 85500 Control
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3
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2
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Circuit Diagrams and PWB Layouts 10-3-13
Q552.4E LA
10.
EN 105
PNX 85500: SDRAM
B05E
PNX 85500: SDRAM
B05E
7S00-6 PNX85500 T25 T26
HDMIA-RX1+ HDMIA-RX1-
U25 P U26 RX1_A N
P RX0_A N
DDC_A
Y26 SCL Y25 SDA
HDMIA-RX0+ HDMIA-RX0-
V25 P RX2_A V26 N HOT_PLUG_A
HDMIA-RXC+ HDMIA-RXC-
W25 P W26 RXC_A N
DDCA-SCL DDCA-SDA IS10
T24
IS01
3S0W
W24
RREF
10u
12K
F3 C2 F2 C3 B4 F1 C1 E1 F4 B2 E5 C5 A4 G5 B3 F5 U3 P2 U2 P3 N1 U1 P1 T1 V4 R5 U5 P5 N3 V3 R4 V5
3S07
180R 1%
180R 1%
3S22
DDR2-VREF-CTRL2
2S12
CLK
N P
DQS0
N P
DQS1
N P
DQS2
N P
DQS3
N P
CASB CKE CSB ODT PCAL RASB WEB 1 VREF 2
DDR2-CLK_N DDR2-CLK_P
3S30
N5 N4
10R
3S33 10R
E2 E3
DDR2-DQS0_N DDR2-DQS0_P
D3 D4
DDR2-DQS1_N DDR2-DQS1_P
R1 R2
DDR2-DQS2_N DDR2-DQS2_P
T3 T4
DDR2-DQS3_N DDR2-DQS3_P
K3 K4 L5 M4 M1 M5 H3
DDR2-CAS DDR2-CKE DDR2-CS DDR2-ODT DDR2-RAS DDR2-WE
A2 V1
DDR2-CKE
3S6Q 10K
DDR2-ODT
3S6P 10K RES
DDR2-VREF-CTRL2 DDR2-VREF-CTRL3
3S0V
FS01
DDR2-VREF-CTRL3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DQ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
2S24
FS02
100u 2.0V
3S06
180R 1%
180R 1%
3S20
+1V8
M0
DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-A14
IS42 261R
DDR2-D0 DDR2-D1 DDR2-D3 DDR2-D2 DDR2-D6 DDR2-D5 DDR2-D4 DDR2-D7 DDR2-D8 DDR2-D9 DDR2-D10 DDR2-D11 DDR2-D12 DDR2-D13 DDR2-D14 DDR2-D15 DDR2-D16 DDR2-D17 DDR2-D19 DDR2-D18 DDR2-D22 DDR2-D23 DDR2-D20 DDR2-D21 DDR2-D24 DDR2-D30 DDR2-D26 DDR2-D25 DDR2-D28 DDR2-D31 DDR2-D27 DDR2-D29
0 1 DM 2 3
J1 J3 K1 G4 L3 G3 L2 H5 L1 J5 J2 M3 J4 M2 K5
1%
D1 D5 R3 T5
0 1 2 3 4 5 6 7 A 8 9 10 11 12 13 14
100p
DDR2-DQM0 DDR2-DQM1 DDR2-DQM2 DDR2-DQM3
MEMORY
0 1 BA 2
100n 2S25
DDR2-BA2
H1 H2 G1
DDR2-BA0 DDR2-BA1
100n 2S17
7S00-8 PNX85500
100p 2S20
RES 2S2A
+3V3
HDMI_DV
HDMIA-RX2+ HDMIA-RX2-
PNX 85500 SDRAM
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Circuit Diagrams and PWB Layouts
10.
EN 106
PNX 85500: Nandflash - conditional access
PNX 85500: Nandflash - conditional access
B05F
7S00-5 PNX85500
D22 ALE C21 NAND CLE
XIO-A00 XIO-A01 XIO-A02 XIO-A03 XIO-A04 XIO-A05 XIO-A06 XIO-A07 XIO-A08 XIO-A09 XIO-A10 XIO-A11 XIO-A12 XIO-A13 XIO-A14
J25 J26 H21 H22 H23 H24 H25 H26 G21 G22 G23 G24 G25 G26 F22 F23
IS25
00 01 02 03 04 05 06 07 XIO_A 08 09 10 11 12 13 14 15
XIO-D00 XIO-D01 XIO-D02 XIO-D03 XIO-D04 XIO-D05 XIO-D06 XIO-D07 XIO-D08 XIO-D09 XIO-D10 XIO-D11
XIO
B22 OE_ C22 WE_
XIO-OEn XIO-WEn
CLK_BURST CE1_ CE2_ NAND RDY2 RDY1 WP_
INPACK XIO-D14 XIO-D15
B21 E21 D21 A20 F21 A21
IS26
INPACK
3S15 10K
+3V3 NAND-CE1n
NAND-RDY1n NAND-WPn
9S08
10K RES
NAND-ALE NAND-CLE
D25 D26 C24 D23 C23 B23 A22 E22 F24 F25 F26 E23 E24 E25 E26 D24
00 01 02 03 04 05 06 07 XIO_D 08 09 10 11 12 13 14 15
3S1V
FLASH
10K
+3V3
Non CI * 3S1W
B05F
+3V3
J22
CA-DATADIR
K25 K26
CA-DATAENn
3S03
CA-MICLK
N23 10R L25
CA-MOCLK
N24 3S31 CA-MIVAL 33R
CA-MOSTRT
N25 L22 L23
CA-MOVAL
J21 CA-RDY
L24
CA-RST
L26 J23
RES 9S01
CA-MISTRT
J24
CA-MDO0 CA-MDO1 CA-MDO2 CA-MDO3 CA-MDO4 CA-MDO5 CA-MDO6 CA-MDO7
XIO-D00 XIO-D01 XIO-D02 XIO-D03 XIO-D04 XIO-D05 XIO-D06 XIO-D07 NAND-CE1n NAND-CLE NAND-ALE
ADD_EN DATA_DIR
VS
K23 1 K24 2
CD
K21 1 K22 2
DATA_EN I MCLK O
37
100n
VCC
N26 M21 M22 M23 M24 M25 M26 L21
9S00
CA-VS1n CA-MOCLK
3S0A-1 1 3S0A-3 3 3S0B-1 1 3S0B-3 3
3S0C-2 2 +3V3
XIO-OEn XIO-WEn NAND-WPn
CA-CD1n CA-CD2n
CA
3S0D 3S0C-4 4
100R 3S0A-2 6 100R 3S0A-4 8 100R 3S0B-2 6 100R 3S0B-4
2
7
100R 100R
4
5
2
7
100R
4
5
100R IS0A
6
100R
8
100R
7 100R 3S0C-3 3 10K 3S0C-1 1 5 100R
16 17 9 8 18 19 6 7
IS0B 3S0F
+3V3
+3V3
29 30 31 32 41 42 43 44
8
2K2 NAND-RDY1n
MISTRT MIVAL MOSTRT MOVAL OOB_EN
TS-CHDEC-DATA
3S1R
560R
TS-CHDEC-CLK
3S1S
560R
TS-CHDEC-VALID
3S1T
560R
TS-CHDEC-SOP
3S1U
560R
TS-CHDEC-DATA
3S23
470R
0 1 2 3 IO 4 5 6 7 CLE ALE CE_ RE WE WP SE R B
NC
IS0C
* Non DVBS / T2 / LATAM * Non DVBS / T2 / LATAM
1 2 3 4 5 10 11 14 15 20 21 22 23 24 25 26 27 28 33 34 35 38 39 40 45 46 47 48
RDY RST VCCEN VPPEN
T21 DATA T23 ERR T22 TNR_SER1 MICLK R23 MIVAL R22 SOP
TS-CHDEC-DATA TS-FE-ERR
TS-CHDEC-CLK TS-CHDEC-VALID TS-CHDEC-SOP
TS-CHDEC-CLK
3S24
470R
TS-CHDEC-VALID
RES 3S28
470R
TS-CHDEC-SOP
RES 3S29
470R
VSS
DVBS / T2 / LATAM * DVBS * / T2 / LATAM
100n
7S02 5
33R
+3V3
0 1 2 3 MDO 4 5 6 7
36
CA-ADDENn
VIDEO_STREAM
0 1 2 3 MDI 4 5 6 7
13
P21 P22 P23 P24 P25 P26 N21 N22
10K
7 3S01-2 2 3 33R 33R 5 3S02-4 4 7 3S02-2 2 33R 33R 8 3S02-1 1 6 3 33R 3S02-3 33R 5 3S01-4 4 33R
3S0G
1
+3V3
3S01-1 8 33R 3S01-3 6
CA-MDI0 CA-MDI1 CA-MDI2 CA-MDI3 CA-MDI4 CA-MDI5 CA-MDI6 CA-MDI7
7S0A H27U4G8F2D
12
7S00-11 PNX85500
10K
Non CI *3S1X
+3V3
100n 2S0B
2S0A
IS00
3S04 2S09
10-3-14
Q552.4E LA
1 4 2 3
74LVC1G08GW
PNX 85500 Nandflash conditional access
3139 123 6533
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3
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2
2011-05-25
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Circuit Diagrams and PWB Layouts
10.
EN 107
PNX 85500: Common interface
PNX 85500: Common interface +3V3
TRANSPORT STREAM FROM CAM
+5VCA 2F01
22u 16V
+T
7F00 74LVC245A 1
0R3
19 3F02
CA-MOCLK CA-MOVAL CA-MOSTRT
100R 3F03-2 2
1
3F03-1
8 100R
7
CA-CD1n CA-CD2n
3EN1 3EN2 G3
CA-DATAENn 1
2
3 4 5 6 7 8 9
100R
RES
100n
2
18
MOCLK
17 16 15 14 13 12 11
MOVAL MOSTRT
CA-DATADIR
CA-ADDENn MOCLK MOVAL
10
MOSTRT
19
2
CA-MDO0
3F04-1 1
8 100R
IF05
3F04-3 3 3F05-1 1 3F05-3 3
3F04-2 6 100R 3F04-4 8 100R 3F05-2 6 100R 3F05-4
MDO4
2
1
IF06 CA-MDO1 CA-MDO2 CA-MDO3 CA-MDO4 CA-MDO5 CA-MDO6 CA-MDO7
MDO3
2
7 100R
4
5 100R
2
7 100R
4
5 100R
2
3 4 5 6 7 8 9
18
MDO0 MDO5
17 16 15 14 13 12 11
MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7
MDO6 MDO7
10
CA-WAITn +3V3
CA-INPACKn 2F03
15-BIT ADDRESS 3EN1 3EN2 G3 18
XIO-A01 XIO-A02 XIO-A03 XIO-A04 XIO-A05 XIO-A06 XIO-A07
17 16 15 14 13 12 11
1 2
CA-VS1n
1 19
CA-ADDENn
2
CA-A00
3 4 5 6 7 8 9
CA-A01 CA-A02 CA-A03 CA-A04 CA-A05 CA-A06 CA-A07
10
XIO-A00
CA-WP
100n
20
7F02 74LVC245A
RES
XIO-A09 XIO-A10 XIO-A11 XIO-A12 XIO-A13 XIO-A14
17 16 15 14 13 12 11
20 1 2
1 19
CA-ADDENn
2
CA-A08
3 4 5 6 7 8 9
CA-A09 CA-A10 CA-A11 CA-A12 CA-A13 CA-A14
10
18
RES
100n
3EN1 3EN2 G3 XIO-A08
+3V3 2F05
8-BIT DATA 3EN1 3EN2 G3 18
XIO-D01 XIO-D02 XIO-D03 XIO-D04 XIO-D05 XIO-D06 XIO-D07
17 16 15 14 13 12 11
1 2
1
CA-DATADIR
19
CA-DATAENn
2
CA-D00
3 4 5 6 7 8 9
CA-D01 CA-D02 CA-D03 CA-D04 CA-D05 CA-D06 CA-D07
10
XIO-D00
RES
100n
20
7F04 74LVC245A
+3V3 2F06
CONTROL
1X06 REF EMC HOLE
1X05 REF EMC HOLE
3EN1 3EN2 G3
1X04 EMC HOLE XIO-D11
18
XIO-D09 XIO-D08 XIO-OEn XIO-WEn XIO-D14 XIO-D15 CA-WAITn
17 16 15 14 13 12 11
1 2
1 19
CA-ADDENn
2
CA-REGn
3 4 5 6 7 8 9
CA-CE1n CA-CE2n CA-OEn CA-WEn CA-IORDn CA-IOWRn XIO-D10
8 10K 7 10K 3 3F10-3 6 10K 3F10-4 4 5 10K 2
3F10-2
3F12 10K 7 10K 3F11-3 3 6 10K 3F11-4 4 5 10K 3F11-1 8 1 10K 2
+3V3
+3V3
3F11-2
IF08
+5VCA
+3V3
1P00
CA-MIVAL CA-MICLK CA-A12 CA-A07 CA-A06 CA-A05 CA-A04 CA-A03 CA-A02 CA-A01 CA-A00 CA-D00 CA-D01 CA-D02 CA-WP
CA-CD1n MDO3 MDO4 MDO5 MDO6 MDO7 CA-CE2n CA-VS1n CA-IORDn CA-IOWRn CA-MISTRT CA-MDI0 CA-MDI1 CA-MDI2 CA-MDI3 +5VCA CA-MDI4 CA-MDI5 CA-MDI6 CA-MDI7 MOCLK CA-RST CA-WAITn CA-INPACKn CA-REGn MOVAL MOSTRT MDO0 MDO1 MDO2 CA-CD2n 71 72
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
MPC-20-5V-PBT-BRF-V0
PNX 85500 Common interface
10
1X02 REF EMC HOLE
100n
20
7F05 74LVC245A
IF04
3F10-1
+5VCA 2F04
1X01 REF EMC HOLE
1
3F09-2
CA-D03 CA-D04 CA-D05 CA-D06 CA-D07 CA-CE1n CA-A10 CA-OEn CA-A11 CA-A09 CA-A08 CA-A13 CA-A14 CA-WEn CA-RDY
+3V3
7F03 74LVC245A
+3V3
3F09-1
8 10K 7 10K 3F09-3 3 6 10K 3F09-4 4 5 10K
CA-RDY
IF07
3F07-4
3F07-2
1 3F08-1 8 10K 3F08-2 2 7 10K 3F08-3 3 6 10K 4 3F08-4 5 10K 1
MDO2
3EN1 3EN2 G3
B05G 100K
5 10K 7 10K 3F07-3 3 6 10K 3F07-1 1 8 10K
MDO1 RES
100n
20
7F01 74LVC245A 1
4
2
MDO0 +3V3 2F02
3F06
CA-RST
10K
+5V
2F00
10K RES 3F14
3F01
RES 3F13
B05G
20
10-3-15
Q552.4E LA
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2011-05-25
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Circuit Diagrams and PWB Layouts
10.
EN 108
PNX 85500: Audio
PNX 85500: Audio
B05H +2V5-AUDIO
3S53-1 100R
+3V3
3S53-2
OUT BP
IN INH
1 3
IS13
COM
1u0
4S14
+2V5
2S2S
100R
4
2S34
2S2V
22K
5 IS12
10u RES
FS08
2
100R 3S53-4
7 10K
7
1u0
2S2T
AUDIO-IN1-R
2
IS1J
2 3S12-2
3S16-2
3S53-3
100n
22K
2S2W
10u
8
1u0 RES
100R
1 3S16-1 8 10K
IS1H
3S12-1
7S08 LD3985M25
2S2R
1 AUDIO-IN1-L
6 10K
2S30
22K
3S17-2
2
7 10K
100u 4V
1u0
2S41
3S34 3S35
33R 33R
ADAC(3) ADAC(4)
AD4 OSCLK AD1 SCK AD2 WS
3S36 3S37 3S38
10R 10R 10R
SCKI2SOUT I2SCLK WSI2SOUT
AE1 1 AF2 VREF_AADC 2 AE3 I2S_OUT_SD 3 AF3 AC8 VCOM_AADC 4
3S39
10R
SDI2SOUT1
1 2 3 ADAC 4 5 6
AD9 L AIN4 AC9 R
2S32
7 1u0 3S10 100R
2S2L IS1B
1u0
IS19
AD7 AE7 AF7 AD6 AE6 AF6
AE9 L AIN3 AF9 R
1u0
AF8 L AIN5 AE8 R
I2S_OUT AB9 POS VR_AADC AB8 NEG AD8
AE5
SPDIF_OUT SPDIF_IN1
1n0
DBS8
1n0 2S38
AF5
56R
10K 2S35
3S3F
3S32
IS1A
+3V3 +3V3-ARC
3S11
IS1L
2S3Q
1R0
3S6N
14
7S09-1 74LVC00APW 1
SPDIF-OUT-PNX
&
SPDIF-OPT
47R
3 2 +3V3
7
+3V3
+3V3-ARC
IS1C
6
14
+3V3-ARC 7S09-3 74LVC00APW 9
&
& 8
5 10
2S3L
180R
100n
3S6M
IS1K
2S3M
IS44 eHDMI+
100n 68R
3S25
7
+3V3
+3V3-ARC 7S09-4 74LVC00APW 12
14
SEL-HDMI-ARC
7S09-2 74LVC00APW 4
& 11
+3V3
13 7
SPDIF-OUT-PNX
14
IS1Q
3S13-2 22K
2S33
100n
2
8 10K
8
10u 2S3G
AUDIO-IN4-R
22K
3S17-1
100n 2S3H
1
1
IS1P
3S13-1
AUDIO-IN4-L
1u0
AC6 P AB6 ADACR N
AD10 L AIN2 AC10 R
1u0
7
IS1R
3 3S17-3
2S36
AUDIO AE10 AC7 L P AB7 AIN1 ADACL AF10 R N
1u0
100n
6
7S00-2 PNX85500
2S31
10K
3S13-3
3
5 10K
3S19
AUDIO-IN3-R
22K
3S17-4
5
9S06 RES
4
4
IS0R
3S13-4 AUDIO-IN3-L
4R7 2S42
3S51
IS1M
10u 2S3N
B05H
2S3F
10-3-16
Q552.4E LA
PNX 85500 Audio
3139 123 6533
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3
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2
2011-05-25
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Circuit Diagrams and PWB Layouts
10.
EN 109
PNX 85500: Headphone
PNX 85500: Headphone
B05I
+3V3-STANDBY
4 7NN2-2 PUMD12
6 5 2
RESET-AUDIO
7NN2-1 PUMD12 1
RESET-HP 3
2NN0 47p
3NN1-2
4 3NN1-4 5
2
7
22K 1
22K
3NN1-1
3NN1-3 8
6
3
22K 2NN5
22K
VO
1u0
INN6
3
2
7 4V 100u
INN8
2
3NN2-2
22n
2NN8
6NN8
1NN8
1K0
1NN2 MSJ-035-12D-B-AG-PBT-BRF 2 3 1
FNN2 7
AMP2
AMP2
33R
BYPASS
1 3NN2-1 8
GND
33R
22n
2NN2
SHUTDOWN
AMP1
2NN9
5
3NN5-1
8 4V 100u 2NN7
INN5
FNN1
33R
CDS4C12GTA 12V
5 10K
4 3NN2-4 5
CDS4C12GTA 12V
4
2
INN7
RES
3NN0-4
6
1
IN-
2NN6
6NN9
7 10K
33R 1
RES
2
1
VDD
AMPLIFIER
1NN9
3NN0-2
2
1
8 10K
5
1
1K0
1u0
3NN0-1
4
RESET-HP
2NN4
1u0
4
ADAC(4)
2NN3
3NN5-4
Φ
ADAC(3)
AMP1
3 3NN2-3 6
8
7NN1 TS489IST
100n
2NN1
47p +3V3
22K
B05I
RES 3NN6
10-3-17
Q552.4E LA
FNN7
PNX 85500 Headphone
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2011-05-25
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Circuit Diagrams and PWB Layouts 10-3-18
Q552.4E LA
10.
EN 110
PNX 85500: Video out - LVDS
B05J
PNX 85500: Video out - LVDS
B05J
7S00-7 PNX85500 PX1APX1A+
A7 B7
PX1BPX1B+
C8 B8
PX1CLKPX1CLK+
3S91 3S92
22R 22R
N A P
LVDS
N B P
C10 N CLK B10 P
A
N P
B
N P
CLK
D7 E7
PX3APX3A+
E8 D8
PX3BPX3B+
E10 N D10 P
3S95 3S96
22R 22R
PX3CLKPX3CLK+
C
N P
D9 E9
PX3CPX3C+
N D P
D
D11 N E11 P
PX3DPX3D+
PX1EPX1E+
C12 N E B12 P
E
E12 N D12 P
PX3EPX3E+
PX2APX2A+
A14 B14
N A P
A
D14 N E14 P
PX4APX4A+
PX2BPX2B+
C15 N B B15 P
B
E15 N D15 P
PX4BPX4B+
CLK
E17 N D17 P
N C P
C
D16 N E16 P
PX4CPX4C+
N D P
D
D18 N E18 P
PX4DPX4D+
E
E19 N D19 P
PX4EPX4E+
PX1CPX1C+
A9 B9
PX1DPX1D+
A11 B11
PX2CLKPX2CLK+
3S93 3S94
22R 22R
N C P
LOUT1 LOUT3
C17 N B17 CLK P LOUT2 LOUT4
PX2CPX2C+
A16 B16
PX2DPX2D+
A18 B18
PX2EPX2E+
C19 B19 N E P
3S97 3S98
22R 22R
PX4CLKPX4CLK+
PNX 85500 Video out - LVDS
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2
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Circuit Diagrams and PWB Layouts
10.
EN 111
PNX 85500: Analog video
PNX 85500: Analog video
B05K 2S87
AV1-CVBS
2S8A
47R
Y-SVHS
47R
22n
3S5B
3S59
22n
Connectivity
56R
B05K
3S05
10-3-19
Q552.4E LA
2S7J
AV1-R
2S22
56R
3S4J
22n
C-SVHS 22n
EU: SCART1
CVBS-MON-OUT1 22n
560R
3S5F
2S7K
AV1-B
56R
-
3S4L
AP:
3S08
560R
47p
2S7H
2S40
IS4V
22n
8K2
IS4W
3S09
56R
3S4K
AV1-G
2S7M
YPBPR1-SYNCIN1
10n 2S7L
56R
3S4P
AV3-Y 22n
2S7N 22n 7S00-1 PNX85500
AF15 AE15 AC15 AD15 AB14 AF14 AE14 AC14 AD14 AF16 AD16 AE16 AB18 AC18 AF4 AD24 AD25
2S15 22n
2S14
AC12 AF13
2S16 22n
CVBS_Y1 ATV_CVBS_Y3 R C3 B AV1 G CVBS_Y7 C7 SYNCIN1 Y_G1 CVBS1_OUT PR_R_C1 CVBS2_OUT PB_B1 RESREF CVBS_Y2 CURREF SYNCIN2 Y_G2 1 PR_R_C2 2 PB_B2 3 REF 4 R 5 G VGA 6 B HSYNC_IN IF_AGC RF_AGC IN VSYNC OUT P SCL VGA_EDID TUNER N SDA
22n
AB15 AC13 AD13 AE13
2S18 22n
22n
22n
56R
3S4T
AV3-PB
2S19
ANALOG_VIDEO
2S7P
AD11 AC11 AF11 AE11 AB10 AA11 AC16 AB16 AB13 AB12 AA12 AA10 AD12 AB11 AE12 AF12
FS13
IS5E
3S5S 10K
IS5D IS5F IS5G IS5H IS5J
3S75 FS15
SOC-IF-AGC
10K
10n
YPBPR1
2S75
3S4R
AP:
YPBPR1
56R
AV3-PR
EU:
BS10
AA14
AGND
3S4V
10n
100R
SOC-IF-P
680R
3S4U
2S77
2S78
3S4W
10n
100R
SOC-IF-N
2S84
56R
3S50
R-VGA
22n
2S85
56R
3S52
G-VGA 22n
2S86
3
V-SYNC-VGA
7 100R
3S5V-2 2
5 100R
3S5V-4
7 100R
8
4
100R 3S5T-3
2
3S5T-1
100R
1
H-SYNC-VGA
4
AP: VGA
3S5T-4
5
22n
3S5T-2
EU: VGA
56R
3S54
B-VGA
6
100R VGA-SCL-EDID
RES
3
3S5V-3
6
100R VGA-SDA-EDID
RES
1
3S5V-1
8
PNX 85500 Analog video
100R
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Circuit Diagrams and PWB Layouts
10.
EN 112
PNX 85500: Analogue externals A
PNX 85500: Analogue externals A
FNA2
FN71
2N88
1n0
2N91
1n0
1K0
100p
2N14
RES
5K6
10K
IN51
18K
BC847BPN(COL)
820R
10u
CVBS-MON-OUT1 18p
5N80 2N98
2u2
1 3N19
3NB1
IN59 39p
2N81
2N97
IN70 2
IN60
AV2-BLK
4p7
6 7N06-1 3 BC847BPN(COL)
4K7
3N73 39K
1u0
2N99
5
IN96
1
100n
2N74
100p
2N12
1N19
150p
3N18
7N06-2
FN81 CDS4C12GTA 12V
18R
2NB3
IN61
4
+5V
RES 6N28
1u8
2N86
2N85
AV1-R
3N79
3N06
1K0
3NA1
IN89 IN13
18R 5N76
+3V3
FN85
3N78
FNA6
3N17
1R0
3NA2
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
330R
150p
RES
1N18
18R
FN80
RES 6N26
1u8
2N84
150p
2N83
3N77
100p
RES 6N22
4K7
3N32 3N76 18R
2N18
FN75
12K
5N74
100p
FN74
3N31
1N55
AV1-STATUS
FNA5
2N15
FN73 IN18
IN90
3NB3
RES
1VA1 49045-0011 25 26 1N12
150p
2N80
150p
2N79
18R
CDS4C12GTA 12V
3N75
* EU
100n
FNA1
1u8
CDS4C12GTA 12V
5N73
RES 6N23
FNA4
IN05
2NB1
3N74 18R
AV2-STATUS +5V
9N01
6N09 RES
100p
2N04
FNA3
AV1-G
1N31
3N03
AUDIO-IN1-L
AV1-B
1N54
RES 6N03
100p
2N06
1K0
CDS4C12GTA 12V
3N02
CDS4C12GTA 12V
AUDIO-IN1-R
B05L
CDS4C12GTA 12V
B05L
150p
3NB6-1 IN91 8 470R
3NB6-2
7
6
CVBS-OUT-SC1
4
470R
3NB6-4
100n
2N24
3N44
3NB6-3
3N45 68R
5
470R 3
IN92
7N05 BC847BW 470R
2
+3V3
4K7
RES 3N48 3
68R 3N42
100p
*
RES 2N75
RES 5N77
FNA8
3N62 FN84
CVBS-OUT-SC1
1N25
27R 150p
RES 6N32
2N45
1u8
2N44
AV1-CVBS
1N22
4K7
CDS4C12GTA 12V
FN82
CDS4C12GTA 12V
1
3N43
7N03 BC847BW 2
6N29
FNA7
75R
AV1-BLK
150p
100p
RES 2N76
1N23
12V
CDS4C12GTA
FN83 RES 6N30
10-3-20
Q552.4E LA
DEBUG PNX 85500 Analogue externals A
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Circuit Diagrams and PWB Layouts
10.
EN 113
PNX 85500: Analogue externals B
PNX 85500: Analogue externals B
YPBPR 5 4 3
FN51 CDS4C12GTA 12V
RES 6N51
FN42
MSJ-035-75C-G-RF-PBT-BRF
3N89
100p 1N28
2 1
2N67
1VA8
FN5B
FN5A
18R
CDS4C12GTA 12V
RES 6N40
3N87
100p 1N43
B05M
AV3-PR
AV3-PB
18R
FN54
2N27
FN5C
18R
CDS4C12GTA 12V
RES 6N52
3N90
100p 1N39
2N68
FN48
AV3-Y YPBPR1-SYNCIN1
CVBS & AUDIO 5 4 3 CDS4C12GTA 12V
VGA ( OR DVI ) AUDIO
2N71
CDS4C12GTA 12V
100p 100p
IN10
100p
IN09 AUDIO-IN4-L
100p
1K0 2N35
CDS4C12GTA 12V
3N21
RES 6N19
V_NOM
1n0 1N37
2N36
FN02
AUDIO-IN4-R
1K0 2N38
CDS4C12GTA 12V
RES 6N20
2N37
MSJ-035-75C-BL-RF-PBT-BRF
V_NOM
3N20
2 1
AUDIO-IN3-L
1K0
FN01
1n0 1N38
5 4 3
FN5G
3N96
RES 6N38
1n0 1N42
2N40
FN49
AUDIO-IN3-R
1K0 2N72
RES 6N06
FN43
MSJ-035-75C-Y-RF-PBT-BRF
1n0 1N29
2 1
FN03
1N10 3150-831-030-H1 2 VCC
FN55
1
SPDIF-OPT
CDS4C12GTA 12V
RES 6N53
V_NOM
3
100p 1N80
GND MT 5 4
FN5H
100n
VIN
1R0
+3V3
RES 2N77
1N09
FN5D
3N97 FN50 2N39
1VA4
3N9C
B05M
2N73
10-3-21
Q552.4E LA
PNX 85500 Analogue externals B
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Circuit Diagrams and PWB Layouts
10.
EN 114
PNX 85500: VGA
PNX 85500: VGA
B05N
FFC1 CDS4C12GTA 12V
RES 6FC1
1FC1
100p
RES 2FC1
3FC5
CDS4C12GTA 12V
RES 6FC2
1FC2
100p
G-VGA
18R
1FC3
RES 6FC3
FFC4
100p
RES 2FC3
FFC3
CDS4C12GTA 12V
3FC7
9FC5
H-SYNC-VGA
9FC6
V-SYNC-VGA
4K7
3FC3
CDS4C12GTA 12V
RES 6FC4
1FC4
FFC6 MDS-15P-V-11-B-8.2-U4-ZN-PBT-BRF
B-VGA
18R
FFC5
47p
CDS4C12GTA 12V
RES 6FC6
47p
2FC6
10K
FFC9
RES 6FC7
47p
2FC7
10K
CDS4C12GTA 12V
RES 3FC2
4K7
3FC4
CDS4C12GTA 12V
RES 6FC5
1FC5
FFC8
9FC1
VGA-SDA-EDID-HDMI
9FC2 RES
VGA-SDA-EDID
9FC3
VGA-SCL-EDID-HDMI
9FC4 RES
VGA-SCL-EDID
1FC6
+5V-VGA CDS4C12GTA 12V
RES 3FC1
47p
2FC5
FFC7
RES 6FC8
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
2FC4
VGA CONNECTOR
3FC6
RES 2FC2
1N05
R-VGA
18R
FFC2
47p
B05N
2FC8
10-3-22
Q552.4E LA
PNX 85500 VGA
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Circuit Diagrams and PWB Layouts
10.
EN 115
PNX 85500: Temperature sensor
PNX 85500: Temperature sensor
B05O
47R
2
SCL
A2
1K0
3USG
9USB RES
9USA RES
IUSB
6
IUSC
5
1K0
3USC
A1
IUSA
9USC RES
SCL-SSB-550
SDA
7
1K0 3USF
1
A0
3USD
47R
GND
3USB
4
SDA-SSB-550
OS
+VS
7USA LM75BDP 3
100n
8
2USA
1K0 LTST-C190KGKT
RES
RES 3USA
+3V3
6USA
B05O
For DEV Use Only
10-3-23
Q552.4E LA
PNX 85500 Temperature sensor
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Circuit Diagrams and PWB Layouts
10.
EN 116
PNX 85500: Vdisp-switch
PNX 85500: Vdisp-switch
B05P
*8 *7 *6 *5 *8 *7 *6 *5
3
IUU0
7UU2-1 PUMD12 1
10K
1 IUU2
220n 3UU3-1
8
22u
47K RES 3
1
IUU4 3UU3-3 IUU5 3UU3-4 4 5 6 3 47K RES
2
FUU1
VDISP-SWITCH
LTST-C190KGKT
IUU3 7UU3 RES BC847BW
22K
2
IUU1
RES 2UU5
1u0
RES 3UU9
*
+3V3-STANDBY
47R 3UU6 47K
6 3UU5
3UU1
2K2
FOR DEVELOPMENT USE ONLY
3UU2
+3V3
47K RES
RES 100n
5
1n0
2
47K 2UU1
6UU1
3UU4
2UU0
4 PUMD12 7UU2-2
3
7
RES 2UU4
RES 2UU3
4 RES 3UU3-2
+VDISP T 2.0A 63V
22n
+12VD
FUU2
1UU0
6 5 2 1
2UU2
RES 7UU1 SI3441BDV
47R
7UU0 SI4835DDY
FUU0
RES 3UU8
1 9UU0-1 RES 2 9UU0-2 RES 3 9UU0-3 RES 4 9UU0-4 RES 1 9UU1-1 RES 2 9UU1-2 RES 3 9UU1-3 RES 4 9UU1-4 RES
47K
B05P
3UU7
10-3-24
Q552.4E LA
+3V3
4K7 RES
9UU2
LCD-PWR-ONn LCD-PWR-ON-FPGAn DONE-LX25
*
9UU3
3
3 RES 7UU4 PDTC114EU
1
RES 7UU5 PDTC114EU
1 2
2
4
PNX 85500 Vdisp-switch
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Circuit Diagrams and PWB Layouts 10-3-25
Q552.4E LA
10.
EN 117
Class-D amplifier
Class-D amplifier
B06A
B06A 7D80 SI2304
FD34 +3V3-AUDIO
+3V3-STANDBY
3D83
6D61
2D39
1K0
PDZ2.7B(COL)
1n0
30R
5D51
3D80
*
+3V3 30R SPEAKER-R-
31
3D81
10K
100u 16V
10n
2D78
220n
220n 2D71
RES 2D56
10n 2D70
2D98
10n
1 2 3
SUB-
FD95
1D51
1D50
2041145-3 1D52
10n
RES 2D76
30R
10n 5D81
RES 2D73
3 RES 5D72 4 30R 2041145-4
SPEAKER-R-
1D02 SUB+
2D87
30R
10n
RES 2D99 5D01
10u
1 RES 5D78 30R 2
SPEAKER-R+ 1D56
NC
VR_DIG
5D76
1D55
VR_ANA
5 7 40 41 44 45
FD33
1D01
10n
330p
PVDD_CD
2D5D
18R
3D73 ID92 18R
2D75
3D74 ID93
330p
2D94
34 35
27 DVDD
SSTIMER
VREG
VIA
30
50 51 52 53 54 55 56 57 58 59
30R
1D53
100n
ID80
18
FD32
5D71
PBTL
STEST
Left+ FD30 LeftRight+ Right-
FD31
1D54
ID79
1u0
SPEAKER-LSPEAKER-R+
VIA
60 61 62 63 64 65 66 67 68 69
ID53
5D79
RES 5D80 SPEAKER-R-
10u
30R
CD00
GND-PLL
30R
2D77
10u 100n
30R
10n 5D83
2D72 2D74
2D67
10u
RES 2D91
7D61 PDTC144EU
AUDIO-MUTE-UP
ID75
18K2 1%
SPEAKER-L-
10n
12
32
ID84 3D71
RES 5D75
2D81
26
16
5D74
220n
6
36
FD92
SPEAKER-L+
220n 2D55
ID70
GVDD_OUT
ID52
220n 2D83
2n2
OSC_RES
P PLL_FLT M
33n 33n
RES 2D89
2D54
ID61
8
OUT_D
42 33
18R
9D51
PDN
2D82 2D85
39
3D75
11 10
BST_C BST_D
ID62 ID63
ID51
46
ID94
47n 470R
ID66 4n7 470R ID69 47n 4n7
10K
1n0
3D82
7D50-1 PUMH2
DETECT2
2D50 3D51 2D52 2D53
30R
330p
ID65 2D51 3D52
RESET
33n 33n
2D95
+3V3D
5D00
10u
18R
19
OUT_C A_SEL
2D79 2D80
3D72
25
5D70
ID95
ID56
D-RESET
OUT_B
SDA SCL
ID81 ID82
330p
14
4 43
2D88
15K 15K
GND_HS
23 24
ID50
1
49
RES 3D76 3D77
+3V3D
47R 47R
BST_A BST_B
SDIN
37 38 PGND_CD
3D55 3D56
SDA-SSB-550 SCL-SSB-550
*
SPEAKER-L+
MCLK
47 48 PGND_AB
ID87
22
GND
15
DVSSO
FD66
FD50
SDI2SOUT1
29
7D50-2 PUMH2
BAT54 COL
6D60
47K
3D54
D-RESET
*
7D60 TAS5731PHP
OUT_A
17
SCKI2SOUT +3V3-STANDBY
SCLK
DVSS
RES 9D54
LRCLK
AVSS
10K
3D50
21
AGND
20 9D52 9D53
I2SCLK
9
FD67
WSI2SOUT RESET-AUDIO
AVDD
+3V3D
2 3
13
1R0
PVDD_AB
ID78 3D57 ID77
1R0
10K
5D85 RES 10K
2D5C
100u 16V
100n
*
3D58
28
2D5B
100u 16V
3D79
10K
*
+3V3-AUDIO 30R
+3V3D
*
2D5F
100n 2D69
SPEAKER-L-
10u 2D68
2D86
2D5A
100u 16V
3D78
10K
*
5D84 +3V3D
ID55
ID54
*
220n
2D64
47u 35V
+12V-AUDIO
30R 2D57
5D50
220n
2D60
47u 35V 2D61
+12V-AUDIO
3D84
+12V-AUDIO
5D77 30R
GND-PLL
2D57 2D60 3D83 6D61
+12V-AUDIO (5000 & 5500 series) 100uF 16V (2022 031 00538) 100uF 16V (2022 031 00538) 1K0 (3198 031 01020) BZX2V7 (3198 020 52780)
Speaker Configuration Active 2.1 (with Virtual Ground) Active 2.1 ( E-cap in speaker) Passive 2.1 2.0
*
1D02 Yes Yes Yes No
+24V-AUDIO (4500 series) 47uF 35V (2020 031 00753) 47uF 35V (2020 031 00753) 6K8 (3198 031 06820) BZX5V6 (3198 020 55680)
2D70 Yes Yes Yes No
2D87 Yes Yes Yes No
2D98 Yes Yes Yes No
2D55 Yes Yes No No
2D71 Yes Yes No No
2D83 Yes Yes No No
5D71 Yes Yes No No
5D77 Yes Yes No No
2D56 No No Yes Yes
2D73 No No Yes Yes
2D76 No No Yes Yes
2D89 No No Yes Yes
2D91 No No Yes Yes
2D99 No No Yes Yes
5D75 No No Yes Yes
5D80 No No Yes Yes
5D72 No No Yes No
5D78 No No Yes No
5D81 No Yes No No
5D83 No Yes No No
2D5A Yes No No No
2D5B Yes No No No
2D5C Yes No No No
2D5D Yes No No No
3D78 Yes No No No
3D79 Yes No No No
3D81 Yes No No No
3D81 Yes No No No
* Current Configuration
Class-D amplifier
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Circuit Diagrams and PWB Layouts
10.
EN 118
USB hub
USB hub
B06B
100n 2FLA
B06B
+3V3
+3V3
USB1 1P08
+5V-USB1
FL36 FL37
USB1-DM USB1-DP
100n
100n
2FL4
2FL1
3
25
10K
6 7 24
USB3-DM USB3-DP IFLH
USB-OVR3
IFLJ
12 13 20
IFLK
15 16 19
USB2-DM USB2-DP USB-OVR2 USB1-DM USB1-DP +3V3
10K 3FLD 3FLB 3FLC
3FLP
28 17 22 23 8
180R 1% RES 2FLF
47K
1u0 3FLM
2FLH
+3V3
IFLA 10K 100K 470R 1%
21
27 DD3DD3+ OVR3
TEST|SCL
USB-DM USB-DP
FL42
26
RES 3FLL
10K
18
RES 3FLN
10K
+3V3
30 31 32 33
FL43
+T 0R3
+5V-USB1
USB-OVR2
4
3FL4-4
5
100K 3 3FL4-3 6
6
FL33
* 100K *3 3FL8-3 6 4
+5V-USB2
USB-OVR3
3FL8-4
100K
100K
2 3F34-2 7
2 3FL4-2 7
*2 3FL8-2 7
100K 1 3F34-1 8
100K 1 3FL4-1 8
* 1 3FL8-1 8
100K
100K
3FL7
+T 0R3
+5V FL40
(WIFI)
3FLJ
RES
+T 0R3
FL38 FL39 FL30
USB-WIFI-DDn +5V-USB3
2
3
1
4 1F01 ACM2012
USB-WIFI-DDp
100K
2FLD
USB-OVR1
100K 3 3F34-3 6
*
+5V +5V
+T 0R3
*
+5V
3F32 3F34-4
2 3 4 5
USB-01-PBT-B-30-CU2-BRF
3FL2
4
FL44 FL45
FL46
VREG RESET SELFPWR GANG RREF
USB3
* *1 1P06
+5V-USB3
VIA1 VIA2 VIA3 VIA4
6
USB-16-PBT-B-30-CU1-BRF
USB3-DM USB3-DP
DD4DD4+ OVR4
100n
RESET-USBn
USB-OVR1
3FLF
10u 16V RES 2FLG
+3V3
SDA
DD2DD2+ OVR2
1 2
100K
FL31
3FLK
DD+
DD1DD1+ OVR1
100n
*
USB2-DM USB2-DP
1 2 3 4 5
29
+3V3
XOUT
FL47 FL41
100n
3 4
USB-WIFI-DDn USB-WIFI-DDp
XIN
+5V-USB2
2FLC
11
USB2 1P07
VCC_D
IFLG
5 VCC_A_1 9 VCC_A_2 14 VCC_A_3
10
GND_HS
IFL4
VCC
18p
2FL7
2FL6
12M 7FL5 CY7C65632-28LTXCT
6
100n
100n 2FL9
2FL2 100n
1u0
1u0 2FL8
1FL5
1 2 3 4 5
USB-16-PBT-B-30-CU1-BRF
2FLB
1
2FL5
FL32
18p
10-3-26
Q552.4E LA
*1 1C30 2 3 4 5 6
7
502386-0570
*
100K
*
ONLY FOR 6000
7FL5 5000 2 × USB
CY7C65634
6000 3 × USB + WIFI
CY7C65632
USB hub
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_056_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 119
Ethernet & service
Ethernet & service
B06C
B06C IN07
5N08 +3V3
+3V3-ET-ANA
6N43 IN38
IN32
2 3 1
47R
1N06
UART SERVICE CONNECTOR
MSJ-035-69A-B-RF-PBT-BRF FN58
15 10K 10K
+3V3
ETH-TXEN
21
ETH-TXD(0) ETH-TXD(1) ETH-TXD(2)
22 23 24 25 18
ETH-TXD(3) ETH-TXER
17 16
ETH-MDC ETH-MDIO
100n
10u
2N49
2N48 RX
P N
TX
P N
1
RST 0 MODE 1 RMIISEL PHYAD2 RXD
TXCLK
ETH-TXP ETH-TXN
20
ETH-TXCLK ETH-RXDV
IN63 10K
IN64
7
3N34
10K
3N72
2
14
VIA VIA
VIA
+3V3
RES 3N68 RES 3N35 RES
34 35 36
ETH-RXCLK
10K
3
CRS
+3V3
RES
3N65
10K
7N10-2 LAN8710A-EZK
ETH-RXER
3N64
REGOFF 1 LED 2 INTSEL
0 1 2 TXD 3 4 INT TXER
29 28
13
RXER RXD4 0 PHYAD 1 RXCLK
TXEN
ETH-RXP ETH-RXN
26
RXDV
COL CRS_DV MODE2
31 30
43 44 45
IO
40 41 42
VIA ETH-REGOFF
10K
37 38 39
10K
1K5
FN57
5
+3V3 ETH-INTSEL
10K
9N42
+3V3 ETH-CRS
32
RBIAS
IN39
MDC MDIO
12K1 1%
19
1A 2A VDD
3N40
10p
RES 3N71 RES 3N80
VSS
+3V3
33
3N51
FN56
8
12
6
CLKIN 1 XTAL 2
27
5 4
11 10 9 8 3N70 RES
4n7
100n 2N53
2N52 10p
2N54
10p
10K 3N33
2N55
10K 10K 10K 10K
7N10-1 LAN8710A-EZK
CR
ETH-RXD(0) ETH-RXD(1) ETH-RXD(2) ETH-RXD(3)
ETH-COL
47R 3N53-4
25M
RES 2N70
3N69 RES 10K
3N53-1
IN33
1M0 1N70 NX3225GA
RES RES RES RES
3N66 3N67 3N81 3N82
3N30
IN26
4
3
47R
+3V3
+3V3
RESET-ETHERNETn
1
2
1N85
+3V3-ET-ANA
47R 3N53-3
1N86
6
RXD1-MIPS
3N53-2
PDZ5.1B(COL)
7
TXD1-MIPS
PDZ5.1B(COL) 6N44
100n
2N62
10u 2N63
100n 2N66
30R
+3V3-ET-ANA
CONFIGURATION RESISTOR SETTINGS
ETHERNET CONNECTOR
ETH-TXP
5N0C-1 E2101
1N87 3 ACM2012 2
FN27
16 RD+
1N00 RX+ 1
1 2 3 4 5 6 7 8
FN60 4
ETH-RXP
FN29
1N88 3 ACM2012 2
ETH-RXN
FN31
4
1
15 RDTC
RX- 3
FN61 5N0C-2 E2101 11 TD+
TX+ 6
10 TCT
TXCT 7
9 TD-
TX- 8
EMPTY
9 98435-111LF
3N64 (RES)
PHYADD(0) = 1
PHYADD(0) = 0
3N65 (RES)
PHYADD(1) = 1
PHYADD(1) = 0
3N66 (RES)
PHYADD(2) = 1
PHYADD(2) = 0
3N67 (RES)
RMII mode selected
MII mode selected
3N68 (RES)
Internal 1.2V reg. disabled Internal 1.2V reg. enabled
3N69 (RES)
MODE(0) = 0
MODE(0) = 1
3N70 (RES)
MODE(1) = 0
MODE(1) = 1
3N71 (RES)
MODE(2) = 0
MODE(2) = 1
INTERRUPT FUNCTION
INTERRUPT FUNCTION
DISABLED ON
ENABLED ON
FN34 IN0B
8 7 6 5
22R
22R 3N98
+3V3-ET-ANA
3N26
8 6N47-1 1
CDA5C16GTH 16V
7 6N47-2 2
CDA5C16GTH 16V RES
6 3
CDA5C16GTH 16V RES
4
6N47-3
5 RES
CDA5C16GTH 16V RES
1 6N47-4
RES 27n
Primary FN32
3N0A-1 3N0A-2 3N0A-3 3N0A-4
22n
2N60
1 2 3 4
FN30
15p
IN0A
3N72 Secondary
nINT/TXER/TXD4 SIGNAL nINT/TXER/TXD4 SIGNAL
2N0L 1n0
RES 15p RES 0 ohm RES 2N59
5N04 2N09 15p 3N39
RES 27n RES 15p 0 ohm
RES 2N58
RES
5N03 2N08 15p
3N29
5N02
RES 27n
2N07
RES 0 ohm RES 15p RES 2N57
15p
3N28
5N01
RES 27n
2N05 3N27
RXCT 2
14 RD-
75R 75R 75R 75R
FN28
ETH-TXN
POP
49R9 1%
3N99
49R9 1%
3N95
49R9 1%
3N25
49R9 1%
3N22
Resistor
RES 0 ohm RES 15p RES 2N56
10-3-27
Q552.4E LA
ETH-INTSEL ETH-REGOFF
FN33
Ethernet & service
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_057_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 120
HDMI
HDMI
B06D
AIN-5V
1u0
67 68
BRX2BRX1+
ARX1ARX1+
69 70
ARX2ARX2+
71 72
BIN-5V
47K
3NCA-2
7
10R
BRX-DDC-SDA BRX-DDC-SCL
6 100K 1u0
IN43
35 36 33 34
BRXCBRXC+
BIN-5V
BRX-HOTPLUG
1
20 22
47K
FNC8 FNCF
3NCA-1
8
BRX-DDC-SCL BRX-DDC-SDA
BIN-5V
HDMI CONNECTOR 1
2 3NCN-2 2NCP
3 3NCM-3 6
CIN-5V
10R
CRX1CRX0+
CIN-5V
100R
+3V3-STANDBY
4
DIN-5V
3NCM-4
9NC0
BRX2BRX2+
7 8
7 100K 1u0
IN44
CRXCCRXC+ CRX0CRX0+
13 14
CRX1CRX1+
15 16
CRX2CRX2+
17 18
8 100K 1u0
IN45
2
INC6 CEC-HDMI 4
DDCA-SCL
3NCU-2 10K 3NCU-4
7
45 46 43 44
10p
2NCC
30R
ARC-eHDMI+
2
41 42
11 12
5NC2
DDCA-SDA 1 INC5
5
eHDMI+
CIN-5V
INC4
1 3NCN-1 2NCQ
10R
22K RES
7NC0 BC847BW
3NCD
47K
3NCA-4
3N23 RES 7N02 BC847BW
5 6
DRX-DDC-SDA DRX-DDC-SCL
47K
CRX-HOTPLUG
20 22
PCEC-HDMI
3NCA-3
CIN-5V
3
FNCM FNCN
BRX1BRX1+
DRX-HOTPLUG
CRX-DDC-SCL CRX-DDC-SDA 6
FNCK FNCL
5
CRXCPCEC-HDMI ARC-eHDMI+ CRX-DDC-SCL CRX-DDC-SDA
4
CRX0CRXC+
FNCA
3 4
39 40
CRX2CRX1+
FNCJ
BRX0BRX0+
CRX-DDC-SDA CRX-DDC-SCL
CRX2+
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 23
1 2
CRX-HOTPLUG
1P02
10K
1u0
3NCH
2NC2
+3V3
5
DRXCDRXC+
19 20
DRX0DRX0+
21 22
DRX1DRX1+
23 24
DRX2DRX2+
25 26
100n
2NC3
CEC_D
100n
10K RES 2NCZ
6 3
1
49
10K 3NCP-3
3NCP-1
8
DSCL4 DSDA4
N R0X0 P
10u
RES 2NCW 38
37
R4PWR5V
N R0XC P
48 47
VGA-SCL-EDID-HDMI VGA-SDA-EDID-HDMI
51
9NC2
CEC-HDMI
RES
N R0X1 P N R0X2 P (CBUS) HPD1 R1PWR5V DSDA1 DSCL1
TX2
N P
TX1
N P
TX0
N R1XC P
TXC
N R1X0 P
N P N P
57 56
HDMIA-RX2HDMIA-RX2+
59 58
HDMIA-RX1HDMIA-RX1+
61 60
HDMIA-RX0HDMIA-RX0+
63 62
HDMIA-RXCHDMIA-RXC+ 3NCJ RES
N R1X1 P
TPWR_CI2CA
N R1X2 P
CEC_A
4K7
55
3NCK
MICOM-VCC33
4K7
(CBUS) HPD2 R2PWR5V
INT
50
52
FNCR
9NC3 RES
FNCY
PCEC-HDMI 3NCL RES
+3V3
4K7
DSDA2 DSCL2 N R2XC P
CSCL CSDA
N R2X0 P RSVDL
N R2X1 P
54 53
10 28
N R2X2 P (CBUS) HPD3 R3PWR5V DSDA3 DSCL3 N R3XC P VIA
N R3X0 P N R3X1 P N R3X2 P
3NC3 3NC5
47R 47R
SCL-SSB-550 SDA-SSB-550
74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89
10K 73
EPAD INC7
IN11
FNCZ
100K
2NCU 1u0
DRX2DRX1+ DIN-5V
DRX1DRX0+ DRX0DRXC+
8
BAT54 COL
DRX2+
DRXCPCEC-HDMI FNC9 FNCH FNCQ FNCU
DRX-DDC-SCL DRX-DDC-SDA
47K
+5V-VGA
+5V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FNCV 21 23
3NCT-1
6NC1
3NCF
FNCW
1P05 +3V3-STANDBY
1
22K
HDMI CONNECTOR SIDE 3NCR
FNCP
3NCM-2
3 3NCN-3 2NCN
DSDA0 DSCL0
+5V-EDID
7
BRXCPCEC-HDMI
2
BIN-5V
2
BRX0BRXC+
(CBUS) HPD0 R0PWR5V
10p
BRX2+
ARX0ARX0+
AIN-5V
BRX-DDC-SCL BRX-DDC-SDA
+3V3
30R
10p RES 2NCY
29 30
ARX-DDC-SDA ARX-DDC-SCL
1
31 32
BRX-HOTPLUG
FNCC FNCD
5NC3 RES
RES 2NCX
IN42
SBVCC33
8
10R
5 100K 1u0
MICOM_VCC33
1
AIN-5V
4 3NCN-4 2NCM
65 66
BRX1BRX0+
100n VCC33
3NCM-1
ARXCARXC+
HDMI CONNECTOR 2
9 27 64
7NC1 SII9287B ARX-HOTPLUG
8 ARX-HOTPLUG
100n 2NC8
100n 2NC7
2NC6
Reserved
47266-9002
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FNCG 21 23
10u
FNCB
INC8
47K
3NC1-1
AIN-5V
20 22
1P03
SII9187B = 0xB2
GND
ARX-DDC-SCL ARX-DDC-SDA
FNC4 FNC5
1
100n
VOUT
30R
2NCV
2NC4
EN EN
+3V3
2K2
3NC7
3 47K
3NC1-3 6
ARXCPCEC-HDMI ARX-DDC-SCL ARX-DDC-SDA
4
3
+3V3-HDMI
ARX0ARXC+
FNC1 FNC2
FNCT
FLG
MICOM-VCC33
2
ARX1ARX0+
3K3
RES 3NC6
ARX2ARX1+
6NC2
ARX2+
PDZ2.4B(COL)
1P04
VIN
FNC3
FNC0 2NC0
5
5NC0
100u 16V
FNCS
HDMI CONNECTOR 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FNC6 21 23
I2C Address
7NC2 RT9715EGB
RES 2NC1
+5V
30R
5NC4
+3V3
4R7
B06D
3NCG
10-3-28
Q552.4E LA
DRX-DDC-SCL DRX-DDC-SDA
2 3NCT-2 7
DIN-5V
47K DIN-5V
DRX-HOTPLUG
20 22
HDMI
+5V-EDID
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_058_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 121
FPGA, power & control
FPGA, power & control
B07A
B07A
5J20 +3V3
FJ21
30R
1
3J21
DBG
+3V3
470R
7J25 PDTC144EU 2 DBG
220n
2u2 2J27
DBG
LTST-C190KGKT
RES
2u2 2J26
2u2 2J25
2u2 2J24
2u2 2J23
2J22
2u2
RES 2J21
6J21
3
VAUX DONE
7J20 LD1117DT12 MISO
FJ22
2
VCCINT
+3V3 FJ26
2J2K
RES 4K7
5J21
FJ23
1 2 3 4 5 6
220n
220n 2J41
220n 2J40
2u2 2J39
1J22
VCCO3
RES
2u2 2J38
30R 2J37
+3V3
CCLK CSO-B MOSI MISO PROG-B 7
MOSI CCLK CSO-B
7J21 M25P40-VMN6
*
8
3J23
220n
220n 2J36
2u2 2J35
2u2 2J34
2u2 2J33
2J32
22u
22u 2J31
2J30
10u
2J29
1
2J28
COM
VCC
FJ27
5
FJ28 FJ29
IJ22 Q
2
C
1
S HOLD
3
8
Φ
D
6
100n
OUT
10R
IN
3J24
3
+3V3 100n
7
W
502382-0670
GND 4
5J22
FJ20
+3V3
VCCO2
220n
220n 2J46
220n 2J45
2u2 2J44
PROGRAMMING ENGINEERING
FJ30
6SLX4-4MB-M25P40 6SLX9-4MB-M25P40
RES
2u2 2J43
2J42
30R
+3V3 FJ24 4
VCCO1
FPGA-LED0 3J25
3
47R
FPGA-LED2
18p
18p
8 330R 1
DBG 3J26-1 DBG 6J25
LTST-C190KGKT
DBG 3J26-2
7 330R 2 LTST-C190KGKT
DBG 6J24
DBG 3J26-3
6 330R 3 LTST-C190KGKT
DBG FPGA-SYS-CLK
PNX-SPI-CLK
RES 4
9J21-4
5
PNX-SPI-SDO
RES 3
9J21-3
6
AMBI-SPI-OUT-MOSI
PNX-SPI-SDI
RES 2
9J21-2
7
AMBI-SPI-OUT-MISO
PNX-SPI-CS-BLn
RES 1
9J21-1
8
AMBI-SPI-OUT-CSn
AMBI-SPI-OUT-CCLK
1n0
PROG-B
2J2N
2
2J2P
12M
2J51
6J22
1
47R 1K0
3J29
1M0
10K
3J31
3 GND
RES
47R
1J21
VCC RESET
3J27
1
2J50
7J26 NCP803
4
3J28
3J30
+3V3
RES
1 NC
3
1
NC
5
5 1
+3V3 7J24 74LVC1GU04GW 2 4
3
220n
220n 2J2H
220n 2J2G
2u2 2J2F
RES
2u2 2J2D
2J2C
+3V3 7J23 74LVC1GU04GW 2
DBG
VCCO0
30R
5 330R 4
FPGA-LED3 DBG 3J26-4
FJ25
FPGA-LED1
2
2J2M
5J24
100n
VALUE
+3V3
FPGA-SYS-CLK
6J23
220n
220n 2J2B
220n 2J2A
2u2 2J49
7J22 3225
1
RES
2u2 2J48
2J47
30R
LTST-C190KGKT
5J23 +3V3
100n
10-3-29
Q552.4E LA
FPGA, power & control
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_059_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 122
FPGA, I/O banks
FPGA, I/O banks
B07B 7J01-1 XC6SLX4-2TQG144C0100
7J01-6 XC6SLX4-2TQG144C0100
BANK0
VCCO0
122 125 135
VCCO1
76 86 103
VCCO2
42 63
VCCO3
4 18 31
GND
VCCINT
19 28 52 89 128
VCCINT
VAUX
20 36 53 90 129
144 143 142 141 140 139 138 137 134 133 132 131
VCCAUX
RES 9J02
PWR_GND
3 13 25 49 54 68 77 91 96 108 113 130 136
IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0
IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0
127 126 124 123 121 120 119 118 117 116 115 114 112 111
7J01-2 XC6SLX4-2TQG144C0100
BANK1 105 104 102 101 100 99 98 97 95 94 93 92
IO_L1P_1 IO_L42P_GCLK7_1 IO_L1N_VREF_1 IO_L42N_GCLK6_TRDY1_1 IO_L32P_1 IO_L43P_GCLK5_1 IO_L32N_1 IO_L43N_GCLK4_1 IO_L33P_1 IO_L45P_1 IO_L33N_1 IO_L45N_1 IO_L34P_1 IO_L46P_1 IO_L34N_1 IO_L46N_1 IO_L40P_GCLK11_1 IO_L47P_1 IO_L40N_GCLK10_1 IO_L47N_1 IO_L41P_GCLK9_IRDY1_1 IO_L74P_AWAKE_1 IO_L41N_GCLK8_1 IO_L74N_DOUT_BUSY_1
88 87 85 84 83 82 81 80 79 78 75 74
7J01-3 XC6SLX4-2TQG144C0100
BANK2 DONE CCLK
3J02 IJ01
10R
PNX-SPI-CLK PNX-SPI-SDO MISO MOSI PNX-SPI-SDI PNX-SPI-CS-BLn
3J09
10R
9J01 FPGA-LED3 FPGA-LED2
CMPCS_B_2 IO_L30P_GCLK1_D13_2 DONE_2 IO_L30N_GCLK0_USERCCLK_2 IO_L1P_CCLK_2 IO_L31P_GCLK31_D14_2 IO_L1N_M0_CMPMISO_2 IO_L31N_GCLK30_D15_2 IO_L2P_CMPCLK_2 IO_L48P_D7_2 IO_L2N_CMPMOSI_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L49N_D4_2 IO_L12P_D1_MISO2_2 IO_L62P_D5_2 IO_L12N_D2_MISO3_2 IO_L62N_D6_2 IO_L13P_M1_2 IO_L64P_D8_2 IO_L13N_D10_2 IO_L64N_D9_2 IO_L14P_D11_2 IO_L65P_INIT_B_2 IO_L14N_D12_2 IO_L65N_CSO_B_2 PROGRAM_B_2
FPGA-SYS-CLK
IJ02 2J01
100n RES
3J03 3J04
10R 10R
3J05
10R
3D-LR-DISP 3D-LED 3D-VS 3D-LR SCL-SSB-550 SDA-SSB-550 CSO-B PROG-B
BANK3
AMBI-SPI-OUT-CSn AMBI-SPI-OUT-MISO
10p
FPGA-LED1 FPGA-LED0
7J01-4 XC6SLX4-2TQG144C0100
35 34 33 32 33R 30 33R 29 27 26 24 23 22 21
3J0A 3J00
AMBI-SPI-OUT-MOSI AMBI-SPI-OUT-CCLK
2J04
56 55 51 50 48 47 46 45 44 43 41 40 39 38 37
FJ07
10K
10K
3J0C
VAUX
3J0G
IO_L43P_GCLK23_3 IO_L1P_3 IO_L1N_VREF_3 IO_L43N_GCLK22_IRDY2_3 IO_L44P_GCLK21_3 IO_L2P_3 IO_L44N_GCLK20_3 IO_L2N_3 IO_L49P_3 IO_L36P_3 IO_L36N_3 IO_L49N_3 IO_L50P_3 IO_L37P_3 IO_L50N_3 IO_L37N_3 IO_L51P_3 IO_L41P_GCLK27_3 IO_L51N_3 IO_L41N_GCLK26_3 IO_L52P_3 IO_L42P_GCLK25_TRDY2_3 IO_L52N_3 IO_L42N_GCLK24_3 IO_L83P_3 IO_L83N_VREF_3
17 16 15 14 12 11 10 9 8 7 6 5 2 1
BL-DIM1 BL-DIM2 BL-DIM3 BL-DIM4 BL-DIM5 BL-DIM6 BL-DIM7 BL-DIM8 BL-DIM
10K
10K
3J06
3J07
VAUX
7J01-5 XC6SLX4-2TQG144C0100
MISC 109 110 107 106
DBG 1J02
7
FJ02 FJ03 FJ04 FJ05
73
FJ06
8
100n DBG
1 2 3 4 5 6
2J02
1K0
DONE
72 71 70 69 67 66 65 64 62 61 60 59 58 57
FJ01
10p
VCCO2
3J01
2J03
B07B
VCCO_3 VCCO_2 VCCO_1 VCCO_0
10-3-30
Q552.4E LA
TCK TDI TMS TDO SUSPEND
VAUX
FPGA, I/O banks
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_060_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 123
Tuner, channel decoder
B08A
Tuner, channel decoder
B08A
VCC-TUNER IFA1
3FA0
22u
22u 2FA6
2FA5 100n
1FA2 U.FL-R-SMT-1(10)
2FA8
3
5FA6
3FA2 3FA1
30R
5FA7
1n0
2FA4
1
100n
10u 2FA2
FFA7 FFA6
30R
FFA1
2FA9
5FA5 330n 10p
2FAA
10p
4
FFA4
FFA3
100R 100R
FFA2
1FA0 DBG
5
10p 2FAK 10p
AFA1
12
SCL-TUNER SDA-TUNER
330n
14
A3.3V IF1_P IF1_N AGC1 NC1 NC2 IF2_P IF2_N AGC2 I2C_SCL I2C_SDA
10p
VCC-TUNER
AFA3
10p 2FAH
2
OUT
3FA4 47R
AFA0
10p 2FAG
IN
COM 2FA1
2FA0
RES
330u 6.3V
30R
5FA4
10p 2FAC
3
+5V
FFA0
FFA8
2FAJ
9FA0
9FA1
2FAB
IFA0
5FA0
AFA4
5KC9 330n
AFA2
3FA3 47R
SOC-IF-N SOC-IF-P
1 2 3 4 5 6 7 8 9 10 11
AFA5
330n
47R 7FA0 LD1117DT33
FFA9
5KC8 3KA1
47R
TUNER
3KA0
IF-N-DVBT2 IF-P-DVBT2
16
15
1F00 SUT-RE214Z
13
1
10p
2
3
2FA7
2 1FA1 1 U.FL-R-SMT-1(10)
30R
5FA1
0R1
FFAA
1 2 3
BM03B-SRSS-TBT
3KA3
IF-AGC
41
2KCH
DKC0 IKC4 3KC7 2KCJ
+3V3-DVBT2-D
32
7 19 42
10 22 28 44
47R
1K0
IF-AGC 100n 3KC8
1 47 2
48
10K IKC5 3KC9
3K3
0 1 2 3 TSDATA 4 5 6 7
TAINP TAINM
IKC6
46 45
RFAIN
GPIO0 GPIO1 GPIO2
I2C ADDRESS = 0XD8
SCL SDA
TIFAGC
TTUSCL TTUSDA
3K3
DKC1 RESET-FUSION-OUTn
26
29
30
33 40
TESTMODE
SLVADR0
VIA
OSCEN_X
RST_X
SLVADR3
NC1 NC2 VSS
1 3KC0-1 47R
TS-CHDEC-CLK TS-CHDEC-VALID TS-CHDEC-SOP
3 3KC0-3 47R
TS-CHDEC-DATA
3KCC
22K
3FAD
22K
10p
2FAE 470R
3FAC
3FAB
470R
3FAA
VCC-TUNER
5KC5
IKC7
5KC7
VCC-TUNER 3KC2
SCL-FE SDA-FE
3KC3
47R
+3V3-DVBT2-D
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
IKC8 +1V2-DVBT2-C
+1V2-FE 30R
30R 5KC6 +3V3 30R
47R
+1V2-DVBT2-C
3KCE
IKC9 +1V2-DVBT2-P
22R
GND_HS 49
25
6 11 18 23 27 31 36 39 43
24
8 9 12 13 14 15 16 17 20 21
6p8 47R 8 2 3KC0-2 47R 6
7
1u0
10p 3KC6
4u7
TSCLK TSVALID TSSYNC
3KC1
5 4 3
2KCR
2KCG
3KCB
IFA4
RES 2KCK
PVDD
XTALO
IFA5
FKC1
Position Nr
FUSION
3FA7
-
3FA9
2K7
3FAA
470R
-
10u
47R IKC3
38 37
7FA1-2 BC857BS(COL) 4
2KCS
3KCA
TS-INT-CLK TS-INT-VALID TS-INT-SOP TS-INT-DATA
5
1u0
IKC2
10p 2KCF 100n
34
DVDD
5 8 7 6
3
IFA3 2
2KCP
100n
IKC1
CVDD XTALI
1K0
2KCD 2KCE
5KC1 T2-AGC
3KC4
35
2K7
6 7FA1-1 BC857BS(COL) 1
10K
2KC0
100n
100n
2KC1
100n 2KC2
2KC3
100n
VCC-TUNER
2KC4 100n
2KC5 100n
100n
2KC7
2KC6 100n
9KC0 9KC1
12p
2KCB
12p 1KC0
4u7 IF-P-DVBT2 IF-N-DVBT2
2 4
2KCC 5KC0
7KC0 CXD2834ER IKC0
6K8
6K8
3KA2 7KA0 PDTA114EU RES
+1V2-DVBT2-P
4 9RC2-4 1 9RC2-1 2 9RC2-2 3 9RC2-3
1
RES
FFAC
+3V3-DVBT2-D
41M 3
10p
100R
3FA9
+1V2-DVBT2-C
2FAF 3FA7
RES IFA6 T2-AGC
22n
FFA5
100R RES
SOC-IF-AGC
3FA8
3KA4
FFAB
IF-AGC
2FAD
100R
10n
10-3-31
Q552.4E LA
TV550-R4 100R
3FAB
10K
3FAC
470R
3FAD
22K
22K
2FAD
100nF
7FA1
BC857BS
22nF _
-
Tuner, channel decoder
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_061_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts 10-3-32
Q552.4E LA
10.
EN 124
DVBS, FE
DVBS, FE
B08B
B08B 7RA1-1 STV0903BAC
22u
2RAG
100n
10n
2RAF
100n
2RAE
10n
2RAD
100n
2RAC
2RAB
+1V0-DVBS
Diversity Matrix (Satellite Tuner dependant) Position Nr Affected Pin Default Value STV6110 STV6111
JUMP
2RB7
27
10U
2RBU
27
4N7
-
X
2RBV
27
68P
X -
9RB9
27
JUMP
X
-
3RB3
27
4R7
X
2K2
10n
2RAP
10n
10n
2RAN
100n
2RAM
X
+2V5-DVBS
X X
VDDA2V5
8 7
IM IP
N Q1 P
60 56
F22-DISECQ-TX NC NC
IRA0
3RA7
SCL-FE SDA-FE
47R
47R
IRA1
3RA8
SCLT SDAT
FRA0
RESET-DVBS IRA2
+3V3-DVBS
0 CS 1
128 20 126 107
DISEQCIN1 DISEQCOUT1 FSKRX_IN FSKRX_OUT NC
97 98
SCL SDA
19 18
SCLT 1 SDAT
62 58
RESETB STDBY
26 23 24 29 27
FRA1 FRA2 FRA3 FRA4 FRA5
82 83 84 86 87 89 90 91 94 95 108 109 111 115 116 119 120
TCK TDI TDO TMS TRST
101 50 49 47 46 44 43 37 35 34 32 30 55
1 2 3 4 5 6 GPIO 7 8 9 10 11 12 13
FRA6
47n
NC
47p
TS-INT-DATA TS-INT-CLK TS-INT-SOP TS-INT-VALID
NC NC NC NC NC
3RA0-3 3 3RA1 3RA0-2 2 3RA0-1 1
6 47R 7 47R 8 47R 47R
NC
NC NC NC NC NC
TS-DVBS-DATA TS-DVBS-CLK TS-DVBS-SOP TS-DVBS-VALID
NC NC NC NC NC NC NC NC NC NC NC NC
40 41
0 COMP 1
AGC 2RC9 RES
2RB0
NC
6p8
N I1 P
129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165
1K0 63 64 65 67 68 70 71 73 74 75 78 79
0 1 2 3 D 4 5 6 7 CLKOUT STROUT DPN ERROR
IRA3
3RA3 120K
NC NC NC NC NC NC NC NC NC NC NC NC NC
100n
JUMP
VDDA1V0
5 9 13 114 118 123 127 2RAW
25 25
+1V0-DVBS
X
100n
9RB6 9RB7
VDD3V3
2 3
2RAV
33N
100n
7
X
2RAL
2RBW
-
100n
27P
2RAU
4,5
100n
2RCB
-
2RAK
X
100n
27P
2RAT
4,5
100n
2RBM
100n
X
2RAR
JUMP
100n
4,5
2RAS
9RB8
X
2RAJ
-
100P
VIA
21 38 54 76 80 92 96 106
+3V3-DEMOD 2RAH
4,5
2RBY
VDD1V0
DIRCLK CLKI CLKI2 CLKOUT27
SENSE+1V0-DVBS FRA7
3RA2
16
AGCRF1
I2C-ADDRESS : D0
59 104 103 100 11 12
QM QP
52
VS
XTALO
RES 2RB1
10n
2RAA
100n
10n
2RA9
100n
2RA8
10n
2RA7
10n
2RBK
22u
2RBL
30R
100n
2RA5
+3V3RF
+3V3-DVBS
2RA6
IRA7
GND_HS
NC NC
Φ
MAIN
XTALI
124
1K0
+1V0-DVBS
GNDA
NC
3RA4
RES
1 4 6 10 14 113 117 121 125
10K
100n
10n
2RA4
100n
2RA3
10n
2RA2
100n
2RA1
22u
2RA0
22u 2RCC
22u 2RCD
RES
2RCE
22u
2RAY
30R
5RA1
Φ
POWER_VIA
2p2
15 17 22 25 28 31 33 36 39 42 45 48 51 53 57 61 66 69 72 77 81 85 88 93 99 102 105 110 112
+3V3-DEMOD
3RA6
+3V3-DVBS
122
XTAL RES 2RCA
7RA1-2 STV0903BAC +1V0-DVBS
IRA8
5RA0
+3V3RF
*
*
*
68p
10u 2RBV
4n7
2RBU
100n
100n 2RB6
1n0 2RB5
1n0 2RB4
1n0 2RB3
2RB2
IRA9
* 3RB3 4R7
2RB7
IRA4
* 9RB9
7RC1 LD1117DT33
*
16V
+2V5-DVBS IRC1
4
1u0
BP
FRC0
5
2RC2
EN
COM 10K
3RC2
100n
10K
3
OUT
1u0
+3V3-DVBS
IN
2RC1
IRC2
9RB7
27p
3RC1
SYN HS 29 33
2RC6
2RC5
100n
7RC0 RT9193-25GB
10n
10p 2RBS
10p
10p
1
IRC0
+3V3
2RC3
RF LNA LT MIX DIG BB VCO 5 3 9 10 15 17 25 26
+3V3-DVBS
10p
IP IM
2RBP
*
8 100R
GND
9RB6
100p
2RBY 2RCB
9RB8
0p56
*
7 34 35 36 37 38 39 40 41 42
QP QM
FRC1
2
2RC4
RF_IN
2 3RB1-2
5 100R
2
VIA
21 20
4 6 3RB1-4 100R 1 7 3RB1-1 100R
OUT COM
1u0
NC
3 3RB1-3
2RBR
AS
1K0
10p
RF_OUT
AGC
100p
IN
30R
XTAL
10p
I2C-ADDRESS : C6
QP QN
3RB0
1
* RES 2RBG
100p
1n0 2RBH
SM15T 2RBJ
47p 6RA0
RES 2RBT
4
SATELLITE TUNER
27p
FRA8
+V-LNB
2RBM
27n
8 9 5 10
5RA2
6 7
*
1 2 3 4
Φ
18 19
2RB8
2RC0
1R01
SCL SDA
IP IN
32
2RBN
23 24
+3V3RF
XTAL_OUT
XTAL_IN
XTAL_CMD
3
+5V
SYN
2RBB
16
VCO
2RBC
9RB0 RES
MIX DIG BB VSS
IRC3
5RC0
28
10p
2
27
10p
RES 10p
22
2RBA
12 13
14
2RB9
2RBD
1
11
33n
2RC8 AGC
31
10p
RES 10p
8
LNA LT 30
10p
2RC7 SCLT SDAT
1
6
2RBW
1RA0 16M 2RBF
2 NC 4 NX3225GA
3
10p
7RA0 STV6110AT
22u
2RBE
* * +3V3RF +3V3-DVBS
7RC2 BC847BW
DVBS, FE
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_062_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 125
Video out - LVDS
B09A
Video out - LVDS
B09A
TX1-CLKTX1-CLK+
FG1D FG2T FG1F FG1G FG1H FG11 FG1J
TX1-DTX1-D+ TX1-ETX1-E+
FG1K FG1L FG1M FG1N
TX2-ATX2-A+ TX2-BTX2-B+ TX2-CTX2-C+
FG12 FG13 FG14 FG15 FG16 FG17
TX2-CLKTX2-CLK+
FG18
TX2-DTX2-D+ TX2-ETX2-E+
FG19 FG1A FG1B FG1Q FG1P
41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
10K
47p
47p
100p
10K
47p
47p
10K
47p
47p
10p
10p
10K
47p
10K
10K
10K
10K
3G47
RES 2G7A
2G7F
RES 2G79
RES 2G7D
RES 2G26
RES 3G40
RES 2G7C
RES 3G39
RES 2G7B
2G75
2G76
RES 2G77
RES 3G38
SAMSUNG 3G35
RES 3G34
RES 3G33
*
FG2R
FG2L FG2M
TX3-ATX3-A+ TX3-BTX3-B+ TX3-CTX3-C+
FG2U FG2F FG1Y FG1Z FG20 FG21
TX3-CLKTX3-CLK+
FG22 FG23
TX3-DTX3-D+ TX3-ETX3-E+
FG24 FG25 FG26 FG27
TX4-ATX4-A+ TX4-BTX4-B+ TX4-CTX4-C+
FG28 FG29 FG2A FG2B FG2C FG2D
TX4-CLKTX4-CLK+
FG1R FG1S
TX4-DTX4-D+ TX4-ETX4-E+
FG1T FG1U FG1W FG1V
RES 2G28 RES 2G29
47p 47p
FG2P 100n
FG30 FG31 FG32 FG33
100R 68R 100R 100R 100R 100R
2G91
100n
3G37
** 3G48 3G45 3G41 * 3G42 * 3G31 RES
*
FG34 FG2H FG2G
100n
2G95
RES
CTRL-DISP3 BL-PWM 3D-LR-DISP CTRL-DISP1 CTRL-DISP2 3D-LR
*
EMC 100n RES 2G9D
FG2J
51 49 47 45 43
100R 10R 10R
RES 9G0G
FG2N
+VDISP 1X03 EMC HOLE
EMC 100n RES 2G9C
100n
50 48 46 44 42
SAMSUNG 3G32 3G2W 3G2Y
CTRL-DISP3 SDA-DISP SCL-DISP
* *
EMC 100n RES 2G9E
100n
2G94
FG1C
TO DISPLAY
EMC RES 2G9F
TX1-ATX1-A+ TX1-BTX1-B+ TX1-CTX1-C+
1G50 *20519-041E
100n
47p 47p 47p 47p
x x x x x -----
TO DISPLAY
2G93
2G96 2G99 2G97 2G98
------x x x
3G44
5 6 7 8 9G0K-4 9G0K-3 9G0K-2 9G0K-1 2G92
OTHERS 10K
3G41 3G42 3G43 3G44 3G45 3G46 3G47 3G48 2G7F
+VDISP
LGD 50HZ 3D TM100
3G43
*
RES 3G46
RESERVED FOR 100HZ PANEL
10K
+3V3
4 3 2 1
10-3-33
Q552.4E LA
Video out - LVDS
1G51 20519-051E 60 61 58 59 56 57 54 55 52 53
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
3
2011-12-29
2
2011-09-29
3139 123 6531 19220_076_120229.eps 120229
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 126
FPGA, I/O banks
FPGA, I/O banks
B10A
7K00-6 XC6SLX25-2FTG256C0100
POWER G7 G9 H10 H8 J7 J9 K10 K8
+1V2-LX25
E5 F11 F8 G10 H6 J10 L6 L9
VAUX-LX25
B13 B4 B9 D10 D7
VCCO0-LX25
D15 G13 J15 K13 N15 R13
VCCO1-LX25
VCCO2-LX25
N10 N7 R4 R8
VCCO3-LX25
D2 G4 J2 K4 N2
C4 A4
LCD-PWR-ON-FPGAn
VCCINT
GND
VCCO_0
VCCO_1
A1 A16 B11 B7 D13 D4 E9 G15 G2 G8 H12 H7 H9 J5 J8 K7 K9 L15 L2 M8 N13 P3 R10 R6 T1 T16
BANK2
BANK0
RES 9K01
VCCAUX
7K00-3 XC6SLX25-2FTG256C0100
7K00-1 XC6SLX25-2FTG256C0100
TX3-B+ TX3-B-
B5 A5
TX3-A+ TX3-A-
D5 C5
TX3-CLK+ TX3-CLK-
B6 A6
BL-DIM6 BL-DIM8
F7 E6
TX3-D+ TX3-D-
C7 A7
TX3-C+ TX3-C-
D6 C6 B8 A8
TX3-E+ TX3-ETX4-A+ TX4-A-
C9 A9
TX4-B+ TX4-B-
B10 A10
3K06
CCLK-LX25
IO_L1P_HSWAPEN_0 IO_L1N_VREF_0
IO_L36P_GCLK15_0 IO_L36N_GCLK14_0
IO_L2P_0 IO_L2N_0
IO_L37P_GCLK13_0 IO_L37N_GCLK12_0
IO_L3P_0 IO_L3N_0
IO_L38P_0 IO_L38N_VREF_0
IO_L4P_0 IO_L4N_0
IO_L39P_0 IO_L39N_0
IO_L5P_0 IO_L5N_0
IO_L40P_0 IO_L40N_0
IO_L6P_0 IO_L6N_0
IO_L62P_0 IO_L62N_VREF_0
IO_L7P_0 IO_L7N_0
IO_L63P_SCP7_0 IO_L63N_SCP6_0
IO_L33P_0 IO_L33N_0
IO_L64P_SCP5_0 IO_L64N_SCP4_0
IO_L34P_GCLK19_0 IO_L34N_GCLK18_0
IO_L65P_SCP3_0 IO_L65N_SCP2_0
IO_L35P_GCLK17_0 IO_L35N_GCLK16_0
IO_L66P_SCP1_0 IO_L66N_SCP0_0
E7 E8
10R
BL-DIM7 BL-DIM3
E10 C10
AMBI-SPI-OUT-MOSI AMBI-SPI-OUT-CCLK
D8 C8
BL-DIM4 BL-DIM5
C11 A11
TX4-C+ TX4-C-
F9 D9
BL-DIM1 BL-DIM2
B12 A12
TX4-CLK+ TX4-CLK-
C13 A13
TX4-D+ TX4-D-
F10 E11
IK00
MISO-LX25 MOSI-LX25
TX4-E+ TX4-E-
D11 D12
PNX-SPI-CLK PNX-SPI-SDO
3K12 FK08
10R
RES 3K08
FK09
PNX-SPI-CS-BLn PNX-SPI-SDI
B14 A14
M12 M11
TX1-A+ TX1-A-
FPGA-RESET-SYSn 3D-LR-DISP
R11 T11
P10 T10 N12 P12
1K0
BL-DIM
N11 P11
TX1-CLK+ TX1-CLK-
N9 P9
TX1-C+ TX1-C-
R9 T9
TX1-B+ TX1-B-
L10 M10
FPGA-SYS-CLK-LX25 CTRL-DISP3
M9 N8
9K02
RES 3K14
100R
IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2
IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2 IO_L13N_D10_2
IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2
IO_L14P_D11_2 IO_L14N_D12_2
IO_L49P_D3_2 IO_L49N_D4_2
IO_L23P_2 IO_L23N_2
IO_L62P_D5_2 IO_L62N_D6_2
IO_L16P_2 IO_L16N_VREF_2 IO_L29P_GCLK3_2 IO_L29N_GCLK2_2
IO_L64P_D8_2 IO_L64N_D9_2
TX1-D+ TX1-D-
P7 M7
TX2-B+ TX2-B-
R7 T7
TX1-E+ TX1-E-
P6 T6
FPGA-RESET-SYSn
R5 T5
TX2-CLK+ TX2-CLK-
N5 P5
TX2-D+ TX2-D-
L8 L7
TX2-A+ TX2-A-
P4 T4
TX2-E+ TX2-E-
M6 N6
TX2-C+ TX2-C-
R3 T3 T2 L11 P13
IK01 RES 2K01 3K07
100n 10R
FK07
CSO-B-LX25 PROG-B-LX25 DONE-LX25 DONE-LX25
3K05 VCCO2-LX25 1K0
FK06
VCCO_3
10K
10K
7K00-5 XC6SLX25-2FTG256C0100
3K11
3K10 FK01 FK02 FK03 FK04 FK00
JTAG
A15 E14 P14
VAUX-LX25
PX4B+ PX4B-
E13 E12
PX4D+ PX4D-
B15 B16
3D-LR
F12 G11
PX4C+ PX4C-
C12
DBG 1K01
2K02
IO_L63P_2 IO_L63N_2
P8 T8
VCCO_2
C14
100n DBG
IO_L47P_2 IO_L47N_2
PROGRAM_B_2 CMPCS_B_2 DONE_2
VAUX-LX25
8
IO_L32P_GCLK29_2 IO_L32N_GCLK28_2
IO_L65P_INIT_B_2 IO_L65N_CSO_B_2
7K00-4 XC6SLX25-2FTG256C0100
BANK1
7
IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2
IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2
7K00-2 XC6SLX25-2FTG256C0100
1 2 3 4 5 6
IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2
TCK TDI TMS TDO SUSPEND
D14 D16
PX3D+ PX3D-
F13 F14
PX4E+ PX4E-
C15 C16
PX4A+ PX4A-
E15 E16
PX3E+ PX3E-
F15 F16
PX3C+ PX3C-
G14 G16
PX3A+ PX3A-
H15 H16
3D-VS 3D-LED
G12 H11
PX3B+ PX3B-
H13 H14
IO_L1P_A25_1 IO_L1N_A24_VREF_1 IO_L29P_A23_M1A13_1 IO_L29N_A22_M1A14_1
IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1 IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L41N_GCLK8_M1CASN_1
IO_L30P_A21_M1RESET_1 IO_L42P_GCLK7_M1UDM_1 IO_L30N_A20_M1A11_1 IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L31P_A19_M1CKE_1 IO_L31N_A18_M1A12_1 IO_L32P_A17_M1A8_1 IO_L32N_A16_M1A9_1
IO_L43P_GCLK5_M1DQ4_1 IO_L43N_GCLK4_M1DQ5_1 IO_L44P_A3_M1DQ6_1 IO_L44N_A2_M1DQ7_1
IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1
IO_L45P_A1_M1LDQS_1 IO_L45N_A0_M1LDQSN_1
IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1
IO_L46P_FCS_B_M1DQ2_1 IO_L46N_FOE_B_M1DQ3_1
IO_L35P_A11_M1A7_1 IO_L35N_A10_M1A2_1
IO_L47P_FWE_B_M1DQ0_1 IO_L47N_LDC_M1DQ1_1
IO_L36P_A9_M1BA0_1 IO_L36N_A8_M1BA1_1
IO_L48P_HDC_M1DQ8_1 IO_L48N_M1DQ9_1
IO_L37P_A7_M1A0_1 IO_L37N_A6_M1A1_1 IO_L38P_A5_M1CLK_1 IO_L38N_A4_M1CLKN_1 IO_L39P_M1A3_1 IO_L39N_M1ODT_1
IO_L49P_M1DQ10_1 IO_L49N_M1DQ11_1 IO_L50P_M1UDQS_1 IO_L50N_M1UDQSN_1 IO_L51P_M1DQ12_1 IO_L51N_M1DQ13_1 IO_L52P_M1DQ14_1 IO_L52N_M1DQ15_1 IO_L53P_1 IO_L53N_VREF_1 IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1
J11 J12
PX2CLK+ PX2CLK-
J13 K14
PX4CLK+ PX4CLK-
K12 K11
PX1CLK+ PX1CLK-
J14 J16
PX3CLK+ PX3CLK-
K15 K16
PX2E+ PX2E-
N14 N16
PX1E+ PX1E-
M15 M16
PX2B+ PX2B-
L14 L16
PX2D+ PX2D-
P15 P16
PX1D+ PX1D-
R15 R16
PX1C+ PX1C-
R14 T15
PX1B+ PX1B-
T14 T13
PX1A+ PX1A-
R12 T12
3K13 3K03
47R 47R
SCL-SSB-550 SDA-SSB-550
L12 L13
PX2C+ PX2C-
M13 M14
PX2A+ PX2A-
RES 3K04
1% IK02 100R
RES 2K00
100n
BANK3 M4 M3 M5 N4 R2 R1 P2 P1 N3 N1 M2 M1 L3 L1 K2 K1 J3 J1 H2 H1 G3 G1 F2 F1 K3 J4
IO_L1P_3 IO_L1N_VREF_3
IO_L43P_GCLK23_M3RASN_3 IO_L43N_GCLK22_IRDY2_M3CASN_3
IO_L2P_3 IO_L2N_3
IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3
IO_L32P_M3DQ14_3 IO_L32N_M3DQ15_3 IO_L33P_M3DQ12_3 IO_L33N_M3DQ13_3 IO_L34P_M3UDQS_3 IO_L34N_M3UDQSN_3 IO_L35P_M3DQ10_3 IO_L35N_M3DQ11_3
IO_L45P_M3A3_3 IO_L45N_M3ODT_3 IO_L46P_M3CLK_3 IO_L46N_M3CLKN_3 IO_L47P_M3A0_3 IO_L47N_M3A1_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3
IO_L36P_M3DQ8_3 IO_L36N_M3DQ9_3
IO_L49P_M3A7_3 IO_L49N_M3A2_3
IO_L37P_M3DQ0_3 IO_L37N_M3DQ1_3
IO_L50P_M3WE_3 IO_L50N_M3BA2_3
IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3
IO_L51P_M3A10_3 IO_L51N_M3A4_3
IO_L39P_M3LDQS_3 IO_L39N_M3LDQSN_3 IO_L40P_M3DQ6_3 IO_L40N_M3DQ7_3 IO_L41P_GCLK27_M3DQ4_3 IO_L41N_GCLK26_M3DQ5_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L42N_GCLK24_M3LDM_3
IO_L52P_M3A8_3 IO_L52N_M3A9_3 IO_L53P_M3CKE_3 IO_L53N_M3A12_3 IO_L54P_M3RESET_3 IO_L54N_M3A11_3 IO_L55P_M3A13_3 IO_L55N_M3A14_3 IO_L83P_3 IO_L83N_VREF_3
J6 H5 H4 H3 L4 L5 E2 E1 K5 K6 C3 C2 D3 D1 C1 B1 G6 G5 B2 A2 F4 F3 E4 E3 F6 F5 B3 A3 100n
B10A
RES 2K03
10-3-34
Q552.4E LA
FPGA, I/O banks
3
2011-12-29
2
2011-09-29
3139 123 6531 19220_077_120229.eps 120229
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 127
FPGA, supply & control
FPGA, supply & control
B10B
B10B
5K20 +3V3
FK20
VAUX-LX25
100n
100n 2K28
100n 2K27
100n 2K26
100n 2K25
100n 2K24
100n 2K23
100n 2K22
2K21
1u0
RES 2K20
30R
+3V3 5K21
FK22
+3V3
VCCO3-LX25
100n
100n 2K42
100n 2K41
100n 2K40
100n 2K39
2K38
1u0
2K37
4
30R
7K20 3225
1
3
5K22
FK23
+3V3
IK20
3K20
IK21
FPGA-SYS-CLK-LX25
47R
2
100n
2K2T
VALUE
VCCO2-LX25
100n
100n 2K48
100n 2K47
100n 2K46
2K45
1u0
1u0 2K44
2K43
30R
6K20
3
5K23
FK24
+3V3
DBG 3K21
VCCO1-LX25
DBG
+3V3
470R
LTST-C190KGKT 7K21 PDTC144EU 2 DBG
1
DONE-LX25
100n
1604 1 2 3 4 5 6 VCCO0-LX25
FK26
8
7K22 M25P40-VMN6TP VCC IK22 Q 2
MOSI-LX25 FK21
CCLK-LX25 CSO-B-LX25
FK28 FK29
100n
100n 2K36
100n 2K35
100n 2K34
1u0
2K33
5
Φ
D
6
*
C
1
S HOLD
3
7
W GND 4
1u0 RES 2K32
1u0 RES 2K31
1u0 2K30
+1V2-LX25 2K29
+1V2-LX25
FK27
100n
2K2V
RES 3K22
100n
100n 2K2R
100n 2K2Q
100n 2K2P
100n 2K2N
2K2M
1u0
1u0 2K2L
8
502382-0670
30R 2K2K
+3V3 7
10R
FK25
MISO-LX25
3K23
5K24 +3V3
CCLK-LX25 CSO-B-LX25 MOSI-LX25 MISO-LX25 PROG-B-LX25
4K7
100n 2K2J
100n 2K2H
100n 2K2G
100n 2K2F
100n 2K2D
2K2C
1u0
1u0 2K2B
2K2A
30R
FK30 +5V 2K3A
+3V3
4 VDD
1n0
1
1
5 FK3A
6SLX9-4MB-M25P40 6SLX16-4MB-M25P40 6SLX25-8MB-M25P80 ---16MB-M25P16
SENSE+1V2-LX25
68K
4K7 1% 3K3C
10K 1%
9
3K3A
3 7
D C
Φ
32M FLASH
S W HOLD VSS 4
NC GND GND HS
VIA
6
cK3A
PGOOD 10
7 2K3D
ADJ
5
+1V2-LX25
10u
EN
6
2K3C
VOUT
8
2K3B
2
VIN
3K3B
3
+1V8
RES 7K23 M25P32-VMW6TG VCC 2 Q 8
1u0
7K24 RT9025-12GSP
10u
10-3-35
Q552.4E LA
FPGA, supply & control
3
2011-12-29
2
2011-09-29
3139 123 6531 19220_078_120229.eps 120229
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 128
Layout top
1G51
9G0G
2U87
2U85
2UD3 2UD6
2C94
2C7N 3C7H
1C86
5C55 2C71 9C06 2C70 3C7F
3U84
3J06 3J07
3UD5
3UD4
3J26
2J02
2J2K
6J21
2UDB
2UDC
2UDA
3U85
2C96
9C07 3C7G 2C7M
3C70
3C99
5C56
2C7F
3C98
2C95
1C04
2C7L
2C7K
5C57
2C7G 3C83
5C53
2U88
2U86
2U83
2U82
2U84
2C83
7J21
7J01
2UF1 2UF4
3UF2 3UF5 3UF6
9U44
3J0G
3J0C 2J04 3J00 3J0A 2J03
9U43
2UF7
3UF4
5UD2
7UD1
3C96
2UFA 2UFB
2G9C
2G9D
2C84
1K01 2UB6
2G91
2G9F
5U00
5U01
3U24
2U09
6U00
2U11
7U01 7U04 7U02
2UF0
5UD3
2U18
2UD8
2U19
3U23
2U25
2U23
2U24
2U17
2UD7
2UDF
2U20
5U03
2G9E
2C85
1C85
3UD3
2UF3
2UU2
5U02
1J02
3UD1
2UF9
2UU3
2UDD
3UU4
2UDH
5UD1
3U82
1UU0
7UD0
7U48
2UF8
3U83
2U71
2UD0
7U41
3U80
2D87
3U60
3U61
2UD1
3U73
3U62
2UD9
1D51
3U72
6UU1
2UD2
3U63
5UD0
2UF6
6U40
2U55
6J22 6J23
2UD4
1U40
6J25 6J24
2U68
2U47
2U54
3U71
2U81
1M54
9C09
1A04
1C03
9C08
5C54
7U40
3U45
3U42
2U46
2U45
2U8D
3U81
2U53
3U65
3U43
2U44
2D70
1D52
3U64
2D98
1D02
1D50
1A05
1T71 3C81
1M99 1J22
1M95
3K10 3K11
2K2T
7K20
2K02
1P00
7K00
3G47 3G45 3G31
3G46
2G7A 3G48
2G79 2G7F
3G34
2G7D 3G41 3G40 3G44 3G33 2G26 3G39 2G7B 2G7C 2G76 3G37 2G75
1TP1
6TP4
2NN7 2NN6
2TPC
2TPJ
3S44
3N9C
2T02
2N73
6N53 2N77 3FLN
1N80
3FLB
3FLD
2FL2
3FLK
3FLL
2FLG
2KCR 2RB1
2T20
2KCJ
5FA7 3FA1
3KA3
5FA6 3FA2
2FAA
5RA1 2RC8
2RBR
2RBB
9RB0
2RB4
9RB8
2RB3
2RB2
2RBM
2RBY
2N15
2RBW
7RA0 2RCB
2RBE
2RBK
2RB6
2RBD
2RBU
9RB9
1F00
2RC7
2RBC
2RB9
3FL7
2RBA
2RBL
9RB7
3FL8 2FLC
6RA0
2RBV
2RB5
3RB0
2RB7
3RB3
9RB6
1RA0
2NCW
IN43
2RBS
3RB1
2RBN
2RB8
2NC2
2RBP 2RCA
5NC2
3NCA
3FA0
3NC5
7NC1
2NC3
2FA6
3NC3
2NCY
INC8 5NC3
2RC9
2FA5
3NCK 3NCJ
2NCX
2NCZ
1N43
1P07
7RA1
2N91
1P05
2N88
1N31
1P03
1P02
5RA2 2RBJ
1P04
2RBH
1N54
1N05
2T12
7RC2 2KCK
3KC0 3KC7
2FA9
2RBG
1VA1
5T01
3F58
2T15
2S3M
7S09
7KC0 3KA0
3KA1
5FA5 2FAB
3NCN
3NCM
2FAC
2RBT
1N12
2T01 5T00
3S1T
3S1S
3S1U 3KC3
3KCA
3KCB 2KCG
2KCD
2KCE
2KCF 9KC1
5KC1
9KC0
2KCC 3S84
3S83
1VA8 1N28
1N39
6N43
6N44
3N87 2N27
3N89 2N67
6N40
6N51
2N68
3N90
2N71
3N97
3N96 2N40
2N39
6N52
6N06
2N55
1N42
1N06 2NCC
6N19
5FA4
2RBF
2N06
2NC1
3FA4
9FA0
5KC9 2FAG
3N02
2N04
6N03
6N09
2N79
3N03
2N80
6N23
5N73 3N74
3N75
3N32
2N24
6N22
2N35
9FA1
5KC8
IN45 2NCQ 2NCP
2NC8 2N18
1FA0
5KC0
2S87 3S59
2S7N
3S4J 2S7J
3S4U
2S7M
2S7L 3S4P
2S7K
2S7P
2S7H
3S4L
3S4K
3S13
3S4T
2S33
2S30
2S2W 2S2V
2S31
2S32
4S14
2S34
7S08
6N38
3N34 3N68
3N35
3N72
2N54
1N37
1N86
3N22 3N25
2N56
6N20 1N55
1N19 1N18
3N31
3N44
3N42
6N29
7N03
2N75
2N76
2N45
3N43
1N22
3N62
6N30
6N32
2N44
1N23
9FC3 9FC4 2FC7
1FC6
5N77
3FC2
2FC6
1N25
2FC1
1FC1
6FC7
3FC1
6FC6
6FC8
6FC1
2FC8
2FC2
1FC3 1FC4 1FC2
3RA1
3KC8
1N85
2N36 3N21
1FA1
2FAH
3NCH
3FC5 2FC4
3FC6
9FC5 3FC3
2FC3
6FC2
6FC4
3FC7
9FC6
2FC5
IC74
9FC2 9FC1
1NN9
6NN8
3S34
3S35
2S35
DBS8 3S36
2S38
3N28
2N07
5N02
2N57
3N20 2N38
6FC3
6C07
2NCN 2NCM
3N53
1N29
2N37
2RC6 3RA0
3KC9
3FA3
3N65
1VA4
6D61
9D53
9D52
3D55
2D72
2D74
9D54
3D71
3D58
3D56
2D39
2C81
3U68 3U41 9U41
3FC4
3C78
5N01
1N00
5D85
IC75
3C73 3C7A
2C80
1N09
6D60 3D83
3D76
6FC5
2C7B 2C7C
3N82
2N72
3N30
1FA2
3KC1
3N64
3N81
1N70
2FA0
3S4V 3S4W
3F65 3F64
5D84
3U59
3C71
2N05
1N38
3D50
3D77
3U74
3C95
2C72
7N10
2N59
5N04 2N08
3D57
3C94
2C87
2S78
2KCB
3D54
7D50
3D84
2S77
3S4R
1P08
3KC2
1F51
3N80 9N42
3N66
2N58
5N03
2D5F 2D77
7D80
3C97
2D68
2D86
2C93
7U42
2C91
3C76
BS10
3N51
3N29
2D64 2D67
1FC5
2C77
2FL7
3S3W 3N17
3S12
3N67
2D69
3C79
6C05
3N39
2N09
3C77
2C82
3N27
5D79 2D88
2D50
3D51 2D51
2C97
2C90
2S2T
3S26
3S6J
2D89
2D95
7D60
9D51
2D54 2D53 3C72
2D52
2C99
5N0C
3D72
2FL6
3S3F
3S37 3S38
3S32
3S00
3B04
5D76
5D74 2D94
2D61
3D73
2D79 3D52
2C86
2D82
2D75
2D85
5D70
2D80
3S42
2S41 2S4M
2N62
5N08
1N88
1FL5
3S3M
3S43
3KC4
1N87
7FL5
1F10
3S50
3S53
3D75
3D74
2C78
2D55
6N47
5D75
2D56 5D00
1N10
3S19
3S54
1S02
IS13
3S27
2D71
7F52
3S6N
3S2M
5D71
5D01
3F52 2F52
3S52
2S4G
3B14
9S06
5D72
2F49
2FLF
2T05
3S25
DS50
3S39
2B45
5D81
2D99
3B15
2D83
3S6M
1NN2
3S80 2S4F
7B03
5D80
5D77
3S28
3S1R 3S6K
3NCU 3B05
2D78
5D83
2D81
2D76
1D55
3S81
2D73
1F01
1D56
3S3L
3B24
2D91
1C30 1D01 1D54
2S3L
FF04
3S1C
3D80
2D5B 2D5D
5D78
1D53
3S24
2S3Q 3S1L
3S3N
3B13
3S1B
3S11
3S2A
3S3T
3S3R
3S1J
3B12
1KC0
3D81
7F58
FF28
3S1K
3B23
3B00
3D78
3S29
3S23
3S03
3S3Q
2F58
3S3S
2G95 3D79
3F60 3F59
3S21
2S4C
2B44
2G94
3S62
2S4D
7B02
2D5A 2D5C
9S01
2T00
9S00
2G99
2G93
7S02
3S02 3S01
3B02
2G97
2G92
3S3Y
3S04
2G98
2G96
7T00
3B07
2S09
3S31
6NN9
2T10
2B46
3B17
2D57
2D60
1G50
7B00
3B16
2NN8
7NN2
3B25
1NN8
3NN1
3TPB
7TP2
2NN9
5TP5
2TPL
2TPD
1F52
3S98
3S94
3S93
3S92
7S0A
2TPK
3B08
3B10
7S00
3S91
2S4P
3S97
3B19
3NN0
3S96
3S95 2B47
3B18
3TPF
7K21 3B11
6TP6
3B26
7B01
3TPD
2F01
1604
3K21
6K20
2TPF
2TPG
3G32 3G35
2TPH
3K06
3K12
3G2W 3G38
9K02
3G2Y 2G77
1C22 1C20 1C21
10-3-36
Q552.4E LA
1R01
1P06
Layout top
3
2011-12-29
2
2011-09-29
3139 123 6531 19220_079_120229.eps 120229
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 129
Layout bottom
IC7A
FC77
FC9K
FC99
FC9L
FC98
IC7D
IC7G
IC79
FC72
FC96
FC97
FJ27
FC75 FJ26
FJ29
2U89
FU58 2U50
FU60
FU63
2U06
IUU3
7UU3
7UU2
3UU8
9J02
3U18
7UU5 7UU4
3U04
IU06
FU05
IU08
IUDF
3UF1
3U28
IUD1
3U11
IU16
IU10
IUD4 2UF2
2J28
7U03
IU07
3U14
IU17 FU06
FU02
3UF3 IUD5
2U02
IU13
3U05
IU23
IU11
IUD2
2U22
2U21 IUDG
3U17 IU20
IUD9
IU09
IU19
IU14
FU04
IU18
3U20
2UF5
2U05
IU02
FU09
IU21
IU01
FUD2
2U29
FU00 FG2P
FU08 FUA4
3F03 FK01
FK02
FG2N
2U12
2U14 2U13
FG1V
FG1T
FG1S
FG1R
2K35
3K3A
3K3B
2K3D
2K3B
2K00
2K41
3K20
2K39
IK02
2K25
3K04
2K3C
3K23
2G28
2K47
2K48
FG26
FG25
FG24
FG23
FG22
3K07
3G43
FK07
FG20
FG2U
FG2F
FG2R FG2G
FK09
2K45
FG2M
FG2L
IK01
FK08 3K08
3K03
3K13
2K01
FG2H 5K22
2K43 2K44
FG34
7K22
2K2V
FG29
FG27
FG21
2K46
7K23 3K22
FK29
FG2B
FG28 2G29
3G42
2K2F
FG2C
3K3C
2K3A
2K20
FK21
IK20 IK21
2K23
FK27
2K29
7K24
2K28 FK20
5K20
2K40
2K37
FK22
5K21
9K01 2K38
2K42
2K26
2K2J
2K2D
FK28
2K24
2K34 2K22
2K33 2K32
FG2A
2K30
2K2P 2K36 2K2G
2F03
3UB1 FUA5
2K27
7F02
3F05
2K31
FK3A
2K2N
2K2L
5K24
2K2K
FK25 2K2A
2K2B
2K2H
2K21 2K2C
3UB3
3UB2
2K03
2K2Q
FK24
5K23
IF06 2UB3
2K2R
FK03
IF07
2UB2
2K2M
7F01
7UA4
FK00
IF05
3F04
FG1U
FK04 FU03
FUA3
FG1W
FG2D
3F10
2U08
3U09
FG1Z
3F09
3U19
2U07
IU04
FG1Y
FF62
3U08
IU24
IU15
5J21
FJ23
3U10
2U03 3U22
2U01
IUD8
2J2D
2J26
2J30
7J20
2J2H
7U00
FU01 3U01
2U16 2U15
2F02
FUA0
3F02
3F01
7USA
2UB0
6USA
FK23
IK22
3K05
FK26
6TP5
3K14
FK30
FK06
IK00
2B27
2B32 FB00
2B34
2B35
2B33
6TP1
FTPA
2B39
2B43
3TP3
ITPJ
ITPG
ITP4
FS2Y
2B42
3B27 2B22
3S06 2S4N
2B24
2S5P
2S17
2B19
3S6P
2S19
3NB6
2N53
IN64
2N63 IN32
IN07
ID92
FN02
FN03
IN33 FN32
AFA4
2RAV
IN0A
ID63
ID80 ID69
FC89 ID66
ID65
2RAS
FC9D 2RAT
2RB0
3RA2
ID56 2RA0
2RA1
FRA4
ID70
ID81 ID75
IN0B
2RAR
2RAU FRA1
ID77
3RA4
FRA2
2N0L
2RAW
2RA3
ID93
ID95 FN01
2RA4
FRA5
ID82
ID50
FN50
FN33
3RA3
ID62
ID94
FN34
2N52
FN56
FN49
3N40
FN27
ID53
2RA5
FRA6
9G0K FD32
IN39
FN61
3N95 3N99
2N49
2N48
FN29
IN38
2RAF
IRA3
3N26
3N98 2N70
3N33 3N71
FN31
3N70
FN5G
IN42
2RA6
ID52
3N69 FN5B
FFAA
AFA5
FL31
FN60
IN26 2N66
3N45
IN61
FN54
AFA1
FL39
ID51
IN63
AFA2
2RAE
FN30
IN92
3FAC
AFA0
2B36
2S42
7N05
IN91
IN96
IFA4
FFA8
IN44
2RCD
9N01
IN90
AFA3
3FAB
2NB1
IFA5 3FA9
IFA3
7FA1
2N74
7KA0 3FA8
3FA7
3KA2
3KA4
FFA7
3FAA
FL38
FN5D
2RAC
FFA3
2FLD
IN09
FN28
FN5A 2RAK
2RAG
2RAB
2RAL
2RAA
IFA6
2NB3
2FAD
2RAY
2RA2
2T16
2T17
FFA6
FFA2
2RAD
IRA8
2RCC 5T03
2RAM
2RA8
3RA6
5RA0
2RA7
2RAJ
7T03
FL33
FFA5
2RAP IRA0
IRA2
3FL4
2RAN
FRA0
FT09
2FLB
IFLJ
IRA1
2RCE
2T18
FL47
2RA9
FL41
IKC3
IN60
3N0A
3N18 IN89
IKC2
3RA8
2N98
7N06 IN13
3N19
IKC0 IKC6 FFAB
3RA7
3NB3
3N06 3NA2
IKC5
FL42
FD31
3S87
IN70
3NB1
2N81
FD33
IN10
2N99
2N97
2B08
2B03 2B07
IS1H
5N80
IN59
3N48
2KCS
FF64
FS13 IS0R
3S3P IKC1
IS1Q
3NA1
IKC9
IKC7
3S49
2KC0 2KC1
3S5F
3KCE
IS1R
FD95
IS12
3S86
FN5C
2B00
3B03
3S51
2S2R IS1J
2KC5
2KC7 2KC3
2KC4
FG1D
FG31
2B01
2S2S
IS1P
FF65
DKC0
3S85
2KC6
FFA0
FFAC
3S16 3S17 3S47
IKC8
3S1D
2KCP
2KC2
2FA4
3KC6
9RC2
FF66
DKC1 FKC1
5KC5
2FA1
IRC1
2RC4
5KC6
IKC4
7FA0
3RC2
2RC1
IRC2
FRC0
7RC0
2RC3 3RC1 FRC1
3B28
2B41
IN05 FFA1
2KCH
7RC1 2RC5
5RC0 5KC7
3F34
2FLA
3F32
IFLK FL43
2FA2
IFA0
FG1C
FG32
FD30
IS5G
2RC2
FG33
2B09
FS08
IS4V
2S8A
3S05
2S22
2S16
IS20
5FA0 2RC0 IRC0
FG1F
FD92
2B06
3S5T
IS5J
3S08
IS2Z
3S2S
2S3F
IS3G
IRC3
2B21
2B12 IS50
3S10
2B02
IS1B
IS1M
2B04
IS19
IS3F
IFL4
FG1J
FG1H
FG2T
2B05
IS5H
FL36
FG11
FG1G
2B14
2B16
2S24
2S68
2S4Q
2S36
FS0Y 3S46
3B20
3S07
3S6Q
2S29
IS3D
2S64 2S60
2S23 3S09
2S14 3S2L
2S86 2S84
FG1L
2B40
IS1A
2S2L
IS5D
3S1G 3S1H
2B17
2B13
2S45
2S4Z
3S4A
2S15
2S50 IS5E 3S5S FS15
FS10
IS44
5D50
FS02
2S4R
2S13
IS3B
FG12
FG1K
FG30
2S75
FS11
5S93
5S89
2S20
3S22
FS51
2S85
5D51
2S46
2S40
FS53
2S10
IN51
ID54
2B37 2B15
3S5B
FS52
IS5F 3N73
FS44
IFLG
ID55
IS42
2S6G
2S18
FS50
IS4Z
FG14
2B10 3S0V
2S65
3B01
FS0Z
3S5V
2FL1 FS49
3S55
FG16
2S6R 2S6D
2S6N
2S51
3S75
3S1P FS57
2S4K
2FLH
3FLP
3FLC
3FLF
2FL4 2FL5
3S2V
7S20
3S6H
FG18
FG15
FG13
2SHW
IS3L
FG1A
FG17
2B18
3S30
5S87
2S5A
2S28
5S81 5S90
5S04
2S55
5S95
5S84
3S2K
3S41 3S2H
2FL8 2FL9
3B06
3S33
2S4U 3S40
3S45 3S1F
3FLM
2S4L
FF03
IS16
IS1C
IFLA
9S09
IS05
FG1Q
FG19
3B22
2S5G 2S5K
2S4T 3C74
FG1P
2B11
2S6B
2S6C IF54
FL32
2S21
5S83
2S43
2S56
2S59
2S6M
2S5B IS01
FN55
2S4Y
2S3N
3S64
2S27
2S4V
FS64 IS1L
IS1K
3S0W
FT06
2S6A
FF29
FN5H
2S2A
FS54
2S6K
2S6L
IS10
IS04
2S6H
IS3S
IF59
2S5C
3S82
2S5D
IT18
5S82
FF57
IT02
2S11
IT00
2S58
5S80
5S92
IS58
IS3Q
2S37
5S85
2S4W
2S3G
2S6F
3S1X
3F06 3S1A
5S94
2S57
2S3H
3S1W
2S5H
3S56
3S69
3S6V
2S5J
3S6W
FF55
FF56
3S2F
3S6A FNN7
2S62
IS3K
2S5M
2S6P
3S57
2S4S
IS25 IS17
IS4W
IT01
2S63
IS26
3S5Y
3S20
3S6D
3S2G
2S25
3S6F
3S5Z
IT04
2B20
2S26
3S6L
2S67
3T01 3T02 2T04
IT24
2S61
5S88
2T03
3S1V 3S60
2S53
3NN5
2S52
FNN2
FNN1
2S66 3S6G 3S15
3T00 3T04 2T13 2T14 3T06 3T05
3S61 FT07
FG1B
FS01
FG1N
3S58 3S5W
9S08
FL30
2S89
IS00
3FLJ
3S6B 3S6C
INN8
2N60
3S0G
3S0A
IS09 IS0B
2B31
FG1M
9S12
FG2J
3S67
3B21
3S65
2NN1
3NN2
INN7
3B09
2B30
9S11
2B26
3S0C
3F12
2S0B
2NN3
2NN4
ITP2
9S13
2S0A
2B38
9S10
IS0C
2B25
7S01
3S0F 3S0D IS0A
2S12
3S0B
3F63
3F62
7NN1
3NN6
FF61
2NN0
INN5
2B29 IS08
FF63
2B28
2NN5
2B23
3S66
2NN2
ITPF
FS31
3F07
3S68
FS2W INN6
3FL2
FC88 ID87
ID61
2RAH
2C76
ID79
FRA3
FD67 2FAE
2FAK
2FAJ
2FAF
2FA7
3KCC
2FA8
FD34
FC87
7D61
FD50
3C75
3FAD
FFA9
FC91
3D82 ID78 FD66
FC94
6C03
ID84 FFA4
6C02
5FA1
IC7H
2C79 FC90
FC9A
IFA1
FNCP
FNCK
FNCJ FN58
FFC2
FFC5
FFC3
FFC7
7U43
3U69 FC9H
FNA7
IU44
FNA8
2N84
IN18
FC93
FC9J
FN83
FNA3
FNC1
FNC2
FNC6
FNC4 FN74 FN85
FN71
FN75
FN80
5N76 2N85 2N12
1N18 1N19
6N28
FNA6
2N86 3N79
FNC5
5N74
3N78
FNA5 FN73
6N26
3NC7
FNCG
FNC8
FFC1
FFC9
FN84
FN81 FN82
FNCF
FL44
FFC8
3U75
FNA1 FNA2
FNA4
FNCW FL45
9U42
5NC4
FNCS
FNCT
2N14
FNC0
6NC2
3N23
3N77
3NC6
3NCR
INC4
3N76
9NC3
3NCD IN11
7N02
2N83
FNCZ
FNCB
INC7
INC5
7NC0 6NC1
FNCY
2NCU
FRA8
3NCG
FNCR
FN43
IU47 FFC4
3NC1
INC6 9NC2 3NCL
3NCF
FRA7
FC9B
FC9G
FFC6
2NC4
3NCP
9NC0
2NC7
5NC0
FN48
7NC2
FNC3
FNCV 2NC6
FNCQ
FN42
2NCV
FN57
IRA7 FNCU
FN51
3U70
FC95
IU43
IU45
FL40
2NC0
FL46
3U53
FC92 IRA4 FNCH
IC73
IRA9 IFLH
FNC9
3NCT
FNCM
3USC
IUSC
IUU1
FUU1
9UU3
3U00
IU05
FU55
IUU0
2UU1
FUU0 FUD3
5J24 2J2N 2J2P
1J21
2J24
2J36 2J40
2J31
3J05
2J25 2J39 2J38 2J35
9J21
2J2G
2J37 2J41
FJ20
2J01 2J27
IJ02
IU22 FU73
2J2F 2J2C
7J24 3J28 3J30
7J23
2J34 2J23 3S72
3J03 3J04 2J44 2J43 2J42 5J22
7UC0
7J22
3J27 3J25 3J29
2J33
FJ22
2J29
IUSB
3USA
3USB
2UA4
7F00
2F00
3F11
7F05
2F06
3UB0
IF08 IUSA
FJ25
2J2M
FU52
2UU4
IUU2
FUU2
IU03
2J45 9J01
3J09
7F03
7F04 3F53 3F67
IF04
3F08
3UU3 IUU4
FJ03
FJ07
IF55
IF57
3F14 3F13
2F53 2UB1
6UA0
9USB
3USG
3USF
2USA
3USD
3F68
9USC
9USA
IF56
9F51 3F69
7F54
7F53 FF58
9UA0
3F66 3F54
FJ05
IJ01
3J01 2J46
3U03
2F04
2F05
FJ28
3J02
FJ01
2UU0 IUU5
7UU0
3UU2
2J22 2J21 5J20
FJ02
FJ24
FU51
IU55 FU53
FU72
9UU1 9UU0
FJ04
2J49 2J2B
5J23
2J32
2J2A
2J48 2J47
7J25
FU66
FU67
IU49
IU51
IUD6 FJ06
3J21 FC86
IU56
IU48
2UDG
FC85
2U49
FU75
1U40
FU76 IUDA
3UU7
IUD7
2UD5 3UD2
IUDH
2UU5
3J23
FU59
3UD0
FU48
3UU6
FC76 FJ21
3U21
IUD0 FU77
FJ30
IJ22
3UU9
IUD3
IUDC
2U56
3J24
7UU1
FU7K
9UU2
FU7J
3UU1
FU7H
3UU5
FU7G
IU12
FU7F
IU25
FU7D
3U02
FU7C
2U04
FU7B
2U00
FU7A
3U27
FC9F
7J26
2J50 3J31 2J51
FC71 FC74
2U10
IC78
FC73
FL37
10-3-37
Q552.4E LA
FNCL
FNCA
FNCN
FNCC
FNCD
Layout bottom
3
2011-12-29
2
2011-09-29
3139 123 6531 19220_080_120229.eps 120229
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.4E LA
10.
EN 130
10.4 B 313912365333 - 313912365334 SSB Power connectors
Power connectors
+5V +3V3-STANDBY
+12V-AL
RES 10K
**
GND-AL
3U75
RES 10K
LED-2
FU48
**
3U74
GND-AL
1 2 3 4 5 6 7 8
+3V3-STANDBY
+3V3
To be connect directly to 1A04 with 3mm Track width ** 1M99 **
IU43
9U41
2041145-8
RES 10K
**
3U69
BL-DIM1 BL-DIM2 BL-DIM3 BL-DIM4 BL-DIM5 BL-DIM6 BL-DIM7 BL-DIM8
10K
100R 100R 100R 100R 100R 100R 100R 100R
3U68
8 7 6 5 8 7 6 5
10u
1 2 3 4 1 2 3 4
1n0 1n0 1n0 1n0 1n0 1n0 1n0 1n0
2041145-9
3U84-1 3U84-2 3U84-3 3U84-4 3U85-1 3U85-2 3U85-3 3U85-4
10n
FU7A FU7B FU7C FU7D FU7F FU7G FU7H FU7J FU7K
1 2 3 4 5 6 7 8 9
* AL 2U56
* 1M54
B01A
* AL 2U89
B01A
2U81 2U82 2U83 2U84 2U85 2U86 2U87 2U88
4 Pin stuffing variant 1M11
RES RES RES RES RES RES RES RES
6 Pin stuffing variant 1M1B
IU44 IU45 9U42 RES
LED-1
LED2
LED2
3U59 10K RES
7U42 RES BC847BW
+12VIN IU47
+3V3
3U70
7U43 BC847BW
10n
RES 2U8D
3U41 10K RES
GND-AL
LED1
LED1
10K
3U53 10K
1u0
10n 2U68
3U71
STANDBY
3U82
100R
10n
1K0 RES 1 3U83-1 8
7U48-1 BC857BS(COL) FU77 6
2U54
STANDBY-1
1
2U47
+3V3-STANDBY
ENABLE-3V3-5V
cU40
100K
4 3U83-4 5
+12VD 1U40
+12V +3V3-STANDBY 4
10n
T 3.0A 32V
3
+12VIN 2U50
100n
2U71
2
100K
1M95 FU58 FU59 FU60
100HZ 3D with LX4 & LX25
100HZ 2D
LGD 50HZ 3D TM100
x x --
x -x
--x
7U48-2 BC857BS(COL)
+12V-AUDIO
3U61
10K
2 3U62-2 7
2
RES 10K
10K 5
22K
22K
3U60-3
4K7
6 6 8 7U41-1 BC847BS(COL) 1 10K
2
5 3U60-4 4
5
FU76
ENABLE-3V3n
22K
4 RES 10K
10n 2U46
3U62-1 1
7U41-2 BC847BS(COL)
3U63
1n0 2U45 RES
100p
100K
3K3
2U44
3
3U73 +3V3-STANDBY
DETECT2
3
POWER-OK
1
ENABLE-1V8
FU72
3U80
BL-DIM BL-I-CTRL
1K0
1n0
7U40-1 BC847BPN(COL)
3U60-2
100R
IU49
FU73
22K
7
3U43
IU55
3U64
3
100K
100K
1 3U60-1 8
6
2
2U55
100R
IU51
BL-DIM1
3U62-4
4 FU55
3U42
* 9U43 * 9U44
1K0
*
FU53
100R
3U72
3U45
FU51
PDZ6.2B(COL)
BL-ON BL-PWM
FU52
3U83-3
3
1u0 RES
IU56 10K
6U40
3U81
+3V3
1-2041145-4
6
5
10n
2U49
BL-ON-1 BL-DIM-1 BL-I-CTRL-1 POWER-OK-1
2 3U83-2 7 4
IU48
3
FU66
FU67
7U40-2 BC847BPN(COL)
10K
3U42 9U43 9U44
3U62-3
FU63 FU75
6
5
*
3U65
1 2 3 4 5 6 7 8 9 10 11 12 13 14
2U53
10-4-1
Power connectors
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_031_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts 10-4-2
Q552.4E LA
10.
EN 131
Interface connectors
Interface connectors
B01B
B01B
1C04
IC79
FC9F
+3V3
100K RES
V-AMBI
FC87
T 1.0A63V
3C75
100p
100R
2C77
3C76
100p
IC73
100R
2C78
IC74
3C77
100p
LIGHT-SENSOR 2C93
100p
100R
2C80
FC95
10K
KEYBOARD
100n
3C79 2C82
10R
1C86
100p
2.0A 63V
6C02
2041145-8
**
SDA-SET
9 10
FC97
FC98
100R
10p
6
RXD2-MIPS
100p
1u0 2C99 100p
2C97
RES 2C86 TXD2-MIPS
IRQ-CRP
FC9G
RES 3C71 RES 100R 3C73 47R RES 3C7A 47R
FC9H FC9J
100p
502386-0470
TEMPERATURE SENSOR
RES 2C72
10p 2C84
2C83
5
1 2 3 4
cC01
10p
3C83
TACHO
10p RES 2C7C
FC86
20
100R
1T71
FC96
19
FC9D
RES 2C7B
3C81 100R
13
FC9B
47R
502386-0870
FC85
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
FC9A
47R
3C72
3D-LED
12
RES 1C21 FH52-18S-0.5SH
0R3
RES 3C94 RES 3C95
SCL-SET
10p
AMP1 AMP2
**+T3C97
10p RES 2C87
+5V +12V
+5V
1C20 FH52-11S-0.5SH 1 2 3 4 5 6 7 8 9 10 11
**
1 2 3 4 5 6 7 8
** 2C91
**
RES * 1C03
* HOTEL TV
FC9L FC9K
4K7
100R 100R
3C96
* *
RES 3C98 RES 3C99
IC7H
1u0
2C90
+3V3-STANDBY
GND-AL
+3V3
T 1.0A 63V
30R
RES 5C53 +12V
2C85
5C54 +3V3
1u0
FC99
RES 1C85
SDA-BL
+5V
1 2 3 4 5 6 7 8
100n
3C78
2C81
IC75
LED-1
+12V-AL
GND-AL
SCL-BL
FC94
AMBI-SPI-OUT-CCLK
FH34SRJ-18S-0.5SH(50)
FH34SRJ-18S-0.5SH(50)
RXD1-MIPS TXD1-MIPS
RES PDZ5.6B(COL)
FC92 FC93
100p
T
FC91
+3V3-STANDBY 2C79
AV2-STATUS
FC77
FC90
RES
9C07
AMBI-SPI-OUT-MOSI
FC89
6C05
GND-AL
33R 10p 33R 10p
**
1C22
FC88
RES 6C07 PDZ5.6B(COL)
30R 100R
RES 2C94
FC76
20
100R
1u0
AMBI-TEMP
5C55 3C70
100n 2C70
FC73 FC74 FC75
3C7G 2C7M 3C7H 2C7N
To sensor & control
PDZ5.6B(COL)
10n
10u RES 2C7L
RES 2C7K
IC7G RES 9C09
LED-2
9C06
2C71
GND-AL
47n RES
10n
IC7D
FC71 FC72
10u 2C96
30R
2C95
RES 5C57
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
RC
19
IC7A RES 9C08
20
1u0
2C7F
1u0
1A04
19
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
+3V3
RES 3C7F
RES 1A05
V-AMBI
V-AMBI
RES 2C7G
RESERVED
6C03 RES
30R
2C76
PDZ5.6B(COL)
5C56
3C74
+3V3
IC78
Interface connectors
30R
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
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2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts 10-4-3
Q552.4E LA
10.
EN 132
DC/DC
B02A
DC/DC
B02A 5U03 RES 30R 5U02
FU05
IU22 +12V
1u0
2U20
10u
10u
7 8
IU10
12V/1V8 CONVERSION
1
2
3R3
3U11
2U19
2U25
7U02-1 SI4952DY
10u
10u
2U23
2U24
0R
FU02
2U21
5U00
FU03 +1V8 22u
47u
2U16
1
47R
47R 3U23-1 2
2U15
7
8
3u6
5 6 4
IU23 1n0
2U17
3
IU09
3U23-2
6 3
4
7U02-2 SI4952DY
47R
47R 3U23-3
5
220p 3U23-4
IU11
IU15
IU08
5 6 7 8
IU12
4
3U14 IU07
20
VIN
V5FILT VREG5
3U28 GND-SIG
18 19
FU04
1u0
2U05
10u
2U04
6
10K
2U14
22u
IU17
IU25
GND
+1V1 100n
RES 100u 2.0V
7 17
2U13
1 2
47u
TEST
2U12
1 TRIP 2
22 15
10R RES
1 2
+1V1
3U20
PGND
FU01
2u0 47R
1 VFB 2
5U01
FU06
24 13
47R 3U24-1
1 2
3U24-2
SW
47R
1 VO 2
12V/1V1 CONVERSION
1 12
47R 3U24-3
1 2
1 2 3
STPS2L30A
DRVH
4 IU14
1n0
GND-SIG
1 EN 2
5 6 78
IU16
23 14
2U11
IU02
12K
GND-SIG
21 16
1 2
RES 2U06
IU18 1u0
2U10
GND-SIG
1n0
2U09
GND-SIG
FU00
3U21 IU19
SENSE+1V1
GND-SIG
2U07
22K
3U10
GND-SIG
CU01 CU02 CU03 CU04 CU05
5K6
FU08
100n
1% 330R 1% 1K0
CU00
3U19
FU09
IU04
2U08
3U22 1K0 1% 3U09
330R 1%
1K0 1%
3U08 +1V8
100p RES
IU20
RES 2U29
3U17 3U18
100R 1%
RES 100p
10K RES 3U01
+3V3-STANDBY
IU01 3U03
22K
3
1 2
RES 3U00
5 8
DRVL
7U04 SI4778DY-GE3
3U24-4
1n0 RES
2U03 IU03
4 9
+1V1 +1V8
1 VBST 2
220p
6U00
3 10
ENABLE-1V8
3R3
2U01
100n
2 11
IU24
GND-SIG 3U02
3U05
7U03 TPS53126PW
IU13
10R
2U02 100n
RES 7U00 BC847BW
3R3
2U22 IU06
IU05
RES
1 2 3
3R3
10u
2U00
10R
3U04
1n0
3U27
2U18
7U01 SI4778DY-GE3
IU21
GND-SIG
GND-SIG
GND-SIG
GND-SIG GND-SIG
DC/DC
3139 123 6533
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2012-04-23
3
2011-12-12
2
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Circuit Diagrams and PWB Layouts
10.
EN 133
DC/DC, 1.8 V to 1.2 V conversion
DC/DC 1.8 V to 1.2 V conversion
B02B
+12V
+5V
1
IN
OUT
FUA4
3
PDZ5.1B(COL)
2UB6
2
1u0
2UA4
COM FUA0
6UA0
7UC0 LF25ABDT
22u 16V
RES 9UA0
4K7
4K7
4 3UB0-4 5
4K7
3 3UB0-3 6
4K7
2 3UB0-2 7
1 3UB0-1 8
+3V3
CUA0
+2V5
+2V5-LVDS
2UB1 1u0
ADJ PGOOD
1 5
9
3UB1
FUA5 SENSE+1V2
3K9 1% 82K
3UB3
7UA4-2 RT9025-12GSP
7
3UB2
22 23 24 25 26
8
NC GND GND HS
+1V2
1n0
EN
FUA3
6
2UB3
VOUT
10K 1%
10u
2
VIN
10u
VDD 3
+1V8
2UB2
4
7UA4-1 RT9025-12GSP
VIA 18 19 20 21
VIA
VIA
10 11 12 13
VIA 14 15 16 17
B02B
2UB0
10-4-4
Q552.4E LA
DC/DC 1.8 V to 1.2 V conversion
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
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Circuit Diagrams and PWB Layouts
10.
EN 134
DC/DC, 12 V to 5 V/3.3 V conversion
B02C
DC/DC 12 V to 5 V/3.3 V conversion
B02C
12V/5V CONVERSION 7UD0 RT8293AHGSP
100u 16V
100u 16V RES 2UDF
RES 2UDH
22u
2UDC
10K 1%
22u
2K2 1%
RES 1n0
ENABLE-3V3-5V
IUDA 470p
RES
2UDG
10n
SS2_GND
15K RES 2UD7
cUD1 3UD1
2UD3
IUDH
22u 3UD5
4
SS2_GND
6
12K 3UD4
COMP GND GND HS
+5V
IUD6
2UDB
VIA
FUD3
10u
3UD3
10
5UD1
100n
22u 2UDA
FB
SS
1R0
3 5
2UD5
2UDD
100n
8
SW
IUD7
3UD0
IUD3
10R
IUDC
EN
1
RES
2UD4
BOOT
3UD2
7 10u
2UD2
10u
2UD1
10u
2UD0
0R
VIN
3n3
2
2UD6
IUD0
9
5UD0 +12V
SS2_GND SS2_GND SS2_GND SS2_GND
12V/3V3 CONVERSION 7UD1 RT8293AHGSP
IUD9
SS1_GND
RES
SS1_GND
470p
cUD2
100u 16V
100u 16V RES 2UFB
RES 2UFA
22u
22u RES 2UF9
22u RES 2UF8
22u 2UF7
1K5 1%
3UF4
IUD4
4K7 1% 2UF6
+3V3
100K 3UF6
SS1_GND
6
FUD2
10u
IUD5
3UF5
COMP GND GND HS
5
5UD2
100n
10R
VIA
1R0
3
2UF2
2UF5
ENABLE-3V3-5V
FB
IUD8
RES
10
SS
3UF1
3UF3
8
SW
4
100n
IUDG
EN
IUD2
10n
2UF1
7
1
12K RES 2UF4
10u
2UF0
10u
2UD9
10u
IUDF
BOOT
3UF2
0R
VIN
3n3
2
2UF3
IUD1
9
5UD3 +12V
2UD8
10-4-5
Q552.4E LA
SS1_GND SS1_GND
SS1_GND
DC/DC 12 V to 5 V/3.3 V conversion
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
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2012-Jun-29 back to
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Circuit Diagrams and PWB Layouts
10.
EN 135
DVBS supply
DVBS supply
B03A
5T00
IT00 7T00 TPS54227DDA
Φ
SS
1
SW
EN VREG5
7
IT02
2T05 5T01
100n 6
IT18
3
IT24
FT06
2T10
10 11
5
9
3T00 RES 68K 3T04 RES
10n
8K2 1% 2T13
GND-1V0
1%
1n0 RES 2T14
22K
GND-1V0
470K
IT04
RES 3T02
2T04
1n0
RES 2T03
GND-1V0
VIA
1u0
IT01 GND_HS GND
+1V0-DVBS
3u0 22u
4 +2V5-DVBS
VBST
VFB
22u 2T12
2
RES 2T15
VIN
STEP DOWN
3T01
100n
10u 2T02
10u
2T01
30R
8
+12V-DVBS
22p 3T05
GND-1V0
FT07
SENSE+1V0-DVBS
8K2 1% 3T06 68K
cT01
+5V
+3V3
7T03-2 RT9025-12GSP
2T16
22 23 24 25 26
GND-1V0
VIA
5T03
EN
ADJ PGOOD
NC GND GND HS
6
+1V2-FE
7 1 5
VIA
VIA
VIA 14 15 16 17
VOUT
10u RES 2T20
VIN
10 11 12 13
9
10u
2
8
3
FT09
18 19 20 21
220u 6.3V
VDD
2T18
30R
1u0
4
7T03-1 RT9025-12GSP
+1V8
2T17
B03A
2T00
10-4-6
Q552.4E LA
DVBS supply
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
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2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 136
Core voltage supply for DVBS demodulator
Core voltage supply for DVBS demodulator
B03B
+12V
+12V-DVBS
1TP1 T
3.0A 32V
+12V-DVBS
100n
10u
5TP5
B230LA-M3
6TP6
RS1D
6TP5
2TPH
47u 35V
2TPG
17
7TP2 LNBH25PQ
+12V-DVBS +V-LNB
470n
10u 2TPC
ITPJ
10u 2TPD
VCC
47R
7
SDA-SSB-550
3TPD
47R
8 19
F22-DISECQ-TX 3TP3
DEBUG 6TP1
1K0
LTST-C190KGKT
DEBUG
3TPF
2 18
SCL SDA
DSQ
DETIN
NC
IN OUT FLT BPSW
ITP2 9
VIA
ISEL GND_HS
+V-LNB
FTPA
20 1 5 10 11 12 13 14 24 26 27 28 29 30 31 32 33
ITPG
25
4
PGND
22K GND
+5V
22 23
VOUT
2TPF
3TPB
ADDR
470n
21
47u 35V
SCL-SSB-550
VUP
2TPJ
B230LA-M3
6
16
ITPF
6TP4
VBYP
ITP4
3
220n
LX
2TPK
Φ
15
B03B
2TPL
10-4-7
Q552.4E LA
Core voltage supply for DVBS demodulator
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
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Circuit Diagrams and PWB Layouts
10.
EN 137
DDR
DDR
3B28
DDR2-CLK_P
240R
DDR2-CLK_N
G2 G3 G1
DDR2-BA2
DDR2-ODT RES 3B01
F9 E8 F8 F2 G8 F7 G7 F3 B3
240R
DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM2
3B23
0 1 2 3 4 5 6 7
DQS
C8 3 C2 D7 1 D3 D1 D9 3B00-4 4 B1 B9 3B00-1 1
2 6 3B02-3 33R 3 8 3B02-1 33R 2 3B02-2 5 3B02-4 4 33R 8 33R
B7 A8
NU|RDQS
3B00-2
7 33R 6 3B00-3 33R 7 33R 5 33R
3B12 33R
3B13 2B44 RES
0 1 BA 2
2p2
DDR2-D16 DDR2-D17 DDR2-D18 DDR2-D19 DDR2-D20 DDR2-D21 DDR2-D22 DDR2-D23
DDR2-DQS2_P DDR2-DQS2_N
33R
A2
H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 G1
DDR2-BA0 DDR2-BA1 DDR2-BA2
DDR2-ODT
ODT
RES 3B03
CK CKE CS RAS CAS WE DM|RDQS VSS
NC
L3 L7
DDR2-A14
VSSQ
VSSDL
F9 E8 F8 F2 G8 F7 G7 F3 B3
240R
DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM3
3B24 33R
2B17 100n 2B37 100p VDD
VDDL
E2
A9 C1 C3 C7 C9
E1
A1 E9 L1 H9
100n
100n 2B16
100n 2B15
100n 2B14
100n 2B13
100n 2B12
100n 2B11
100n 2B10
47u 2B09
E2
E1
A9 C1 C3 C7 C9
DQ
A3 E3 J1 K9
33R
2B41
2B36 100p 2B08 100n
DDR2-BA0 DDR2-BA1
SDRAM
DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13
VREF
VDDQ
Φ
0 1 2 3 4 5 6 A 7 8 9 10 11 12 13
SDRAM DQ
0 1 2 3 4 5 6 7
DQS
C8 3B05-3 C2 3B04-3 D7 D3 D1 D93B04-4 B1 B93B04-1
4 1
B7 A8
NU|RDQS
3B14 33R
3B15 2B45 RES
0 1 BA 2
3B04-2 2 7 6 33R 6 33R 33R 33R 2 7 3B05-2 1 8 3B05-1 33R 5 5 3B05-4 33R 4 33R 8 33R
3 3
DDR2-D24 DDR2-D25 DDR2-D26 DDR2-D27 DDR2-D28 DDR2-D29 DDR2-D30 DDR2-D31
DDR2-DQS3_P DDR2-DQS3_N
33R
2p2
A2
ODT CK CKE CS RAS CAS WE DM|RDQS VSS
+1V8
NC
L3 L7
DDR2-A14
VSSQ
VSSDL
A7 B2 B8 D2 D8
DDR2-CLK_P DDR2-CLK_N
7B03 EDE1108AGBG-1J-F
VREF
VDDQ
Φ
B04A
DDR2-VREF-DDR
E7
3B27 240R
VDDL
A3 E3 J1 K9
DDR2-CLK_N
VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13
A7 B2 B8 D2 D8
DDR2-CLK_P
240R
H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8
E7
3B22
DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13
A1 E9 L1 H9
7B02 EDE1108AGBG-1J-F
AT T-POINT
+1V8
DDR2-VREF-DDR
100n
100n 2B07
100n 2B06
100n 2B05
100n 2B04
100n 2B03
100n 2B02
100n 2B01
47u 2B00
+1V8
2B40
B04A
+1V8 DDR2-VREF-DDR
DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM0
FB00
1X20 HOOK1
1X21 HOOK1
1X22 HOOK1
1X23 HOOK1
3B25 33R
0 1 2 3 4 5 6 7
DQS
C8 C23B08-4 4 D7 D3 3B08-2 2 D1 D9 3B07-4 4 B1 B9 3B07-1 1
B7 A8
NU|RDQS
2 5 33R 7 33R 5 33R 8 33R
2p2
3 1 3
3B07-2
7 33R 6 3B07-3 33R 8 3B08-1 33R 6 3B08-3 33R
3B16 33R
3B17 2B46 RES
0 1 BA 2
DDR2-D0 DDR2-D1 DDR2-D3 DDR2-D2 DDR2-D4 DDR2-D5 DDR2-D6 DDR2-D7
DDR2-DQS0_P DDR2-DQS0_N
33R
A2
DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13
H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8
DDR2-BA0 DDR2-BA1
G2 G3 G1
DDR2-BA2
DDR2-ODT
ODT
3B09
CK CKE CS RAS CAS WE DM|RDQS VSS
NC
VSSDL
L3 L7
DDR2-A14
VSSQ
DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM1
RES 240R
3B26 33R
F9 E8 F8 F2 G8 F7 G7 F3 B3
2B35 100n 2B39 100p VDD
VDDL
VDDQ
E2
A9 C1 C3 C7 C9
E1
A1 E9 L1 H9
100n
100n 2B34
100n 2B33
100n 2B32
100n 2B31
100n 2B30
100n 2B29
100n 2B28
47u 2B27
E2
E1
DQ
A3 E3 J1 K9
3B21
DDR2-VREF-DDR
240R
F9 E8 F8 F2 G8 F7 G7 F3 B3
Φ
SDRAM
VREF
Φ
0 1 2 3 4 5 6 A 7 8 9 10 11 12 13
SDRAM DQ
0 1 2 3 4 5 6 7
DQS
C8 C2 3B11-3 3 D7 3B10-3 33R 3 D3 D1 D93B10-4 4 B1 B93B10-1 1
B7 A8
NU|RDQS
2 1 5 3B11-1 33R 4 8 33R
3B10-2
2p2
7 33R
7 3B11-2 8 33R 33R 3B11-4 33R
5
3B18 33R
3B19 2B47 RES
0 1 BA 2
2 6 6 33R
DDR2-D8 DDR2-D14 DDR2-D10 DDR2-D11 DDR2-D12 DDR2-D13 DDR2-D9 DDR2-D15
DDR2-DQS1_P DDR2-DQS1_N
33R
A2
ODT CK CKE CS RAS CAS WE DM|RDQS VSS
NC
VSSDL
L3 L7
DDR2-A14
VSSQ A7 B2 B8 D2 D8
3B20
180R 1%
RES 3B06
7B01 EDE1108AGBG-1J-F
VREF
E7
DDR2-BA2
DDR2-ODT
VDDQ
A3 E3 J1 K9
G2 G3 G1
VDDL
2B43
2B26 100n 2B38 100p
DDR2-BA0 DDR2-BA1
VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13
A7 B2 B8 D2 D8
H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8
E7
+1V8
DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13
A1 E9 L1 H9
7B00 EDE1108AGBG-1J-F
A9 C1 C3 C7 C9
100n
100n 2B25
100n 2B24
100n 2B23
100n 2B22
100n 2B21
100n 2B20
100n 2B19
47u 2B18
2B42
DDR2-VREF-DDR
180R 1%
10-4-8
Q552.4E LA
1X24 HOOK1
DDR
3139 123 6533
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2012-04-23
3
2011-12-12
2
2011-05-25
19220_038_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 138
PNX 85500: Power
PNX 85500: Power
B05A
5S80
IS3Q
30R
1
100n
2S5A
10u
2
+1V1 2S6A
B05A
5S81 10u
2S5B
5S82
VDD_3V3_SBY
10u
2S5D
2S4M
100n
1 10u
2S4P
100n
2S4N
VSSA_USB
VDDA_2V5_VADC VDDA_2V5_VDAC VDDA_3V3_USB
100n
2S4Y
10u
2S50
100n
2S4Z
6.3V 10u
100n
c000
SENSE+1V2
Y17 D13 T20 Y13
+2V5-AUDIO
Y10
100n
VDDA_2V5_USB
+1V2 30R
R21
R20
VSSA_2V5_LVDS_BG
100n
2S45
+2V5-AUDIO
5S87 +2V5 1u0
2S56
100n
2S55
30R
5S88 30R
10u
100n 2S57
2S5M
+2V5-LVDS
+2V5 100n 2S58
30R
1
10u
2 100n 2S6K
1
2S6H
2
5S89
5S90 +2V5 10u
100n 100n
2S53
2S4T
30R
2SHW
5S92 1u0
100n 2S59
2
+3V3 30R
1
100n 2S6L
2S6M
2
IS58
1
VDD_1V1_DDR
VSSA_1V1_LVDS_PLL
VDDA_2V5_LVDS_BG
+2V5 5S84
AA9 AA7
30R
30R
2S46
VDDA_2V5_DCS
5S95
Y12
1u0 2S4W
+1V1 IS3L
2S52
VDDA_2V5_ADAC
5S83
B13
2S51
VDDA_2V5_AADC
10u
100n
Y19 Y18
AA15 Y15 VDDA_1V2 AA13 VDDA_2V5
2S6P
2
+3V3-STANDBY
IS3K VDDA_1V1_LVDS_PLL
+3V3
30R
1
100n
100n 2S6C
2 100n 2S6N 1
2
W20 P20 M20 K20 V7 Y8
100n 1 2S6G 2
5S85
10u 2S4U
VDD_1V1
C7 C9 C11 C14 C16 C18
2S4V
VDD_3V3
+2V5-LVDS
N6 N7
2S6F
VDD_2V5_LVDS
U22
1
VDD_2V5
220u 6.3V
2
100n 2S6R 2
U20 U21
2S6D
HDMI_VDDA_2V5
+2V5
30R
1
HDMI_VDDA_1V1
V20 V21
HDMI_VDDA_3V3_TERM
C13
1u0
2S21
100n
2 1
VDD
HDMI_AGND
J7
30R
VDD_1V8
A13
2S29
220u 2V0
7
5 100n
4
100n 2S5J-4
100n 2S5J-2 2
3 5S94
+1V1
2S5P
VSS
10u
VSS
VSS
2S4S
VSS
M7 N2 N20 P10 P12 P14 P16 P18 P4 P6 P7 T10 T12 T14 T16 T18 T2 T6 T7 U4 V10 V12 V14 V16 V18 V2 Y20
AF1 AE2 AD3 AC4 AB5 H20 F11 G11 F13 G13 F15 G15 F17 G17 F19 G19 J9 J11 J13 J15 J17 L9 L11 L13 L15 L17 N9 N11 N13 N15 N17 R9 R11 R13 R15 R17 U9 U11 U13 U15 U17 J6 AA6 Y7 W7 F9 G9
U24 V24
100u
2S23
5 100n
4
100n 2S5H-4
6 3
100n 2S5H-3
8 100n 2S5H-2 8 100n 2S5J-1
5
6
1
3
4
100n 2S5J-3
6
7
AA16 AA8 Y11 Y14 Y16 Y9 VSSA
G14 G16 G18 G2 G20 G8 H4 H6 H7 J20 K10 K12 K14 K16 K18 K2 K6 K7 L20 L4 M10 M12 M14 M16 M18 M6
A1 A10 A12 A15 A17 A19 A26 A3 A8 B1 B20 C20 C4 D2 D20 E13 E20 E4 F10 F12 F14 F16 F18 F20 F8 G10 G12
100n 2S5K-4
100n 2S5K-3
100n 2S5K-2 2
1
2S5K-1
8
4
2
6
5
1
100n 2S5H-1
100n 2S5G-4
3
100n 2S5G-3
7 2
100n 2S5G-2
2S5G-1 1
22u
22u 2S4R
100n
2S4Q
100n
2S27
2S28
2S43
8
7
+1V1
30R
5S93 L6 L7 R6 R7 U7 A5 A6 B5 B6 C6 D6 E6 F6 G6 F7 G7
7S00-10 PNX85500
7S00-12 PNX85500
100n
2S5C
2
+3V3
c001
SENSE+1V1
30R
1
100n
2S6B
2
+2V5
IS3S
100n
100n 2S68
100n 2S67
100n 2S66
100n 2S65
100n 2S64
100n 2S63
100n
2S62
100n 2S61
100u 2S60
2S26
+1V8
100n
10-4-9
Q552.4E LA
PNX 85500 Power
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_039_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts 10-4-10
Q552.4E LA
10.
EN 139
PNX 85500: Standby controller
PNX 85500: Standby controller
B05B
+1V1
B05B
100n
1u0 2S10
2S13
30R
RES 5S04
IS3B
2S37 1u0 2S11
IS20
10K 3S3T 10K
+3V3-STANDBY 3S1H 10K
3S1G
RXD-UP TXD-UP
10K 3S2A
RXD-UP TXD-UP DETECT2
AE21 0 AF21 1 AA22 2 AB22 P3 3 AC22 4 AD22 5
RESET-SYSTEMn AV2-BLK AV1-BLK KEYBOARD LIGHT-SENSOR AV1-STATUS AV2-STATUS
AD23 0 AE26 1 AE25 P5 2 AE24 3
DETECT2
10K RES 3S1K 10K RES
RESET-SYSTEMn 3S1J 100K RES
KEYBOARD 2S4C 100n
3S1L 10K
SPI-PROG
SPI-PROG PNX-SPI-WPn
AF22 4 AE22 P6 5
PSEN MC
54M
1S02
AC17
AF26
VDD_XTAL
ALE
RESET-STBYn
AB24
EA
AB23
ALE
AC26
PSEN
AC23 SDA AC24 SCL
AD26 0 AC25 PWM 1
3S2F 100R
100R
3S2G
100R
3S2K
3S2H 100R
SDA-UP-MIPS SCL-UP-MIPS LED1 LED2
AE23 SDO AF25 SDI SPI AF24 CLK AF23 CSB
IS3F
3S44
IS3G
10K
3S43
IS3D
10K 3S42
10K
EA ALE PSEN RES
SDA-UP-MIPS SCL-UP-MIPS
3S6V
RES
LED1 LED2
3S4A
100R
FS0Y IS2Z
CTRL-DISP3 RESET-DVBS RESET-USBn RESET-ETHERNETn SEL-HDMI-ARC RESET-AVPIP RESET-AUDIO AUDIO-MUTE-UP
CTRL-DISP3 RESET-DVBS RESET-USBn RESET-ETHERNETn SEL-HDMI-ARC RESET-AVPIP RESET-AUDIO AUDIO-MUTE-UP
3S1P
4K7
RES
3S41
10K 10K
PNX-SPI-SDO PNX-SPI-SDI PNX-SPI-CLK PNX-SPI-CSBn
AB17 0 AA18 1 AD18 2 AE18 3 AF18 P0 4 AA19 5 AB19 6 AC19 7
3S6W
4K7
RES RES RES RES RES RES
3S2L 3S46 3S3Y 3S47 3S2S 3S2M 3S3W 3S49
10K 10K 10K 10K 10K 10K 10K 10K
+3V3-STANDBY
+3V3-STANDBY
7S20 NCP803
10K
RES 3S3S
EA
AA26
3S2V
10K
AC20 0 AD20 1 AE20 2 AF20 3 AA21 P2 4 AB21 5 AC21 6 AD21 7
+3V3-STANDBY
10p
VCC RESET GND
FS0Z
2
RESET-STBYn
1n0
3S3P
LCD-PWR-ONn EJTAG-DETECTn BL-ON STANDBY CTRL-DISP1 CTRL-DISP2 POWER-OK ENABLE-3V3n
RESET_IN
STANDBY
10p 2S4F
AF17
RES 2S4L
10K
LCD-PWR-ONn EJTAG-DETECTn BL-ON STANDBY CTRL-DISP1 CTRL-DISP2 POWER-OK ENABLE-3V3n
1
3
3S3M
RES 10K 3S3N RES 10K 3S3Q RES 10K 3S3R 10K RES
2 4
AE17
1
3S3L
10K
7S00-9 PNX85500
XTAL_OUT
2S4G
3
1
XTAL_IN
AD17
3S1A 10K +3V3-STANDBY
AD19 0 AE19 1 AF19 2 P1 AA20 3 AB20 7
100n
10K 3S1D 27K
RES 10K RES 3S1F
RC TACHO CEC-HDMI BACKLIGHT-PWM-ANA-DISP SDM
VDDA_ADC2V5
3S1C
RC TACHO CEC-HDMI BACKLIGHT-PWM-ANA-DISP SDM
VSS_XTAL
2S4D 1n0
3S1B
DS50
2S4K
+3V3-STANDBY
VDDA_1V1_DCS
AA17
POL
100n
PNX 85500 Standby controller
3139 123 6533
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2012-04-23
3
2011-12-12
2
2011-05-25
19220_040_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
B05C
* 3D ACTIVE
+3V3
7S00-3 PNX85500
CONTROL
3D-LR
3S82
BL-I-CTRL-PNX
+3V3 10K
RES 3S21
10K 10K
+3V3
FS10 TXD2-MIPS FS11 RXD2-MIPS IS04
* 9S09
GPIO6 PNX-SPI-CS-BLn
BL-I-CTRL-PNX GPIO6
SELECT-SAW
PNX-SPI-CS-BLn
+3V3
USB-DM USB-DP
10K
SELECT-SAW
2
SDA SCL
3
SDA SCL
4
SDA SCL
RESET_SYS
5K6
+3V3
3S55
10K
RES 3S64
GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_10 GPIO_11
TRSTN TMS R26 DN TCK R25 USB DP TDO IS4Z R24 RREF TDI
10K RES 3S62
IS16
BL_PWM
FS64
CLK_54_OUT
3S83
3S5Y
B25 A24
1 100R
B24 A23
3S60 1 2 100R
2 3S5W
2
3S6C
2K2
SDA-SSB-550 SCL-SSB-550
SDA-SSB-550 SCL-SSB-550
3S6L
2K2
1 100R
2
3S61
SDA-TUNER SCL-TUNER
SDA-TUNER SCL-TUNER
3S6G
2K2
3S6B
2K2
3S6D
2K2
3S6F
2K2
3S6K
EJTAG-TRSTn-PNX85500 EJTAG-TMS-PNX85500 EJTAG-TCK-PNX85500 EJTAG-TDO-PNX85500 EJTAG-TDI-PNX85500
1 10K
8 3S6H-1 10K 3 6 3S6H-3 10K 2 10K
+3V3-STANDBY 7 3S6H-2 5 3S6H-4 4 10K RES 1F10
RESET-SYSTEMn
33R
AD5
SDA-SET SCL-SET
3S5Z
3S00
4K7
4K7
2
EJTAG-TRSTn-PNX85500 EJTAG-TMS-PNX85500 EJTAG-TCK-PNX85500 EJTAG-TDO-PNX85500 EJTAG-TDI-PNX85500
AE4
3S6A
1 100R
AA25 AA24 AA23 AB26 AB25
BL-DIM
AC5
RXD1-MIPS
+3V3
1 100R
SDA-SET SCL-SET
3S69
SDA-UP-MIPS SCL-UP-MIPS
cS51 cS52 cS53
SDA-SSB-550 SCL-SSB-550
RESET-SYSTEMn
SDA-FE SCL-FE RESET-FUSION-OUTn
FS44
EJTAG-TRSTn-PNX85500 EJTAG-TMS-PNX85500 EJTAG-TDO-PNX85500 EJTAG-TCK-PNX85500 EJTAG-TDI-PNX85500
FS49 FS50 FS51 FS52
EJTAG-DETECTn
FS53
3D-VS
10K 3S84
TXD1-MIPS
+3V3
+3V3
3S72
BL-DIM
10 9
+3V3
1 2 3 4 5 6 7 8
FOR FACTORY USE ONLY
100R
10K
+3V3
FS57
BM08B-SRSS-TBT
RES
+3V3 RES 2S89 100n RES 7S01 PCA9540B
VDD
SCL-SET SDA-SET
1 2
+3V3
3
3S80 3S81
IS17
3S58 1 2 100R
B26 A25
SDA-UP-MIPS SCL-UP-MIPS
10K
FS54
10K
Y21 Y22 Y23 Y24 W21 W22 W23 V22 V23 U23
2 3S57
3S27
* 3S40
BOOTMODE 3D-LR RXD1-MIPS TXD1-MIPS RXD2-MIPS TXD2-MIPS
1 100R
10K
10K
3S56 1 2 100R
C25 SDA C26 SCL
3S26
1
BOOTMODE
RES 3S6J
IS05
3S45 +3V3
+3V3 +3V3
EN 140
PNX 85500: MIPS
B05C
+3V3
10.
PNX 85500: MIPS
10K
10-4-11
Q552.4E LA
SCL SDA
INP FIL
I 2 C -BUS CTRL
SC0
5
SCL-DISP
SC1
8
SCL-BL
SD0
4
SDA-DISP
SD1
7
SDA-BL
SCL-DISP
RES 3S65
4K7
SCL-BL
RES 3S66
4K7
SDA-DISP
RES 3S67
4K7
SDA-BL
RES 3S68
4K7
6
VSS
FS31
9S10 RES IS08 SCL-SET
7S00-4 PNX85500
+3V3
3S85-3 3S85-2 3S86-2 3S85-4
3 2 2 4
6 7 7 5
47K 47K 47K 47K
SDIO-CMD SDIO-DAT0 SDIO-WP SDIO-DAT2
3S86-4 3S85-1 3S86-3 3S86-1
4 1 3 1
5 8 6 8
47K 47K 47K 47K
SDIO-DAT3 SDIO-DAT1 SDIO-CDn
RES 3S87 47K
SDIO-CLK
SDA-SET
AA3
ETH-RXD(0) ETH-RXD(1) ETH-RXD(2) ETH-RXD(3)
Y5 0 Y6 1 AB4 RXD ETH 2 AC1 3
IS50
ETH-RXDV ETH-RXER
AC2 RXDV Y4 RXER
SDIO-DAT3 SDIO-CLK SDIO-CMD SDIO-DAT0 SDIO-DAT1 SDIO-DAT2 SDIO-CDn SDIO-WP
W2 W1 W6 W5 W4 W3 U6 V6
FS2W
SCL-DISP
9S12
FS2Y
SDA-DISP
9S13 RES
SDA-BL
ETHERNET
ETH-RXCLK
RXCLK
IS09
SCL-BL
9S11
TXCLK 0 1 2 3 TXEN TXER COL CRS MDC MDIO
TXD ETH
CC_DAT3 CLK CMD 0 SDIO 1 DAT 2 SDCD SDWP
AA2
ETH-TXCLK
AA1 AA4 AB1 AB2 AA5 AB3 AC3 Y2 Y3 Y1
ETH-TXD(0) ETH-TXD(1) ETH-TXD(2) ETH-TXD(3) ETH-TXEN ETH-TXER ETH-COL ETH-CRS ETH-MDC ETH-MDIO
PNX 85500 MIPS
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_041_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 141
PNX 85500: Control
PNX 85500: Control
+3V3-STANDBY
B05D
+3V3-STANDBY
+3V3
3F66
2
PNX-SPI-SDI
Q
Φ
512K FLASH
D C
5
PNX-SPI-SDO
6
PNX-SPI-CLK
1
S
PNX-SPI-CSBn IF54
3
W
7
HOLD
BL-I-CTRL 7F53 RES PDTA114EU
PNX-SPI-WPn
IF55
BL-I-CTRL-PNX
+5V
+3V3-STANDBY FF28
VSS
FF29
7F54-1 RES BC847BPN(COL) 6
7F54-2 RES BC847BPN(COL)
SPI-PROG
4
IF56 4
IF57 FF03
47K
VCC
3F68 RES
RES 3F67
7F52 M25P05-AVMN6
+3V3
+3V3
10K
8
3F52
100n RES
2F52
100p
2F49
+3V3-STANDBY
10K RES
B05D
10K
2 1
5
FF04
SDM 3 RES 3F53
FF58
DEBUG ONLY 2F58 RES
1 2 3
0 1 2
FF61
ADR SDA
1K0
100R FF62
SDA-SSB-550
8
WC
RES 3F54
RES 1F52
3F62
3F63
FF63
SCL
4
100R
SCL
1 2 3
SDA 5
7 6 5
FF55
3F59 100R
3F60
SCL-UP-MIPS
FF56
SDA-UP-MIPS
100R
4
IF59
Φ (8K × 8) EEPROM
10K
3F58
9F51
SCL-SSB-550
100n 7F58
10K
MAIN NVM
+3V3
RES 3F69
RES 2F53
10K
1u0
10-4-12
Q552.4E LA
FF57
LEVEL
DEBUG / RS232 INTERFACE
TXD-UP RXD-UP RESET-STBYn SPI-PROG
FF65
3F64
FF66
100R
SHIFTED
RES 1F51 FF64
3F65 100R
7
6
1 2 3 4 5
UP
FOR DEBUG USE ONLY
PNX 85500 Control
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_042_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts 10-4-13
Q552.4E LA
10.
EN 142
PNX 85500: SDRAM
B05E
PNX 85500: SDRAM
B05E
7S00-6 PNX85500 T25 T26
HDMIA-RX1+ HDMIA-RX1-
U25 P U26 RX1_A N
P RX0_A N
DDC_A
Y26 SCL Y25 SDA
HDMIA-RX0+ HDMIA-RX0-
V25 P RX2_A V26 N HOT_PLUG_A
HDMIA-RXC+ HDMIA-RXC-
W25 P W26 RXC_A N
DDCA-SCL DDCA-SDA IS10
T24
IS01
3S0W
W24
RREF
10u
12K
F3 C2 F2 C3 B4 F1 C1 E1 F4 B2 E5 C5 A4 G5 B3 F5 U3 P2 U2 P3 N1 U1 P1 T1 V4 R5 U5 P5 N3 V3 R4 V5
3S07
180R 1%
180R 1%
3S22
DDR2-VREF-CTRL2
2S12
CLK
N P
DQS0
N P
DQS1
N P
DQS2
N P
DQS3
N P
CASB CKE CSB ODT PCAL RASB WEB 1 VREF 2
DDR2-CLK_N DDR2-CLK_P
3S30
N5 N4
10R
3S33 10R
E2 E3
DDR2-DQS0_N DDR2-DQS0_P
D3 D4
DDR2-DQS1_N DDR2-DQS1_P
R1 R2
DDR2-DQS2_N DDR2-DQS2_P
T3 T4
DDR2-DQS3_N DDR2-DQS3_P
K3 K4 L5 M4 M1 M5 H3
DDR2-CAS DDR2-CKE DDR2-CS DDR2-ODT DDR2-RAS DDR2-WE
A2 V1
DDR2-CKE
3S6Q 10K
DDR2-ODT
3S6P 10K RES
DDR2-VREF-CTRL2 DDR2-VREF-CTRL3
3S0V
FS01
DDR2-VREF-CTRL3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DQ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
2S24
FS02
100u 2.0V
3S06
180R 1%
180R 1%
3S20
+1V8
M0
DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-A14
IS42 261R
DDR2-D0 DDR2-D1 DDR2-D3 DDR2-D2 DDR2-D6 DDR2-D5 DDR2-D4 DDR2-D7 DDR2-D8 DDR2-D9 DDR2-D10 DDR2-D11 DDR2-D12 DDR2-D13 DDR2-D14 DDR2-D15 DDR2-D16 DDR2-D17 DDR2-D19 DDR2-D18 DDR2-D22 DDR2-D23 DDR2-D20 DDR2-D21 DDR2-D24 DDR2-D30 DDR2-D26 DDR2-D25 DDR2-D28 DDR2-D31 DDR2-D27 DDR2-D29
0 1 DM 2 3
J1 J3 K1 G4 L3 G3 L2 H5 L1 J5 J2 M3 J4 M2 K5
1%
D1 D5 R3 T5
0 1 2 3 4 5 6 7 A 8 9 10 11 12 13 14
100p
DDR2-DQM0 DDR2-DQM1 DDR2-DQM2 DDR2-DQM3
MEMORY
0 1 BA 2
100n 2S25
DDR2-BA2
H1 H2 G1
DDR2-BA0 DDR2-BA1
100n 2S17
7S00-8 PNX85500
100p 2S20
RES 2S2A
+3V3
HDMI_DV
HDMIA-RX2+ HDMIA-RX2-
PNX 85500 SDRAM
3139 123 6533
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3
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2
2011-05-25
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2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 143
PNX 85500: Nandflash - conditional access
PNX 85500: Nandflash - conditional access
B05F
7S00-5 PNX85500
D22 ALE C21 NAND CLE
XIO-A00 XIO-A01 XIO-A02 XIO-A03 XIO-A04 XIO-A05 XIO-A06 XIO-A07 XIO-A08 XIO-A09 XIO-A10 XIO-A11 XIO-A12 XIO-A13 XIO-A14
J25 J26 H21 H22 H23 H24 H25 H26 G21 G22 G23 G24 G25 G26 F22 F23
IS25
00 01 02 03 04 05 06 07 XIO_A 08 09 10 11 12 13 14 15
XIO-D00 XIO-D01 XIO-D02 XIO-D03 XIO-D04 XIO-D05 XIO-D06 XIO-D07 XIO-D08 XIO-D09 XIO-D10 XIO-D11
XIO
B22 OE_ C22 WE_
XIO-OEn XIO-WEn
CLK_BURST CE1_ CE2_ NAND RDY2 RDY1 WP_
INPACK XIO-D14 XIO-D15
B21 E21 D21 A20 F21 A21
IS26
INPACK
3S15 10K
+3V3 NAND-CE1n
NAND-RDY1n NAND-WPn
9S08
10K RES
NAND-ALE NAND-CLE
D25 D26 C24 D23 C23 B23 A22 E22 F24 F25 F26 E23 E24 E25 E26 D24
00 01 02 03 04 05 06 07 XIO_D 08 09 10 11 12 13 14 15
3S1V
FLASH
10K
+3V3
Non CI * 3S1W
B05F
+3V3
J22
CA-DATADIR
K25 K26
CA-DATAENn
3S03
CA-MICLK
N23 10R L25
CA-MOCLK
N24 3S31 CA-MIVAL 33R
CA-MOSTRT
N25 L22 L23
CA-MOVAL
J21 CA-RDY
L24
CA-RST
L26 J23
RES 9S01
CA-MISTRT
J24
CA-MDO0 CA-MDO1 CA-MDO2 CA-MDO3 CA-MDO4 CA-MDO5 CA-MDO6 CA-MDO7
XIO-D00 XIO-D01 XIO-D02 XIO-D03 XIO-D04 XIO-D05 XIO-D06 XIO-D07 NAND-CE1n NAND-CLE NAND-ALE
ADD_EN DATA_DIR
VS
K23 1 K24 2
CD
K21 1 K22 2
DATA_EN I MCLK O
37
100n
VCC
N26 M21 M22 M23 M24 M25 M26 L21
9S00
CA-VS1n CA-MOCLK
3S0A-1 1 3S0A-3 3 3S0B-1 1 3S0B-3 3
3S0C-2 2 +3V3
XIO-OEn XIO-WEn NAND-WPn
CA-CD1n CA-CD2n
CA
3S0D 3S0C-4 4
100R 3S0A-2 6 100R 3S0A-4 8 100R 3S0B-2 6 100R 3S0B-4
2
7
100R 100R
4
5
2
7
100R
4
5
100R IS0A
6
100R
8
100R
7 100R 3S0C-3 3 10K 3S0C-1 1 5 100R
16 17 9 8 18 19 6 7
IS0B 3S0F
+3V3
+3V3
29 30 31 32 41 42 43 44
8
2K2 NAND-RDY1n
MISTRT MIVAL MOSTRT MOVAL OOB_EN
TS-CHDEC-DATA
3S1R
560R
TS-CHDEC-CLK
3S1S
560R
TS-CHDEC-VALID
3S1T
560R
TS-CHDEC-SOP
3S1U
560R
TS-CHDEC-DATA
3S23
470R
0 1 2 3 IO 4 5 6 7 CLE ALE CE_ RE WE WP SE R B
NC
IS0C
* Non DVBS / T2 / LATAM * Non DVBS / T2 / LATAM
1 2 3 4 5 10 11 14 15 20 21 22 23 24 25 26 27 28 33 34 35 38 39 40 45 46 47 48
RDY RST VCCEN VPPEN
T21 DATA T23 ERR T22 TNR_SER1 MICLK R23 MIVAL R22 SOP
TS-CHDEC-DATA TS-FE-ERR
TS-CHDEC-CLK TS-CHDEC-VALID TS-CHDEC-SOP
TS-CHDEC-CLK
3S24
470R
TS-CHDEC-VALID
RES 3S28
470R
TS-CHDEC-SOP
RES 3S29
470R
VSS
DVBS / T2 / LATAM * DVBS * / T2 / LATAM
100n
7S02 5
33R
+3V3
0 1 2 3 MDO 4 5 6 7
36
CA-ADDENn
VIDEO_STREAM
0 1 2 3 MDI 4 5 6 7
13
P21 P22 P23 P24 P25 P26 N21 N22
10K
7 3S01-2 2 3 33R 33R 5 3S02-4 4 7 3S02-2 2 33R 33R 8 3S02-1 1 6 3 33R 3S02-3 33R 5 3S01-4 4 33R
3S0G
1
+3V3
3S01-1 8 33R 3S01-3 6
CA-MDI0 CA-MDI1 CA-MDI2 CA-MDI3 CA-MDI4 CA-MDI5 CA-MDI6 CA-MDI7
7S0A H27U4G8F2D
12
7S00-11 PNX85500
10K
Non CI *3S1X
+3V3
100n 2S0B
2S0A
IS00
3S04 2S09
10-4-14
Q552.4E LA
1 4 2 3
74LVC1G08GW
PNX 85500 Nandflash conditional access
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2
2011-05-25
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Circuit Diagrams and PWB Layouts
10.
EN 144
PNX 85500: Common interface
PNX 85500: Common interface +3V3
TRANSPORT STREAM FROM CAM
+5VCA 2F01
22u 16V
+T
7F00 74LVC245A 1
0R3
19 3F02
CA-MOCLK CA-MOVAL CA-MOSTRT
100R 3F03-2 2
1
3F03-1
8 100R
7
CA-CD1n CA-CD2n
3EN1 3EN2 G3
CA-DATAENn 1
2
3 4 5 6 7 8 9
100R
RES
100n
2
18
MOCLK
17 16 15 14 13 12 11
MOVAL MOSTRT
CA-DATADIR
CA-ADDENn MOCLK MOVAL
10
MOSTRT
19
2
CA-MDO0
3F04-1 1
8 100R
IF05
3F04-3 3 3F05-1 1 3F05-3 3
3F04-2 6 100R 3F04-4 8 100R 3F05-2 6 100R 3F05-4
MDO4
2
1
IF06 CA-MDO1 CA-MDO2 CA-MDO3 CA-MDO4 CA-MDO5 CA-MDO6 CA-MDO7
MDO3
2
7 100R
4
5 100R
2
7 100R
4
5 100R
2
3 4 5 6 7 8 9
18
MDO0 MDO5
17 16 15 14 13 12 11
MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7
MDO6 MDO7
10
CA-WAITn +3V3
CA-INPACKn 2F03
15-BIT ADDRESS 3EN1 3EN2 G3 18
XIO-A01 XIO-A02 XIO-A03 XIO-A04 XIO-A05 XIO-A06 XIO-A07
17 16 15 14 13 12 11
1 2
CA-VS1n
1 19
CA-ADDENn
2
CA-A00
3 4 5 6 7 8 9
CA-A01 CA-A02 CA-A03 CA-A04 CA-A05 CA-A06 CA-A07
10
XIO-A00
CA-WP
100n
20
7F02 74LVC245A
RES
XIO-A09 XIO-A10 XIO-A11 XIO-A12 XIO-A13 XIO-A14
17 16 15 14 13 12 11
20 1 2
1 19
CA-ADDENn
2
CA-A08
3 4 5 6 7 8 9
CA-A09 CA-A10 CA-A11 CA-A12 CA-A13 CA-A14
10
18
RES
100n
3EN1 3EN2 G3 XIO-A08
+3V3 2F05
8-BIT DATA 3EN1 3EN2 G3 18
XIO-D01 XIO-D02 XIO-D03 XIO-D04 XIO-D05 XIO-D06 XIO-D07
17 16 15 14 13 12 11
1 2
1
CA-DATADIR
19
CA-DATAENn
2
CA-D00
3 4 5 6 7 8 9
CA-D01 CA-D02 CA-D03 CA-D04 CA-D05 CA-D06 CA-D07
10
XIO-D00
RES
100n
20
7F04 74LVC245A
+3V3 2F06
CONTROL
1X06 REF EMC HOLE
1X05 REF EMC HOLE
3EN1 3EN2 G3
1X04 EMC HOLE XIO-D11
18
XIO-D09 XIO-D08 XIO-OEn XIO-WEn XIO-D14 XIO-D15 CA-WAITn
17 16 15 14 13 12 11
1 2
1 19
CA-ADDENn
2
CA-REGn
3 4 5 6 7 8 9
CA-CE1n CA-CE2n CA-OEn CA-WEn CA-IORDn CA-IOWRn XIO-D10
8 10K 7 10K 3 3F10-3 6 10K 3F10-4 4 5 10K 2
3F10-2
3F12 10K 7 10K 3F11-3 3 6 10K 3F11-4 4 5 10K 3F11-1 8 1 10K 2
+3V3
+3V3
3F11-2
IF08
+5VCA
+3V3
1P00
CA-MIVAL CA-MICLK CA-A12 CA-A07 CA-A06 CA-A05 CA-A04 CA-A03 CA-A02 CA-A01 CA-A00 CA-D00 CA-D01 CA-D02 CA-WP
CA-CD1n MDO3 MDO4 MDO5 MDO6 MDO7 CA-CE2n CA-VS1n CA-IORDn CA-IOWRn CA-MISTRT CA-MDI0 CA-MDI1 CA-MDI2 CA-MDI3 +5VCA CA-MDI4 CA-MDI5 CA-MDI6 CA-MDI7 MOCLK CA-RST CA-WAITn CA-INPACKn CA-REGn MOVAL MOSTRT MDO0 MDO1 MDO2 CA-CD2n 71 72
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
MPC-20-5V-PBT-BRF-V0
PNX 85500 Common interface
10
1X02 REF EMC HOLE
100n
20
7F05 74LVC245A
IF04
3F10-1
+5VCA 2F04
1X01 REF EMC HOLE
1
3F09-2
CA-D03 CA-D04 CA-D05 CA-D06 CA-D07 CA-CE1n CA-A10 CA-OEn CA-A11 CA-A09 CA-A08 CA-A13 CA-A14 CA-WEn CA-RDY
+3V3
7F03 74LVC245A
+3V3
3F09-1
8 10K 7 10K 3F09-3 3 6 10K 3F09-4 4 5 10K
CA-RDY
IF07
3F07-4
3F07-2
1 3F08-1 8 10K 3F08-2 2 7 10K 3F08-3 3 6 10K 4 3F08-4 5 10K 1
MDO2
3EN1 3EN2 G3
B05G 100K
5 10K 7 10K 3F07-3 3 6 10K 3F07-1 1 8 10K
MDO1 RES
100n
20
7F01 74LVC245A 1
4
2
MDO0 +3V3 2F02
3F06
CA-RST
10K
+5V
2F00
10K RES 3F14
3F01
RES 3F13
B05G
20
10-4-15
Q552.4E LA
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2011-05-25
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Circuit Diagrams and PWB Layouts
10.
EN 145
PNX 85500: Audio
PNX 85500: Audio
B05H +2V5-AUDIO
3S53-1 100R
+3V3
3S53-2
OUT BP
IN INH
1 3
IS13
COM
1u0
4S14
+2V5
2S2S
100R
4
2S34
2S2V
22K
5 IS12
10u RES
FS08
2
100R 3S53-4
7 10K
7
1u0
2S2T
AUDIO-IN1-R
2
IS1J
2 3S12-2
3S16-2
3S53-3
100n
22K
2S2W
10u
8
1u0 RES
100R
1 3S16-1 8 10K
IS1H
3S12-1
7S08 LD3985M25
2S2R
1 AUDIO-IN1-L
6 10K
2S30
22K
3S17-2
2
7 10K
100u 4V
1u0
2S41
3S34 3S35
33R 33R
ADAC(3) ADAC(4)
AD4 OSCLK AD1 SCK AD2 WS
3S36 3S37 3S38
10R 10R 10R
SCKI2SOUT I2SCLK WSI2SOUT
AE1 1 AF2 VREF_AADC 2 AE3 I2S_OUT_SD 3 AF3 AC8 VCOM_AADC 4
3S39
10R
SDI2SOUT1
1 2 3 ADAC 4 5 6
AD9 L AIN4 AC9 R
2S32
7 1u0 3S10 100R
2S2L IS1B
1u0
IS19
AD7 AE7 AF7 AD6 AE6 AF6
AE9 L AIN3 AF9 R
1u0
AF8 L AIN5 AE8 R
I2S_OUT AB9 POS VR_AADC AB8 NEG AD8
AE5
SPDIF_OUT SPDIF_IN1
1n0
DBS8
1n0 2S38
AF5
56R
10K 2S35
3S3F
3S32
IS1A
+3V3 +3V3-ARC
3S11
IS1L
2S3Q
1R0
3S6N
14
7S09-1 74LVC00APW 1
SPDIF-OUT-PNX
&
SPDIF-OPT
47R
3 2 +3V3
7
+3V3
+3V3-ARC
IS1C
6
14
+3V3-ARC 7S09-3 74LVC00APW 9
&
& 8
5 10
2S3L
180R
100n
3S6M
IS1K
2S3M
IS44 eHDMI+
100n 68R
3S25
7
+3V3
+3V3-ARC 7S09-4 74LVC00APW 12
14
SEL-HDMI-ARC
7S09-2 74LVC00APW 4
& 11
+3V3
13 7
SPDIF-OUT-PNX
14
IS1Q
3S13-2 22K
2S33
100n
2
8 10K
8
10u 2S3G
AUDIO-IN4-R
22K
3S17-1
100n 2S3H
1
1
IS1P
3S13-1
AUDIO-IN4-L
1u0
AC6 P AB6 ADACR N
AD10 L AIN2 AC10 R
1u0
7
IS1R
3 3S17-3
2S36
AUDIO AE10 AC7 L P AB7 AIN1 ADACL AF10 R N
1u0
100n
6
7S00-2 PNX85500
2S31
10K
3S13-3
3
5 10K
3S19
AUDIO-IN3-R
22K
3S17-4
5
9S06 RES
4
4
IS0R
3S13-4 AUDIO-IN3-L
4R7 2S42
3S51
IS1M
10u 2S3N
B05H
2S3F
10-4-16
Q552.4E LA
PNX 85500 Audio
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2011-05-25
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Circuit Diagrams and PWB Layouts
10.
EN 146
PNX 85500: Headphone
PNX 85500: Headphone
B05I
+3V3-STANDBY
4 7NN2-2 PUMD12
6 5 2
RESET-AUDIO
7NN2-1 PUMD12 1
RESET-HP 3
2NN0 47p
3NN1-2
4 3NN1-4 5
2
7
22K 1
22K
3NN1-1
3NN1-3 8
6
3
22K 2NN5
22K
VO
1u0
INN6
3
2
7 4V 100u
INN8
2
3NN2-2
22n
2NN8
6NN8
1NN8
1K0
1NN2 MSJ-035-12D-B-AG-PBT-BRF 2 3 1
FNN2 7
AMP2
AMP2
33R
BYPASS
1 3NN2-1 8
GND
33R
22n
2NN2
SHUTDOWN
AMP1
2NN9
5
3NN5-1
8 4V 100u 2NN7
INN5
FNN1
33R
CDS4C12GTA 12V
5 10K
4 3NN2-4 5
CDS4C12GTA 12V
4
2
INN7
RES
3NN0-4
6
1
IN-
2NN6
6NN9
7 10K
33R 1
RES
2
1
VDD
AMPLIFIER
1NN9
3NN0-2
2
1
8 10K
5
1
1K0
1u0
3NN0-1
4
RESET-HP
2NN4
1u0
4
ADAC(4)
2NN3
3NN5-4
Φ
ADAC(3)
AMP1
3 3NN2-3 6
8
7NN1 TS489IST
100n
2NN1
47p +3V3
22K
B05I
RES 3NN6
10-4-17
Q552.4E LA
FNN7
PNX 85500 Headphone
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Circuit Diagrams and PWB Layouts 10-4-18
Q552.4E LA
10.
EN 147
PNX 85500: Video out - LVDS
B05J
PNX 85500: Video out - LVDS
B05J
7S00-7 PNX85500 PX1APX1A+
A7 B7
PX1BPX1B+
C8 B8
PX1CLKPX1CLK+
3S91 3S92
22R 22R
N A P
LVDS
N B P
C10 N CLK B10 P
A
N P
B
N P
CLK
D7 E7
PX3APX3A+
E8 D8
PX3BPX3B+
E10 N D10 P
3S95 3S96
22R 22R
PX3CLKPX3CLK+
C
N P
D9 E9
PX3CPX3C+
N D P
D
D11 N E11 P
PX3DPX3D+
PX1EPX1E+
C12 N E B12 P
E
E12 N D12 P
PX3EPX3E+
PX2APX2A+
A14 B14
N A P
A
D14 N E14 P
PX4APX4A+
PX2BPX2B+
C15 N B B15 P
B
E15 N D15 P
PX4BPX4B+
CLK
E17 N D17 P
N C P
C
D16 N E16 P
PX4CPX4C+
N D P
D
D18 N E18 P
PX4DPX4D+
E
E19 N D19 P
PX4EPX4E+
PX1CPX1C+
A9 B9
PX1DPX1D+
A11 B11
PX2CLKPX2CLK+
3S93 3S94
22R 22R
N C P
LOUT1 LOUT3
C17 N B17 CLK P LOUT2 LOUT4
PX2CPX2C+
A16 B16
PX2DPX2D+
A18 B18
PX2EPX2E+
C19 B19 N E P
3S97 3S98
22R 22R
PX4CLKPX4CLK+
PNX 85500 Video out - LVDS
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2011-05-25
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Circuit Diagrams and PWB Layouts
10.
EN 148
PNX 85500: Analog video
PNX 85500: Analog video
B05K 2S87
AV1-CVBS
2S8A
47R
Y-SVHS
47R
22n
3S5B
3S59
22n
Connectivity
56R
B05K
3S05
10-4-19
Q552.4E LA
2S7J
AV1-R
2S22
56R
3S4J
22n
C-SVHS 22n
EU: SCART1
CVBS-MON-OUT1 22n
560R
3S5F
2S7K
AV1-B
56R
-
3S4L
AP:
3S08
560R
47p
2S7H
2S40
IS4V
22n
8K2
IS4W
3S09
56R
3S4K
AV1-G
2S7M
YPBPR1-SYNCIN1
10n 2S7L
56R
3S4P
AV3-Y 22n
2S7N 22n 7S00-1 PNX85500
AF15 AE15 AC15 AD15 AB14 AF14 AE14 AC14 AD14 AF16 AD16 AE16 AB18 AC18 AF4 AD24 AD25
2S15 22n
2S14
AC12 AF13
2S16 22n
CVBS_Y1 ATV_CVBS_Y3 R C3 B AV1 G CVBS_Y7 C7 SYNCIN1 Y_G1 CVBS1_OUT PR_R_C1 CVBS2_OUT PB_B1 RESREF CVBS_Y2 CURREF SYNCIN2 Y_G2 1 PR_R_C2 2 PB_B2 3 REF 4 R 5 G VGA 6 B HSYNC_IN IF_AGC RF_AGC IN VSYNC OUT P SCL VGA_EDID TUNER N SDA
22n
AB15 AC13 AD13 AE13
2S18 22n
22n
22n
56R
3S4T
AV3-PB
2S19
ANALOG_VIDEO
2S7P
AD11 AC11 AF11 AE11 AB10 AA11 AC16 AB16 AB13 AB12 AA12 AA10 AD12 AB11 AE12 AF12
FS13
IS5E
3S5S 10K
IS5D IS5F IS5G IS5H IS5J
3S75 FS15
SOC-IF-AGC
10K
10n
YPBPR1
2S75
3S4R
AP:
YPBPR1
56R
AV3-PR
EU:
BS10
AA14
AGND
3S4V
10n
100R
SOC-IF-P
680R
3S4U
2S77
2S78
3S4W
10n
100R
SOC-IF-N
2S84
56R
3S50
R-VGA
22n
2S85
56R
3S52
G-VGA 22n
2S86
3
V-SYNC-VGA
7 100R
3S5V-2 2
5 100R
3S5V-4
7 100R
8
4
100R 3S5T-3
2
3S5T-1
100R
1
H-SYNC-VGA
4
AP: VGA
3S5T-4
5
22n
3S5T-2
EU: VGA
56R
3S54
B-VGA
6
100R VGA-SCL-EDID
RES
3
3S5V-3
6
100R VGA-SDA-EDID
RES
1
3S5V-1
8
PNX 85500 Analog video
100R
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2
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Circuit Diagrams and PWB Layouts
10.
EN 149
PNX 85500: Analogue externals A
PNX 85500: Analogue externals A
FNA2
FN71
2N88
1n0
2N91
1n0
1K0
100p
2N14
RES
5K6
10K
IN51
18K
BC847BPN(COL)
820R
10u
CVBS-MON-OUT1 18p
5N80 2N98
2u2
1 3N19
3NB1
IN59 39p
2N81
2N97
IN70 2
IN60
AV2-BLK
4p7
6 7N06-1 3 BC847BPN(COL)
4K7
3N73 39K
1u0
2N99
5
IN96
1
100n
2N74
100p
2N12
1N19
150p
3N18
7N06-2
FN81 CDS4C12GTA 12V
18R
2NB3
IN61
4
+5V
RES 6N28
1u8
2N86
2N85
AV1-R
3N79
3N06
1K0
3NA1
IN89 IN13
18R 5N76
+3V3
FN85
3N78
FNA6
3N17
1R0
3NA2
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
330R
150p
RES
1N18
18R
FN80
RES 6N26
1u8
2N84
150p
2N83
3N77
100p
RES 6N22
4K7
3N32 3N76 18R
2N18
FN75
12K
5N74
100p
FN74
3N31
1N55
AV1-STATUS
FNA5
2N15
FN73 IN18
IN90
3NB3
RES
1VA1 49045-0011 25 26 1N12
150p
2N80
150p
2N79
18R
CDS4C12GTA 12V
3N75
* EU
100n
FNA1
1u8
CDS4C12GTA 12V
5N73
RES 6N23
FNA4
IN05
2NB1
3N74 18R
AV2-STATUS +5V
9N01
6N09 RES
100p
2N04
FNA3
AV1-G
1N31
3N03
AUDIO-IN1-L
AV1-B
1N54
RES 6N03
100p
2N06
1K0
CDS4C12GTA 12V
3N02
CDS4C12GTA 12V
AUDIO-IN1-R
B05L
CDS4C12GTA 12V
B05L
150p
3NB6-1 IN91 8 470R
3NB6-2
7
6
CVBS-OUT-SC1
4
470R
3NB6-4
100n
2N24
3N44
3NB6-3
3N45 68R
5
470R 3
IN92
7N05 BC847BW 470R
2
+3V3
4K7
RES 3N48 3
68R 3N42
100p
*
RES 2N75
RES 5N77
FNA8
3N62 FN84
CVBS-OUT-SC1
1N25
27R 150p
RES 6N32
2N45
1u8
2N44
AV1-CVBS
1N22
4K7
CDS4C12GTA 12V
FN82
CDS4C12GTA 12V
1
3N43
7N03 BC847BW 2
6N29
FNA7
75R
AV1-BLK
150p
100p
RES 2N76
1N23
12V
CDS4C12GTA
FN83 RES 6N30
10-4-20
Q552.4E LA
DEBUG PNX 85500 Analogue externals A
3139 123 6533
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2012-04-23
3
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2
2011-05-25
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2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 150
PNX 85500: Analogue externals B
PNX 85500: Analogue externals B
YPBPR 5 4 3
FN51 CDS4C12GTA 12V
RES 6N51
FN42
MSJ-035-75C-G-RF-PBT-BRF
3N89
100p 1N28
2 1
2N67
1VA8
FN5B
FN5A
18R
CDS4C12GTA 12V
RES 6N40
3N87
100p 1N43
B05M
AV3-PR
AV3-PB
18R
FN54
2N27
FN5C
18R
CDS4C12GTA 12V
RES 6N52
3N90
100p 1N39
2N68
FN48
AV3-Y YPBPR1-SYNCIN1
CVBS & AUDIO 5 4 3 CDS4C12GTA 12V
VGA ( OR DVI ) AUDIO
2N71
CDS4C12GTA 12V
100p 100p
IN10
100p
IN09 AUDIO-IN4-L
100p
1K0 2N35
CDS4C12GTA 12V
3N21
RES 6N19
V_NOM
1n0 1N37
2N36
FN02
AUDIO-IN4-R
1K0 2N38
CDS4C12GTA 12V
RES 6N20
2N37
MSJ-035-75C-BL-RF-PBT-BRF
V_NOM
3N20
2 1
AUDIO-IN3-L
1K0
FN01
1n0 1N38
5 4 3
FN5G
3N96
RES 6N38
1n0 1N42
2N40
FN49
AUDIO-IN3-R
1K0 2N72
RES 6N06
FN43
MSJ-035-75C-Y-RF-PBT-BRF
1n0 1N29
2 1
FN03
1N10 3150-831-030-H1 2 VCC
FN55
1
SPDIF-OPT
CDS4C12GTA 12V
RES 6N53
V_NOM
3
100p 1N80
GND MT 5 4
FN5H
100n
VIN
1R0
+3V3
RES 2N77
1N09
FN5D
3N97 FN50 2N39
1VA4
3N9C
B05M
2N73
10-4-21
Q552.4E LA
PNX 85500 Analogue externals B
3139 123 6533
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3
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2
2011-05-25
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div. table
Circuit Diagrams and PWB Layouts
10.
EN 151
PNX 85500: VGA
PNX 85500: VGA
B05N
FFC1 CDS4C12GTA 12V
RES 6FC1
1FC1
100p
RES 2FC1
3FC5
CDS4C12GTA 12V
RES 6FC2
1FC2
100p
G-VGA
18R
1FC3
RES 6FC3
FFC4
100p
RES 2FC3
FFC3
CDS4C12GTA 12V
3FC7
9FC5
H-SYNC-VGA
9FC6
V-SYNC-VGA
4K7
3FC3
CDS4C12GTA 12V
RES 6FC4
1FC4
FFC6 MDS-15P-V-11-B-8.2-U4-ZN-PBT-BRF
B-VGA
18R
FFC5
47p
CDS4C12GTA 12V
RES 6FC6
47p
2FC6
10K
FFC9
RES 6FC7
47p
2FC7
10K
CDS4C12GTA 12V
RES 3FC2
4K7
3FC4
CDS4C12GTA 12V
RES 6FC5
1FC5
FFC8
9FC1
VGA-SDA-EDID-HDMI
9FC2 RES
VGA-SDA-EDID
9FC3
VGA-SCL-EDID-HDMI
9FC4 RES
VGA-SCL-EDID
1FC6
+5V-VGA CDS4C12GTA 12V
RES 3FC1
47p
2FC5
FFC7
RES 6FC8
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
2FC4
VGA CONNECTOR
3FC6
RES 2FC2
1N05
R-VGA
18R
FFC2
47p
B05N
2FC8
10-4-22
Q552.4E LA
PNX 85500 VGA
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2
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Circuit Diagrams and PWB Layouts
10.
EN 152
PNX 85500: Temperature sensor
PNX 85500: Temperature sensor
B05O
47R
2
SCL
A2
1K0
3USG
9USB RES
9USA RES
IUSB
6
IUSC
5
1K0
3USC
A1
IUSA
9USC RES
SCL-SSB-550
SDA
7
1K0 3USF
1
A0
3USD
47R
GND
3USB
4
SDA-SSB-550
OS
+VS
7USA LM75BDP 3
100n
8
2USA
1K0 LTST-C190KGKT
RES
RES 3USA
+3V3
6USA
B05O
For DEV Use Only
10-4-23
Q552.4E LA
PNX 85500 Temperature sensor
3139 123 6533
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2012-04-23
3
2011-12-12
2
2011-05-25
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Circuit Diagrams and PWB Layouts
10.
EN 153
PNX 85500: Vdisp-switch
PNX 85500: Vdisp-switch
B05P
*8 *7 *6 *5 *8 *7 *6 *5
3
IUU0
7UU2-1 PUMD12 1
10K
1 IUU2
220n 3UU3-1
8
22u
47K RES 3
1
IUU4 3UU3-3 IUU5 3UU3-4 4 5 6 3 47K RES
2
FUU1
VDISP-SWITCH
LTST-C190KGKT
IUU3 7UU3 RES BC847BW
22K
2
IUU1
RES 2UU5
1u0
RES 3UU9
*
+3V3-STANDBY
47R 3UU6 47K
6 3UU5
3UU1
2K2
FOR DEVELOPMENT USE ONLY
3UU2
+3V3
47K RES
RES 100n
5
1n0
2
47K 2UU1
6UU1
3UU4
2UU0
4 PUMD12 7UU2-2
3
7
RES 2UU4
RES 2UU3
4 RES 3UU3-2
+VDISP T 2.0A 63V
22n
+12VD
FUU2
1UU0
6 5 2 1
2UU2
RES 7UU1 SI3441BDV
47R
7UU0 SI4835DDY
FUU0
RES 3UU8
1 9UU0-1 RES 2 9UU0-2 RES 3 9UU0-3 RES 4 9UU0-4 RES 1 9UU1-1 RES 2 9UU1-2 RES 3 9UU1-3 RES 4 9UU1-4 RES
47K
B05P
3UU7
10-4-24
Q552.4E LA
+3V3
4K7 RES
9UU2
LCD-PWR-ONn LCD-PWR-ON-FPGAn DONE-LX25
*
9UU3
3
3 RES 7UU4 PDTC114EU
1
RES 7UU5 PDTC114EU
1 2
2
4
PNX 85500 Vdisp-switch
3139 123 6533
2012-04-23
3
2011-12-12
2
2011-05-25
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Circuit Diagrams and PWB Layouts 10-4-25
Q552.4E LA
10.
EN 154
Class-D amplifier
Class-D amplifier
B06A
B06A 7D80 SI2304
FD34 +3V3-AUDIO
+3V3-STANDBY
3D83
6D61
2D39
1K0
PDZ2.7B(COL)
1n0
30R
5D51
3D80
*
+3V3 30R SPEAKER-R-
31
3D81
10K
100u 16V
10n
2D78
220n
220n 2D71
RES 2D56
10n 2D70
2D98
10n
1 2 3
SUB-
FD95
1D51
1D50
2041145-3 1D52
10n
RES 2D76
30R
10n 5D81
RES 2D73
3 RES 5D72 4 30R 2041145-4
SPEAKER-R-
1D02 SUB+
2D87
30R
10n
RES 2D99 5D01
10u
1 RES 5D78 30R 2
SPEAKER-R+ 1D56
NC
VR_DIG
5D76
1D55
VR_ANA
5 7 40 41 44 45
FD33
1D01
10n
330p
PVDD_CD
2D5D
18R
3D73 ID92 18R
2D75
3D74 ID93
330p
2D94
34 35
27 DVDD
SSTIMER
VREG
VIA
30
50 51 52 53 54 55 56 57 58 59
30R
1D53
100n
ID80
18
FD32
5D71
PBTL
STEST
Left+ FD30 LeftRight+ Right-
FD31
1D54
ID79
1u0
SPEAKER-LSPEAKER-R+
VIA
60 61 62 63 64 65 66 67 68 69
ID53
5D79
RES 5D80 SPEAKER-R-
10u
30R
CD00
GND-PLL
30R
2D77
10u 100n
30R
10n 5D83
2D72 2D74
2D67
10u
RES 2D91
7D61 PDTC144EU
AUDIO-MUTE-UP
ID75
18K2 1%
SPEAKER-L-
10n
12
32
ID84 3D71
RES 5D75
2D81
26
16
5D74
220n
6
36
FD92
SPEAKER-L+
220n 2D55
ID70
GVDD_OUT
ID52
220n 2D83
2n2
OSC_RES
P PLL_FLT M
33n 33n
RES 2D89
2D54
ID61
8
OUT_D
42 33
18R
9D51
PDN
2D82 2D85
39
3D75
11 10
BST_C BST_D
ID62 ID63
ID51
46
ID94
47n 470R
ID66 4n7 470R ID69 47n 4n7
10K
1n0
3D82
7D50-1 PUMH2
DETECT2
2D50 3D51 2D52 2D53
30R
330p
ID65 2D51 3D52
RESET
33n 33n
2D95
+3V3D
5D00
10u
18R
19
OUT_C A_SEL
2D79 2D80
3D72
25
5D70
ID95
ID56
D-RESET
OUT_B
SDA SCL
ID81 ID82
330p
14
4 43
2D88
15K 15K
GND_HS
23 24
ID50
1
49
RES 3D76 3D77
+3V3D
47R 47R
BST_A BST_B
SDIN
37 38 PGND_CD
3D55 3D56
SDA-SSB-550 SCL-SSB-550
*
SPEAKER-L+
MCLK
47 48 PGND_AB
ID87
22
GND
15
DVSSO
FD66
FD50
SDI2SOUT1
29
7D50-2 PUMH2
BAT54 COL
6D60
47K
3D54
D-RESET
*
7D60 TAS5731PHP
OUT_A
17
SCKI2SOUT +3V3-STANDBY
SCLK
DVSS
RES 9D54
LRCLK
AVSS
10K
3D50
21
AGND
20 9D52 9D53
I2SCLK
9
FD67
WSI2SOUT RESET-AUDIO
AVDD
+3V3D
2 3
13
1R0
PVDD_AB
ID78 3D57 ID77
1R0
10K
5D85 RES 10K
2D5C
100u 16V
100n
*
3D58
28
2D5B
100u 16V
3D79
10K
*
+3V3-AUDIO 30R
+3V3D
*
2D5F
100n 2D69
SPEAKER-L-
10u 2D68
2D86
2D5A
100u 16V
3D78
10K
*
5D84 +3V3D
ID55
ID54
*
220n
2D64
47u 35V
+12V-AUDIO
30R 2D57
5D50
220n
2D60
47u 35V 2D61
+12V-AUDIO
3D84
+12V-AUDIO
5D77 30R
GND-PLL
2D57 2D60 3D83 6D61
+12V-AUDIO (5000 & 5500 series) 100uF 16V (2022 031 00538) 100uF 16V (2022 031 00538) 1K0 (3198 031 01020) BZX2V7 (3198 020 52780)
Speaker Configuration Active 2.1 (with Virtual Ground) Active 2.1 ( E-cap in speaker) Passive 2.1 2.0
*
1D02 Yes Yes Yes No
+24V-AUDIO (4500 series) 47uF 35V (2020 031 00753) 47uF 35V (2020 031 00753) 6K8 (3198 031 06820) BZX5V6 (3198 020 55680)
2D70 Yes Yes Yes No
2D87 Yes Yes Yes No
2D98 Yes Yes Yes No
2D55 Yes Yes No No
2D71 Yes Yes No No
2D83 Yes Yes No No
5D71 Yes Yes No No
5D77 Yes Yes No No
2D56 No No Yes Yes
2D73 No No Yes Yes
2D76 No No Yes Yes
2D89 No No Yes Yes
2D91 No No Yes Yes
2D99 No No Yes Yes
5D75 No No Yes Yes
5D80 No No Yes Yes
5D72 No No Yes No
5D78 No No Yes No
5D81 No Yes No No
5D83 No Yes No No
2D5A Yes No No No
2D5B Yes No No No
2D5C Yes No No No
2D5D Yes No No No
3D78 Yes No No No
3D79 Yes No No No
3D81 Yes No No No
3D81 Yes No No No
* Current Configuration
Class-D amplifier
3139 123 6533
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2012-04-23
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2011-05-25
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Circuit Diagrams and PWB Layouts
10.
EN 155
USB hub
USB hub
B06B
100n 2FLA
B06B
+3V3
+3V3
USB1 1P08
+5V-USB1
FL36 FL37
USB1-DM USB1-DP
100n
100n
2FL4
2FL1
3
25
10K
6 7 24
USB3-DM USB3-DP IFLH
USB-OVR3
IFLJ
12 13 20
IFLK
15 16 19
USB2-DM USB2-DP USB-OVR2 USB1-DM USB1-DP +3V3
10K 3FLD 3FLB 3FLC
3FLP
28 17 22 23 8
180R 1% RES 2FLF
47K
1u0 3FLM
2FLH
+3V3
IFLA 10K 100K 470R 1%
21
27 DD3DD3+ OVR3
TEST|SCL
USB-DM USB-DP
FL42
26
RES 3FLL
10K
18
RES 3FLN
10K
+3V3
30 31 32 33
FL43
+T 0R3
+5V-USB1
USB-OVR2
4
3FL4-4
5
100K 3 3FL4-3 6
6
FL33
* 100K *3 3FL8-3 6 4
+5V-USB2
USB-OVR3
3FL8-4
100K
100K
2 3F34-2 7
2 3FL4-2 7
*2 3FL8-2 7
100K 1 3F34-1 8
100K 1 3FL4-1 8
* 1 3FL8-1 8
100K
100K
3FL7
+T 0R3
+5V FL40
(WIFI)
3FLJ
RES
+T 0R3
FL38 FL39 FL30
USB-WIFI-DDn +5V-USB3
2
3
1
4 1F01 ACM2012
USB-WIFI-DDp
100K
2FLD
USB-OVR1
100K 3 3F34-3 6
*
+5V +5V
+T 0R3
*
+5V
3F32 3F34-4
2 3 4 5
USB-01-PBT-B-30-CU2-BRF
3FL2
4
FL44 FL45
FL46
VREG RESET SELFPWR GANG RREF
USB3
* *1 1P06
+5V-USB3
VIA1 VIA2 VIA3 VIA4
6
USB-16-PBT-B-30-CU1-BRF
USB3-DM USB3-DP
DD4DD4+ OVR4
100n
RESET-USBn
USB-OVR1
3FLF
10u 16V RES 2FLG
+3V3
SDA
DD2DD2+ OVR2
1 2
100K
FL31
3FLK
DD+
DD1DD1+ OVR1
100n
*
USB2-DM USB2-DP
1 2 3 4 5
29
+3V3
XOUT
FL47 FL41
100n
3 4
USB-WIFI-DDn USB-WIFI-DDp
XIN
+5V-USB2
2FLC
11
USB2 1P07
VCC_D
IFLG
5 VCC_A_1 9 VCC_A_2 14 VCC_A_3
10
GND_HS
IFL4
VCC
18p
2FL7
2FL6
12M 7FL5 CY7C65632-28LTXCT
6
100n
100n 2FL9
2FL2 100n
1u0
1u0 2FL8
1FL5
1 2 3 4 5
USB-16-PBT-B-30-CU1-BRF
2FLB
1
2FL5
FL32
18p
10-4-26
Q552.4E LA
*1 1C30 2 3 4 5 6
7
502386-0570
*
100K
*
ONLY FOR 6000
7FL5 5000 2 × USB
CY7C65634
6000 3 × USB + WIFI
CY7C65632
USB hub
3139 123 6533
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2012-04-23
3
2011-12-12
2
2011-05-25
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Circuit Diagrams and PWB Layouts
10.
EN 156
Ethernet & service
Ethernet & service
B06C
B06C IN07
5N08 +3V3
+3V3-ET-ANA
6N43 IN38
IN32
2 3 1
47R
1N06
UART SERVICE CONNECTOR
MSJ-035-69A-B-RF-PBT-BRF FN58
15 10K 10K
+3V3
ETH-TXEN
21
ETH-TXD(0) ETH-TXD(1) ETH-TXD(2)
22 23 24 25 18
ETH-TXD(3) ETH-TXER
17 16
ETH-MDC ETH-MDIO
100n
10u
2N49
2N48 RX
P N
TX
P N
1
RST 0 MODE 1 RMIISEL PHYAD2 RXD
TXCLK
ETH-TXP ETH-TXN
20
ETH-TXCLK ETH-RXDV
IN63 10K
IN64
7
3N34
10K
3N72
2
14
VIA VIA
VIA
+3V3
RES 3N68 RES 3N35 RES
34 35 36
ETH-RXCLK
10K
3
CRS
+3V3
RES
3N65
10K
7N10-2 LAN8710A-EZK
ETH-RXER
3N64
REGOFF 1 LED 2 INTSEL
0 1 2 TXD 3 4 INT TXER
29 28
13
RXER RXD4 0 PHYAD 1 RXCLK
TXEN
ETH-RXP ETH-RXN
26
RXDV
COL CRS_DV MODE2
31 30
43 44 45
IO
40 41 42
VIA ETH-REGOFF
10K
37 38 39
10K
1K5
FN57
5
+3V3 ETH-INTSEL
10K
9N42
+3V3 ETH-CRS
32
RBIAS
IN39
MDC MDIO
12K1 1%
19
1A 2A VDD
3N40
10p
RES 3N71 RES 3N80
VSS
+3V3
33
3N51
FN56
8
12
6
CLKIN 1 XTAL 2
27
5 4
11 10 9 8 3N70 RES
4n7
100n 2N53
2N52 10p
2N54
10p
10K 3N33
2N55
10K 10K 10K 10K
7N10-1 LAN8710A-EZK
CR
ETH-RXD(0) ETH-RXD(1) ETH-RXD(2) ETH-RXD(3)
ETH-COL
47R 3N53-4
25M
RES 2N70
3N69 RES 10K
3N53-1
IN33
1M0 1N70 NX3225GA
RES RES RES RES
3N66 3N67 3N81 3N82
3N30
IN26
4
3
47R
+3V3
+3V3
RESET-ETHERNETn
1
2
1N85
+3V3-ET-ANA
47R 3N53-3
1N86
6
RXD1-MIPS
3N53-2
PDZ5.1B(COL)
7
TXD1-MIPS
PDZ5.1B(COL) 6N44
100n
2N62
10u 2N63
100n 2N66
30R
+3V3-ET-ANA
CONFIGURATION RESISTOR SETTINGS
ETHERNET CONNECTOR
ETH-TXP
5N0C-1 E2101
1N87 3 ACM2012 2
FN27
16 RD+
1N00 RX+ 1
1 2 3 4 5 6 7 8
FN60 4
ETH-RXP
FN29
1N88 3 ACM2012 2
ETH-RXN
FN31
4
1
15 RDTC
RX- 3
FN61 5N0C-2 E2101 11 TD+
TX+ 6
10 TCT
TXCT 7
9 TD-
TX- 8
EMPTY
9 98435-111LF
3N64 (RES)
PHYADD(0) = 1
PHYADD(0) = 0
3N65 (RES)
PHYADD(1) = 1
PHYADD(1) = 0
3N66 (RES)
PHYADD(2) = 1
PHYADD(2) = 0
3N67 (RES)
RMII mode selected
MII mode selected
3N68 (RES)
Internal 1.2V reg. disabled Internal 1.2V reg. enabled
3N69 (RES)
MODE(0) = 0
MODE(0) = 1
3N70 (RES)
MODE(1) = 0
MODE(1) = 1
3N71 (RES)
MODE(2) = 0
MODE(2) = 1
INTERRUPT FUNCTION
INTERRUPT FUNCTION
DISABLED ON
ENABLED ON
FN34 IN0B
8 7 6 5
22R
22R 3N98
+3V3-ET-ANA
3N26
8 6N47-1 1
CDA5C16GTH 16V
7 6N47-2 2
CDA5C16GTH 16V RES
6 3
CDA5C16GTH 16V RES
4
6N47-3
5 RES
CDA5C16GTH 16V RES
1 6N47-4
RES 27n
Primary FN32
3N0A-1 3N0A-2 3N0A-3 3N0A-4
22n
2N60
1 2 3 4
FN30
15p
IN0A
3N72 Secondary
nINT/TXER/TXD4 SIGNAL nINT/TXER/TXD4 SIGNAL
2N0L 1n0
RES 15p RES 0 ohm RES 2N59
5N04 2N09 15p 3N39
RES 27n RES 15p 0 ohm
RES 2N58
RES
5N03 2N08 15p
3N29
5N02
RES 27n
2N07
RES 0 ohm RES 15p RES 2N57
15p
3N28
5N01
RES 27n
2N05 3N27
RXCT 2
14 RD-
75R 75R 75R 75R
FN28
ETH-TXN
POP
49R9 1%
3N99
49R9 1%
3N95
49R9 1%
3N25
49R9 1%
3N22
Resistor
RES 0 ohm RES 15p RES 2N56
10-4-27
Q552.4E LA
ETH-INTSEL ETH-REGOFF
FN33
Ethernet & service
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_057_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 157
HDMI
HDMI
B06D
AIN-5V
1u0
67 68
BRX2BRX1+
ARX1ARX1+
69 70
ARX2ARX2+
71 72
BIN-5V
47K
3NCA-2
7
10R
BRX-DDC-SDA BRX-DDC-SCL
6 100K 1u0
IN43
35 36 33 34
BRXCBRXC+
BIN-5V
BRX-HOTPLUG
1
20 22
47K
FNC8 FNCF
3NCA-1
8
BRX-DDC-SCL BRX-DDC-SDA
BIN-5V
HDMI CONNECTOR 1
2 3NCN-2 2NCP
3 3NCM-3 6
CIN-5V
10R
CRX1CRX0+
CIN-5V
100R
+3V3-STANDBY
4
DIN-5V
3NCM-4
9NC0
BRX2BRX2+
7 8
7 100K 1u0
IN44
CRXCCRXC+ CRX0CRX0+
13 14
CRX1CRX1+
15 16
CRX2CRX2+
17 18
8 100K 1u0
IN45
2
INC6 CEC-HDMI 4
DDCA-SCL
3NCU-2 10K 3NCU-4
7
45 46 43 44
10p
2NCC
30R
ARC-eHDMI+
2
41 42
11 12
5NC2
DDCA-SDA 1 INC5
5
eHDMI+
CIN-5V
INC4
1 3NCN-1 2NCQ
10R
22K RES
7NC0 BC847BW
3NCD
47K
3NCA-4
3N23 RES 7N02 BC847BW
5 6
DRX-DDC-SDA DRX-DDC-SCL
47K
CRX-HOTPLUG
20 22
PCEC-HDMI
3NCA-3
CIN-5V
3
FNCM FNCN
BRX1BRX1+
DRX-HOTPLUG
CRX-DDC-SCL CRX-DDC-SDA 6
FNCK FNCL
5
CRXCPCEC-HDMI ARC-eHDMI+ CRX-DDC-SCL CRX-DDC-SDA
4
CRX0CRXC+
FNCA
3 4
39 40
CRX2CRX1+
FNCJ
BRX0BRX0+
CRX-DDC-SDA CRX-DDC-SCL
CRX2+
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 23
1 2
CRX-HOTPLUG
1P02
10K
1u0
3NCH
2NC2
+3V3
5
DRXCDRXC+
19 20
DRX0DRX0+
21 22
DRX1DRX1+
23 24
DRX2DRX2+
25 26
100n
2NC3
CEC_D
100n
10K RES 2NCZ
6 3
1
49
10K 3NCP-3
3NCP-1
8
DSCL4 DSDA4
N R0X0 P
10u
RES 2NCW 38
37
R4PWR5V
N R0XC P
48 47
VGA-SCL-EDID-HDMI VGA-SDA-EDID-HDMI
51
9NC2
CEC-HDMI
RES
N R0X1 P N R0X2 P (CBUS) HPD1 R1PWR5V DSDA1 DSCL1
TX2
N P
TX1
N P
TX0
N R1XC P
TXC
N R1X0 P
N P N P
57 56
HDMIA-RX2HDMIA-RX2+
59 58
HDMIA-RX1HDMIA-RX1+
61 60
HDMIA-RX0HDMIA-RX0+
63 62
HDMIA-RXCHDMIA-RXC+ 3NCJ RES
N R1X1 P
TPWR_CI2CA
N R1X2 P
CEC_A
4K7
55
3NCK
MICOM-VCC33
4K7
(CBUS) HPD2 R2PWR5V
INT
50
52
FNCR
9NC3 RES
FNCY
PCEC-HDMI 3NCL RES
+3V3
4K7
DSDA2 DSCL2 N R2XC P
CSCL CSDA
N R2X0 P RSVDL
N R2X1 P
54 53
10 28
N R2X2 P (CBUS) HPD3 R3PWR5V DSDA3 DSCL3 N R3XC P VIA
N R3X0 P N R3X1 P N R3X2 P
3NC3 3NC5
47R 47R
SCL-SSB-550 SDA-SSB-550
74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89
10K 73
EPAD INC7
IN11
FNCZ
100K
2NCU 1u0
DRX2DRX1+ DIN-5V
DRX1DRX0+ DRX0DRXC+
8
BAT54 COL
DRX2+
DRXCPCEC-HDMI FNC9 FNCH FNCQ FNCU
DRX-DDC-SCL DRX-DDC-SDA
47K
+5V-VGA
+5V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FNCV 21 23
3NCT-1
6NC1
3NCF
FNCW
1P05 +3V3-STANDBY
1
22K
HDMI CONNECTOR SIDE 3NCR
FNCP
3NCM-2
3 3NCN-3 2NCN
DSDA0 DSCL0
+5V-EDID
7
BRXCPCEC-HDMI
2
BIN-5V
2
BRX0BRXC+
(CBUS) HPD0 R0PWR5V
10p
BRX2+
ARX0ARX0+
AIN-5V
BRX-DDC-SCL BRX-DDC-SDA
+3V3
30R
10p RES 2NCY
29 30
ARX-DDC-SDA ARX-DDC-SCL
1
31 32
BRX-HOTPLUG
FNCC FNCD
5NC3 RES
RES 2NCX
IN42
SBVCC33
8
10R
5 100K 1u0
MICOM_VCC33
1
AIN-5V
4 3NCN-4 2NCM
65 66
BRX1BRX0+
100n VCC33
3NCM-1
ARXCARXC+
HDMI CONNECTOR 2
9 27 64
7NC1 SII9287B ARX-HOTPLUG
8 ARX-HOTPLUG
100n 2NC8
100n 2NC7
2NC6
Reserved
47266-9002
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FNCG 21 23
10u
FNCB
INC8
47K
3NC1-1
AIN-5V
20 22
1P03
SII9187B = 0xB2
GND
ARX-DDC-SCL ARX-DDC-SDA
FNC4 FNC5
1
100n
VOUT
30R
2NCV
2NC4
EN EN
+3V3
2K2
3NC7
3 47K
3NC1-3 6
ARXCPCEC-HDMI ARX-DDC-SCL ARX-DDC-SDA
4
3
+3V3-HDMI
ARX0ARXC+
FNC1 FNC2
FNCT
FLG
MICOM-VCC33
2
ARX1ARX0+
3K3
RES 3NC6
ARX2ARX1+
6NC2
ARX2+
PDZ2.4B(COL)
1P04
VIN
FNC3
FNC0 2NC0
5
5NC0
100u 16V
FNCS
HDMI CONNECTOR 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FNC6 21 23
I2C Address
7NC2 RT9715EGB
RES 2NC1
+5V
30R
5NC4
+3V3
4R7
B06D
3NCG
10-4-28
Q552.4E LA
DRX-DDC-SCL DRX-DDC-SDA
2 3NCT-2 7
DIN-5V
47K DIN-5V
DRX-HOTPLUG
20 22
HDMI
+5V-EDID
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_058_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 158
FPGA, power & control
FPGA, power & control
B07A
B07A
5J20 +3V3
FJ21
30R
1
3J21
DBG
+3V3
470R
7J25 PDTC144EU 2 DBG
220n
2u2 2J27
DBG
LTST-C190KGKT
RES
2u2 2J26
2u2 2J25
2u2 2J24
2u2 2J23
2J22
2u2
RES 2J21
6J21
3
VAUX DONE
7J20 LD1117DT12 MISO
FJ22
2
VCCINT
+3V3 FJ26
2J2K
RES 4K7
5J21
FJ23
1 2 3 4 5 6
220n
220n 2J41
220n 2J40
2u2 2J39
1J22
VCCO3
RES
2u2 2J38
30R 2J37
+3V3
CCLK CSO-B MOSI MISO PROG-B 7
MOSI CCLK CSO-B
7J21 M25P40-VMN6
*
8
3J23
220n
220n 2J36
2u2 2J35
2u2 2J34
2u2 2J33
2J32
22u
22u 2J31
2J30
10u
2J29
1
2J28
COM
VCC
FJ27
5
FJ28 FJ29
IJ22 Q
2
C
1
S HOLD
3
8
Φ
D
6
100n
OUT
10R
IN
3J24
3
+3V3 100n
7
W
502382-0670
GND 4
5J22
FJ20
+3V3
VCCO2
220n
220n 2J46
220n 2J45
2u2 2J44
PROGRAMMING ENGINEERING
FJ30
6SLX4-4MB-M25P40 6SLX9-4MB-M25P40
RES
2u2 2J43
2J42
30R
+3V3 FJ24 4
VCCO1
FPGA-LED0 3J25
3
47R
FPGA-LED2
18p
18p
8 330R 1
DBG 3J26-1 DBG 6J25
LTST-C190KGKT
DBG 3J26-2
7 330R 2 LTST-C190KGKT
DBG 6J24
DBG 3J26-3
6 330R 3 LTST-C190KGKT
DBG FPGA-SYS-CLK
PNX-SPI-CLK
RES 4
9J21-4
5
PNX-SPI-SDO
RES 3
9J21-3
6
AMBI-SPI-OUT-MOSI
PNX-SPI-SDI
RES 2
9J21-2
7
AMBI-SPI-OUT-MISO
PNX-SPI-CS-BLn
RES 1
9J21-1
8
AMBI-SPI-OUT-CSn
AMBI-SPI-OUT-CCLK
1n0
PROG-B
2J2N
2
2J2P
12M
2J51
6J22
1
47R 1K0
3J29
1M0
10K
3J31
3 GND
RES
47R
1J21
VCC RESET
3J27
1
2J50
7J26 NCP803
4
3J28
3J30
+3V3
RES
1 NC
3
1
NC
5
5 1
+3V3 7J24 74LVC1GU04GW 2 4
3
220n
220n 2J2H
220n 2J2G
2u2 2J2F
RES
2u2 2J2D
2J2C
+3V3 7J23 74LVC1GU04GW 2
DBG
VCCO0
30R
5 330R 4
FPGA-LED3 DBG 3J26-4
FJ25
FPGA-LED1
2
2J2M
5J24
100n
VALUE
+3V3
FPGA-SYS-CLK
6J23
220n
220n 2J2B
220n 2J2A
2u2 2J49
7J22 3225
1
RES
2u2 2J48
2J47
30R
LTST-C190KGKT
5J23 +3V3
100n
10-4-29
Q552.4E LA
FPGA, power & control
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_059_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 159
FPGA, I/O banks
FPGA, I/O banks
B07B 7J01-1 XC6SLX4-2TQG144C0100
7J01-6 XC6SLX4-2TQG144C0100
BANK0
VCCO0
122 125 135
VCCO1
76 86 103
VCCO2
42 63
VCCO3
4 18 31
GND
VCCINT
19 28 52 89 128
VCCINT
VAUX
20 36 53 90 129
144 143 142 141 140 139 138 137 134 133 132 131
VCCAUX
RES 9J02
PWR_GND
3 13 25 49 54 68 77 91 96 108 113 130 136
IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0
IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0
127 126 124 123 121 120 119 118 117 116 115 114 112 111
7J01-2 XC6SLX4-2TQG144C0100
BANK1 105 104 102 101 100 99 98 97 95 94 93 92
IO_L1P_1 IO_L42P_GCLK7_1 IO_L1N_VREF_1 IO_L42N_GCLK6_TRDY1_1 IO_L32P_1 IO_L43P_GCLK5_1 IO_L32N_1 IO_L43N_GCLK4_1 IO_L33P_1 IO_L45P_1 IO_L33N_1 IO_L45N_1 IO_L34P_1 IO_L46P_1 IO_L34N_1 IO_L46N_1 IO_L40P_GCLK11_1 IO_L47P_1 IO_L40N_GCLK10_1 IO_L47N_1 IO_L41P_GCLK9_IRDY1_1 IO_L74P_AWAKE_1 IO_L41N_GCLK8_1 IO_L74N_DOUT_BUSY_1
88 87 85 84 83 82 81 80 79 78 75 74
7J01-3 XC6SLX4-2TQG144C0100
BANK2 DONE CCLK
3J02 IJ01
10R
PNX-SPI-CLK PNX-SPI-SDO MISO MOSI PNX-SPI-SDI PNX-SPI-CS-BLn
3J09
10R
9J01 FPGA-LED3 FPGA-LED2
CMPCS_B_2 IO_L30P_GCLK1_D13_2 DONE_2 IO_L30N_GCLK0_USERCCLK_2 IO_L1P_CCLK_2 IO_L31P_GCLK31_D14_2 IO_L1N_M0_CMPMISO_2 IO_L31N_GCLK30_D15_2 IO_L2P_CMPCLK_2 IO_L48P_D7_2 IO_L2N_CMPMOSI_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L49N_D4_2 IO_L12P_D1_MISO2_2 IO_L62P_D5_2 IO_L12N_D2_MISO3_2 IO_L62N_D6_2 IO_L13P_M1_2 IO_L64P_D8_2 IO_L13N_D10_2 IO_L64N_D9_2 IO_L14P_D11_2 IO_L65P_INIT_B_2 IO_L14N_D12_2 IO_L65N_CSO_B_2 PROGRAM_B_2
FPGA-SYS-CLK
IJ02 2J01
100n RES
3J03 3J04
10R 10R
3J05
10R
3D-LR-DISP 3D-LED 3D-VS 3D-LR SCL-SSB-550 SDA-SSB-550 CSO-B PROG-B
BANK3
AMBI-SPI-OUT-CSn AMBI-SPI-OUT-MISO
10p
FPGA-LED1 FPGA-LED0
7J01-4 XC6SLX4-2TQG144C0100
35 34 33 32 33R 30 33R 29 27 26 24 23 22 21
3J0A 3J00
AMBI-SPI-OUT-MOSI AMBI-SPI-OUT-CCLK
2J04
56 55 51 50 48 47 46 45 44 43 41 40 39 38 37
FJ07
10K
10K
3J0C
VAUX
3J0G
IO_L43P_GCLK23_3 IO_L1P_3 IO_L1N_VREF_3 IO_L43N_GCLK22_IRDY2_3 IO_L44P_GCLK21_3 IO_L2P_3 IO_L44N_GCLK20_3 IO_L2N_3 IO_L49P_3 IO_L36P_3 IO_L36N_3 IO_L49N_3 IO_L50P_3 IO_L37P_3 IO_L50N_3 IO_L37N_3 IO_L51P_3 IO_L41P_GCLK27_3 IO_L51N_3 IO_L41N_GCLK26_3 IO_L52P_3 IO_L42P_GCLK25_TRDY2_3 IO_L52N_3 IO_L42N_GCLK24_3 IO_L83P_3 IO_L83N_VREF_3
17 16 15 14 12 11 10 9 8 7 6 5 2 1
BL-DIM1 BL-DIM2 BL-DIM3 BL-DIM4 BL-DIM5 BL-DIM6 BL-DIM7 BL-DIM8 BL-DIM
10K
10K
3J06
3J07
VAUX
7J01-5 XC6SLX4-2TQG144C0100
MISC 109 110 107 106
DBG 1J02
7
FJ02 FJ03 FJ04 FJ05
73
FJ06
8
100n DBG
1 2 3 4 5 6
2J02
1K0
DONE
72 71 70 69 67 66 65 64 62 61 60 59 58 57
FJ01
10p
VCCO2
3J01
2J03
B07B
VCCO_3 VCCO_2 VCCO_1 VCCO_0
10-4-30
Q552.4E LA
TCK TDI TMS TDO SUSPEND
VAUX
FPGA, I/O banks
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_060_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 160
Tuner, channel decoder
B08A
Tuner, channel decoder
B08A
VCC-TUNER IFA1
3FA0
22u
22u 2FA6
2FA5 100n
1FA2 U.FL-R-SMT-1(10)
2FA8
3
5FA6
3FA2 3FA1
30R
5FA7
1n0
2FA4
1
100n
10u 2FA2
FFA7 FFA6
30R
FFA1
2FA9
5FA5 330n 10p
2FAA
10p
4
FFA4
FFA3
100R 100R
FFA2
1FA0 DBG
5
10p 2FAK 10p
AFA1
12
SCL-TUNER SDA-TUNER
330n
14
A3.3V IF1_P IF1_N AGC1 NC1 NC2 IF2_P IF2_N AGC2 I2C_SCL I2C_SDA
10p
VCC-TUNER
AFA3
10p 2FAH
2
OUT
3FA4 47R
AFA0
10p 2FAG
IN
COM 2FA1
2FA0
RES
330u 6.3V
30R
5FA4
10p 2FAC
3
+5V
FFA0
FFA8
2FAJ
9FA0
9FA1
2FAB
IFA0
5FA0
AFA4
5KC9 330n
AFA2
3FA3 47R
SOC-IF-N SOC-IF-P
1 2 3 4 5 6 7 8 9 10 11
AFA5
330n
47R 7FA0 LD1117DT33
FFA9
5KC8 3KA1
47R
TUNER
3KA0
IF-N-DVBT2 IF-P-DVBT2
16
15
1F00 SUT-RE214Z
13
1
10p
2
3
2FA7
2 1FA1 1 U.FL-R-SMT-1(10)
30R
5FA1
0R1
FFAA
1 2 3
BM03B-SRSS-TBT
3KA3
IF-AGC
41
2KCH
DKC0 IKC4 3KC7 2KCJ
+3V3-DVBT2-D
32
7 19 42
10 22 28 44
47R
1K0
IF-AGC 100n 3KC8
1 47 2
48
10K IKC5 3KC9
3K3
0 1 2 3 TSDATA 4 5 6 7
TAINP TAINM
IKC6
46 45
RFAIN
GPIO0 GPIO1 GPIO2
I2C ADDRESS = 0XD8
SCL SDA
TIFAGC
TTUSCL TTUSDA
3K3
DKC1 RESET-FUSION-OUTn
26
29
30
33 40
TESTMODE
SLVADR0
VIA
OSCEN_X
RST_X
SLVADR3
NC1 NC2 VSS
1 3KC0-1 47R
TS-CHDEC-CLK TS-CHDEC-VALID TS-CHDEC-SOP
3 3KC0-3 47R
TS-CHDEC-DATA
3KCC
22K
3FAD
22K
10p
2FAE 470R
3FAC
3FAB
470R
3FAA
VCC-TUNER
5KC5
IKC7
5KC7
VCC-TUNER 3KC2
SCL-FE SDA-FE
3KC3
47R
+3V3-DVBT2-D
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
IKC8 +1V2-DVBT2-C
+1V2-FE 30R
30R 5KC6 +3V3 30R
47R
+1V2-DVBT2-C
3KCE
IKC9 +1V2-DVBT2-P
22R
GND_HS 49
25
6 11 18 23 27 31 36 39 43
24
8 9 12 13 14 15 16 17 20 21
6p8 47R 8 2 3KC0-2 47R 6
7
1u0
10p 3KC6
4u7
TSCLK TSVALID TSSYNC
3KC1
5 4 3
2KCR
2KCG
3KCB
IFA4
RES 2KCK
PVDD
XTALO
IFA5
FKC1
Position Nr
FUSION
3FA7
-
3FA9
2K7
3FAA
470R
-
10u
47R IKC3
38 37
7FA1-2 BC857BS(COL) 4
2KCS
3KCA
TS-INT-CLK TS-INT-VALID TS-INT-SOP TS-INT-DATA
5
1u0
IKC2
10p 2KCF 100n
34
DVDD
5 8 7 6
3
IFA3 2
2KCP
100n
IKC1
CVDD XTALI
1K0
2KCD 2KCE
5KC1 T2-AGC
3KC4
35
2K7
6 7FA1-1 BC857BS(COL) 1
10K
2KC0
100n
100n
2KC1
100n 2KC2
2KC3
100n
VCC-TUNER
2KC4 100n
2KC5 100n
100n
2KC7
2KC6 100n
9KC0 9KC1
12p
2KCB
12p 1KC0
4u7 IF-P-DVBT2 IF-N-DVBT2
2 4
2KCC 5KC0
7KC0 CXD2834ER IKC0
6K8
6K8
3KA2 7KA0 PDTA114EU RES
+1V2-DVBT2-P
4 9RC2-4 1 9RC2-1 2 9RC2-2 3 9RC2-3
1
RES
FFAC
+3V3-DVBT2-D
41M 3
10p
100R
3FA9
+1V2-DVBT2-C
2FAF 3FA7
RES IFA6 T2-AGC
22n
FFA5
100R RES
SOC-IF-AGC
3FA8
3KA4
FFAB
IF-AGC
2FAD
100R
10n
10-4-31
Q552.4E LA
TV550-R4 100R
3FAB
10K
3FAC
470R
3FAD
22K
22K
2FAD
100nF
7FA1
BC857BS
22nF _
-
Tuner, channel decoder
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_061_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts 10-4-32
Q552.4E LA
10.
EN 161
DVBS, FE
DVBS, FE
B08B
B08B 7RA1-1 STV0903BAC
22u
2RAG
100n
10n
2RAF
100n
2RAE
10n
2RAD
100n
2RAC
2RAB
+1V0-DVBS
Diversity Matrix (Satellite Tuner dependant) Position Nr Affected Pin Default Value STV6110 STV6111
JUMP
2RB7
27
10U
2RBU
27
4N7
-
X
2RBV
27
68P
X -
9RB9
27
JUMP
X
-
3RB3
27
4R7
X
2K2
10n
2RAP
10n
10n
2RAN
100n
2RAM
X
+2V5-DVBS
X X
VDDA2V5
8 7
IM IP
N Q1 P
60 56
F22-DISECQ-TX NC NC
IRA0
3RA7
SCL-FE SDA-FE
47R
47R
IRA1
3RA8
SCLT SDAT
FRA0
RESET-DVBS IRA2
+3V3-DVBS
0 CS 1
128 20 126 107
DISEQCIN1 DISEQCOUT1 FSKRX_IN FSKRX_OUT NC
97 98
SCL SDA
19 18
SCLT 1 SDAT
62 58
RESETB STDBY
26 23 24 29 27
FRA1 FRA2 FRA3 FRA4 FRA5
82 83 84 86 87 89 90 91 94 95 108 109 111 115 116 119 120
TCK TDI TDO TMS TRST
101 50 49 47 46 44 43 37 35 34 32 30 55
1 2 3 4 5 6 GPIO 7 8 9 10 11 12 13
FRA6
47n
NC
47p
TS-INT-DATA TS-INT-CLK TS-INT-SOP TS-INT-VALID
NC NC NC NC NC
3RA0-3 3 3RA1 3RA0-2 2 3RA0-1 1
6 47R 7 47R 8 47R 47R
NC
NC NC NC NC NC
TS-DVBS-DATA TS-DVBS-CLK TS-DVBS-SOP TS-DVBS-VALID
NC NC NC NC NC NC NC NC NC NC NC NC
40 41
0 COMP 1
AGC 2RC9 RES
2RB0
NC
6p8
N I1 P
129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165
1K0 63 64 65 67 68 70 71 73 74 75 78 79
0 1 2 3 D 4 5 6 7 CLKOUT STROUT DPN ERROR
IRA3
3RA3 120K
NC NC NC NC NC NC NC NC NC NC NC NC NC
100n
JUMP
VDDA1V0
5 9 13 114 118 123 127 2RAW
25 25
+1V0-DVBS
X
100n
9RB6 9RB7
VDD3V3
2 3
2RAV
33N
100n
7
X
2RAL
2RBW
-
100n
27P
2RAU
4,5
100n
2RCB
-
2RAK
X
100n
27P
2RAT
4,5
100n
2RBM
100n
X
2RAR
JUMP
100n
4,5
2RAS
9RB8
X
2RAJ
-
100P
VIA
21 38 54 76 80 92 96 106
+3V3-DEMOD 2RAH
4,5
2RBY
VDD1V0
DIRCLK CLKI CLKI2 CLKOUT27
SENSE+1V0-DVBS FRA7
3RA2
16
AGCRF1
I2C-ADDRESS : D0
59 104 103 100 11 12
QM QP
52
VS
XTALO
RES 2RB1
10n
2RAA
100n
10n
2RA9
100n
2RA8
10n
2RA7
10n
2RBK
22u
2RBL
30R
100n
2RA5
+3V3RF
+3V3-DVBS
2RA6
IRA7
GND_HS
NC NC
Φ
MAIN
XTALI
124
1K0
+1V0-DVBS
GNDA
NC
3RA4
RES
1 4 6 10 14 113 117 121 125
10K
100n
10n
2RA4
100n
2RA3
10n
2RA2
100n
2RA1
22u
2RA0
22u 2RCC
22u 2RCD
RES
2RCE
22u
2RAY
30R
5RA1
Φ
POWER_VIA
2p2
15 17 22 25 28 31 33 36 39 42 45 48 51 53 57 61 66 69 72 77 81 85 88 93 99 102 105 110 112
+3V3-DEMOD
3RA6
+3V3-DVBS
122
XTAL RES 2RCA
7RA1-2 STV0903BAC +1V0-DVBS
IRA8
5RA0
+3V3RF
*
*
*
68p
10u 2RBV
4n7
2RBU
100n
100n 2RB6
1n0 2RB5
1n0 2RB4
1n0 2RB3
2RB2
IRA9
* 3RB3 4R7
2RB7
IRA4
* 9RB9
7RC1 LD1117DT33
*
16V
+2V5-DVBS IRC1
4
1u0
BP
FRC0
5
2RC2
EN
COM 10K
3RC2
100n
10K
3
OUT
1u0
+3V3-DVBS
IN
2RC1
IRC2
9RB7
27p
3RC1
SYN HS 29 33
2RC6
2RC5
100n
7RC0 RT9193-25GB
10n
10p 2RBS
10p
10p
1
IRC0
+3V3
2RC3
RF LNA LT MIX DIG BB VCO 5 3 9 10 15 17 25 26
+3V3-DVBS
10p
IP IM
2RBP
*
8 100R
GND
9RB6
100p
2RBY 2RCB
9RB8
0p56
*
7 34 35 36 37 38 39 40 41 42
QP QM
FRC1
2
2RC4
RF_IN
2 3RB1-2
5 100R
2
VIA
21 20
4 6 3RB1-4 100R 1 7 3RB1-1 100R
OUT COM
1u0
NC
3 3RB1-3
2RBR
AS
1K0
10p
RF_OUT
AGC
100p
IN
30R
XTAL
10p
I2C-ADDRESS : C6
QP QN
3RB0
1
* RES 2RBG
100p
1n0 2RBH
SM15T 2RBJ
47p 6RA0
RES 2RBT
4
SATELLITE TUNER
27p
FRA8
+V-LNB
2RBM
27n
8 9 5 10
5RA2
6 7
*
1 2 3 4
Φ
18 19
2RB8
2RC0
1R01
SCL SDA
IP IN
32
2RBN
23 24
+3V3RF
XTAL_OUT
XTAL_IN
XTAL_CMD
3
+5V
SYN
2RBB
16
VCO
2RBC
9RB0 RES
MIX DIG BB VSS
IRC3
5RC0
28
10p
2
27
10p
RES 10p
22
2RBA
12 13
14
2RB9
2RBD
1
11
33n
2RC8 AGC
31
10p
RES 10p
8
LNA LT 30
10p
2RC7 SCLT SDAT
1
6
2RBW
1RA0 16M 2RBF
2 NC 4 NX3225GA
3
10p
7RA0 STV6110AT
22u
2RBE
* * +3V3RF +3V3-DVBS
7RC2 BC847BW
DVBS, FE
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_062_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 162
Video out - LVDS
B09A
Video out - LVDS
B09A
PX1CLKPX1CLK+
FG1D FG2T FG1F FG1G FG1H FG11 FG1J
PX1DPX1D+ PX1EPX1E+
FG1K FG1L FG1M FG1N
PX2APX2A+ PX2BPX2B+ PX2CPX2C+
FG12 FG13 FG14 FG15 FG16 FG17
PX2CLKPX2CLK+
FG18
PX2DPX2D+ PX2EPX2E+
FG19 FG1A FG1B FG1Q FG1P
41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
3G37 3G48 3G45 3G41 3G42 3G31
100R 68R 100R 100R 100R 100R
** * *
10K
47p
47p
100p
10K
47p
47p
10K
47p
47p
10p
10p
10K
47p
10K
10K
10K
10K
3G47
2G79
2G7A
2G7F
RES
RES
RES
2G7D
3G40 RES
2G26 RES
RES
2G7C
3G39 RES
RES
2G7B
2G76
2G75
RES
2G77
3G38 RES
RES 3G33
3G44
SAMSUNG 3G35
RES
*
*
FG34 FG2H FG2G FG2R
FG2L FG2M
PX3APX3A+ PX3BPX3B+ PX3CPX3C+
FG2U FG2F FG1Y FG1Z FG20 FG21
PX3CLKPX3CLK+
FG22 FG23
PX3DPX3D+ PX3EPX3E+
FG24 FG25 FG26 FG27
PX4APX4A+ PX4BPX4B+ PX4CPX4C+
FG28 FG29 FG2A FG2B FG2C FG2D
PX4CLKPX4CLK+
FG1R FG1S
PX4DPX4D+ PX4EPX4E+
FG1T FG1U FG1W FG1V
RES 2G28 RES 2G29
47p 47p
FG2P 100n
FG30 FG31 FG32 FG33
CTRL-DISP3 BL-PWM 3D-LR-DISP CTRL-DISP1 CTRL-DISP2 3D-LR
*
100n
100n
100R 10R 10R
2G91
2G95
3G32 3G2W 3G2Y
EMC 100n RES 2G9D
FG2J
SAMSUNG
RES 9G0G
FG2N
+VDISP 1X03 EMC HOLE
EMC 100n RES 2G9C
100n 100n
CTRL-DISP3 SDA-DISP SCL-DISP
* *
EMC 100n RES 2G9E
2G93
FG1C
TO DISPLAY
EMC RES 2G9F
PX1APX1A+ PX1BPX1B+ PX1CPX1C+
1G50 20519-041E 50 51 49 48 46 47 44 45 42 43
*
47p 47p 47p 47p
x x x x x -----
TO DISPLAY
100n
2G94
2G96 2G99 2G97 2G98
------x x x
RES 3G34
5 6 7 8 9G0K-4 9G0K-3 9G0K-2 9G0K-1 2G92
OTHERS 10K
3G41 3G42 3G43 3G44 3G45 3G46 3G47 3G48 2G7F
+VDISP
LGD 50HZ 3D TM100
3G43
*
RES 3G46
RESERVED FOR 100HZ PANEL
10K
+3V3
4 3 2 1
10-4-33
Q552.4E LA
Video out - LVDS
1G51 20519-051E 60 61 58 59 56 57 54 55 52 53
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19220_063_120228.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 163
Layout top 3139 123 65333
2G91 2G9E 2G9F
1G51
9G0G
3J06 3J07
2C96
2C95
2C94
2C7N 3C7H
5C55
3C70
2C7F
3C7G 2C7M
5C56
2C7L
2C7K
5C57
2C7G
3C81
5C53
2U88
2U87
2U86
2U85
2U84
2U83
3C99
1C86
2C71
9C06
2C70 3C7F
6J22 6J23
6J25 6J24
3UD5 2UD6 2UD3
3UD4
2J02
3U84
7J21
3J26
2J2K
6J21
7J01 2UB6
2UF4 3UF2 3UF5 3UF6
2UDB
3J0G
2J04 3J00 3J0A 2J03
9U44
3J0C
2UF7
9C07
1C04
3C98
2UDC
2UDA 2UF0
2UD8
2C83
3UD3
2UF1
7UD1
5UD2
2C84
1P00
3C96
2UFA 2UFB
2G9C
2G9D
5U00
5U01
6U00
2U11
3U242U09
7U01 7U04 7U02
2UD9
5UD3
2U18
2U19
2C85
1C85
9C09
1A04
1C03
9C08
5C54
3U85
9U43
3U23
2U24 2U23 2U25
2U17
2UD7
2UDF
2U20 5U03
3UF4 2UF3
2UU2 5U02
1J02
3UD1
2U82
2U81
1M54
2UF9
2UU3
2UDD
5UD1
6UU1 3UU4
1UU0
2UD0
7U48
3U82
2UDH
3U61
7UD0
2UF8
3U83
2U71
2UD1
5UD0
3U60
7U41
3U80
2D87
1D51
3U73
3U62
2UD2
3U63
2U55 3U72
2UF6
2U47
2U54
3U71
2U68
2UD4
7U40
2U46
2U8D
6U40
2U45
3U42
3U81 3U45
2U53
2U44
3U65
3U43
2D70
1D52 1D50
2D98
1D02
3U64
1A05
1T71 3C83
1M99 1J22
1M95
3G47 3G45 3G31 3G46 2G7A 2G7F
3G34
3G48
2G79
2G7D
3G41
3G40
3G44
3G33
2G26
3G39
2G7B
2G7C
2G76
3G37
2G75
3G2Y
2G77
1N05
1TP1
6TP4
2TPF
1NN8
2NN6 2NN8
1NN9 2N73 3N9C
2T02
6NN9
6NN8
2NN7
2NN9
6N53 2N77
2FL2
3FLB
3FLD
3FLK
3FLN
7FL5
1N80
3NN0
3NN1
2T01
2T00 5T00
2FLG
3FLL
3TPF
5T01
2S3M
1N10
3KA3
3FA2 5FA6
1P07
2T20
2RB1
3RA1
3FA1 5FA7
2FA9 2FAA
1P08
2KCR
7RC2 2KCK
3KC0
3RA0
2KCJ 3KC7
2FAC 2FAB
2RC6
1FA0
7RA1 5RA1 2RBK
2RB4 2RB3
2RB2
2RCB
2RBY 9RB8
2RBW
7RA0
3FL8 2FLC
6RA0
9RB0
2RB6
1P05
2RB9 2RBB
3FL7
2RC8
2RC7
2RBC
2RBL
2RB5
2RBV
2RB7
2RBU 3RB3
2RBE
2RBS
3RB12RBR
2RBA
9RB9
1RA0
2RBF
9RB7
2RBD
3RB0
2RBT
9RB6
2RBM
1N122N15 2N91
2RBN
2RB8
IN43
2RBP
2RCA
1F00
7NC1
2RC9
2N88
1N31
1P03
1P02
5RA2 2RBJ
1P04
2RBH
2RBG
1VA1
2T12
3S1T
3KCA
9KC1 2KCF 3KCB
5KC1 2KCG
9KC0 2KCE
3KA1
3FA3 3FA4
9FA0
3FA0
2NCW
2NC3
2NCC 5NC2
2NC1
2T15
3S1S 3S24
3S28
3KC3
3NCN
6N43
6N44
3NCM
5NC3
3N21 2N35
9FA1
5KC8 5KC9 5FA4 5FA5 2FAH 2FAG
1N06 3NCA
2N36
1FA1
2FA5 2FA6
3NCJ 3NCK
2NCX 3NC3
1N43
1VA8
3NCH
2N38
3KC8
IN45 2NCQ 2NCP
2NC8
2N37
3KC9
3KA0 3S84
3S83
1N86
2N27 3N87
2N67 3N89
6N51
6N40
2NCN 2NCM
INC8
3N20
1KC0
2KCC
1FA2
3KC1
1N85 2NCZ 2NCY 3NC5
1N39
1VA4
1N42
1N29 1N37
2N68 3N90
6N52
2N40 3N96 2N71
2N39 3N97
6N38
6N06
3N53
1N28
3N30
3F58
3S1R
3S1U 3S29
3S11 2S3Q
3S1L
7KC0
2KCB
2N55
3N68 3N34
2N54
3N35
6N20 3N02 2N06
6N03
6N09
2N79
3N03 2N04
1N70
2FL6
3S44
3S4U
2S7N
3S59 2S87
2S7M
3S4J 2S7J
3S4P 2S7L
3S4T 2S7P
3S4L 2S7K
3S4K 2S7H
3S13
4S14
7S08 2S34
2FA0
3S4V
5KC02KCD
2S33 2S32 2S30 2S31 2S2V 2S2W
3S3F
2S38 3S35
2S35 3S34
3S39
3S37
3S38
DBS8
3S36
3S32
3N22 3N25 3N72
2N07
3N28 2N56 2N57
5N01 5N02 2N05
3N27 3N39
5N03 5N04
2N58 2N59
6N47 6N23
5N73 3N74
6N22
3N75 2N80
3N32
3N31
3N44
1N552N18
2N24
7N03
1N54
6N29
9FC3 9FC4 2FC7
1N23 2N76
1FC6
6N32 5N77 2N45
3FC2
2FC8
2N72
3N65
1FL5
3KC2
3S4W
3F65 3F64
2NC2
3FC5
6FC1
2FC1 2FC6
1FC1
1N252N44 3N62
2FC2
3FC1
3FC3
3FC6
9FC5
9FC2
6FC7
2FC4
1FC3 1FC4 1FC2
1N38
9FC1
6FC6 6FC8
2FC3
6FC2
9FC6
2FC5
IC74
6FC4
9U41
3FC7
6C07
3U68 2C81 3U41
6FC3
3C78
3FC4
3C73 3C7A
2C80
IC75
2C7B 2C7C
7U42
3C71
3U74
3C95
2S77 2S78
3N82
3N66
3N29
5N0C
5D84 5D85
3U59
2C87
3S4R
3N64
3N67
7F52
2FL7
1F51
9N42
3N81
2FLF
1F10
BS10
3N80
7N10
3F52 2F52
3S3W
3N17
3N51
6N19
6D61
3D55
9D53
9D52
3D56
3D84 2D39
3D77
3C94
2C72
7D80
3D76
2D72
9D54
2D74
3D71
3D58
2D68
2D86
3C97
3D83
1FC5
2C91
2C99
2D85
6D60
6FC5
1C20
2C86
3S42
2S41 2S4M
2N62
1N09
3D57 3D50
2C77 3C76 2C93
2N09
2N08
3C77
6C05
5N08
3D54
7D50
2N75 3N42
2D51
2C90
1N88
2D5F
2D77 2D69
6N30
7D60
1N87
1N00
2D88
2D64
2D67
2D50
3D51
3D72
2C97 2C78
2C82 3C79
9S06
3S00
3S6J 3S26
2D89
5D79
2D94 9D51
2D53 2D54
2D79
2D61
3D73
2D75
2D52
3S3M
2F49
3S2M
3KC4
2D95
5D70
2D80 2D82
3S43
2T05
3S25
1NN2
3S6N 3S19
3S12
3S53
3D75
3D74
3D52 3C72
5D76
5D74
5D00
2D71
2D55
1N22 3N43
5D75
2D56
1F01
1C30
5D01
2S4G
1S02
IS13
3S6K
3NCU
3B05 3B04
5D71 3S27
1C22
3S81 3S80 3S52 3S54 3S50
DS50
2S2T
5D81
2B45
2D78 2D99
2D76
5D72
FF04
3S3L
3B15
2D83
2S3L3S6M
7S09
3B00
3S1C
3B14
7F58
2F58
3S1B 2S4D
3S3N
2S4F
7B03
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1D55
1D01
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5D77
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3B02 3B12
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3B07
3S1J
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3F60 3F59
3S3S FF28 3S1K 3S2A
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3S62 3S21
3S3R
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2TPD
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3S94
3S91
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3B10 3B08
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3B25 3B16
2D57
2D60
1G50
7B00
5TP5
3B19
3S97
2B47
6TP6
3B18
7S00
2TPH
3S95
3B26
7B01
3S96
3B11
2F01
3G32
3G35
1D54
2TPG
3G2W
3G38
1C21
10-4-34
Q552.4E LA
1P06
1R01 Layout top
3
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Circuit Diagrams and PWB Layouts
10.
EN 164
IC79
IC7G
FC9L
FC9K
FC72
FC77
IC7D
Layout bottom 3139 123 65333
IC7A FC98 FC99 FC96
FC97
FJ27
FC75 FJ29
2U89
FU58
IUDG
IUD1
3UF1
IU10
IUD8
2UF2
IUD5
IUU3
7UU3
7UU2
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IU19
IU18
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3UU9 3UU6
2U02 IU07 IU08 IU16
2J28
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FU05
IU15
IU23
FJ23 5J21
2J36 2J40
7UU5 7UU4
IU20
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2U05
9J02
2J37 2J41
3U22 2U07 2U08
2U01 IU24 3U08 3U09 3U18 3U17
IU11
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9UU3
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7J20
2J2N 2J2P
1J21
2J29 2J2G
2J26
2J31 2J30
FJ22
2J2F
2J2C
7J23 3J28 3J30 7J24
3J03 3J04 2J44 2J43 2J42 5J22 2J25 2J39 2J38 2J35
3J05
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FJ20
2J34 2J23
7J22
5J24
IU03
3J27 3J25 3J29
9J21
3UU3 IUU4
FUU2
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2UU0 IUU5
7UU0 FU73
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3UU8 2UU5 2UU1 3UU1 IUU13UU2
9UU1 9UU0
2J22 2J21 5J20
2J32
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FJ28
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FU67
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FJ03
FJ25
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FG29
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FG24
FG23
FG22
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3G43
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FC94
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2RB0
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2KC0 2KC5
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9RC2
2RC4
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FNCL FNCA
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FNCC
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FC71
7UU1
IC78
FC73
FL41
10-4-35
Q552.4E LA
FC9J FC93
FFC9
FN84
FN82
FNCF
FNCD
Layout bottom
3
2011-12-12
2
2011-05-25
3139 123 6533 19220_065_120228.eps 120228
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 165
Layout top 3139 123 65334
2G9F
1G51
3J06 3J07
2C96
2C95
2C94
5C56
3C70
3C98
2C7F
3C99
2C9A
2C9B
2C9C
2C9D
2C7L
2C7K
5C57
5C53
2C7G
3C81
3C83
3C9A
3C9B
3C9D
2U85
2U88
2U87
2U86
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2U83
3C7H
1C86
2C71 2C70 3C7F
6J22 6J23
3UD5 2UD6 2UD3
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7J01 2UB6
2UF4 3UF2 3UF5 3UF6
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2UDC
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2T12
2T15
3S1U 3S29
2FAC 2FAB
1F00
2NC1
3RA0
2RC9
3N21 2N35
3F58
3S1R 3S23
3KC3 3KCA
5KC02KCD
5KC1 2KCG
9KC1 2KCF 3KCB
3KA0
3NCN
3NCM
6N43
6N44
1N06 3NCH
2N38
3FA3 3FA4
9FA0
3FA0
2NCX 3NC3
3NCJ 3NCK
1VA8
1N10
2RC6
1FA0
IN45 2NCQ 2NCP
2NC2
3N20
2N36
9FA1
5KC8 5KC9 5FA4 5FA5 2FAH 2FAG
INC8
2N37
1KC0
2KCC
3S84
3S83
1N86
2N27 3N87
6N40
1FA1
2NCN 2NCM
3KC1
1N85 2NCZ 2NCY 3NC5
1N28 1N39
1N42
1VA4
3KC9 3KC8
9KC0 2KCE
3S4U
3S59 2S87
2S7N
3S4J 2S7J
2S7M
3S4P 2S7L
3S4T 2S7P
3S4L 2S7K
3S4K 2S7H
2N67 3N89
2N68 3N90
6N51
3N53
1N29 1N37
6N52
2N40 3N96 2N71
6N06
2N39 3N97
2N72
1N43
3N30
1FA2
3N64
3N65
2FL6
3S44
2S35 3S34
2S33 2S32 2S30 2S31 2S2V 2S2W
2S38 3S35
3S37
3S39
3S3F
3S38
3S32
DBS8
3S36
3S00
9S06 2S2T
4S14
3S13
7KC0
2KCB
2N55
3N35
3N68 3N34
1N70 2N54
3N72 3N02 2N06
6N03
6N09
3N03 2N04
6N23
3N75 2N80
3N74
6N22
5N73 2N79
3N32
3N31
3N44
1N552N18
2N24
7N03
1N54
6N29
2N75 3N42
6N30
1N22 3N43
9FC3 9FC4 2FC7
1N23 2N76
1FC6
6N32 5N77 2N45
2FC8
1N252N44 3N62
3FC2
IC75
3FC5
6FC1
2FC1 2FC6
1FC1
6FC7
2FC2
3FC1
3FC3
3FC6
3FC7
2FC4
1FC3 1FC4 1FC2
9FC2 9FC1
6FC6 6FC8
2FC3
6FC4
2FC5
IC74
9FC5
6FC2
9FC6
6FC3
3FC4
9U41 3U59
6C07
3U68 2C81 3U41
2FA0
3N82
6N38
3N28 2N56 2N57
5N01 5N02
3N27
3N22 3N25
3N39 2N58 2N59
2N05
5N03 5N04
3N29
2N07
6N47 1N38
9N42
3N66
1FL5
3KC2
3S4V 3S4W
3F65 3F64
2NCC 5NC2
5D84 5D85
3U74
3C78
2S77 2S78
2NC8
3D84 2D39
3D77
1FC5
3C73 3C7A
2C80
3S4R
1F51
3N67
7F52
2FL7
3S12
3N81
6N19
7D80
6D61
3D56
3D55
2D74
3D71
9D52
9D53
2D72
9D54
3D58
2D68
2D86
3D83
7N10
2FLF
1F10
BS10
3N80
3C71
2C7B 2C7C
3S42
3F52 2F52
3S3W
3N17
3N51
6N20
3C95
7U42
2C91
3C94
2C87
6FC5
1C20
2C99
3C97
2C86
3D76
3S3M
2S41 2S4M
2N62
1N09
7D50
3D57
6D60
6C05
5N08
3D54
3D50
2C77 3C76 2C93
2N09
2N08
3C77
2C90
2C72
5N0C
2D88
2D64
2D77
2D50
2D51
2C82 3C79
1N88
2D5F
2D69
2C97 2C78
1N87
1N00
3D73
2D61 9D51
2D53 2D54
3D51
3D72
2D67
7D60
2D52
IS13
3S43
2F49
3S2M
3KA1
2D89
5D79
2D94
2D80 2D82
2D75
2D79 3D52 3C72
3D75
3D74
DS50
2S4G
2T05
3S25
1NN2
3S6N 3S19
3KC4
2D85
5D70
2D71
1C22
3S81 3S80 3S52 3S54 3S50
1S02
3S53
2D95
5D00
2D55
5D76
5D74
2D56
1F01
1C30
5D75
3S6J 3S26
3S27
3S6K
3NCU
3B05 3B14
5D71
5D01
FF04
3S3L
7S08 2S34
5D72
2S3L3S6M
7S09
3B00
3S1C
3B15
2D83
3S28
3S11 2S3Q
3S1L
3S3N
3B04
2D91
2D76
5D77
2B45
5D81
2D99 2D81
7F58
2F58
3S1B 2S4D
7S02
3B13
2S4F
7B03
5D83 5D80
2D73
3S24
3S03
3S3Q
3S1J 3S3T
3B24
2D78
1D55
1D01
1D56
3D81 3D80
3F60 3F59
3S3S FF28 3S1K
3B12
2D5B 2D5D
5D78
1D53
2TPH
9S00
3S02 3S01
3B23
3S62 3S21
2G95 3D79 3D78
7T00
3B07
2S4C
3S2A
2G94
3S3Y
3S04
9S01
3S3R
2G93
3TPB
2T10
2B46
3B02
7B02
2D5A 2D5C
2G92
2B44
2G99
2TPJ
7NN2
2S09
3S31
2G97
2TPC
7TP2
3B17
2G98
2G96
2TPK
3B25 3B16
2D57
2D60
1G50
7B00
2TPL
2TPD
1F52
3S98
3S94
3S93
3S92
3S91
2S4P
3B10
7S0A
3B08
7S00
5TP5
3B19
3S97
2B47
7B01
6TP6
3B18
3TPD
3B26
3S96
3S95
3B11
2F01
3G32
3G35
1D54
2TPG
3G2W
3G38
1C21
10-4-36
Q552.4E LA
1P06
1R01 Layout top
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19221_001_120509.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
10.
EN 166
IC79
IC7G
FC9L
FC9K
FC72
FC77
IC7D
Layout bottom 3139 123 65334
IC7A FC98 FC99 FC96
FC97
FJ27
FC75 FJ26
2U89
FU58
IUU3
7UU3
7UU2
IUD2
IUD1
3UF1 IUD4
IU10
IUD8
2UF2
7U03
IU12
IU13
3U14
IU17 FU06
FU02
3UF3 IUD5
3U05
2U02 IU07 IU08 IU16
IUDF
IU06
FU05
IU15
IU23
2J28
3UU7
7UU5 7UU4
IU20
IU04
2UF5
IU09
IUD9
FJ23 5J21
FU04
IU02 FU09
IU14
IU21
FUD2
IU25
IU19
IU18
IU01
9J02
2J37 2J41
IUDG
IU11
FJ22
7J20
2J2N 2J2P
1J21
2J24 2J2H 2J2D
3U22 2U07 2U08
2U01 IU24 3U08 3U09 3U18 3U17
2U05
5J24 2J2F
2J2C
7J23 3J28 3J30 7J24
2J29 2J2G
IU05
FUU1
9UU3
7U00 2U03 3U10 3U19
FU01
3U01
FU55
IUU0
3U02
2J25 2J39 2J38 2J35
3U00 FU73
2J26
2J31 2J30
2J27
3J05
FJ20
3J03 3J04 2J44 2J43 2J42 5J22
IJ02 2J01
IU22
FU52
2UU4
IUU2
FUU2
FJ05
FUD3
2J33
2J36 2J40
2J34 2J23
7J22
3J27 3J25 3J29
9J21
3UU3 IUU4
3UU9 3UU6
9UU1 9UU0
2J32
2J22 2J21 5J20
2J48 2J47
FJ28
2J2M
3S72
7UC0
2UA4
7F00
2U29
FG2P
FU08 FUA4
FK01
FK02
FK04
FG2N
2U12
2U14 2U13
FG1V
3F03
FK03
2G28
FG1R
FG2C
FG2A
FG2B
FG28
FG29
FG27
FG26
FG25
FG24
IK20 IK02 FG23
FK28
FK27
FK08 FK07
FG22
FG21
FG20
FG1Y
FG1Z
FG2U
FG2F
FG1P
FG1Q
FG1B
FG1A
FG19
FG18
FG17
FG16
FG2M
3G42 IK01
FG2L
3G43
3UB3
FUA5
IK21
2F03
IF07
3UB1
3UB2
FG1T
FG1S
FG2D
2G29
3F04 3F05 2UB3
FK21 FK20
FK22
IF06
2UB2
FK3A
FK25 FK24
IF05
FUA3
FG1U
FK00
7F02
7UA4
7F01
FU03
FG1W
2U16 2U15
2F00
2UU0 IUU5
7UU0
3UU8 2UU5 2UU1 3UU1 IUU13UU2
IUD6
3F09 3F10
3F02
3F01
2F02
FF62
2J49 2J2B
5J23 3J09
7F03
7F04 3F11
7F05
3F53 3F67
2F06 3F14 3F13
3F69
2F53
6UA0
3USF 9USB
FG2R FG2G
FK09
FG2H FG34
FK29
IK22
FK23
6TP5
FK30
FK26
FK06
2B43 IK00
2B32
2B33
6TP1
FTPA
ITP4
2B27
3TP3
ITPJ
2B35 2B39
ITPG
2B34
FB00
FS2Y
2B28
2B29
9G0K FG30
2B36
2S42
2N60
3N26
3N98 FN27
2N66
3N95 3N99
IN33
ID93 ID92
ID95 FN01
ID50
ID53
IN07
2N63 IN32
ID82
FN02
FN03
FN32
AFA4
2N0L
2RAR
IN0A
ID63 ID81 ID75
ID80
IN0B
ID77
ID70
FC89
2N49
ID62
ID94
ID69
IN64
IN39 3N40
FN61
FN34
IN38
2N53
FN50
FN29
2N52
FN49
FN31
3N70
FN5D
FN56
2N70
3N33 3N71
3N69
FN5G
ID66
ID65
FC9D
2RAS
2RAT
3RA2
FL31
ID52
ID56
2RA0
2RB0
3B20 2B26 3B21
2B23 2B14
2B16 2B12
2B11 2B03
2B02
2B04 2B07
3S51
2S2S 2S2R
3S86
3S5F
3S85
FN5B
FN28
IN26
FC88
ID87
ID61
2RAH
FD50
FD67
FRA3
3C75
3D82 ID78
FC94
FD66
FD34 FFA9
2FAE 2FAK 2FAJ 2FAF 2FA7 3KCC 2FA8 FFA43FAD
ID79
2C76 FC87
7D61
3RA4
FRA5 FRA4
2RAU FRA1
3FLJ
2N98 3NB3
3NB1
7N06 IN13
9N01
2N74
3NA1
IN63
3N45
3N0A
2RAV
FL30
FN60
2RAW
FRA2
FL39
ID51
FN33 FRA6
FG1D
FG31
FD33
FN30
IN92
2RA4
2RA3
FG1C
FG32
FL38
2RAF
2RA5
FG1F
2FLD
3NB6
IN42
2RA6
FD95
7N05
AFA2
IN44
FG1J
FG1H
FG2T
FD31
2N48
FFAA
IN90
FN5A
FG11
FG1G
2B00
3B03
IN09
IN91
FG1L
2B01
3S87
IN96
FG1K
FD32
FN54
IFA4
3B28
IN10
IN60
3N48
3S1D
3S49
AFA3
3FAB
2NB1
IFA3
7FA1 3FAC
IS0R
IS12
IN61
3KCE IKC0
3FAA 3FA9
7KA0 3FA7
FFA8
AFA5
2RAE
FFA3
3N18
2NB3 3NA2
AFA0
2RAC
IFA6
2FAD 2RAK
2RAG
2RAB
2RAA
2RAM
2RA8
2RAL
FFA7
3KA4
FFA5
FFA6
FFA2
2RAD
IS1H
IN89 3N06 IKC3
IS1Q
FS13
5N80
2N97 2N99
2N81 IN70
IKC2
AFA1
2RA2
2T16
2T17
2RAY
IRA3
2RCC 5T03
2RA9
5RA0
2RCD 3RA3
IFLJ
2RA7
IRA8
2RAJ
7T03
3FL4
FL33
IRA1
2RAP IRA0
IRA2
2RA1
FT09
2RAN
FRA0
2RCE
3RA6
2T18 2FLB
IN59
IFA5
3FA8
FFAB
3RA8
IS1R
3N19 IKC5
3KA2
3RA7
IKC7
IKC1
3KC6
2KC4 2KC1
3S3P
2KCS
DKC0
IS1P
IS1J
FN5C
IKC9
IKC4
IKC6
FL47
FF65
2KC0 2KC5
FFA0
3S16 3S17
3S47
IKC82KC6
FF64
2KC2
2FA4
FFAC
FL42
FF66
DKC1 FKC1
2KC3 2KC7
2KCP
5KC6
5KC5
IRC1
9RC2
2RC4
7FA0
3RC2
IRC2
FRC1
FFA1
2KCH
7RC0
2RC3 3RC1
2RC1
FRC0
2B09
2B41
IN05
2FA2
2RC2IFA0
2FA1
2RC5
7RC1
5RC0 2FLA
5KC7
3F34
IFLK FL43
5FA0 2RC0
IRC0
FG1M
FD30
IS5G IRC3
FG12
FG1N
FD92
FS08
IS4V
3B01
2B08
3S20
IS50
2S3F
2B05
3S09
2S40
IS1B
2B38
2B25
2S26
2S25
2S67
2S63 5S93 2S60 2S64
3S6Q
2S4S
2S23
2S53 2S52
2S45 IS5J
IS3F
2S4Q
IS19
3S10 IS1M
FG33
2B13
2B06
3S2S
2S19
3S5T
2S68
5S87
IS5H
IS20
3F32
2S5P
2S5J
2S28 2S56
2S14 FS0Y
3S46IS2Z
FG14
FG13
2B40
2S29
3S2L
5D51 5D50
2B17
2S4R 2S36
ID54
2B10 2B37
FS02
2S3N
3S1H
ID55
2B15
3S22
IS1A
IS4W
2S75
2S18
3S1G
IFL4
3FL2
IS5E
3S5S
2S2L
FS10
IS3G
FL36
2S20
3S08
FS11 IS3D
3B22
2S6N
FS15
2B18
3S33 3S0V IS42
2S65
2S3H2S3G
2S5H 2S58 2S5A
3S40
IS16
5S81 5S89
2S13
IS3B
FS51
2S85 2S86 2S84
FL37
2S15
IS05
3S45
IS44
2S10
IN51
3B06
3S30
2S6R 2S6D
3S5B
FS53
IS5F
3N73
2B22
2B20
2S46
2S8A
FS52
IS4Z
FS0Z
FG2J
3B27
2B24
FG15
2S4T 2S51 2S6G
2S22
FS50
FS44
IFLG
3S55
2SHW
IS3L
3S05
FS49
7S20
IS5D
2FL1
3S6H
2S4U
2S5K
2S43
2S16
2FLH
3S2V
2S4K
FS57
9S09
3S2K
3S41 3S2H
2FL8 2FL9
3FLP
3FLC
3FLF
2FL4 2FL5
3FLM
3S5V
3S1P
3S1F
IS1C
IFLA
2S4L
IF54
3C74
FF03
FL32
2S21
5S83
5S95
2S55
2S5B 2S6B 2S6C
FN55
5S94
2S4Y
2S5G
2S27
2S11
2S6H
IS01
5S80
2S4V
2S2A
3S64
FS64
IS1L
IS1K
3S0W
FF29 FT06
2S6A
IS10
FS54 FN5H
2S6L
2S5C
IS3S
IS04
IF59
3S82
2S5D
5S82
FF57
IT18
IS3Q
2S37 5S04
IS58
IT00
5S92 2S6F
5S85
2S6M
3S1X
3F06 3S1A
2S62
IS3K
2S572S4W
2S4Z
3S1W
3S4A
FF55
FF56
3S6A 3S6W 3S6V 3S69 FNN7
2S5M
3S75
3S2F
3S2G
IS25
3S57 3S56
2S6P
IS17
IT02
5S88
3S5Y
IT01
5S90
IS26
2S50
3S6F 3S6D
5S84
3S6L 3S5Z
2S59
IT04
3S1V
3S60
3T01 3T02 2T04
2T03IT24
2S66 2S61
3S6P
3S6G
2S6K
FNN2
3S61 FT07
2B42 FS01
2B19
2S4N
2B21
3S5W
9S08
3B09 2B31
2S17
2S12
2S89 3S58
IS00
3S15
3NN5
3S68
3S6B 3S6C
INN8
3T00 3T04 2T13 2T14 3T06 3T05
FNN1
3NN2
3S67 9S12
3S07 3S06
IS0B
2NN1 INN7
2B30
9S11 3S65
2S24
3S0C
3F12
3S0A
2NN3
2S0B
3S0G
ITP2
IS08
3S66 9S13 9S10
IS0C
FS31
7S01
3F63
3F62
3S0F 3S0D IS0A
2S0A
2NN4
INN5
FF61
IS09
3S0B
2NN2
FF63
7NN1
2NN0 3NN6
ITPF
2NN5
FS2W
3F07
INN6
FC91
6C03
ID84
2C79
5FA1
6C02 IC7H
FC90
FC9A
IFA1 IRA9
FNCM
FNCK
FNC8
FNCL FNCN
FNCC
FNC6
FN85
FN71
2N84
FN83
IC73
FN75
FN80
2N85 2N12
FNA6
1N18 1N19 FN81
3U70
IU45
IU47 FFC8
FFC1
FFC2
FFC5
FFC3
FFC7
FC9B
9U42
FC95
FC9G
7U43 3U69
2N86
FC9H
3U75 IU44
FNA8
5N76
6N28
FNC5 FNC4
5N74
3N79
FNC2
FNA7
FN73
3N78
FNC1
FN58
FNCG
6N26
IN18
FNA4
FL44
FNCA
FNA3
2N14
5NC0
FFC4 FNA1 FNA2
3NC7
3N77
FNCT
FNCJ FNCW
FL45
FNCS
FNC0
6NC2
FNA5
3NCD
IN11
3NC6
2N83
FNCB
3N23
3N76
FNCP
INC7
3NCR
INC4
FN74
2NCUFNCZ
FRA8
7NC0
IU43
FFC6
3NC1
9NC2
FNCR
3NCG 9NC3
FN43
FN48
2NC4
2NC6
INC6 FNCY
3NCL 3NCF
FRA7
INC5
3NCP
FN42
7N02
2NC7
FNCV
9NC0
FN51
6NC1
FNC3
FN57
2NC0
FL40 IRA7
FNCQ
2NCV
IRA4
FL46
7NC2 5NC4
FC92 FNCH
3U53
IFLH
FNC9
3NCT
FNCU
2USA
2UB1
IUSC
2UB0 FUA0
6USA
3USB
IF08
3USA
3USC
3UB0
FU72
IU03 FJ25
FU51
IU55 FU53
IU49
FJ03
2J45 9J01
FJ07
IF04
IF57
FJ24
IJ01
3F08
IUSB
7USA
IUSA
3F68
9USC 3USG
3USD 9USA
IF56
FF589F51
FUU0
FJ02
FU66
FU67
IU48
IU51
3J01 2J46
IF55
9UA0
7F54
7F53
IU56
IUDA
FJ04
3J02
FJ01
2F04
2F05
7J25
3F66 3F54
2J2A
FC86
2U49
FU75
FU63
1U40
FU76
3UD2 2UDG
3UU59UU2
FJ21 FJ06
3J21 FC85
IUD7
2UD5 IUDH
FU602U50
FU59
3UD0
FU48
FC76
3U27
IUD0 FU77
FJ30
3J23
2U22
IUD3
IUDC
2U56
3J24 IJ22
3U20
FC9N
FJ29
2U10
FU7K
FU7J
2U00
FU7H
2U04
FU7G
2U06
FU7F
2U21 3U04
FU7D
3U11
FU7C
3U28
FC9M
FU7B
3U03
FU7A
FU003U21
FC9F
7J26
2J50 3J31 2J51
FC71 FC74
7UU1
IC78
FC73
FL41
10-4-37
Q552.4E LA
FC9J FC93
FFC9
FN84
FN82
FNCF
FNCD
Layout bottom
3139 123 6533
4
2012-04-23
3
2011-12-12
2
2011-05-25
19221_002_120509.eps 120509
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.4E LA
10.
EN 167
10.5 J 272217190529 Sensor board IR/LED/analogue light sensor
IR/LED/analogue light sensor
J +3.3V
J1
R14 10k RES
R9 RES
SDA VSS SCL
1 2 3 4 5 6 7 8 9 10 11
+3.3V
R13 RES 10k
CONNECTOR
R10
+3.3V
Keyboard-IRQ-SRF VSS VSS LED2 3D-LED LIGHT SENSOR
1 2 3
SCL-SRF
C4 10pF RES
C50 100pF RES VSS
VSS
VSS
R1
1 2 3 4 5 6 7 8
IR-IRQ-RF4CE
U1
10R
3
R2 100R
ZD2 5.6V RES
ESD RES
+3.3V
SCL-SRF
VSS
SDA-SRF RESETn
+5V
VDD
4
C3 10uF/6.3V
VSS
Keyboard-IRQ-SRF
FH52-08S-0.5SH
OUT
2
+3.3V
option
J12
C10 C2 100pF 2.2uF/16V VSS RES VSS
IR
+3.3V
C5 10pF RES
FH52-11S-0.5SH C1 2.2uF/16V VSS
VSS
Keyboard-IRQ-SRF
TYCO 2.0- 3pin
10R RES
+5V
IR-IRQ-RF4CE
J2 SDA-SRF
10R
VSS
1
+3.3V
GND
1
GND
R4 47R/100R
TSOP75236
VSS
RED LED +5V
D1
8
+5V
100R
47k
VSS
R21
VSS
R24 18k
3.3V
R25 100k
VSS C110.1u
10k ZD1
100k VSS
LED2 R3
LM358 C12 R23 15k 0.1u
VSS VSS
Q2 RES BC847
LIGHT SENSOR 2
C
6
R26
B Q1 BC857
2
B
VSS
ZD3 5.6V RES
C14 102 RES
E
7
470R
3
U2B
LM358
R20 22k
95-21 RES
1
3
5
C
R22
E
1 2
R19
D1*
LIGHT SENSOR
U2A
1
G1 TEMT6200FX01 3
4
J
2
10-5-1
R5 10k RES
VSS C13 0.1u 1
IR/LED/ analogue light sensor
2011-12-27
2722 171 90529 19220_084_120229.eps 120229
2012-Jun-29 back to
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Circuit Diagrams and PWB Layouts
10.
EN 168
IR/LED/analogue light sensor board layout
ZD1 C13
C11 R22 R21 C12 R25 R26 R20 R23 R24 R19
C3
G1
C50 R1 R2
U1
C4 R9 R13
J12
J2
J1
R5
U2
C1 C10 C2 R3
Layout IR/LED Board (Top Side)
ZD2
10-5-2
Q552.4E LA
C14
R10 R14 C5
R4 V1.0 GWA7.820.742-1
Q1 Q2
ZD3
D1
Layout IR/LED Board (Bottom Side)
1
Layout
2011-12-27
2722 171 90529 19220_085_120229.eps 120229
2012-Jun-29 back to
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Circuit Diagrams and PWB Layouts
Q552.4E LA
10.
EN 169
10.6 J 272217190532 Sensor board IR/LED/analogue light sensor/3D blaster
IR/LED/analogue light sensor/3D blaster
J +3.3V
1 2 3 4 5 6 7 8 9 10 11
+3.3V
R13 RES 10k
CONNECTOR J1
R14 10k RES
R9 RES
SDA VSS SCL
VSS
J2 1 2 3
SDA-SRF
10R
+5V
R10
SCL-SRF
IR-IRQ-RF4CE +3.3V
Keyboard-IRQ-SRF VSS VSS LED2 3D-LED LIGHT SENSOR
C4 10pF RES
C2
C50 100pF RES VSS
2.2uF/16V
+3.3V
C5 10pF RES
VSS
VSS 3D-LED1 R1510R
VSS
option
J12 1 2 3 4 5 6 7 8
FH52-11S-0.5SH C1 2.2uF/16V VSS
VSS
Keyboard-IRQ-SRF
TYCO 2.0- 3pin
10R RES
C9 C10 100pF 100pF VSS RES VSS RES +3.3V
VSS
Keyboard-IRQ-SRF +3.3V
SCL-SRF
VSS
SDA-SRF RESETn
+5V
FH52-08S-0.5SH R4 47R
RED LED D1*
IR
95-21 RES
IR-IRQ-RF4CE
R1
U1
10R
3
OUT
1
D1
2
Q2 BC847 RES 2 B
ZD3 5.6V RES
C14 102 RES
VDD
4
C3 10uF/6.3V
GND
1
VSS
GND TSOP75236
3
1
Q1 BC857
R2 100R
E
B
ZD2 5.6VRES
ESD RES
2
C
C
2
10k
E
LED2 R3
1
3
+3.3V
R5 +5V
10k RES
VSS
R27 4R7 C45
3D-IR
+5V +5V
VSS
U2A
2
R22
5
U2B 7
470R
6
VSS
R21
C12 R23 15k 0.1u
VSS
3D-LED1
R25
3.3V
R45 10K
VSS VSS
VSS
VSS
ZD5
2
5.6V RES VSS
1
R17 10R
EN
R29 4R7
C43 104 VSS 4
100k VSS
C110.1u
10K
ZD1 R24 18k
R28 4R7
U4
LM358
100k VSS
LIGHT SENSOR
100R
LM358
47k
R26
VSS
+5V
R16
5
1
R20 22k
D7
S12306BDS Q5 C44 103 RES
R18 47K
ZD6 5.6V RES
74LVC1G126 3
G1 TEMT6200FX01 3
R19
D6
C46
100uF/6.3V 100uF/6.3V
LIGHT SENSOR
8
J
4
10-6-1
VSS
C13 0.1u VSS
1
IR/LED/analogue light sensor/3D blaster
2011-12-30
2722 171 90532 19220_087_120229.eps 120229
2012-Jun-29 back to
div. table
Circuit Diagrams and PWB Layouts 10-6-2
Q552.4E LA
10.
EN 170
IR/LED/analogue light sensor board layout
Layout IR/LED Board (Top Side)
Layout IR/LED Board (Bottom Side)
1
Layout
2011-12-30
2722 171 90532 19220_088_120229.eps 120229
2012-Jun-29 back to
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Circuit Diagrams and PWB Layouts
Q552.4E LA
10.
EN 171
10.7 J 715G5255 Sensor board IR/LED board
J
IR/LED 4000 series
J +3V3_STBY
1
R301 100R 1/10W 5%
LED301 LED
Red
Light_sensor
2
IR RECEIVER
C204 LED_R 3
U201
KEY1 +3V3_STBY RC6 +5V
1UF16V
+5V
GND Vs OUT GND TSOP75436W
2
D202
C201
C202
100N 16V
100N 16V
1
+3V3_STBY
1 2 3 4
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