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Very Large Scale Integration (VLSI)

VLSI Encyclopedia - Connecting VLSI Engineers ▼ Finite State Machine (FSM) Coding In VHDL There is a special Coding style for State Machines in VHDL as well as in Verilog. Let us consider below given state machine which is a “1011” overlapping sequence detector. Output becomes ‘1’ when sequence is detected in state S4 else it remains ‘0’ for other states. fsm_seq_detector VHDL Code for FSM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; --Sequence detector for detecting the sequence "1011". --Overlapping type. entity seq_det is port( clk : in std_logic;

--clock signal

reset : in std_logic;

--reset signal

S_in : in std_logic;

--serial bit Input sequence

S_out : out std_logic); -- Output end seq_det; architecture Behavioral of seq_det is --Defines the type for states in the state machine type state_type is (S0,S1,S2,S3,S4); --Declare the signal with the corresponding state type. signal Current_State, Next_State : state_type; begin -- Synchronous Process process(clk)

begin if( reset = '1' ) then

--Synchronous Reset

Current_State