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• Rommel Loayza

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Citation preview

A

B

C

D

E

1

1

Compal confidential

2

2

Schematics Document Mobile AMD S1G2 CPU with ATI RS780M(NB) & SB700(SB) core logic 3

3

2007-12-03 REV:0.2

4

A

B

C

D

l.c

ho

Cover Sheet

Rev 0.2

f@

Size Document Number Custom LA-4111P Date:

ai

Compal Electronics, Inc. in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Monday, December 03, 2007

Sheet E

xa

2008/08/02

Deciphered Date

1

he

2007/08/02

Issued Date

tm

Compal Secret Data

Security Classification

om

4

of

48

A

B

C

D

E

Compal Confidential

Consumer AMD 14" UMA - Ripley (JBL20) Accelerometer ST LIS302DLTR

1

Thermal Sensor ADM1032ARMZ

AMD S1G2 CPU

Page 6

Page 30

Fan conn

72QFN

DDR2-SO-DIMM X2

DDR2 800MHz 1.8V

BANK 0, 1, 2, 3

Dual Channel

638-PIN uFCPGA 638

1

Clock Generator SLG8SP626VTR

Page 8, 9

Page 15

Page 4 Page 4, 5, 6, 7

Side-Port DDR2 SDRAM 256Mbits(16Mbx16)Page 12

Hyper Transport Link 16X16

USB conn x2 LVDS Panel Interface Page

ATI RS780M

17

CRT

BT Conn

Page 10, 11, 12, 13, 14

Page 16

2

DDR2 400MHz

HDMI

4X PCI-E

USB conn x1

PCI-E BUS*5

Azalia (HDA I/F)

CardReader JMicron JMB385-LGEZ0A

Realtek Mini-Card*2 8102E(10/100M) WLAN & WWAN

Page 27

Page 25

CardReader Socket

2

26

Page 31

Page 17

SATA Slave

FingerPrinter AES1610 USBx1 page 35

SATA Slave Page 19, 20, 21, 22, 23

daughter board daughter board

Page 26

MDC V1.5 3

daughter board

SATA Master-2

Express Card Page 26

Page 31

USB WebCam

SATA Master-1

ATI SB700

daughter board

Mini-Card WWAN Page 14" Only

USB2.0 X12

A-Link Express II

Page 18

Page 31

LPC BUS

RJ45/11 CONN

daughter board

Page 34

Audio CKT

Page 25

Page 27

TPA6017A2

Page 28

KBC ENE KB926

3

AMP & Audio Jack

Codec_IDT9271B7

Page 29

SATA HDD Connector

Page 24

Page 33

Docking CONN.

4

*RJ-45(LED*2) *RJ-11(Pass Through) *CRT *COMPOSITE Video Out *S-VIDEO OUT *SPDIF *Headphone/Line Out L/R *Stereo Mic L/R *Volume Control *Consumer IR *USB x1 *DC JACK

SATA ODD Connector

LED

Page 24

Touch Pad CONN.

P41

Int.KBD

Page 34

Page 33

Page 19

SPI SPI ROM SST25VF080B

Consumer IR Page 34

Page 32

P35

4

Power On/Off CKT. P35

Compal Secret Data 2007/08/02

Issued Date

DC/DC Interface CKT. A

Page 31

Power OK CKT.

Security Classification

Page 35

Multi-Bay HDD/ODD Option Connector Page 24 14" UMA PA Only e-SATA Connector

RTC CKT.

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Page 36 B

C

D

Title

Compal Electronics, Inc. Block Diagram

Size Document Number Custom LA-4111P Date:

Rev 0.2 Sheet

Friday, November 30, 2007 E

2

of

48

A

B

O MEANS ON

Voltage Rails

C

X MEANS OFF

D

E

Symbol Note :

1

1

: means Digital Ground +5VS +3VS

: means Analog Ground

+1.5VS

power plane

+0.9V

L

+VCCP

Please see VGA@ as no install. No support RX780M.

+CPU_CORE

+B

12/03 update

+VGA_CORE +2.5VS

: Question Area Mark.(Wait check)

+1.8VS +1.2VS

"*" as default BOM setting PA@ : means install when Ripley PA. PR@ : means install when Ripley PR. RM@ : means install when Rachman. *RP@ : means install when Ripley. SIDE@ : means install when SidePort support. *DOCK@ : means install when DOCK support. *CY@ : means install when Function Board-Cypress. ENE@ : means install when Function Board-ENE. @ : means just reserve , no build DEBUG@ : means just reserve for debug. 45@ : Install when 45 level Assy. D3E@ : means install when JMircon D3E support

+0.9VGA

2

S1

O

O

O

O

S3

O

O

O

X

O

O

X

X

S5 S4/ Battery only

O

X

X

X

S5 S4/AC & Battery don't exist

X

X

X

X

S5 S4/AC

SMBUS Control Table SOURCE

3

SMB_EC_CK1

I2C / SMBUS ADDRESSING DEVICE

SMB_EC_DA1 SMB_EC_CK2

HEX

ADDRESS

DDR SO-DIMM 0

A0

10100000

I2C_CLK

DDR SO-DIMM 1

A4

10100100

I2C_DATA

CLOCK GENERATOR (EXT.)

D2

11010010

DDC_CLK0

SMB_EC_DA2

DDC_DATA0 DDC_CLK1

EC SM Bus1 address Device

HEX

Address

Smart Battery

16H

0001 011X b

24C16

A0H

1010 000X b

EC SM Bus2 address

DDC_DATA1 SCL0

Device

HEX

Address

CPU

98H

1001 100X b

SCL1

9AH

1001 101X b

SDA1

ADI1032-2 CPU

KB926 RS780M

RS780M RS780M SB700

SDA0

SB700

SCL2

SB700

SDA2 4

KB926

SCL3

SB700

SDA3

X X X X X X X X X

BATT

V X X X X X X X X

SERIAL EEPROM

V X X X X X X X X

THERMAL SENSOR CPU & ADM1032

SODIMM I / II

X V X X X X X X X

X X X X X V X X X

2007/08/02

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

CLK CHIP

X X X X X V X X X

Compal Secret Data

Security Classification Issued Date

INVERTER

D

Title

MINI CARD Slot 2

X X X X X X V X X

LCD

HDMI

X X V X X X X X X

X X X V X X X X X

G-Sensor

4

Compal Electronics, Inc. Notes List

Size Document Number Custom LA-4111P Date:

3

X X X X X X X V X om

O

l.c

O

ai

O

tm

O

ho

S0

2

Rev 0.2

f@

State

in

+3VALW

Friday, November 30, 2007

Sheet E

xa

+1.8V

3

he

+5VALW

Layout Notes

of

48

A

B

C

D

E

1

1

VLDT CAP.

+1.2V_HT

250 mil 1

H_CADIP[0..15] H_CADIN[0..15]

H_CADIP[0..15]

H_CADOP[0..15]

H_CADIN[0..15]

H_CADON[0..15]

H_CADOP[0..15] H_CADON[0..15]

C1 4.7U_0805_10V4Z

2

1

1

C2 4.7U_0805_10V4Z

2

C3 0.22U_0603_16V4Z

2

1

C4 0.22U_0603_16V4Z

2

1

C5 180P_0402_50V8J

2

1

C6 180P_0402_50V8J

2

Near CPU Socket +1.2V_HT JCPUA

E3 E2 E1 F1 G3 G2 G1 H1 J1 K1 L3 L2 L1 M1 N3 N2 E5 F5 F3 F4 G5 H5 H3 H4 K3 K4 L5 M5 M3 M4 N5 P5

L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15

H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1

J3 J2 J5 K5

L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1

H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1

N1 P1 P3 P4

2

3



L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1

VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3

L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15

AE2 +VLDT_B 1 C7 AE3 AE4 AE5 AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3

L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CLKOUT_H1 L0_CLKOUT_L1

Y1 W1 Y4 Y3

L0_CTLOUT_H0 L0_CTLOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1

R2 R3 T5 R5

2 4.7U_0805_10V4Z If VLDT is connected only on one side, one 4.7uF cap should be added to the island side.

H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15

2

+5VS

11/14 update H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1

PWM Fan Control circuit



JP2

1

VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3

H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15



HT LINK

D1 D2 D3 D4

1 D1 CH751H-40PT_SOD323-2



2

1

C8 4.7U_0805_10V4Z

C9 0.1U_0402_16V4Z

2

2

VLDT=500mA

1

1 2 5 6

Athlon 64 S1 Processor Socket

D Q1

@ D2

G FAN_PWM

RLZ5.1B_LL34

3

S

SI3456BDV-T1-E3_TSOP6

3

Change PCB Footprint from ACES_85204-02001_2P to ACES_88231-02001_2P

4

GND GND

2

9/20 SP07000DM00/SP07000EQ00

1 2

3 4

ACES_88231-02001 CONN@

+VCC_FAN FOX_PZ6382A-284S-41F_GRIFFIN CONN@

1 2

4

4

Compal Secret Data

Security Classification 2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Compal Electronics, Inc. AMD CPU S1G2 HT I/F

Size Document Number Custom LA-4111P Date:

Rev 0.2 Sheet

Friday, November 30, 2007 E

4

of

48

A

B

C

D

E

Processor DDR2 Memory Interface PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH

1

1

DDR_A_CLK#0

2

C10 1.5P_0402_50V9C

DDR_A_CLK1 1

DDR_A_CLK#1

2

C11 1.5P_0402_50V9C +1.8V

1

2

R1 C14 1.5P_0402_50V9C

1K_0402_1% 1

DDR_B_CLK#0

+MCH_REF

2

DDR_B_CLK1 1

2

R2 C15 1.5P_0402_50V9C

C12

1K_0402_1% 1

DDR_B_CLK#1

09/13 update

2

DDR_B_CLK0

1

C13

1

2 2 1000P_0402_25V8J 0.1U_0402_16V4Z

2

+0.9V

+0.9V JCPUB

Place them close to CPU within 1"

+1.8V

R4 1 1 R3

39.2_0402_1% 2 2 39.2_0402_1%

DDR_A_ODT0 DDR_A_ODT1



DDR_CS0_DIMMA# DDR_CS1_DIMMA#



DDR_CKE0_DIMMA DDR_CKE1_DIMMA

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1

3

DDR_A_MA[15..0]



DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2



DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

VTT1 VTT2 VTT3 VTT4

AF10 AE10

MEMZP MEMZN

MEM:CMD/CTRL/CLK VTT5 VTT6 VTT7 VTT8 VTT9

H16

RSVD_M1

T19 V22 U21 V19

MA0_ODT0 MA0_ODT1 MA1_ODT0 MA1_ODT1

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

T20 U19 U20 V20

MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1

DDR_CKE0_DIMMA DDR_CKE1_DIMMA

J22 J20

MA_CKE0 MA_CKE1

T2

D10 C10 B10 AD10

PAD

DDR_A_ODT0 DDR_A_ODT1

W10 AC10 AB10 AA10 A10

VTT_SENSE

Y10

MEMVREF

W17

VTT_SENSE +MCH_REF

RSVD_M2

B18

MB0_ODT0 MB0_ODT1 MB1_ODT0

W26 W23 Y26

DDR_B_ODT0 DDR_B_ODT1

MB0_CS_L0 MB0_CS_L1 MB1_CS_L0

V26 W25 U22

DDR_CS0_DIMMB# DDR_CS1_DIMMB#

MB_CKE0 MB_CKE1

J25 H26

DDR_CKE0_DIMMB DDR_CKE1_DIMMB

MA_CLK_H5 MA_CLK_L5 MA_CLK_H1 MA_CLK_L1 MA_CLK_H7 MA_CLK_L7 MA_CLK_H4 MA_CLK_L4

MB_CLK_H5 MB_CLK_L5 MB_CLK_H1 MB_CLK_L1 MB_CLK_H7 MB_CLK_L7 MB_CLK_H4 MB_CLK_L4

P22 R22 A17 A18 AF18 AF17 R26 R25

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

N21 M20 N22 M19 M22 L20 M24 L21 L19 K22 R21 L22 K20 V24 K24 K19

MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15

P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2

R20 R23 J21

MA_BANK0 MA_BANK1 MA_BANK2

MB_BANK0 MB_BANK1 MB_BANK2

R24 U26 J26

DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

R19 T22 T24

MA_RAS_L MA_CAS_L MA_WE_L

MB_RAS_L MB_CAS_L MB_WE_L

U25 U24 U23

DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

T1

09/13 update PAD

N19 N20 E16 F16 Y16 AA16 P19 P20

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1

PAD

T3 DDR_B_ODT0 DDR_B_ODT1



DDR_CS0_DIMMB# DDR_CS1_DIMMB#



DDR_CKE0_DIMMB DDR_CKE1_DIMMB



DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1 DDR_B_MA[15..0]

DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2



DDR_B_RAS# DDR_B_CAS# DDR_B_WE#













DDR_B_DM[7..0]

DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7

MEM:DATA DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11 Y11 AE14 AF14 AF11 AD11

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

A12 B16 A22 E25 AB26 AE22 AC16 AD12

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7

C12 B12 D16 C16 A24 A23 F26 E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12

MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7

FOX_PZ6382A-284S-41F_GRIFFIN Athlon 64 S1 Processor Socket

4

1

JCPUC

DDR_B_D[63..0]

DDR_A_CLK0

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12

DDR_A_D[63..0]

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

E12 C15 E19 F24 AC24 Y19 AB16 Y13

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7

G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13

DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7

2

3

DDR_A_DM[7..0]

DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7













FOX_PZ6382A-284S-41F_GRIFFIN Athlon 64 S1 Processor Socket

4

CONN@

A

B

C

D

l.c ai

Compal Electronics, Inc. ho

AMD CPU S1G2 DDRII I/F Date:

Rev 0.2

f@

Size Document Number Custom LA-4111P

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Friday, November 30, 2007

Sheet E

xa

2008/08/02

Deciphered Date

5

he

2007/08/02

Issued Date

tm

Compal Secret Data

Security Classification

om

CONN@

of

48

B

C

D

+2.5VDDA VDDA=300mA L1 3300P_0402_50V7K 1 2 FBM_L11_201209_300L_0805 1 1 1 1 + 4.7U_0805_10V4Z C17 C18 C19 0.22U_0603_16V4Z 2 2 2 2

+2.5VS

A:Need to re-Link "SGN00000200"

+1.8V

R10

1

1 R5

2 10K_0402_5% 2 300_0402_5%

@ R6 1

B

C16 100U_D2_10VM

E

11/13 update

0_0402_5% 2

ENTRIP2

2

A

E

Q3 CPU_THERMTRIP#_R 3 1 MMBT3904_NL_SOT23-3 C

1 R16 1 R7

2 0_0402_5% 2 0_0402_5%

H_THERMTRIP#_EC H_THERMTRIP#



JCPUD

C20

LDT_RST# H_PWRGD_CPU LDT_STOP# CPU_LDT_REQ#

B7 A7 F10 C6

RESET_L PWROK LDTSTOP_L LDTREQ_L

CPU_SIC CPU_SID

AF4 AF5 AE6

SIC SID ALERT_L

R6 P6

HT_REF0 HT_REF1

R8 169_0402_1%

0718 Silego -- 216 ohm

CLK_CPU_BCLK#

C21

1

2 3900P_0402_50V7K

Address:100_1100

+1.2V_HT

R13 R14

1 1

2 44.2_0402_1% CPU_HTREF0 2 44.2_0402_1% CPU_HTREF1

2

2

1

R15 300_0402_5%

LDT_RST# 1

2

T4

+CPU_CORE_0 R487 10_0402_5% 1 2CPU_VDD0_FB_H 1 2CPU_VDD0_FB_L R486 10_0402_5%

C22 0.01U_0402_25V4Z @

CPU_VDD1_FB_H CPU_VDD1_FB_L

CPU_VDD1_FB_H Y6 CPU_VDD1_FB_L AB6

VDD1_FB_H VDD1_FB_L

VDDNB_FB_H VDDNB_FB_L

H6 G6

PAD

T9 PAD T11 PAD

CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1 CPU_TEST22_SCANSHIFTEN CPU_TEST12_SCANSHIFTENB CPU_TEST27_SINGLECHAIN R25

2 0_0402_5%

+1.8VS 2 1

H_PWRGD_CPU

2

+3VS

H_PWRGD_CPU

E9 E8

TEST21 TEST20 TEST24 TEST22 TEST12 TEST27

C2 AA6

TEST9 TEST6

A3 A5 B3 B5 C1

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5

2

1

+1.8V CPU_SVC CPU_SVD

09/11 update

09/19 update PAD PAD

T42 T43

VDD_NB_FB_H VDD_NB_FB_L

DBREQ_L

E10

CPU_DBREQ#

TDO

AE9

CPU_TDO

R22 1 1 R23

1K_0402_5% 2 2 1K_0402_5%

+CPU_CORE_NB R484 10_0402_5% VDD_NB_FB_H 1 2 VDD_NB_FB_L 1 2 R485 10_0402_5%

Close to CPU

J7 H8

CPU_TEST28_H_PLLCHRZ_P CPU_TEST28_L_PLLCHRZ_N

TEST17 TEST16 TEST15 TEST14

D7 E7 F7 C7

CPU_TEST17_BP3 CPU_TEST16_BP2 CPU_TEST15_BP1 CPU_TEST14_BP0

TEST7 TEST10

C3 K8

TEST8

C4

TEST29_H TEST29_L

C9 C8

RSVD10 RSVD9 RSVD8 RSVD7 RSVD6

+1.8V sense no support

VDD_NB_FB_H VDD_NB_FB_L

TEST28_H TEST28_L

TEST25_H TEST25_L

AB8 AF7 AE7 AE8 AC8 AF8

+1.8V

R17 2

THERMDC_CPU THERMDA_CPU

PAD PAD PAD PAD PAD PAD

T5 T6

route as differential as short as possible testpoint under package

2

T7 T8 T10 T12

CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N

PAD PAD

T13 T14

H18 H19 AA7 D5 C5

FOX_PZ6382A-284S-41F_GRIFFIN CONN@

1

34.8K_0402_1%~N

2.09V for Gate

C23 G

2

TEST18 TEST19

CPU_THERMTRIP#_R CPU_PROCHOT#_1.8 CPU_MEMHOT#_1.8V

3 1 R59

2

1

TEST23

H10 G9

R814 1

20K_0402_5%

11/30 update

2

C939 0.1U_0402_16V4Z

AD7

CPU_PROCHOT#_1 .8

0.1U_0402_16V7K

+1.8VS 2

CPU_SIC

3

1

SMB_EC_DA2

SMB_EC_DA2

SMB_EC_CK2

3

Q127 FDV301N_NL_SOT23-3 G

+1.8V

FDV301N_NL_SOT23-3 Q129 3

1 SMB_EC_CK2 D

S

R36 300_0402_5%

CPU_SID R18 2 1 390_0402_5% R19 2 1 390_0402_5%

D

+1.8V

S

3

2

CPU_TEST23_TSTUPD

1

@ MMBT3904_NL_SOT23-3 Q2 1 H_PROCHOT# 2 0_0402_5%

0718 AMD --> 1K ohm



CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1

1

W7 W8

W9 Y9

1

R175

THERMDC THERMDA

VDDIO_FB_H VDDIO_FB_L

DBRDY TMS TCK TRST_L TDI



@ 300_0402_5%

VDD0_FB_H VDD0_FB_L

+CPU_CORE_1 R489 10_0402_5% 1 2CPU_VDD1_FB_H 1 2CPU_VDD1_FB_L

R21 300_0402_5%

AF6 AC7 AA8

F6 E6

R488 10_0402_5%

09/13 update

THERMTRIP_L PROCHOT_L MEMHOT_L

CPU_VDD0_FB_H CPU_VDD0_FB_L

G10 AA9 AC9 AD9 AF9

CPU_SVC CPU_SVD

1 @ 10K_0402_5% 2 300_0402_5%

11/22 update

CPU_VDD0_FB_H CPU_VDD0_FB_L

Close to CPU

LDT_RST#

SVC SVD



CPU_ DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI +1.8VS

CLKIN_H CLKIN_L

CPU_SVC CPU_SVD

A6 A4

2 R11 1 R9

+1.8V

M11 W18

C

1

CLK_CPU_BCLK

A9 A8

KEY1 KEY2

E

CPU_CLKIN_SC_P CPU_CLKIN_SC_N

2 3900P_0402_50V7K

1

VDDA1 VDDA2

2

Place close to CPU wihtin 1.5"

B

F8 F9

2

1

+1.8V

+3VS

0718 AMD , need check with AMD

2

+1.8VS

4

1

R30 300_0402_5% CPU_LDT_REQ#

1

2

C27 1 CPU_LDT_REQ#

C24 0.01U_0402_25V4Z @

FDV301N, the Vgs is: min = 0.65V Typ = 0.85V Max = 1.5V

+1.8V

C26 2 U2 1

THERMDC_CPU 3 2 2200P_0402_50V7K 4

2200p change to 1000p for ADT7421

SCLK

8

SMB_EC_CK2

D+

SDATA

7

SMB_EC_DA2

D-

ALERT#

6

GND

5

VDD

THERM#

R24

1

CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1 CPU_TEST22_SCANSHIFTEN CPU_TEST12_SCANSHIFTENB CPU_TEST15_BP1 CPU_TEST14_BP0 CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1

R26 R27 R28 R29 R31 R32 R33 R34 R35

1 2 2 2 2 2 2 2 2

2 @ 300_0402_5%

09/11 update

1

THERMDA_CPU 2

CPU_TEST27_SINGLECHAIN

ADM1032ARMZ-2REEL_MSOP8

CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO

NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.

HDT Connector JP3 1 3 5 7 9 11 13 15 17 19 21 23

2 4 6 8 10 12 14 16 18 20 22 24 26

2 1 1 1 1 1 1 1 1

@ 300_0402_5% @ 300_0402_5% @ 300_0402_5% @ 300_0402_5% @ 300_0402_5% @ 300_0402_5% @ 300_0402_5% @ 300_0402_5% @ 300_0402_5%

+3VS 5

C25 0.01U_0402_25V4Z @

U1 HDT_RST#

4

P

2

LDT_STOP#

B

2

G

1

A

1

Y 3

LDT_STOP#

2 1 @ 220_0402_5% R37 2 1 @ 220_0402_5% R38 2 1 @ 220_0402_5% R39 2 1 @ 220_0402_5% R40 2 1 @ 220_0402_5% R41

0.1U_0402_16V4Z

1

EC is PU to 5VALW

@ SAMTEC_ASP-68200-07

LDT_RST# SB_PWRGD

4

@ NC7SZ08P5X_NL_SC70-5

9/20 SP020016900 Address:100_1101

Compal Secret Data

Security Classification 2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Compal Electronics, Inc. AMD CPU S1G2 CTRL

Size Document Number Custom LA-4111P Date:

Rev 0.2

Friday, November 30, 2007

Sheet E

6

of

48

A

B

C

D

L

VDD(+CPU_CORE) decoupling. +CPU_CORE_0

1

+

18A/720mil/36vias

1

+

C30 330U_X_2VM_R6M

2

+

C28 330U_X_2VM_R6M

2

1 C31 330U_X_2VM_R6M

2

+

C29 330U_X_2VM_R6M

2

Near CPU Socket +CPU_CORE_0

+CPU_CORE_1

L

?A/?mil/?vias +CPU_CORE_NB

1

C32 22U_0805_6.3V6M

2

1

C33 22U_0805_6.3V6M

2

1

C34 22U_0805_6.3V6M

2

1

C35 22U_0805_6.3V6M

1

2

1

C36 22U_0805_6.3V6M

2

2

+CPU_CORE_0

1

C38 22U_0805_6.3V6M

2

1

C39 22U_0805_6.3V6M

2

+1.8V

+CPU_CORE_1

C40 0.22U_0603_16V4Z

2

C37 22U_0805_6.3V6M

1

1

C41 0.01U_0402_25V4Z

2

1

1

C42 180P_0402_50V8J

2

C43 0.22U_0603_16V4Z

2

1

C44 0.01U_0402_25V4Z

2

1

?A/?mil/?vias

L

L

+CPU_CORE_0

+CPU_CORE_1

1 1

E

C45 180P_0402_50V8J

2

Under CPU Socket 2

18A/720mil/36vias

JCPUE G4 H2 J9 J11 J13 J15 K6 K10 K12 K14 L4 L7 L9 L11 L13 L15 M2 M6 M8 M10 N7 N9 N11

VDD0_1 VDD0_2 VDD0_3 VDD0_4 VDD0_5 VDD0_6 VDD0_7 VDD0_8 VDD0_9 VDD0_10 VDD0_11 VDD0_12 VDD0_13 VDD0_14 VDD0_15 VDD0_16 VDD0_17 VDD0_18 VDD0_19 VDD0_20 VDD0_21 VDD0_22 VDD0_23

K16 M16 P16 T16 V16

VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5

H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17

VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12

VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8 VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26

P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2

VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13

Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18

+CPU_CORE_1

+1.8V

FOX_PZ6382A-284S-41F_GRIFFIN Athlon 64 S1 Processor Socket

CONN@

+CPU_CORE_NB VDDIO decoupling.

+CPU_CORE_NB

1

+1.8V

C52 22U_0805_6.3V6M

2 1

C46 22U_0805_6.3V6M

2

1

C47 22U_0805_6.3V6M

1

1

C48

1

C49

1

C50

1

C53 22U_0805_6.3V6M

2

1

C54 22U_0805_6.3V6M

2

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65

VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129

J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6

1

2

FOX_PZ6382A-284S-41F_GRIFFIN Athlon 64 S1 Processor Socket

C51

CONN@ 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J 2 2 2 2

2

+0.9V

Under CPU Socket

3

decoupling.

JCPUF AA4 AA11 AA13 AA15 AA17 AA19 AB2 AB7 AB9 AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21 AD6 AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23 B4 B6 B8 B9 B11 B13 B15 B17 B19 B21 B23 B25 D6 D8 D9 D11 D13 D15 D17 D19 D21 D23 D25 E4 F2 F11 F13 F15 F17 F19 F21 F23 F25 H7 H9 H21 H23 J4

3

Near Power Supply

VTT decoupling.

1

C: Change to NBO CAP

+ C59 220U_Y_4VM 2

Between CPU Socket and DIMM +1.8V +0.9V 1

1

C55 0.22U_0603_16V4Z

2

C56 0.22U_0603_16V4Z

2

C57 0.22U_0603_16V4Z

2

+1.8V

1

1

1

2

1

C61 0.01U_0402_25V4Z

2

C58 0.22U_0603_16V4Z 1

2

+1.8V

C60 0.01U_0402_25V4Z

1

2

180PF Qt'y follow the distance between CPU socket and DIMM0. 1

C62 180P_0402_50V8J

2

1

C63 180P_0402_50V8J

2

C64 180P_0402_50V8J

2

1

C67 4.7U_0805_10V4Z

2

1

C68 0.22U_0603_16V4Z

2

1

C69 0.22U_0603_16V4Z

2

1

C70 1000P_0402_25V8J

2

1

C71 1000P_0402_25V8J

2

1

C72 180P_0402_50V8J

2

1

C73 180P_0402_50V8J

2

Near CPU Socket Right side. C65 180P_0402_50V8J

+0.9V

2

A: Add C165 and C176 to follow AMD Layout review recommand for EMI

+1.8V

1

C66 4.7U_0805_10V4Z

1

1

C79 4.7U_0805_10V4Z

2

C80 4.7U_0805_10V4Z

2

1

C81 0.22U_0603_16V4Z

2

1

C82 0.22U_0603_16V4Z

2

1

C83 1000P_0402_25V8J

2

1

C84 1000P_0402_25V8J

2

1

C85 180P_0402_50V8J

2

1

C86 180P_0402_50V8J

2

4

4

+ C78 220U_Y_4VM @

Near CPU Socket Left side.

2

Compal Secret Data

Security Classification 2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Compal Electronics, Inc.

l.c

C77 4.7U_0805_10V4Z

ai

2

tm

C76 4.7U_0805_10V4Z

AMD CPU S1G2 PWR & GND ho

2

Size Document Number Custom LA-4111P Date:

Rev 0.2

f@

C75 4.7U_0805_10V4Z

C: Change to NBO CAP

in

2

1

Friday, November 30, 2007

Sheet E

xa

C74 4.7U_0805_10V4Z

1

7

he

2

1

om

1 1

of

48

A

B

C

D

E

+V_DDR_MCH_REF +1.8V

DDR_A_D0 DDR_A_D1 DDR_A_DQS#0 DDR_A_DQS0

1

DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1

VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

DDR_A_D[0..63]

DDR_A_DM[0..7]

DDR_A_DM[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

DDR_A_DQS#[0..7]

DDR_A_DM0 DDR_A_DQS[0..7] DDR_A_D6 DDR_A_D7

DDR_A_MA[0..15] DDR_A_DQS#[0..7]

DDR_A_D12 DDR_A_D13

DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6

8 7 6 5

DDR_CKE0_DIMMA DDR_A_BS#2 DDR_CKE1_DIMMA DDR_A_MA15

DDR_A_DM1 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_D14 DDR_A_D15

+1.8V

DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 2

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2

DDR_CKE0_DIMMA DDR_A_BS#2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1



DDR_A_BS#0 DDR_A_WE#



DDR_A_CAS# DDR_CS1_DIMMA#

DDR_A_ODT1

DDR_A_MA10 DDR_A_BS#0 DDR_A_WE# DDR_A_CAS# DDR_CS1_DIMMA# DDR_A_ODT1 DDR_A_D32 DDR_A_D33 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35

3

DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59

4

SMB_CK_DAT0 SMB_CK_CLK0 +3VS

1 C103 0.1U_0402_16V4Z

2

VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1

42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

R43 1K_0402_1%

DDR_A_D20 DDR_A_D21 +V_DDR_MCH_REF

+V_DDR_MCH_REF

DDR_A_DM2 DDR_A_D22 DDR_A_D23

C95

1

C96

2 1000P_0402_25V8J

DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3

1

R44 1K_0402_1%

2

DDR_A_D30 DDR_A_D31 DDR_CKE1_DIMMA

DDR_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6

C88

1 1

2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1

C90 C89

C91 C92

C93 C94

1 1

1 1

1 1

2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

47_0804_8P4R_5% RP5 8 1 7 2 6 3 5 4

DDR_A_ODT1 DDR_CS1_DIMMA# DDR_A_WE# DDR_A_CAS#

47_0804_8P4R_5% RP6 8 1 7 2 6 3 5 4

1 C100 1 C99

2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

47_0804_8P4R_5% RP7 DDR_CS0_DIMMA# 8 1 DDR_A_RAS# 7 2 DDR_A_MA13 6 3 DDR_A_ODT0 5 4

1 C102 1 C101

2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

C98 C97

1 1

2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

2

47_0804_8P4R_5%

Cross between +1.8V and +0.9V power plan DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# DDR_A_ODT0 DDR_A_MA13

DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# DDR_A_ODT0

DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 3

DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63

4

FOX_AS0A426-N8RN-7F CONN@

9/20 SP07000BZ00/SP07000EU00 DDR2 SOCKET H9.2 (REV)

Compal Secret Data

Security Classification 2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

C87

DDR_A_BS#0 DDR_A_MA10 DDR_A_MA1 DDR_A_MA3

0.1U_0402_16V4Z

09/13 update

47_0804_8P4R_5% RP2 8 1 7 2 6 3 5 4

47_0804_8P4R_5% RP4 8 1 7 2 6 3 5 4

DDR_A_MA5 DDR_A_MA8 DDR_A_MA9 DDR_A_MA12

1

VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD

2

DDR_A_DQS#2 DDR_A_DQS2

41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199

1 2 3 4

47_0804_8P4R_5% RP3 8 1 7 2 6 3 5 4

DDR_A_MA4 DDR_A_MA2 DDR_A_BS#1 DDR_A_MA0

1

DDR_A_D16 DDR_A_D17

+1.8V

+0.9V RP1 DDR_A_D[0..63]

DDR_A_D4 DDR_A_D5

2

DDR_A_D10 DDR_A_D11

+1.8V

JP4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

B

C

D

Title

Compal Electronics, Inc. DDRII SO-DIMM 0

Size Document Number Custom LA-4111P Date:

Rev 0.2 Sheet

Friday, November 30, 2007 E

8

of

48

A

B

C

+1.8V

D

E

+1.8V 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

+V_DDR_MCH_REF DDR_B_D0 DDR_B_D1 C104

1

2 1000P_0402_25V8J

1

DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D13 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11

+1.8V

+0.9V

JP5

RP8

VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

DDR_B_D[0..63] DDR_B_D4 DDR_B_D5

DDR_B_DM[0..7]

DDR_B_DM0

DDR_B_DQS[0..7]

DDR_B_D6 DDR_B_D7

DDR_B_MA[0..15] DDR_B_DQS#[0..7]

DDR_B_D12 DDR_B_D9

DDR_B_D[0..63]

DDR_B_MA6 DDR_B_MA2 DDR_B_MA0 DDR_CS0_DIMMB#

DDR_B_DM[0..7]

DDR_B_DQS[0..7]

DDR_B_MA[0..15]

DDR_B_DQS#[0..7]

8 7 6 5

1 2 3 4

2 C105 1 C106

1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

2 C108 1 C107

1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

2 C109 1 C110

1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

2 C111 1 C112

1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

2 C114 1 C113

1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

2 C116 1 C115

1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

2 C118 1 C117

1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

47_0804_8P4R_5% RP9 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA4

8 7 6 5

DDR_B_DM1

1 2 3 4

1

47_0804_8P4R_5% DDR_B_CLK0 DDR_B_CLK#0

RP10 DDR_B_BS#2 DDR_CKE0_DIMMB DDR_B_MA15 DDR_CKE1_DIMMB

DDR_B_D14 DDR_B_D15

8 7 6 5

1 2 3 4

47_0804_8P4R_5% 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201

DDR_B_D21 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25 DDR_B_DM3 DDR_B_D26 DDR_B_D27 2



DDR_CKE0_DIMMB DDR_B_BS#2

DDR_CKE0_DIMMB DDR_B_BS#2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1



DDR_B_BS#0 DDR_B_WE#



DDR_B_CAS# DDR_CS1_DIMMB#

DDR_B_ODT1

DDR_B_MA10 DDR_B_BS#0 DDR_B_WE# DDR_B_CAS# DDR_CS1_DIMMB# DDR_B_ODT1 DDR_B_D32 DDR_B_D33 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35

3

DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 DDR_B_DM7 DDR_B_D58 DDR_B_D59

SMB_CK_DAT0 SMB_CK_CLK0 +3VS

4

C119 0.1U_0402_16V4Z

1

VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND

VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 GND

42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202

DDR_B_D20 DDR_B_D16

RP11 DDR_B_MA5 DDR_B_MA8 DDR_B_MA9 DDR_B_MA12

DDR_B_DM2 DDR_B_D22 DDR_B_D23

8 7 6 5

1 2 3 4

47_0804_8P4R_5% RP12

DDR_B_D28 DDR_B_D29

DDR_B_MA10 DDR_B_BS#0 DDR_B_MA1 DDR_B_MA3

DDR_B_DQS#3 DDR_B_DQS3

8 7 6 5

1 2 3 4

47_0804_8P4R_5% DDR_B_D30 DDR_B_D31

RP13

DDR_CKE1_DIMMB

DDR_CKE1_DIMMB

DDR_B_ODT1 DDR_CS1_DIMMB# DDR_B_CAS# DDR_B_WE#

DDR_B_MA15 DDR_B_MA14

8 7 6 5

1 2 3 4

2

47_0804_8P4R_5% DDR_B_MA11 DDR_B_MA7 DDR_B_MA6

RP14 DDR_B_RAS# DDR_B_BS#1 DDR_B_ODT0 DDR_B_MA13

DDR_B_MA4 DDR_B_MA2 DDR_B_MA0

8 7 6 5

1 2 3 4

47_0804_8P4R_5% DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB# DDR_B_ODT0 DDR_B_MA13

Cross between +1.8V and +0.9V power plan

DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB# DDR_B_ODT0

DDR_B_D36 DDR_B_D37 DDR_B_DM4

09/26 update

DDR_B_D38 DDR_B_D39

DDR_B_D21 swap with DDR_B_D16 DDR_B_D13 swap with DDR_B_D9

DDR_B_D44 DDR_B_D45

3

DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_CLK1 DDR_B_CLK#1 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 +3VS

4

TYCO_292527-4 CONN@

2

A

B

C

D

DDRII SO-DIMM 1 Date:

l.c ai Rev 0.2

f@

Size Document Number Custom LA-4111P

tm

Compal Electronics, Inc. in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Friday, November 30, 2007

Sheet E

xa

2008/08/02

Deciphered Date

9

he

2007/08/02

Issued Date

ho

Compal Secret Data

Security Classification

om

9/20 SP07000ET00/SP07000GN00

of

48

A

B

C

D

E

U3B

PCIE_PTX_C_IRX_P0 PCIE_PTX_C_IRX_N0 PCIE_PTX_C_IRX_P1 PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_P2 PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P3 PCIE_PTX_C_IRX_N3

2



PCIE_PTX_C_IRX_P5 PCIE_PTX_C_IRX_N5





SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N

AE3 AD4 AE2 AD3 AD1 AD2 V5 W6 U5 U6 U8 U7

GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N GPP_RX4P GPP_RX4N GPP_RX5P GPP_RX5N

AA8 Y8 AA7 Y7 AA5 AA6 W5 Y5

SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N

PART 2 OF 6

GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N

A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2

GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N

AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2

SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N

AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5

PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN)

AC8 AB8

PCIE I/F

PCIE I/F SB

TMDS_B_DATA2 TMDS_B_DATA2# TMDS_B_DATA1 TMDS_B_DATA1# TMDS_B_DATA0 TMDS_B_DATA0# TMDS_B_CLK TMDS_B_CLK# 1

PCIE_ITX_PRX_P0 PCIE_ITX_PRX_N0 PCIE_ITX_PRX_P1 PCIE_ITX_PRX_N1 PCIE_ITX_PRX_P2 PCIE_ITX_PRX_N2 PCIE_ITX_PRX_P3 PCIE_ITX_PRX_N3

C152 C153 C154 C155 C156 C157 C158 C159

PCIE_ITX_PRX_P5 PCIE_ITX_PRX_N5

C160 1 C161 1

SB_TX0P_C SB_TX0N_C SB_TX1P_C SB_TX1N_C SB_TX2P_C SB_TX2N_C SB_TX3P_C SB_TX3N_C R55 R56

C162 C163 C164 C165 C166 C168 C169 C167

1 1 1 1 1 1 1 1

1 1

2 2

1

0.1U_0402_16V7K 2 0.1U_0402_16V7K 0.1U_0402_16V7K 2 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 0.1U_0402_16V7K

PCIE_ITX_C_PRX_P0 PCIE_ITX_C_PRX_N0 PCIE_ITX_C_PRX_P1 PCIE_ITX_C_PRX_N1 PCIE_ITX_C_PRX_P2 PCIE_ITX_C_PRX_N2 PCIE_ITX_C_PRX_P3 PCIE_ITX_C_PRX_N3







0.1U_0402_16V7K 2 0.1U_0402_16V7K

PCIE_ITX_C_PRX_P5 PCIE_ITX_C_PRX_N5



2 1

1

2 1

1 1 1 1

2 2 2 2 2 2 2 2

2

0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K

1.27K_0402_1% 2K_0402_1%

SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N

New Card CardReader WLAN LAN10/100

H_CADOP[0..15]

TV Tuner

H_CADON[0..15]







H_CADOP[0..15]

H_CADIP[0..15]

H_CADON[0..15]

H_CADIN[0..15]

H_CADIP[0..15]

H_CADIN[0..15]

2

U3A

+1.1VS

RS780M_FCBGA528 RS780M Display Port Support (muxed on GFX) GFX_TX0,TX1,TX2 and TX3 DP0 AUX0 and HPD0 GFX_TX4,TX5,TX6 and TX7 DP1 AUX1 and HPD1

9/20 SA00001ZG00(A11) S IC 216-0674001-00/RS780M FCBGA528P 0FH 3



H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1



H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 1 R57

H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7

Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25

H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15

AC24 AC25 AB25 AB24 AA24 AA25 Y22 Y23 W21 W20 V21 V20 U20 U21 U19 U18

HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N

T22 T23 AB23 AA22

HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N

M22 M23 R21 R20

H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1

2 301_0402_1% C23 A24

HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N

D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22

H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7

HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N

F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18

H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15

HT_TXCLK0P HT_TXCLK0N HT_TXCLK1P HT_TXCLK1N

H24 H25 L21 L20

HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N

HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N

M24 M25 P19 R18

HT_RXCALP HT_RXCALN

HT_TXCALP HT_TXCALN

B24 B25

HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N

PART 1 OF 6

HYPER TRANSPORT CPU I/F







GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N

PCIE I/F GFX

1

D4 C4 A3 B3 C2 C1 E5 F5 G5 G6 H5 H6 J6 J5 J7 J8 L5 L6 M8 L8 P7 M7 P5 M5 R8 P8 R6 R5 P4 P3 T4 T3

RS780M_FCBGA528

0718 Place within 1" layout 1:2

H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1

3

H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1



H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1



1 R58

2 301_0402_1%

0718 Place within 1" layout 1:2

NEED CHECK R68 & R69 WITH AMD 4

4

Compal Secret Data

Security Classification 2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Compal Electronics, Inc. RS780-HT/PCIE

Size Document Number Custom LA-4111P Date:

Rev 0.2 Sheet

Friday, November 30, 2007 E

10

of

48

A

B

C

D

E

1

1

+3VS L2 AVDD=100mA 1 2 +AVDD1 BLM18PG121SN1D_0603 1 L4 +AVDD2 C170 +1.8VS 2.2U_0603_6.3V4Z 0_0603_5% 1 2 L6 +AVDDQ C172 1 2 BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z U3C 2 F12 AVDD1(NC) 1 E12 AVDD2(NC) C175 F14 AVDDDI(NC) 2.2U_0603_6.3V4Z G15 AVSSDI(NC) 2 H15 AVDDQ(NC) H14 AVSSQ(NC) +1.8VS

R68

CPU_LDT_REQ#

1

2

NB_ALLOW_LDTSTOP

0_0402_5%

T46 T47 T48

PAD PAD PAD

11/05 update

+1.1VS

2

+1.8VS

1 R62 1 R63 1 R64

RED 2 150_0402_1% GREEN 2 150_0402_1% BLUE 2 150_0402_1%

L9 1 2 BLM18PG121SN1D_0603 1 L7 C178

RED

GREEN

BLUE

1 2 BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z 1 2 L10 C176 +NB_PLLVDD 1 2 +NB_HTPVDD BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z 1 2 +1.8VS L11 C179 1 2 +VDDA18HTPLL BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z 1 2 C180 2.2U_0603_6.3V4Z

Install when SB700 A12 use

CRT_HSYNC CRT_VSYNC

R65

11/13 update

1 2 R71 4.7K_0402_5%

1 2 R72 4.7K_0402_5%



G18 G17 E18 F18 E19 F19

RED(DFT_GPIO0) REDb(NC) GREEN(DFT_GPIO1) GREENb(NC) BLUE(DFT_GPIO3) BLUEb(NC)

A11 B11 F8 E8

DAC_HSYNC(PWM_GPIO4) DAC_VSYNC(PWM_GPIO6) DAC_SCL(PCE_RCALRN) DAC_SDA(PCE_TCALRN)

2 715_0402_1% G14

1

PLLVDD(NC) PLLVDD18(NC) PLLVSS(NC)

H17

VDDA18HTPLL

SYSRESETb POWERGOOD LDTSTOPb ALLOW_LDTSTOP

CLK_NBHT CLK_NBHT#

C25 C24

HT_REFCLKP HT_REFCLKN

NB_OSC_14.318M

E11 F11

REFCLK_P/OSCIN(OSCIN) REFCLK_N(PWM_GPIO3)

1 R371

NBGFX_CLK NBGFX_CLK#

CLK_SBLINK_BCLK CLK_SBLINK_BCLK#

LCD_DDC_CLK LCD_DDC_DAT HDMIDAT_UMA HDMICLK_UMA RS780_DFT_GPIO_0 +3VS

Strap pin

2 1 R88 10K_0402_5%

AUX_CAL

T2 T1

GFX_REFCLKP GFX_REFCLKN

U1 U2

GPP_REFCLKP GPP_REFCLKN

V4 V3

GPPSB_REFCLKP(SB_REFCLKP) GPPSB_REFCLKN(SB_REFCLKN)

B9 A9 B8 A8 B7 A7

I2C_CLK I2C_DATA DDC_DATA0/AUX0N(NC) DDC_CLK0/AUX0P(NC) DDC_CLK1/AUX1P(NC) DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

Strap pin

A22 B22 A21 B21 B20 A20 A19 B19

LVDS_A0+ LVDS_A0- LVDS_A1+ LVDS_A1- LVDS_A2+ LVDS_A2-

TXOUT_U0P(NC) TXOUT_U0N(NC) TXOUT_U1P(PCIE_RESET_GPIO3) TXOUT_U1N(PCIE_RESET_GPIO2) TXOUT_U2P(NC) TXOUT_U2N(NC) TXOUT_U3P(PCIE_RESET_GPIO5) TXOUT_U3N(NC)

B18 A18 A17 B17 D20 D21 D18 D19

LVDS_B0+ LVDS_B0- LVDS_B1+ LVDS_B1- LVDS_B2+ LVDS_B2-

TXCLK_LP(DBG_GPIO1) TXCLK_LN(DBG_GPIO3) TXCLK_UP(PCIE_RESET_GPIO4) TXCLK_UN(PCIE_RESET_GPIO1)

B16 A16 D16 D17

LVDS_ACLK+ LVDS_ACLK- LVDS_BCLK+ LVDS_BCLK-

VDDLTP18(NC) VSSLTP18(NC)

A13 B13

+VDDLTP18

VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC)

A15 B15 A14 B14

+VDDLT18

VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)

C14 D15 C16 C18 C20 E20 C22

LVDS_DIGON(PCE_TCALRP) LVDS_BLON(PCE_RCALRP) LVDS_ENA_BL(PWM_GPIO2)

E9 F7 G12

DAC_RSET(PWM_GPIO1)

A12 D14 B12

D8 A10 C10 C12

R66 0_0402_5% 1 2 NB_RESET# NB_PW RGD NB_LDTSTOP# NB_ALLOW_LDTSTOP 2 10K_0402_5%

3



C_Pr(DFT_GPIO5) Y(DFT_GPIO2) COMP_Pb(DFT_GPIO4)

VDDA18PCIEPLL1 VDDA18PCIEPLL2

+1.8VS

E17 F17 F15

D7 E7



+1.1VS

GREEN BLUE

+VDDA18PCIEPLL 2 PLT_RST# NB_PWRGD

L

RED

CRT_HSYNC CRT_VSYNC UMA_CRT_CLK UMA_CRT_DAT

+1.8VS

TV_CRMA TV_LUMA TV_COMPS

TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC) TXOUT_L2N(DBG_GPIO0) TXOUT_L3P(NC) TXOUT_L3N(DBG_GPIO2)

PART 3 OF 6

CRT/TVOUT

NB_LDTSTOP#

2

0_0402_5%

PLL PWR LVTM

1

LDT_STOP#

PM

R67

CLOCKs

11/13 update

2

L3 1 2 BLM18PG121SN1D_0603

1

1 C173 0.1U_0402_16V4Z

C171 2.2U_0603_6.3V4Z 2 L5 1 2 BLM18PG121SN1D_0603 1

2

2

+1.8VS

C174 4.7U_0805_10V4Z

0.08A/10mil/1vias

L

1 R69 1 R70

+1.8VS

2 20_0402_5% 0_0402_5%

UMA_ENVDD ENBKL

PA_RS780A4 placement close to NB ball 3

flash issue check IALAA MIS.

TMDS_HPD(NC) HPD(NC) SUS_STAT#(PWM_GPIO5) THERMALDIODE_P THERMALDIODE_N TESTMODE

D9 D10

HPD

1 2 D12 R77 0_0402_5% AE8 NB_THERMAL_DA AD8 NB_THERMAL_DC D13

AUX_CAL(NC)

SUS_STAT_R# SUS_STAT# PAD PAD

T49 T50

Strap pin

NB temp to SB

1 2 R80 1.8K_0402_5%

RS780M_FCBGA528

4

A

B

C

D

l.c

ho

Rev 0.2

f@

Size Document Number Custom LA-4111P Date:

ai

Compal Electronics, Inc. RS780 VEDIO/CLK GEN in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Friday, November 30, 2007

Sheet E

xa

2008/08/02

Deciphered Date

11

he

2007/08/02

Issued Date

tm

Compal Secret Data

Security Classification

om

4

of

48

A

B

C

D

U3D

U61 L2 L3

BA0 BA1

MEM_A12 MEM_A11 MEM_A10 MEM_A9 MEM_A8 MEM_A7 MEM_A6 MEM_A5 MEM_A4 MEM_A3 MEM_A2 MEM_A1 MEM_A0

R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8

A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

MEM_CLKN MEM_CLKP

K8 J8

CK CK

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

VDD VDD VDD VDD VDD

A1 E1 J9 M9 R1

MEM_DQ15 MEM_DQ11 MEM_DQ13 MEM_DQ12 MEM_DQ8 MEM_DQ10 MEM_DQ9 MEM_DQ14 MEM_DQ3 MEM_DQ7 MEM_DQ1 MEM_DQ6 MEM_DQ5 MEM_DQ0 MEM_DQ4 MEM_DQ2

100_0402_1% SIDE@

2

R91

MEM_CKE

K2

CKE

MEM_CS#

L8

CS

MEM_WE#

K3

WE

MEM_RAS#

K7

RAS

MEM_CAS#

L7

MEM_DM0 MEM_DM1

F3 B3

MEM_ODT

CAS LDM UDM

VDDL VSSDL

+1.8V_MEM_VDDQ

+1.8V_MEM_VDDQ L96 1 2 SIDE@0_0603_5%

+VDDL

J1 J7

ODT

1

MEM_DQS_P0 MEM_DQS_N0

F7 E8

LDQS LDQS

2

MEM_DQS_P1 MEM_DQS_N1

B7 A8

UDQS UDQS

J2

VREF

A2 E2 L1 R3 R7 R8

NC NC NC NC NC NC

+MEM_VREF

MEM_BA2

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

VSS VSS VSS VSS VSS

A3 E3 J3 N1 P9

AB12 AE16 V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14 Y14

MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC)

MEM_BA0 MEM_BA1 MEM_BA2

AD16 AE17 AD17

MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC)

MEM_RAS# MEM_CAS# MEM_WE# MEM_CS# MEM_CKE MEM_ODT

W12 Y12 AD18 AB13 AB18 V14

MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC)

MEM_CLKP MEM_CLKN

K9

2

PAR 4 OF 6

MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12

2 R92 2 R93

V15 W14

MEM_COMP_P 1 [email protected]_0402_1% MEM_COMP_N 1 [email protected]_0402_1%

AE12 AD12

SBD_MEM/DVO_I/F

MEM_BA0 MEM_BA1

1

1

E

MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC) MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC) MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC) MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC) MEM_DQ12(NC) MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC)

AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21

MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3 MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7 MEM_DQ8 MEM_DQ9 MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15

MEM_DQS0P/DVO_IDCKP(NC) MEM_DQS0N/DVO_IDCKN(NC) MEM_DQS1P(NC) MEM_DQS1N(NC)

Y17 W18 AD20 AE21

MEM_DQS_P0 MEM_DQS_N0 MEM_DQS_P1 MEM_DQS_N1

MEM_DM0(NC) MEM_DM1/DVO_D8(NC)

W17 AE19

MEM_DM0 MEM_DM1

IOPLLVDD18(NC) IOPLLVDD(NC)

AE23 AE24

IOPLLVSS(NC)

AD23

MEM_VREF(NC)

AE18

MEM_CKP(NC) MEM_CKN(NC) MEM_COMPP(NC) MEM_COMPN(NC)

1

MEM_COMP_P and MEM_COMP_N trace width >=10mils and 10mils spacing from other Signals in X,Y,Z directions

+NB_IOPLLVDD 1 +MEM_VREF1

2

1 2 BLM18PG121SN1D_0603 C181 2.2U_0603_6.3V4Z SIDE@

RS780M_FCBGA528

+1.8VS L12 1 2 BLM18PG121SN1D_0603

+1.8V_IOPLLVDD

L13

+1.1VS 1 1 C182 0.1U_0402_16V4Z 2 SIDE@

C183 2.2U_0603_6.3V4Z

2

SIDE@

+1.8V_MEM_VDDQ

09/19 update 2

C184 SIDE@1U_0603_10V6K

Layout Note: 50 mil for VSSDL

09/19 update Del SI3456 and MEM related Pull-high.

HY5PS561621AFP-25_FBGA84 SIDE@

9/20 SA000012G20 S IC D2 32M16 HY5PS121621CFP-25 FBGA 84P

3

3

Side Port disable,VREF need connect to +1.8VS for DDR2

2

1 C203 SIDE@ 2

22U_0805_6.3V6M

2

1 C202

SIDE@

0.1U_0402_16V4Z

1

1

0.1U_0402_16V4Z

SIDE@

C201

1

1U_0402_6.3V4Z

2

SIDE@

C607

C608

2 1

2

1K_0402_1%

SIDE@

2 SIDE@

R99

SIDE@

0.1U_0402_16V4Z

1

10/8 update

+1.8VS

L15

+MEM_VREF1

C200

2

1K_0402_1%

SIDE@

C199

1

0.1U_0402_16V4Z R98 1 2

+MEM_VREF

+1.8V_MEM_VDDQ SIDE@ 1U_0402_6.3V4Z

2 R97 1

2

10/8 update

1K_0402_1%

SIDE@

0.1U_0402_16V4Z

1 SIDE@

C196

2

+1.8V_MEM_VDDQ

1K_0402_1%

C195

1 SIDE@

0.1U_0402_16V4Z R96 1 2

+1.8V_MEM_VDDQ

1 SIDE@

2 0_0805_5%

220 ohm @ 100MHz,2A

SIDE@

4

4

Compal Secret Data

Security Classification 2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Compal Electronics, Inc. RS780 Side-Port DDR2 SDRAM

Size Document Number Custom LA-4111P Date:

Rev 0.2

Friday, November 30, 2007

Sheet E

12

of

48

A

B

C

D

E

U3F

0.6A/50mil/4vias 2A

4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z L22

0.25A/30mil/2vias

L

2A

2

+1.8VS

+VDDA18PCIE

1

FBMA-L11-201209-221LMA30T_0805

1

C235 4.7U_0805_10V4Z

1 C246

2

1 C236

2

1 C237

2

1 C238

2

J10 P10 K10 M10 L10 W9 H9 T10 R10 Y9 AA9 AB9 AD9 AE9 U10

1 C239

2

2

4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

F9 G9 AE11 AD11

+1.8VS +1.8VS 3

C251 1U_0402_6.3V4Z

2 +1.8V_VDD_SP 0_0603_5%

1 R1051

11/13 update

1

L

+1.8VS

2

VDD18_1 VDD18_2 VDD18_MEM1(NC) VDD18_MEM2(NC)

VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC) VDD33_1(NC) VDD33_2(NC)

AE10 AA11 Y11 AD10 AB10 AC10 H11 H12

RS780M_FCBGA528

1

2

VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15

L20 1 2 FBMA-L11-201209-221LMA30T_0805 L21 1 2 FBMA-L11-201209-221LMA30T_0805

+1.1VS

L

+NB_VDDC

7A/280mil/16vias VDD_CORE=5A 330U_D2E_2.5VM_R15

C245

2

K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16

C233

2

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22

10U_0805_10V4Z

2

1 C229

C232

2

1 C228

10U_0805_10V4Z

2

1 C227

1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

C244

1 C226

2 2 2 2 1 1

0.1U_0402_16V4Z

1

1 1 1 1 2 2

C231

L95 C225 2 1 @ FBMA-L11-201209-221LMA30T_0805

VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13

C220 C219 C222 C221 C224 C223

0.1U_0402_16V4Z

2

AE25 AD24 AC23 AB22 AA21 Y20 W19 V18 U17 T17 R17 P17 M17

10U_0805_10V4Z

C212

C230

+VDDHTTX

VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7

10U_0805_10V4Z

C211

0.1U_0402_16V4Z

0.5A/50mil/4vias

L 2A

H18 G19 F20 E21 D22 B23 A23

+1.1VS

+VDDA11PCIE

C243

0.1U_0402_16V4Z

PART 5/6

A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9

0.1U_0402_16V4Z

2

VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8 VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17

C242

C216 2 2 2 0.1U_0402_16V4Z

2

VDDHT_1 VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7

0.1U_0402_16V4Z

0.45A/40mil/3vias

J17 K16 L16 M16 P16 R16 T16

L17 1 2 FBMA-L11-201209-221LMA30T_0805

0.7A/60mil/4vias VDDA_12=2.5A

C241

U3E

0.1U_0402_16V4Z

L

0.1U_0402_16V4Z

C240

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 C217 1 1 C214 C218

C215 4.7U_0805_10V4Z

+1.35VS

2 2 0.1U_0402_16V4Z

+VDDHTRX

2A

L19 2 1 FBMA-L11-201209-221LMA30T_0805

C207

0.1U_0402_16V4Z

1

FBMA-L11-201209-221LMA30T_0805

11/20 update

2

L

L18 2

+1.2V_HT

2

C247

C209 4.7U_0805_10V4Z

POWER

FBMA-L11-201209-221LMA30T_0805

0.1U_0402_16V4Z

+VDDHT 0.1U_0402_16V4Z 0.1U_0402_16V4Z C2081 1 C206 1 1 1 C210

1

0.1U_0402_16V4Z

L L16 2

+1.1VS

1

2

1

2

1

2

1

2

1

2

1

2

2

1

2

1

2

1

2

1

2

1

C234

+ 2

VSSAHT1 VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27

L12 M14 N13 P12 P15 R11 R14 T12 U14 U11 U15 V12 W11 W15 AC12 AA14 Y18 AB11 AB15 AB17 AB19 AE20 AB21 K11

VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34

PART 6/6

1

A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2

VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8 VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40

2

AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10

RS780M_FCBGA528

+1.8VS

10/04 update SIDE@0_0603_5% +1.8V_VDD_MEM 1 2 R1054

L

1

A25 D23 E22 G22 G24 G25 H19 J22 L17 L22 L24 L25 M20 N22 P20 R19 R22 R24 R25 H20 U22 V19 W22 W24 W25 Y21 AD25

GROUND

1

0.15A/30mil/2vias

C249 C248 C597 C598 C599

2 2 2 2 2

1 1 1 1 1

[email protected]_0805_10V4Z [email protected]_0402_16V4Z [email protected]_0402_16V4Z [email protected]_0402_16V4Z [email protected]_0402_16V4Z 3

+3VS

C252 1U_0402_6.3V4Z

1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z

2 2

C250 C253

Just for RS780M A11 version boot issue U64 VCNTL

6

GND

NC

5

2

R1015 1K_0402_1%

3

VREF

NC

7

4

VOUT

NC

8

2

@ 10U_0805_10V4Z

VIN

2

+3VS

1

C1064

1

1

TP

9

1

2

C1065 @ 1U_0603_10V6K

@ G2992F1U_SO8 +VREF1.35V +1.35VS

1

@

1

1

2

4

C1067 @ 10U_0805_10V4Z

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B

C

D

Title

Compal Electronics, Inc. RS780 PWR/GND

Size Document Number Custom LA-4111P Date:

ai

2007/08/02

Issued Date

tm

Compal Secret Data

Security Classification

l.c

@ 0.1U_0402_16V7K

11/20 update

A

om

2

ho

1

S

C1068 @ 0.1U_0402_16V7K

C1066

Rev 0.2

f@

2

@ 3K_0402_5%

in

D

2 G

Friday, November 30, 2007

Sheet E

xa

10/8 update

2 @ 0_0402_5%

2

1 R1017

VLDT_EN#

3

13

he

4

R1016 1

Q163 @ 2N7002_SOT23-3

of

48

A

B

C

1

D

E

1

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

RS780 DFT_GPIO5 mux at CRT_VSYNC pull low to 3K

2 R101 2 R102

CRT_VSYNC

1 1K_0402_5% 1 @ 1K_0402_5%

Enables the Test Debug Bus using GPIO. 1 : Disable (RS780) Enable (RX780) 0 : Enable (RS780) Disable (RX780) PIN: RX780:NB_TV_C; RS740: RS740_DFT_GPIO5; RS780: VSYNC#

+3VS

11/28 update

11/28 update

2

2

DFT_GPIO1: LOAD_EEPROM_STRAPS

RS780 DFT_GPIO1

1 @ R104

AUX_CAL

D4 2

SUS_STAT_R#

2 150_0402_1% @ CH751H-40PT_SOD323-2 1

PLT_RST#

Selects Loading of STRAPS from EPROM 1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use

default values if not connected RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.

3

3

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb

RS780_DFT_GPIO_0

2 @ R105

1 1K_0402_5%

RX780: Enables the Test Debug Bus using PCIE bus 1 : Disable ( Can still be enabled using nbcfg register access ) 0 : Enable

RS780 use HSYNC to enable SIDE PORT (internal pull high)

RS740/RS780: Enables Side port memory ( RS780 use HSYNC#) 1. Disable (RS740/RS780) 0 : Enable (RS740/RS780)

2 1 R107 SIDE@3K_0402_5%

CRT_HSYNC

10/09 update

4

4

Compal Secret Data

Security Classification 2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Compal Electronics, Inc. RS780 STRAPS

Size Document Number Custom LA-4111P Date:

Rev 0.2 Sheet

Friday, November 30, 2007 E

14

of

48

A

B

C

D

+3VS_CLK

+3VS R167 1 2 0_0805_5%

+VDDCLK_IO

+1.2V_HT R168 1 2 0_0805_5%

1

0.1U_0402_16V4Z 1 C452

10U_0805_10V4Z

2

0.1U_0402_16V4Z 1

1

C453 2

C454

C455

2 0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z 1

1

C456

2

C457

2 0.1U_0402_16V4Z

E

1 C444 10U_0805_10V4Z

2

1

C445 0.1U_0402_16V4Z

2

1

C446 0.1U_0402_16V4Z

2

1

C447 0.1U_0402_16V4Z

2

1

C448 0.1U_0402_16V4Z

2

1

C449 0.1U_0402_16V4Z

2

1 @ C451

C450 0.1U_0402_16V4Z

2

1U_0402_6.3V4Z

2 1

1

C458

1

C459

1

C460

C461

1

1

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

EMI Caps for single end clock. CLK_48M_USB

22P_0402_50V8J 2

2

22P_0402_50V8J

09/29 update U10

GND

Routing the trace at least 10mil



SMB_CK_CLK0 SMB_CK_DAT0 +3VS_CLK

PA_RS7X0A1

SB LINK

CLK_SBLINK_BCLK# CLK_SBLINK_BCLK +VDDCLK_IO

CLK_PCIE_MCARD1# CLK_PCIE_MCARD1 CLK_PCIE_MCARD2# MiniCard_2 CLK_PCIE_MCARD2

MiniCard_1

1.1V 200R/100R

2 +3VS_CLK 8.2K_0402_5%

1

@ 5P_0402_50V8C

CLK_CPU_BCLK

2 0_0402_1% 2 0_0402_1%

54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37

CLK_CPU_BCLK#

+3VS_CLK +VDDCLK_IO CLKREQ_NCARD# CLKREQ_MCARD2#

CLKREQ_NCARD# CLKREQ_MCARD2#

+3VS_CLK

CLK_SBSRC_BCLK CLK_SBSRC_BCLK# SB +3VS_CLK CLKREQ_MCARD1# CLKREQ4 1 2 R372 10K_0402_5%

CLKREQ_MCARD1# +3VS_CLK

SRC

PA_RS7X0A1

For ICS need to pull high. For SLG is NC

+3VS_CLK +VDDCLK_IO 3

SLG8SP626VTR_QFN72_10x10

+3VS_CLK

+VDDCLK_IO

2

CLKREQ4 NBGFX_CLK NBGFX_CLK#

1

NB GFX

CLK_PCIE_MCARD0 CLK_PCIE_MCARD0# CLKREQ_LAN# CLK_PCIE_LAN CLK_PCIE_LAN#

CLKREQ_LAN#

CLK_PCIE_NCARD CLK_PCIE_NCARD#

27M_SEL

SEL_SATA 0

1 *

configure as SATA output *

* default

0

+3VS_CLK

Card Reader

NB CLOCK INPUT TABLE

GLAN

NB CLOCKS

New Card

RX780

RS780

HT_REFCLKP 100M DIFF 100M DIFF

100M DIFF 100M DIFF

configure as 27M and 27M_SS output

REFCLK_N

14M SE (1.8V) NC

14M SE (1.1V) vref

GFX_REFCLK

100M DIFF

100M DIFF(IN/OUT)*

REFCLK_P

27M_SEL configure as normal SRC(SRC_6) output

2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 @ 8.2K_0402_5%

11/28 update

HT_REFCLKN 1

configure as SRC_7 output * default

4

A

B

C

D

Clock generator Size Document Number Custom LA-4111P Date:

l.c ai

Compal Electronics, Inc. ho

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Rev 0.2

f@

2008/08/02

Deciphered Date

in

2007/08/02

Issued Date

tm

Compal Secret Data

Security Classification

configure as single-ended 66MHz output

0* configure as differential 100MHz output * default

Friday, November 30, 2007

Sheet E

xa

1 NB_OSC_14.318M

om

Use voltage divider resistor R379 & R380 to pull low

15

he

4

1 R324 1 R325 1 R326 1 R1039 1 R1045

CLKREQ_MCARD2#

CLKREQ_LAN#

R180 8.2K_0402_5% 1

R181 8.2K_0402_5%

2

2 1 2

SEL_SATA

@ 5P_0402_50V8C

2

CPU

10/03 update

CLKREQ_MCARD1#

+3VS_CLK

C1074

@ 5P_0402_50V8C C1075

9/20 SA00001Z300 S IC SLG8SP626VTR QFN 72P CLK GEN 9/20 SA000025B00 S IC RTM880N-795-GRT QFN 72P CLK GEN

@ R179 8.2K_0402_5%

1

CLKREQ_NCARD#

+3VS_CLK

2

2

R186 @ 261_0402_1%

09/21 update

VDD_CPU VDD_CPU_I/O VSS_CPU CLKREQ_1# CLKREQ_2# VDD_A VSS_A VSS_SATA SRC_6/SATA SRC_6#/SATA# VDD_SATA CLKREQ_3# CLKREQ_4# SB_SRC_SLOW# SB_SRC_0 SB_SRC_0# VDD_SB_SRC VDD_SB_SRC_IO

1

CLK_14M_SIO

CLK_14M_SIO CLK_NBHT CLK_NBHT# NB

1 R946 CLK_CPU_BCLK#_R 1 R945

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

3

1.8V 75R/100R

RS780

C1076

CLK_CPU_BCLK_R

SCL SDA VDD_DOT SRC_7#/27M SRC_7/27M_SS VSS_DOT SRC_5# SRC_5 SRC_4# SRC_4 VSS_SRC VDD_SRC_IO SRC_3# SRC_3 SRC_2# SRC_2 VDD_SRC VDD_SRC_IO

RX780

2

1 R174

2 100_0402_1%

R220 33_0402_5% 1 2

NB_OSC_14.318M

OSC_14M_NB

NB_OSC_14.318M 1 R380

VSS_SRC SRC_1# SRC_1 SRC_0# SRC_0 CLKREQ_0# ATIGCLK_2# ATIGCLK_2 VSS_ATIG VDD_ATIG_IO VDD_ATIG ATIGCLK_1# ATIGCLK_1 ATIGCLK_0# ATIGCLK_0 SB_SRC_1# SB_SRC_1 VSS_SB_SRC

+3VS_CLK +VDDCLK_IO

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

CLK_XTAL_OUT CLK_XTAL_IN

14.31818MHZ_20P_6X1430004201 1 C465

2 200_0402_1%

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

1

CLK_48M_USB

VSS_48 48MHz_0 48MHz_1 VDD_48 XTAL_OUT XTAL_IN VSS_REF REF_0/SEL_HTT66 REF_1/SEL_SATA REF_2/SEL_27 VDD_REF VDD_HTT HTT_0/66M_0 HTT_0#/66M_1 VSS_HTT PD# CPU_K8_0 CPU_K8_0#

C464

1

73

2

CLK_48M_USB_R

Y2

1

NB_OSC_14.318M_R SEL_SATA 27M_SEL +3VS_CLK +3VS_CLK

CLK_XTAL_IN

2

R379

+3VS_CLK

CLK_XTAL_OUT

33_0402_5%

2

1

R170 1

of

48

A

B

C

D

E

CRT CONNECTOR

1

+5VS

+R_CRT_VCC

@ D35

@ D37

@ D34

+CRT_VCC F2

2

1

1

1

D36

1

1

1

2 1

RB491D_SOT23 1A_6VDC_MINISMDC110 C475 0.1U_0402_16V4Z

+3VS

R211

R217

C471 2

1 C859 2

1 C469 2

C858

3

2

3

2

1

2

HSYNC BLUE_L

1 C476 2

1 C472 2

22P_0402_50V8J

R214 2

1

D_DDCDATA GREEN_L

22P_0402_50V8J

RED_L

22P_0402_50V8J

BLUE

BLUE

L47 1 2 BLM15AG121SN1D_0402 L48 1 2 BLM15AG121SN1D_0402 L49 1 2 BLM15AG121SN1D_0402

6P_0402_50V8K

GREEN

6P_0402_50V8K

GREEN

2 1 150_0402_1%

2 1 150_0402_1%

RED

2 1 150_0402_1%

RED

6P_0402_50V8K

JCRT

2

DAN217_SC59DAN217_SC59

3

2

DAN217_SC59

+CRT_VCC

VSYNC D_DDCCLK

6 11 1 7 12 2 8 13 3 9 14 4 10 15 5

RGND ID0 Red GGND SDA Green BGND Hsync Blue +5V Vsync res SGND SCL GND

16 17

GND GND

11/14 update

Update PCB Footprint SUYIN_070546FR015S263ZR_15P-T : Change back JCRT.5JCRT.15 ; JCRT.14JCRT.4 ; JCRT.13JCRT.3 ; JCRT.12JCRT.2 ; JCRT.11JCRT.1

2

CONN@ SUYIN_070546FR015S263ZR RED_L

GREEN_L BLUE_L

+3VS



+CRT_VCC

UMA_CRT_CLK

6.8K_0402_5%

1

1

6.8K_0402_5% D_DDCDATA

6

Q10A 2N7002DW-7-F_SOT363-6

D_DDCDATA

CRT_HSYNC

2

5 1 A

Y

4

D_HSYNC

R240 1

HSYNC

2 0_0603_5%

U14 SN74AHCT1G125GW_SOT353-5

3



D_HSYNC

5

UMA_CRT_DAT

R218

P OE#

2

R100

1 2 C473 0.1U_0402_16V4Z

G

R238 4.7K_0402_5% 2

D_VSYNC

2

1

+CRT_VCC

R237 4.7K_0402_5%

CRT_VSYNC

2 470P_0402_50V8J

3

2

11/07 update Y

4

D_ VSYNC

R241 1

VSYNC

2 0_0603_5%

U13 SN74AHCT1G125GW_SOT353-5

1 @ C474

1

@ C470

2

2

10P_0402_50V8J

@ C856

3

470P_0402_50V8J

1 2 @ C477 0.1U_0402_16V4Z 2 A

5 1

G

@ C857

D_DDCCLK

1

10P_0402_50V8J

1

P OE#

D_DDCCLK

4 3 Q10B 2N7002DW-7-F_SOT363-6

3

4

4

Compal Secret Data

Security Classification 2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Compal Electronics, Inc. CRT Connector

Size Document Number Custom LA-4111P Date:

Rev 0.2 Sheet

Friday, November 30, 2007 E

16

of

48

B

C

D

WebCam+Digital Mic Reserve

10U_0805_10V4Z

1

8

G2

C720

ACES_88231-06001 CONN@

1

10U_0805_10V4Z

L D52 +USB_CAM USB20N5

09/26 update

4

VIN

IO1

2

3

IO2 GND

1

1

VIN

VOUT

2

GND

3

EN

5

R891

4

@ 215K_0402_1% 2 C719

Place R1027~R1030 close to JLVDS

R1027 USB20_P5 1 USB20_N51 R1028

@ 0_0402_5% 2 USB20P5 2 USB20N5 @ 0_0402_5%

R1029 DMIC_DAT1 DMIC_CLK1 R1030

@ 0_0402_5% 2 DMICDAT 2 DMICCLK @ 0_0402_5%

2

DMICCLK DMICDAT

2

1

2

BP

1

@ C1072

U54

PJP4 PAD-OPEN 2x2m

7

G1

RT9193-39GB_SOT23-5

1

C718 0.1U_0402_16V4Z

R1013

1

1

R892

1

C718 install when U54 is RT9193-39GB

L

10U_0805_10V4Z

@ 100K_0402_1%

2

0_0402_5%

Close to JLVDS

L

D22

2

Close to JP7

L

1 2 3 4 5 6

2

+USB_CAM

1 2 3 4 5 6

1

USB20P5 USB20N5

USB_VCCA is +3.9V, R892:100K; R891:215KKohm G916 Vref=1.25V when U54 install G916-390T1UF

+USB_CAM

+5VALW

11/13 update

JP7 1

E

2

A

@ R1014 1 2 0_0402_5%

+USB_CAM CAM_SHDN#

USB20_N5

USB20P5

4

VIN

IO1

2

3

IO2 GND

1

USB20_P5

@ PRTR5V0U2X_SOT143-4

@ PRTR5V0U2X_SOT143-4

11/09 update

2

3

1

80mil

5

UMA_ENVDD

B+ L44 1 2 FBMA-L11-201209-221LMA30T_0805

LVDS_A1-

C1057

1

2 @ 10P_0402_50V8J

LVDS_A1+

LVDS_A0-

C1058

1

2 @ 10P_0402_50V8J

LVDS_A0+

3

1

2 @ 10P_0402_50V8J

LVDS_ACLK+

LVDS_B2-

C1060

1

2 @ 10P_0402_50V8J

LVDS_B2+

LVDS_B1-

C1061

1

2 @ 10P_0402_50V8J

LVDS_B1+

LVDS_B0-

C1062

1

2 @ 10P_0402_50V8J

LVDS_B0+

LVDS_BCLK- C1063

1

2 @ 10P_0402_50V8J

LVDS_BCLK+

+3VS

C481

2

LVDS_ACLK- C1059



680P_0402_50V7K

09/19 update

80mil

11/07 update +LCDVDD

1 C487 4.7U_0805_10V4Z

2

C491 0.1U_0402_16V4Z

1

1

1 Q45B 2N7002DW-7-F_SOT363-6

C480

LVDS CONN

680P_0402_50V7K

USB20_P5 USB20_N5

LVDS_BCLK+ LVDS_BCLK LVDS_B0+ LVDS_B0 LVDS_B1+ LVDS_B1 LVDS_B2+ LVDS_B2-

JLVDS

USB20_P5 USB20_N5

LVDS_BCLK+ LVDS_BCLKLVDS_B0+ LVDS_B0LVDS_B1+ LVDS_B1LVDS_B2+ LVDS_B2-

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 GND

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

LVDS_A2LVDS_A2+ LVDS_A1LVDS_A1+ LVDS_A0LVDS_A0+ LVDS_ACLKLVDS_ACLK+

LVDS_A2- LVDS_A2+ LVDS_A1- LVDS_A1+ LVDS_A0- LVDS_A0+ LVDS_ACLK- LVDS_ACLK+

DMIC_DAT DMIC_CLK

DMIC_DAT DMIC_CLK

11/07 update

INV_PWM BKOFF# DAC_BRIG

9/20 SP02000EA00/SP02000BW00



+5VS

R491 1

2 200_0805_5% INV_PWM BKOFF# DAC_BRIG

LCD_DDC_CLK LCD_DDC_DAT

ACES_88242-4001 CONN@

3

@

+USB_CAM LCD_DDC_CLK LCD_DDC_DAT

@

@

+3VS

10/08 update



1

1

2

2 @

C483 680P_0402_50V7K

LVDS_A2+

R276 2.2K_0402_5%

C482 680P_0402_50V7K

2 @ 10P_0402_50V8J

4

2

C867 680P_0402_50V7K 2 1

1

1

3

1 INVPWR_B+

C866 680P_0402_50V7K 2 1

C1056

1

LVDS_A2-

C863 1000P_0402_50V7K

2

2

2

D

1

2

R222 1 2 100K_0402_5%

2

680P_0402_50V7K C479

SI2301BDS-T1-E3_SOT23-3 Q43

G

Q45A 2N7002DW-7-F_SOT363-6

+LCDVDD

+3VS

R224 1M_0402_5%

6 2

R225 470_0805_5%

S

2

2

+5VALW

1

+LCDVDD

BKOFF# 1 @ 4.7K_0402_5%

2 R483

LCD_DDC_CLK 1 4.7K_0402_5%

2 R274

LCD_DDC_DAT 1 4.7K_0402_5%

2 R275

4

A

B

C

D

Rev 0.2

f@

Size Document Number Custom LA-4111P Date:

l.c

ho

LCD CONN. / WebCam

ai

Compal Electronics, Inc. in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Friday, November 30, 2007

Sheet E

xa

2008/08/02

Deciphered Date

17

he

2007/08/02

Issued Date

tm

Compal Secret Data

Security Classification

om

4

of

48

A

B

C

D

E

+HDMI_5V_OUT

2

1

+3VS

R176 4.7K_0402_5%

HDMI_HPD 2

2

G

A

2

2.2K_0402_5% Y

4

HPD

R628 100K_0402_5%

U39 SN74AHCT1G125GW_SOT353-5

3

HDMIDAT_UMA

1

HDMICLK_UMA

1

R236 6.8K_0402_5% HDMI_SDATA

1 6 Q134A 2N7002DW-7-F_SOT363-6

2

+3VS

R210 6.8K_0402_5%

5

1 R615

C850 0.1U_0402_16V4Z

HDMI_SCLK

4 3 Q134B 2N7002DW-7-F_SOT363-6

1

1

P OE#

0.1U_0402_16V4Z

5 1

2

1

2

+HDMI_5V_OUT

C851

R209 4.7K_0402_5% 2

1

C:Chg. PN to SB770020010.

2

2

11/13 update MP:Update D10 to meet HDMI. HDMI_CLK+ R112

1

2 0_0402_5%

HDMI_R_CK+ D10 2

+5VS

L85 1

1

2

2

4

4

3

3

1

+HDMI_5V_OUT

RB491D_SOT23 1

C507 1 C508 1

2 0.1U_0402_16V7K 2 0.1U_0402_16V7K

HDMI_CLKHDMI_CLK+

TMDS_B_DATA0# TMDS_B_DATA0

C655 1 C675 1

2 0.1U_0402_16V7K 2 0.1U_0402_16V7K

HDMI_TX0HDMI_TX0+

TMDS_B_DATA1# TMDS_B_DATA1

C804 1 C827 1

2 0.1U_0402_16V7K 2 0.1U_0402_16V7K

HDMI_TX1HDMI_TX1+

C852 1 C853 1

2 0.1U_0402_16V7K 2 0.1U_0402_16V7K

HDMI_TX2HDMI_TX2+



TMDS_B_CLK# TMDS_B_CLK

HDMI_CLK-

@ WCM-2012-900T_4P 1 2 R113 0_0402_5%

HDMI_TX0+ R115



TMDS_B_DATA2# TMDS_B_DATA2

HDMI_TX1HDMI_TX1+

1 1

R297 750_0402_1%

R139 750_0402_1%

R141 750_0402_1%

5

2

3

@ WCM-2012-900T_4P 1 2 R116 0_0402_5%

1

2 0_0402_5%

1

1

2

2

4

4

3

3

@ WCM-2012-900T_4P 1 2 R118 0_0402_5%

1

4

Q162B 2N7002DW-7-F_SOT363-6

HDMI_TX2+ R119

1

2 0_0402_5%

0.1U_0402_16V4Z

HDMI Connector +HDMI_5V_OUT JHDMI 18 +5V 16 SDA 15 SCL 19 HP_DET

HDMI_R_D0-

HDMI_R_D1+

HDMI_SDATA HDMI_SCLK HDMI_HPD

CEC Reserved

13 14

HDMI_R_CKHDMI_R_CK+ HDMI_R_D0HDMI_R_D0+ HDMI_R_D1HDMI_R_D1+ HDMI_R_D2HDMI_R_D2+

GND GND GND GND GND GND GND GND DDC/CEC_GND

2 5 8 11 20 21 22 23 17

12 10 9 7 6 4 3 1

CKCK+ D0D0+ D1D1+ D2D2+

3

CONN@ SUYIN_100042MR019S153ZL HDMI_R_D1-

11/14 update

5

Q136A Q136B Q162A 2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 1

2

3

L87

4

2

2

4

R117

HDMI_TX1-

11/13 update

1

4

HDMI_TX1+

UMA use 750 ohm VGA use 499 ohm

3

+5VS 6

+5VS

2 2

R304 750_0402_1%

1

C468

HDMI_R_D0+

1 1

R172 750_0402_1%

3

+5VS 6

+5VS

R173 750_0402_1%

1 1

Just change P/N to SD034750080

2 2

R307 750_0402_1%

1 2

R315 750_0402_1%

HDMI_TX2HDMI_TX2+ 2 2

HDMI_TX0HDMI_TX0+

2 1

HDMI_CLKHDMI_CLK+

2 0_0402_5%

L86

HDMI_TX03

1

2

HDMI_R_CK-

HDMI_R_D2+

L88

HDMI_TX2-

1

1

2

2

4

4

3

3

@ WCM-2012-900T_4P 1 2 R120 0_0402_5%

HDMI_R_D2-

4

4

Change PCB Footprint from SW_WCM2012F2S_4P to KING_WCM-2012-900T_4P

L

Compal Secret Data

Security Classification 2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Compal Electronics, Inc. HDMI

Size Document Number Custom LA-4111P Date:

Rev 0.2 Sheet

Friday, November 30, 2007 E

18

of

48

A

1

U22 U21 U19 V19 R20 R21 R18 R17

PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N

R305 R306 +PCIE_VDDR L53 1 2 BLM18PG121SN1D_0603 1 C504 10U_0805_10V4Z

1 562_0402_1% 1 2.05K_0402_1%

2 2

2

+SB_PCIEVDD

T25 T24

PCIE_CALRP PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

1

2

C505 1U_0402_6.3V4Z

Part 1 of 5

@ R314 20M_0402_5% 1 2 C643 SB_32KHI

2

18P_0402_50V8J

11/23 update

Y3

1

1

4

R389

1

20M_0402_5%

1

NC

3

OSC

NC

2

L

Need use new P/N with 10PPM

K23 K22

NB_DISP_CLKP NB_DISP_CLKN

M24 M25

NB_HT_CLKP NB_HT_CLKN

P17 M18

CPU_HT_CLKP CPU_HT_CLKN

M23 M22

SLT_GFX_CLKP SLT_GFX_CLKN

J19 J18

GPP_CLK0P GPP_CLK0N

L20 L19

GPP_CLK1P GPP_CLK1N

M19 M20

GPP_CLK2P GPP_CLK2N

N22 P22

GPP_CLK3P GPP_CLK3N

L18

25M_48M_66M_OSC

J21

PCI INTERFACE

PCIE_RCLKP/NB_LNK_CLKP PCIE_RCLKN/NB_LNK_CLKN

25M_X1

32.768KHZ_12.5PF_Q13MC14610050_10PPM

2

C652

11/29 update

OSC

N25 N24

CLOCK GENERATOR

2

CLK_SBSRC_BCLK CLK_SBSRC_BCLK#

SB_32KHO

2

J20

N1

25M_X2

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CBE0# CBE1# CBE2# CBE3# FRAME# DEVSEL# IRDY# TRDY# PAR STOP# PERR# SERR# REQ0# REQ1# REQ2# REQ3#/GPIO70 REQ4#/GPIO71 GNT0# GNT1# GNT2# GNT3#/GPIO72 GNT4#/GPIO73 CLKRUN# LOCK# INTE#/GPIO33 INTF#/GPIO34 INTG#/GPIO35 INTH#/GPIO36

X1

SB_32KHO

B3

X2

09/11 update +1.8VS

2 R318

1 CPU_LDT_REQ# @ 10K_0402_5%

+3VS

2 R319

H_PROCHOT# 1 10K_0402_5%

11/13 update

CPU_LDT_REQ# H_PROCHOT# H_PWRGD

F23 F24 F22 G25 G24

ALLOW_LDTSTP PROCHOT# LDT_PG LDT_STP# LDT_RST#

H_PWRGD_CPU

2

LPCCLK0 LPCCLK1 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ0# LDRQ1#/GNT5#/GPIO68 BMREQ#/REQ5#/GPIO65 SERIRQ

2 @ 22_0402_5%CLK_PCI_SIO

H_PWRGD

0_0402_5%

CLK_PCI_SIO2

U2 P7 V4 T1 V3 U1 V1 V2 T2 W1 T9 R6 R7 R5 U8 U5 Y7 W8 V9 Y8 AA8 Y4 Y3 Y2 AA2 AB4 AA1 AB3 AB2 AC1 AC2 AD1 W2 U7 AA7 Y1 AA6 W5 AA5 Y5 U6 W6 W4 V7 AC3 AD4 AB7 AE6 AB6 AD2 AE4 AD5 AC6 AE5 AD6 V5

PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28

PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28





PCI_SERR#

PAD

T15

PAD PAD

T16 T17

AD3 AC4 AE2 AE3 PCI_PIRQH#

2

LPCCLK1

R308 1

22_0402_5%

2

R967 2

1 0_0402_5%

ACCEL_INT

3

STRAP PIN EC & Debug

C3 C2 B2

RTC_CLK +SB_VBAT

ZZZ

STRAP PIN

+SB_VBAT

09/29 update +RTCVCC_R

R316 120_0402_5% 1 2

218S7EALA11FG_BGA528_SB700

1 C509

1 C510

2 1U_0402_6.3V4Z

+RTCVCC

2

R876 1 3 1 2 W=20mils 1K_0402_5% DAN202U_SC70

2007/08/02

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C

D

1 2 GND GND

CONN@ ACES_85205-02001

2008/08/02

Deciphered Date

1 2 3 4

+RTCBATT_R

9/20 SP020008T00

09/29 update

Compal Secret Data

Security Classification

JBATT1 W=20mils

J1 @ JUMP_43X39

1

4

+RTCBATT D42

1

2

+3VL

R317 120_0402_5% 1 2

W=20mils

0.1U_0402_16V4Z

B

CLK_PCI_SIO

11/22 update

22_0402_5% 09/29 update 2 CLK_PCI_EC G22 CLK_PCI_EC_R R302 1 CLK_PCI_EC E22 LPCCLK1 LPCCLK1 H24 LPC_AD0 H23 LPC_AD1 J25 LPC_AD2 J24 LPC_AD3 H25 LPC_FRAME# PAD T18 H22 AB8 11/13 update LPC_DRQ# AD7 V15 SIRQ

9/20 SA00001S510 S IC 218S7EALA11FG SB700 BGA 528P SB 0FH

A

CLK_PCI_SIO PCI_CLK4 PCI_CLK5

PCB-MB RTCCLK INTRUDER_ALERT# VBAT

R311 1

2 @ 22_0402_5%CLK_PCI_SIO2

R301 1

RTC

CPU_LDT_REQ# H_PROCHOT# H_PWRGD LDT_STOP# LDT_RST#

L PC

A3

CPU

SB_32KHI

RTC XTAL

18P_0402_50V8J

Close to SB

R303 1

1

Close to SB



PCIRST#

CLK_PCI_SIO_R

Title

4

Compal Electronics, Inc.

om

PCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N

l.c

V23 V22 V24 V25 U25 U24 T23 T22

ai

SB_RX0P_C SB_RX0N_C SB_RX1P_C SB_RX1N_C SB_RX2P_C SB_RX2N_C SB_RX3P_C SB_RX3N_C

tm

0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K

11/09 update

SB700-PCIE/PCI/ACPI/LPC/RTC ho

+1.2V_HT

2 2 2 2 2 2 2 2

P4 P3 P1 P2 T4 T3

Size Document Number Custom LA-4111P Date:

Rev 0.2

f@

SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N

1 1 1 1 1 1 1 1

PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5/GPIO41

in







C492 C493 C494 C495 C496 C497 C498 C499

A_RST#

Friday, November 30, 2007

Sheet E

xa

5

1 33_0402_5%

11/30 update

SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N

SB700

N2

@ NC7SZ08P5X_NL_SC70-5





PCICLK2

U15A NB_RST#_R

19

he

2 NB_RST#_R @ 8.2K_0402_5%

2

1 R300

2

PLT_RST#

3

A

PCI CLKS

4PLT_RST#

Y

1

3

E

U16

P

B

2 R312 1

D

PCI EXPRESS INTERFACE

NB_RST#_R

C

Check AMD need pull low or not

@ 0.1U_0402_16V4Z 2

G

2

B

+3VALW

C506

of

48

A

B

R1052

NB_PWRGD

2

C

D

E

1 NBPWRGD 0_0402_5%

R1053 2 1 @ 100_0402_5% U15D

11/13 update

+3VALW 1 R320 1 R321 1 R322

2 @ 2.2K_0402_5% 2 @ 2.2K_0402_5% 2 @ 2.2K_0402_5%



SB_TEST2 SB_TEST1

GATEA20 KB_RST# EC_SCI# EC_SMI#

11/13 update

SB_TEST0

10/08 update

+3VS R328

1

2 2.2K_0402_5%

SMB_CK_CLK0

R329

1

2 2.2K_0402_5%

SMB_CK_DAT0

H_THERMTRIP#

EC_RSMRST#

EC_RSMRST#

D3

SB700 has internal PD R327 2.2K_0402_5%

1

+3VALW R331

1

2 2.2K_0402_5%

SMB_CK_CLK1

R332

1

2 2.2K_0402_5%

SMB_CK_DAT1

SB_SPKR SMB_CK_CLK0 SMB_CK_DAT0 SMB_CK_CLK1 SMB_CK_DAT1 +3VS R83

2

SMB_CK_CLK0 SMB_CK_DAT0 SMB_CK_CLK1 SMB_CK_DAT1

2

+3VALW

SB_GPIO5

1 2 @ 10K_0402_5%

R540 10K_0402_5%

G8

USB_FSD13P USB_FSD13N

E6 E7

USB_FSD12P USB_FSD12N

F7 E8

USB MISC

SUS_STAT#

C8

USB_RCOMP

USB 1.1

2 4.7K_0402_5%

USBCLK/14M_25M_48M_OSC

AE18 AD18 AA19 W17 V17 W20 W21 AA18 W18 K1 K2 AA20 Y18 C1 Y19 G5

PCIE_WAKE# 1 0_0402_5% 1 @ 0_0402_5%

11/13 update

11/13 update







3

HDA_BITCLK_CODEC HDA_BITCLK_MDC HDA_SDOUT_MDC HDA_SDOUT_CODEC HDA_SDIN0 HDA_SDIN1 HDA_SYNC_MDC HDA_SYNC_CODEC HDA_RST#_CODEC HDA_RST#_MDC

HDARST#

R333 R334 R335 R336

EC_LID_OUT# EXP_CPPE# CR_CPPE# 33_0402_5% 1 2 33_0402_5% 1 2 33_0402_5% 1 2 33_0402_5% 1 2

R337 R338

33_0402_5% 33_0402_5%

1 1

2 2

R339 R340

33_0402_5% 33_0402_5%

1 1

2 2

R82 EXP_CPPE# 1 CR_CPPE# 1 R81 HDA_BITCLK

B9 B8 A8 0_0402_5% A9 E5 2 F8 2 D3E@ 0_0402_5% E4

HDA_SDOUT HDA_SDIN0 HDA_SDIN1 HDA_SYNC HDARST#

M1 M2 J7 J8 L8 M3 L6 M4 L5

USB_OC6#/IR_TX1/GEVENT6# USB_OC5#/IR_TX0/GPM5# USB_OC4#/IR_RX0/GPM4# USB_OC3#/IR_RX1/GPM3# USB_OC2#/GPM2# USB_OC1#/GPM1# USB_OC0#/GPM0# AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO42 AZ_SDIN1/GPIO43 AZ_SDIN2/GPIO44 AZ_SDIN3/GPIO46 AZ_SYNC AZ_RST# AZ_DOCK_RST#/GPM8#

INTEGRATED uC

MINI_PCIE_WAKE#

2 R993 2 R994

HD AUDIO

LAN_PCIE_WAKE#

PAD T41

STRAP PIN

H19 H20 H21 F25

IMC_GPIO0 IMC_GPIO1 SPI_CS2#/IMC_GPIO2 IDE_RST#/F_RST#/IMC_GPO3

D22 E24 E25 D23

IMC_GPIO4 IMC_GPIO5 IMC_GPIO6 IMC_GPIO7

INTEGRATED uC

USB OC

1

11/16 update

1

2 R323

09/04 update Touch Screen (delete)

USB_HSD11P USB_HSD11N

H11 J10

USB_HSD10P USB_HSD10N

E11 F11

USB20_P10 USB20_N10

USB_HSD9P USB_HSD9N

A11 B11

USB_HSD8P USB_HSD8N

C10 D10

USB20_P8 USB20_N8

USB_HSD7P USB_HSD7N

G11 H12

USB20_P7 USB20_N7

USB_HSD6P USB_HSD6N

E12 E14

USB20_P6 USB20_N6

USB_HSD5P USB_HSD5N

C12 D12

USB20_P5 USB20_N5

USB_HSD4P USB_HSD4N

B12 A12

USB_HSD3P USB_HSD3N

G12 G14

USB20_P3 USB20_N3

USB_HSD2P USB_HSD2N

H14 H15

USB20_P2 USB20_N2

USB_HSD1P USB_HSD1N

A13 B13

USB20_P1 USB20_N1

USB_HSD0P USB_HSD0N

B14 A14

USB20_P0 USB20_N0

IMC_GPIO8 IMC_GPIO9 IMC_PWM0/IMC_GPIO10 SCL2/IMC_GPIO11 SDA2/IMC_GPIO12 SCL3_LV/IMC_GPIO13 SDA3_LV/IMC_GPIO14 IMC_PWM1/IMC_GPIO15 IMC_PWM2/IMC_GPO16 IMC_PWM3/IMC_GPO17

A18 B18 F21 D21 F19 E20 E21 E19 D19 E18

IMC_GPIO18 IMC_GPIO19 IMC_GPIO20 IMC_GPIO21 IMC_GPIO22 IMC_GPIO23 IMC_GPIO24 IMC_GPIO25

G20 G21 D25 D24 C25 C24 B25 C23

IMC_GPIO26 IMC_GPIO27 IMC_GPIO28 IMC_GPIO29 IMC_GPIO30 IMC_GPIO31 IMC_GPIO32 IMC_GPIO33 IMC_GPIO34 IMC_GPIO35 IMC_GPIO36 IMC_GPIO37 IMC_GPIO38 IMC_GPIO39 IMC_GPIO40 IMC_GPIO41

B24 B23 A23 C22 A22 B22 B21 A21 D20 C20 A20 B20 B19 A19 D18 C18

RSMRST#

SATA_IS0#/GPIO10 CLK_REQ3#/SATA_IS1#/GPIO6 SMARTVOLT1/SATA_IS2#/GPIO4 CLK_REQ0#/SATA_IS3#/GPIO0 CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40 SPKR/GPIO2 SCL0/GPOC0# SDA0/GPOC1# SCL1/GPOC2# SDA1/GPOC3# DDC1_SCL/GPIO9 DDC1_SDA/GPIO8 LLB#/GPIO66 SMARTVOLT2/SHUTDOWN#/GPIO5 DDR3_RST#/GEVENT7#

CLK_48M_USB USB_RCOMP 1 11.8K_0402_1%

USB20_P11 USB20_N11

USB 2.0

1 R388

Part 4 of 5

SB700 PCI_PME#/GEVENT4# RI#/EXTEVNT0# SLP_S2/GPM9# SLP_S3# SLP_S5# PWR_BTN# PWR_GOOD SUS_STAT# TEST2 TEST1 TEST0 GA20IN/GEVENT0# KBRST#/GEVENT1# LPC_PME#/GEVENT3# LPC_SMI#/EXTEVNT1# S3_STATE/GEVENT5# SYS_RESET#/GPM7# WAKE#/GEVENT8# BLINK/GPM6# SMBALERT#/THRMTRIP#/GEVENT2# NB_PWRGD

GPIO

demo circuit SLP_S3# SLP_S5# PWRBTN_OUT# SB_PWRGD SUS_STAT#

+3VS

E1 E2 LID use RI# H7 F5 G1 H2 H1 SUS_STAT# K3 SB_TEST2 H5 SB_TEST1 H4 SB_TEST0 H3 Y15 W15 K4 K24 F1 PAD T19 J2 PCIE_WAKE# H6 F2 H_THERMTRIP# J6 NBPWRGD W14

ACPI / WAKE UP EVENTS

1

2

For SB700 A11 divider to 1.8V for RS & RX780

USB20_P11 USB20_N11



USB-11 New Card

USB20_P10 USB20_N10



USB-10 MiniCard(TV) USB-9 Card Reader (delete)

USB20_P8 USB20_N8



USB-8 MiniCard(WWAN)

USB20_P7 USB20_N7



USB-7 Fingerprint

USB20_P6 USB20_N6



USB-6 Bluetooth

USB20_P5 USB20_N5



USB-5 USB Camera

2

USB-4 Left side USB20_P3 USB20_N3



USB-3 Dock

USB20_P2 USB20_N2



USB-2 Left Side

USB20_P1 USB20_N1



USB-1 Right side

USB20_P0 USB20_N0



USB-0 Right side (S/W Debug Port)

GPIO16 GPIO17

STRAP PIN STRAP PIN



3

218S7EALA11FG_BGA528_SB700

4

4

Compal Secret Data

Security Classification 2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Compal Electronics, Inc. SB700 USB/AC97

Size Document Number Custom LA-4111P Date:

Rev 0.2 Sheet

Friday, November 30, 2007 E

20

of

48

A

B

1

Y4

R341

E

Change the PCB Footprint from Y_KDS_1BX25000CK1A_2P to Y_6X25000017_2P

L

10M_0402_5% 2

2

25MHz_20pF_6X25000017 10P_0402_50V8J 2

D

SATA_X1

1 C516 1

10P_0402_50V8J 2

C

1 C517

SATA_X2

10/09 update

1

1

U15B



SATA_TXP1 SATA_TXN1

C514 C515

1 1

2 0.01U_0402_25V7K 2 0.01U_0402_25V7K



SATA_TXP2 SATA_TXN2

C520 C521

1 1

2 0.01U_0402_25V7K 2 0.01U_0402_25V7K





11/05 update



C518 C519

SATA_TXP3 SATA_TXN3

SATA_STX_DRX_P0 SATA_STX_DRX_N0

SATA_RXN0_C SATA_RXP0_C SATA_STX_DRX_P1 SATA_STX_DRX_N1

SATA_RXN1_C SATA_RXP1_C SATA_STX_DRX_P2 SATA_STX_DRX_N2

SATA_RXN2_C SATA_RXP2_C SATA_STX_DRX_P3 SATA_STX_DRX_N3

2 0.01U_0402_25V7K 2 0.01U_0402_25V7K

1 1



11/06 update

SATA_RXN3_C SATA_RXP3_C

2

2 R342

11/05 update +3VS

+1.2V_HT

R343 10K_0402_5% 1 2

L54 2 1 BLM18PG121SN1D_0603

+PLLVDD_SATA 2

C522 1U_0402_6.3V4Z

1

2

1

C523 1U_0402_6.3V4Z

+3VS L55 2 1 BLM18PG121SN1D_0603 3

C524 1U_0402_6.3V4Z

SATA_TX0P SATA_TX0N

AB10 AC10

SATA_RX0N SATA_RX0P

AE10 AD10

SATA_TX1P SATA_TX1N

AD11 AE11

SATA_RX1N SATA_RX1P

AB12 AC12

SATA_TX2P SATA_TX2N

AE12 AD12

SATA_RX2N SATA_RX2P

AD13 AE13

SATA_TX3P SATA_TX3N

AB14 AC14

SATA_RX3N SATA_RX3P

AE14 AD14

SATA_TX4P SATA_TX4N

AD15 AE15

SATA_RX4N SATA_RX4P

AB16 AC16

SATA_TX5P SATA_TX5N

AE16 AD16

SATA_RX5N SATA_RX5P

SATA_CAL 1 1K_0402_1% SATA_X1

V12

SATA_CAL

Y12

SATA_X1

SATA_X2

AA12

SATA_X2

W11

SATA_LED#

+XTLVDD_SATA 2

SB700

AD9 AE9

Part 2 of 5

ATA 66/100/133

2 0.01U_0402_25V7K 2 0.01U_0402_25V7K

PLLVDD_SATA

W12

XTLVDD_SATA

AA24 AA25 Y22 AB23 Y23 AB24 AD25 AC25 AC24 Y25 Y24

IDE_D0/GPIO15 IDE_D1/GPIO16 IDE_D2/GPIO17 IDE_D3/GPIO18 IDE_D4/GPIO19 IDE_D5/GPIO20 IDE_D6/GPIO21 IDE_D7/GPIO22 IDE_D8/GPIO23 IDE_D9/GPIO24 IDE_D10/GPIO25 IDE_D11/GPIO26 IDE_D12/GPIO27 IDE_D13/GPIO28 IDE_D14/GPIO29 IDE_D15/GPIO30

AD24 AD23 AE22 AC22 AD21 AE20 AB20 AD19 AE19 AC20 AD20 AE21 AB22 AD22 AE23 AC23

SPI_DI/GPIO12 SPI_DO/GPIO11 SPI_CLK/GPIO47 SPI_HOLD#/GPIO31 SPI_CS1#/GPIO32

G6 D2 D1 F4 F3

LAN_RST#/GPIO13 ROM_RST#/GPIO14

U15 J1

FANOUT0/GPIO3 FANOUT1/GPIO48 FANOUT2/GPIO49

M8 M5 M7

FANIN0/GPIO50 FANIN1/GPIO51 FANIN2/GPIO52

P5 P8 R8

TEMP_COMM TEMPIN0/GPIO61 TEMPIN1/GPIO62 TEMPIN2/GPIO63 TEMPIN3/TALERT#/GPIO64

C6 B6 A6 A5 B5

VIN0/GPIO53 VIN1/GPIO54 VIN2/GPIO55 VIN3/GPIO56 VIN4/GPIO57 VIN5/GPIO58 VIN6/GPIO59 VIN7/GPIO60

A4 B4 C4 D4 D5 D6 A7 B7

AVDD

F6

AVSS

G7

SATA_ACT#/GPIO67

AA11

IDE_IORDY IDE_IRQ IDE_A0 IDE_A1 IDE_A2 IDE_DACK# IDE_DRQ IDE_IOR# IDE_IOW# IDE_CS1# IDE_CS3#

Local Frame Buffer Strapping List Copy from Becks.

LFB_ID2 LFB_ID1 LFB_ID0 Hynix

0

0

0

Qimonda

0

0

1

Samsung

0

1

0

LFB_ID0 to LFB_ID2 got internal PU 10K to S5. 2

LFB_ID2

R344 1

2 1K_0402_5%

LFB_ID1

R367 1

2 1K_0402_5%

LFB_ID0

R345 1

2 1K_0402_5%

R1032

SPI ROM

1 1

HW MONITOR

C512 C513

SERIAL ATA

SATA_TXP0 SATA_TXN0

SATA PWR



1

+3VALW +3VALW

11/13 update CR_WAKE#

11/13 update HDD_HALTLED# SB_INT_FLASH_SEL THERMAL_DC R1062

1

2 0_0402_5% WLOFF# BT_COMBO_EN# WWOFF# EC_THERM#

11/05 update

AC_IN_D BT_OFF CAM_SHDN#

11/13 update

LFB_ID0 LFB_ID1 LFB_ID2

3

+SB_AVDD 1 1

2 C525 0.1U_0402_16V4Z

218S7EALA11FG_BGA528_SB700

1 2 @ 10K_0402_5% 1 2 @ 10K_0402_5% R1033

2

+3VALW L56 2 1 BLM18PG121SN1D_0603 C526 2.2U_0603_6.3V4Z

4

A

B

C

D

Rev 0.2

f@

Size Document Number Custom LA-4111P Date:

l.c

ho

SB700 SATA/IDE/SPI

ai

Compal Electronics, Inc. in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Friday, November 30, 2007

Sheet E

xa

2008/08/02

Deciphered Date

21

he

2007/08/02

Issued Date

tm

Compal Secret Data

Security Classification

om

4

of

48

A

B

C

D

E

11/20 update

CORE S0

PCI/GPIO I/O

2 2 2 2 2 2

2 @ 0_0805_5% 2 0_0805_5% 2 C529 C532 1 C534 1 C538 1 C537 1 C527 1 C540 1

C546 C545 C548 C551 C550

1 1 2 2 1

2 2 1 1 2

U15E

+1.2VALW

SB700

+1.2V_HT

L60 2 1 BLM18PG121SN1D_0603

+1.2V_CKVDD

+1.2V_HT

1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z

T10 U10 U11 U12 V11 V14 W9 Y9 Y11 Y14 Y17 AA9 AB9 AB11 AB13 AB15 AB17 AC8 AD8 AE8

AVSS_SATA_1 AVSS_SATA_2 AVSS_SATA_3 AVSS_SATA_4 AVSS_SATA_5 AVSS_SATA_6 AVSS_SATA_7 AVSS_SATA_8 AVSS_SATA_9 AVSS_SATA_10 AVSS_SATA_11 AVSS_SATA_12 AVSS_SATA_13 AVSS_SATA_14 AVSS_SATA_15 AVSS_SATA_16 AVSS_SATA_17 AVSS_SATA_18 AVSS_SATA_19 AVSS_SATA_20

A15 B15 C14 D8 D9 D11 D13 D14 D15 E15 F12 F14 G9 H9 H17 J9 J11 J12 J14 J15 K10 K12 K14 K15

AVSS_USB_1 AVSS_USB_2 AVSS_USB_3 AVSS_USB_4 AVSS_USB_5 AVSS_USB_6 AVSS_USB_7 AVSS_USB_8 AVSS_USB_9 AVSS_USB_10 AVSS_USB_11 AVSS_USB_12 AVSS_USB_13 AVSS_USB_14 AVSS_USB_15 AVSS_USB_16 AVSS_USB_17 AVSS_USB_18 AVSS_USB_19 AVSS_USB_20 AVSS_USB_21 AVSS_USB_22 AVSS_USB_23 AVSS_USB_24

S5_3.3V_1 S5_3.3V_2 S5_3.3V_3 S5_3.3V_4 S5_3.3V_5 S5_3.3V_6 S5_3.3V_7

A17 A24 B17 J4 J5 L1 L2

+S5_3V

S5_1.2V_1 S5_1.2V_2

G2 G4

+S5_1.2V

1 R564

1 22U_A_4VM 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 0_0805_5% 2 2 2 2 2 2 2

1 1 1 1 1 1

C556 C559 C561 C562 C563 C564 C565

+1.2VALW L64

+1.2VALW +1.2_USB

A10 B10

L65

1U_0402_6.3V4Z 2 0.1U_0402_16V4Z 2

0_0603_5%

1 22U_A_4VM 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z 2

2

0_0603_5% 1 C569 1 C570

C573 C574 C575

1 1

+AVDD_USB L66 2 1 FBMA-L11-201209-221LMA30T_0805 1 1 1 1 1 1 1

2 2 2 2 2 2 2

A16 B16 C16 D16 D17 E17 F15 F17 F18 G15 G17 G18

10U_0805_10V4Z 10U_0805_10V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

AVDDTX_0 AVDDTX_1 AVDDTX_2 AVDDTX_3 AVDDTX_4 AVDDTX_5 AVDDRX_0 AVDDRX_1 AVDDRX_2 AVDDRX_3 AVDDRX_4 AVDDRX_5

V5_VREF

AE7

+V5_VREF

AVDDCK_3.3V

J16

+AVDDCK_3.3V

AVDDCK_1.2V AVDDC

1K_0402_5% 2

K17

C578 +AVDDCK_1.2V0.1U_0402_16V4Z

E9

+AVDDC

2

2

1

C579 1U_0603_10V4Z 1

L67 2 1 BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z 2 0.1U_0402_16V4Z

218S7EALA11FG_BGA528_SB700

+AVDDCK_1.2V

2

C585

1

C586

+AVDDCK_3.3V

2

0.1U_0402_16V4Z

2

+3VS

H18 J17 J22 K25 M16 M17 M21 P16 F9

PCIE_CK_VSS_1 PCIE_CK_VSS_2 PCIE_CK_VSS_3 PCIE_CK_VSS_4 PCIE_CK_VSS_5 PCIE_CK_VSS_6 PCIE_CK_VSS_7 PCIE_CK_VSS_8 AVSSC

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50

PCIE_CK_VSS_9 PCIE_CK_VSS_10 PCIE_CK_VSS_11 PCIE_CK_VSS_12 PCIE_CK_VSS_13 PCIE_CK_VSS_14 PCIE_CK_VSS_15 PCIE_CK_VSS_16 PCIE_CK_VSS_17 PCIE_CK_VSS_18 PCIE_CK_VSS_19 PCIE_CK_VSS_20 PCIE_CK_VSS_21

Part 5 of 5

AVSSCK

A2 A25 B1 D7 F20 G19 H8 K9 K11 K16 L4 L7 L10 L11 L12 L14 L16 M6 M10 M11 M13 M15 N4 N12 N14 P6 P9 P10 P11 P13 P15 R1 R2 R4 R9 R10 R12 R14 T11 T12 T14 U4 U14 V6 Y21 AB1 AB19 AB25 AE1 AE24

1

2

P23 R16 R19 T17 U18 U20 V18 V20 V21 W19 W22 W24 W25 3

L17

218S7EALA11FG_BGA528_SB700

+1.2V_HT

1

C587

1

C588

L69 2 1 BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z 2

+5VS

2

+3VALW

L68 2 1 BLM18PG121SN1D_0603

0.1U_0402_16V4Z

1 R346

CH751H-40PT_SOD323-2

1

2.2U_0603_6.3V4Z 2

D14

1

GROUND

AVDD_SATA_1 AVDD_SATA_4 AVDD_SATA_2 AVDD_SATA_3 AVDD_SATA_5 AVDD_SATA_6 AVDD_SATA_7

+3VALW

0.1A/30mil/2vias ? +

L

USB_PHY_1.2V_1 USB_PHY_1.2V_2

Amber

D6

2

11/14 update

HT-297UY5/BP5_YELLOW-WHITE

TP_LED# 3

2 G

4 2 YELLOW

1

HDD_HALTLED#

2

1 R42 2 0_0402_5%

1

@ 10K_0402_5%

@ 2N7002_SOT23-3S

Battery Charge LED

1 2 3 4 5 6 7 8 9 10 GND GND

Reed switch BOARD.

D18 need correct pin connection after netin 11/10 update

L D17

3

R985

WHITE

10/08 update

HT-297UY5/BP5_YELLOW-WHITE

12/03 update

11/10 update

2 2

+5VS 1

YELLOW 3

1

1

2N7002DW-7-F_SOT363-6

R984 390_0402_5%

2

2 2

3 WHITE 4

2N7002DW-7-F_SOT363-6 D Q156

2

D18 need correct pin connection after netin

3

3

SATA_LED#

1

L

D18

6 Q7A

R983 200_0402_5%

390_0402_5%

Q7B 5

09/29 update

JP36

1 2 ON/OFFBTN_LED# 3 4 5 6 7 8 ON/OFF# 9 10 11 12

1

R988

4

1 2

10K_0402_5%

1

R987 200_0402_5%

R20

RM@ 0_0603_5%

1

1

+5VS

R558 10K_0402_5%

+5VS_LED

11/14 update

+5VS_LED

2

+5VS_LED +3VS

R555

RP@0_0603_5%

@ 4.7K_0402_5%

11/20 update

S

C777

11/13 update

HDD/G-Sensor LED

R554

1 1 1

2 R496 @ 10_0402_5%

C780 @4.7U_0805_10V4Z

1000P_0402_50V7K 0.1U_0402_16V4Z

3

1

1

1

1 C779 2

ACES_88020-12101 CONN@

@ C821 2 100P_0402_50V8J

10K_0402_5% HDA_BITCLK_MDC

13 14 15 16 17 18

1 C778 2

GND GND GND GND GND GND

+3VS

1

Q85 SI2301BDS-T1-E3_SOT23-3

2

1 R495 2HDA_SDIN1_MDC 33_0402_5%

R645

+3VS

G

HDA_SYNC_MDC HDA_SDIN1 HDA_RST#_MDC

+3VS

1

1

D

S



2 4 6 8 10 12

TP_CLK TP_DATA

+5V_TP

0_0603_5% 2 3

2 4 6 8 10 12

TP_CLK TP_DATA

@ C820 100P_0402_50V8J 2

Max 0.5A R235 1

JP25 1 3 5 7 9 11

1 2 3 4

9/20 SP01000KC00/SP01E000900

11/01 update 1 3 5 7 9 11

1 2 3 4

G1 G2

ACES_85201-04051 CONN@

+5VALW

HDA_SDOUT_MDC

5 6

9/20 SP01000J100 9/20 STANDOFF (H= 5.0 mm) ES000000800

MDC 1.5 Conn.

TP_BTN#

1

@ D31 PSOT24C_SOT23-3

2

JP37

2

ON/OFF#

SW2 SMT1-05_4P

SW1 SMT1-05-A_4P

1 2 3 4

2

4 6 5

2 1

1 ON/OFF# 2 ON/OFFBTN_LED# 3 4

2

3

@ C819 0.1U_0402_16V4Z

R1038 @ 10K_0402_5%

5 6

1

JP1

11/22 update

1

1

+5VALW_LED

BTN

TP_DATA TP_CLK

Max 0.5A +5V_TP

M/B TO TP/B

+3VALW

1

TP ON/OFF

E

2

ON/OFF Button Connector

D

2 2

for debug only

C

3

B

1

A

HT-F196BP5_WHITE

White LED: VF=3V, IF = 10mA, Res = 200 ohm Amber LED: VF=1.8V, IF = 8mA, Res = 390 ohm

Compal Secret Data

Security Classification 2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Compal Electronics, Inc. TP,MDC,ON/OFF,S/W,LED,Reed

Size Document Number Custom LA-4111P Date:

Rev 0.2

Monday, December 03, 2007

Sheet E

34

of

48

A

B

C

D

E

Atlas/ Saturn Dock +DOCKVIN JDOCK

1

2

1

DOCK@ C831 1000P_0402_50V7K

RED_L GREEN_L BLUE_L D_DDCDATA D_DDCCLK D_HSYNC D_VSYNC USB20_N3 USB20_P3

D_DDCDATA D_DDCCLK D_HSYNC D_ VSYNC USB20_N3 USB20_P3

09/19 update

DOCK_PWR_ON Spec 0V = Notebook S4/S5, Dock off 2.5V = Notebook S3, Dock on 4V = Notebook S0, Dock on



PJP5 1

B+ DOCK@

DOCK_PWR_ON

3

R588 10K_0402_5% DOCK@

L

1

2

DOCK@ C844 1000P_0402_50V7K

H33 @ H_2P8

C942

1

1

H35 @ H_2P8

C Q149 @ MMBT3904_NL_SOT23-3

3

DOCK_LOUT_C_L

R646 1 2 @ 0_0402_5%

E

DOCK@ 1 C944

R992

SPDIFO_L

C943

DOCK@ C945 1 2

2 B

1 2 DOCK@ 0_0603_5%

2 2 DOCK@ 220P_0402_50V7K DOCK@ 220P_0402_50V7K

SPDIF_OUT

0.1U_0402_16V7K R573 DOCK@ 110_0402_5%

2

220P_0402_50V7K

R647 1 2 DOCK@ 220_0402_5%

Q33 2N7002_SOT23-3 DOCK@

09/29 update

R566 47K_0402_5% DOCK@

H34 @ H_2P8

R976 @ 33_0402_5%

DOCK_LOUT_C_R

2

SPDIF

+1.5VS

L

Change PCB Footprint from L_FBM-11-160808_2P to TAI-T_FCM1608KF-601T02_2P Need 600 Ohm 500 mA

MIC_Dock

H36 @ H_2P8

DOCK_MIC_R

DOCK_MIC_L

DOCK@ L94 DOCK@ R942 10K_0402_5% FCM1608KF-601T02_2P DOCK_MIC_R_C 2 1 DOCK_MIC_R_R 1 2 DOCK@ R943 10K_0402_5% DOCK_MIC_L_C 2 1 DOCK_MIC_L_R 1 2 FCM1608KF-601T02_2P DOCK@ L93 1 1 DOCK@ R980 1.21K_0402_1% 10/09 updateDOCK@ C921 DOCK@ C922 2 220P_0402_50V7K 220P_0402_50V7K 2

3

DOCK@ R944 1.21K_0402_1%

H41 @ H_2P8

2

H40 @ H_2P8

1

1

H39 @ H_2P8

2

H37 @ H_2P8

1

1

1

1

1

H32 @ H_2P8

R976/Q149/R646 be option with R992/C945

1 1

DOCK@ C843 1000P_0402_50V7K

2 3

DOCK_VOL_UP# DOCK_VOL_DWN#

+DOCKVIN

R_VOL_DWN#

2 1 1

S

2 G 1

2

D

3

CONA#

DOCK@

MUTE_LED DOCK_SLP_BTN# JACK_DET# DOCK_VOL_UP# DOCK_VOL_DWN#

1

2

R565 10K_0402_5% DOCK@

1

1

CIR_ IN CIR_IN DOCK_PWR_ON MUTELED 1 2 DOCK_SLP_BTN# DOCK@ R591 1K_0402_5% JACK_DET# R_VOL_UP# DOCK@ R567 1 2 200_0402_5% R_VOL_DWN# DOCK@ R568 1 2 200_0402_5% SPDIFO_L AUDIO_OGND DOCK_LOUT_C_R DOCK_LOUT_C_R DOCK_LOUT_C_L DOCK_LOUT_C_L DOCK_MIC_R_C DOCK_MIC_L_C AUDIO_IGND DOCK_PRESENT

L R_VOL_UP#

+3VL_EC

R572 1K_0402_5%

T51 T52 T53

Update symbol finish and swap back JDOCK Pin38/40 , 34/36 , 30/32, 26/28, 22/24, 10/12, 6/8 Add pin 45/46 to GND

1

DOCK_PRESENT

PAD PAD PAD

1

S

41 42 43 44

11/05 update

11/14 update

2 1 Q36 2N7002_SOT23-3 DOCK@

2

D

GND GND GND GND

TV_LUMA_L TV_CRMA_L TV_COMPS_L

CONN@ FOX_QL1122L-H212AR-7F DAN202U_SC70

2 G

SYSON#

3

GND GND

39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

2

PAD-OPEN 2x2m 1

45 46

Digital gnd TV Luma TV chroma TV composite TV ground CIR input PWR_ON Mute_LED Sleep Botton Jack Detect VOL_up VOL_down SPDIF Audio Output gnd Right headphone Left headphone Mic_Right Mic_Left Mic gnd Dock_present

2

+5VS +3VALW

DOCK@ D43 2

2 1K_0402_5% 2 1K_0402_5% DOCK@

CRT_Red CRT_Green CRT_Blue DDC_DATA DDC_Clock Hsync Vsync USBUSB+ Digital gnd MDI3MDI3+ MD2IMDI2+ MDI1MDI1+ MDI0MDI0+ Battery out Battery out

2

1 R586 1 R585

RJ45_MIDI1RJ45_MIDI1+ RJ45_MIDI0RJ45_MIDI0+ +V_BATTERY

RJ45_MIDI1RJ45_MIDI1+ RJ45_MIDI0RJ45_MIDI0+

38 40 34 36 30 32 26 28 22 24 18 20 14 16 10 12 6 8 2 4

1

2

H54 @ H_3P3X0P6N

1

C

D

S

Q100

2 G

DOCK@ 2N7002_SOT23-3

3

S DOCK@ Close Q18 2N7002_SOT23-3

E

to CODEC U27

C978 1

4

1

1

1

1

R913 DOCK@ 47K_0402_5%

D

2 G

2 B 2

SENSE_B# 1

DOCK@ Q16 MMBT3904_NL_SOT23-3

3

DOCK@ R912 1 2 10K_0402_5%

DOCK_MIC_L_C

H52 H53 @ H_1P5N @ H_3P3X0P6N

DOCK@ 1U_0603_10V6K

A

B

C

D

Date:

l.c

ho

DOCK CONN

Rev 0.2

f@

Size Document Number Custom LA-4111P

ai

Compal Electronics, Inc. in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Friday, November 30, 2007

Sheet E

xa

2008/08/02

Deciphered Date

35

he

1

2007/08/02

Issued Date

tm

Compal Secret Data

Security Classification

11/09 update

om

H55 H51 @ H_5P6N @ H_6P0X5P0N

1

4

2 1

1

H48 @ H_3P3

DOCK@ R915 10K_0402_5% 1

1

R914 DOCK@ 10K_0402_5%

3

1

H46 @ H_4P2

1

1

H44 @ H_4P2

2

1

H47 @ H_3P3

H43 @ H_4P2

1

1

H42 @ H_2P8

1

1

+3VS

of

48

A

B

C

D

E

DIM LED

+5VALW_LED Q32

PJP7

RUNON

2

1U_0402_6.3V4Z RUNON 2 R152 1 330K_0402_5%

1

B+

D C834

2

Q17 SUSP 2 2N7002_SOT23-3 G S

1

2

S

2

1

DIM_LED#

2

C1026

2

C836 0.1U_0402_16V4Z

2

2

1 C1024 4.7U_0805_10V4Z

1U_0402_6.3V4Z SI4800BDY_SO8 RUNON_S4 2 R956 1 330K_0402_5% 1 D C1025 Q138

2

1

B+

DIM_LED

DIM_LED

1

C840 2

2

1

C1023 1 2 3 4

D

S

Q51 2N7002_SOT23-3

2 G

1

2

1 4.7U_0805_10V4Z

1

R587 10K_0402_5%

3

1

1

C838

3

+5VS_LED

SYSON# 2 G 2N7002_SOT23-3

Q166

PJP8 1

2

D

+5VS

SI2301BDS-T1-E3_SOT23-3

S

4.7U_0805_10V4Z

1 2 3 4

SI4800BDY_SO8

SI4800BDY_SO8 C864

S S S G

0.01U_0402_25V7K

2

1U_0402_6.3V4Z

1

C839

D D D D

4.7U_0805_10V4Z

2

8 7 6 5

1

S S S G

Q14

1

4.7U_0805_10V4Z

D D D D

C835

3

1

C833 1 2 3 4

0.01U_0402_25V7K

Q35 8 7 6 5

2 PAD-OPEN 2x2m

10/8 update

1 R50 2 @ 0_0603_5% Q137 8 D S 7 D S 6 D S 5 D G

4.7U_0805_10V4Z 1

1

3

+5VS

+5VALW +3V

1

+3VALW

+3VS

D

+3VALW TO +3V

+3VALW

G

+5VALW

+3VALW TO +3VS

S

+5VALW TO +5VS

SI2301BDS-T1-E3_SOT23-3

3

1 1

2

G

PAD-OPEN 2x2m

2

C837

Q12 VLDT_EN# 2 2N7002_SOT23-3 G S

09/13 update

1 C1029

RUNON_S4

2 +1.2V

Q140 2N7002_SOT23-3

D

R598 100K_0402_5%

D

S

EC_ON#

3

SYSON# 2 G S

Reserve until SI-1 stage after SB USB PHY power saving report

Discharge circuit

Q44 2N7002_SOT23-3

2 1 S 2N7002_SOT23-3

EC_ON#

Q41

3

@ 470_0805_5%

1

D

SYSON# 2 G

S

09/29 update (Wait EC Code fix)

D

3

1 Q37

1

S 2N7002_SOT23-3

VLDT_EN#2 G

D

2 G

EC_ON

R368

3

Q48

1

S 2N7002_SOT23-3

2 G

D

3

1 SUSP

Q46

3

1 3

S 2N7002_SOT23-3

D

+1.2VALW

R284 470_0805_5%

1

R280 470_0805_5%

1

R279 470_0805_5%

1

R239 470_0805_5%

D

+1.8V 2

2

2

+1.2V_HT 2

+1.8VS

+5VS

2 G

+5VL

R958 470_0805_5%

Q141 2N7002_SOT23-3

SYSON# 2 G

08/23 new add

SUSP

+3V

R957 470_0805_5%

09/29 update

3

2

S

Q42

2 G

09/13 update (Del +V_DDR_MCH_REFP)

@ 2N7002_SOT23-3

09/13 update

+1.1VS

SYSON#

R597

2

100K_0402_5%

2

SYSON#

SUSP

100K_0402_5% SUSP



S 2N7002_SOT23-3

SUSP

Q52

2 G

SYSON

S 2N7002_SOT23-3

D

S

1

Q38 SYSON 2 G 2N7002_SOT23-3

D

S

3

Q50

2 G

D

1

1 D

3

S 2N7002_SOT23-3

SUSP

1

1 1 Q49

3

3

S 2N7002_SOT23-3

R294 470_0805_5%

3

SYSON# 2 G

Q47

2 G

D

3

1

D

R596

100K_0402_5%

R293 470_0805_5%

1

R292 470_0805_5%

1 1 SUSP 4

2

2

2

2

R595 R288 470_0805_5%

1

+1.5VS

2

+0.9V

Q39 2 G 2N7002_SOT23-3

SUSP#



09/13 update Compal Secret Data

Security Classification 2007/08/02

Issued Date FM1 1

FM2 1

FM3 1

1

CF1 1 A

CF2 1

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CF3

B

C

+5VL

1

+3VS

Change to +3VL(same as EC) to avoid leakage

+5VL

1

+5VL

09/13 update

D

Title

VLDT_EN#

VLDT_EN

VLDT_EN# 1

3

S

2 G Q13 2N7002_SOT23-3

B+

4.7U_0805_10V4Z

2

1U_0402_6.3V4Z Q139

D

2

1

2

2 0.01U_0402_25V7K

2

1

C1028

D

3

SUSP

1U_0402_6.3V4Z 2 R233 1 330K_0402_5%

1

1

D C849

2

C1027 1 2 3

1

1

1

B+

8 7 6 5

3

R138 2 1 330K_0402_5%

4.7U_0805_10V4Z

1

1.8VS_ENABLE

C847

2

1

1

2

1

C862

2

4.7U_0805_10V4Z

C842

1

3

1

4

1U_0402_6.3V4Z

1 2 3

1

1

C846

8 7 6 5

+1.2V

10/8 update

1 R51 2 @ 0_0603_5% IRF8113PBF_SO8

1

2

C841 10U_0805_10V4Z

+1.2VALW

2

2

C848

4

4.7U_0805_10V4Z

2

1 2 3

+1.2V_HT

Q11 IRF8113PBF_SO8

1

1

8 7 6 5

+1.2VALW

3

Q4 IRF8113PBF_SO8

4

+1.8VS

0.01U_0402_25V7K

+1.8V

11/06 update

+1.2VALW TO +1.2V

+1.2VALW TO +1.2V_HT

4.7U_0805_10V4Z

+1.8V TO +1.8VS

C1069 0.1U_0402_16V4Z

2

DIM_LED#

S

VLDT_EN 2 G

Q40 2N7002_SOT23-3

4

Compal Electronics, Inc. DC/DC Circuits

Size Document Number Custom LA-4111P Date:

Rev 0.2 Sheet

Friday, November 30, 2007 E

36

of

48

A

B

C

D

E

BATT1

45@ CR2032 RTC BATTERY

+3VALW

1

PQ3 TP0610K-T1-E3_SOT23-3

3

1

499K_0402_1% 340K_0402_1% PR4 1 PR1 1 2 2

BATT

PJP2 8 7 6 5 4 3 2 1 9 10

EC_SMD EC_SMC

PD2 @SM05_SOT23

8

105K_0402_1% PR6 1 2

+

0 -

PU1A LM358ADT_SO8

PR5 10K_0402_5% 2 1

1

BATT_OVP

2

PH1 under CPU botten side : CPU thermal protection at 90 +-3 degree C Recovery at 47 +-3 degree C

PL3 HCB2012KF-121T50_0805 1 2

1 2 PL4 HCB2012KF-121T50_0805

1

3

BATT

1 2

PC8 1000P_0402_50V7K

PC9 0.01U_0402_50V4Z

2

2

2

3

8 7 6 5 4 3 2 1 GND GND

2

1

VMB

PC5 1000P_0402_50V7K 2 1

PC4 100P_0402_50V8J 2 1

1

PJSOT24C_SOT23-3

PC3 1000P_0402_50V7K

2

PD1 2

1

2 1 PC2 100P_0402_50V8J

3

2

PJP1

1

ADPIN

PL2 SMB3025500YA_2P 2 1

P

3 PL1 SMB3025500YA_2P 1 2

G

2

+DOCKVIN

2

5 4 3 2 1

VIN

RLZ3.6B_LL34

1 2 PR3 10K_0402_5% 0.01U_0402_25V7K PC6

5 4 3 2 1

2

2 ADP_SIGNAL

@1000P_0402_50V7K

+5VALW

4

PD4 PR2 10K_0402_5%

1

ACES_88334-057N

PC12 1

PR8 100_0402_5%

1

1

2 1

ADP_ID

0.01U_0402_25V7K PC1 2 1

AC_LED

2

SUYIN_200275MR008GXOLZR

PR7 47K_0402_1% 1 2

+5VS

3

3

PH1

2

+

1

6

-

PR15 150K_0402_1%

4

2

2 BATT_TEMP

0

S

D

S

PQ1 SSM3K7002FU_SC70-3

2 G

7

PU1B LM358ADT_SO8

1

PR12 2.55K_0402_1%

D

PC11 1000P_0402_50V7K

2

PC10 0.22U_0603_10V7K

2

+3VL

2 PR11 150K_0402_1%

1

1

+5VALW

PR17 1K_0402_5% 2

5

1

PR16 6.49K_0402_1% 1 2

ENTRIP1

PR10 15K_0402_1% 1 2

1

3

SMB_EC_CK1

1

1 2 PR9 10K_0402_5% BAT_ID

1

SMB_EC_CK1

10KB_0603_1%_TH11-3H103FT

3

8

SMB_EC_DA1

P

SMB_EC_DA1

2

2

+3VL

PD3 @SM24.TC_SOT23-3

G

PR14 100_0402_5%

PR13 100_0402_5%

1

1

1

1

CPU

ENTRIP2

PQ2 SSM3K7002FU_SC70-3

2 G

4

A

B

C

D

l.c ai

Compal Electronics, Inc. ho

DC Connector/CPU_OTP Date:

Rev 0.1

f@

Size Document Number Custom LA-4111P

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Friday, November 30, 2007

Sheet E

xa

2008/08/02

Deciphered Date

37

he

2007/08/02

Issued Date

tm

Compal Secret Data

Security Classification

om

4

of

48

A

B

C

P4

D

B+

BATT VIN

P2 PQ102 AM4835EP-T1-PF_SO8

25

12

VADJ

REGN

24

RE GN 2

LODRV

23

DL _CHG

EXTPWR

4

1 2

1

DPMDET

3 2 1

21

1 1

3

1

20

19

18

1

2

BAT_ID

PC122 @0.1U_0603_25V7K

1

1

IREF

PR121 200K_0402_1%

PR122 681K_0402_1% 1 2

2

PC124 0.1U_0603_25V7K

1

3

BATT

PR120 2 1 133K_0402_1%

2

17

16

2

CELLS

SRP

SRN

BAT

IADAPT

PR123 1M_0402_5% 1 2

@47K_0402_5% PR119 2 G

S

2

PC123 0.1U_0402_10V7K

2

BQ24740VREF

D PQ111 SSM3K7002FU_SC70-3

1

2

PC118 0.1U_0402_10V7K

1U_0603_10V6K

1

PC120 0.22U_0603_10V7K 2 1

ADP_I

PC119

PR117 100K_0402_5% 1 2

PC121 100P_0402_50V8J 2 1

PR118 10K_0402_5% 1 2

Charge Detector

BATT

PR112 0.015_1206_1% 1 2

5 6 7 8 PQ110 AO4466_SO8

22

IADAPT

15

2

2

PR116 39K_0402_5%

PGND SRSET

ISYNSET

1

1

14

PQ106 DTC115EUA_SC70-3

1

4 PR115 100K_0402_1%

3

5 6 7 8

PL102 10U_LF919AS-100M-P3_4.5A_20% 1 2

1

13

2

1 2

PC105 4.7U_0805_25V6-K

1 2

PD102 VA DJ

3

P2 BQ24740VREF

PR124 1K_0402_5% 1 2

VIN

1

VIN

4

2

7

1

PACIN 1

8 P G

2 1

O

LM393DG_SO8

PR134 10K_0402_5%

PD103 RLZ4.3B_LL34

S FSTCHG# 1 2 G

FSTCHG

STD_ADP

PR136 49.9K_0402_1% 1 2

D

P2

PQ113 SSM3K7002FU_SC70-3 3

1.24VREF

PR133 10K_0603_0.1%

PU102B

2

PU102A LM393DG_SO8

-

2

PQ112 SSM3K7002FU_SC70-3

+

6

2

D

2 G

PC126 0.047U_0402_16V7K

5

PR127 10K_0402_1%

2

1

2

PR135 10K_0603_0.1%

G

1

O

1

PR132 100K_0402_5% 2 1

1 -

3

+

2

P

3

PR130 2.15K_0402_1% 1 2

4

PR128 10K_0402_5% 2 1

1 2

CH GEN#

8

2

PC125 0.1U_0603_25V7K

PR129 10K_0402_1% 2 1

2

1 PR131 133K_0402_1%

PR126 100K_0402_1% +3VL

AC_IN

1

1

+3VL PR125 47_1206_5%

VIN

PC116 4.7U_0805_25V6-K

PH

ACOFF

PQ108 AO4466_SO8

3 2 1 VDAC

1

11

2

PC115 4.7U_0805_25V6-K 2 1

DH_CHG LX_CHG

S PQ114 SSM3K7002FU_SC70-3

1

26

D

2 G

2

HIDRV

PU101 BQ24740RHDR_QFN28_5X5

VREF

PC111 0.1U_0402_10V7K 1 2 4

BST_CHG

PR139 100K_0402_5% 1 2

PC114 4.7U_0805_25V6-K

27

RLS4148_LL34-2

2

PC117 1U_0603_10V6K

+3VLP

PC113 4.7U_0805_25V6-K 2 1

28

BTST

2

VCTRL

PC104 4.7U_0805_25V6-K

1 2 2 1

2

CHGEN

ACP

ACN

3

5

4 LPMD

ACDET

7

6

PVCC

AGND

1

AC_LED

PA CIN

PC110 1U_0805_25V6K 1 2

IADSLP

VIN

PR105 10K_0402_5%

CHG_B+

29

1

PR103 47K_0402_5% 1 2

A COFF#

PR108 10_1206_5% 1 2 TP

8 7 6 5

CHG_B+

+3VL

2

PD101 RLS4148_LL34-2

PR114 @0_0402_5% 1 2

PC103 4.7U_0805_25V6-K

1

1 2

PC108

PC109 @0.1U_0603_25V7K

9 10

PR113 143K_0402_1%

S

2

3

PC102 1U_0603_6.3V6M 1 2

8

BQ24740VREF

1U_0603_6.3V6M PQ109 SSM3K7002FU_SC70-3

3 1

LPREF

PR110 0_0402_5% 1 2

SUSP#

D

2 G

1 2 3

PL101 HCB2012KF-121T50_0805 2

2 1

PR111 3K_0402_1% 1 2

A COFF#

2

1

CH GEN#

PC112 1 2

PA CIN

0.1U_0603_25V7K

1 PC107 @0.01U_0402_16V7K

PR109

150K_0402_5% PQ107 SSM3K7002FU_SC70-3

ACSET

ACSET

1

AC_SET

2 1 PR106 200K_0402_5%

PC106 0.22U_0603_16V7K 2 1

3

1 2

1

2 G

ACDET

PR104 0_0402_5% 1 2

1

3

S

DTA144EUA_SC70-3 PQ104

PQ105 DTC115EUA_SC70-3

3

1

D

PR102 0.012_2512_1% 1 2

8 7 6 5

2

2

1 2 3

4

PR101 47K_0402_5% 1 2

PC101 47P_0402_50V8J PR107 47K_0402_1% 1 2

PQ103 AM4835EP-T1-PF_SO8

1 2 3

4

8 7 6 5

2

PQ101 AM4835EP-T1-PF_SO8

1

S PU103 4

ACDET

2

2

22P_0402_50V8J 2

100K_0402_1% PR138

4

1

PC127 PR137 20K_0402_1%

CATHODE

3

NC

2

5

NC

1

1.24VREF

ANODE

4

APL1431LBBC-TR_SOT23-5

Compal Secret Data

Security Classification Issued Date

2007/05/29

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

REF

1

1

B

C

Title

Compal Electronics, Inc. Charger

Size

Document Number

Rev 0.1

LA-3941P Date:

Friday, November 30, 2007 D

Sheet

38

of

48

A

B

C

D

E

1

2VREF_51125

PR303 20K_0402_1% 1 2

1

PR304 20K_0402_1% 2

22

DRVH1

21

11

LL2

LL1

20

LX_5V

12

DRVL2

DRVL1

19

LG_5V

5 6 7 8

+5VALWP

1

1 PR316 @4.7_1206_5%

+3VL PR317 100K_0402_5%

3 2 1

2

2

PC319 @22U_0805_6.3V6M PC310 150U_D_6.3VM

2

PC311 10U_0805_10V6K

1

2

1

2

3/5V_OK

+

PC315 @680P_0603_50V8J PQ304 FDS6690AS_NL_SO8

VL

PR311 620K_0402_5%

1

1 2

4

2

PU301 TPS51125RGER_QFN24_4X4

2

VCLK 18

VIN

VREG5 17

16

EN0

PL303 4.7UH_PCMC063T-4R7MN_5.5A_20% 1 2 1

VBST1

DRVH2

2

3 2 1

VBST2

13

PC313 4.7U_0805_25V6-K

2

3

1

VFB1

VREF

TONSEL

ENTRIP1

4 PR308 PC308 0_0402_5% 0.1U_0402_10V7K BST_5V 1 PR310 2 1 2 0_0402_5% UG_5V 1 2

1

PC314 @680P_0603_50V8J

23

9

1 2

2

24

10

PR315 @4.7_1206_5%

+

VO1 PGOOD

PQ302 AO4466_SO8

5 6 7 8

VREG3

1

VO2

8

GND

UG_3V

7

14

1 PC309 220U_6.3VM_R15

1 2 1 2 0_0402_5% PC307 0.1U_0402_10V7K LX_3V LG_3V

1

+3VALWP

P PAD

15

PL302 4.7UH_SIQB74B-4R7PF_4A_20% 2 1

BST_3V

VFB2

25

PR307 PR309 0_0402_5% 1 2

4

5

6 SP8K10S-FD5_SO8

2

PC306 10U_0805_6.3V6M

ENTRIP2

8 7 6 5

SKIPSEL

1G 1S/2D 1S/2D 1S/2D

2

PR306 133K_0402_1% 2

1

1

D1 D1 G2 S2

2

1 2

PC303 4.7U_0805_25V6-K

2

PQ301 1 2 3 4

UG1_3V

PC301 2200P_0402_50V7K 2 1

PR305 174K_0402_1% 1

B++

PC305 4.7U_0805_25V6-K 2 1

+3VLP

2 PC316 @0.1U_0402_25V4K 2 1

1

PR302 30.9K_0402_1% 2

PC304 2200P_0402_50V7K 2 1

PL301 HCB2012KF-121T50_0805

1

ENTRIP1

B++

B+

2

ENTRIP2

PR301 13.7K_0402_1% 1

1

PC317 @0.1U_0402_25V4K 2 1

PC302 0.22U_0603_10V7K

2

1

B++ ENTRIP1

ENTRIP2

2

3

PC312 0.1U_0603_25V7K

3

2 G

1

D PQ305 SSM3K7002FU_SC70-3

D

3

1

2VREF_51125

S

PQ306 SSM3K7002FU_SC70-3

2 G

3

S

PJP301

1

VL

PQ307 SSM3K7002FU_SC70-3 2 G

2

+5VALW

(4.5A,180mils ,Via NO.= 9)

+3VALW

(3A,120mils ,Via NO.= 6)

1 PAD-OPEN 2x2m

PAD-OPEN 4x4m PJP303 1

+3VALWP

2

+5VL

VL PJP304

PAD-OPEN 4x4m

2

EC_ON

1 PAD-OPEN 2x2m

S

1

3

S

D

1

+5VALWP

2

PR314 100K_0402_5% 2

PC318 0.022U_0603_25V7K

D

2

1

AC_IN

3

PQ308 SSM3K7002FU_SC70-3 1 2 2 PR318 G 330K_0402_1%

1

1

PR313 100K_0402_5% 2

+3VL

+3VLP PJP302

4

A

B

C

D

3.3VALWP/5VALWP Date:

l.c ai Rev 0.1

f@

Size Document Number Custom LA-4111P

tm

Compal Electronics, Inc. in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Friday, November 30, 2007

Sheet E

xa

2008/08/02

Deciphered Date

39

he

2007/08/02

Issued Date

ho

Compal Secret Data

Security Classification

om

4

of

48

A

B

C

D

1

1

PR401 0_0402_5% 1 2

PL401

VOUT

4

V5FILT

5

VFB

13

DH_1.8V

LL

12

LX_1.8V

TRIP

11

V5DRV

10

PR410 1 2 0_0402_5%

3 2 1

DRVH

DH_1.8V_1

PQ401 AO4466_SO8

+5VALW

2 PR406 15.4K_0402_1%

1 2

4.7U_0805_25V6-K PC404 2 1

PR407 @4.7_1206_5%

1 +

2 2

PC415 4.7U_0805_10V6K

9

DRVL

15

4

2

PGND

1

TPS51117RGYR_QFN14_3.5x3.5 DL_1.8V

3 2 1

1 2 14.3K_0603_0.1%

PC406 @680P_0402_50V7K 2

PL402 2.2UH_PCMC063T-2R2MN_8A_20% 1 2

5 6 7 8

1

1

PR408

7

+1.8VP

PGOOD

8

6

2

1

PC409 1U_0603_10V6K

B+

14

4

2 PC412 @680P_0603_50V7K

PC408 220U_D2_4VY_R25M

3

TP

1

TON

PC402 0.1U_0402_10V7K

HCB1608KF-121T30_0603 1 2

1

2 1 0_0402_5%

2

VBST

2 PR405

EN_PSV

PU401 PR404 255K_0402_1% 1 2

2

4.7U_0805_25V6-K PC403 2 1

BST1_1.8V 1

PR402 0_0402_5%

PR403 316_0402_1%

+1.8VP

2

2

BST_1.8V 1

GND

2

1

5 6 7 8

1+5VALW

+5VALW

@0.1U_0402_25V4K PC414 2 1

1.8V_B+

2

PC401 @1000P_0402_50V7K

2200P_0402_50V7K PC405

1

SYSON

+1.8VP

PQ402 FDS6690AS_NL_SO8

1

1 2 PC413 @10P_0402_50V8J

3

3

2

PR409 10K_0603_0.1%

PJP401

1

+1.8VP

2

+1.8V

(7A,280mils ,Via NO.= 14)

PAD-OPEN 4x4m

4

4

Compal Secret Data

Security Classification Issued Date

2007/05/29

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

Title

Compal Electronics, Inc. 1.8VP

Size

Document Number

Rev 0.1

LA-3941P Date:

Friday, November 30, 2007 D

Sheet

40

of

48

A

B

C

D

E

1

1

PR501 11.5K_0402_1%

2

1 2 PR517 10_0402_5%

1

2

PR502 24.9K_0402_1%

PR503 18.7K_0402_1%

PR504 11.5K_0402_1%

1

2

2

2

+1.2VALWP

1

B+++

B+ PL502 HCB2012KF-121T50_0805 2 1

2 0_0402_5%

1 PR508

8 7 6 5

10

LX_1.1V

11

LL2

LG_1.1V

12

DR VL2

5 6 7 8

1

2

VO1

VFB1

4

3

23

4

VBST2

VBST1

22

BST_1.2V

DR VH2

DR VH1

21

UG_1.2V

LL1

20

LX_1.2V

DR VL1

19

LG_1.2V

PR507 0_0402_5% 2 1 2

PC507 0.1U_0402_10V7K 1

2 UG1_1.2V

1 PR509 0_0402_5%

1 2

PGND1

TRIP1

18

PR510 17.8K_0402_1%

1

PR512 33K_0402_5% 2

1

2

+5VALW

1

1 2

PC514 1U_0603_10V6K

2

2

1

PR514 3.3_0402_5% PC513 @0.1U_0402_10V7K

PC512 0.1U_0402_16V7K

PC515 4.7U_0805_10V6K

(4A,160mils ,Via NO.=8)

PJP501 1

2

3/5V_OK

(6A,240mils ,Via NO.=12)

+1.1VSP

2

3

1

1

SUSP#

PC520 @680P_0603_50V8J

1

+

2

PR513 0_0402_5% 2

+1.2VALWP

3 2 1

PR511 19.1K_0402_1% 1 2

PR516 @4.7_1206_5%

4 PQ504 AO4466_SO8

1

PQ503 FDS6690AS_NL_SO8

+1.2VALWP

PL503 3.3UH_SIQB74B-3R3PF_5.9A_20% 1 2

TPS51124RGER_QFN24_4x4

17

V5FILT

V5IN 16

15

TRIP2

PGND2 13

4

2 3

PC516 @0.1U_0402_25V4K 2 1

9

UG_1.1V

GND

24

EN1

5 6 7 8

BST_1.1V

TONSEL

6

5

VO2

PGOOD1

14

PC519 @680P_0603_50V8J

1 2 3

2

EN2

1 2

+

PR515 @4.7_1206_5%

PGOOD2

8

2

1

PC509 4.7U_0805_6.3V6K 2 1

PC508 220U_D2_4VY_R25M

1

+1.1VSP

UG1_1.1V

PL501 2.2UH_PCMC063T-2R2MN_8A_20% 2 1

7

2

PC511 220U_D2_4VY_R25M

1 2 3

PC506 PR506 0.1U_0402_10V7K 0_0402_5% 2 1 2 1

PQ502 AO4466_SO8

1

4

P PAD

3 2 1

AO4466_SO8

+1.1VSP

PU501 25

2

PQ501

VFB2

PC503 @0.022U_0603_25V7K

2

1

8 7 6 5

VCCP_POK

PC510 4.7U_0805_6.3V6K 1 2

+1.1VSP

PC505 2200P_0402_50V7K 2 1

1

PR505 0_0402_5% PC518 @0.1U_0402_25V4K 2 1

PC502 2200P_0402_50V7K 2 1

1 2

PC501 4.7U_0805_25V6-K 2 1

PC517 4.7U_0805_25V6-K

B+++

1

PC504 4.7U_0805_25V6-K 2 1

+1.1VSP

2

PR518 0_0402_5% 1

+1.1VS

B+++

PJP502 2

+1.1VS

1

+1.2VALWP

PAD-OPEN 4x4m

2

+1.2VALW

PAD-OPEN 4x4m

PJP503 4

+1.1VSP

1

2

4

+1.1VS

A

B

C

D

1.1VSP/1.2VALWP Date:

l.c ai Rev 0.1

f@

Size Document Number Custom LA-4111P

tm

Compal Electronics, Inc. in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Friday, November 30, 2007

Sheet E

xa

2008/08/02

Deciphered Date

41

he

2007/08/02

Issued Date

ho

Compal Secret Data

Security Classification

om

PAD-OPEN 4x4m

of

48

A

B

C

D

E

1

1

+1.8V +1.8V

PU603

+5VALW

NC

8

TP

9

PC603 1U_0603_16V6K

G2992F1U_SO8

6

NC

5

3

VREF

NC

7

4

VOUT

NC

8

TP

9

+5VALW

PR606 1K_0402_1%

1

VOUT

VCNTL

GND

2

4

PC613 10U_0805_10V4Z

VIN

2 1

NC

1

VREF

7

2

3

1

2

5 1

6

NC

2

VCNTL

PC609 @10U_0805_10V4Z

GND

1

VIN

2

2

1

1 PR601 1K_0402_1% 2

1 2

2

PC601 10U_0805_10V4Z

PC602 @10U_0805_10V4Z

1

PU601

PC612 1U_0603_16V6K

G2992F1U_SO8

PR608 0_0402_5%

2

PC606 @0.1U_0402_16V7K

S

2

1

D

2 G

+1.5VSP

2

1 2

PR607 5.1K_0402_1% 2

1

SUSP

1

1 PC605 10U_0805_6.3V6M

3

S

PQ602 SSM3K7002FU_SC70-3

1

2 G

+0.9VP

2

2

PR604 @0_0402_5%

PR603 1K_0402_1%

D 2

1

1

SUSP

2 1 PC604 0.1U_0402_16V7K

PQ601 SSM3K7002FU_SC70-3 2

1

1

2 PR602 0_0402_5%

2 1 PC611 0.1U_0402_16V7K

VREF1.5V

1

3

SYSON#

PC614 10U_0805_6.3V6M

2

PC610 @0.1U_0402_16V7K

(500mA,40mils ,Via NO.= 1)

PU602 APL5508-25DC-TRL_SOT89-3

2

1

PAD-OPEN 3x3m

2

PJP603 +1.5VSP

1

2

+1.5VS

(1A,40mils ,Via NO.= 2)

+2.5VS

(500mA,40mils ,Via NO.= 1)

IN

OUT

+2.5VSP

3

GND 1

3

1

(2A,80mils ,Via NO.= 4)

PR605 @150_1206_5% 2

+0.9V

1

2

2

1

PC607 1U_0603_6.3V6M

+0.9VP

3

+3VS

PC608 4.7U_0805_6.3V6K

PJP601

PAD-OPEN 3x3m

PJP602 +2.5VSP

1

2 PAD-OPEN 3x3m

4

4

Compal Secret Data

Security Classification 2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Compal Electronics, Inc. 0.9VSP/2.5VSP/1.5VSP

Size Document Number Custom LA-4111P Date:

Rev 0.1 Sheet

Friday, November 30, 2007 E

42

of

48

B

C

8 7 6 5

1

1 2

2

1

UGATE NB1

PHASE NB

LGATE NB

PC204 4.7U_0805_25V6-K

2 PR205 2_0402_5% 1 2

A

B

1 2

PC249 3300P_0402_50V7K 2 1 PC250 1800P_0402_50V7K 2 1 PC211 @47U_25V_M

PC248 3300P_0402_50V7K 2 1

PC214 2200P_0402_50V7K 2 1

PC213 4.7U_0805_25V6-K 2 1

PC212 4.7U_0805_25V6-K 2 1

PC235 4.7U_0805_25V6-K 2 1

D D D D

PC234 4.7U_0805_25V6-K 2 1

5 6 7 8 G S S S 4 3 2 1

PR221 14K_0402_1% 2 1

1

PR220 4.7_1206_5%

1 2 2

PC218 470P_0603_50V8J

3 2 1

3 2 1

1 2

4

AO4456_SO8

3 2 1

PQ208 3 2 1

PQ207

ISP 1

AO4456_SO8

2 2

1

1

PC222 2200P_0402_50V7K 2 1

PC221 4.7U_0805_25V6-K 2 1 1

2

ISP 1

1 PR238 54.9K_0402_1% 2 1 PJP201

PC232 1200P_0402_50V7K PR240 1K_0402_1% 2 1

2

1 +CPU_CORE_1 PL204 0.36UH_PCMC104T-R36MN1R17_30A_20%

PR233 6.65K_0603_1% 1 2

PC229 0.1U_0603_25V7K

PC231 180P_0402_50V8J PR236 6.81K_0402_1%

PC220 4.7U_0805_25V6-K 2 1

PC226 470P_0603_50V8J

PC230 1000P_0402_50V7K 2 1

1

PR231 14K_0402_1% 2 1

1 PR229 4.7_1206_5%

2

+CPU_CORE_1

2

PC236 4.7U_0805_25V6-K 2 1

PC237 4.7U_0805_25V6-K 2 1

PC240 @0.1U_0402_25V4K 2 1

5 6 7 8 D D D D G S S S 4 3 2 1 5 6 7 8

5 6 7 8

PC224 0.22U_0603_10V7K

4

2

2

3

2

+CPU_CORE_0

1

2

+CPU_CORE_1

PAD-OPEN 4x4m PJP202

PR243 255_0402_1% 2 1

+CPU_CORE_0

1

4

2

+CPU_CORE_1

PAD-OPEN 4x4m

Compal Secret Data

Security Classification 2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C

D

Title

Compal Electronics, Inc. CPU_CORE

Size Document Number Custom LA-4111P Date:

om

4700P_0402_25V7K PC233

tm

1 PR241 0_0402_5%

UGATE1_1

49

TP

1 PR228 2.2_0603_5%

PR226 1 2 0_0603_5% 2 1 2

ho

CPU_VDD1_FB_H

2

Rev 0.1

f@

1 ISP 0

in

1 PR239 0_0402_5%

1

CPU_VDD1_FB_L

2

PC242 2 1000P_0402_50V7K

PC219 0.1U_0603_25V7K

Friday, November 30, 2007

Sheet E

xa

4

PQ205 AO4456_SO8

PR217 6.65K_0603_1% 1 2

43

he

CPU_VDD0_FB_L

2

4

+CPU_CORE_0

CPU_B+

2 2

1 PR237 0_0402_5%

5 6 7 8

5 6 7 8 BOOT0

UGATE_NB

PHASE_NB ISP1

ISN1 24

23

VW1 22

21

20

18 VSEN1

COMP1

25

BOOT1

FB1

UGATE1

PC241 2 1000P_0402_50V7K

PC239 330P_0402_50V7K 2 1

1 2

2 BOOT_NB

PHASE NB

UGATE NB 37

38

39

LGATE NB PGND_NB

LGATE_NB

OCSET_NB

RTN_NB

VSEN_NB

PHASE1

26

VDIFF1

27

UGATE1

2

PC215 1000P_0402_50V7K

1 BOOT_NB1 2 1

PR207 11.3K_0402_1%

2

1 43

44

45

PHASE1

COMP0

BOOT1

4

LGATE1

FB0

VW0

PQ204 AO4456_SO8

PQ206 SI4684DY-T1-E3_SO8

11

6.81K_0402_1%

1 PR235 0_0402_5%

FSET_NB

28

1

CPU_VDD0_FB_H

COMP_NB

29

PGND1

PR232 1

46

LGATE1

VDIFF0

1 2 PC228 1000P_0402_50V7K

VCC

OCSET ISL6265IRZ-T_QFN48_6X6

+ 2

PL203

LGATE0

10

12

54.9K_0402_1%

FB_NB

30

PC225 1 2

1200P_0402_50V7K 1 2 PC227 180P_0402_50V8J

48 VIN

9

PVCC

17

2

8

32 31

ISP0

PR230

RBIAS

2

1K_0402_1%

1

7

PGND0 LGATE0

16

1

ENABLE

RTN1

3

SVC

6

VSEN1

4700P_0402_25V7K PR227

5

RTN0

2

255_0402_1%

33

15

1

95.3K_0402_1%

PC223 1 2

PHASE0

PHASE0

19

21K_0402_1%

2

UGATE0

UGATE0

RTN1

1

1

0.36UH_PCMC104T-R36MN1R17_30A_20% 2 1

1 2 0_0603_5% PR219

36

SVD

VSEN0

2

1

UGATE0_1

2.2_0603_5% 0.22U_0603_10V7K PR214 PC217 1 2 1 2

35

PWROK

ISN0

PR224

PC210 2.2U_0603_6.3V6K

PQ203 SI4684DY-T1-E3_SO8

BOOT0

4

VSEN0

1

PR225

SVC

PR223

2

+5VS

BOOT_NB

34

1 @1000P_0402_50V7K PC244 2 1 @1000P_0402_50V7K PC245 2 1 @1000P_0402_50V7K PC246 1 @1000P_0402_50V7K PC247

VR_ON

PL202 SMB3025500YA_2P

2

3

14

CPU_SVC

SVD

PGOOD

13

PR218 1 2 0_0402_5% PR2221 2 0_0402_5%

CPU_SVD

OFS/VFIXEN

2

ISP 0

SB_PWRGD

1

+CPU_CORE_0

VGATE

PU201

47

PR216 10K_0402_1% 2 1

PR215 @10K_0402_5%

B+

CPU_B+

PR211 1_0603_5%

40

2 PR212 0_0402_5% 1 2 PR213 @0_0402_5% 1 2

PC206 0.1U_0603_16V7K

2

VSEN_NB

1

RTN0

+5VS

+3VS

2

1

41

2

PC216 0.1U_0603_25V7K

PC243 1000P_0402_50V7K

1

CPU_B+

RTN_NB

PR208 2_0402_5% 1 2

42

2

33P_0402_50V8K PC209 2 1

PC207 0.1U_0402_16V7K

2 1 2 1 PR210 PC208 44.2K_0402_1% 1200P_0402_50V7K

1

+5VS

l.c

PC205 1000P_0402_50V7K

ai

1

1 PR209 0_0402_5%

PR204 22K_0402_1% 1 2

PR203 0_0402_5%

2

PR206 0_0402_5% 2 1

1

PC203 2200P_0402_50V7K

CPU_B+

1

2

1 2 3

2

VDD_NB_FB_L

1 2 3

2

PC202 220U_D2_4VY_R25M

4

1 2

VDD_NB_FB_H

+

E

PQ202 AO4466_SO8

PQ201 AO4466_SO8 8 7 6 5

1

10U_0805_6.3V6M PC201

D

2 1 4.7UH_SIQB74B-4R7PF_4A_20%

PC238 470P_0402_50V7K

PL201

+CPU_CORE_NB

4

A

of

48

A

B

C

D

E

Version Change List ( P. I. R. List ) for Power Circuit Item Page# 1

Title

Date Request Owner

Issue Description

Rev.

Solution Description

1

37

DC Connector /CPU_OTP

9/29

Compal

for Layout

PL3 change the value from SMB3025500YA_2P to HCB2012KF-121T50_0805 and add PL4 the same of the value.

2

41

1.1VSP/1.2VALWP

9/29

Compal

HW request

PC508 and PC511 change the value from 220U_6.3VM_R15 to 220U_D24VY_R25M

3

41

1.1VSP/1.2VALWP

9/29

Compal

HW request

Add PJP503

4

43

CPU_CORE

9/29

Compal

HW request

PC202 change the value from 220U_6.3VM_R15 to 220U_D24VY_R25M

5

43

CPU_CORE

9/29

Compal

TI FAE suggested that after he review the layout.

Add PC241、PC242、PC243, and the value are 1000P_0402_50V7K. Reserve PC244、PC245、PC246、PC247, and the value are 1000P_0402_50V7K.

6

43

CPU_CORE

9/29

Compal

TI FAE suggested that after he review the layout.

Add PJP201、PJP202

7

38

Charger

9/29

Compal

the footprint is wrong

Change the footprint of PR102

8

37

10/08

Compal

for Layout

These two choke are parallel ,it's not series.

9

38

Charger

10/08

Compal

the footprint is wrong

Change the footprint of PR102

10

40

1.8VP

10/08

Compal

PWR request

Delete PC410 and PC411

11

41

1.1VSP/1.2VALWP 10/08

Compal

PWR request

Add PR517、PR518

2

DC Connector /CPU_OTP

1

2

3

3

12

37

13

37

14

43

15

37

DC Connector /CPU_OTP 3.3VALWP/5VALWP CPU_CORE 3.3VALWP/5VALWP

11/01

Compal

PWR request

Add PD4、PC12

11/01

Compal

for Layout

change PQ301, Cencel PQ303

11/02

Compal

EMI request

Add PC248, PC249, PC250

11/12

Compal

for Layout

Change PC310, add PC319

4

4

Compal Secret Data

Security Classification 2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Compal Electronics, Inc. Power Changed-List History-1

Size Document Number Custom LA-4111P Date:

Rev 0.1 Sheet

Friday, November 30, 2007 E

44

of

48

A

B

C

D

E

Version Change List ( P. I. R. List ) for HW Circuit

29 4

Audio FAN

6

29

7

CRT can not display

10/30 11/01

HW HW

Speaker no sound FAN Conn. not correct part

Speaker

11/01

HW

Speaker Conn. not correct part

34

MDC

11/01

HW

MDC Conn. not correct part

8 9

11,35 11,21

TV_OUT 11/05 NB/SB Thermal 11/05

HW HW

TV-OUT Function no support NB Thermal Function no support (locate too far)

10

21,31

SB SATA

11/05

HW

11

21

SB SATA

11/05

HW

SB SATA Port 5 change to Port 2 for ATI Common Design SB SATA_ACT# Pull High become +3VS

12

21

SB GPIO

11/05

HW

Change SB GPIO refer to JBK00 for common

13 14 15 16 17

31 29 25 21,24 36

SB SATA 11/05 Audio HP OUT 11/05 LAN Transfermor11/05 SB SATA 11/06 DIM LED 11/06

HW HW HW HW HW

Vertical L51 14 , 23 for layout routing Add 150UF Caps for each DOCK_LOUT_R/L Correct U19 LAN Transfermor pin definition SB SATA Port 4 change to Port 3 for ATI Open Issue Reduce DIM LED unnecessary design

18

27

CardReader

HW

Change CardReader Socket for M/E new part and Chip for JMicron new version

11/06

4

0 .2

2007/08/02

B

C

0 .2 0 .2 0 .2 0 .2

2

0 .2

Change R343.1 power rail from +5VS to +3VS. Install R343.

0 .2

1. Connect U15.C6 to GND by 0_0402. 2. Change WLOFF# from GPIO50 to GPIO61. 3. Change BT_COMBO_EN# from GPIO51 to GPIO62. 4. Change WWOFF# from GPIO52 to GPIO63. Vertical L51 14 , 23 for layout routing

0 .2

0 .2 0 .2 0 .2 0 .2 0 .2

Add 150UF Caps for each DOCK_LOUT_R/L Correct U19 LAN Transfermor pin definition Change SB SATA port 4 to port 3

3

Del R1026 and Q167, add Net "DIM_LED#" for connect. Change location from PJP604 to PJP8. Change JREAD to TAITW_R015-B10-LM. 0 .2 Reserve R413,C902 close to JREAD.20; R412,C901 close to JREAD.26; R411,C900 close to JREAD.37. Change R457 close to U23.42 Add R455,R456 close to U23.42 Del Q169,R1051. Change net CR_LED# become CR_LED connect U23.21 and Q53.2 Add R454 pull down to GND Change R405,R122 from 200K to 10K pull-high Remove C895,U22

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

0 .2 0 .2

Change JP2 PCB Footprint from ACES_85204-02001_2P to ACES_88231-02001_2P Change JP20 PCB Footprint from ACES_85204-04001_4P to ACES_88231-04001_4P Change JP20 PCB Footprint from ACES_88018-124G_12P to ACES_88020-12101_12P Del R59,R60,R61,R115,R116,R117 and TV-OUT related design. Cancel NB_THERMAL_DA/DC connection between NB and SB,del C500 Change SB SATA port 5 to port 2

Compal Secret Data

Security Classification Issued Date

Change the CRT Conn. signals connection first. Wait correct symbol for fix Add R973(10K_0402) to +3VALW on HP_DET#

D

Title

4

Compal Electronics, Inc.

om

4 5

HW

0 .2

l.c

16

Update the LAN Design page and support circuit

ai

3

LAN CRT

1

tm

25

0 .2

HW Changed-List History-1

ho

3

10/29 10/29

2

Rev.

Size Document Number Custom LA-4111P Date:

Rev 0.2

f@

2

10/29

Solution Description Update the LAN Design page and support circuit

in

25

Request Issue Description Owner HW Change LAN Chip U20 from Marvell 88E8042 to Realtek RTL8102EL HPQ Add POE(Power Over Ethernet) design

Friday, November 30, 2007

Sheet E

xa

1 1

Date

Title LAN

45

he

Item Page#

of

48

A

B

C

D

E

Version Change List ( P. I. R. List ) for HW Circuit Item Page# 1

2

Date

Request Owner HW HW CIC HW HW

Normalize CRT design for common Normalize LCD design for common CIC feedback RMA concern for common Normalize KB926 Crystal part for common Change U54 WebCam power design and related

Change L83,L84 (10_0402) become R241,R240 (0_0603)

Issue Description

Rev.

19 20 21 22 23

16 17 18 33 17

Title CRT LCD LCD KBC WebCam

24 25

18 19,32

HDMI 11/09 SB-CLK-Debug 11/09

HW HW

Reduce HDMI Design Debug Card no function issue

Remove R490(100K_0402)

0 .2 0 .2

26 27 28 29 30 31

25 18 6 33 35 26

LAN HDMI CPU KBC Holes Mini-Card

11/09 11/09 11/09 11/09 11/09 11/09

HW HW HW HW ME HW

RJ45 LED Power correct back Reduce HDMI Design Add H_THERMTRIP# one more way Update KBC Pin Definition for common Update for M/E Drawing Reduce Mini-Card design, change SIM Card design

Change JRJ45.13, JRJ45.11 from +3V_LAN_LED to +3V_LAN

0 .2 0 .2 0 .2 0 .2 0 .2 0 .2

32 33

33 27

KBC CardReader

11/09 11/10

HW HW

Reserve 0_0603 for KB Back Light Correct CardReader LED part

34

34

LED Function

11/10

HW

Correct LED function for common

11/07 11/07 11/07 11/07 11/09

Solution Description Change R491 from 200_0402 to 200_0805 Change Q43 from AOS3413 to SI2301

Change Y7 from 9H03200413 small to 1TJS125DJ4A420P normal. Change U54 from G916-390T1UF to RT9193-39GB. Remove R891,R892 if no use G916-390T1UF. Add C718 close to U54.4 for RT9193-39GB. Remove R1027~R1030 for JP7 no install. Change JP7 from 8pin to 6pin

Del R1031,add R303 close to R301 and U15.P2 Connect for CLK_PCI_SIO2 to JP41.15

Remove R490(100K_0402) Add R16 close to Q3.1 for H_THERMTRIP# Add H_THERMTRIP# to U33.25 Del H49 H50 H38 H45 for M/E drawing change

Replace D17 and D47 become R52 and R53 Del R400 and R46, Change JP6 pin definition for common Add R516 (0_0603) between JP48.1/4 and +5VS_LED

0 .2 0 .2

HW

Change R15.2,R21.2,R36.2,R30.2 connection from +1.8V to +1.8VS; Remove R622, install R581

0 .2

11/13

HW

Reduce the level shift design for Chip A12.

0 .2

11/13 11/13

HW HW

Update the WebCam+Digital Mic reserver conn. Update THERMTRIP# design to EC

Del Q6,R87; Q5,R84 and replace by 0ohm (add R67,R68) connect directly. Install R371 (10K ohm)

11/13

HW

Remove EMI solution become reserve for verify

SB-GPIO KBC-GPIO

11/10 11/11

HW HW

37

6,31

CPU,FPR

11/13

38

11

NB

39 40

17 6,33

WebCam CPU,KBC

41

18

4

2007/08/02

Issued Date

Change JP7 from SP02000HC00(8pin)-->SP02000IL00(6pin)

C

4

Add R112,R113,R115~R120 close to each L85~L88 for co-lay

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B

0 .2 0 .2

Change R16.2 connection from THERMTRIP# to THERMTRIP#_EC for separate

Compal Secret Data

Security Classification

A

3

Add HDD_HALTLED# connect from U15.P8 Add R46 10K_0402 PH to +5VL close to U33 Add R514,R515 10K_0402 PH to +3VL close to U33

21 33

D

Title

2

0 .2

Add one more way for GSENSOR LED# inform pin Add CIR_IN PH to +5VL Add ESB_CLK/DAT PH to +3VL Reduce S3 power consumption

35 36

1

0 .2 0 .2

Change D5 from SC500004E00(AQUA_WHITE) to SC500004W00(WHITE) Change LED from D50,D30,D27 SC500004E00 (AQUA_WHITE) to D6,D7,D8 SC500004W00(WHITE) Change LED from D45,D46 SC500004B00 (AQUA_WHITE/AMBER) to D17,D18 SC500005M00 (YELLOW/WHITE); Add Q7,R20 and R42 close to D18

3

HDMI

0 .2 0 .2 0 .2 0 .2 0 .2

0 .2

Compal Electronics, Inc. HW Changed-List History-2

Size Document Number Custom LA-4111P Date:

Rev 0.2 Sheet

Friday, November 30, 2007 E

46

of

48

A

B

C

D

E

Version Change List ( P. I. R. List ) for HW Circuit

11/13

HW

BIOS Debug Tool reserve

44 45 46 47

25 13 18 20

LAN NB HDMI SB

11/13 11/13 11/13 11/13

HW HW HW HW

Update LAN Chip Symbol link to CIS server Add 0ohm_0603 to separate VDD18_MEM Reduce HDMI related design for common Reduce SB related design for common and A12 chip

48

SB,Cardreader

11/13

HW

49 50 51

20,21, 27 21,33 28,33 33

SB,KBC Codec,KBC KBC

11/13 11/13 11/13

HW HPQ HW

Reserve Cardreader D3E function (CR_WAKE# & CR_CPPE#) Reduce SB related design for common EC_BEEP function for KBC add Reduce S5 Power Consumption

52

33

KBC

11/13

HW

Reduce KBC Design for common and Ver:C0 Chip Change from SA00001J530 to SA00001J540

53

34

Switch Design

11/13

HW

Update CSD function board design for common

54

34

LED

11/14

HW

Audio-Dock Holes Multi-Bay

11/14 11/14 11/14

HPQ ME ME

58 59 60 61 62 63

33 20 33 35 33 28,29

Holes SB KBC DOCK K/B AUDIO

11/14 11/16 11/16 11/16 11/16 11/18

ME ATI EC EMC HW HPQ

Update Holes to meet M/E Drawing Reserve to fix the OTS325055 Issue Change design for EC team debug Connect DOCK guide pin to GND Fix KB matrix issue Make some Audio related design change

29

AUDIO

11/19

HPQ

B

0 .2 0 .2 0 .2

Del KSI6 and KSO9 out of page net connect Change C983,C984 from 1UF to 0.022UF. Change C1049,C1050,C1040,C1041 from 0.47UF to 0.022UF. Change R1002,R1005 from 20K to 0 ohm. Change C1044 from 10UF to 4.7UF. Remove R1000,R1004; Install R1001,R1003.

Change R968,R969 from 40.2_0402 to 47_0603 Compal Secret Data 2007/08/02

C

3

Add JDOCK.45/46 to GND

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

0 .2

Reserve R83 PH to +3VS Change JP34.1 from +5VALW to +5VL

Security Classification Issued Date

0 .2

Update JP2,JP9,JP10,JP11,JP20,JP40,JHDMI,JESAT,JCRT, JDOCK Symbol Add back H52 become H_1P5N; Del CF4

Make some Audio related design change

D

Title

2

0 .2 0 .2 0 .2 0 .2

Add back H52 become H_1P5N; Del CF4

4

64

Add R563 close to C955; Add R544 close to U33.31 Change R1040.1 connection from +3VL_EC to +3VALW Del R546 PH to +3VL_EC, Del D26 replace by add R547 close to U33 for short Del R537 become Test Point, change R516 become 150_0603 Remove R1044, change R1040 from 10K to 100K Change R528.2 , R529.2 connection from +5VALW to +5VL Install C814 (4.7U_0805) Change JP36.1 connection become +3VL;Change R1046.1 and R1047.1 connection become SMB_EC_CK1/DA1 Change JP36.7 connection from GND to +5VALW_LED by Change Q153 from 2N7002DW to 2N7002 Change R988.1 connection from +5VS_LED to +3VS Add R968,R969 close to C775/C776.

0 .2

0 .2 0 .2 0 .2 0 .2 0 .2 0 .2 4

0 .2

Compal Electronics, Inc.

tm

29 29 4,24

Add R81 close to U15;Q54,R124 close to U23 for connect U15.F8 to U23.13 ;Add R369 close to U23 for connect U15.M5 to U23.16 Del D51 and R1034, Change the net AC_IN become AC_IN_D

HW Changed-List History-2

ho

55 56 57

Correct T/P On/Off LED design define Correct G-Sensor LED design define For GS mark requirement Update Holes to meet M/E Drawing Update Symbol to meet M/E Drawing

3

0 .2 0 .2 0 .2 0 .2

Size Document Number Custom LA-4111P Date:

Rev 0.2

f@

2

0 .2

om

SB,BIOS

1

l.c

21,32

0 .2

ai

43

Del Q155,R986, and add R311 close to U15. Del R1011 become T18, Cancel R1012 and connect to H31 and JP41 directly Add SB_INT_FLASH_SEL and related (JP12,U30,R228,R226,C489 close to U29) Update LAN Chip U20 Symbol link to CIS server Add R1051(0_0603) between +1.8VS & +1.8V_VDD_SP Del R490 (100K_0402) Remove R994 (0_0402) Change U15.F1 connection become test point Remove R1053, change R1052 become 0_0402

in

1

Rev.

Solution Description

Friday, November 30, 2007

Sheet E

xa

11/13

Request Issue Description Owner HW Reduce SB related design for Chip A12 and others

Date

47

he

Title 4 2 19.32 SB,BIOS

Item Page#

of

48

A

B

C

D

E

Version Change List ( P. I. R. List ) for HW Circuit Item Page# 66 67 68

Title 13 NB 22 SB 22 SB 33,34 Function Board

69 70 71 72 73 74 75 76 77

23 31 34 33 6 19 26 28 10~13

65 1

2

3

Date

11/20 11/20 11/20 11/20

SB 11/20 BlueTooth 11/20 Power On Switch 11/22 KBC 11/22 CPU 11/22 SB 11/22 Express Card 11/22 Audio Codec 11/22 NB, 11/23 78 19 SB 11/23 79 22 SB 11/26 80 28 Codec 11/26 81 34 T/P 11/28 82 14 HDMI 11/28 83 15 CLK Gen. 11/28 84 28 Codec 11/28 8 5 20,27 SB,CardReader 11/28 86 32 BIOS 11/28 87 34 LED 11/28 88 19 SB 11/30 8 9 06,19, SB 11/30 23 90 33 KBC 11/30 91 32 BIOS 12/03 92 34 LED 12/03

Request Issue Description Owner ATI Design Change for NB A12 Version chip

Rev.

Solution Description Remove U64,C1064,C1065,C1066,C1067,R1015,R1016,Q163,R1017. Install L19, remove L95

0 .2 1

Install R593, remove R592 Remove R12,C543,C544,C547,C536

ATI HW HW

Design Change for SB A12 Version chip Reduce SB Power Design-No IDE support Reserve for Rachman UMA selective

HW HW HW HW HW HW HW HW HW

Make the SB Strap Seeting for common Update BT design for common Cancel one reserved power on switch Modify SMB_EC_DA1/CK1 PH for common Link PROCHOT# between CPU and NB Reserve LPCCLK1 for debug card function To avoid New Card Switch leakage issue Reserve SPDIF OUT1 test point for verify BOM correct for SI-1 SMT build

HW HW HW HW ATI HW HW HW HW HW HW ATI

Change Crystal Res. size for layout space Reduce SB SATA Power Caps (Confirm with ATI FAE) SPDIF0 --> 1 design change to follow Vader Change T/P Power for reduce S4/S5 power consumption Fix HDMI no function issue Change design for new version CLK Gen. Change EC_BEEP function become reserve Disconnect D3E support for A version to avoid risk Use Ext. BIOS as default Cancel WLAN/WWAN ext pull high Fix PA M/E Interfere issue for SI-1 ATI recommend for update

HW HW HW

Change 32.768KHz Main Source Vendor become EPSON Change Y7 from SJ100001V00 to SJ132P7K220 Cancel Ext. BIOS reflash design because of +3VL erroe Add R221; Remove U30,R226,R228,C489 Remove Q156 Cancel G-Sensor INT2 LED function

0 .2 0 .2 0 .2

Reserve R555 for +5VALW_LED, add R554 for +3VL close to JP36.1 Reserve R1034 close to JP36.4,R1035 close JP36.5,Remove R1036 Add R513 PH to +3VS close to U33.19

Install R356 (10K_0402) Change R520 from 47K_0402 to 10K_0402 Del SW3 Change R528,R529 pin 2 connection from +5VL to +3VL Add R59 close to Q2

0 .2 0 .2 0 .2 0 .2 0 .2 0 .2 0 .2 0 .2 0 .2

Add R308 22_0402 for U15.E22 close to R362.1, remove R301

Add R54(0_0402) close to U21.6 Add T21 close to U27.45 Update U3(SA00001ZG00-->SA00001ZG20);U10(SA00001Z300--> SA00001Z310);U15(SA00001S510-->SA00001S560)

Change R389 from 0603 to 0402 Change C567,C568 from 10U_0805 to 1U_0805 Change U27.48/45 pin connection Remove R235; Add Q85, R645, Q34 Remove R102; Add R101 Remove R1045 Remove R563 Remove R81,R369 Remove R221 Remove R1041

2

0 .2 0 .2 0 .2 0 .2 0 .2 0 .2 0 .2 0 .2 0 .2 0 .2 0 .2 0 .2

change Y3 from SJ100001U00 to SJ100006600 with 10PPM Change R312 from 0_0402 to 33_0402; Change R356 from 10K_0402 to 2.2K_0402; Install C23 as 0.1UF_0402

3

0 .2 0 .2 0 .2

4

4

Compal Secret Data

Security Classification 2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Compal Electronics, Inc. HW Changed-List History-2

Size Document Number Custom LA-4111P Date:

Rev 0.2 Sheet

Monday, December 03, 2007 E

48

of

48