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Essentials Oak 14 Schematic Chief River 2012-09-05 REV : A00

C

C

B

A

B

DY : None Installed UMA: UMA only installed OPS: DISCRTE OPTIMUS installed

M14 DIS

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

Cover Page Size A3

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Date: 2

Document Number

Rev

OAK14 Chief River DIS

W ednesday, September 05, 2012

Sheet 1

1

A00 of

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5

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CHARGER

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Project code: 91.4WT01.001 91.4XP01.001 PCB P/N : 12204 Revision: A00

BQ24727 INPUTS

Oak14 Block Diagram

40

OUTPUTS

AD+

DCBATOUT

BT+

SYSTEM DC/DC TPS51225 INPUTS OUTPUTS

41

3D3V_AUX_S5 5V_AUX_S5 DCBATOUT 5V_S5 3D3V_S5

D

Intel CPU Nvidia

VRAM(DDR3) *8 128Mx16bx4(1GB) 256Mx16bx4(2GB) 128Mx16bx8(2GB)

DDR3

PCIe x 8

DDR3 1333/1600MHz Channel B

BGA1023

DDR3 SUS TPS51216 INPUTS OUTPUTS

SODIMM B 15

4,5,6,7,8,9,10

only

VCC_CORE VCC_GFXCORE 26

DCBATOUT

DDR3 1333/1600

83,84,85,86,87

Switchable Graphic

42~44 ISL95833 33 INPUTS OUTPUTS

14

17W (DC)

25W

CPU Core/NB Power

SODIMM A

Ivy Bridge

N13P - GS - OP N13M- GSR

88,89,90,91

DDR3 1333/1600

DDR3 1333/1600MHz Channel A

D

46

DCBATOUT 1D5V_S3

DDR3 VTT FDIx4x2

TPS51216 INPUTS OUTPUTS

DMIx4

46

DCBATOUT 0D75V_S0

CPU VCCP_CPU

HDMI V1.4a

C

PCIE x 1

51

Intel PCH 14.0" LCD (16:9)

LVDS (2channel)

58

B

12 USB 2.0/1.1 ports 4 USB 3.0 ports High Definition Audio 6 SATA ports 8 PCIE ports LPC I/F ACPI 4.0a

HDA CODEC

MIC_IN/GND

SYW231 INPUTS

OUTPUTS

3D3V_S5

1D8V_S0

47

Intel CPU_VCCSA TPS51463 INPUTS OUTPUTS

65

5V_S5

USB3.0 x 2

LPC BUS

0D85V_S0

ADP3211MNR2G INPUTS OUTPUTS

USB3.0 Port x 2 61,62,63

Switches

USB Board

INPUTS

USB2.0 Port x 1

CardReader Realtek RTS5170

SD/SDHC/MS/MS Pro Slot

SPI

NPCE885P

36 93

OUTPUTS

1D5V_S3

1D5V_S0

5V_S5

5V_S0

3D3V_S5

3D3V_S0

B

1D05V_VGA_S0

3D3V_S0

3D3V_VGA_S0

1D5V_S3

1D5V_VGA_S0

PCB LAYER

74

32

L1:Top L4:Signal L2:VCC L5:GND L3:Signal L6:Bottom

17,18,19,20,21,22,23,24,25

NUVOTON

92

DCBATOUT VGA_CORE

USB2.0 x 2

USB2.0 x 1

48

Nvidia VGA_CORE

Left side

KBC

Fan Control

A

Mini-Card 802.11 b/g/n BT V4.0 combo

C

Intel PCH 1D8V_S0

VCCP_CPU

SMBUS

NUVOTON NCT7718W 28

FAN 28

USB2.0 x 1

USB2.0 x 1

71

NUVOTON NCT3940S-A

59

Right side

LPC debug port

Thermal

PCIE x 1

45

DCBATOUT 1D05V_S0

29

2CH SPEAKER (2CH 2W/4ohm)

58

31

HDA

Realtek ALC3221

HP_R/L

Combo Jack

HM76

USB2.0 x 1 49

RJ45 Conn.

Realtek RTL8105E-VD

Panther Point

49

BGA989 Camera Digital MIC

TPS51219 INPUTS OUTPUTS

10/100 NIC

HDMI

SATA(Gen3) x 1

HDD 56

27

28

Int. KB

Flash ROM

PS2

8MB

SATA(Gen1) x 1

60

ODD

69

56

Touch PAD Profile/Image sensor

A

SMBUS M14 DIS

69

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

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Block Diagram Document Number

OAK14 Chief River DIS

Wednesday, September 05, 2012

Sheet 1

2

of

Rev

A00 105

A

B

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PCH Strapping

INIT3_3V#

4 INTVRMEN

DF_TVS

SATA1GP/ GPIO19

3

The signal has a weak internal pull-down. Note: the internal pull-down is disabled after PLTRST# deasserts. If the signal is sampled high, this indicates that the system is strapped to the “No Reboot” mode (Panther Point will disable the TCO Timer system reboot feature). This signal has a weak internal pull-up. Note: The internal pull-up is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled low. Leave as "No Connect".

Pin Name

CFG[2]

GNT[3:0]# functionality is not available on Mobile. Used as GPIO only. Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail. This signal is a strap for selecting DMI and FDI termination voltage. For Ivy Bridge processor only implementation: DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms ±5% resistor. For future processor compatibility: It needs to be connected to PROC_SELECT through a 1.0 kOhms ±5% series resistor. The PROC_SELECT signal would need a 2.2 kOhms ±5% pull-up resistor to PCH VccDFTERM. Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved 1 0 PCI 1 1 SPI 0 0 LPC NOTE: If option 00 LPC is selected BIOS may still be placed on LPC, but all platforms with Panther Point require SPI flash connected directly to the Panther Point's SPI bus with a valid descriptor in order to boot. NOTE: Booting to PCI is intended for debut/testing only. Boot BIOS Destination Select to LPC/PCI by functional strap or via Boot BIOS Destination Bit will not affect SPI accesses initiated by Management Engine or Integrated GbE LAN. NOTE: PCI Boot BIOS destination is not supported on mobile. Reserved. This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled.

SATA3GP/ GPIO37

Reserved This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled.

Strap Description

CFG[0]

Integrated 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when high NOTE: This signal should always be pulled high External 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when Low. NOTE: This signal should be pulled down to GND through 330 kOhms resistor

SATA2GP/ GPIO36

CFG[6:5]

Chief River Schematic Checklist Revision 1.5 Configuration (Default value for each bit is 1 unless specified otherwise)

HDA_SDO

HDA_SYNC

2 GPIO15

L_DDC_DATA

SDVO_CTRLDATA

PCIe Static x16 Lane Numbering Reversal.

Display Port Presence strap

PCIE Port Bifurcation Straps

1: Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed 1:Disabled - No Physical Display Port attached to Embedded DisplayPort No connect for disable 0:Enabled - An external Display Port device is connected to the Embedded Display Port Pull-down to GND through a 1KΩ ± 5% resistor to enable port 00 01 10 11

= = = =

1 x 8, 2 x 4 PCI Express reserved 2 x 8 PCI Express 1 x 16 PCI Express

1 GPIO28

GPIO29/ SLP_LAN#

5V 3.3V 1.8V 1.5V 1.05V 0.95 - 0.85V 0.75V 0.35V to 1.5V 0.4 to 1.25V 1.8V 3.3V 1V

DESCRIPTION

5V_USBX_S3 1D5V_S3 DDR_VREF_S3

5V 1.5V 0.75V

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5

6V-14.1V 6V-14.1V 5V 5V 3.3V 3.3V

3D3V_LAN_S5

3.3V

WOL_EN

Legacy WOL

3D3V_AUX_KBC

3.3V

DSW, Sx

ON for supporting Deep Sleep states

3D3V_AUX_S5

3.3V

G3, Sx

Powered by Li Coin Cell in G3 and +V3ALW in Sx

ACTIVE IN

Schematic Notes

DDR3 VREF

CPU Core Rail Graphics Core Rail

S3

AC Brick Mode only All S states

PCIE Routing

Sandy Bridge + Ivy Bridge PROC_SELECT# & DF_TVS

DDR3 VREF M1 and M3 Guidelines are required. Note: The M3 traces are routed to the Sandy Bridge Processor reserved pins.

Connect DF_TVS signal of the PCH to PROC_SELECT# of the processor through a 1K±5% series resistor. PROC_SELECT# also needs a 2.2K±5% pull up resistor to PCH VccDFTERM rail. No change.

Ivy Bridge

Sandy Bridge + Ivy Bridge VCCIO VR Implementation Ivy Bridge

USB Table

B

Device

LANE2

X X

2

USB2.0 port3

LANE3

Mini Card1(WLAN)

3

X

LANE4

x

4

X

5

Touch Panel

LANE5

6

HM76 NC

LANE6

X Onboard LAN

7

HM76 NC

8

X

LANE7

X

9

LANE8

X

10

CARD READER

11 12

Mini Card (WLAN) X

13

CAMERA

The POR for Ivy Bridge mobile parts is now 1.05 V. There is no longer a requirement for a separate VCCIO VR for Sandy Bridge + Ivy Bridge compatibility.

0

USB3.0 port1

1

USB3.0 port2, with Debug Port

X

No change.

Sandy Bridge + Ivy Bridge VCCSA_SEL connection to VCCSA_VID[1:0] lines

LANE1

No change.

Ivy Bridge

2

SATA Table

VCCSA_SELECT[0:1] which should be connected to VID[1:0] of the System Agent (SA) VR controller.

SATA Ivy Bridge

No change.

Sandy Bridge + Ivy Bridge Layout Requirement on PCI Express Gen3 Ivy Bridge

GT Core VR Implementation

Sandy Bridge + Ivy Bridge

Processor PCI Express Graphics Guidelines

Sandy Bridge + Ivy Bridge (PCIe Gen3):

Ivy Bridge

GPIO29 is multiplexed with SLP_LAN#. If Intel LAN is implemented on the platform, SLP_LAN# must be used to control the power to the PHY LAN (no other implementation is supported). If integrated Intel LAN is not supported on the platform, GPIO29 can be used as a normal GPIO. A soft strap determines the functionality of GPIO29, either as SLP_LAN# or GPIO. By default, the soft strap enables SLP_LAN# functionality on the pin. If the soft trap is changed to enable GPIO functionality, then SLP_LAN# functionality is no longer available, and the signal can be used as a normal GPIO (default to GPI).

4

S0

Pair Configuration

Pair

The total motherboard length for a pair of consecutive PCI Express Tx lanes be length matched within 100 mils (2.54 mm) No change.

Depending on the PDDG specifications, some IVB GT2 SKUs may require a new VR controller and 2 phase VCC GT core VR.

Device

0

HDD1

1

X

2

X

3

X

4

ODD1

5

X

No change.

Ivy Bridge

To support Gen 3 PCI Express Graphic, the value of the AC coupling capacitor should be 180 - 265 nF. No change.

The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is disabled.If not used, 8.2-kΩ to 10-kΩ pull-up to +V3.3A power-rail. GPIO28 signal also needs to be pulled up to 3.3V_SUS with 4.7K resistor to ensure proper strap setting when use as the chipset test interface.Refer to the latest platform debug design guide and platform design guide for more details. NOTE:This signal has a weak internal pull-up. The internal pull-up is disabled after RSMRST# deasserts.

A

VOLTAGE

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0

1

Chief River Schematic Checklist Revision 1.5

Port B Detected When '1'- Port B is detected; When '0'- Port B is not detected This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

DDPD_CTRLDATA

Voltage Rails POWER PLANE

3

Pin Name

LVDS Detected. When '1'- LVDS is detected; When '0'- LVDS is not detected. This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

Port D Detected. When '1'- Port D is detected; When '0'- Port D is not detected This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

1

Sandy Bridge + Ivy Bridge Compatibility Requirements

Signal has a weak internal pull-down. If strap is sampled low, the security measures defined in the Flash Descriptor will be in effect (default).If sampled high, the Flash Descriptor Security will be overridden. This strap should only be asserted high via external pull-up in manufacturing/debug environments ONLY. Note: The weak internal pull-down is disabled after PLTRST# deasserts. Asserting the HDA_SDO high on the rising edge of PWROK will also halt Intel Management Engine after chipset bring up and disable runtime Intel Management Engine features. This is a debug mode and must not be asserted after manufacturing/ debug.This signal has a 20k internal pull down resistor. This signal has a weak internal pull-down. On Die PLL VR is supplied by 1.5 V from VCCVRM when sampled high, 1.8 V from VCCVRM when sampled low. Needs to be pulled High for Chief River platform. Note: HDA_SYNC signal also serves as a strap for selecting VRM voltage to the PCH. The strap is sampled on the rising edge of RSMRST# signal. Due to potential leakage on the codec (path to GND), the strap may not be able to achieve the Vihmin at PCH input.Therefore, platform may need to isolate this signal from the codec during the strap phase. Refer to the example circuits provided in the latest Chief River platform design guide. TLS Confidentiality Low (0) – Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality This signal has a weak internal pull-down. NOTE:The weak internal pull-down is disabled after RSMRST# deasserts. NOTE: A strong pull-up may be needed for GPIO functionality

Port C Detected. When '1'- Port C is detected; When '0'- Port C is not detected This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

1

Reserved configuration CFG[17:7] lands. A test point may be placed on the board for these lands.

High Definition Audio Dock Enable: This signal controls the external Intel HD Audio docking isolation logic. This is an active-low-signal. When deasserted the external docking switch is in isolate mode. When asserted the external docking switch electrically connects the IntelR HD Audio dock signals to the corresponding Panther Point signals. This signal can instead be used as GPIO33.

DDPC_CTRLDATA

Default Value

Connect a series 1 kOhms resistor on the critical CFG[0] trace in a manner which does not introduce any stubs to CFG[0] trace. Route as needed from the opposite side of this series isolation resistor to the debug port. ITP will drive the net to GND.

Sandy Bridge + Ivy Bridge HDA_DOCK_EN# /GPIO33

E Power Plane

Processor Strapping

Schematics Notes

CFG[4] GNT3#/GPIO55 GNT2#/GPIO53 GNT1#/GPIO51

D

Chief River Schematic Checklist Revision 1.5

Name

SPKR

C

1 M14 DIS

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2

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Date:

D

Table of Content OAK14 Chief River DIS

Document Number

Wednesday, September 05, 2012

E

Sheet

3

Rev

A00 of

105

5

4

SSID = CPU

3

2

1

WWW.AliSaler.Com Layout Note: Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

D

D VCCP_CPU 1 OF 9

CPU1A

Layout Note:

19 DMI_CPU_RXP_PCH_TXP[3:0]

19 DMI_CPU_TXN_PCH_RXN[3:0]

19 DMI_CPU_TXP_PCH_RXP[3:0]

19 FDI_CPU_TXN_PCH_RXN[7:0]

C Layout Note:

FDI trace length 2000~6500mil

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_CPU_RXP_PCH_TXP0 DMI_CPU_RXP_PCH_TXP1 DMI_CPU_RXP_PCH_TXP2 DMI_CPU_RXP_PCH_TXP3

N3 P7 P3 P11

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_CPU_TXN_PCH_RXN0 DMI_CPU_TXN_PCH_RXN1 DMI_CPU_TXN_PCH_RXN2 DMI_CPU_TXN_PCH_RXN3

K1 M8 N4 R2

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_CPU_TXP_PCH_RXP0 DMI_CPU_TXP_PCH_RXP1 DMI_CPU_TXP_PCH_RXP2 DMI_CPU_TXP_PCH_RXP3

K3 M7 P4 T3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI_CPU_TXN_PCH_RXN0 FDI_CPU_TXN_PCH_RXN1 FDI_CPU_TXN_PCH_RXN2 FDI_CPU_TXN_PCH_RXN3 FDI_CPU_TXN_PCH_RXN4 FDI_CPU_TXN_PCH_RXN5 FDI_CPU_TXN_PCH_RXN6 FDI_CPU_TXN_PCH_RXN7

U7 W11 W1 AA6 W6 V4 Y2 AC9

FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3

FDI_CPU_TXP_PCH_RXP0 FDI_CPU_TXP_PCH_RXP1 FDI_CPU_TXP_PCH_RXP2 FDI_CPU_TXP_PCH_RXP3 FDI_CPU_TXP_PCH_RXP4 FDI_CPU_TXP_PCH_RXP5 FDI_CPU_TXP_PCH_RXP6 FDI_CPU_TXP_PCH_RXP7

U6 W10 W3 AA7 W7 T4 AA3 AC8

FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3

FDI_FSYNC0 AA11 FDI_FSYNC1 AC12

19 FDI_FSYNC0 19 FDI_FSYNC1

FDI_INT

19 FDI_INT

FDI_LSYNC0 AA10 FDI_LSYNC1 AG8

19 FDI_LSYNC0 19 FDI_LSYNC1

B

VCCP_CPU

R402 1

U11

2 24D9R2F-L-GP

DP_COMP

Layout Note:

FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC

EDP_COMPIO EDP_ICOMPO EDP_HPD#

AG4 AF4

EDP_AUX# EDP_AUX

AC3 AC4 AE11 AE7

EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3

AC1 AA4 AE10 AE6

EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3

eDP

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

AF3 AD2 AG11

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

Intel(R) FDI

19 FDI_CPU_TXP_PCH_RXP[7:0]

M2 P6 P1 P10

DMI

DMI trace length 2000~8000mil

DMI_CPU_RXN_PCH_TXN0 DMI_CPU_RXN_PCH_TXN1 DMI_CPU_RXN_PCH_TXN2 DMI_CPU_RXN_PCH_TXN3

IVY-BRIDGE-GP-NF

71.00IVY.A0U

PCI EXPRESS -- GRAPHICS

19 DMI_CPU_RXN_PCH_TXN[3:0]

G3 G1 G4

PEG_IRCOMP_R

R401

2 24D9R2F-L-GP

1

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

CPU_RXP_C_dGPU_TXP7 CPU_RXP_C_dGPU_TXP6 CPU_RXP_C_dGPU_TXP5 CPU_RXP_C_dGPU_TXP4 CPU_RXP_C_dGPU_TXP3 CPU_RXP_C_dGPU_TXP2 CPU_RXP_C_dGPU_TXP1 CPU_RXP_C_dGPU_TXP0

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

CPU_TXN_dGPU_RXN7 CPU_TXN_dGPU_RXN6 CPU_TXN_dGPU_RXN5 CPU_TXN_dGPU_RXN4 CPU_TXN_dGPU_RXN3 CPU_TXN_dGPU_RXN2 CPU_TXN_dGPU_RXN1 CPU_TXN_dGPU_RXN0

1OPS 1OPS 1OPS 1OPS 1OPS 1OPS 1OPS 1OPS

2 2 2 2 2 2 2 2

C401 C402 C403 C404 C405 C406 C407 C408

SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP

dGPU_RXN_C_CPU_TXN8 dGPU_RXN_C_CPU_TXN9 dGPU_RXN_C_CPU_TXN10 dGPU_RXN_C_CPU_TXN11 dGPU_RXN_C_CPU_TXN12 dGPU_RXN_C_CPU_TXN13 dGPU_RXN_C_CPU_TXN14 dGPU_RXN_C_CPU_TXN15

PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

CPU_TXP_dGPU_RXP7 CPU_TXP_dGPU_RXP6 CPU_TXP_dGPU_RXP5 CPU_TXP_dGPU_RXP4 CPU_TXP_dGPU_RXP3 CPU_TXP_dGPU_RXP2 CPU_TXP_dGPU_RXP1 CPU_TXP_dGPU_RXP0

1OPS 1OPS 1OPS 1OPS 1OPS 1OPS 1OPS 1OPS

2 2 2 2 2 2 2 2

C409 C410 C411 C412 C413 C414 C415 C416

SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP

dGPU_RXP_C_CPU_TXP8 dGPU_RXP_C_CPU_TXP9 dGPU_RXP_C_CPU_TXP10 dGPU_RXP_C_CPU_TXP11 dGPU_RXP_C_CPU_TXP12 dGPU_RXP_C_CPU_TXP13 dGPU_RXP_C_CPU_TXP14 dGPU_RXP_C_CPU_TXP15

CPU_RXN_C_dGPU_TXN7 CPU_RXN_C_dGPU_TXN6 CPU_RXN_C_dGPU_TXN5 CPU_RXN_C_dGPU_TXN4 CPU_RXN_C_dGPU_TXN3 CPU_RXN_C_dGPU_TXN2 CPU_RXN_C_dGPU_TXN1 CPU_RXN_C_dGPU_TXN0

CPU_RXN_C_dGPU_TXN[7..0]

83

CPU_RXP_C_dGPU_TXP[7..0]

83

C dGPU_RXN_C_CPU_TXN[8..15]

83

dGPU_RXP_C_CPU_TXP[8..15]

83

B

Note: PEG with reversal type.

A

A

M14 DIS

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

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Size A3 Date:

CPU(PCIE/DMI/FDI) Document Number

Rev

A00

OAK14 Chief River DIS W ednesday, September 05, 2012

Sheet

4

of

105

5

4

SSID = CPU

3

2

1

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D

2 OF

TPAD14-OP-GP

TP501

F49

SKTOCC#_R

1

C57

PROC_SELECT# PROC_DETECT#

VCCP_CPU TPAD14-OP-GP

TP502

1

2

C49

CATERR#

H_PECI

A48

PECI

H_PROCHOT#_R

C45

PROCHOT#

H_THERMTRIP#

D45

THERMTRIP#

H_PROCHOT#

62R2J-GP

22,27

H_PECI R513

1

27,38,40,42 H_PROCHOT#

2

56R2J-4-GP 22 H_THERMTRIP#

THERMAL

H_CATERR#

R501

1

Layout Note: R501, R513 place near to CPU

H_PM_SYNC

H_PM_SYNC R504 0R0402-PAD 1 2

22 H_CPUPW RGD

C48

H_CPUPW RGD_R

B46

PM_SYNC

UNCOREPWRGOOD

1 R503 2 10KR2J-3-GP VDDPW RGOOD

37 VDDPW RGOOD

BUF_CPU_RST#

2

R510 1K5R2F-2-GP

D44

RESET#

1

1

C501 SC220P50V2KX-3GP

DY

BCLK BCLK#

J3 H2

CLK_EXP_P CLK_EXP_N

AG3 AG1

CLK_DP_P_R1 CLK_DP_N_R2

CLK_EXP_P 20 CLK_EXP_N 20 RN503

DPLL_REF_CLK DPLL_REF_CLK#

4 3

VCCP_CPU

SRN1KJ-7-GP

Layout Note: Checking the connector pin's LAYOUT

SM_DRAMRST#

AT30

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

BF44 BE43 BG43

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

PRDY# PREQ#

N53 N55

XDP_PRDY# XDP_PREQ#

TCK TMS TRST#

L56 L55 J58

XDP_TCLK XDP_TMS XDP_TRST#

TDI TDO

M60 L59

XDP_TDI XDP_TDO

SM_DRAMRST# 37 R506 1 R508 1 R511 1

2 140R2F-GP 2 25D5R2F-GP 2 200R2F-L-GP

Layout Note: XDP_PRDY# 71 XDP_PREQ# 71

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils. Trace width = 15mil

RN501 XDP_TDI XDP_TMS XDP_TDO

DBR#

K58

XDP_DBRESET#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

G58 E55 E59 G55 G59 H60 J59 J61

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

C VCCP_CPU

XDP_DBRESET# 19

1 2 3 4

8 7 6 5

XDP

SRN51J-1-GP XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

71 71 71 71 71 71 71 71

RN502 XDP_TRST# XDP_TCLK

1 2

4 3

XDP

SRN51J-GP

2

R509 698R2F-GP

2

PLT_RST#

SM_DRAMPWROK

1

18,27,31,65,71,83

BE45

PWR MANAGEMENT

19

JTAG & BPM

C

D

9

R507 4K99R2F-L-GP 1 2

DDR3 MISC

H_SNB_IVB#

H_SNB_IVB#

MISC

22

CLOCKS

CPU1B

IVY-BRIDGE-GP-NF

71.00IVY.A0U

B

B

Layout Note: C501 place near to CPU

XDP_DBRESET#

1

1

DY

EC502 SCD1U10V2KX-5GP

EC503 SCD1U10V2KX-5GP

DY

2

2

DY

PLT_RST#

2

1

H_CPUPW RGD EC501 SCD1U10V2KX-5GP

reserve for EMI Request

A

A

M14 DIS

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

WWW.AliSaler.Com

Size A3 Date:

CPU(THERMAL/CLOCK/PM) Document Number

Rev

A00

OAK14 Chief River DIS W ednesday, September 05, 2012

Sheet

5

of

105

5

4

3

2

1

SSID = CPU WWW.AliSaler.Com 4 OF 9

CPU1D 3 OF 9 15 M_B_DQ[63:0]

M_A_DQ[63:0]

14 M_A_DQ[63:0]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

C

B

AG6 AJ6 AP11 AL6 AJ10 AJ8 AL8 AL7 AR11 AP6 AU6 AV9 AR6 AP8 AT13 AU13 BC7 BB7 BA13 BB11 BA7 BA9 BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

14 14 14

M_A_BS0 M_A_BS1 M_A_BS2

BD37 BF36 BA28

SA_BS0 SA_BS1 SA_BS2

14 14 14

M_A_CAS# M_A_RAS# M_A_W E#

BE39 BD39 AT41

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

D

M_B_DQ[63:0]

SA_CK0 SA_CK#0 SA_CKE0

AU36 AV36 AY26

M_A_DIMA_CLK_DDR0 14 M_A_DIMA_CLK_DDR#0 14 M_A_DIMA_CKE0 14

SA_CK1 SA_CK#1 SA_CKE1

AT40 AU40 BB26

M_A_DIMA_CLK_DDR1 14 M_A_DIMA_CLK_DDR#1 14 M_A_DIMA_CKE1 14

SA_CS#0 SA_CS#1

BB40 BC41

M_A_DIMA_CS#0 14 M_A_DIMA_CS#1 14

SA_ODT0 SA_ODT1

AY40 BA41

M_A_DIMA_ODT0 14 M_A_DIMA_ODT1 14

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_A_DQS#[7:0] 14

M_A_DQS[7:0] 14

M_A_A[15:0] 14

AL4 AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9 BD13 BF12 BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59 AM60 AL59 AF61 AH60

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

15 15 15

M_B_BS0 M_B_BS1 M_B_BS2

BG39 BD42 AT22

SB_BS0 SB_BS1 SB_BS2

15 15 15

M_B_CAS# M_B_RAS# M_B_W E#

AV43 BF40 BD45

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

CPU1C

SB_CK0 SB_CK#0 SB_CKE0

BA34 AY34 AR22

M_B_DIMB_CLK_DDR0 15 M_B_DIMB_CLK_DDR#0 15 M_B_DIMB_CKE0 15

SB_CK1 SB_CK#1 SB_CKE1

BA36 BB36 BF27

M_B_DIMB_CLK_DDR1 15 M_B_DIMB_CLK_DDR#1 15 M_B_DIMB_CKE1 15

SB_CS#0 SB_CS#1

BE41 BE47

M_B_DIMB_CS#0 15 M_B_DIMB_CS#1 15

SB_ODT0 SB_ODT1

AT43 BG47

M_B_DIMB_ODT0 15 M_B_DIMB_ODT1 15

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

D

C

M_B_DQS#[7:0] 15

M_B_DQS[7:0] 15

B

M_B_A[15:0] 15

IVY-BRIDGE-GP-NF IVY-BRIDGE-GP-NF

71.00IVY.A0U

71.00IVY.A0U

M14 DIS

A

A

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

CPU (DDR) Size A3

5

4

WWW.AliSaler.Com 3

Date: 2

Document Number

Rev

OAK14 Chief River DIS W ednesday, September 05, 2012

Sheet 1

6

of

A00 105

5

4

3

2

1

SSID = CPU WWW.AliSaler.Com

C

TP719

1VCC_DIE_SENSE

H43 K43

VCC_VAL_SENSE VSS_VAL_SENSE

H45 K45

VAXG_VAL_SENSE VSSAXG_VAL_SENSE

F48 G48

VCC_DIE_SENSE RSVD47

H48 K48

RSVD6 RSVD7

BA19 AV19 AT21 BB21 BB19 AY21 BA22 AY22 AU19 AU21 BD21 BD22 BD25 BD26 BG22 BE22 BG26 BE26 BF23 BE24

B

1 BCLK_ITP BCLK_ITP#

BCLK_ITP BCLK_ITP#

N59 N58

RSVD30 RSVD31 RSVD32 RSVD33

N42 L42 L45 L47

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

M13 M14 U14 W14 P13

RSVD39 RSVD40

AT49 K24

RSVD41 RSVD42 RSVD43 RSVD44

AH2 AG13 AM14 AM15

RSVD45

N50

1 1

OPS

TP721 TP722

CFG[2]

2

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

1: Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed

Display Port Presence Strap 1: Disabled; No Physical Display Port attached to Embedded Display Port

CFG[4]

0: Enabled; An external Display Port device is connected to the Embedded Display Port

CFG5

C

CFG6

PCIE Port Bifurcation Straps 1

1 1

B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53

D

PEG Static Lane Reversal R702 1KR2J-1-GP

R701

R704

CFG[6:5]

DY 1KR2J-1-GP OPS 1KR2J-1-GP DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58 DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1

RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27

A4 C4 DC_TEST_C4_D3 D3 D1 A58 A59 TP_DC_TEST_A59_C59 C59 A61 TP_DC_TEST_A61_C61 C61 D61 BD61 BE61 BE59 TP_DC_TEST_BE59_BE61 BG61 BG59 DC_TEST_BG59_BG61 BG58 BG4 BG3 DC_TEST_BE3_BG3 BE3 BG1 DC_TEST_BE1_BG1 BE1 BD1

11: 1x16 PCI Express 10: 2 x8 - PCI Express

2

TP702 TP703

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6

1

1

2

CFG0 TP701

RESERVED

71

CFG2

5 OF 9

CPU1E

D

01: Reserved 00: 1x8, 2x4 PCI Express

B

IVY-BRIDGE-GP-NF

71.00IVY.A0U

M14 DIS A

A

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

CPU (RESERVED) Size A3

5

4

WWW.AliSaler.Com 3

Date: 2

Document Number

Rev

OAK14 Chief River DIS W ednesday, September 05, 2012

Sheet 1

7

of

A00 105

5

4

3

2

1

SSID = CPU

WWW.AliSaler.Com VCC_CORE

CPU1F

POWER

6 OF 9

1 2

1 2

1

1 2

2

1

1 2

2

1

1 2

2

1 2 1 2

1

1

1 2

2

2

1 2

1

1 2

2

1 2

1 1

2

1

1 2

2

2

PEG IO AND DDR IO

1 2

1

1 2

2 1 2

1

1

1 2

2

2

1 2

1

1 2

2

1 2

1 1

2

1

1 2

2

2

SC10U6D3V3MX-GP C885

C

W16 W17

BC22

H_SNB_IVB#_PWRCTRL

1

TP801

VCCPQ Output Decoupling CAP Recommendation: 1 x 1 uF (0402)

+V1.05S_VCCPQE_R AM25 AN22

SVID

VIDALERT# VIDSCLK VIDSOUT

A44 B43 C44

R812 0R0402-PAD 2 1

VCCP_CPU

VCCP_CPU

Layout Note:

C802 SC1U6D3V2KX-GP

R803, R804, R805 need close to CPU Alert# signal must be routed between the Clock and Data lines to reduce the cross talk between them

2

R804 130R2F-1-GP 2

R805 75R2F-2-GP R803 43R2J-GP 1 2

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

1

1

1

VCCPQE1 VCCPQE2

2

QUIET RAILS

1 2

1 2

1 2

1 2

1 2 1 2

1 2 1 2

1 2 1 2

1 2 1 2

1 2 1 2 1 2

SC1U6D3V2KX-GP C886

SC1U6D3V2KX-GP C883

SC1U6D3V2KX-GP C882

SC10U6D3V3MX-GP C889

DY

SC1U6D3V2KX-GP C881

DY

SC10U6D3V3MX-GP C893

SC10U6D3V3MX-GP C897

DY

DY

SC1U6D3V2KX-GP C847

DY

SC1U6D3V2KX-GP C848

DY

SC1U6D3V2KX-GP C846

VCCIO_SEL

DY

SC10U6D3V3MX-GP C895

VCCIO50 VCCIO51

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

SC1U6D3V2KX-GP C890

CORE SUPPLY

1 2

1

1 2

2

1 2

1 2

1 2

1 2

1 2

1 2

2 1 2 1 2

SC4D7U6D3V3KX-GP C884

SC10U6D3V3MX-GP C888

VCCP_CPU

VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 VCCIO40 VCCIO41 VCCIO42 VCCIO43 VCCIO44 VCCIO45 VCCIO46 VCCIO47 VCCIO48 VCCIO49

SC1U6D3V2KX-GP C891

1

DY

SC1U6D3V2KX-GP C842

SC1U6D3V2KX-GP C841

SC10U6D3V3MX-GP C892

SC10U6D3V3MX-GP C896

DY

SC1U6D3V2KX-GP C839

DY

SC1U6D3V2KX-GP C840

SC1U6D3V2KX-GP C837

DY

SC4D7U6D3V3KX-GP C894

2

SC1U6D3V2KX-GP C838

SC1U6D3V2KX-GP C836

SC1U6D3V2KX-GP C834

SC1U6D3V2KX-GP C835

SC1U6D3V2KX-GP C833

SC1U6D3V2KX-GP C844

DY

SC1U6D3V2KX-GP C887

C

DY

8.5A

D

SC1U6D3V2KX-GP C845

SC2D2U6D3V2MX-GP C823

SC2D2U6D3V2MX-GP C822

SC2D2U6D3V2MX-GP C821

SC2D2U6D3V2MX-GP C820

SC2D2U6D3V2MX-GP C829

SC2D2U6D3V2MX-GP C828

SC2D2U6D3V2MX-GP C827

SC2D2U6D3V2MX-GP C826

SC2D2U6D3V2MX-GP C825

SC2D2U6D3V2MX-GP C824

DY

SC2D2U6D3V2MX-GP C818

SC2D2U6D3V2MX-GP C819

SC2D2U6D3V2MX-GP C817

SC2D2U6D3V2MX-GP C816

SC2D2U6D3V2MX-GP C815

SC2D2U6D3V2MX-GP C814

DY

SC1U6D3V2KX-GP C832

SC10U6D3V3MX-GP C813

SC10U6D3V3MX-GP C812

DY

DY

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76

SC1U6D3V2KX-GP C843

A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

SC1U6D3V2KX-GP C831

ULV 33A

D

DY

VCCIO1 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29

SC1U6D3V2KX-GP C830

SC10U6D3V3MX-GP C811

SC10U6D3V3MX-GP C810

SC10U6D3V3MX-GP C809

SC10U6D3V3MX-GP C808

SC22U6D3V5MX-2GP C807

SC22U6D3V5MX-2GP C806

SC22U6D3V5MX-2GP C805

SC22U6D3V5MX-2GP C804

SC22U6D3V5MX-2GP C803

SC22U6D3V5MX-2GP C801

1

VCCP_CPU VCC_CORE

VR_SVID_ALERT# 42 H_CPU_SVIDCLK 42 H_CPU_SVIDDAT 42

Need place Pull Hi at IMVP page

VCC_CORE

2

VCCSENSE VSSSENSE

VCCSENSE 43 VSSSENSE 43 VCCP_CPU

R802 100R2F-L1-GP-U

1 AN16 AN17

R807 10R2F-L-GP VCCIO_SENSE 45 VSSIO_SENSE 45

1

IVY-BRIDGE-GP-NF

71.00IVY.A0U

R806 10R2F-L-GP 2

Voltage Rail

A

Voltage(V)

VCC_CORE

0.3~1.52

VAXG

0~1.52

VCCIO

1.05

VDDQ

1.5

VCCSA

0.675~0.9

VCCPLL

1.8

2

VCCIO_SENSE VSS_SENSE_VCCIO

1. PH/PL resisors place close CPU 2. SENSE signal recommend differential routing

1

F43 G43

2

SENSE LINES

R801 100R2F-L1-GP-U

VCC_SENSE VSS_SENSE

B

Layout Note:

1

B

Layout Note: 1. PH/PL resisors place close CPU 2. SENSE signal recommend differential routing

Iccmax(A) 33 29 (GT2) 8.5 5 4 1.2 A

Refer to CPU EDS V.1.7.5 M14 DIS

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

CPU (VCC_CORE) Size A2 5

4

WWW.AliSaler.Com 3

Date: 2

Document Number

Rev

OAK14 Chief River DIS Wednesday, September 05, 2012 1

Sheet

8

of

A00 105

5

4

3

2

1

SSID = CPU

WWW.AliSaler.Com Voltage Rail

VREF

1 2 1 2

1 2 1

1 2 1 2

1 2 1 2

1 2 1 2

1 2 1 2

1 2 1

2 1 2

2

1

1 2

1 2

- 1.5V RAILS DDR3

2 1

1 2 2

1

GRAPHICS

1

1 2 1 2 2 2

1

1 2 1 2 1 2

3 1.2

SC10U6D3V3MX-GP C926

1

DY

SC4D7U6D3V3KX-GP C925

2

1 2 1 2

1.8

SC1U6D3V2KX-GP C936

1

VCCPLL

SC1U6D3V2KX-GP C935

2

5

0.675~0.9

SC10U6D3V3MX-GP C924

DY

SC1U6D3V2KX-GP C934

DY

SC10U6D3V3MX-GP C923

1

8.5

1.5

VCCSA

1D5V_S0

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

SC10U6D3V3MX-GP C922

2

1

C

+V1.5S_VCCD_Q

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 VCCSA9 VCCSA10 VCCSA11 VCCSA12 VCCSA13 VCCSA14 VCCSA15 VCCSA16

1 2

VDDQ_SENSE VSS_SENSE_VDDQ

1D5V_S0

2

AM28 AN26

R903 0R0402-PAD 1

BC43 BA43

TP_VDDQ_SENSE TP_VDDQ_VSS

U10

VCCSA_SENSE

TP901 TP902

1 1

TPAD14-OP-GP TPAD14-OP-GP

B

VCCSA_SENSE

VCCSA_SENSE

48

VCCSA Power Select Voltage(ULV) VCCSA_VID0 VCCSA_VID1

D48 D49

VCCSA_SEL0 VCCSA_SEL1

VCCSA_SEL0 VCCSA_SEL1

48 48

RN901 SRN1KJ-7-GP

3 4

IVY-BRIDGE-GP-NF

QUIET RAILS

1.8V RAIL SA RAIL

2

VCCPLL1 VCCPLL2 VCCPLL3

1 2 1 2 1 2

1 2 1 2 1 2

1 1 2 1 2

1 2 1 2

1 2 1

L17 L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21 W20

DY

SC1U6D3V2KX-GP C914

SC10U6D3V3MX-GP C909 SC1U6D3V2KX-GP C915

2

SC10U6D3V5KX-1GP C955

DY

SC10U6D3V3MX-GP C910 SC1U6D3V2KX-GP C916

DY

SC10U6D3V3MX-GP C911 SC1U6D3V2KX-GP C917

SC10U6D3V3MX-GP C912 SC1U6D3V2KX-GP C918

SC10U6D3V3MX-GP C913

DY

DY

SC1U6D3V2KX-GP C908

SC1U6D3V2KX-GP C907

ULV 4A

0D85V_S0 B

BB3 BC1 BC4

1.2A

2

1D8V_S0

SENSE LINES

VAXG_SENSE VSSAXG_SENSE

VCCSA VID lines

F45 G45

1

VCC_AXG_SENSE VSS_AXG_SENSE

R902 100R2F-L1-GP-U

VCCDQ1 VCCDQ2

SC1U6D3V2KX-GP C937

44 VCC_AXG_SENSE 44 VSS_AXG_SENSE

SENSE LINES

2

R901 1. PH/PL resisors place close CPU 100R2F-L1-GP-U 2. SENSE signal recommend differential routing

2 1

1 2 1 2

1.05

VDDQ

5A VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26

SC1U6D3V2KX-GP C933

1

33 29 (GT2)

D

SC1U6D3V2KX-GP C932

2

VCCIO

Iccmax(A)

Refer to CPU EDS V2.0

SC10U6D3V3MX-GP C921

1

DY

SRN1KJ-7-GP

SC10U6D3V3MX-GP C920

2

1 2 1 2

0~1.52

2 1

SC1U6D3V2KX-GP C931

1

3 4

SC1U6D3V2KX-GP C930

2

BE7 DDR_WR_VREFA BG7 DDR_WR_VREFB

SC10U6D3V3MX-GP C919

1

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

SC1U6D3V2KX-GP C929

VCC_GFXCORE

Layout Note:

RN902

SC1U6D3V2KX-GP C928

DY

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 VAXG55 VAXG56

SM_VREF

AY43

SC1U6D3V2KX-GP C927

SC1U6D3V2KX-GP C949

DY

SC10U6D3V3MX-GP C943

SC1U6D3V2KX-GP C950

SC1U6D3V2KX-GP C954

SC1U6D3V2KX-GP C952

SC1U6D3V2KX-GP C948

SC1U6D3V2KX-GP C947

SC1U6D3V2KX-GP C946

2

C906 SC22U6D3V5MX-2GP

SC10U6D3V3MX-GP C942

SC10U6D3V3MX-GP C941

DY

C905 SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP C904

SC10U6D3V3MX-GP C940

SC1U6D3V2KX-GP C951

SC1U6D3V2KX-GP C953

DY

C903 SC22U6D3V5MX-2GP

SC1U6D3V2KX-GP C945

SC1U6D3V2KX-GP C944

C

SC10U6D3V3MX-GP C939

SC10U6D3V3MX-GP C938

DY

SC10U6D3V5KX-1GP C902

C901 SC22U6D3V5MX-2GP

D

+V_SM_VREF_CNT

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46 N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61

0.3~1.52

VAXG

+V_SM_VREF_CNT should have 10 mil trace width 7 OF 9

ULV GT2 33A

VCC_GFXCORE

Voltage(V)

VCC_CORE

2

CPU1G

POWER

Layout Note:

71.00IVY.A0U

VID[0]

VID[1]

0.9

0

0.85

0

0 1

0.775

1

0

0.75

1

1

A

A

M14 DIS

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

CPU (VCC_GFXCORE) Size A2 5

4

WWW.AliSaler.Com 3

Date: 2

Document Number

Rev

OAK14 Chief River DIS Wednesday, September 05, 2012 1

Sheet

9

of

A00 105

5

4

3

2

1

SSID = CPU WWW.AliSaler.Com 8 OF 9

CPU1H

9 OF 9

CPU1I

C

B

VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180

VSS

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53 BG9 C29 C35 C40 D10 D14 D18 D22 D26 D29 D35 D4 D40 D43 D46 D50 D54 D58 D6 E25 E29 E3 E35 E40 F13 F15 F19 F29 F35 F40 F55 G51 G6 G61 H10 H14 H17 H21 H4 H53 H58 J1 J49 J55 K11 K21 K51 K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61 M11 M15

VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249

VSS

NCTF TEST PIN A5,A57,BC61,BG5 BG57,C3,E1,E61

D

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90

NCTF

A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53 A9 AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56 AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46 AC6 AD17 AD20 AD4 AD61 AE13 AE8 AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59 AG10 AG14 AG18 AG47 AG52 AG61 AG7 AH4 AH58 AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48 AJ7 AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61 AM13 AM20 AM22 AM26 AM30 AM34

VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59

VSS_NCTF_1#A5 VSS_NCTF_2#A57 VSS_NCTF_3#BC61 VSS_NCTF_8#BG5 VSS_NCTF_9#BG57 VSS_NCTF_10#C3 VSS_NCTF_13#E1 VSS_NCTF_14#E61

A5 A57 BC61 BG5 BG57 C3 E1 E61

VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_11 VSS_NCTF_12

BD3 BD59 BE4 BE58 C58 D59

D

C

B

IVY-BRIDGE-GP-NF

71.00IVY.A0U

M14 DIS

A

A

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

IVY-BRIDGE-GP-NF

71.00IVY.A0U Title

CPU (VSS) Size A3

5

4

WWW.AliSaler.Com 3

Date: 2

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OAK14 Chief River DIS W ednesday, September 05, 2012

Sheet 1

10

of

A00 105

5

4

3

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1

WWW.AliSaler.Com D

D

C

C

(Blanking)

B

B

M14 DIS

A

A

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

XDP Size A3

5

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OAK14 Chief River DIS W ednesday, September 05, 2012

Sheet 1

11

of

A00 105

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4

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1

WWW.AliSaler.Com D

D

C

C

(Blanking)

B

B

M14 DIS

A

A

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3

5

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Document Number

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OAK14 Chief River DIS W ednesday, September 05, 2012

Sheet 1

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A00 of

105

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4

3

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1

WWW.AliSaler.Com D

D

C

C

(Blanking)

B

B

M14 DIS

A

A

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3

5

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(Reserved)

Document Number

Rev

OAK14 Chief River DIS W ednesday, September 05, 2012

Sheet 1

13

A00 of

105

5

4

3

2

1

SSID = MEMORY

C1418 SC1U6D3V2KX-GP

2

1 2

C1420 SC1U6D3V2KX-GP

1 2

C1419 SC1U6D3V2KX-GP

DY

1

6 M_A_DQS#[7:0]

6 M_A_DQS[7:0] B

116 120

6 M_A_DIMA_ODT0 6 M_A_DIMA_ODT1

126 1

M_VREF_CA_DIMMA M_VREF_DQ_DIMMA

Layout Note: All VREF traces should have width=20mil; spacing=20 mil

15,37 DDR3_DRAMRST# 0D75V_S0

EC1401 1

DY

30 2 SCD1U10V2KX-5GP 203 204

M_A_DIMA_CLK_DDR0 6 M_A_DIMA_CLK_DDR#0 6

102 104

M_A_DIMA_CLK_DDR1 6 M_A_DIMA_CLK_DDR#1 6

1 1 2 2

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2

C1401 SCD1U10V2KX-5GP 1D5V_S3

Close to DIMM1.199 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

1

DY 2

1

1

DY

C1408 SC10U10V5ZY-1GP

DY

2

DY

2

DY

C1407 SC10U6D3V5KX-1GP

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

1D5V_S3

C1406 SC10U6D3V5KX-1GP

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

77 122 125

SA0_DIMA SA1_DIMA

1

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

3D3V_S0

199 197 201

2

SA0 SA1 NC#1 NC#2 NC#/TEST

PCH_SMBDATA 15,20,69 PCH_SMBCLK 15,20,69

198

C1405 SC10U6D3V5KX-1GP

VDDSPD

200 202

C1404 SC10U6D3V5KX-1GP

SDA SCL EVENT#

11 28 46 63 136 153 170 187

1

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

D

2

CK1 CK1#

1

12 29 47 64 137 154 171 188

CK0 CK0#

2

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

101 103

R1401 0R0402-PAD

1

10 27 45 62 135 152 169 186

6 6

2

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DIMA_CKE0 M_A_DIMA_CKE1

Note: SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

R1402 0R0402-PAD

C

C1417 SC1U6D3V2KX-GP

Place these caps close to VTT1 and VTT2.

73 74

SA0_DIMA SA1_DIMA

C1416 SC1U6D3V2KX-GP

Layout Note: 0D75V_S0

6 6

C1403 SC10U6D3V5KX-1GP 2 1

1 2

C1429 SCD1U10V2KX-5GP

1

DY 2

C1411 SCD1U10V2KX-5GP

1

2

M_VREF_DQ_DIMMA

CKE0 CKE1

BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

M_A_DIMA_CS#0 M_A_DIMA_CS#1

1

1

Place these caps close to VREF_DQ

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

114 121

2

1

Layout Note:

R1404 0R0402-PAD

2

2

2

DDR_VREF_S3

C1426 SCD1U10V2KX-5GP

1 C1428 SC2D2U10V3KX-1GP

DY

C1423 SC2D2U10V3KX-1GP

2

C1427 SCD1U10V2KX-5GP

1

2

M_VREF_CA_DIMMA

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

CS0# CS1#

C1415 SCD1U10V2KX-5GP

Place these caps close to VREF_CA

R1405 0R0402-PAD

C

M_A_BS0 M_A_BS1 M_A_DQ[63:0]

M_A_RAS# 6 M_A_WE# 6 M_A_CAS# 6

1

1

Layout Note:

109 108

NP1 NP2 110 113 115

2

6 6 6

DDR_VREF_S3

M_A_BS2

NP1 NP2 RAS# WE# CAS#

TC1401 ST330U2VDM-4-GP

6

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2

1

D

DM1 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79

2

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

C1414 SCD1U10V2KX-5GP

M_A_A[15:0]

1

6

2

WWW.AliSaler.Com

Layout Note: Place these Caps near SO-DIMMA.

1D5V_S0

1D5V_S3

1

2

DY C1421 SCD1U10V2KX-5GP 1

2 B

DY C1424 SCD1U10V2KX-5GP

Layout Note: For S3 reduction circuit's 1D5V return pass.

DDR3-204P-119-GP-U

62.10017.Z81

A

A

M14 DIS

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

DDR3-SODIMM1 Size A2 5

4

WWW.AliSaler.Com 3

Date: 2

Document Number

Rev

A00

DNE40 14 CR DIS Wednesday, September 05, 2012 1

Sheet

14

of

105

5

4

SSID = MEMORY

6 M_B_DQS#[7:0]

6 M_B_DQS[7:0] B

116 120

6 M_B_DIMB_ODT0 6 M_B_DIMB_ODT1

126 1

M_VREF_CA_DIMMB M_VREF_DQ_DIMMB

Layout Note: All VREF traces should have width=20mil; spacing=20 mil

30

14,37 DDR3_DRAMRST#

EC1501 1 0D75V_S0

2

DY SCD1U10V2KX-5GP 203 204

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2

SA1_DIMB

1

SA0_DIMB

1

2 10KR2J-3-GP R1506

1D5V_S3

2

0R0402-PAD

Close to DIMM1.199

1D5V_S3

DY

1 2

1

DY

C1510 SC10U6D3V5KX-1GP

DY

C1509 SC10U6D3V5KX-1GP

DY

2

DY

C1508 SC10U6D3V5KX-1GP 2 1

C

C1514 SCD1U10V2KX-5GP

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

R1507

1

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

C1501 SCD1U10V2KX-5GP

2

12 29 47 64 137 154 171 188

77 122 125

SA0_DIMB SA1_DIMB

C1507 SC10U6D3V5KX-1GP

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

3D3V_S0

199 197 201

1

10 27 45 62 135 152 169 186

PCH_SMBDATA 14,20,69 PCH_SMBCLK 14,20,69 3D3V_S0

198

1

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

200 202

C1513

Place these caps close to VTT1 and VTT2.

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

D

2

1 2

C1521 SC1U6D3V2KX-GP

1 2

C1519 SC1U6D3V2KX-GP

1 2

DY

C1518 SC1U6D3V2KX-GP

Layout Note:

NC#1 NC#2 NC#/TEST

M_B_DIMB_CLK_DDR1 6 M_B_DIMB_CLK_DDR#1 6

11 28 46 63 136 153 170 187

SCD1U10V2KX-5GP 2 1

0D75V_S0

SA0 SA1

102 104

2

2

1

Place these caps close to VREF_DQ

C1517 SCD1U10V2KX-5GP

2

DY

C1516 SC2D2U10V3KX-1GP

1

2 1 2

C1515 SCD1U10V2KX-5GP

C

Layout Note: M_VREF_DQ_DIMMB

VDDSPD

6 6

M_B_DIMB_CLK_DDR0 6 M_B_DIMB_CLK_DDR#0 6

C1504 SC10U10V5ZY-1GP

R1503 0R0402-PAD

SDA SCL EVENT#

M_B_DIMB_CKE0 M_B_DIMB_CKE1

101 103

1

1

DDR_VREF_S3

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

73 74

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

2

Place these caps close to VREF_CA

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

CK1 CK1#

BA0 BA1

6 6

C1512 SCD1U10V2KX-5GP

1 2

C1522 SCD1U10V2KX-5GP

1 2

DY

C1524 SC2D2U10V3KX-1GP

2

C1523 SCD1U10V2KX-5GP

1

Layout Note:

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

CK0 CK0#

M_B_DIMB_CS#0 M_B_DIMB_CS#1

1

2

M_VREF_CA_DIMMB

CKE0 CKE1

M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6

114 121

2

109 108

CS0# CS1#

NP1 NP2 110 113 115

C1503 SC10U10V5ZY-1GP

M_B_BS0 M_B_BS1 M_B_DQ[63:0]

NP1 NP2 RAS# WE# CAS#

1

M_B_BS2

6 6 6

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2

2

R1505 0R0402-PAD

6

1

DM2 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79

C1511 SCD1U10V2KX-5GP

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

DDR_VREF_S3

1

D

M_B_A[15:0]

1

6

2

2

WWW.AliSaler.Com

3

Layout Note: Place these Caps near SO-DIMMA.

B

DDR3-204P-90-GP

62.10017.U81

A

A

M14 DIS

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

DDR3-SODIMM2 Size A2 5

4

WWW.AliSaler.Com 3

Date: 2

Document Number

Rev

OAK14 Chief River DIS Wednesday, September 05, 2012 1

Sheet

15

of

A00 105

5

4

3

2

1

WWW.AliSaler.Com D

D

C

C

(Blanking)

B

B

M14 DIS

A

A

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3

5

4

WWW.AliSaler.Com 3

Date: 2

Document Number

Reserved

Rev

OAK14 Chief River DIS W ednesday, September 05, 2012

Sheet 1

16

A00 of

105

5

4

3

2

1

SSID = PCH WWW.AliSaler.Com

D

D

3D3V_S0

49 L_BKLT_CTRL

SRN2K2J-1-GP

RN1702

L_CTRL_CLK L_CTRL_DATA

L_BKLT_EN LVDS_VDD_EN

3 4

L_BKLTEN L_VDD_EN

P45

L_BKLTCTL

LVDS_DDC_CLK_R T40 LVDS_DDC_DATA_R K47

49 LVDS_DDC_CLK_R 49 LVDS_DDC_DATA_R

2 1

J47 M45

LVDS_IBG LVDS_VBG

L_DDC_CLK L_DDC_DATA

T45 P39

LVD_IBG LVD_VBG

AE48 AE47

LVD_VREFH LVD_VREFL

49 LVDSA_CLK# 49 LVDSA_CLK

AK39 AK40

LVDSA_CLK# LVDSA_CLK

49 LVDSA_DATA0# 49 LVDSA_DATA1# 49 LVDSA_DATA2#

AN48 AM47 AK47 AJ48

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

49 LVDSA_DATA0 49 LVDSA_DATA1 49 LVDSA_DATA2

AN47 AM49 AK49 AJ47

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

49 LVDSB_CLK# 49 LVDSB_CLK

AF40 AF39

LVDSB_CLK# LVDSB_CLK

49 LVDSB_DATA0# 49 LVDSB_DATA1# 49 LVDSB_DATA2#

AH45 AH47 AF49 AF45

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3

49 LVDSB_DATA0 49 LVDSB_DATA1 49 LVDSB_DATA2

AH43 AH49 AF47 AF43

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

SDVO_STALLN SDVO_STALLP

AM42 AM40

SDVO_INTN SDVO_INTP

AP39 AP40

RN1706 SRN2K2J-1-GP

Layout Note: Close HDMI port

P38 M39

PCH_HDMI_CLK 51 PCH_HDMI_DATA 51

DDPB_AUXN DDPB_AUXP DDPB_HPD

AT49 AT47 AT40

HDMI_PCH_DET

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

HDMI_DATA2_R# 51 HDMI_DATA2_R 51 HDMI_DATA1_R# 51 HDMI_DATA1_R 51 HDMI_DATA0_R# 51 HDMI_DATA0_R 51 HDMI_CLK_R# 51 HDMI_CLK_R 51

SDVO_CTRLCLK SDVO_CTRLDATA

2

Place near PCH; trace to trace spacing=20mil C

Layout Note: LVDS signal trace length max 4000mil

3 4

3D3V_S0

Digital Display Interface

R1701 2K37R2F-GP

Layout Note:

LVDS

1

1

AP43 AP45

L_CTRL_CLK L_CTRL_DATA

AF37 AF36

TP1701

SRN100KJ-6-GP

SDVO_TVCLKINN SDVO_TVCLKINP

2 1

27 L_BKLT_EN 49 LVDS_VDD_EN

3D3V_S0

4 OF 10

PCH1D L_CTRL_DATA L_CTRL_CLK

4 3

3 4

RN1701

1 2

N48 P49 T49

CRT_BLUE CRT_GREEN CRT_RED

T39 M40

CRT_DDC_CLK CRT_DDC_DATA

M47 M49

CRT_HSYNC CRT_VSYNC

T43 T42

DAC_IREF CRT_IRTN

P46 P42

Layout Note: HDMI trace length to DC CAP. max 10000mil

DDPC_AUXN DDPC_AUXP DDPC_HPD

AP47 AP49 AT38

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

DDPD_CTRLCLK DDPD_CTRLDATA

C

M43 M36

B

CRT_DDCCLK CRT_DDCDATA

1

DAC_IREF_R

Layout Note:

DDPD_AUXN DDPD_AUXP DDPD_HPD

AT45 AT43 BH41

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

B

PANTHER-GP-NF

71.0HM76.A0U 2

Place near PCH; trace to trace spacing=30mil

R1702 1KR2J-1-GP

CRT

2 1

RN1707 SRN2K2J-1-GP

DDPC_CTRLCLK DDPC_CTRLDATA

51

M14 DIS

A

A

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

PCH (LVDS/CRT/DDI) Size A3

5

4

WWW.AliSaler.Com 3

Date: 2

Document Number

Rev

OAK14 Chief River DIS W ednesday, September 05, 2012

Sheet 1

17

of

A00 105

5

4

3

2

1

SSID = PCH

WWW.AliSaler.Com BOARD_ID1

20

3D3V_S0

8 7 6 5

RN1804 SRN10KJ-6-GP 1 2 3 4

INT_PIRQD# KB_LED_BL_DET INT_PIRQC# PCH_GPIO04

RN1805 SRN10KJ-6-GP 1 2 3 4

PCH_GPIO52 INT_PIRQB# SATA_ODD_DA# INT_PIRQA#

3D3V_S0

8 7 6 5

Layout Note: Trace Length : PCH ~~9000mil~~Cap~~1000mil~~CONN

USB3.0/2.0 Mapping Table C

USB 3.0 Port

USB3_RX1_N USB3_RX2_N

62 USB3_RX1_N 62 USB3_RX2_N

USB 2.0 port

Port 1

Port 0

Port 2

Port 1

Port 3

Port 2

Port 4

Port 3

USB3_RX1_P USB3_RX2_P

62 USB3_RX1_P 62 USB3_RX2_P 62 USB3_TX1_N 62 USB3_TX2_N

USB3_TX1_N USB3_TX2_N

62 USB3_TX1_P 62 USB3_TX2_P

USB3_TX1_P USB3_TX2_P

SATA1GP/GPIO19

Boot BIOS Location

0

0

0

1

Reserved

1

0

Reserved

1

1

R1808

1

B

TP21 TP22 TP23 TP24

BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30

PIRQA# PIRQB# PIRQC# PIRQD#

PCH_GPIO50 PCH_GPIO52 PCH_GPIO54

C46 C44 E40

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

2 10KR2J-3-GP BBS_BIT1 TP1801 PCH_GPIO53 1 PCI_GNT3#

D47 E42 F46

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

DY

PCH_GPIO02

G42 G40 PCH_GPIO04 C42 KB_LED_BL_DET D44

56 SATA_ODD_DA#

SPI(Default) TP1802

1

PCI_PME# PCI_PLTRST#

Low = A16 swap override/Top-Block Swap Override enabled High = Default

A

AY7 AV7 AU3 BG4

RSVD5 RSVD6

AT10 BC8

RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

RSVD23 RSVD24

AV5 AV10

RSVD25

AT8

Pair

RSVD26 RSVD27

AY5 BA2

0

USB3.0 port2

1

USB3.0 port1, with Debug Port

RSVD28 RSVD29

AT12 BF3

2

USB2.0 port3

3

NC

4

NC

5

Touch Panel

6

HM76 NC

7

HM76 NC

8

NC

9

NC

10

Card reader

11

WLAN

12

NC

13

CAMERA

D

USB Table

USB2.0 Signal Group USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P USBRBIAS#

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB_PN0 USB_PP0 USB_PN1 USB_PP1 USB_PN2 USB_PP2 USB_PN4 USB_PP4

1 1

B33

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

A14 K20 B17 C16 L16 A16 D14 C14

TP1803 TP1804

USB_PN10 USB_PP10 USB_PN11 USB_PP11

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

32 32 65 65

1 2 R1811 22D6R2F-L1-GP

Layout Note:

USB_OC#0_1 61

USB_OC#4_5

USB_OC#4_5 61

OC#

1

R1812 8K2R2J-3-GP 2

3D3V_S5

RN1802 USB_OC#0_1 USB_OC#4_5

1 2

4 3

3D3V_S5

SRN10KJ-5-GP

M14 DIS

A

R1823 1 2 PCI_PLTRST# 0R0402-PAD

1

DY DY

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

C1801 SC220P50V2KX-3GP

Title

PCH (PCI/USB/NVRAM)

2

4

B

1. USBRBIAS/# use 50ohm single-ended impedance spacing to other signal=15mil 2. Length < 500mil

USB_OC#0_1

2 5

C

1. USB Ext. port 9 (HS) External debug port use on Chief River platform. 2. 2011 July; Microsoft will support USB3.0 debug--> Port1 useable.

PME# PLTRST#

Device

USB_PN13 49 USB_PP13 49

C33 USB_RBIAS

USBRBIAS

62 62 62 62 82 82

USB_PN5 49 USB_PP5 49

71.PANTH.00U

PLT_RST# R1816 100KR2J-1-GP

RSVD1 RSVD2 RSVD3 RSVD4

PANTHER-GP-NF

1

5,27,31,65,71,83

DY EC1804DY EC1805 1

DY

2 22R2J-2-GP CLK_PCI_FB_R H43 2 22R2J-2-GP CLK_PCI_KBC_R J48 K42 H40

SC10P50V2JN-4GP

PCI_GNT#3

EC1802

1

Swap Override jumper

SC4D7P50V2CN-1GP

A16

C6

LPC 2 22R2J-2-GP CLK_PCI_LPC_R H49

1 1 1

2

CLK_PCI_LPC CLK_PCI_FB CLK_PCI_KBC

2

71 20 27

2

R1801 4K7R2J-2-GP

R1807 R1805 R1806

1

DY

K10

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PCI_GNT3#

1

SC4D7P50V2CN-1GP

2

USB3RN1 USB3RN2 USB3RN3 USB3RN4 USB3RP1 USB3RP2 USB3RP3 USB3RP4 USB3TN1 USB3TN2 USB3TN3 USB3TN4 USB3TP1 USB3TP2 USB3TP3 USB3TP4

K40 K38 H38 G38

3D3V_S0

LPC

B21 M20 AY16 BG46

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

Boot Bios Strap GNT1#/GPIO51

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

USB

PCH_GPIO50 PCH_GPIO54 PCH_GPIO02 BOARD_ID1

BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45

RSVD

RN1803 SRN10KJ-6-GP 1 2 3 4

PCI

8 7 6 5

D

5 OF 10

PCH1E

3D3V_S0

Size A3

WWW.AliSaler.Com 3

Date: 2

Document Number

Rev

A00

DNE40 14 CR DIS W ednesday, September 05, 2012

Sheet 1

18

of

105

5

4

3

2

1

SSID = PCH WWW.AliSaler.Com 3 OF 10

4 DMI_CPU_TXP_PCH_RXP[3:0]

4 DMI_CPU_RXN_PCH_TXN[3:0]

4 DMI_CPU_RXP_PCH_TXP[3:0]

Layout Note: DMI_ZCOMP keep W=4 mils and routing length less than 500 1D05V_PCH mils. DMI_IRCOMP keep W=4 mils and R1901 1 routing length less than 500 R1902 1 mils.

BC24 BE20 BG18 BG20

DMI0RXN DMI1RXN DMI2RXN DMI3RXN

DMI_CPU_TXP_PCH_RXP0 DMI_CPU_TXP_PCH_RXP1 DMI_CPU_TXP_PCH_RXP2 DMI_CPU_TXP_PCH_RXP3

BE24 BC20 BJ18 BJ20

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI_CPU_RXN_PCH_TXN0 DMI_CPU_RXN_PCH_TXN1 DMI_CPU_RXN_PCH_TXN2 DMI_CPU_RXN_PCH_TXN3

AW24 AW20 BB18 AV18

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI_CPU_RXP_PCH_TXP0 DMI_CPU_RXP_PCH_TXP1 DMI_CPU_RXP_PCH_TXP2 DMI_CPU_RXP_PCH_TXP3

AY24 AY20 AY18 AU18

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

BJ24 2 49D9R2F-GP DMI_COMP_R

BG25

2 750R2F-GP

BH21

RBIAS_CPY

FDI_CPU_TXN_PCH_RXN[7:0]

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

FDI_CPU_TXN_PCH_RXN0 FDI_CPU_TXN_PCH_RXN1 FDI_CPU_TXN_PCH_RXN2 FDI_CPU_TXN_PCH_RXN3 FDI_CPU_TXN_PCH_RXN4 FDI_CPU_TXN_PCH_RXN5 FDI_CPU_TXN_PCH_RXN6 FDI_CPU_TXN_PCH_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

FDI_CPU_TXP_PCH_RXP0 FDI_CPU_TXP_PCH_RXP1 FDI_CPU_TXP_PCH_RXP2 FDI_CPU_TXP_PCH_RXP3 FDI_CPU_TXP_PCH_RXP4 FDI_CPU_TXP_PCH_RXP5 FDI_CPU_TXP_PCH_RXP6 FDI_CPU_TXP_PCH_RXP7

FDI_INT

AW16

FDI_INT

FDI_INT

AV12

FDI_FSYNC0

FDI_FSYNC0

FDI_FSYNC1

BC10

FDI_FSYNC1

FDI_FSYNC1

4

FDI_LSYNC0

AV14

FDI_LSYNC0

FDI_LSYNC0

4

FDI_LSYNC1

BB10

FDI_LSYNC1

FDI_LSYNC1

4

DSWVRMEN

A18

DSW ODVREN

DPWROK

E22

PCH_DPW ROK

WAKE#

B9

PCH_W AKE#

CLKRUN#/GPIO32

N3

PM_CLKRUN#

SUS_STAT#/GPIO61

G8

PM_SUS_STAT#

SUSCLK/GPIO62

N14

SUS_CLK

SLP_S5#/GPIO63

D10

PM_SLP_S5#

SLP_S4#

H4

PM_SLP_S4#

SLP_S3#

F4

PM_SLP_S3#

SLP_A#

G10

PM_SLP_A#

1

TP1903

SLP_SUS#

G16

PM_SLP_SUS#

1

TP1904

PMSYNCH

AP14

H_PM_SYNC

K14

PM_SLP_LAN#

1

TP1905

FDI

D

DMI_CPU_TXN_PCH_RXN0 DMI_CPU_TXN_PCH_RXN1 DMI_CPU_TXN_PCH_RXN2 DMI_CPU_TXN_PCH_RXN3

DMI

PCH1C 4 DMI_CPU_TXN_PCH_RXN[3:0]

DMI_ZCOMP

FDI_FSYNC0

DMI_IRCOMP DMI2RBIAS

4

D

FDI_CPU_TXP_PCH_RXP[7:0]

4

4

DSWODVREN - On Die DSW VR Enable 4

HIGH

Enabled (DEFAULT)

LOW

Disabled

TP1907 R1905 1

5 36

1

SUSACK#

C12

2 10KR2J-3-GP K3

XDP_DBRESET# SYS_PW ROK

1 R1921 2 0R0402-PAD

27,36 S0_PW R_GOOD

1

45,46,47,93 RUNPW ROK

R1907

DY

PW ROK 1 R1916 2 0R0402-PAD 2 0R2J-2-GP

MEPW ROK

R1924 1 2 0R0402-PAD

27 PM_PW RBTN#

B

27,86 AC_PRESENT 27

BATLOW #

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

PM_RSMRST#

C21

RSMRST#

SUS_PW R_ACK

K16

SUSWARN#/SUSPWRDNACK/GPIO30

37 PM_DRAM_PW RGD 27 RSMRST#_KBC

SUSACK#

PM_PW RBTN#

E20

AC_PRESENT

H20

BATLOW #

E10

PM_RI#

A10

PWRBTN# ACPRESENT/GPIO31 BATLOW#/GPIO72 RI#

SLP_LAN#/GPIO29

DSW ODVREN R1911 R1927

1 1

DY

2 10KR2J-3-GP 2 0R0402-PAD

R1917

1

2 330KR2J-L1-GP C

PM_RSMRST#

3D3V_S0

1 R1929 2 0R0402-PAD 1

PM_CLKRUN#

R1919

1

2 8K2R2J-3-GP

TP1901 TPAD14-OP-GP

1 R1925 2 0R0402-PAD 1

PM_CLKRUN#_EC 27

PCH_SUSCLK_KBC

27

PCH_SUSCLK_KBC

TP1902 TPAD14-OP-GP

2

3D3V_S0

EC1901 SC4D7P50V2CN-1GP

PM_SLP_S4# 27,46

DY 1

C

System Power Management

RTC_AUX_S5 RTC_AUX_S5

PM_SLP_S3# 27,36,37,47

B

H_PM_SYNC

5

PANTHER-GP-NF

Sequence: S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

71.PANTH.00U

3D3V_S5 SYS_PW ROK

S0_PW R_GOOD

RUNPW ROK

DY

EC1903 SCD1U10V2KX-5GP

DY

2

DY

EC1902 SCD1U10V2KX-5GP

1

EC1907 SCD1U10V2KX-5GP

2

1

BATLOW # PM_RI# SUS_PW R_ACK PCH_W AKE#

2

1 2 3 4

1

RN1901

8 7 6 5

SRN10KJ-6-GP

PM_DRAM_PW RGD

1

A

2

R1926 R1904

1 1

DY

2

R1908

1 10KR2J-3-GP PM_RSMRST#

DY

RSMRST#_KBC

EC1904 SCD1U10V2KX-5GP

DY

EC1905 SCD1U10V2KX-5GP

AC_PRESENT

1

2 100KR2J-1-GP AC_PRESENT 1 10KR2J-3-GP PM_SLP_LAN#

M14 DIS

EC1906 SCD1U10V2KX-5GP

Wistron Corporation

DY

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

2 100KR2J-1-GP SYS_PW ROK 2 100KR2J-1-GP PW ROK

Title

PCH (DM I/FDI/PM)

reserve for EMI Request

5

A

2

DY

1

1 2

2

R1909 R1920

4

WWW.AliSaler.Com 3

Size A3 Date: 2

Document Number

Rev

A00

DNE40 14 CR DIS W ednesday, September 05, 2012

Sheet 1

19

of

105

5

4

SSID = PCH

3

2

WWW.AliSaler.Com

S5 power rail CLKREQ#: PCIECLKRQ[0]# PCIECLKRQ[7:3]#

3D3V_S5

1

3D3V_S5 SMB_CLK SMB_DATA

4 3

1 RN2003 2 SRN2K2J-1-GP

SML0_DATA SML0_CLK SML1_CLK SML1_DATA

1 2 3 4

8 RN2004 7 SRN2K2J-2-GP 6 5

RN2001

PCIE_TXN3_C PCIE_TXP3_C

BF36 BE36 AY34 BB34

31 31 31 31

C

PCH_RXN_C_LAN_TXN6 PCH_RXP_C_LAN_TXP6 LAN_RXN_C_PCH_TXN6 LAN_RXP_C_PCH_TXP6

C2001 1 C2002 1

2 SCD1U10V2KX-5GP PCH_TXN_LAN_RXN6 2 SCD1U10V2KX-5GP PCH_TXP_LAN_RXP6

Layout Note:

PERN4 PERP4 PETN4 PETP4

BG37 BH37 AY36 BB36

PERN5 PERP5 PETN5 PETP5

BJ38 BG38 AU36 AV36

PERN6 PERP6 PETN6 PETP6

BG40 BJ40 AY40 BB40

PERN7 PERP7 PETN7 PETP7

BE38 BC38 AW38 AY38

PERN8 PERP8 PETN8 PETP8

Layout trace < 14000mil

3D3V_S0

S0 power rail CLKREQ#: PCIECLKRQ[2:1]# 1 2

4 3

CLK_PCIE_W LAN_REQ# CLK_PCIE_REQ1#

PCIE_CLK_RQ2# PCIE_CLK_RQ1# PCIE_CLK_REQ0#

NC NC WLAN NC LAN NC NC

CLKOUT_PCIE0N CLKOUT_PCIE0P

J2

65 CLK_PCIE_W LAN# 65 CLK_PCIE_W LAN

CLK_PCH_SRC2_N CLK_PCH_SRC2_P

CLKOUT_PCIE1N CLKOUT_PCIE1P

M1

CLKOUT_PCIE2N CLKOUT_PCIE2P

Layout Note:

PCIE_CLK_REQ3#

CLKOUT termination place close to PCH