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4046 Phase Locked Loop as an FM Demodulator 1. Construct the following circuit in which a CD4046BE Phase Locked Loop (PLL) IC is configured as an FM Demodulator that relies on the output of Phase Comparator I, basically an XOR gate. V1 9Vdc

U1 16

V2 VOFF = 0 VAMPL = FC = MOD = FM =

0

0.1u

C1 0.01u

R1

0

ZE NE R

VD D*

0

C3

15

10k

14 3 4 6 7 11 12 5

SIG_IN DEMO_OUT COMP_IN VCO_OUT C1 COMP1_OUT C2 COMP2_OUT VS R1 PH_PULSE S* VCO_IN R2 INH 8

10 Rs 100k

2 13 1 9

R3 10k

CD4046

C2 0.1u

0

You will use the headphone output of your laptop and Cool Edit software as the source V 2 that provides the FM signal for demodulation. Here is a possible layout:

0

In this layout, pins 5 and 8 are connected to ground simply by bending and soldering them to the adjacent ground buss on the backside of the PC board. Pin 16 connects to the 9V buss in a similar fashion. Also, pin 9 connects to the junction of R3 and C2 on the backside of the PC board. 2. With no input to the PLL, the VCO in a 4046 PLL made with Phase Comparator I idles at a center frequency, f o , that depends mainly on R1 and C1 , but also varies with the power supply voltage, Vcc , and from chip to chip. The data sheet for the CD4046BE describes typical dependence of f o on these parameters in the form of a parameterized log-log plot. With the values for the circuit of part 1, note that the plot indicates a typical value for

f o lies somewhere between 1kHz and 10 kHz , although a note on the plot indicates that the values of f o for a particular chip can vary by  50% from the value indicated on the chart.

With the input of your PLL circuit shorted to ground (with a black alligator clip, for instance), display the output voltage (that is, the voltage at pin 10 and the voltage across the resistor Rs ) in the FFT Analyzer of the Real Time Analyzer to determine the approximate value of f o . Ideally, the output voltage should be absolutely zero with no input to the demodulator. In practice, a small amount of the VCO output leaks through, enough to let you observe the VCO frequency of oscillation. Because this leakage signal is very small, its Fourier spectrum will appear noisy. Once you have identified the frequency spike corresponding to the VCO frequency, you should adjust the frequency range of the FFT Analyzer to focus in on the range near the VCO frequency so that you can use the cursor to obtain a reasonably accurate measurement of its value. Include a screen shot of the Fourier spectrum of the output voltage, and record your estimate for f 0 . Why not observe the output of the VCO directly at pin 4? Because the input impedance of the microphone input on your laptop is low enough to affect the operation of the VCO, a very low power CMOS circuit that is easily disturbed. The output terminal, pin 10, on the other hand, is driven by a voltage follower, a circuit that is often used to replicate a voltage from a circuit easily disturbed by measurement as the Thevenin voltage of a circuit with a low Thevenin resistance. A solution: Here is a screen shot of the Fourier spectrum of the output voltage:

Note the spikes at about 9 kHz and at about 18 kHz . These spikes evidently correspond to the fundamental and second harmonic of the VCO frequency with no input to the demodulator. Here is a screen shot of the Fourier spectrum with an expanded frequency scale:

By using the cursor, the value of the fundamental frequency, which corresponds to the frequency f o , is seen to be about

fo  8936 Hz  9.0 kHz 3. The relative unpredictability of the center frequency, f o , of the PLL may seem disturbing, but in practice it is not an insurmountable problem. First, the CD4046BE data sheet shows that once the VCO in a PLL that employs the Phase Comparator I locks onto an input, the PLL remains phase-locked over the frequency range 0  f  2 f L , where the lock frequency, f L , with Phase Comparator I is just the center frequency f o , the frequency you measured in part 2 for your particular circuit: f L  fo . Thus, lock-in is

possible over a broad range of frequencies so that the value of f o is less critical that it might first appear. Initially, however, the input frequency to the PLL must be somewhat close to the center frequency, f o , before the PLL can capture and lock onto the input signal. How close must the input frequency be to f o ? Again according to the CD4046BE data sheet, the frequency of the input signal must differ from f o by no more than the capture frequency, f C : fC 

2 f L

1



1

where

f L  fo

 1  R3 C2 The capture range of frequencies for a PLL, therefore, is:

f L  fC  f  f L  fC The capture range of frequencies, f L  fC  f  f L  fC , is smaller than the lock-in range of frequencies, 0  f  2 f L . Calculate the range of input frequencies, f L  fC  f  f L  fC which your circuit should be able to capture. Show your calculations and record your values. A solution:

 1  R3 C2  10000  0.1  F   103 sec fC 

1 2

2 f L

1



Thus, the capture range is

1 2

2  9000 Hz  1200 Hz 103 sec

f L  fC  f  f L  fC 9.0 kHz  1.2 kHz  f  9.0 kHz  1.2 kHz 7.8 kHz  f  10.2 kHz

4. Use Cool Edit to generate 10sec of an FM modulated signal with a sinusoidal carrier frequency near the value you measured for the center frequency, f o , with single tone sinusoidal modulation with frequency

f m  400 Hz , and with a frequency deviation  f  400 Hz so that the modulation index is    f f m  1 . Calculate the bandwidth of this FM signal according to Carson's rule (Rizzoni, Chapter 19) and, from this result, note and record the approximate range of frequencies that should be present in the FM modulated waveform. As you feed the FM modulated signal from Cool Edit through the headphone output on your laptop to the input of the PLL, measure the Fourier spectrum of the FM signal at the PLL input with the Real Time FFT Analyzer and compare its frequency range with the frequency range you calculated from Carson's rule. Be sure that you adjust the signal level to keep the Real Time Analyzer Peak Level Monitor within range. Include a screen shot of the Fourier spectrum of the FM modulated signal. If a large portion of the Fourier spectrum lies within the capture range for your circuit, your PLL should have no problem in capturing and locking onto this FM modulated input signal. A solution: Carson's rule: the approximate bandwidth, B , of an FM modulated signal is given by:

 1 1  B  2  f  2 f m  2  f 1    2  400 Hz  1    1.6 kHz  1  

With a center frequency of fo  9.0 kHz , the range of frequencies estimated according to Carson's rule should be: fo 

B B  f  fo  2 2

9.0 kHz  0.8 kHz  f  9.0 kHz  0.8 kHz 8.2 kHz  f  9.8 kHz

Here is a screen shot of the Fourier spectrum of the input to the PLL:

The main Fourier spectrum of the input signal lies in the range 6.5 kHz  f  11.5 kHz , in only fair agreement with the approximate

frequency range calculated from Carson's rule: 8.2 kHz  f  9.8 kHz . The extra bandwidth may be due to

harmonics introduced by nonlinear distortion in the audio system in my laptop. Certainly, the secondary spectrum centered around 18 kHz reflects second harmonic nonlinear distortion in the

imperfect audio system. Notice, however, that the peak of the secondary spectrum is more than 50 dB below the peak of the main

spectrum, more than 100 times smaller in amplitude. The logarithmic vertical scale magnifies, for good purpose, small amplitudes so that they are more visible. 5. As you feed the FM modulated signal generated in part 4 from Cool Edit through the headphone output on your laptop to the input of the PLL, use the Realtime Analyzer Oscilloscope to display the PLL output, which should show the modulating signal, a 400 Hz sine wave. For best results, make the output from your large. Include a screen shot of the output waveform, as well as a check of its frequency calculated from the period of the displayed sinusoid. A solution: Here is a screen shot of the PLL output waveform:

Note that the period of the waveform is 2.5 m sec , corresponding to the modulation frequency of 400 Hz .

6. To investigate the effect of increasing the modulation frequency on the output of the PLL FM demodulator, modify the FM modulated signal generated by Cool Edit so that the modulating frequency, f m , sweeps from 400 Hz to 700 Hz during the 10sec duration of the waveform. Set  f  400 Hz and keep the carrier frequency f c at the value you set before.

As you send this swept frequency waveform into the PLL, use the Real Time Analyzer Oscilloscope to make screen shots of the output waveform at a time early in the waveform and at a time late in the waveform. Include these screen shots and explain their implication about the audio frequency response of your circuit. A solution: Here is a screen shot of the PLL output waveform at low frequency (early):

Here is a screen shot of the PLL output waveform at high frequency (late):

Note that at the amplitude of the output for high frequency modulation is smaller than its amplitude for low frequency modulation. This behavior indicates that the response of this circuit drops as the modulation frequency increases. 7. To investigate the effect of increasing the frequency deviation of the FM modulated input on the output of the PLL FM demodulator, modify the FM modulated signal generated by Cool Edit so that the frequency deviation,  f , sweeps from 300 Hz to 600 Hz during the 10sec duration of the

waveform. Set f m  400 Hz and keep the carrier frequency f c at the value you set before. As you send this swept frequency waveform into the PLL, use the Real Time Analyzer Oscilloscope to make screen shots of the output waveform at a time early in the waveform and at a time late in the waveform. Include these screen shots and explain their implication about the effects of increasing the frequency deviation on the response of your circuit. A solution:

Here is a screen shot of the PLL output waveform at low deviation (early):

Here is a screen shot of the PLL output waveform at high deviation (late):

Note that at the amplitude of the output at low frequency deviation is smaller than its amplitude at high deviation. This behavior shows, as expected, that the response of this circuit increases as the frequency deviation of the input signal increases. Note also, that the signal appears more distorted, becomes more triangular in fact, at larger frequency deviations. 8. To investigate the effect of increasing the carrier frequency of the FM modulated input on the output of the PLL FM demodulator, modify the FM modulated signal generated by Cool Edit so that the carrier frequency, f o , sweeps from 7500 Hz (which should be below the capture range you calculated in part 3) to 15000 Hz during the 10sec duration of the waveform. Set f m  400 Hz and set  f  100 Hz . As you send this swept frequency waveform into the PLL, use the Real Time Analyzer Oscilloscope to display the output waveform. When the swept waveform begins, the carrier frequency is below the capture range of the PLL. As the carrier frequency increases during the waveform, you can observe the change in the output waveform as the PLL captures the input waveform. Before the waveform ends, the carrier frequency is above the capture range but the PLL remains locked to the input signal because the carrier frequency should be still within the lock-in range, 0  f  2 f o mentioned in part 2. Include screen shots of the PLL output voltage at a time early in the waveform and at a time late in the waveform and explain their implication about the effects of sweeping the carrier frequency on the response of your circuit. In particular, compare the range of permissible carrier frequencies of the PLL as an FM demodulator with that of a ratio detector, the demodulation circuit used in the AM/FM radio you constructed. A solution: Here is a screen shot of the PLL output waveform with low carrier frequency (early), but after capture:

Here is a screen shot of the PLL output waveform with high carrier frequency (late):

These two screen shots show that the PLL can demodulate FM signals with a broad range of carrier frequencies, a range of

somewhat less than 2 to 1. In contrast, ratio detectors, which rely on tuned circuits for operation, can function over a range of perhaps 10 % of the carrier frequency.

9. OrCAD PSpice 10.0 Demo does not have a PSpice model for the 4046 PLL IC. Thus, use instead the Cadence PSD 15.0, full strength industrial software available on the computers available in Simrall 131. The Cadence software uses the same Capture schematic capture environment as OrCAD PSpice Demo 10, but includes the PSpice model CD 4046 in the MIX_MISC library. In the simulation, use the component values shown in part 1. To produce the FM modulated input signal, use the PSpice single frequency FM voltage source, VSFFM, available in the SOURCE library. Set the carrier frequency to the value you used in the earlier parts. Set f m  400 Hz and  f  400 Hz so that the modulation index   1 . Note that the MOD property for the VSFFM source corresponds to the modulation index,  . For the moment, set the amplitude of the source to zero so that there is no input to the PLL, attach a voltage probe to the VCO output, run a transient simulation for a few milliseconds, and from the resulting plot determine the approximate value for the center frequency f o , the frequency at which the VCO oscillates when no input is present. Recall the large tolerance on the center frequency of particular CD4046BE chips mentioned in the data sheet. Thus, the VCO idle frequency produced by the simulation can be far different than the one that you measured. As a consequence, the simulated PLL may not capture and lock onto the FM modulated input signal during the simulation. To deal with this problem, adjust the value of capacitor C1 until the simulated VCO frequency roughly matches the center frequency you measured for your particular circuit. Note and record this value. Once you have accomplished adjustment of the center frequency of the simulation, set the amplitude of the VSFFM source to 0.5V , add voltage probes to the output of the PLL (pin 10) and to the top of the VSFFM source, and run the simulation for about 10 cycles of the modulation frequency, f m  400 Hz .

Set the maximum step size during simulation to 1  sec . Ignore the countless simulation warnings. Include screen shots of your Capture schematic and of your simulation output plots. The output voltage of the PLL should be roughly sinusoidal with frequency 400 Hz . Include, in addition, a screen shot of the Fourier spectrum of the FM output of the VSFFM PSpice source and compare this spectrum with the result of Carson’s rule that you calculated in part 4. A solution: Here is a screen shot of the Capture schematic:

Note the choice C1  0.003 F to obtain a center frequency near 9 kHz .

Here is a screen shot of the simulation outputs:

Note that the PLL locks in after about 8 m sec . The output waveform is roughly sinusoidal with period of about 2.5 m sec , which corresponds to a frequency of about 400 Hz . Here is a screen shot that shows the simulated Fourier spectrum of the FM modulated input signal to the PLL:

Notice that the major frequency components lie in the range 8.2 kHz  f  9.8 kHz . In part 4, we saw that Carson’s rule predicts

the range of frequencies to be 8.2 kHz  f  9.8 kHz . The close agreement suggests that the extra width of the spectrum measured in part 4 resulted from imperfections in the audio system on my laptop. 10.Explain how a digital divider that divides an input frequency by N and a PLL chip such as the CD4046BE can be configured as a frequency synthesizer that in effect provides a variable frequency output based on a single fixed frequency reference source. Note that because the output frequency of the PLL can be controlled electronically, this approach is used to tune the local oscillator in most contemporary superheterodyne receivers, including those in TVs and cell phones.

A solution: To configure a CD4046BE PLL as a variable frequency synthesizer, connect the input of the PLL to a stable reference frequency, say 1kHz (or for some applications the 60 Hz frequency of the power

lines), connect the output of the VCO to the input of the digital divider, and connect the output of the digital divider to the input of Phase Comparator II, which in comparison with Phase Comparator I offers the advantages of not locking on to harmonics of the reference frequency and of accommodating a periodic pulse waveform at its input rather than the square wave required at the input of Phase Comparator I. The phase comparator compares the reference frequency, f ref , with fVCO N , where fVCO is the frequency of the VCO. Once the PLL locks in, fVCO  N f ref . With a reference frequency of, for example, f ref  1 kHz , the frequency of the VCO can be varied in increments of 1kHz by adjusting the value of N .