5 4 3 2 1 D D DR1(Roberts) Schematics Document uFCPGA Mobile Penryn Intel Cantiga-GM + ICH9M C C 2009-08-03 REV
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DR1(Roberts) Schematics Document uFCPGA Mobile Penryn Intel Cantiga-GM + ICH9M C
C
2009-08-03 REV : -3 B
B
DY : Nopop Component
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Custom Date: Monday, August 03, 2009 5
4
3
2
Cover Page
Rev
-3
Roberts Sheet 1
1
of
59
5
4
3
2
1
CPU DC/DC
Roberts Block Diagram D
Socket P
28,29
INPUTS
OUTPUTS
+PWR_SRC
+VCC_CORE
SYSTEM DC/DC
Project code : 91.4AQ01.001 PCB P/N : 48.4AQ01.031 Revision : 08212-3
Intel Mobile CPU Penryn
Clock Generator SLG8SP513VTR 4
ISL6266A
TPS51117
30
INPUTS
OUTPUTS
+PWR_SRC
+1.05V_VCCP
D
5,6,7
SYSTEM DC/DC MAX17020 FSB 800/1066MHz
INPUTS
OUTPUTS +5V_ALW2 +3.3V_RTC_LDO +5V_ALW +3.3V_ALW
+PWR_SRC
DDRII 667/800
Slot 0 14
DDRII 667/800 Channel A
Intel Cantiga-GML
SYSTEM DC/DC
CRT (on I/O board)
RGB CRT
TPS51116 Power SW
AGTL+ CPU I/F
DDRII 667/800
C
Slot 1 15
LVDS(Dual Channel)
DDR Memory I/F
DDR II 667/800 Channel B
G577BR91U
LCD
27
INPUTS
41
35
31
OUTPUTS +1.8V_SUS +0.9V_DDR_VTT +V_DDR_MCH_REF
+PWR_SRC
External Graphics
C
8,9,10,11,12,13
PCIE x 1 & USB 2.0 x 1
PCIE x 1
10/100 NIC Marvell 88E8040
SD/MMC MS/MS Pro/xD
USB2.0
Realtek RTS5159
37
Digital Mic Array MIC IN
CAMERA (Option)
USB 2.0 x 1
USB 2.0
SATA ports (4)
OUTPUTS
+5V_ALW
+5V_RUN
+3.3V_ALW
+3.3V_RUN
37
MAX8731A
26
B
41
INPUTS
OUTPUTS
+DC_IN
LPC I/F
+PWR_SRC
ACPI 1.1
+PBATT
USB 2.0 x 1
Bluetooth
41
USB 2.0 x 1
Right Side: USB x 1
43
PCI/PCI BRIDGE
IDT 92HD71B7
LPC Bus
16,17,18,19 22
Internal Analog MIC
34
MAXIM CHARGER
PCI Express ports (6)
AZALIA
+1.5V_RUN
LDO
Mini-Card
PCIE x 1
High Definition Audio
Azalia CODEC
+1.8V_SUS
SYSTEM DC/DC
USB 2.0/1.1 ports (12)
CAMERA Module
OUTPUTS
INPUTS
ICH9-M
32
INPUTS
Left Side: USB x 2
41
PCIE
APL5912 RJ45 CONN
802.11a/b/g 21
B
20
USB 2.0 x 2
Intel
CardReader
SYSTEM DC/DC 41
I/O Board Connector
C-LINK
DMIx4
New Card
PCB LAYER L1: Top
OP AMP MAX9789A
SATA
HP1
SATA
L2: VCC L3: Signal
KBC
WINBOND
SPI
L4: Signal
24
WPCE773L
L5: GND
23
L6: Bottom A
A
2CH SPEAKER HDD 36
ODD 36
Flash ROM 2MB 42
Touch PAD 44
Int. KB
Thermal & Fan EMC2102
44
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
25
40 Title
Block Diagram
Size Document Number Custom
Date: Thursday, August 27, 2009 5
4
3
2
Rev
-3
Roberts Sheet 1
2
of
59
A
B
C
ICH9M Functional Strap Definitions Usage/When Sampled
HDA_SDOUT
XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 PCIE Port Config1 bit1, pulled low. When TP3 not pulled low at rising edge Rising Edge of PWROK. of PWROK, sets bit1 of RPC.PC (Cofig Registers: offset 224h). This signal has weak internal pull-down. PCIE config1 bit0, Rising Edge of PWROK.
HDA_SYNC
This signal has a weak internal pull-down. Sets bit0 of PRC.PC (Config Registers: Offset 224h).
GNT2#/ GPIO53
PCIE config2 bit2, Rising Edge of PWROK.
This signal has a weak internal pull-up. Sets bit2 of PRC.PC2 (Config Registers: Offset 224h).
GPIO20
Reserved.
This signal should not be pulled high.
GNT1#/ GPIO51
ESI Strap (Server Only) ESI compatible mode is for server platforms only. Rising Edge of PWROK. This signal should not be pulled low for desktop and mobile.
GNT3#/ GPIO55
Top-Block Swap override. Rising Edge of PWROK.
Sampled low: Top-Block Swap mode (inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down. Controllable via Boot BIOS Destination bit (Config Registers: Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC
GNT0#: SPI_CS1#/ GPIO58
Boot BIOS Destination Selection 0:1. Rising Edge of PWROK.
SPI_MOSI
Integrated TPM Enable, Sample low: the Integrated TPM will be disable. Rising Edge of CLPWROK. Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable.
GPIO49
DMI Termination Voltage. Rising Edge of CLPWROK.
SATALED#
SPKR
TP3
2
Rev.1.5
Signal
4
3
ICH9 EDS 642879 Comment
GPIO33/ HDA_DOCK _EN#
ICH9 Integrated pull-up and pull-down Resistors
The signal is required to be low for desktop applications and required to be high for mobile applications.
ICH9 EDS 642879
E
Rev.1.5
Montevina Platform Design guide 22339 Rev.0.5
Resistor Type/Value
Pin Name
Strap Description
CL_CLK[1:0]
PULL-UP 20K
CFG[2:0]
CL_DATA[1:0]
PULL-UP 20K
FSB Frequency Select 000 = FSB1067 011 = FSB667 010 = FSB800 others = Reserved
CL_RST0#
PULL-UP 20K
DPRSLPVR/GPIO16
PULL-DOWN 20K
ENERGY_DETECT
SIGNAL
Configuration
4
PULL-UP 20K
CFG[4:3] Reserved CFG8 CFG[15:14] CFG[18:17]
HDA_BIT_CLK
PULL-DOWN 20K
CFG5
DMI x2 Select
0 = DMI x2 1 = DMI x4 (Default)
HDA_DOCK_EN#/GPIO33
PULL-UP 20K
CFG6
iTPM Host Interface
HDA_RST#
PULL-DOWN 20K
0 = The iTPM Host Interface is enabled (Note 2) 1 = The iTPM Host Interface is disabled (default)
HDA_SDIN[3:0]
PULL-DOWN 20K
CFG7
HDA_SDOUT
PULL-DOWN 20K
Intel Management engine crypto strap
0 = Transport Layer Security (TLS) cipher suite with no confidentiality 1 = TLS cipher suite with confidentiality(Default)
HDA_SYNC
PULL-DOWN 20K
CFG9
PCIE Graphics Lane
GLAN_DOCK#
The pull-up or pull-down active when configured for native GLAN_DOCK# functionality and determined by LAN controller.
0 = Reserved Lanes, 15->0, 14->1 ect.. 1 = Normal operation (Default): Lane Numbered in Order
CFG10
PCIE Loopback enable 0 = Enable (Note 3) 1 = Disable (Default)
GNT[3:0]#/GPIO[55,53,51]
PULL-UP 20K
GPIO20
PULL-DOWN 20K
GPIO49
PULL-UP 20K
LDA[3:0]#/FHW[3:0]#
PULL-UP 20K
LAN_RXD[2:0]
PULL-UP 20K
LDRQ[0]
PULL-UP 20K
LDRQ[1]/GPIO23
PULL-UP 20K
PME#
PULL-UP 20K
PWRBTN#
PULL-UP 20K
SATALED#
PULL-UP 15K
SPI_CS1#/GPIO58/CLGPIO6
PULL-UP 20K
PCI Express Lane Reversal. Rising Edge of PWROK.
Signal has weak internal pull-up. Sets bit 27 of MPC.LR (Device 28: Function 0:Offset D8).
SPI_MOSI
PULL-DOWN 20K
No Reboot. Rising Edge of PWROK.
If sampled high, the system is strapped to the "No Reboot" mode (ICH9 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.
SPI_MISO
PULL-UP 20K
SPKR
PULL-DOWN 20K
TACH_[3:0]
PULL-UP 20K
XOR Chain Entrance. Rising Edge of PWROK. Flash Descriptor Security Override Strap. Rising Edge of PWROK.
This signal should not be pull low unless using XOR Chain testing. Sampled low: the Flash Descriptor Security will be overridden. If high, the security measures will be in effect. This should only be enabled in manufacturing environments using an external pull-up resister.
TP[3]
PULL-UP 20K
USB[11:0][P,N]
PULL-DOWN 15K
PCIE Routing
D
Cantiga chipset and ICH9M I/O controller Hub strapping configuration
CFG[13:12] XOR/ALL
00 10 01 11
CFG16
FSB Dynamic ODT
0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default)
CFG19
DMI Lane Reversal
0 = Normal operation (Default): Lane Numbered in Order 1 = Reverse Lanes DMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3) DMI x2 mode [MCH->ICH]: (3->0, 2->1)
CFG20
Digital Display Port 0 = Only Digital Display Port or PCIE is operational (Default) (SDVO/DP/iHDMI) display Port and PCIe are operating Concurrent with PCIe 1 = Digital simulataneously via the PEG port
SDVO SDVO Present _CTRLDATA L_DDC_DATA Local Flat Panel (LFP) Present
= = = =
Reserve XOR mode Enabled ALLZ mode Enable (Note 3) Disabled (Default)
3
0 = No SDVO Card Present (Default) 1 = SDVO Card Present 0 = LFP Disabled (Default) 1 = LFP Card Present; PCIE disabled
NOTE: 1. All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal. 2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6. Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.
2
USB Table USB
1
LANE2
MiniCard WLAN
LANE3
LAN
LANE5
New Card
Pair 0 1 2 3 4 5 6 7 8 9 10 11
Device USB1 USB2 USB3 RESERVED MINI CARD RESERVED BLUETOOTH NEW CARD RESERVED RESERVED Card Reader CAMERA
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Custom Date: Monday, May 18, 2009
Table of Content
Rev
-3
Roberts Sheet
3
of
59
2
1
3D3V_S0_CK505_IO
NEWCARD_CLKREQ# CLK_PCIE_NEW CLK_PCIE_NEW#
3D3V_S0_CK505_IO
1
CLK_XTAL_IN CLK_XTAL_OUT
R217 1
CLK_48M_CARD
2
3 2
2 22R2J-2-GP
19 27 43 52 33 56
U54
VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO
4 16 9 46 62 23
C461 SC12P50V2JN-3GP
DY VDDREF VDD48 VDDPCI VDDSRC VDDCPU VDDPLL3
2
1
1 C462 SC12P50V2JN-3GP
2
1
C237 SCD1U16V2KX-3GP
2
1
C215 SCD1U16V2KX-3GP
2
1 2
C209 SCD1U16V2KX-3GP
1 2
C239 SCD1U16V2KX-3GP
1 2
2
DY
C210 SCD1U16V2KX-3GP
1
1
X-14D31818M-37GP
2
1 R204 2 0R0603-PAD
C226 SC10U6D3V5MX-3GP
2
1
D
C229 SC1U10V3KX-3GP
X3
1
CLK_48M_ICH
3D3V_S0_CK505
CPUT1_F CPUC1_F
58 57
CLK_MCH_BCLK CLK_MCH_BCLK#
CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8
54 53
CLK_CPU_ITP CLK_CPU_ITP#
SRCT7/CR#_F SRCC7/CR#_E
51 50
CLK_PCIE_LAN CLK_PCIE_LAN#
SRCT6 SRCC6
48 47
1
USB_48MHZ/FSLA
45 44
PCI_STOP# CPU_STOP#
SRCC10
41 42
SRCT11/CR#_H SRCC11/CR#_G
40 39
SRCT9 SRCC9
37 38
CLK_PCIE_MINI1 CLK_PCIE_MINI1#
SRCT4 SRCC4
34 35
CLK_MCH_3GPLL CLK_MCH_3GPLL#
SRCT3/CR#_C SRCC3/CR#_D
31 32
CLK_PCIE_ICH CLK_PCIE_ICH#
SRCT2/SATAT SRCC2/SATAC
28 29
CLK_PCIE_SATA CLK_PCIE_SATA#
27MHZ_NONSS/SRCT1/SE1 27MHZ_SS/SRCC1/SE2
24 25
MCH_SSCDREFCLK MCH_SSCDREFCLK#
SRCT0/DOTT_96 SRCC0/DOTC_96
20 21
DY 2SC4D7P50V2CN-1GP
7 6
CK_PWRGD
63
CPUT0 CPUC0
X1 X2
17
ICH_SMBCLK ICH_SMBDATA
A00.08/0910 CLK_CPU_BCLK CLK_CPU_BCLK#
1
H_STP_PCI# H_STP_CPU#
C234 SCD1U16V2KX-3GP
2
1
C225 SCD1U16V2KX-3GP
2
1 2
C207 SCD1U16V2KX-3GP
1 2
C238 SCD1U16V2KX-3GP
1 2
C218 SCD1U16V2KX-3GP
1 2
C211 SC10U6D3V5MX-3GP
1 2
C233 SC1U10V3KX-3GP
C245 1 R200 2 0R0603-PAD
FSA 2 22R2J-2-GP
ICS9LPRS355BKLFT-GP-USRCT10 SCLK SDATA CK_PWRGD/PD#
27_SEL ITP_EN
CLK_14M_ICH
R190 1
2 33R2J-2-GP
FSB FSC
64 5
FSLB/TEST_MODE REF0/FSLC/TEST_SEL
55
NC#55 GND48 GNDPCI GNDREF
1
C224 SC4D7P50V2CN-1GP
18 15 1
DY 2
1
C243 SC4D7P50V2CN-1GP
DY 2
1
C236 SC4D7P50V2CN-1GP
2
DY
PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN
GND
2 33R2J-2-GP 2 33R2J-2-GP
DY
CLKREQ#_1 PCI2_TME
CLK_PCIE_NEW CLK_PCIE_NEW# NEWCARD_CLKREQ# MINI1_CLKREQ# C
CLK_MCH_DREFCLK CLK_MCH_DREFCLK#
A00.08/0910
65
R207 1 R212 1
A00.08/0922
2 475R2F-L1-GP 2 33R2J-2-GP
22 30 36 49 59 26
PCLK_KBC CLK_PCI_ICH
8 10 11 12 13 14
R178 1 R196 1
GND GNDSRC GNDSRC GNDSRC GNDCPU GND
C
CLKSATAREQ# CLKREQ#_B PCLK_FWH
D
61 60
R216 +3.3V_RUN
DY
+3.3V_RUN
1
+3.3V_RUN
2 10KR2J-3-GP 2 10KR2J-3-GP
2
3D3V_S0_CK505
R193 1 R195 1
EC57 SC22P50V2JN-4GP
NEWCARD_CLKREQ# MINI1_CLKREQ#
1
SSID = CLOCK
C464 SC4D7P50V2CN-1GP
3
2
4
C463 SC4D7P50V2CN-1GP
5
Main source: 71.08513.003 (SLG8SP513VTR) 2nd source: 71.00875.C03 (RTM875N-606-VD-GRT) 3rd source: Co-layout Ref: 71.09355.B03 (ICS9LPRS355BKLFT) B
B
SRC8 CPU_ITP
PCI2_TME
DY
1 EC140 SC47P50V2JN-3GP
DY
EC139 SC47P50V2JN-3GP
PCI2_TME R202 10KR2J-3-GP
0
Overclocking of CPU and SRC allowed
1
Overclocking of CPU and SRC not allowed
27_SEL
PIN 20
PIN 21
0
DOT96T
DOT96C
1
SRCT0
SRCC0
GM45 PM45
2
DY
Output
CLK_MCH_DREFCLK#
2
0 1
R206 10KR2J-3-GP
R198 10KR2J-3-GP
2
1
Output
1 R218 10KR2J-3-GP
2
DY
ITP_EN
2
1
ITP_EN
1
2
R209 10KR2J-3-GP
CLK_MCH_DREFCLK 1
27_SEL
2
3D3V_S0_CK505 1
3D3V_S0_CK505
SEL2 SEL1 SEL0 FSC FSB FSA 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0
A
CPU 100M 133M 166M 200M 266M
FSB X 533M 667M 800M 1067M
R186 1
CPU_BSEL2
2 10KR2J-3-GP
SB
1 R412 2 0R0402-PAD R214 1 2 2K2R2J-2-GP
CPU_BSEL1 CPU_BSEL0
FSC
Wistron Corporation
FSA
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
R215 1
2 1KR2J-1-GP
MCH_CLKSEL0
R411 1
2 1KR2J-1-GP
MCH_CLKSEL1
R181 1
2 1KR2J-1-GP
MCH_CLKSEL2
Title
Clock Generator SLG8SP513VTR
Size Document Number Custom
Date: Tuesday, August 11, 2009 5
4
3
A
FSB
2
Rev
-3
Roberts Sheet 1
4
of
59
5
4
3
2
1
SSID = CPU U41A 1 OF 4 H_A#[35..3]
H_ADSTB#1
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1
H_A20M# H_FERR# H_IGNNE#
A6 A5 C4
A20M# FERR# IGNNE#
H_STPCLK# H_INTR H_NMI H_SMI#
D5 C6 B4 A3
STPCLK# LINT0 LINT1 SMI#
C
B
TP12
1 1 1 1 1 1 1 1 1 1
RSVD_CPU_1 RSVD_CPU_2 RSVD_CPU_3 RSVD_CPU_4 RSVD_CPU_5 RSVD_CPU_6 RSVD_CPU_7 RSVD_CPU_8 RSVD_CPU_9 RSVD_CPU_10
M4 N5 T2 V3 B2 C3 D2 D22 D3 F6
1
RSVD_CPU_11
B1
CONTROL
BR0# IERR# INIT#
H_ADS# H_BNR# H_BPRI#
H5 F21 E1
H_DEFER# H_DRDY# H_DBSY#
F1
LOCK#
H4
RESET# RS0# RS1# RS2# TRDY#
C1 F3 F4 G3 G2
HIT# HITM#
G6 E4
BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
PROCHOT# THRMDA THRMDC THERMTRIP#
BCLK0 BCLK1
R47
2 56R2J-4-GP H_INIT#
1
H_TRDY# H_HIT# H_HITM# ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_DBRESET# R50
1
R51
1
DY
ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_DBRESET# 2 0R2J-2-GP 2 56R2J-4-GP
D21 A24 B25
C CPU_PROCHOT#
H_THRMTRIP# 1
DY
2 56R2J-4-GP
H_THERMDA
+1.05V_VCCP H_THERMDA H_THERMDC
C7
A22 A21
+1.05V_VCCP
H_LOCK# H_CPURST# H_RS#[2..0]
H_CPURST# H_RS#0 H_RS#1 H_RS#2
R76
HCLK
D
H_BREQ#0
D20 CPU_IERR# B3
THERMAL
ICH
TP30 TP31 TP13 TP23 TP21 TP24 TP19 TP55 TP25 TP34
A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1#
ADDR GROUP 1
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
REQ0# REQ1# REQ2# REQ3# REQ4#
DEFER# DRDY# DBSY#
H1 E2 G5
+1.05V_VCCP
1
H_REQ#0 K3 H_REQ#1 H2 H_REQ#2 K2 H_REQ#3 J3 H_REQ#4 L1
ADS# BNR# BPRI#
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
DY H_THERMDC
2
H_ADSTB#0 H_REQ#[4..0]
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0#
XDP/ITP SIGNALS
D
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1
ADDR GROUP 0
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16
C49 SC2200P50V2KX-2GP
H_THRMTRIP# should connect to ICH9 and MCH without T-ing.
A00.08/0903 CLK_CPU_BCLK CLK_CPU_BCLK#
RSVD#M4 RSVD#N5 RSVD#T2 RSVD#V3 RSVD#B2 RSVD#C3 TEST7 RSVD#D2 RSVD#D22 RSVD#D3 RSVD#F6
RESERVED
H_A#[35..3]
KEY_NC
B
BGA479-SKT6-GPU7
62.10040.221
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Custom
CPU-FSB(1/3)
Date: Tuesday, August 11, 2009
Rev
-3
Roberts Sheet
5
of
59
5
4
3
2
1
SSID = CPU
D
H_DINV#[3..0] H_DSTBN#[3..0] H_DSTBP#[3..0] H_D#[63..0]
D H_DINV#[3..0] H_DSTBN#[3..0] H_DSTBP#[3..0] H_D#[63..0]
Layout notes Z= 55 Ohm 0.5" MAX for CPU_GTLREF0
2
+1.05V_VCCP
R354 2KR2F-3-GP
CPU_GTLREF0
2
DY 2
B
H_DSTBN#1 H_DSTBP#1 H_DINV#1
1
1
1
R357 1KR2F-3-GP
C376 SC1KP50V2KX-1GP
R53 R60 R58
1 1 1
R7
1
DY DY DY DY
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
2 1KR2J-1-GP 2 1KR2J-1-GP 2 1KR2J-1-GP
TEST1 TEST2 CPU_TEST3
2 1KR2J-1-GP
CPU_TEST5
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1#
AD26 C23 D25 C24 AF26 AF1 A26
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6
B22 B23 C21
DATA GRP1
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31
DATA GRP3
H_DSTBN#0 H_DSTBP#0 H_DINV#0
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0#
DATA GRP0
C
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
DATA GRP2
U41B 2 OF 4 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15
MISC
BSEL0 BSEL1 BSEL2
D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47
D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3#
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
COMP0 COMP1 COMP2 COMP3
R26 U26 AA1 Y1
COMP0 COMP1 COMP2 COMP3
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
E5 B5 D24 D6 D7 AE6
C
H_DSTBN#2 H_DSTBP#2 H_DINV#2
H_DSTBN#3 H_DSTBP#3 H_DINV#3 R350 R349 R14 R13
1 1 1 1
2 2 2 2
27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP
H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# PSI#
Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5". Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5".
B
BGA479-SKT6-GPU7
62.10040.221
Route the CPU_TEST3 and CPU_TEST5 signals through a ground referenced Zo = 55-ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection.
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Custom
CPU-FSB(2/3)
Date: Tuesday, August 11, 2009
Rev
-3
Roberts Sheet
6
of
59
5
4
3
2
1
SSID = CPU 1 2
1 2
1
C366 SC22U6D3V5MX-2GP
2
DY 2
DY
C365 SC22U6D3V5MX-2GP
DY
1
C3 SC22U6D3V5MX-2GP
1 2
2
C6 SC22U6D3V5MX-2GP
DY
DY
C367 SC22U6D3V5MX-2GP
1
C5 SC22U6D3V5MX-2GP
DY
C338 SC22U6D3V5MX-2GP
1
C370 SC22U6D3V5MX-2GP
DY
2
1
C11 SC22U6D3V5MX-2GP
DY
2
2
1
DY
2
1
DY
C10 SC22U6D3V5MX-2GP
1 2
1 2
C363 SC22U6D3V5MX-2GP
1 2
C357 SC22U6D3V5MX-2GP
2
1
C13 SC22U6D3V5MX-2GP
1 2
1 2
1
1
C35 SC22U6D3V5MX-2GP
2
C24 SC22U6D3V5MX-2GP
1 2
1 2
C368 SC22U6D3V5MX-2GP
2
1
C347 SC22U6D3V5MX-2GP
1
C344 SC22U6D3V5MX-2GP
2
1
C340 SC22U6D3V5MX-2GP
2
1
C29 SC22U6D3V5MX-2GP
2
1
C30 SC22U6D3V5MX-2GP
2
1 2
C32 SC22U6D3V5MX-2GP
1 2
1 2
C12 SC22U6D3V5MX-2GP
+VCC_CORE
C336 SC22U6D3V5MX-2GP
1
1 2
2
2
2
C7 SCD1U10V2KX-4GP
VSS_SENSE
+1.5V_VCCA
2
VSSSENSE
1
VCC_SENSE
AE7
C9 SCD1U10V2KX-4GP
AF7
layout note: "+1.5V_VCCA" as short as possible
2
VCCSENSE
1
AD6 AF5 AE5 AF4 AE3 AF3 AE2
C45 SCD1U10V2KX-4GP
VID0 VID1 VID2 VID3 VID4 VID5 VID6
1
B26 C26
DY
1
VCCA VCCA
1
VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
2
C43 SCD1U10V2KX-4GP
C44 SCD1U10V2KX-4GP
+1.05V_VCCP
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
BGA479-SKT6-GPU7
2
1 2
1
DY 2
1 2
C14 SC22U6D3V5MX-2GP
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
C8 SCD1U10V2KX-4GP
+1.5V_RUN 1 R356 2 0R0603-PAD
C374 SCD01U16V2KX-3GP
R311 1
R302 1
2 100R2F-L1-GP-U
2
1
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6
1
CPU_VID[6..0]
2
B
DY
U41D A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
+VCC_CORE VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
TC17 ST220U2D5VBM-LGP
C
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
DY
C26 SC22U6D3V5MX-2GP
U41C 3 OF 4 A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
C31 SC22U6D3V5MX-2GP
+VCC_CORE
DY
C352 SC22U6D3V5MX-2GP
+VCC_CORE
C36 SC22U6D3V5MX-2GP
D
DY
C15 SC22U6D3V5MX-2GP
2
DY
C17 SC22U6D3V5MX-2GP
1
C25 SC22U6D3V5MX-2GP
+VCC_CORE
C377 SC10U6D3V5MX-3GP
Layout Note: Place as close as possible to the CPU VCCA pin.
+VCC_CORE
VCC_SENSE and VSS_SENSE lines should be of equal length.
2 100R2F-L1-GP-U
4 OF 4
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
62.10040.221
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
D
C
NCTF PIN CPU_GND11
TP10 B
CPU_GND21 CPU_GND31
TP224 TP20
CPU_GND41
TP56
BGA479-SKT6-GPU7
62.10040.221
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Custom
CPU-Power(3/3)
Date: Tuesday, August 11, 2009 5
4
3
2
Rev
-3
Roberts Sheet 1
7
of
59
5
4
3
2
1
SSID = MCH
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
+1.05V_VCCP
H_SWING routing Trace width and Spacing use 10 / 20 mil
R368 221R2F-2-GP 2
H_SWING Resistors and Capacitors close MCH 500 mil ( MAX )
R367 100R2F-L1-GP-U 2
2
1
1
H_SWING C399 SCD1U10V2KX-4GP
H_RCOMP routing Trace width and Spacing use 10 / 20 mil
B
1 R361
2 H_RCOMP 24D9R2F-L-GP
Place R51 near to the chip ( < 0.5")
H_SWING H_RCOMP
C5 E3
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
H_SWING H_RCOMP
2
+1.05V_VCCP
F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6
HOST
H_D#[63..0]
1
C
H_D#[63..0]
1
C12 E11
H_CPURST# H_CPUSLP#
R369 1KR2F-3-GP
A11 B11
H_AVREF H_DVREF
A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
J8 L3 Y13 Y1
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
L10 M7 AA5 AE6
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
L9 M8 AA6 AE5
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4
B15 K13 F13 B13 B14
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_RS#_0 H_RS#_1 H_RS#_2
B6 F12 C8
H_RS#0 H_RS#1 H_RS#2
D
C H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BREQ#0 H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DINV#[3..0]
H_DSTBN#[3..0]
B H_DSTBP#[3..0]
H_REQ#[4..0]
H_RS#[2..0]
H_DSTBP#[3..0]
H_REQ#[4..0]
H_RS#[2..0]
CANTIGA-GM-GP-U-NF
1
DY
H_CPURST# H_CPUSLP#
H_A#[35..3]
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
C403 SCD1U16V2KX-3GP
2
R372 2KR2F-3-GP
2
1
H_AVREF
H_A#[35..3]
1 OF 10
U52A
D
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Cantiga-HOST(1/6)
Size Document Number Custom
Date: Tuesday, August 11, 2009
Rev
-3
Roberts Sheet
8
of
59
4
3
+3.3V_RUN
BF28 BH28
SM_RCOMP_VOH SM_RCOMP_VOL
SM_VREF SM_PWROK SM_REXT SM_DRAMRST#
AV42 AR36 BF17 BC36
SM_REXT R374 1
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#
B38 A38 E41 F41
CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK#
PEG_CLK PEG_CLK#
F43 E43
CLK_MCH_3GPLL CLK_MCH_3GPLL#
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
AE41 AE37 AE47 AH39
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
R121 1
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
AE40 AE38 AE48 AH40
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
AE35 AE43 AE46 AH42
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
AD35 AE44 AF46 AH43
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
2 2K21R2F-GP CFG18
FSB setting
2 4K02R2F-GP CFG19
MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2
2 4K02R2F-GP CFG20
RN20 4 3
1 2
PM_EXTTS#0 PM_EXTTS#1
SRN10KJ-5-GP R383 1 R112 1 R111 1 R102 1 R382 1 R375 1 R101 1 R105 1 R103 1
DY DY DY DY DY DY DY DY DY
2 2K21R2F-GP CFG5 2 2K21R2F-GP CFG6 2 2K21R2F-GP CFG7
1 1
TP84 TP85
2 2K21R2F-GP CFG8 2 4K02R2F-GP CFG9
1
TP87
2 2K21R2F-GP CFG10
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
CFG
CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20
1 1
TP86 TP88
T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28
RSTIN# PM_PWROK
R29 B7 N33 P32 AT40 AT11 T20 R32
2009/07/27
PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
PM
PM_SYNC# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1
2 2K21R2F-GP CFG16
1 1
1 2
C151 SCD01U16V2KX-3GP
2
2
DY
R116 3K01R2F-3-GP
SM_RCOMP_VOL 2
R142 10KR2J-3-GP R145 10KR2J-3-GP
C145 SC2D2U10V3KX-1GP
R119 1KR2F-3-GP 1
2
DY
CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK#
C162 SCD01U16V2KX-3GP
1
1 1 2 499R2F-2-GP
C159 SC2D2U10V3KX-1GP
+1.8V_SUS
2
+V_DDR_MCH_REF
C
CLK_MCH_3GPLL CLK_MCH_3GPLL#
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 +1.05V_VCCP
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
+3.3V_RUN
R370 56R2J-4-GP
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
CANTIGA-GM-GP-U-NF
TSATN#
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
B33 B32 G33 F33 E33
GFX_VR_EN
C34
DY
R371 10KR2J-3-GP
B
TSATN#_KBC
DY
Q19 MMBT3904WT1G-GP
B
+1.05V_VCCP
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
AH37 AH36 AN36 AJ35 AH34
MCH_CLVREF
DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC#
N28 M28 G36 E36 K36 H36
TSATN#
B12
HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC
B28 B30 B29 C29 A28
R126 1KR2F-3-GP
CL_CLK0 CL_DATA0 M_PWROK CL_RST#0
MCH_CLVREF ~= 0.35V
MISC
A
NC#BG48 NC#BF48 NC#BD48 NC#BC48 NC#BH47 NC#BG47 NC#BE47 NC#BH46 NC#BF46 NC#BG45 NC#BH44 NC#BH43 NC#BH6 NC#BH5 NC#BG4 NC#BH3 NC#BF3 NC#BH2 NC#BG2 NC#BE2 NC#BG1 NC#BF1 NC#BD1 NC#BC1 NC#F1 NC#A47
NC
H_THRMTRIP# DPRSLPVR
DY
BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47
HDA
C94 SC100P50V2JN-3GP
1
-3
2
100R2J-2-GP
2
1
ME
R94 PLT_RST#
SM_RCOMP_VOH
TSATN#_KBC
2 2K21R2F-GP CFG12 2 2K21R2F-GP CFG13
R122 1KR2F-3-GP
R377 80D6R2F-L-GP
C
R117 1
2 2K21R2F-GP CFG11
DMI
R128 1
DY DY DY DY
2
SM_RCOMP_VOH SM_RCOMP_VOL
1
M_RCOMPP M_RCOMPN
2
BG22 BH21
GRAPHICS VID
R104 1
B
SM_RCOMP SM_RCOMP#
CLK
C
M_ODT0 M_ODT1 M_ODT2 M_ODT3
1
L_DDC_DATA DDPC_CTRLDATA
Reverse DMI lanes
BD17 AY17 BF15 AY13
2
SDVO_CTRLDATA
* PCIE and SDVO are Only PCIE or SDVO simultaneously * operatiing is operational via the PEG port enable SDVO interface disable * SDVOLFPinterface LFP disable card present * SDVO/iHDMI/DP SDVO/iHDMI/DP interface disabled * interface enabled Normal operation
RESERVED#BG23 RESERVED#BF23 RESERVED#BH18 RESERVED#BF18
SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1
+1.8V_SUS
1
CFG 19 DMI Lane Reserved CFG 20 SDVO concurrent with PCIE
BG23 BF23 BH18 BF18
M_CS0# M_CS1# M_CS2# M_CS3#
2
FSB dynamic ODT disable
CFG 16
RESERVED#AY21
BA17 AY16 AV16 AR13
D
R380 80D6R2F-L-GP
E
XOR mode enable
SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1
+1.8V_SUS
1
CFG 13
AY21
M_CKE0 M_CKE1 M_CKE2 M_CKE3
2
ALLZ mode enable
BC28 AY28 AY36 BB36
1
PCIE loopback enable
CFG 12
RESERVED#B31 RESERVED#B2 RESERVED#M1
SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1
2
CFG 10
B31 B2 M1
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
1
PCIE GFX lane reversed
AR24 AR21 AU24 AV20
2
CFG 9
SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1
2
CFG 7
* * * * PCIE loopback disable * ALLZ mode disable * XOR mode disable * FSB Dynamic ODT enable * ITPM disable
TLS cipher suite with confidentiality PCIE GFX lane numbered in oder
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
1
ITPM enable TLS cipher suite with no confidentiality
RSVD
CFG 6
D
DMI X 4
AP24 AT21 AV24 AU20
1
TP271
+3.3V_RUN
1
High
DMI X 2
1
R130 499R2F-2-GP
R131 CLKREQ#_B
1
2
10KR2J-3-GP
2
Low
CFG 5
SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1
1
CFG Strap
RESERVED#M36 RESERVED#N36 RESERVED#R33 RESERVED#T33 RESERVED#AH9 RESERVED#AH10 RESERVED#AH12 RESERVED#AH13 RESERVED#K12 RESERVED#AL34 RESERVED#AK34 RESERVED#AN35 RESERVED#AM35 RESERVED#T24
2
* is current setting
M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24
DDR CLK/ CONTROL/COMPENSATION
SSID = MCH
2
2 OF 10
U52B
C175 SCD1U10V2KX-4GP
5
CLKREQ#_B MCH_ICH_SYNC# TSATN#
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Cantiga-DMI/CFG(2/6)
Size Document Number Custom
Date: Tuesday, August 11, 2009
Sheet
Rev
-3
Roberts 9
of
59
5
4
3
2
1
SSID = MCH
B
CANTIGA-GM-GP-U-NF
A
M_A_BS#0 M_A_BS#1 M_A_BS#2
SA_RAS# SA_CAS# SA_WE#
BB20 BD20 AY20
M_A_RAS# M_A_CAS# M_A_WE#
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14
BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14
M_A_DQS[7..0]
M_A_DQS#[7..0]
M_A_A[14..0]
M_A_DM[7..0]
M_A_DQS[7..0]
M_A_DQS#[7..0]
M_A_A[14..0]
M_B_DQ[63..0]
5 OF 10
U52E M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
SB_BS_0 SB_BS_1 SB_BS_2
BC16 BB17 BB33
M_B_BS#0 M_B_BS#1 M_B_BS#2
SB_RAS# SB_CAS# SB_WE#
AU17 BG16 BF14
M_B_RAS# M_B_CAS# M_B_WE#
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7
AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14
AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
M_B_DM[7..0]
B
BD21 BG18 AT25
MEMORY
M_B_DQ[63..0]
SA_BS_0 SA_BS_1 SA_BS_2
M_A_DM[7..0]
A
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
MEMORY
AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12
SYSTEM
4 OF 10
U52D M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
DDR
M_A_DQ[63..0]
SYSTEM
C
M_A_DQ[63..0]
DDR
D
D
M_B_DM[7..0]
M_B_DQS[7..0]
M_B_DQS[7..0]
M_B_DQS#[7..0]
M_B_DQS#[7..0]
C
M_B_A[14..0]
M_B_A[14..0]
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14
B
CANTIGA-GM-GP-U-NF
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Cantiga-DDR(3/6)
Size Document Number Custom
Date: Tuesday, August 11, 2009
Rev
-3
Roberts Sheet
10
of
59
4
3
2
SSID = MCH
1
FOR VCC CORE
1 2
C156 SCD1U10V2KX-4GP
1 2
C166 SCD1U10V2KX-4GP
1 2
C113 SCD22U10V2KX-1GP
1 2
C111 SC10U6D3V5MX-3GP
1 2
C164 SCD1U10V2KX-4GP
1 2
C142 SC1U10V3KX-3GP
1 2
C170 SC22U6D3V5MX-2GP
C161 SCD47U6D3V2KX-GP
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
T32
D
VCC
+1.05V_VCCP
Imax
Supply
Signal Group
+1.05V_VCCP
VCC
2898.52mA
+1.05V_VCCP
VCC_AXG
8700mA
+1.05V_VCCP
VTT
852mA
+1.05V_VCCP
VCC_PEG
1782mA
+1.05V_VCCP
VCC_DMI
456mA
+1.05V_VCCP
VCCA_SM
720mA
+1.05V_VCCP
VCCA_SM_CK
26mA
+1.05V_VCCP
VCCA_HPLL
24mA
+1.05V_VCCP
VCCA_MPLL
139.2mA
+1.05V_VCCP
VCCD_HPLL
157.2mA
+1.05V_VCCP
VCCA_PEG_PLL
50mA
+1.05V_VCCP
VCCD_PEG_PLL
50mA
+1.05V_VCCP
VCC_AXF
321.35mA
+1.5V_RUN
VCC_HDA
50mA
+1.5V_RUN
VCCD_TVDAC
35mA
+1.8V_SUS
VCCD_LVDS
60.31mA
+1.8V_SUS
VCC_SM
3000mA
+1.8V_SUS
VCC_SM_CK
124mA
+3.3V_RUN
VCCA_PEG_BG
414uA
+3.3V_RUN
VCC_HV
105.3mA
VCC NCTF
1 2
2
DY
C435 SC22U6D3V5MX-2GP
1
C426 SC22U6D3V5MX-2GP
1 2
TC21 ST220U2D5VBM-2GP
1
+1.8V_SUS
POWER
1
C80 SCD1U10V2KX-4GP
2
1 2
C98 SCD1U10V2KX-4GP
1 2
C84 SCD1U16V2KX-3GP
1 2
2
C91 SCD22U10V2KX-1GP
1
C390 SC22U6D3V5MX-2GP
1 2
C383 SC10U6D3V5MX-3GP
1 2
C173 SCD1U16V2KX-3GP
1 2
C110 SCD1U16V2KX-3GP
1 2
C108 SCD1U16V2KX-3GP
Place CAP where LVDS and DDR2 taps
2
VCC_AXG_SENSE VSS_AXG_SENSE
FOR VCC SM
C431 SCD1U10V2KX-4GP
AJ14 AH14
VCC_GMCH_35
AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33
SB
VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF
AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23
C
B
1 2
C186 SC1U10V3KX-3GP
C178 SC1U10V3KX-3GP
1 2
1 2
C182 SCD47U6D3V2KX-GP
C134 SCD22U10V2KX-1GP
1 2
C81 SCD22U10V2KX-1GP
1 2
2
1
AV44 SM_LF1_GMCH BA37 SM_LF2_GMCH AM40 SM_LF3_GMCH AV21 SM_LF4_GMCH AY5 SM_LF5_GMCH AM10 SM_LF6_GMCH BB13 SM_LF7_GMCH C92 SCD1U10V2KX-4GP
CANTIGA-GM-GP-U-NF
VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF
1
VCC GFX
CANTIGA-GM-GP-U-NF
C99 SCD1U10V2KX-4GP
1VCC_AXG_SENSE 1VSS_AXG_SENSE
1 R125 2 0R0402-PAD
2
TP83 TP82
Coupling CAP
Place on the Edge
VCC SM LF
A
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
1 2
8700mA
B
Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14
Coupling CAP
1
POWER VCC GFX NCTF
+1.05V_VCCP
DY
Coupling CAP 370 mils from the Edge
TC19 ST220U2D5VBM-2GP
VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC
W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16
Place on the Edge
2
BA36 BB24 BD16 BB21 AW16 AW13 AT13
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
+1.05V_VCCP
2898.52mA
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
3000mA
C
AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29
VCC SM
D
7 OF 10
U52G
+1.8V_SUS
6 OF 10
U52F
+1.05V_VCCP
VCC CORE
5
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Cantiga-Power(4/6)
Size Document Number Custom
Date: Monday, July 27, 2009
Rev
-3
Roberts Sheet
11
of
59
5
+1.05V_VCCP
4
VCCA_LVDS
J47
VSSA_LVDS
VCCA_PEG_BG
1
TC3 ST220U2D5VBM-LGP
2
1
EC48 SCD1U25V3KX-GP
2
1 2
C128 SC4D7U6D3V3KX-GP
1 2
C123 SC4D7U6D3V3KX-GP
1 2
C135 SC2D2U10V3KX-1GP
C143 SCD47U6D3V2KX-GP
1
1 2
1 2
C408 SC1U10V3KX-3GP
C
C407 SC10U6D3V5MX-3GP
2 2 1
R100 1R3F-GP
1
1
1 R97 2 0R0805-PAD
C137 SC10U6D3V5MX-3GP
1 2
1 2
B
C449 SC22U6D3V5MX-2GP
1 2
1 2
1 2
C191 SC10U6D3V5MX-3GP
VTTLF VTTLF VTTLF
HV
AH48 AF48 AH47 AG47
1
105.3mA
VCC_DMI VCC_DMI VCC_DMI VCC_DMI
1 R405 2 0R0603-PAD
+1.05V_VCCP
C446 SC10U6D3V5MX-3GP
+1.05V_VCCP
1
VTTLF1 VTTLF2 VTTLF3
2
A8 L1 AB2
CANTIGA-GM-GP-U-NF 1
1
2 C181 SCD1U10V2KX-4GP
1 2
1 2
C90 SCD47U6D3V2KX-GP
VCCD_LVDS VCCD_LVDS
C394 SCD47U6D3V2KX-GP
M38 L37
60.31mA
1D8V_SUS_DLVDS
2
C133 SCD1U10V2KX-4GP
AXF 124mA
SM CK
A CK
321.35mA
2 VCCD_PEG_PLL 50mA
V48 U48 V47 U47 U46
C395 SCD47U6D3V2KX-GP
C438 SCD1U10V2KX-4GP
+1.8V_SUS 1 R140 2 0R0603-PAD
DY
1
1
C385 SCD1U10V2KX-4GP
157.2mA
VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG
+3.3V_VCC_HV
2
VCCD_HPLL
AA47
1D8V_TXLVDS_S3
C447 SC4D7U6D3V3KX-GP
AF1
1D05V_RUN_PEGPLL
35mA
2mA
K47 C35 B35 A35
PEG
VCCD_QDAC
BF21 BH20 BG20 BF20
VCC_HV VCC_HV VCC_HV
1782mA
VCCD_TVDAC
L28
VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK
456mA
M25
1D5VRUN_QDAC
DMI
1D5VRUN_TVDAC
1D05V_RUN_HPLL
2
50mA
B22 B21 A21
VTTLF
VCC_HDA
VCC_AXF VCC_AXF VCC_AXF
118.8mA VCC_TX_LVDS
D TV/CRT
A32
1 R373 2 0R0603-PAD
+1.8V_SUS
TV
1
C416 SCD01U16V2KX-3GP
VCC_HDA
C437 SCD1U10V2KX-4GP
+1.8V_SUS
LVDS
+1.05V_VCCP
1 2 1
Reserved for TV ripple
852mA
POWER
VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF
VCCA_TV_DAC VCCA_TV_DAC
1 10R2J-2-GP
BAT54-7-F-GP
VCCA_PEG_PLL 50mA
B24 A24
2
1 R398 2 0R0402-PAD
+1.05V_VCCP
HDA
1
C157 SCD1U10V2KX-4GP
AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23
2
1 2
C158 SCD1U10V2KX-4GP
1 2
C154 SCD01U16V2KX-3GP
1 R395 2 0R0402-PAD
2
1D05V_VCC_AXF
VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM
+3.3V_VCC_HV
R396
3
A PEG
AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16
+3.3V_RUN
D22 1
A SM
1 2
C129 SC1U10V3KX-3GP
1
C130 SC4D7U6D3V3KX-GP
2
AA48
+1.05V_VCCP
C440 SC1KP50V2KX-1GP
AD48
DY 2
1
C417 SCD1U10V2KX-4GP
DY
G9091-330T12U-GP
Main source: 74.09091.H3F 2nd source: 74.09198.07F
VTT
13.2mA
D
DY
2
J48
1 2
C445 SC10U6D3V5MX-3GP
1D8V_TXLVDS
U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1
1D05V_SM_CK
2
1
C126 SC22U6D3V5MX-2GP
2 1
C144 SC2D2U10V3KX-1GP
DY 2
2 1 2
1 R378 2 0R0402-PAD
U53 EN GND VIN VOUT NC#5
CRT
1
C433 SCD1U10V2KX-4GP
2 1
VCCA_MPLL 139.2mA
24mA
A LVDS
2 2 1
C127 SC22U6D3V5MX-2GP
1 2 1 2 1 2 1
AE1
+3.3V_TV_DAC
1 R360 2 0R0603-PAD
2
C419 SC10U6D3V5MX-3GP
VCCA_HPLL
1D5VRUN_QDAC
1 2 3 4 5
+3.3V_CRT_LDO
AD1
C442 SCD1U10V2KX-4GP 1D05V_RUN_PEGPLL
2
2
2
1
C153 SCD01U16V2KX-3GP
C152 SCD1U10V2KX-4GP
1
+3.3V_CRT_LDO
1 R120 2 0R0603-PAD
+5V_RUN
A
M_VCCA_HPLL
79mA
180ohm 100MHz
VCCA_DPLLB
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
414uA
L3 1 2 HCB1608K-181T20GP
VCCA_DPLLA
L48
VCCA_PEG_BG
DY
1D5VRUN_TVDAC
A00.08/0903
F47
M_VCCA_DPLLB
5mA
26mA
1 R115 2 0R0603-PAD
M_VCCA_DPLLA
C441 SC1KP50V2KX-1GP
+1.05V_VCCP
+1.05V_VCCP
+1.5V_RUN
VCCA_DAC_BG VSSA_DAC_BG
1
1 R402 2 0R0402-PAD
C443 SCD1U10V2KX-4GP
1D05V_RUN_PEGPLL
2
220ohm 100MHz
C450 SC10U6D3V5MX-3GP
L16 1 2 BLM18BB221SN1D-GP
C384 SCD1U10V2KX-4GP
1 2
+1.05V_VCCP
A25 B25
720mA
C391 SC10U6D3V5MX-3GP
DY
M_VCCA_DAC_BG
+1.5V_RUN
M_VCCA_MPLL
120ohm 100MHz
VCCA_CRT_DAC VCCA_CRT_DAC
M_VCCA_MPLL
C140 SC22U6D3V5MX-2GP
L11 1 2 FCM1608KF-1-GP
C387 SCD1U10V2KX-4GP
1 2
120ohm 100MHz
C393 SC4D7U6D3V3KX-GP
M_VCCA_HPLL
B27 A26
1
1 R403 2 0R0402-PAD
L12 1 2 FCM1608KF-1-GP
C436 SC1U10V3KX-3GP
C423 SCD1U10V2KX-4GP
+1.8V_SUS
R351 0R0603-PAD
8 OF 10
U52H
PLL
2
SB
2
1 2
2
1 R390 2 0R0603-PAD
1
1
C439 SCD1U10V2KX-4GP
2
1
C444 SCD1U16V2KX-3GP
1 2
+1.05V_VCCP
+3.3V_CRT_LDO
DY
+1.05V_VCCP
3D3V_CRTDAC_S0
64.8mA
C448 SCD1U16V2KX-3GP
M_VCCA_DPLLB
C434 SCD01U16V2KX-3GP
1 R394 2 0R0603-PAD
2
2
+3.3V_CRT_LDO
C427 SCD01U16V2KX-3GP
1
C187 SCD1U10V2KX-4GP
2
1
C188 SCD1U16V2KX-3GP
1
C189 SCD1U16V2KX-3GP
2
DY
73mA
1 R408 2 0R0603-PAD
1
1
M_VCCA_DPLLA
D
B
2
SSID = MCH
1 R152 2 0R0603-PAD
C
3
C185 SCD1U10V2KX-4GP
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Cantiga-Power/Filter(5/6)
Size Document Number Custom
Date: Monday, July 27, 2009
Sheet
Rev
-3
Roberts 12
of
59
5
4
3
2
1
+1.05V_VCCP 2
SSID = MCH
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1
VSS VSS VSS VSS
U24 U28 U25 U29 AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17
VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB
BH48 BH1 A48 C1 A3
4 3
LDDC_CLK LDDC_DATA
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK
M33 K33 J33
L_CTRL_DATA L_DDC_CLK L_DDC_DATA
M29 C44 B43 E37 E38 C41 C40 B37 A37
L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK
VGA_TXAOUT0VGA_TXAOUT1VGA_TXAOUT2-
H47 E46 G40 A40
LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3
VGA_TXAOUT0+ VGA_TXAOUT1+ VGA_TXAOUT2+
H48 D45 F40 B40
LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3
VGA_TXBOUT0VGA_TXBOUT1VGA_TXBOUT2-
A41 H38 G37 J37
LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3
VGA_TXBOUT0+ VGA_TXBOUT1+ VGA_TXBOUT2+
B42 G38 F37 K37
LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3
F25 H25 K25
TVA_DAC TVB_DAC TVC_DAC
H24
TV_RTN
C31 E32
TV_DCONSEL_0 TV_DCONSEL_1
L_CTRL_DATA L_CTRL_CLK
1 2
LDDC_CLK LDDC_DATA LCDVDD_EN
SRN2K2J-1-GP R144 2
1 2K37R2F-GP 1 TP225
LIBG LVDS_VBG
VGA_TXACLKVGA_TXACLK+ VGA_TXBCLKVGA_TXBCLK+
R389 1 R386 1 R385 1
M_GREEN M_RED
GMCH_HSYNC
CRT_IREF routing Trace width use 20 mil. GMCH_VSYNC
E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48
L32 G32 M32
4 3
SRN10KJ-5-GP
RN19 1 2
M_BLUE
VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF
NC#E1 NC#D2 NC#C3 NC#B4 NC#A5 NC#A6 NC#A43 NC#A44 NC#B45 NC#C46 NC#D47 NC#B47 NC#A46 NC#F48 NC#E48 NC#C48 NC#B48
RN41 +3.3V_RUN +3.3V_RUN
GMCH_GND11 GMCH_GND21 GMCH_GND31 GMCH_GND41
TP103 TP80 TP226 TP78
3 OF 10
U52C
LBKLT_CTL GMCH_BL_ON
2 75R2F-2-GP 2 75R2F-2-GP 2 75R2F-2-GP
TV_DACA TV_DACB TV_DACC
M_BLUE 2 150R2F-1-GP M_GREEN 2 150R2F-1-GP M_RED 150R2F-1-GP 2
R376 1 R379 1 R381 1
R133 49D9R2F-GP 1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
1 R123
GMCH_DDCCLK GMCH_DDCDATA 2 GMCH_HS 33R2J-2-GP
1 R124
2
CRT_IREF 1K02R2F-1-GP
1 R392
2
GMCH_VS 33R2J-2-GP
E28
CRT_BLUE
G28
CRT_GREEN
J28
CRT_RED
G29
CRT_IRTN
H32 J32 J29 E29 L29
CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
GRAPHICS
VSS
VSS NCTF
BA16 AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13
VSS
VSS SCB
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
PEG_CMP
PEG_COMPI PEG_COMPO
T37 T36
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46
PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46
VGA
A
BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17
TV
B
10 OF 10
U52J AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6
LVDS
C
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
NC
D
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
PCI-EXPRESS
9 OF 10
U52I AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36
Place R105 close to MCH within 500 mils.
D
C
B
CANTIGA-GM-GP-U-NF
NCTF PIN
+3.3V_RUN RN2 +3.3V_RUN
3 4
2 1 SRN2K2J-1-GP
U4 GMCH_DDCDATA
DDC_CLK_CON
DDC_CLK_CON
4
3
5
2
6
1 2N7002SPT
DDC_DATA_CON
DDC_DATA_CON
GMCH_DDCCLK
5V @ ext. CRT side
A
Wistron Corporation
CANTIGA-GM-GP-U-NF
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
CANTIGA-GM-GP-U-NF Title
Cantiga-GND/LVDS/VGA(6/6)
Size Document Number Custom
Date: Tuesday, August 11, 2009
Sheet
Rev
-3
Roberts 13
of
59
5
4
3
2
1
DM2
1
TC8 ST220U2D5VBM-LGP
DY 2
1
C106 SCD1U16V2KX-3GP
2
1
C100 SCD1U16V2KX-3GP
2
1
C109 SCD1U16V2KX-3GP
2
1
C93 SCD1U16V2KX-3GP
DY 2
1 2
2
DY
C116 SC2D2U10V3KX-1GP
1
C138 SC2D2U10V3KX-1GP
1
DY 2
1 2
C122 SC2D2U10V3KX-1GP
1
C132 SC2D2U10V3KX-1GP
2
C
C160 SC2D2U10V3KX-1GP
Layout Note: Place near DM1
+1.8V_SUS
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V_DDR_VTT.
1 2
C420 SCD1U16V2KX-3GP
1 2
C428 SCD1U16V2KX-3GP
1 2
2
C115 SCD1U16V2KX-3GP
1
C119 SCD1U16V2KX-3GP
1
C118 SCD1U16V2KX-3GP
DY 2
1
C114 SCD1U16V2KX-3GP
DY 2
1
C87 SCD1U16V2KX-3GP
2
1
DY 2
2
DY
C432 SCD1U16V2KX-3GP
1
C83 SCD1U16V2KX-3GP
1 2
2
DY
C96 SCD1U16V2KX-3GP
1
C103 SCD1U16V2KX-3GP
1
C409 SCD1U16V2KX-3GP
2
1
DY 2
B
C101 SCD1U16V2KX-3GP
+0.9V_DDR_VTT
A
13 31 51 70 131 148 169 188
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
M_ODT0 M_ODT1
114 119
OTD0 OTD1
1 2
DY
C202 SC2D2U10V3KX-1GP
4
3
195 197
ICH_SMBDATA ICH_SMBCLK
VDDSPD
199
SA0 SA1
198 200
NC#50 NC#69 NC#83 NC#120 NC#163/TEST
50 69 83 120 163
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
81 82 87 88 95 96 103 104 111 112 117 118
VREF VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
202
GND
GND
201
MH1
MH1
MH2
MH2
SKT-SODIMM200-37GP 5
SDA SCL
D
-1
ICH_SMBDATA ICH_SMBCLK +3.3V_RUN
1 R55 1 R56
1
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
C195 DUMMY-C2
DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
10 26 52 67 130 147 170 185
2
11 29 49 68 129 146 167 186
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
1
M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
M_CLK_DDR1 M_CLK_DDR#1
C192 DUMMY-C2
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
CK1 CK1#
M_CLK_DDR1 M_CLK_DDR#1
2
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
M_CLK_DDR0 M_CLK_DDR#0
164 166
1
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
M_CLK_DDR0 M_CLK_DDR#0
C74 DUMMY-C2
BA0 BA1
30 32
2
107 106
CK0 CK0#
1
M_A_BS#0 M_A_BS#1
1
M_ODT0 M_ODT1
2
C203 SCD1U16V2KX-3GP
2
1
+V_DDR_MCH_REF
M_A_BS#2
M_CKE0 M_CKE1
+3.3V_RUN
2 0R0402-PAD 2 0R0402-PAD PM_EXTTS#0
+1.8V_SUS
1
M_A_BS#0 M_A_BS#1
79 80
C53 SC2D2U10V3KX-1GP
M_A_BS#2 M_A_A[14..0]
M_CS0# M_CS1#
CKE0 CKE1
put near connector M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1
DY 2
M_A_DQS[7..0]
CS0# CS1#
110 115
M_A_RAS# M_A_WE# M_A_CAS#
C72 DUMMY-C2
M_A_DM[7..0]
108 109 113
2
D
RAS# WE# CAS#
1
M_A_DQ[63..0]
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2
C54 SCD1U16V2KX-3GP
M_A_DQS#[7..0]
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85
2
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14
SSID = MEMORY
C
Layout Note: Place these resistors close to DM1, all trace length Max=1.5". +0.9V_DDR_VTT RN37 M_A_A9 M_A_A12
1 2
RN6 4 3
4 3
SRN56J-4-GP
4 3
RN35 1 2
4 3
SRN56J-4-GP
4 3
M_A_A5 M_A_A8
1 2 SRN56J-4-GP
RN4 M_ODT0 M_CS0#
M_A_A13
SRN56J-4-GP
RN31 M_A_A10 M_A_BS#0
1 2
RN10 1 2
4 3
M_A_A6 M_A_A2
1 2
B
SRN56J-4-GP
SRN56J-4-GP
RN12 M_CKE1 M_A_A14
4 3
RN33 1 2
4 3
SRN56J-4-GP
SRN56J-4-GP
RN29 M_A_WE# M_A_CAS#
4 3
RN39 1 2
1 2
SRN56J-4-GP
4 3
M_A_A11 M_A_A7
4 3
M_CKE0 M_A_BS#2
4 3 SRN56J-4-GP
RN28 M_CS1# M_ODT1
M_A_A1 M_A_A3
1 2
RN8 1 2
4 3
SRN56J-4-GP
M_A_BS#1 M_A_RAS#
1 2 SRN56J-4-GP
RN11
RN17 1 2
SRN56J-4-GP
4 3
M_A_A0 M_A_A4
1 2 SRN56J-4-GP
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DDRII-SODIMM SLOT1
Size Document Number Custom
Date: Tuesday, August 11, 2009
62.10017.E21 2
Sheet 1
Rev
-3
Roberts 14
of
59
5
4
3
2
1
DM1
1
TC4 ST220U2D5VBM-LGP
DY 2
1
C131 SCD1U16V2KX-3GP
2
1
C104 SCD1U16V2KX-3GP
2
1
C150 SCD1U16V2KX-3GP
2
1
C124 SCD1U16V2KX-3GP
2
1 2
C105 SC2D2U10V3KX-1GP
1 2
1
1 2
2
DY
C102 SCD1U16V2KX-3GP
1
C404 SCD1U16V2KX-3GP
1 2
C88 SCD1U16V2KX-3GP
1
C117 SCD1U16V2KX-3GP
DY 2
1
C410 SCD1U16V2KX-3GP
2
1
C95 SCD1U16V2KX-3GP
2
1
C405 SCD1U16V2KX-3GP
2
1 2
C406 SCD1U16V2KX-3GP
1 2
2
DY
C414 SCD1U16V2KX-3GP
1
C418 SCD1U16V2KX-3GP
1 2
C425 SCD1U16V2KX-3GP
1
C415 SCD1U16V2KX-3GP
2
1
C430 SCD1U16V2KX-3GP
2
DY
DY
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V_DDR_VTT.
+0.9V_DDR_VTT
B
C112 SC2D2U10V3KX-1GP
2
DY
2
1
C97 SC2D2U10V3KX-1GP
1 2
C136 SC2D2U10V3KX-1GP
C
C107 SC2D2U10V3KX-1GP
Layout Note: Place near DM2
+1.8V_SUS
5
4
2 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
GND
GND
202
50 69 83 120 163
NC#50 NC#69 NC#83 NC#120 NC#163/TEST
110 115 79 80 108 113 109
CS0# CS1# CKE0 CKE1 RAS# CAS# WE#
ICH_SMBCLK ICH_SMBDATA
197 195
SCL SDA
M_ODT2 M_ODT3
114 119
ODT0 ODT1
1 C200 SCD1U16V2KX-3GP
201
C201 SC2D2U10V3KX-1GP
+3.3V_RUN
2 0R0402-PAD 2 0R0402-PAD +3.3V_RUN
+3.3V_RUN
+1.8V_SUS
EC12 SCD1U25V3KX-GP
DY
C
Layout Note: Place these resistors close to DM2, all trace length Max=1.5". +0.9V_DDR_VTT RN7 M_B_WE# M_B_CAS#
4 3
RN27 1 2
4 3
SRN56J-4-GP
4 3
RN38 1 2
4 3
SRN56J-4-GP
M_B_BS#1 M_B_A0
4 3
RN36 1 2
4 3
SRN56J-4-GP
RN32
RN34 1 2
4 3
SRN56J-4-GP
4 3
4 3
RN30 1 2
4 3
SRN56J-4-GP
4 3
M_B_RAS# M_CS2#
1 2 SRN56J-4-GP
RN40 M_CKE3
M_B_A10 M_B_BS#0
1 2 SRN56J-4-GP
RN5 4 3
M_B_A4 M_B_A2
1 2
RN9 1 2
SRN56J-4-GP M_ODT3 M_CS3#
B
SRN56J-4-GP
RN15 M_B_A1 M_B_A3
M_B_A7 M_B_A6
1 2
SRN56J-4-GP
4 3
M_B_A14 M_B_A11
1 2 SRN56J-4-GP
RN16 M_B_A5 M_B_A8
M_ODT2 M_B_A13
1 2 SRN56J-4-GP
RN13 M_B_BS#2 M_CKE2
RN14 1 2
4 3
SRN56J-4-GP
M_B_A12 M_B_A9
1 2 SRN56J-4-GP
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DDRII-SODIMM SLOT2
Size Document Number Custom
SKT-SODIMM200-38GP 62.10017.E31 3
1
VREF
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
C197 DUMMY-C2
81 82 87 88 95 96 103 104 111 112 117 118
2
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
1
199
C193 DUMMY-C2
VDD_SPD
2
1 R57 1 R54
-1 M_CLK_DDR2 M_CLK_DDR#2 M_CLK_DDR3 M_CLK_DDR#3
1
198 200
1
SA0 SA1
C75 DUMMY-C2
M_CLK_DDR2 M_CLK_DDR#2 M_CLK_DDR3 M_CLK_DDR#3
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
2
30 32 164 166
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
1
CK0 CK0# CK1 CK1#
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
1
M_ODT2 M_ODT3
2
2
1
+V_DDR_MCH_REF
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
BA0 BA1
M_CS2# M_CS3# M_CKE2 M_CKE3 M_B_RAS# M_B_CAS# M_B_WE# ICH_SMBCLK ICH_SMBDATA
10 26 52 67 130 147 170 185
107 106
PM_EXTTS#1
A
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
M_B_BS#0 M_B_BS#1
2
M_B_BS#0 M_B_BS#1
M_B_BS#2
D
C56 SC2D2U10V3KX-1GP
M_B_BS#2
put near connector M_CLK_DDR2 M_CLK_DDR#2 M_CLK_DDR3 M_CLK_DDR#3
1
M_B_A[14..0]
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
2
M_B_DQS[7..0]
13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186
C52 SCD1U16V2KX-3GP
M_B_DM[7..0]
MH2
C71 DUMMY-C2
M_B_DQ[63..0]
MH2 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2
2
M_B_DQS#[7..0] D
MH1
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85
1
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14
2
MH1
SSID = MEMORY
Date: Tuesday, August 11, 2009 2
Sheet 1
Rev
-3
Roberts 15
of
59
5
4
3
2
+3.3V_RUN
U25B D11 C8 D9 E12 E9 C9 E10 B7 C7 C5 G11 F8 F11 E7 A3 D2 F10 D5 D10 B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3
5 OF 6 U25E
A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29
5 PLT_RST#
PLT_RST#
B
1
A
2
GND
3
VCC
4
DY
Y
PCI_PLTRST#
74LVC1G08GW-1-GP 1 R262 2 0R0402-PAD
+3.3V_RUN R245
R240 10KR2J-3-GP
1
10KR2J-3-GP
DY
U27 SPI_WP# SPI_MOSO SPI_CS#0
4 3 2 1
GND SI WP# SCLK SO HOLD# CS# VCC
DY
SPI_MOSI SPI_CLK SPI_HOLD#
5 6 7 8
DY 2
DY
2 1
1
C315 SCD1U16V2KX-3GP
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
MX25L512MC-12G-GP
J5 E1 J6 C4
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55
PCI
F1 G4 B6 A7 F13 F12 E6 F6
PCI_REQ0# PCI_GNT0# PCI_REQ1# PCI_GNT1# PCI_REQ2# PCI_GNT2# PCI_REQ3# PCI_GNT3#
RN57
1
PCI_PIRQF# PCI_TRDY# PCI_REQ3# PCI_PIRQD#
TP179
1
1 2 3 4 SRN8K2J-4-GP
TP261
RN25 PCI_PIRQB# PCI_PIRQG# PCI_REQ0# PCI_PIRQH#
C/BE0# C/BE1# C/BE2# C/BE3#
D8 B4 D6 A5
IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME#
D3 E3 R1 C6 E4 C2 J4 A4 F5 D7
PCI_IRDY#
PLTRST# PCICLK PME#
C14 D4 R2
PCI_PLTRST#
8 7 6 5
1 2 3 4
D
SRN8K2J-4-GP
PCIRST1# 1 PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#
RN26 TP135
PCI_STOP# PCI_PLOCK# PCI_IRDY# PCI_PERR#
8 7 6 5
PCI_DEVSEL# PCI_REQ1# PCI_FRAME# PCI_REQ2#
8 7 6 5
1 2 3 4 SRN8K2J-4-GP RN58
ICH_PME#
CLK_PCI_ICH
1
TP138
1 2 3 4 SRN8K2J-4-GP
Interrupt I/F PIRQA# PIRQB# PIRQC# PIRQD#
PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
RN56 H4 K6 F2 G2
PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
PCI_SERR# PCI_PIRQE# PCI_PIRQA# PCI_PIRQC#
8 7 6 5
1 2 3 4 SRN8K2J-4-GP C
RP1 USB_OC#7 USB_OC#11 USB_OC#5 USB_OC#4 +3.3V_ALW
PCI_GNT0# 1 R442 SPI_CS#1 1 R443 PCI_GNT3# 1 R441
RN55
1 2 3 4 5
10 9 8 7 6
+3.3V_ALW
USB_OC#0 USB_OC#1 USB_OC#6 USB_OC#2
8 7 6 5
+3.3V_ALW
1 2 3 4
USB_OC#9 USB_OC#8 USB_OC#10 USB_OC#3
SRN8K2J-4-GP
DY DY
2
DY
2
2
1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP
BOOT BIOS Strap
SRN10KJ-L3-GP
PCI_GNT#0
SPI_CS#1
BOOT BIOS Location
4 OF 6 U25D
New Card
C500 2 C497 2
1 SCD1U16V2KX-3GP 1 SCD1U16V2KX-3GP
PCIE_C_TXN2 PCIE_C_TXP2
PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3
C506 2 C510 2
1 SCD1U16V2KX-3GP 1 SCD1U16V2KX-3GP
PCIE_C_TXN3 PCIE_C_TXP3
J29 J28 K27 K26
PERN3 PERP3 PETN3 PETP3
G29 G28 H27 H26
PERN4 PERP4 PETN4 PETP4
E29 E28 F27 F26
PERN5 PERP5 PETN5 PETP5
PCIE_RXN5 PCIE_RXP5 PCIE_TXN5 PCIE_TXP5
C518 2 C517 2
1 SCD1U16V2KX-3GP 1 SCD1U16V2KX-3GP
PCIE_C_TXN5 PCIE_C_TXP5
C29 C28 D27 D26 SPI_CLK SPI_CS#0 SPI_MOSI SPI_MOSO
ICH_GND1 1 ICH_GND2 1 ICH_GND3 1 ICH_GND4 1
R233 1 R241 1 R230 1 R237 1
DY DY
2 15R2J-GP 2 15R2J-GP
DY DY
2 15R2J-GP 2 15R2J-GP
TP178
NCTF PIN TP125 TP127 R208 1
D23 D24 F23
SPI_MOSI_R SPI_MOSO_R
D25 E23
USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11
USB_OC#0 USB_OC#1 USB_OC#2
TP177
SPI_CLK_R SPI_CS#0_R SPI_CS#1
2
22R2F-1-GP
N4 N5 N6 P6 M1 N2 M4 M3 N3 N1 P5 P3
USB_RBIAS_PN AG2 AG1
V27 V26 U29 U28
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0
DMI1RXN DMI1RXP DMI1TXN DMI1TXP
Y27 Y26 W29 W28
DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1
DMI2RXN DMI2RXP DMI2TXN DMI2TXP
AB27 AB26 AA29 AA28
DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2
DMI3RXN DMI3RXP DMI3TXN DMI3TXP
AD27 AD26 AC29 AC28
DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
T26 T25
CLK_PCIE_ICH# CLK_PCIE_ICH
DMI_CLKN DMI_CLKP
DMI_ZCOMP DMI_IRCOMP
PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP
USBP0N USBP0P USBP1N USBP1P SPI_CLK USBP2N SPI_CS0# USBP2P SPI_CS1#/GPIO58/CLGPIO6 USBP3N USBP3P SPI_MOSI USBP4N SPI_MISO USBP4P USBP5N OC0#/GPIO59 USBP5P OC1#/GPIO40 USBP6N OC2#/GPIO41 USBP6P OC3#/GPIO42 USBP7N OC4#/GPIO43 USBP7P OC5#/GPIO29 USBP8N OC6#/GPIO30 USBP8P OC7#/GPIO31 USBP9N OC8#/GPIO44 USBP9P OC9#/GPIO45 USBP10N OC10#/GPIO46 USBP10P OC11#/GPIO47 USBP11N USBP11P USBRBIAS USBRBIAS#
USB
AF29 AF28 AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2
USB_PN5 1 USB_PP5 1
USB_PN8 1 USB_PP8 1 USB_PN9 1 USB_PP9 1 USB_PN10 USB_PP10
SPI
1
0
PCI
1
1
LPC(Default)
A16 swap override strap PCI_GNT#3
low = A16 swap override enable high = default
B
+1.5V_RUN
R429 24D9R2F-L-GP
DMI_IRCOMP_R
USB_PN3 1 USB_PP3 1
1
2
PERN2 PERP2 PETN2 PETP2
L29 L28 M27 M26
DMI0RXN DMI0RXP DMI0TXN DMI0TXP
0
USB Pair 0
USB1
1
USB2
2
USB3
USB_PN0 USB_PP0 USB_PN1 USB_PP1 USB_PN2 USB_PP2 TP246 TP247 USB_PN4 USB_PP4 TP250 TP251 USB_PN6 USB_PP6 USB_PN7 USB_PP7 TP248 TP249 TP252 TP253 USB_PN10 USB_PP10 USB_PN11 USB_PP11
USB1 USB2 USB3
BlUETOOTH New Card
3
RESERVED
4
MINI CARD
5
RESERVED
6
BLUETOOTH
7
NEW CARD
8
RESERVED
9
RESERVED
10
Card Reader
11
CAMERA
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Card Reader CAMERA Title
ICH9-PCI/PCIE/DMI/USB/GND(1/4) Rev
Size Document Number Custom
ICH9M-GP-NF
3
A
Date: Tuesday, August 11, 2009 4
Device
1
LAN
PERN1 PERP1 PETN1 PETP1
PCI-Express
Mini Card
N29 N28 P27 P26 PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2
ICH9M-GP-NF
5
8 7 6 5
ICH9M-GP-NF
Direct Media Interface
B
H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25
SPI
C
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
2
D
U32
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
+3.3V_RUN
2 OF 6
SSID = ICH AA26 AA27 AA3 AA6 AB1 AA23 AB28 AB29 AB4 AB5 AC17 AC26 AC27 AC3 AD1 AD10 AD12 AD13 AD14 AD17 AD18 AD21 AD28 AD29 AD4 AD5 AD6 AD7 AD9 AE12 AE13 AE14 AE16 AE17 AE2 AE20 AE24 AE3 AE4 AE6 AE9 AF13 AF16 AF18 AF22 AH26 AF26 AF27 AF5 AF7 AF9 AG13 AG16 AG18 AG20 AG23 AG3 AG6 AG9 AH12 AH14 AH17 AH19 AH2 AH22 AH25 AH28 AH5 AH8 AJ12 AJ14 AJ17 AJ8 B11 B14 B17 B2 B20 B23 B5 B8 C26 C27 E11 E14 E18 E2 E21 E24 E5 E8 F16 F28 F29 G12 G14 G18 G21 G24 G26 G27 G8 H2 H23 H28 H29
1
2
-3
Roberts Sheet 1
16
of
59
5
4
3
2
1
SSID = ICH ICH_RTCX1 R445 1
2 10MR2J-L-GP
ICH_RTCX2
X4 1
3
2
2
1
4 1 C522 SC12P50V2JN-3GP
2
D
D
C520 SC12P50V2JN-3GP
X-32D768KHZ-38GPU
LPC_LAD[0..3]
1 OF 6 +RTC_CELL
ICH_RTCRST# SRTCRST# SM_INTRUDER#
A25 F20 C22
RTCRST# SRTCRST# INTRUDER#
ICH_INTVRMEN LAN100_SLP
B22 A22
INTVRMEN LAN100_SLP
E25
GLAN_CLK
C13
LAN_RSTSYNC
R461 2 1
1
C526 SC1U10V3KX-3GP
2
20KR2F-L-GP
C
+1.5V_RUN
R506
Place within 500 mil of SB. R444 1 R201 R197 R205 R194
ICH_AZ_CODEC_BITCLK ICH_AZ_CODEC_SYNC ICH_AZ_CODEC_RST# ICH_SDOUT_CODEC
1 1 1 1
1
DY
10KR2J-3-GP GLAN_COMP
2 24D9R2F-L-GP 33R2J-2-GP 33R2J-2-GP 33R2J-2-GP 33R2J-2-GP
2 2 2 2
2GPIO56
HDD B
ODD
C473 1 C474 1
SATA_RXN1_C SATA_RXP1_C SATA_TXN1 SATA_TXP1
C475 1 C476 1
2 SCD01U50V2KX-1GP 2 SCD01U50V2KX-1GP
2 SCD01U50V2KX-1GP 2 SCD01U50V2KX-1GP
GLAN_DOCK#/GPIO56
B28 B27
GLAN_COMPI GLAN_COMPO HDA_BIT_CLK HDA_SYNC HDA_RST#
SATA_LED#
SATA_RXN0_C SATA_RXP0_C SATA_TXN0 SATA_TXP0
B10
AE7
ACZ_SDATAOUT_R
TP235
LAN_TXD0 LAN_TXD1 LAN_TXD2
AF6 AH4
C230 SC4D7P50V2CN-1GP
1
D13 D12 E13
ACZ_RST#_R
1
DY 2
1 2
DY
LAN_RXD0 LAN_RXD1 LAN_RXD2
ACZ_BIT_CLK ACZ_SYNC_R
ICH_SDIN_CODEC C227 SC4D7P50V2CN-1GP
F14 G13 D14
SATA_TXN0_C SATA_TXP0_C
SATA_TXN1_C SATA_TXP1_C
AF4 AG4 AH3 AE5
HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3
AG5
HDA_SDOUT
AG7 AE8
HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34
AG8
SATALED#
AJ16 AH16 AF17 AG17
SATA0RXN SATA0RXP SATA0TXN SATA0TXP
AH13 AJ13 AG14 AF14
SATA1RXN SATA1RXP SATA1TXN SATA1TXP
IHDA
1 +RTC_CELL
SATA
2
1
G49 GAP-OPEN
LAN / GLAN CPU
RTCX1 RTCX2
ICH_RTCRST#
2
20KR2F-L-GP C307 SC1U10V3KX-3GP
2
1
C23 C24
RTC LPC
U25A R456
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
K5 K4 L6 K2
FWH4/LFRAME#
K3
LDRQ0# LDRQ1#/GPIO23
J3 J1
AJ25 AE23
H_DPRSTP#
FERR#
AJ26
H_FERR#_R
CPUPWRGD
AD22
H_PWRGOOD
IGNNE#
AF25
H_IGNNE#
INIT# INTR RCIN#
AE22 AG25 L3
H_INIT# H_INTR
NMI SMI#
AF23 AF24
H_NMI H_SMI#
THRMTRIP# PECI
AG27
SATA4RXN SATA4RXP SATA4TXN SATA4TXP
AH11 AJ11 AG12 AF12
SATA5RXN SATA5RXP SATA5TXN SATA5TXP
AH9 AJ9 AE10 AF10
SATA_CLKN SATA_CLKP
AH18 AJ18
SATARBIAS# SATARBIAS
AJ7 AH7
DY
2
10KR2J-3-GP
DPRSTP# DPSLP#
AH27
R438 1
N7 AJ27
AG26
+3.3V_RUN
LPC_LFRAME#
A20GATE A20M#
STPCLK#
LPC_LAD[0..3]
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
KA20GATE H_A20M#
+1.05V_VCCP R163 1
H_DPRSTP# H_DPSLP# 1 R166
2
56R2J-4-GP
2 56R2J-4-GP
H_FERR# +3.3V_RUN
C
R242 1
DY
2
10KR2J-3-GP KBRCIN# +1.05V_VCCP R164 1
2 56R2J-4-GP
H_STPCLK# H_THERMTRIP_R
1 R165
2 H_THERMTRIP_1 54D9R2F-L1-GP
Placed Within 2" from SB.
1 R167 2 0R0402-PAD
H_THRMTRIP#
SB A00.08/0903
CLK_PCIE_SATA# CLK_PCIE_SATA SATARBIAS
B
1 R187
2 24D9R2F-L-GP
Place within 500 mils from SB.
ICH9M-GP-NF
+RTC_CELL R448 2
ICH_INTVRMEN
1 330KR2F-L-GP
integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN
A
High=Enable
Low=Disable
A
integrated VccLan1_05VccCL1_05
R271 2
LAN100_SLP
1
LAN100_SLP
High=Enable
Wistron Corporation
Low=Disable
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
330KR2F-L-GP Title
R264 2
SM_INTRUDER#
1
ICH9-LAN/HDA/SATA/LPC(2/4)
Size Document Number Custom
1MR2J-1-GP
Date: Tuesday, August 11, 2009 5
4
3
2
Sheet 1
Rev
-3
Roberts 17
of
59
5
4
3
2
1
SSID = ICH
+3.3V_RUN 3 OF 6
SRN10KJ-5-GP
H_STP_PCI# H_STP_CPU#
SMB_ALERT#
A17
H_STP_PCI# H_STP_CPU#
A14 E19
PCIE_WAKE# INT_SERIRQ
E20 M5 AJ23
L4
PM_CLKRUN# R455 1
2 10KR2J-3-GP
PCIE_WAKE#
RN61 8 7 6 5
SMB_ALERT# PM_BATLOW#_R ITP_DBRESET#_1 ICH_RI#
1 2 3 4 SRN8K2J-4-GP
R451 1
2 10KR2J-3-GP
ECSMI#
PCIE_WAKE# INT_SERIRQ THERM_SCI# VGATE_PWRGD R263 1
DY
2 0R2J-2-GP
TP181 TP168 TP236 TP123 TP184 TP262 CLKSATAREQ#
C
+3.3V_RUN
1 1 1 1 1
DY
H_STP_CPU# H_STP_PCI#
1 2
1
TP124
SST
iTPM_EN
SRN10KJ-5-GP
1 1 2 2 2 2 2
DY
2 2 1 1 1 1 1
8K2R2J-3-GP 8K2R2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 8K2R2J-3-GP 10KR2J-3-GP
PM_CLKRUN# INT_SERIRQ GPIO18 ECSCI# ECSWI# GPIO22 CLKSATAREQ#
1
TP263
ICH_TP3
C10
PWROK
G20
PM_PWROK
AG19 AH21 AG21 A21 C12 C21 AE18 K1 AF8 AJ22 A9 D19 L1 AE19 AG22 AF21 AH24 A8
TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 LAN_PHY_PWR_CTRL/GPIO12 ENERGY_DETECT/GPIO13 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 GPIO27 GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5
M7 AJ24 B21 AH20 AJ20 AJ21
SPKR MCH_SYNC# TP3 PWM0 PWM1 PWM2
DPRSLPVR/GPIO16
PM_SLP_S5#
1 1
M2
BATLOW#
B13
PWRBTN#
R3
LAN_RST#
D20
RSMRST#
D22
D
ICH_SUSCLK PM_SLP_S4# TP259
PM_PWRBTN# LAN_RST#1
R5
CLPWROK
R6
M_PWROK
SLP_M#
B16
PM_SLP_M#
CL_CLK0 CL_CLK1
F24 B19
CL_DATA0 CL_DATA1
F22 C19
CL_VREF0 CL_VREF1
C25 A19
CL_RST0# CL_RST1#
F21 D18
GPIO24/MEM_LED GPIO10/SUS_PWR_ACK GPIO14/AC_PRESENT GPIO9/WOL_EN
A16 C18 C11 C20
DY DY
R427 10KR2J-3-GP
DY DY DY DY DY
2 2 2 2 2
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
1 R439 2 0R0402-PAD
PM_PWROK
TP183 CL_CLK0 C
CL_DATA0 CL_VREF0_ICH CL_VREF1_ICH CL_RST#0 GPIO24 GPIO10 GPIO14
1
+3.3V_ALW TP180 R268 3K24R2F-GP
2
1
1 R185 10KR2J-3-GP
2
2
1 = Enable
2
2
0 = Disable
CLK Gen CLK_SEL0 select
CLK_SEL0 CLK_SEL1
1
iTPM_EN
1
R446 100KR2J-1-GP
DY DY
1 1 1 1 1
10KR2J-3-GP 100KR2J-1-GP 0R0402-PAD 10KR2J-3-GP
+3.3V_RUN
R454 3K24R2F-GP
DY
DY
CLK Gen Select
R423 10KR2J-3-GP
2
1
iTPM_EN
1
2
DY
R501 R502 R503 R504 R505
M_PWROK
M_PWROK 1
+3.3V_RUN
R179 10KR2J-3-GP
GPIO10 GPIO13 GPIO14 GPIO17 GPIO48
DY
2 2 2 2
CK_PWRGD
ICH9M-GP-NF
iTPM Select
1 1 1 1
RSMRST#_KBC
CK_PWRGD
+3.3V_RUN
R449 100KR2J-1-GP
R440 R232 R266 R447
DPRSLPVR PM_BATLOW#_R
DY
B
PM_PWROK DPRSLPVR LAN_RST#1 RSMRST#_KBC
TP182
1
R235 R244 R247 R421 R424 R180 R238
SB_SPKR MCH_ICH_SYNC#
WAKE# SERIRQ THRM# VRMPWRGD
CLK_SEL0 CLK_SEL1 GPIO48
RN63 4 3
CLKRUN#
A20
ECSWI# ECSMI# GPIO12 GPIO13 GPIO17 GPIO18 GPIO20 GPIO22 GPIO27 GPIO28
1
STP_PCI# STP_CPU#
D21
ECSWI# ECSMI#
S4_STATE#/GPIO26
GPIO26
SMBALERT#/GPIO11
ICH_TP7 ECSCI#
SB_SLP_S3#
PMSYNC#/GPIO0
VGATE_PWRGD
ECSCI#
ICH_SUSCLK
C16 E16 G17
1
4 3
1
TP186
P1
2
M6
PM_SYNC# RN59
SUSCLK SLP_S3# SLP_S4# SLP_S5#
1
SUS_STAT#/LPCPD# SYS_RESET#
2
R4 G19
R450 453R2F-1-GP
SUS_STAT# ITP_DBRESET#_1
1
1 2
ME_EC_DATA1 ME_EC_CLK1
1
ITP_DBRESET#_1
C523 SCD1U10V2KX-4GP
LINKALERT#
1 2 3 4 SRN10KJ-6-GP
CLK_14M_ICH CLK_48M_ICH
2
2 10KR2J-3-GP
8 7 6 5
2
TP257 R267 1
H1 AF3
C309 SCD1U10V2KX-4GP
D
CLK14 CLK48
SATA2GP SATA3GP SATA1GP SATA0GP
1
RI#
SATA0GP SATA1GP SATA2GP SATA3GP
1
F19
AH23 AF19 AE21 AD20
2
ICH_RI#
SRN2K2J-1-GP
SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37
R261 453R2F-1-GP
SMB_DATA SMB_CLK
1 2
SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1
SATA GPIO
4 3
G16 A13 E17 C17 B18
Clocks
RN60
LINKALERT# ME_EC_CLK1 ME_EC_DATA1
SYS GPIO Power MGT
SMB_CLK SMB_DATA
MISC GPIO Controller Link
+3.3V_ALW
RN49
SMB
U25C
Disable Seligo Realtek ICS
X 1 1 0
B
CLL_SEL1
X 1 0 1
+3.3V_ALW
U29 SB_SLP_S3#
1
B
2
A
3
VCC
5
Y
4
DY
PM_SLP_S3#
PM_SLP_S3#
GND 74LVC1G08GW-1-GP
+3.3V_RUN
1 R265 2 0R0402-PAD RN62 4 3
1 2 SRN2K2J-1-GP
A
ICH_SMBDATA
SMB_CLK
A
U56 1
6
2
5
3
4
SMB_DATA
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. ICH_SMBCLK
Title
ICH9-GPIO/PM/CL(3/4)
2N7002SPT
Size Document Number Custom
Date: Tuesday, August 11, 2009 5
4
3
2
Sheet 1
Rev
-3
Roberts 18
of
59
5
4
3
+RTC_CELL
3D3V_GLAN_S0
A00.08/0909
F18
0R3J-0-U-GP
VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3
A18 D16 D17 E22
VCCSUS3_3
AF1
VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3
T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7
VCCCL1_05
G22
VCCCL1_5
G23
VCCCL3_3 VCCCL3_3
A24 B24
1
C503 SCD1U10V2KX-4GP
2 1
1 VCCSUS1_5[3]
A27
VCCGLANPLL 23mA
D28 D29 E26 E27
VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5
A26
VCCGLAN3_3 1mA
2 1 R452 2 0R0603-PAD
2 1 2
1 2
C217 SCD1U10V2KX-4GP
2
1
C516 SCD1U10V2KX-4GP
1 2
1
C302 SCD1U10V2KX-4GP
ICH9M-GP-NF
1 2
2
1 2
DY
C221 SCD1U10V2KX-4GP
1 R436 2 0R0603-PAD
A
A00.08/0909
+3.3V_RUN SB_VCCCL3_3
+3.3V_ALW
1
VCCSUS1_05[3]
VCCLAN3_3 78mA VCCLAN3_3
1
VCCLAN1_05 VCCLAN1_05
A12 B12
2
A10 A11
C490 SCD022U16V2KX-3GP
VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A
1 R270 2 0R0603-PAD
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
ICH9-POWER(4/4)
Size Document Number Custom
Date: Monday, July 27, 2009 5
4
3
1 R188 2 0R0402-PAD
DY
1
AA7 AB6 AB7 AC6 AC7
11mA
C509 SCD1U10V2KX-4GP
2 1 2
VCCUSBPLL
1
AJ5
C313 SCD1U10V2KX-4GP
VCC1_5_A VCC1_5_A VCC1_5_A
1
AC12 AC13 AC14
DY
2
VCC1_5_A VCC1_5_A
SB_VCCSUS3_3
C491 SCD1U16V2KX-3GP
VCC1_5_A
G10 G9
C507 SCD1U10V2KX-4GP
308mA
1
AC21
SB_VCCHDA
1
VCC1_5_A VCC1_5_A
+3.3V_RUN +3.3V_ALW
2
AC18 AC19
+1.5V_RUN
1 R177 2 0R0603-PAD
B
C308 SCD1U10V2KX-4GP
VCC1_5_A
2
AC9
2
C515 SCD1U10V2KX-4GP
VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A
R172
DY
1
VCCSUS1_5
TP243 TP260
2
1
VCCSUS1_5[2]
1 1
C231 SC4D7U6D3V3KX-GP
VCCSUS1_5[1]
1
VCCSUS1_5
AD8
+3.3V_ALW 1 R191 2 0R0402-PAD
2
VCCSUS1_05[1] VCCSUS1_05[2]
+3.3V_RUN SB_VCC_3_3_C C223 SCD1U10V2KX-4GP
AC8 F17
1
VCCSUS1_05 VCCSUS1_05
C479 SCD1U10V2KX-4GP
11mA VCCSUSHDA
2
SB_VCCHDA
AJ3
C
1 R437 2 0R0603-PAD
1
AJ4
1 R431 2 0R0603-PAD
+3.3V_RUN
EC56 SCD1U25V3KX-GP
11mA VCCHDA
DY
2
PCI_VCCP_CORE_S0
C477 SCD1U10V2KX-4GP
C478 SCD1U10V2KX-4GP
B9 F9 G3 G6 J2 J7 K7
2
2
1
C252 SC10U6D3V5MX-3GP
VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3
+3.3V_RUN
C232 SC1U10V3KX-3GP
2
1
C265 SC10U6D3V5MX-3GP
1
C263 SCD01U16V2KX-3GP
2 1
AD19 AF20 AG24 AC20
C253 SC4D7U6D3V3KX-GP
1 2
2
C492 SCD1U10V2KX-4GP
1
C495 SCD1U10V2KX-4GP
2
1
C501 SCD1U10V2KX-4GP
1
C496 SCD1U10V2KX-4GP
2
2
C488 SCD1U10V2KX-4GP
1634mA CORE
VCC3_3 VCC3_3 VCC3_3 VCC3_3
SB_V_CPU_IO
C514 SCD1U10V2KX-4GP
SB
1 R453 2 0R0603-PAD
3D3V_VCCPCORE_ICH_S0
+1.05V_VCCP
2
+3.3V_RUN
VCC3_3
AC10
1 R434 2 0R0603-PAD
1 R430 2 0R0603-PAD
C511 SCD1U10V2KX-4GP
C279 SCD1U10V2KX-4GP
1 2
2
DY
AC11 AD11 AE11 AF11 AG10 AG11 AH10 AJ10
80mA
C276 SC4D7U6D3V3KX-GP
SB_VCC_3_3_C
GLAN POWER
1
VCC_GLAN_PLL
AJ6
+1.05V_VCCP
2
+1.5V_RUN
VCC3_3
1
SB_VCCLAN3_3
VCC3_3
SB_V_CPU_IO
C493 SCD1U10V2KX-4GP
C485 SCD1U10V2KX-4GP
1 1
C483 SCD1U10V2KX-4GP
2
1 2
DY
AB23 AC23 AG29
D
+1.5V_RUN L5 2 1 IND-1D2UH-5-GP
C513 SC1U10V3KX-3GP
C521 SCD1U10V2KX-4GP
VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A
A00.08/0909
2
A
VCCDMI
2
1
VCCLAN1D05
VCCSATAPLL47mA
AC16 AD15 AD16 AE15 AF15 AG15 AH15 AJ15
USB CORE
2
DY
C482 SCD1U10V2KX-4GP
1
1D5V_USB_S0 C222 SCD1U10V2KX-4GP
1 R183 2 0R0603-PAD
2
2
1
C480 SCD1U10V2KX-4GP
+1.5V_RUN
DY
1D5V_DMIPLL_ICH_S0
V_CPU_IO
VCCP_CORE
1
C251 SC2D2U10V3KX-1GP C219 SC1U10V3KX-3GP
1 1
C220 SC1U10V3KX-3GP
2
1 2 C312 SC10U6D3V5MX-3GP
1 2
1 2
+1.5V_RUN
DY
2mA V_CPU_IO
1342mA
C303 SC2D2U10V3KX-1GP
L7 2 1 VCC_GLAN_PLL IND-1D2UH-5-GP
AJ19
ATX
C481 SC1U10V3KX-3GP
+1.5V_RUN
+1.5V_RUN
B
2
1 2
C301 SCD1U10V2KX-4GP
1 2
1 2
DY
W23 Y23
VCCDMI
ARX
C306 SCD1U10V2KX-4GP
SB_VCCLAN3_3
C213 SC10U6D3V5MX-3GP
1 2 L-10UH-11-GP 1 R269 2 0R0603-PAD
2
1 2
+VCCSATAPLL L4
R29
50mA VCCDMI
DY
1D5V_DMIPLL_ICH_S0
1
+1.5V_RUN +3.3V_RUN
C244 SC10U6D3V5MX-3GP
1 2
DY
C246 SC10U6D3V5MX-3GP
1
TC9 ST220U2D5VBM-LGP
2
DY
2
1
C512 SCD1U10V2KX-4GP
1 2
DY
23mA VCCDMIPLL
2mA
VCCA3GP
C
C489 SCD1U10V2KX-4GP
+1.5V_RUN
VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B
PCI
2
2
C242 SCD1U16V2KX-3GP
V5REF_SUS
646mA
C304 SC1U10V3KX-3GP
AE1 AA24 AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE25 AE26 AE27 AE28 AE29 F25 G25 H24 H25 J24 J25 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T24 T27 T28 T29 U24 U25 V24 V25 U23 W24 W25 K23 Y24 Y25
A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
VCCPSUS
2 1
2 1
R213 10R2J-2-GP
1
V5REF_S5
+5V_ALW
D14 CH751H-40PT
2 R274 10R2J-2-GP 1
2
+3.3V_ALW
1
1
+5V_RUN
D15 CH751H-40PT
+3.3V_RUN
V5REF 2mA
212mA
V5REF_S5
VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05
VCCRTC
A6
VCCPUSB
V5REF_S0
73mA
1
C525 SCD1U10V2KX-4GP
2
2
1
C524 SCD1U10V2KX-4GP
A23
*Within a given well, 5VREF needs to be up before the corresponding 3.3V rail
V5REF_S0
1
+1.05V_VCCP
U25F
SSID = ICH
D
2
6 OF 6
2
Rev
-3
Roberts Sheet 1
19
of
59
5
4
3
2
1
SSID = LOM +2.5V_LOM
4K7R2J-2-GP
34 35
NC#34 NC#35
36 37
NC#36 NC#37
33 39 44 48 58 2 7 13
64 23 VDD25 AVDDL
VDD VDD VDD VDD VDD VDD VDD VDD PCIE_TXN PCIE_TXP
50 49
PCIE_RXN PCIE_RXP
53 54
LED_LINK# NC#62 LED_SPEED# LED_ACT#
63 62 60 59
XTALI XTALO
15 14
PCIE_WAKE# PLT_RST# CLK_PCIE_LAN CLK_PCIE_LAN# LAN_RXN3 LAN_RXP3
C285 1 C284 1
2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP
LANX1 LANX2
R228 2
1 C
GND
+3.3V_LAN X2 LANX2 1
R236 1
2
LANX1
XTAL-25MHZ-96GP C259 SC12P50V2JN-3GP
2
MDI0+ MDI1+
MDI0+ MDI1+
2VPD_DATA
MDI0MDI1-
DY
10MR2J-L-GP
+3.3V_LAN MDI0MDI1-
PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3
65
18 21 27 31
PU_VDDO_TTL#42 PU_VDDO_TTL#43
HSDACP HSDACN
42 43
24 25
TSTPT TESTMODE
LANHP LANHN
RXN TXN NC#27 NC#31
1 1
29 46
TP136 TP139
C
VPD_DATA VPD_CLK
DY DY
LANSC LANPWR LANSV LANRSET CTRL12 CTRL25
41 38
A00.08/0903
1 R246 2 0R0402-PAD R221 1 2 2KR2F-3-GP R243 1 2 10KR2J-3-GP R239 1 2 10KR2J-3-GP
LOM_DISABLE# VAUX_AVLBL SWITCH_VCC VMAIN_AVLBL SWITCH_VAUX RSET PD_12 PD_25
RXP TXP NC#26 NC#30
+3.3V_LAN
1
10 12 11 47 9 16 3 4
17 20 26 30
LOM_DISABLE# 1
6 5 55 56
88E8040-A0-NNC1C000-GP
+3.3V_LAN
TP145 +3.3V_RUN TP147
WAKE# PERST# REFCLKP REFCLKN
1
1
2
R229
1
+3.3V_LAN
VDDO_TTL VDDO_TTL VDDO_TTL VDDO_TTL VDDO_TTL
1 8 40 45 61
57 52 51 32 28 22 19
D
AVDDL AVDD AVDD AVDDL AVDDL AVDDL AVDDL
U26
2
+1.2V_LOM
1 1
TP270 TP269
D
+3.3V_LAN
C260 SC12P50V2JN-3GP
C268 1
2 SC1KP50V2KX-1GP
C283 1
2 SC1U10V3KX-3GP
C281 1
2 SC1U10V3KX-3GP
2
4K7R2J-2-GP R231
R234
DY0R2J-2-GP
1
+2.5V_LOM 2
1
4K7R2J-2-GP
C257 1
2 SCD1U10V2KX-4GP
C258 1
2 SC1KP50V2KX-1GP
C255 1 C288 1
2 SC1KP50V2KX-1GP SC4D7U6D3V5KX-3GP 2 SC1U10V3KX-3GP
C291 1
2
B
B
+1.2V_LOM +3.3V_LAN
+3.3V_RUN
R507 R248
1
DY
2 0R3J-0-U-GP
1
DY
2 0R3J-0-U-GP
Q14 S
C286 SC10U6D3V5MX-3GP
1 2
C271 SC4D7U6D3V5KX-3GP
1 2
1
C290 SC4D7U6D3V5KX-3GP
2
1
C266 SCD1U10V2KX-4GP
2 Q15 2N7002-7F-GP
2
1
AO3403-GP
C269 SCD1U10V2KX-4GP
G
MDI0+
2 D
1
C296 SCD1U10V2KX-4GP
2
D
G
R257 10KR2J-3-GP
A
MDI0MDI1+ MDI1-
1 R222 1 R223 1 R225 1 R224
DY DY DY DY
MDIS0_LAN 49D9R2F-GP
1 C247
DY
49D9R2F-GP 2 MDIS1_LAN 49D9R2F-GP 2 49D9R2F-GP
1 C248
DY2SCD01U16V2KX-3GP
2
2 SC1U10V3KX-3GP
C267 1
2 SC1KP50V2KX-1GP
C282 1
2 SC1U10V3KX-3GP
C270 1
2 SC1KP50V2KX-1GP
C292 1
2 SC1U10V3KX-3GP
C261 1
2 SC1KP50V2KX-1GP
C278 1
2 SC4D7U6D3V5KX-3GP
2 SCD01U16V2KX-3GP
2
A
G
Wistron Corporation
S
PM_LAN_ENABLE
D
1
+3.3V_ALW
C264 1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
LAN Marvell-88E8040
Size Document Number Custom
Date: Tuesday, August 11, 2009 5
4
3
2
Sheet 1
Rev
-3
Roberts 20
of
59
5
4
3
2
1
SSID = SDIO Please close to pin8. +3.3V_PHY D
1 R259 2 0R0603-PAD
+3.3V_PHY 2
MODE_SEL
R283 499KR2F-1-GP
45 36 14 2 44
A00.08/1002 A00.08/0902 5 4
USB_PP10 USB_PN10
XTAL_CTR
13
XTAL_CTR
XTLO XTLI
47 48
EESK EECS
17 16
CARD_EESK CARD_EECS
EEDO EEDI
15 18
CARD_EEDO CARD_EEDI
DP DM
R510 1
DY
C318 SC1U10V2KX-1GP
2
PLT_RST#
2K2R2J-2-GP C568 SC1U10V2KX-1GP
2
DY
MODE_SEL SD_CMD GPIO0 RREF RST#
33 11 D3V3 D3V3
10
1
8 3V3_IN
VREG
AV_PLL
A00.08/1002 R272
1
2 10KR2J-3-GP
+3.3V_PHY
C
CLK_48M_CARD
GND GND GND GND 6 12 32 46
NC#30 NC#7 NC#3
RTS5158E-GRT-GP
30 7 3
SP1 SP2 SP3 SP4 SP5 SP6 SP7 SP8 SP9 SP10 SP11 SP12 SP13 SP14 SP15 SP16 SP17 SP18 SP19
CARD_3V3
19 20 21 23 25 26 27 28 29 31 34 35 37 38 39 40 41 42 43
MS_D5 MS_D4
XD_CD# SD_WP SD_CD# XD_D4/SD_DAT1 XD_D5/MS_BS XD_D3/MS_D1 SD_DAT0/XD_D6/MS_D0 XD_D2/MS_D2 MS_INS# XD_D7/MS_D3 SD_CLK/XD_D1/MS_CLK XD_D0 XD_WP# XD_RDY SD_DAT3/XD_WE# SD_DAT2/XD_RE# XD_ALE XD_CE# XD_CLE
24 22
C
U34
9
1 XD_CD# SD_WP SD_CD# XD_D4/SD_DAT1 XD_D5/MS_BS XD_D3/MS_D1 SD_DAT0/XD_D6/MS_D0 XD_D2/MS_D2 MS_INS# XD_D7/MS_D3 SD_CLK/XD_D1/MS_CLK XD_D0 XD_WP# XD_RDY SD_DAT3/XD_WE# SD_DAT2/XD_RE# XD_ALE XD_CE# XD_CLE
2CARD_RST#_R
1
R284 100KR2J-1-GP
1
6K2R2F-GP
DY
R282
2
CARD_RST#
2
1
1
BLM18BD601SN1D-GP
2
C299 SCD1U16V2KX-3GP
SD_CMD
R260 CARD_RREF
1
SD_CMD +3.3V_RUN_CARD
2
Please close to pin11 and pin33.
1
1
C320 SC4D7U6D3V3KX-GP
2
1 2
C300 SCD1U16V2KX-3GP
1
C297 SC1U6D3V2KX-GP
2
1
C298 SC1U6D3V2KX-GP
2
1 2
+3.3V_RUN
VREG
C310 SCD1U16V2KX-3GP
1 2
C319 SCD1U16V2KX-3GP
+3.3V_PHY D
MS_CLK
MS_CLK
L6 DLW21SN900SQ2LUGP
USB_PN10 USB_PP10
1 R250 2 0R0402-PAD
DY
1
1 R249 2 0R0402-PAD
2
DY DY 2
C273 SC15P50V2JN-2-GP
B
USB_PP10
1
SD_CLK
SD_CLK
4
SD_CLK/XD_D1/MS_CLK
3
B
2
1
USB_PN10
C280 SC15P50V2JN-2-GP
Power mode select +3.3V_PHY
No staff R and C for power saving mode.
U33
GND
8 7 6 5
MODE_SEL
DY
A
C311 SCD1U16V2KX-3GP
1
VCC DC
DY ORG
R280 10KR2J-3-GP
DY
DY
Wistron Corporation
C317 SC47P50V2JN-3GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
2
AT93C46DN-SH-B-GP
2
CS SK DI DO
1
1 2 3 4
1
CARD_EECS CARD_EESK CARD_EEDO CARD_EEDI
2
A
Title
Reserve for changing USB VID/PID. Size Document Number Custom
RTS5158E
Date: Tuesday, August 11, 2009 5
4
3
2
Rev
-3
Roberts Sheet 1
21
of
59
5
4
3
2
1
SSID = AUDIO +3.3V_RUN
Place C915 close to pin9 D
2
BITCLK
ICH_SDIN_CODEC
R465 2
1 33R2J-2-GP
SB_AZ_CODEC_SDIN0_R
8
SDI_CODEC SDO
ICH_SDOUT_CODEC
5
ICH_AZ_CODEC_SYNC
10
SYNC
ICH_AZ_CODEC_RST#
11
RESET#
2
DY
AUD_DMIC_IN0
46 2 4
47 48
DMIC_CLK VOL_UP/DMIC_0/GPIO1 VOL_DN/DMIC_1/GPIO2
PORTB_L PORTB_R VREFOUT_B
21 22 28
AUD_EXT_MIC_L AUD_EXT_MIC_R AUD_VREFOUT_B
AUD_EXT_MIC_L AUD_EXT_MIC_R AUD_VREFOUT_B
PORTC_L PORTC_R VREFOUT_C
23 24 29
AUD_INT_MIC_L AUD_INT_MIC_R AUD_VREFOUT_C
C547 1 C549 1 R292 1
PORTD_L PORTD_R
35 36
AUD_LINE_OUT_L AUD_LINE_OUT_R
C560
PORTE_L PORTE_R VREFOUT_E/GPIO4
14 15 31
PORTF_L PORTF_R GPIO3
16 17 30
NC#18 NC#19 NC#20
18 19 20
PCBEEP
12
MONO_OUT
32
CAP2 VREFFILT
33 27
AVSS1 AVSS2
26 42
EAPD/GPIO0/SPDIF_OUT0OR1 SPDIF_OUT0
GPIO5 GPIO6 GPIO7/SPDIF_OUT1
7 49
DVSS GND
2 2
SC1U10V3KX-3GP SC1U10V3KX-3GP 2 4K7R2J-2-GP
1
R473
2
1 39K2R2F-L-GP
AUD_HP1_JD#
R478
2
1 20KR2F-L-GP
EXT_MIC_JD#
C541
2
1 SC1KP50V2KX-1GP
C
INT_MIC_L_R
2 SC1U6D3V2KX-GP AUD_LINE_OUT_L AUD_LINE_OUT_R
Port Port Port Port
A---> B---> C---> D--->
HP Ext Mic Int Mic Speaker
AUD_PC_BEEP Trace width>15 mils PC BEEP
AUD_PC_BEEP
C531 2
AUD_CAP2 AUD_VREFFLT 1
43 44 45
1
AUD_HP1_OUT_L AUD_HP1_OUT_R
2
AUD_HP1_OUT_L AUD_HP1_OUT_R
C532 SC4D7P50V2CN-1GP
AUD_DMIC_CLK AUD_DMIC_IN0
1
39 41 37
2
PORTA_L PORTA_R NC#37
AUD_SENSE_A AUD_SENSE_B
2
B
92HD71B7A5NLGXB3X8-GP
1 SCD1U10V2KX-4GP SB_SPKR_R
R464 499KR2F-1-GP 1 2
From SB SB_SPKR
2
6
1
13 34
R468 DUMMY-C2
B
1
ICH_AZ_CODEC_BITCLK_R
R479 5K1R2F-2-GP
SENSE_A SENSE_B/NC#34
1
1 22R2J-2-GP
R487 20KR2F-L-GP
25 38
C561 SC10U6D3V5MX-3GP
ICH_AZ_CODEC_BITCLK
R463 2
+VDDA
AVDD1 AVDD2
DVDD_CORE DVDD_CORE NC#40/OTP DVDD_IO
2
1 9 40 3
1
C
U61 C529 SCD1U10V2KX-4GP
+VDDA
C558 SC10U6D3V5MX-3GP
1
2
1 R467 2 0R0402-PAD
2
1
+3.3V_RUN
C555 SC1U10V3KX-3GP
+VDDA
C550 SCD1U10V2KX-4GP
1 2
C533 SCD1U10V2KX-4GP
1
C530 SC1U6D3V2KX-GP
2
1 2
D
C537 SCD1U10V2KX-4GP
Place C914 close to pin1
Azalia I/F EMI ICH_SDOUT_CODEC 1
+3.3V_RUN U59
AUD_DMIC_CLK_G
ICH_AZ_CODEC_SDOUT1
EC154 SC22P50V2JN-4GP
5
VCC
4
Y
DY
OE# A GND
1 2 3
74LVC1G125DC-GP R477 2
1 22R2J-2-GP
AUD_DMIC_CLK A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
1
A
2
1
2
DY
R466 47R2J-2-GP
2
DY
Title
C528 SCD1U10V2KX-4GP
AUDIO CODEC 92HD71B7
Size Document Number Custom
Date: Tuesday, August 11, 2009 5
4
3
2
Sheet 1
Rev
-3
Roberts 22
of
59
5
4
3
2
1
SSID = AUDIO +5V_RUN
Signal inverter for speaker shutdown
+5V_SPK_AMP
Close to U24.8
Close to U24.18
+5V_SPK_AMP
+5V_SPK_AMP 1
1
1 2
2
Close to Pin9
1 100KR2J-1-GP
6040
2 AUD_HP1_JD
5
2
AMP_MUTE#
AUD_HP1_JD
6
1
AUD_HP1_EN
9789
AMP_MUTE#
R286 2
97891
R489 10MR2J-L-GP
2N7002SPT
+5V_RUN
100KR2J-1-GP
2
1
C322 SC1U10V3KX-3GP
1 2
1 2
6040
C556 SC1U10V3KX-3GP
+VDDA
C565 SC1U10V3KX-3GP
1
9789
+5V_SPK_AMP
3
AUD_HP1_JD#
From EC
1 0R2J-2-GP
2 SC1U10V3KX-3GP
AUD_HP1_JD#
4
2
R483 2
AUD_BIAS AUD_SET
MAX9789A-GP
AUD_LINE_OUT_R AUD_LINE_OUT_L
1
2 SCD033U16V3KX-GP 2 SCD033U16V3KX-GP
C
C551 1AUD_CPVSS
1
+5V_SPK_AMP
C566
AUD_BIAS
C567
1
AUD_SET
1 SCD033U16V3KX-GP 6040 2 1 SCD033U16V3KX-GP 6040 2 1 SCD1U10V2KX-4GP 9789
KBC_BEEP
10KR2J-3-GP
AUD_HP1_JD#
From EC
3AUD_SPK_ENABLE
1KR2J-1-GP R484
NB_SPK_EN#
1
2
GAIN SETTING
2
BAW56-2-GP
R287 100KR2J-1-GP 2
D17 2
2
R472 KBC_BEEP_R 1
C535 2
R285 100KR2J-1-GP 2
R293 100KR2J-1-GP
AMP_REGEN
+5V_SPK_AMP 1
+VDDA
SC1U10V3KX-3GP
1
2
C548 SC1U6D3V2KX-GP
1
C552 SC10U6D3V5MX-3GP
2
1 2
C562 SCD1U10V2KX-4GP
1
C554 SC1U6D3V2KX-GP
2
1 30
17
VDD
CPVDD
HPVDD
9
18
2 HP_INR HP_INL
21 5
C
26 27
AUD_SPK_ENABLE# AMP_MUTE#_R AUD_HP1_EN AMP_REGEN AMP_C1P C321 1 AMP_C1N
23 25 22 4 10 12 29 24 1
R469 0R2J-2-GP
R488 2K2R2J-2-GP
C544 1 C543 1
2
C557 SC10U6D3V5MX-3GP
AUD_LIN_R AUD_LIN_L
2 3
PVSS
GAIN1 GAIN2
CPVSS
31 32
SPKR_EN# MUTE# HP_EN REGEN C1P C1N VOUT BIAS SET
14
AUD_AMP_GAIN1 AUD_AMP_GAIN2
D
+5V_SPK_AMP
R485 100KR2J-1-GP
R486 2
CPGND
HPR HPL
C546 SC1U6D3V2KX-GP
U36
SPKR_INR SPKR_INL
13
15 16
PVDD
8
AUD_HP1_JACK_R AUD_HP1_JACK_L
SC10U6D3V5MX-3GP 2K2R2J-2-GP C564 R490 1 2 AUD_HP1_OUT_R1 1 2 AUD_HP1_OUT_R2 1 2 AUD_HP1_OUT_L1 1 2 AUD_HP1_OUT_L2
6040B 6040B
OUTL+ OUTLOUTROUTR+
11
AUD_HP1_OUT_R AUD_HP1_OUT_L
6 7 19 20
GND GND
AUD_HP1_JACK_R AUD_HP1_JACK_L
AUD_SPK_L1 AUD_SPK_L2 AUD_SPK_R2 AUD_SPK_R1
PGND PGND
AUD_SPK_L1 AUD_SPK_L2 AUD_SPK_R2 AUD_SPK_R1
PVDD
U62
C553 SC1U6D3V2KX-GP
+5V_SPK_AMP
28 33
1 2
1 2
C545 SCD1U10V2KX-4GP
1
C538 SC10U6D3V5MX-3GP
60ohm 100MHz 3000mA 0.05ohm DC
2
D
2
BLM21PG600SN-1GP
C563 SC1U10V3KX-3GP
L18 1
U35 4
3
AUD_SPK_ENABLE#
5
2
AMP_MUTE#
6
1 2N7002SPT
+5V_SPK_AMP
B
R288 100KR2J-1-GP 2
DY 2
R290 100KR2J-1-GP
1
1
B
AUD_AMP_GAIN2
1
1
AUD_AMP_GAIN1 R291 100KR2J-1-GP
R289 100KR2J-1-GP
Second source
TPA6040A (74.06040.013)
MAX9789A (74.09789.013) G80
R486
2
2
DY
Main source
100K
No ASM
1
A00.08/0922
GAIN1
GAIN2
No ASM
0 Ohm
R469
No ASM
0 Ohm
R286
No ASM
100K
C535
0.033uF
No ASM
C566
0.033uF
No ASM
C565
1uF
No ASM
C567
No ASM
0.1uF
C564
10uF
2.2uF
C557
10uF
2.2uF
GAP-OPEN-PWR G77 1 2
GAIN
0
0
6dB
0
1
10dB
1
0
15.6dB
1
1
21.6dB
A
R483
2
GAP-OPEN-PWR G79 1 2
GAP-OPEN-PWR G78 1 2 GAP-OPEN-PWR
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
AUDIO AMP/SPEAKER
Size Document Number Custom
Date: Tuesday, August 11, 2009 5
4
3
2
Sheet 1
Rev
-3
Roberts 23
of
59
PM_SLP_S3# KBC_PWRBTN# AC_IN# LID_CLOSE#
C
BIOS_ID
A00.08/0902 R182
RUNPWROK_R 2 0R0402-PAD
1
A00.08/0903 AD_OFF RSMRST#_KBC PM_SLP_S4#
A00.08/0903
3V_5V_POK PM_PWROK PSID_DISABLE# HDD_5V_EN BLON_OUT CPUCORE_ON
R158
PM_PWROK_R 2 0R0402-PAD
1
R159
CPUCORE_ON_R 2 0R0402-PADECSMI#_KBC
1
A00.08/0903 USB_PWR_EN#
101 105 106 107
64 95 93 94 119 6 109 120 65 66 16 17 20 21 22 23 24 25 26 27 28 73 74 75 110
GPI94 GPI95 GPI96 GPI97
GPIO01/TB2 GPIO03 GPIO06 GPIO07 GPIO23 GPIO24 GPIO30 GPIO31 GPIO32/D_PWM GPIO33/H_PWM GPIO40/F_PWM GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO45/E_PWM GPIO46/TRST# GPIO47 GPIO50/TDO GPIO51 GPIO52/RDY# GPIO53 GPIO70 GPIO71 GPIO72 GPO82/TRIS#
R150 10KR2J-3-GP
1 2
2
2
DY
R141 10KR2J-3-GP
1
R143 10KR2J-3-GP
1
X00 X01 X02 -1 -2 -3
0 0 0 0 0 1
0 0 1 1 1 0
80
1
THERM_SCL
2
2
1 R417 PLT_RST1#_1
81
GPIO77 GPIO76/SHBM GPIO75 GPIO81
SPI
GPIO
84 83 82 91
GPO83/SOUT_CR/BADDR1 GPIO87/SIN_CR GPO84/BADDR0
111 113 112
GPIO16 GPIO34 GPIO36
114 14 15
VCORF
44
SER/IR
GND GND GND GND GND GND 1
GMCH_BL_ON
ECSWI#_KBC
KA20GATE KBRCIN#
C KBC_THERMTRIP#
2
1
2
4 3
BAT_SDA BAT_SCL
4 3
1 2 SRN4K7J-8-GP RN46 1 2
BLUETOOTH_EN
3
ECSWI#_KBC
1
ECSCI#
BAS16-1-GP 2
3
ECSCI#_KBC
D12
E51_TxD E51_RxD
1
S5_ENABLE KCOL0
BAS16-1-GP PM_LAN_ENABLE TSATN#_KBC S5_ENABLE
KBC_PWRBTN# R425 LID_CLOSE# R422 LCD_CBL_DET# R409 KB_DET# R406 CAMERA_DET# R401 KBC_THERMTRIP# R404 R407
1
ECSMI#
3
ECSMI#_KBC
R400 KBC_GPIO76 R420
1
2
DY
2
1 1
2
DY
2
1
2
1
2
1
2
1
2
DY
1
100KR2J-1-GP
BIOS_ID
100KR2J-1-GP 100KR2J-1-GP 100KR2J-1-GP 100KR2J-1-GP 10KR2J-3-GP 10KR2J-3-GP
2
DY
KBC_VCORF 2 OF 2
U20B
A00.08/0902 KCOL[0..16]
C204 SC1U10V3KX-3GP
KBC_XI
77
32KX1/32KCLKIN
KBC_XO AMP_MUTE#
79 30
32KX2 GPIO55/CLKOUT
PS_ID_EC PM_PWRBTN# LCD_TST_EN KBC_BEEP BATLOW_LED BRIGHTNESS
63 117 31 32 118 62
GPIO14/TB1 GPIO20/TA2 GPIO56/TA1 GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM
KB_DET# LCD_CBL_DET#
13 12 11 10 71 72
GPIO12/PSDAT3 GPIO25/PSCLK3 GPIO27/PSDAT2 GPIO26/PSCLK2 GPIO35/PSDAT1 GPIO37/PSCLK1
LCD_TST TPDATA TPCLK
PLT_RST#
KBSOUT0/JENK# KBSOUT1/TCK KBSOUT2/TMS KBSOUT3/TDI KBSOUT4/JEN0# KBSOUT5/TDO KBSOUT6/RDY# KBSOUT7 KBSOUT8 KBSOUT9 KBSOUT10 KBSOUT11 KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62 KBSOUT15/GPIO61/XOR_OUT GPIO60/KBSOUT16 GPIO57/KBSOUT17
53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33
KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17
KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7
54 55 56 57 58 59 60 61
KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7
VCC_POR#
85
ECRST#
KBC
CPUCORE_ON
C228 1
C
10KR2J-3-GP
10KR2J-3-GP 1 2 R509 10KR2J-3-GP BIOS_ID: Pull High for Discrete KBC internal Pull Low for UMA
2
SB
C190 SC470P50V2KX-3GP
DY
SRN4K7J-8-GP
EC_SPI_DI EC_SPI_DO EC_SPI_CS# EC_SPI_CLK
EC_SPI_DI EC_SPI_DO EC_SPI_CS# EC_SPI_CLK
1 R192
-1
KBC_XI
2
86 87 90 EC_SPI_CLK_C 92
F_SDI F_SDO F_CS0# F_SCK
B
1
TP122 KROW[0..7]
PS/2
FIU
0R2J-2-GP
SC15P50V2JN-2-GP WPCE773LA0DG-GP ECRST#
2
C240 1
SC15P50V2JN-2-GP
R203 X3_1 1 33KR3-GP
2
KBC_XO
A00.08/0903
R170 0R0402-PAD
Wistron Corporation
1 E
10KR2J-3-GP R173 2 2
1 1
ECRST#_C B Q10 CH3906PT-GP
2
4
3
2
PURE_HW_SHUTDOWN#
DY C453 SC4D7P50V2CN-1GP
A
+3.3V_RTC_LDO
2
R199 20MR3-GP
C
X1 X-32D768KHZ-38GPU
1
2
1
1
R410 0R2J-2-GP
1
2
E51_TxD
R149 4K7R2J-2-GP 1
DY PCLK_KBC_RC
A
2
DY
R148 10KR2J-3-GP
1 2
DY
D13
1
DY
KBC PCLK_KBC CLK EMI 2
+3.3V_RUN
10KR2J-3-GP
RN47 KBC_SCL1 KBC_SDA1
1
ECSWI#
WIFI_RF_EN
WPCE773LA0DG-GP
1 R153 2 0R0402-PAD
-3.09/0803
2
+3.3V_RTC_LDO
SCD1U16V2KX-3GP
BAS16-1-GP 2
TSATN#_KBC
DY
SRN10KJ-5-GP
Q9 CH3904PT-GP
BAT_SDA BAT_SCL
E51_TxD E51_RxD
4 3
C199 2 1
KBC_SDA1 KBC_SCL1
KBC_GPIO76
+3.3V_RUN
RN21
E
H_THRMTRIP#
1 10KR2J-3-GP
0R2J-2-GP
PLT_RST1#_1
1
1
ECSCI#_KBC
2
DY
CAP_SCL
E51_RxD
R156 2
2
0R2J-2-GP
2 0R2J-2-GP
R162 2K2R2J-2-GP
INT_SERIRQ PM_CLKRUN# KBRCIN# KA20GATE
R413 0R0402-PAD
RUNPWROK
DY
R147
LPC_LAD[0..3]
2 R157
GPIO66/G_PWM
DY
1
+1.05V_VCCP
PCLK_KBC LPC_LFRAME#
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
D
R418
2
102
KBC_SDA1
D11
VER0
0 1 0 1 1 0
2
6
GPIO41
124 7 2 3 126 127 128 1 125 8 122 121 29 9 123
68 67 69 70
1
PCB_VER2 PCB_VER1 PCB_VER0
4
SP
3
5
BAT_IN#
GPIO74/SDA2 GPIO73/SCL2 GPIO22/SDA1 GPIO17/SCL1
SMB
MB VERSION ID
MB VER2 VER1 VERSION ID
VDD
D/A
116 89 78 45 18 5
R151 10KR2J-3-GP
1
DY 2
R138 10KR2J-3-GP
1 2
R146 10KR2J-3-GP
1 2
DY
AVCC
LPC
4
2N7002SPT
GPIO10/LPCPD# LRESET# LCLK LFRAME# LAD0 LAD1 LAD2 LAD3 SERIRQ GPIO11/CLKRUN# KBRST# GA20 ECSCI#/GPIO54 GPIO65/SMI# GPIO67/PWUREQ#
A/D
GPI90/AD0 GPI91/AD1 GPI92/AD2 GPI93/AD3 GPIO05 GPIO04
+3.3V_RUN
B
U22
0R2J-2-GP
B
97 98 99 100 108 96
VREF
103
VGATE_PWRGD
2
2 0R2J-2-GP
1
CAMERA_DET#
DY
DY
1
PCB_VER0 PCB_VER1 PCB_VER2
1
KBC_SCL1 1 OF 2
2
KBC_THERMTRIP#
CAP_SDA
C196 DY SC10U6D3V5MX-3GP
AGND
AD_IA CAPA_INT#
115 88 76 46 19
U20A
104
EC_SPI_WP#_R RUNPWROK PWRLED
SSID = KBC 1 R415
R416
THERM_SDA
VCC VCC VCC VCC VCC
1
C460 SCD1U10V2KX-4GP
2
1
C459 SC10U6D3V5MX-3GP
2
1 2
C194 SCD1U10V2KX-4GP
1
+3.3V_RUN
VBAT
C458 SCD1U10V2KX-4GP
1 2
C457 SCD1U10V2KX-4GP
1 2
2
C451 SCD1U10V2KX-4GP
1
C456 SCD1U10V2KX-4GP
1 2
C465 SCD1U10V2KX-4GP
1
C466 SC10U6D3V5MX-3GP
2
D
DY
2
1
2 BLM18AG601SN-3GP
1
1
L17
3
+3.3V_RUN
2
4 CAP close to VCC-GND pin pair
EC132 SCD1U16V2KX-3GP
5
+3.3V_RTC_LDO
C214 SC1U10V3KX-3GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
KBC Winbond WPC773L
Size Document Number Custom
Date: Tuesday, August 11, 2009
Sheet
Rev
-3
Roberts 24
of
59
4
3
+5V_RUN
1
R66 R63 10KR2J-3-GP
1
DY
2
DY
2
0R2J-2-GP
R348 10KR2J-3-GP
2
C389 SCD1U16V2KX-3GP
2
1 2
C386 SC4D7U6D3V5KX-3GP
1
+5V_RUN
+3.3V_RUN
1
SSID = Thermal
2
1
5
D6 EMC2102_FAN_TACH
A
D
EMC2102_FAN_TACH_1
K
EMC2102_FAN_TACH_1 D
RB551V30-GP EMC2102_FAN_DRIVE
EMC2102_FAN_DRIVE
+3.3V_RTC_LDO
RN3 R346
2
3 4
1
DY
2 1
+3.3V_RUN
SRN4K7J-8-GP
49D9R2F-GP
THERM_SCL THERM_SDA +3.3V_RUN
VDD_3V
2
DN1
24
22
25
26
27
23 SMCLK
VDD_5Vb
FANb
FANa
SMDATA
R89 8K2R2J-3-GP
DP1
ALERT#
19
ALERT#
DN2
CLK_IN
18
CLK_32K
EMC2102_DP2
5
DP2
CLK_SEL
17
EMC2102_CLK_SEL
EMC2102_DN3
6
DN3
RESET#
16
EM2102_RESET#
EMC2102_DP3
7
DP3
NC#15
15
2
2
DY
R88 2
1 0R2J-2-GP
1 10KR2J-3-GP
THERM_SCI#
GND = Internal Oscillator Selected +3.3V = External 32.768kHz Clock Selected
C
POWER_OK# 14
THERMTRIP# 13
SYS_SHDN# 12
FAN_MODE
TRIP_SET 11
R85 2 R84 2
EMC2102_SHDN
1 110KR2J-3-GP 10KR2J-3-GP +3.3V_RTC_LDO
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN 2
DY
1
R362 10KR2J-3-GP
EMC2102_FAN_mode
A00.08/0922
G
R71 2 EMC2102_FAN_TACH_1 EMC2102_FAN_DRIVE
S
10KR2J-3-GP
D
PURE_HW_SHUTDOWN#
B
GND = Fan is OFF OPEN = Fan is at 60% full-scale +3.3V = Fan is at 75% full-scale
TRIP_SET Pin Voltage V_DEGREE=(((Degree-75)/21)
V_DEGREE
R78 2K37R2F-GP 2
2
C70 SCD1U16V2KX-3GP
1
1
1 1
R82 10KR2F-2-GP 2
TP223 TP72
1
C78 SCD1U16V2KX-3GP
2
B
Q17 2N7002-7F-GP
1
1
2
10KR2J-3-GP
+3.3V_RUN R347 10KR2J-3-GP
2
R68
3.HW T8 sensor
1
10KR2J-3-GP 1
1
C63 SC470P50V3JN-2GP
DY 1
R87
EMC2102-DZK-GP
R67 2
C63 must be near EMC2102
C
10
C E
C37 SC470P50V3JN-2GP
SHDN_SEL
GND = Channel 1 OPEN = Channel 3 +3.3V = Disabled
Layout notice : Both DN3 and DP3 routing 10 mil trace width and 10 mil spacing.
C37 must be near Q1
NC#8
C61 SC470P50V3JN-2GP
EMC2102
9
2
2
1
1 E
C388 SC470P50V3JN-2GP
2.System Sensor, Put between CPU and NB.
DY
20
4
C61 must be near EMC2102
B
21
GND
3
C388 must be near Q18
Q1 MMBT3904-3-GP
NC#21
EMC2102_DN2
8
C
DY
TACH
2 1
1
1
Layout notice : Both DN2 and DP2 routing 10 mil trace width and 10 mil spacing.
B
+3.3V_RUN
2
H_THERMDA
Q18 MMBT3904-3-GP
VDD_5Va
2
Layout notice : Both H_THERMDA and THERMDC routing 10 mil trace width and 10 mil spacing.
H_THERMDC C50 SC470P50V3JN-2GP
GND
U8
C60 SCD1U16V2KX-3GP
1.For CPU Sensor
29
EMC2102_VDD_3D3
1
1
49D9R2F-GP
28
R340 2
T8 shutdown is set 88 deg-C.
32K suspend clock output +3.3V_ALW U10 R219
G
S
Q13 2N7002-7F-GP
1
CLK_32K
2
10R2J-2-GP
PM_SLP_S3#
DY 2
A
CLK_32K_R
1
B
2
A
1
D
ICH_SUSCLK
EM2102_RESET#
3
C249 SC4D7P50V2CN-1GP
C82 VCC
5
Y
4
DY
DY 1
2
SCD1U16V2KX-3GP
PM_PWROK
GND
A
74LVC1G08GW-1-GP
RUN_POWER_ON
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Thermal/Fan Controllor EMC2102 Rev
Size Document Number Custom
Date: Tuesday, August 11, 2009 5
4
3
2
-3
Roberts Sheet 1
25
of
59
5
4
3
2
1
SSID = Charger 1
MAX8731_LDO
+3.3V_RTC_LDO 1
Id=-8A Qg=17~24nC Rdson=15~20mohm
R72 100KR2J-1-GP
Layout Trace 300mil 1
2
100KR2J-1-GP
D
MAX8731_LX 1 1R3F-GP2 1 2 C42 SC220P50V2KX-3GP MAX8731_DLO
DLO
20
PGND
19
CSIP
18
MAX8731_CSIP
CSIN
17
MAX8731_CSIN
FBSB
16
FBSA
15
SCD1U25V3KX-GP 2
1
1
2
1
MAX8731_LX1
1
R306 2
1
2
D01R2512F-4-GP
IND-5D8UH-GP
CCV CCI CCS REF DAC GND
2
G50 GAP-CLOSE-PWR-3-GP
2
DY
1
GND
1
R335 BAT_SENSE
MAX8731AETI-GP
2
29
1
C59 SCD1U16V2KX-3GP
2
C51 SC1U10V3KX-3GP
1 2
C55 SCD01U50V2KX-1GP
1 2
1
C57 SCD01U50V2KX-1GP
2
1MAX8731_CCV1 2
C58 SCD01U50V2KX-1GP
1 2
C62 SCD1U16V2KX-3GP
1 2
6 2 10KR2F-2-GP MAX8731_CCV MAX8731_CCI 5 MAX8731_CCS 4 MAX8731_REF 3 MAX8731_DAC 7 12
1
1
2
A00.08/0909 R61
G51 GAP-CLOSE-PWR-3-GP
INP
1
8
AD_IA
U44 SI4800BDY-T1
4 3 2 1
CHG_AGND
R65 10KR2F-2-GP
2
Layout Trace 300mil
D D D D BATSEL
B
CHG_PWR
L9
1
23
SDA
1
G S S S
14
A
EC79 SCD1U50V3KX-GP
1 2
1 1 C34
1
9
+PBATT
MAX8731_DHI R44
LX BAT_SDA
BAT_SDA
C40 SCD1U25V3KX-GP
24
2
DHI
C323 SC10U25V6KX-1GP
SCL
2
BAT_SCL
BAT_SCL
SC1U10V3KX-3GP
C329 SC10U25V0KX-3GP
10
CHG_AGND
CHG_AGND
2
DY
1
ACOK
C48 1
U45 SI4800BDY-T1
2
13
R45 D5 0R3J-0-U-GP MAX8731_BST 1 2MAX8731_BST1 K A MAX8731_LDO BAS516-1-GP
CHG_AGND
C371 SC10U25V0KX-3GP
25 21
MAX8731_VCC
C331 SC10U25V0KX-3GP
C64 SCD1U25V3KX-GP ACAV_IN
5 6 7 8
BST LDO
D D D D 27 26
1
VDD
G S S S
11
CSSP CSSN VCC
R49 33R2J-2-GP
4 3 2 1
ACIN
C38 SC1U10V3KX-3GP
2
2
28
CHG_AGND
2
DCIN
MAX8731_ACIN
1
1
22
C41 SCD1U25V3KX-GP
5 6 7 8
B
MAX8731_DCIN
+3.3V_RTC_LDO
2
1 2
2
R48 49K9R2F-L-GP
C46 SCD01U50V2KX-1GP
1
2
2
U7
2
1
CHG_AGNDCHG_AGND
C39 SC1U25V5KX-1GP
ASNS
1
2
MAX8731_CSSN
MAX8731_CSSP
S
SCD1U25V3KX-GP
A00.08/0903 0R0402-PAD
C
1
C47
G
2
S
ACAV_IN
8 7 6 5
R295 470KR2J-2-GP
1
49K9R2F-L-GP Q3 2N7002-7F-GP
2
1
D D D D
2
R62 DCIN_GATE2
2
U37 S S S G AO4407A-GP
G56 GAP-CLOSE-PWR-3-GP
2 D
1
G
R52 365KR3F-GP
G57 GAP-CLOSE-PWR-3-GP
R64 DCIN_GATE1
1 2 3 4
+DC_IN_SS
1
1
DC_IN_D
Q2 2N7002-7F-GP
R46
+PBATT
2
D01R2512F-4-GP
R59 10KR2J-3-GP
C
1
1
+PWR_SRC R338
AO4407A-GP
ACAV_IN
2N7002-7F-GP
+DC_IN_SS
Layout Trace 300mil
+SDC_IN
1 2 3 4
2
S S S G
C369 SC10U25V0KX-3GP
2
U47 D D D D
1
2
8 7 6 5
Q4
S
Adaptor In Soft-Start Circuit
+DC_IN_SS
G
D
Layout Trace 250mil
D
1 2
C67 SC1U10V3KX-3GP
AC_IN#
EC80 SCD1U50V3KX-GP
2
2
R341 15K4R2F-GP
2
1
1
EC77 SCD1U50V3KX-GP
2
ACAV_IN
D
EC76 SCD1U50V3KX-GP
+PBATT
R339 10KR2F-2-GP
1
2
BATT_SENSE
BATT_SENSE
100R2F-L1-GP-U C372 SCD01U50V2KX-1GP A
1
2
G11 GAP-CLOSE-PWR
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
CHG_AGND Title
CHARGER MAX8731
Size Document Number Custom
Date: Tuesday, August 11, 2009 5
4
3
2
Rev
-3
Roberts Sheet 1
26
of
59
A
B
C
D
+PWR_SRC
SSID = PWR.Plane.Regulator_3p3v5v
E
PWR_SRC_17020 G17
2
1
GAP-CLOSE-PWR G23 2 1 +PWR_SRC
GAP-CLOSE-PWR G63 2 1
PWR_SRC_17020
No Install for ISL6236 Install 10 ohm for MAX8778
G19
1
2
GAP-CLOSE-PWR G70 2 1
GAP-CLOSE-PWR G72 1 2 4
GAP-CLOSE-PWR G68 2 1
GAP-CLOSE-PWR G33 1 2
+5V_ALW2
1 1
GAP-CLOSE-PWR G21 1 2
GAP-CLOSE-PWR G66 2 1
2
10R3F-GP GAP-CLOSE-PWR G64 2 1
2
C177 SC4D7U6D3V5KX-3GP
0.1uF for ISL6236, Install with 1uF for Max8778
GAP-CLOSE-PWR G36 1 2
4
+5V_VCC1 R393
PWR_SRC_17020
GAP-CLOSE-PWR +3.3V_RTC
1
+2.0V_REF_3V5VREG +5V_VCC1
1
2
1
C402 SC2200P50V2KX-2GP
2
1 2
C86 SCD1U50V3KX-GP
1 2
C401 SC10U25V6KX-1GP
5 6 7 8
2
1
2
1
3V_ALW +/- 5% Design Current: 5.4A Peak current 7.8A 8.58